From: Gabor Juhos Date: Fri, 14 Nov 2008 08:57:31 +0000 (+0000) Subject: define some bits of the ethernet controller's registers X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=f0a9ec964bf35a6763bf2d7f013a529d9d1f693c;p=openwrt%2Fstaging%2Fneocturne.git define some bits of the ethernet controller's registers SVN-Revision: 13201 --- diff --git a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h index 5cd7dc2c5c..3e15e33e0d 100644 --- a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h +++ b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h @@ -213,6 +213,54 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc) #define MAC_CFG2_IF_1000 BIT(9) #define MAC_CFG2_IF_10_100 BIT(8) +#define FIFO_CFG0_WTM BIT(0) /* Watermark Module */ +#define FIFO_CFG0_RXS BIT(1) /* Rx System Module */ +#define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */ +#define FIFO_CFG0_TXS BIT(3) /* Tx System Module */ +#define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */ +#define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \ + | FIFO_CFG0_TXS | FIFO_CFG0_TXF) + +#define FIFO_CFG0_ENABLE_SHIFT 8 + +#define FIFO_CFG4_DE BIT(0) /* Drop Event */ +#define FIFO_CFG4_DV BIT(1) /* RX_DV Event */ +#define FIFO_CFG4_FC BIT(2) /* False Carrier */ +#define FIFO_CFG4_CE BIT(3) /* Code Error */ +#define FIFO_CFG4_CRC BIT(4) /* CRC error */ +#define FIFO_CFG4_LM BIT(5) /* Length Mismatch */ +#define FIFO_CFG4_LO BIT(6) /* Length out of range */ +#define FIFO_CFG4_OK BIT(7) /* Packet is OK */ +#define FIFO_CFG4_MC BIT(8) /* Multicast Packet */ +#define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */ +#define FIFO_CFG4_DR BIT(10) /* Dribble */ +#define FIFO_CFG4_LE BIT(11) /* Long Event */ +#define FIFO_CFG4_CF BIT(12) /* Control Frame */ +#define FIFO_CFG4_PF BIT(13) /* Pause Frame */ +#define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */ +#define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */ +#define FIFO_CFG4_FT BIT(16) /* Frame Truncated */ +#define FIFO_CFG4_UC BIT(17) /* Unicast Packet */ + +#define FIFO_CFG5_DE BIT(0) /* Drop Event */ +#define FIFO_CFG5_DV BIT(1) /* RX_DV Event */ +#define FIFO_CFG5_FC BIT(2) /* False Carrier */ +#define FIFO_CFG5_CE BIT(3) /* Code Error */ +#define FIFO_CFG5_LM BIT(4) /* Length Mismatch */ +#define FIFO_CFG5_LO BIT(5) /* Length Out of Range */ +#define FIFO_CFG5_OK BIT(6) /* Packet is OK */ +#define FIFO_CFG5_MC BIT(7) /* Multicast Packet */ +#define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */ +#define FIFO_CFG5_DR BIT(9) /* Dribble */ +#define FIFO_CFG5_CF BIT(10) /* Control Frame */ +#define FIFO_CFG5_PF BIT(11) /* Pause Frame */ +#define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */ +#define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */ +#define FIFO_CFG5_LE BIT(14) /* Long Event */ +#define FIFO_CFG5_FT BIT(15) /* Frame Truncated */ +#define FIFO_CFG5_SF BIT(18) /* Short Frame */ +#define FIFO_CFG5_BM BIT(19) /* Byte Mode */ + #define AG71XX_INT_TX_PS BIT(0) #define AG71XX_INT_TX_UR BIT(1) #define AG71XX_INT_TX_BE BIT(3) @@ -233,7 +281,7 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc) #define MII_CMD_WRITE 0x0 #define MII_CMD_READ 0x1 -#define MII_ADDR_S 8 +#define MII_ADDR_SHIFT 8 #define MII_IND_BUSY BIT(0) #define MII_IND_INVALID BIT(2) @@ -249,8 +297,6 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc) #define RX_STATUS_OF BIT(1) #define RX_STATUS_BE BIT(3) -#define FIFO_CFG5_BYTE_PER_CLK BIT(19) - #define MII_CTRL_IF_MASK 3 #define MII_CTRL_SPEED_SHIFT 4 #define MII_CTRL_SPEED_MASK 3 diff --git a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_main.c b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_main.c index 973946cf5d..53376fa817 100644 --- a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_main.c +++ b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_main.c @@ -268,6 +268,8 @@ static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac) #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | MAC_CFG1_SRX \ | MAC_CFG1_STX) +#define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT) + static void ag71xx_hw_init(struct ag71xx *ag) { struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); @@ -287,7 +289,7 @@ static void ag71xx_hw_init(struct ag71xx *ag) ag71xx_sb(ag, AG71XX_REG_MAC_CFG2, MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK); - ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, 0x00001f00); + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT); ag71xx_mii_ctrl_set_if(ag, pdata->mii_if); diff --git a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_mdio.c b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_mdio.c index fb53d9d76d..2cd1ea3224 100644 --- a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_mdio.c +++ b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_mdio.c @@ -50,7 +50,7 @@ static int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg) ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_WRITE); ag71xx_mdio_wr(am, AG71XX_REG_MII_ADDR, - ((addr & 0xff) << MII_ADDR_S) | (reg & 0xff)); + ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff)); ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_READ); i = AG71XX_MDIO_RETRY; @@ -81,7 +81,7 @@ static void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, DBG("mii_write: addr=%04x, reg=%04x, value=%04x\n", addr, reg, val); ag71xx_mdio_wr(am, AG71XX_REG_MII_ADDR, - ((addr & 0xff) << MII_ADDR_S) | (reg & 0xff)); + ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff)); ag71xx_mdio_wr(am, AG71XX_REG_MII_CTRL, val); i = AG71XX_MDIO_RETRY; diff --git a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c index e44bea4f1e..7242868462 100644 --- a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c +++ b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c @@ -100,14 +100,14 @@ static void ag71xx_phy_link_update(struct ag71xx *ag) ifctl &= ~(MAC_IFCTL_SPEED); fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5); - fifo5 &= ~FIFO_CFG5_BYTE_PER_CLK; + fifo5 &= ~FIFO_CFG5_BM; switch (ag->speed) { case SPEED_1000: mii_speed = MII_CTRL_SPEED_1000; cfg2 |= MAC_CFG2_IF_1000; pll = PLL_VAL_1000; - fifo5 |= FIFO_CFG5_BYTE_PER_CLK; + fifo5 |= FIFO_CFG5_BM; break; case SPEED_100: mii_speed = MII_CTRL_SPEED_100;