From: John Crispin Date: Thu, 16 Jul 2020 07:18:28 +0000 (+0200) Subject: mediatek: backport latest pci/e driver from upstream X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=eff87b8f9350ee49c572b1b048f1361e8ff23fef;p=openwrt%2Fstaging%2Fthess.git mediatek: backport latest pci/e driver from upstream Signed-off-by: John Crispin --- diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-rootdisk.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-rootdisk.dts index 6a14ef369b..1638867604 100644 --- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-rootdisk.dts +++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-rootdisk.dts @@ -257,18 +257,16 @@ }; }; -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>; - status = "okay"; - - pcie@0,0 { - status = "okay"; - }; +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; + status = "okay"; +}; - pcie@1,0 { - status = "okay"; - }; +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; + status = "okay"; }; &pio { diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-elecom-wrc-2533gent.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-elecom-wrc-2533gent.dts index 224214e083..d905edc94f 100644 --- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-elecom-wrc-2533gent.dts +++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-elecom-wrc-2533gent.dts @@ -165,19 +165,14 @@ }; }; -&pcie { - pinctrl-names = "default", "pcie1_pins"; - pinctrl-0 = <&pcie0_pins>; - pinctrl-1 = <&pcie1_pins>; - status = "okay"; - - pcie@0,0 { - status = "okay"; - mt7615@0,0 { - reg = <0x0000 0 0 0 0>; - mediatek,mtd-eeprom = <&factory 0x05000>; - }; - }; +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; + status = "okay"; + mt7615@0,0 { + reg = <0x0000 0 0 0 0>; + mediatek,mtd-eeprom = <&factory 0x05000>; + }; }; &pio { diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-rfb1-ubi.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-rfb1-ubi.dts new file mode 100644 index 0000000000..f64a882370 --- /dev/null +++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-rfb1-ubi.dts @@ -0,0 +1,646 @@ +/* + * Copyright (c) 2018 MediaTek Inc. + * Author: Ryder Lee + * + * SPDX-License-Identifier: (GPL-2.0 OR MIT) + */ + +/dts-v1/; +#include +#include + +#include "mt7622.dtsi" +#include "mt6380.dtsi" + +/ { + model = "MT7622_MT7531 RFB"; + compatible = "mediatek,mt7622,ubi"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512"; + }; + + cpus { + cpu@0 { + proc-supply = <&mt6380_vcpu_reg>; + sram-supply = <&mt6380_vm_reg>; + }; + + cpu@1 { + proc-supply = <&mt6380_vcpu_reg>; + sram-supply = <&mt6380_vm_reg>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + factory { + label = "factory"; + linux,code = ; + gpios = <&pio 0 GPIO_ACTIVE_HIGH>; + }; + + wps { + label = "wps"; + linux,code = ; + gpios = <&pio 102 GPIO_ACTIVE_HIGH>; + }; + }; + + gsw: gsw@0 { + compatible = "mediatek,mt753x"; + mediatek,ethsys = <ðsys>; + #address-cells = <1>; + #size-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + + green { + label = "bpi-r64:pio:green"; + gpios = <&pio 89 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + red { + label = "bpi-r64:pio:red"; + gpios = <&pio 88 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + memory { + reg = <0 0x40000000 0 0x40000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&bch { + status = "okay"; +}; + +&btif { + status = "okay"; +}; + +&cir { + pinctrl-names = "default"; + pinctrl-0 = <&irrx_pins>; + status = "okay"; +}; + +ð { + status = "okay"; + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&gsw { + mediatek,mdio = <&mdio>; + mediatek,portmap = "llllw"; + mediatek,mdio_master_pinmux = <0>; + reset-gpios = <&pio 54 0>; + interrupt-parent = <&pio>; + interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; + + port5: port@5 { + compatible = "mediatek,mt753x-port"; + reg = <5>; + phy-mode = "rgmii"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port6: port@6 { + compatible = "mediatek,mt753x-port"; + reg = <6>; + phy-mode = "sgmii"; + fixed-link { + speed = <2500>; + full-duplex; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&emmc_pins_default>; + pinctrl-1 = <&emmc_pins_uhs>; + status = "okay"; + bus-width = <8>; + max-frequency = <50000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; + non-removable; +}; + +&mmc1 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&sd0_pins_default>; + pinctrl-1 = <&sd0_pins_uhs>; + status = "okay"; + bus-width = <4>; + max-frequency = <50000000>; + cap-sd-highspeed; + r_smpl = <1>; + cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; +}; + +&nandc { + pinctrl-names = "default"; + pinctrl-0 = <¶llel_nand_pins>; + status = "disabled"; +}; + +&nor_flash { + pinctrl-names = "default"; + pinctrl-0 = <&spi_nor_pins>; + status = "disabled"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + }; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; + status = "okay"; +}; + +&pio { + /* Attention: GPIO 90 is used to switch between PCIe@1,0 and + * SATA functions. i.e. output-high: PCIe, output-low: SATA + */ + asm_sel { + gpio-hog; + gpios = <90 GPIO_ACTIVE_HIGH>; + output-high; + }; + + /* eMMC is shared pin with parallel NAND */ + emmc_pins_default: emmc-pins-default { + mux { + function = "emmc", "emmc_rst"; + groups = "emmc"; + }; + + /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7", + * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4, + * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively + */ + conf-cmd-dat { + pins = "NDL0", "NDL1", "NDL2", + "NDL3", "NDL4", "NDL5", + "NDL6", "NDL7", "NRB"; + input-enable; + bias-pull-up; + }; + + conf-clk { + pins = "NCLE"; + bias-pull-down; + }; + }; + + emmc_pins_uhs: emmc-pins-uhs { + mux { + function = "emmc"; + groups = "emmc"; + }; + + conf-cmd-dat { + pins = "NDL0", "NDL1", "NDL2", + "NDL3", "NDL4", "NDL5", + "NDL6", "NDL7", "NRB"; + input-enable; + drive-strength = <4>; + bias-pull-up; + }; + + conf-clk { + pins = "NCLE"; + drive-strength = <4>; + bias-pull-down; + }; + }; + + eth_pins: eth-pins { + mux { + function = "eth"; + groups = "mdc_mdio", "rgmii_via_gmac2"; + }; + }; + + i2c1_pins: i2c1-pins { + mux { + function = "i2c"; + groups = "i2c1_0"; + }; + }; + + i2c2_pins: i2c2-pins { + mux { + function = "i2c"; + groups = "i2c2_0"; + }; + }; + + i2s1_pins: i2s1-pins { + mux { + function = "i2s"; + groups = "i2s_out_mclk_bclk_ws", + "i2s1_in_data", + "i2s1_out_data"; + }; + + conf { + pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK", + "I2S_WS", "I2S_MCLK"; + drive-strength = <12>; + bias-pull-down; + }; + }; + + irrx_pins: irrx-pins { + mux { + function = "ir"; + groups = "ir_1_rx"; + }; + }; + + irtx_pins: irtx-pins { + mux { + function = "ir"; + groups = "ir_1_tx"; + }; + }; + + /* Parallel nand is shared pin with eMMC */ + parallel_nand_pins: parallel-nand-pins { + mux { + function = "flash"; + groups = "par_nand"; + }; + }; + + pcie0_pins: pcie0-pins { + mux { + function = "pcie"; + groups = "pcie0_pad_perst", + "pcie0_1_waken", + "pcie0_1_clkreq"; + }; + }; + + pcie1_pins: pcie1-pins { + mux { + function = "pcie"; + groups = "pcie1_pad_perst", + "pcie1_0_waken", + "pcie1_0_clkreq"; + }; + }; + + pmic_bus_pins: pmic-bus-pins { + mux { + function = "pmic"; + groups = "pmic_bus"; + }; + }; + + pwm7_pins: pwm1-2-pins { + mux { + function = "pwm"; + groups = "pwm_ch7_2"; + }; + }; + + wled_pins: wled-pins { + mux { + function = "led"; + groups = "wled"; + }; + }; + + sd0_pins_default: sd0-pins-default { + mux { + function = "sd"; + groups = "sd_0"; + }; + + /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN", + * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1, + * DAT2, DAT3, CMD, CLK for SD respectively. + */ + conf-cmd-data { + pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", + "I2S2_IN","I2S4_OUT"; + input-enable; + drive-strength = <8>; + bias-pull-up; + }; + conf-clk { + pins = "I2S3_OUT"; + drive-strength = <12>; + bias-pull-down; + }; + conf-cd { + pins = "TXD3"; + bias-pull-up; + }; + }; + + sd0_pins_uhs: sd0-pins-uhs { + mux { + function = "sd"; + groups = "sd_0"; + }; + + conf-cmd-data { + pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", + "I2S2_IN","I2S4_OUT"; + input-enable; + bias-pull-up; + }; + + conf-clk { + pins = "I2S3_OUT"; + bias-pull-down; + }; + }; + + /* Serial NAND is shared pin with SPI-NOR */ + serial_nand_pins: serial-nand-pins { + mux { + function = "flash"; + groups = "snfi"; + }; + }; + + spic0_pins: spic0-pins { + mux { + function = "spi"; + groups = "spic0_0"; + }; + }; + + spic1_pins: spic1-pins { + mux { + function = "spi"; + groups = "spic1_0"; + }; + }; + + /* SPI-NOR is shared pin with serial NAND */ + spi_nor_pins: spi-nor-pins { + mux { + function = "flash"; + groups = "spi_nor"; + }; + }; + + /* serial NAND is shared pin with SPI-NOR */ + serial_nand_pins: serial-nand-pins { + mux { + function = "flash"; + groups = "snfi"; + }; + }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0_0_tx_rx" ; + }; + }; + + uart2_pins: uart2-pins { + mux { + function = "uart"; + groups = "uart2_1_tx_rx" ; + }; + }; + + watchdog_pins: watchdog-pins { + mux { + function = "watchdog"; + groups = "watchdog"; + }; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm7_pins>; + status = "okay"; +}; + +&pwrap { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_bus_pins>; + + status = "okay"; +}; + +&sata { + status = "disable"; +}; + +&sata_phy { + status = "disable"; +}; + +&snfi { + pinctrl-names = "default"; + pinctrl-0 = <&serial_nand_pins>; + status = "okay"; + + spi_nand@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + spi-max-frequency = <104000000>; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Preloader"; + reg = <0x00000 0x0080000>; + read-only; + }; + + partition@80000 { + label = "ATF"; + reg = <0x80000 0x0040000>; + }; + + partition@c0000 { + label = "Bootloader"; + reg = <0xc0000 0x0080000>; + }; + + partition@140000 { + label = "Config"; + reg = <0x140000 0x0080000>; + }; + + factory: partition@1c0000 { + label = "Factory"; + reg = <0x1c0000 0x0040000>; + }; + + partition@200000 { + label = "kernel"; + reg = <0x200000 0x400000>; + }; + + partition@600000 { + label = "ubi"; + reg = <0x600000 0x1C00000>; + }; + + partition@2200000 { + label = "User_data"; + reg = <0x2200000 0x4000000>; + }; + }; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spic0_pins>; + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spic1_pins>; + status = "okay"; +}; + +&ssusb { + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + status = "okay"; +}; + +&u3phy { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + +&watchdog { + pinctrl-names = "default"; + pinctrl-0 = <&watchdog_pins>; + status = "okay"; +}; + +&wmac { + mediatek,mtd-eeprom = <&factory 0x0000>; + status = "okay"; +}; diff --git a/target/linux/mediatek/patches-5.4/0991-dt-bindings-PCI-Mediatek-Update-PCIe-binding.patch b/target/linux/mediatek/patches-5.4/0991-dt-bindings-PCI-Mediatek-Update-PCIe-binding.patch new file mode 100755 index 0000000000..2c7e311836 --- /dev/null +++ b/target/linux/mediatek/patches-5.4/0991-dt-bindings-PCI-Mediatek-Update-PCIe-binding.patch @@ -0,0 +1,420 @@ +From patchwork Thu May 28 06:16:45 2020 +Content-Type: text/plain; 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Wed, 27 May 2020 22:20:16 -0800 +Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by + MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id + 15.0.1497.2; Wed, 27 May 2020 23:18:52 -0700 +Received: from mtkcas07.mediatek.inc (172.21.101.84) by + mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id + 15.0.1497.2; Thu, 28 May 2020 14:18:49 +0800 +Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc + (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend + Transport; Thu, 28 May 2020 14:18:47 +0800 +From: +To: , , +Subject: [PATCH v2 1/4] dt-bindings: PCI: Mediatek: Update PCIe binding +Date: Thu, 28 May 2020 14:16:45 +0800 +Message-ID: <20200528061648.32078-2-chuanjia.liu@mediatek.com> +X-Mailer: git-send-email 2.18.0 +In-Reply-To: <20200528061648.32078-1-chuanjia.liu@mediatek.com> +References: <20200528061648.32078-1-chuanjia.liu@mediatek.com> +MIME-Version: 1.0 +X-MTK: N +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20200527_231958_261064_608CC03E +X-CRM114-Status: GOOD ( 13.95 ) +X-Spam-Score: -0.2 (/) +X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: + Content analysis details: (-0.2 points) + pts rule name description + ---- ---------------------- + -------------------------------------------------- + -0.0 SPF_PASS SPF: sender matches SPF record + 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record + 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 + encoding + -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from + author's domain + 0.1 DKIM_SIGNED Message has a DKIM or DK signature, + not necessarily + valid + -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature + -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from + envelope-from domain + 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay + lines +X-BeenThere: linux-mediatek@lists.infradead.org +X-Mailman-Version: 2.1.29 +Precedence: list +List-Id: +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Cc: devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com, + srv_heupstream@mediatek.com, "chuanjia.liu" , + linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, + jianjun.wang@mediatek.com, linux-mediatek@lists.infradead.org, + yong.wu@mediatek.com, bhelgaas@google.com, + linux-arm-kernel@lists.infradead.org, amurray@thegoodpenguin.co.uk +Sender: "Linux-mediatek" +Errors-To: + linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org + +From: "chuanjia.liu" + +There are two independent PCIe controllers in MT2712/MT7622 platform, +and each of them should contain an independent MSI domain. + +In current architecture, MSI domain will be inherited from the root +bridge, and all of the devices will share the same MSI domain. +Hence that, the PCIe devices will not work properly if the irq number +which required is more than 32. + +Split the PCIe node for MT2712/MT7622 platform to fix MSI issue and +comply with the hardware design. + +Signed-off-by: chuanjia.liu +--- + .../bindings/pci/mediatek-pcie-cfg.yaml | 38 +++++ + .../devicetree/bindings/pci/mediatek-pcie.txt | 144 +++++++++++------- + 2 files changed, 129 insertions(+), 53 deletions(-) + create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml + +diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml +new file mode 100644 +index 000000000000..4d2835ab4858 +--- /dev/null ++++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml +@@ -0,0 +1,38 @@ ++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/pci/mediatek-pcie-cfg.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Mediatek PCIECFG controller ++ ++maintainers: ++ - Chuanjia Liu ++ - Jianjun Wang ++ ++description: | ++ The MediaTek PCIECFG controller controls some feature about ++ LTSSM, ASPM and so on. ++ ++properties: ++ compatible: ++ items: ++ - enum: ++ - mediatek,mt7622-pciecfg ++ - mediatek,mt7629-pciecfg ++ - const: syscon ++ ++ reg: ++ maxItems: 1 ++ ++required: ++ - compatible ++ - reg ++ ++examples: ++ - | ++ pciecfg: pciecfg@1a140000 { ++ compatible = "mediatek,mt7622-pciecfg", "syscon"; ++ reg = <0 0x1a140000 0 0x1000>; ++ }; ++... +diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt +index 7468d666763a..ddae110d4379 100644 +--- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt ++++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt +@@ -8,7 +8,7 @@ Required properties: + "mediatek,mt7623-pcie" + "mediatek,mt7629-pcie" + - device_type: Must be "pci" +-- reg: Base addresses and lengths of the PCIe subsys and root ports. ++- reg: Base addresses and lengths of the root ports. + - reg-names: Names of the above areas to use during resource lookup. + - #address-cells: Address representation for root ports (must be 3) + - #size-cells: Size representation for root ports (must be 2) +@@ -19,10 +19,10 @@ Required properties: + - sys_ckN :transaction layer and data link layer clock + Required entries for MT2701/MT7623: + - free_ck :for reference clock of PCIe subsys +- Required entries for MT2712/MT7622: ++ Required entries for MT2712/MT7622/MT7629: + - ahb_ckN :AHB slave interface operating clock for CSR access and RC + initiated MMIO access +- Required entries for MT7622: ++ Required entries for MT7622/MT7629: + - axi_ckN :application layer MMIO channel operating clock + - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when + pcie_mac_ck/pcie_pipe_ck is turned off +@@ -47,10 +47,13 @@ Required properties for MT7623/MT2701: + - reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the + number of root ports. + +-Required properties for MT2712/MT7622: ++Required properties for MT2712/MT7622/MT7629: + -interrupts: A list of interrupt outputs of the controller, must have one + entry for each PCIe port + ++Required properties for MT7622/MT7629: ++- mediatek,pcie-subsys: Should be a phandle of the pciecfg node. ++ + In addition, the device tree node must have sub-nodes describing each + PCIe port interface, having the following mandatory properties: + +@@ -143,56 +146,73 @@ Examples for MT7623: + + Examples for MT2712: + +- pcie: pcie@11700000 { ++ pcie1: pcie@112ff000 { + compatible = "mediatek,mt2712-pcie"; + device_type = "pci"; +- reg = <0 0x11700000 0 0x1000>, +- <0 0x112ff000 0 0x1000>; +- reg-names = "port0", "port1"; ++ reg = <0 0x112ff000 0 0x1000>; ++ reg-names = "port1"; + #address-cells = <3>; + #size-cells = <2>; +- interrupts = , +- ; +- clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, +- <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, +- <&pericfg CLK_PERI_PCIE0>, ++ interrupts = ; ++ interrupt-names = "pcie_irq"; ++ clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, + <&pericfg CLK_PERI_PCIE1>; +- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1"; +- phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>; +- phy-names = "pcie-phy0", "pcie-phy1"; ++ clock-names = "sys_ck1", "ahb_ck1"; ++ phys = <&u3port1 PHY_TYPE_PCIE>; ++ phy-names = "pcie-phy1"; + bus-range = <0x00 0xff>; +- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; ++ ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>; ++ status = "disabled"; + +- pcie0: pcie@0,0 { +- reg = <0x0000 0 0 0 0>; ++ slot1: pcie@1,0 { ++ reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0 0 0 1 &pcie_intc0 0>, +- <0 0 0 2 &pcie_intc0 1>, +- <0 0 0 3 &pcie_intc0 2>, +- <0 0 0 4 &pcie_intc0 3>; +- pcie_intc0: interrupt-controller { ++ interrupt-map = <0 0 0 1 &pcie_intc1 0>, ++ <0 0 0 2 &pcie_intc1 1>, ++ <0 0 0 3 &pcie_intc1 2>, ++ <0 0 0 4 &pcie_intc1 3>; ++ pcie_intc1: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; ++ }; + +- pcie1: pcie@1,0 { +- reg = <0x0800 0 0 0 0>; ++ pcie0: pcie@11700000 { ++ compatible = "mediatek,mt2712-pcie"; ++ device_type = "pci"; ++ reg = <0 0x11700000 0 0x1000>; ++ reg-names = "port0"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ interrupts = ; ++ interrupt-names = "pcie_irq"; ++ clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, ++ <&pericfg CLK_PERI_PCIE0>; ++ clock-names = "sys_ck0", "ahb_ck0"; ++ phys = <&u3port0 PHY_TYPE_PCIE>; ++ phy-names = "pcie-phy0"; ++ bus-range = <0x00 0xff>; ++ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; ++ status = "disabled"; ++ ++ slot0: pcie@0,0 { ++ reg = <0x0000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0 0 0 1 &pcie_intc1 0>, +- <0 0 0 2 &pcie_intc1 1>, +- <0 0 0 3 &pcie_intc1 2>, +- <0 0 0 4 &pcie_intc1 3>; +- pcie_intc1: interrupt-controller { ++ interrupt-map = <0 0 0 1 &pcie_intc0 0>, ++ <0 0 0 2 &pcie_intc0 1>, ++ <0 0 0 3 &pcie_intc0 2>, ++ <0 0 0 4 &pcie_intc0 3>; ++ pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; +@@ -202,39 +222,31 @@ Examples for MT2712: + + Examples for MT7622: + +- pcie: pcie@1a140000 { ++ pcie0: pcie@1a143000 { + compatible = "mediatek,mt7622-pcie"; + device_type = "pci"; +- reg = <0 0x1a140000 0 0x1000>, +- <0 0x1a143000 0 0x1000>, +- <0 0x1a145000 0 0x1000>; +- reg-names = "subsys", "port0", "port1"; ++ reg = <0 0x1a143000 0 0x1000>; ++ reg-names = "port0"; ++ mediatek,pcie-cfg = <&pciecfg>; + #address-cells = <3>; + #size-cells = <2>; +- interrupts = , +- ; ++ interrupts = ; ++ interrupt-names = "pcie_irq"; + clocks = <&pciesys CLK_PCIE_P0_MAC_EN>, +- <&pciesys CLK_PCIE_P1_MAC_EN>, + <&pciesys CLK_PCIE_P0_AHB_EN>, +- <&pciesys CLK_PCIE_P1_AHB_EN>, + <&pciesys CLK_PCIE_P0_AUX_EN>, +- <&pciesys CLK_PCIE_P1_AUX_EN>, + <&pciesys CLK_PCIE_P0_AXI_EN>, +- <&pciesys CLK_PCIE_P1_AXI_EN>, + <&pciesys CLK_PCIE_P0_OBFF_EN>, +- <&pciesys CLK_PCIE_P1_OBFF_EN>, +- <&pciesys CLK_PCIE_P0_PIPE_EN>, +- <&pciesys CLK_PCIE_P1_PIPE_EN>; +- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1", +- "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1", +- "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1"; +- phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>; +- phy-names = "pcie-phy0", "pcie-phy1"; ++ <&pciesys CLK_PCIE_P0_PIPE_EN>; ++ clock-names = "sys_ck0", "ahb_ck0", "aux_ck0", ++ "axi_ck0", "obff_ck0", "pipe_ck0"; ++ + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; + bus-range = <0x00 0xff>; +- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; ++ ranges = <0x82000000 0 0x20000000 0 0x20000000 0 0x8000000>; ++ status = "disabled"; + +- pcie0: pcie@0,0 { ++ slot0: pcie@0,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; +@@ -251,8 +263,34 @@ Examples for MT7622: + #interrupt-cells = <1>; + }; + }; ++ }; ++ ++ pcie1: pcie@1a145000 { ++ compatible = "mediatek,mt7622-pcie"; ++ device_type = "pci"; ++ reg = <0 0x1a145000 0 0x1000>; ++ reg-names = "port1"; ++ mediatek,pcie-cfg = <&pciecfg>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ interrupts = ; ++ interrupt-names = "pcie_irq"; ++ clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, ++ /* designer has connect RC1 with p0_ahb clock */ ++ <&pciesys CLK_PCIE_P0_AHB_EN>, ++ <&pciesys CLK_PCIE_P1_AUX_EN>, ++ <&pciesys CLK_PCIE_P1_AXI_EN>, ++ <&pciesys CLK_PCIE_P1_OBFF_EN>, ++ <&pciesys CLK_PCIE_P1_PIPE_EN>; ++ clock-names = "sys_ck1", "ahb_ck1", "aux_ck1", ++ "axi_ck1", "obff_ck1", "pipe_ck1"; ++ ++ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; ++ bus-range = <0x00 0xff>; ++ ranges = <0x82000000 0 0x28000000 0 0x28000000 0 0x8000000>; ++ status = "disabled"; + +- pcie1: pcie@1,0 { ++ slot1: pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; diff --git a/target/linux/mediatek/patches-5.4/0992-PCI-mediatek-Use-regmap-to-get-shared-pcie-cfg-base.patch b/target/linux/mediatek/patches-5.4/0992-PCI-mediatek-Use-regmap-to-get-shared-pcie-cfg-base.patch new file mode 100755 index 0000000000..e773e2e676 --- /dev/null +++ b/target/linux/mediatek/patches-5.4/0992-PCI-mediatek-Use-regmap-to-get-shared-pcie-cfg-base.patch @@ -0,0 +1,219 @@ +From patchwork Thu May 28 06:16:46 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Chuanjia Liu +X-Patchwork-Id: 11574781 +Return-Path: + +Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org + [172.30.200.123]) + by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0A99B60D + for ; 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Thu, 28 May 2020 14:18:51 +0800 +Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc + (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend + Transport; Thu, 28 May 2020 14:18:49 +0800 +From: +To: , , +Subject: [PATCH v2 2/4] PCI: mediatek: Use regmap to get shared pcie-cfg base +Date: Thu, 28 May 2020 14:16:46 +0800 +Message-ID: <20200528061648.32078-3-chuanjia.liu@mediatek.com> +X-Mailer: git-send-email 2.18.0 +In-Reply-To: <20200528061648.32078-1-chuanjia.liu@mediatek.com> +References: <20200528061648.32078-1-chuanjia.liu@mediatek.com> +MIME-Version: 1.0 +X-MTK: N +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20200527_231859_251275_BED2B1E2 +X-CRM114-Status: GOOD ( 11.62 ) +X-Spam-Score: -0.2 (/) +X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: + Content analysis details: (-0.2 points) + pts rule name description + ---- ---------------------- + -------------------------------------------------- + -0.0 SPF_PASS SPF: sender matches SPF record + 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record + 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 + encoding + -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from + author's domain + 0.1 DKIM_SIGNED Message has a DKIM or DK signature, + not necessarily + valid + -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature + -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from + envelope-from domain + 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay + lines +X-BeenThere: linux-mediatek@lists.infradead.org +X-Mailman-Version: 2.1.29 +Precedence: list +List-Id: +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Cc: devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com, + srv_heupstream@mediatek.com, "chuanjia.liu" , + linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, + jianjun.wang@mediatek.com, linux-mediatek@lists.infradead.org, + yong.wu@mediatek.com, bhelgaas@google.com, + linux-arm-kernel@lists.infradead.org, amurray@thegoodpenguin.co.uk +Sender: "Linux-mediatek" +Errors-To: + linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org + +From: "chuanjia.liu" + +Use regmap to get shared pcie-cfg base and change +the method to get pcie irq. + +Signed-off-by: chuanjia.liu +--- + drivers/pci/controller/pcie-mediatek.c | 25 ++++++++++++++++++------- + 1 file changed, 18 insertions(+), 7 deletions(-) + +diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c +index cb982891b22b..2268d6073eb6 100644 +--- a/drivers/pci/controller/pcie-mediatek.c ++++ b/drivers/pci/controller/pcie-mediatek.c +@@ -14,6 +14,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -23,6 +24,7 @@ + #include + #include + #include ++#include + #include + + #include "../pci.h" +@@ -205,6 +207,7 @@ struct mtk_pcie_port { + * struct mtk_pcie - PCIe host information + * @dev: pointer to PCIe device + * @base: IO mapped register base ++ * @cfg: IO mapped register map for PCIe config + * @free_ck: free-run reference clock + * @mem: non-prefetchable memory resource + * @ports: pointer to PCIe port information +@@ -214,6 +217,7 @@ struct mtk_pcie_port { + struct mtk_pcie { + struct device *dev; + void __iomem *base; ++ struct regmap *cfg; + struct clk *free_ck; + + struct list_head ports; +@@ -650,7 +654,7 @@ static int mtk_pcie_setup_irq(struct mtk_pcie_port *port, + return err; + } + +- port->irq = platform_get_irq(pdev, port->slot); ++ port->irq = platform_get_irq_byname(pdev, "pcie_irq"); + irq_set_chained_handler_and_data(port->irq, + mtk_pcie_intr_handler, port); + +@@ -673,12 +677,11 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) + if (!mem) + return -EINVAL; + +- /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */ +- if (pcie->base) { +- val = readl(pcie->base + PCIE_SYS_CFG_V2); +- val |= PCIE_CSR_LTSSM_EN(port->slot) | +- PCIE_CSR_ASPM_L1_EN(port->slot); +- writel(val, pcie->base + PCIE_SYS_CFG_V2); ++ /* MT7622/MT7629 platforms need to enable LTSSM and ASPM. */ ++ if (pcie->cfg) { ++ val = PCIE_CSR_LTSSM_EN(port->slot) | ++ PCIE_CSR_ASPM_L1_EN(port->slot); ++ regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val); + } + + /* Assert all reset signals */ +@@ -984,6 +987,7 @@ static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie) + struct device *dev = pcie->dev; + struct platform_device *pdev = to_platform_device(dev); + struct resource *regs; ++ struct device_node *cfg_node; + int err; + + /* get shared registers, which are optional */ +@@ -996,6 +1000,13 @@ static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie) + } + } + ++ cfg_node = of_parse_phandle(dev->of_node, "mediatek,pcie-cfg", 0); ++ if (cfg_node) { ++ pcie->cfg = syscon_node_to_regmap(cfg_node); ++ if (IS_ERR(pcie->cfg)) ++ return PTR_ERR(pcie->cfg); ++ } ++ + pcie->free_ck = devm_clk_get(dev, "free_ck"); + if (IS_ERR(pcie->free_ck)) { + if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER) diff --git a/target/linux/mediatek/patches-5.4/0993-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-MT7622.patch b/target/linux/mediatek/patches-5.4/0993-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-MT7622.patch new file mode 100755 index 0000000000..7d3c55c0e4 --- /dev/null +++ b/target/linux/mediatek/patches-5.4/0993-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-MT7622.patch @@ -0,0 +1,423 @@ +From patchwork Thu May 28 06:16:47 2020 +Content-Type: text/plain; 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Wed, 27 May 2020 22:19:17 -0800 +Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by + MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id + 15.0.1497.2; Wed, 27 May 2020 23:18:47 -0700 +Received: from mtkcas07.mediatek.inc (172.21.101.84) by + mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id + 15.0.1497.2; Thu, 28 May 2020 14:18:52 +0800 +Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc + (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend + Transport; Thu, 28 May 2020 14:18:51 +0800 +From: +To: , , +Subject: [PATCH v2 3/4] arm64: dts: mediatek: Split PCIe node for + MT2712/MT7622 +Date: Thu, 28 May 2020 14:16:47 +0800 +Message-ID: <20200528061648.32078-4-chuanjia.liu@mediatek.com> +X-Mailer: git-send-email 2.18.0 +In-Reply-To: <20200528061648.32078-1-chuanjia.liu@mediatek.com> +References: <20200528061648.32078-1-chuanjia.liu@mediatek.com> +MIME-Version: 1.0 +X-MTK: N +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20200527_231859_253529_B6751C5A +X-CRM114-Status: GOOD ( 12.20 ) +X-Spam-Score: -0.2 (/) +X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: + Content analysis details: (-0.2 points) + pts rule name description + ---- ---------------------- + -------------------------------------------------- + -0.0 SPF_PASS SPF: sender matches SPF record + 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record + 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 + encoding + -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from + author's domain + 0.1 DKIM_SIGNED Message has a DKIM or DK signature, + not necessarily + valid + -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature + -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from + envelope-from domain + 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay + lines +X-BeenThere: linux-mediatek@lists.infradead.org +X-Mailman-Version: 2.1.29 +Precedence: list +List-Id: +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Cc: devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com, + srv_heupstream@mediatek.com, "chuanjia.liu" , + linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, + jianjun.wang@mediatek.com, linux-mediatek@lists.infradead.org, + yong.wu@mediatek.com, bhelgaas@google.com, + linux-arm-kernel@lists.infradead.org, amurray@thegoodpenguin.co.uk +Sender: "Linux-mediatek" +Errors-To: + linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org + +From: "chuanjia.liu" + +There are two independent PCIe controllers in MT2712/MT7622 platform, +and each of them should contain an independent MSI domain. + +In current architecture, MSI domain will be inherited from the root +bridge, and all of the devices will share the same MSI domain. +Hence that, the PCIe devices will not work properly if the irq number +which required is more than 32. + +Split the PCIe node for MT2712/MT7622 platform to fix MSI issue and +comply with the hardware design. + +Signed-off-by: chuanjia.liu +--- + arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 75 +++++++++++-------- + .../dts/mediatek/mt7622-bananapi-bpi-r64.dts | 16 ++-- + arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 6 +- + arch/arm64/boot/dts/mediatek/mt7622.dtsi | 68 +++++++++++------ + 4 files changed, 96 insertions(+), 69 deletions(-) + +diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +index 2cd8b33886e5..ab27ff4a869e 100644 +--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +@@ -797,60 +797,73 @@ + }; + }; + +- pcie: pcie@11700000 { ++ pcie1: pcie@112ff000 { + compatible = "mediatek,mt2712-pcie"; + device_type = "pci"; +- reg = <0 0x11700000 0 0x1000>, +- <0 0x112ff000 0 0x1000>; +- reg-names = "port0", "port1"; ++ reg = <0 0x112ff000 0 0x1000>; ++ reg-names = "port1"; + #address-cells = <3>; + #size-cells = <2>; +- interrupts = , +- ; +- clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, +- <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, +- <&pericfg CLK_PERI_PCIE0>, ++ interrupts = ; ++ interrupt-names = "pcie_irq"; ++ clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, + <&pericfg CLK_PERI_PCIE1>; +- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1"; +- phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>; +- phy-names = "pcie-phy0", "pcie-phy1"; ++ clock-names = "sys_ck1", "ahb_ck1"; ++ phys = <&u3port1 PHY_TYPE_PCIE>; ++ phy-names = "pcie-phy1"; + bus-range = <0x00 0xff>; +- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; ++ ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>; ++ status = "disabled"; + +- pcie0: pcie@0,0 { +- device_type = "pci"; +- status = "disabled"; +- reg = <0x0000 0 0 0 0>; ++ slot1: pcie@1,0 { ++ reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0 0 0 1 &pcie_intc0 0>, +- <0 0 0 2 &pcie_intc0 1>, +- <0 0 0 3 &pcie_intc0 2>, +- <0 0 0 4 &pcie_intc0 3>; +- pcie_intc0: interrupt-controller { ++ interrupt-map = <0 0 0 1 &pcie_intc1 0>, ++ <0 0 0 2 &pcie_intc1 1>, ++ <0 0 0 3 &pcie_intc1 2>, ++ <0 0 0 4 &pcie_intc1 3>; ++ pcie_intc1: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; ++ }; + +- pcie1: pcie@1,0 { +- device_type = "pci"; +- status = "disabled"; +- reg = <0x0800 0 0 0 0>; ++ pcie0: pcie@11700000 { ++ compatible = "mediatek,mt2712-pcie"; ++ device_type = "pci"; ++ reg = <0 0x11700000 0 0x1000>; ++ reg-names = "port0"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ interrupts = ; ++ interrupt-names = "pcie_irq"; ++ clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, ++ <&pericfg CLK_PERI_PCIE0>; ++ clock-names = "sys_ck0", "ahb_ck0"; ++ phys = <&u3port0 PHY_TYPE_PCIE>; ++ phy-names = "pcie-phy0"; ++ bus-range = <0x00 0xff>; ++ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; ++ status = "disabled"; ++ ++ slot0: pcie@0,0 { ++ reg = <0x0000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 7>; +- interrupt-map = <0 0 0 1 &pcie_intc1 0>, +- <0 0 0 2 &pcie_intc1 1>, +- <0 0 0 3 &pcie_intc1 2>, +- <0 0 0 4 &pcie_intc1 3>; +- pcie_intc1: interrupt-controller { ++ interrupt-map = <0 0 0 1 &pcie_intc0 0>, ++ <0 0 0 2 &pcie_intc0 1>, ++ <0 0 0 3 &pcie_intc0 2>, ++ <0 0 0 4 &pcie_intc0 3>; ++ pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; +diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +index 83e10591e0e5..7574d88cc46a 100644 +--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +@@ -207,18 +207,16 @@ + }; + }; + +-&pcie { ++&pcie0 { + pinctrl-names = "default"; +- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>; ++ pinctrl-0 = <&pcie0_pins>; + status = "okay"; ++}; + +- pcie@0,0 { +- status = "okay"; +- }; +- +- pcie@1,0 { +- status = "okay"; +- }; ++&pcie1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie1_pins>; ++ status = "okay"; + }; + + &pio { +diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +index 339dc9f88f43..d5131c8b6a79 100644 +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -766,45 +766,41 @@ + #reset-cells = <1>; + }; + +- pcie: pcie@1a140000 { ++ pciecfg: pciecfg@1a140000 { ++ compatible = "mediatek,mt7622-pciecfg", "syscon"; ++ reg = <0 0x1a140000 0 0x1000>; ++ }; ++ ++ pcie0: pcie@1a143000 { + compatible = "mediatek,mt7622-pcie"; + device_type = "pci"; +- reg = <0 0x1a140000 0 0x1000>, +- <0 0x1a143000 0 0x1000>, +- <0 0x1a145000 0 0x1000>; +- reg-names = "subsys", "port0", "port1"; ++ reg = <0 0x1a143000 0 0x1000>; ++ reg-names = "port0"; ++ mediatek,pcie-cfg = <&pciecfg>; + #address-cells = <3>; + #size-cells = <2>; +- interrupts = , +- ; ++ interrupts = ; ++ interrupt-names = "pcie_irq"; + clocks = <&pciesys CLK_PCIE_P0_MAC_EN>, +- <&pciesys CLK_PCIE_P1_MAC_EN>, +- <&pciesys CLK_PCIE_P0_AHB_EN>, + <&pciesys CLK_PCIE_P0_AHB_EN>, + <&pciesys CLK_PCIE_P0_AUX_EN>, +- <&pciesys CLK_PCIE_P1_AUX_EN>, + <&pciesys CLK_PCIE_P0_AXI_EN>, +- <&pciesys CLK_PCIE_P1_AXI_EN>, + <&pciesys CLK_PCIE_P0_OBFF_EN>, +- <&pciesys CLK_PCIE_P1_OBFF_EN>, +- <&pciesys CLK_PCIE_P0_PIPE_EN>, +- <&pciesys CLK_PCIE_P1_PIPE_EN>; +- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1", +- "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1", +- "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1"; ++ <&pciesys CLK_PCIE_P0_PIPE_EN>; ++ clock-names = "sys_ck0", "ahb_ck0", "aux_ck0", ++ "axi_ck0", "obff_ck0", "pipe_ck0"; ++ + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; + bus-range = <0x00 0xff>; +- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; ++ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; + status = "disabled"; + +- pcie0: pcie@0,0 { ++ slot0: pcie@0,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; +- status = "disabled"; +- + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, +@@ -816,15 +812,39 @@ + #interrupt-cells = <1>; + }; + }; ++ }; + +- pcie1: pcie@1,0 { ++ pcie1: pcie@1a145000 { ++ compatible = "mediatek,mt7622-pcie"; ++ device_type = "pci"; ++ reg = <0 0x1a145000 0 0x1000>; ++ reg-names = "port1"; ++ mediatek,pcie-cfg = <&pciecfg>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ interrupts = ; ++ interrupt-names = "pcie_irq"; ++ clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, ++ /* designer has connect RC1 with p0_ahb clock */ ++ <&pciesys CLK_PCIE_P0_AHB_EN>, ++ <&pciesys CLK_PCIE_P1_AUX_EN>, ++ <&pciesys CLK_PCIE_P1_AXI_EN>, ++ <&pciesys CLK_PCIE_P1_OBFF_EN>, ++ <&pciesys CLK_PCIE_P1_PIPE_EN>; ++ clock-names = "sys_ck1", "ahb_ck1", "aux_ck1", ++ "axi_ck1", "obff_ck1", "pipe_ck1"; ++ ++ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; ++ bus-range = <0x00 0xff>; ++ ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; ++ status = "disabled"; ++ ++ slot1: pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; +- status = "disabled"; +- + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, +--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts 2020-06-15 18:52:25.092948824 +0800 ++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts 2020-06-15 18:52:15.909094229 +0800 +@@ -244,18 +244,16 @@ + }; + }; + +-&pcie { ++&pcie0 { + pinctrl-names = "default"; +- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>; ++ pinctrl-0 = <&pcie0_pins>; + status = "okay"; ++}; + +- pcie@0,0 { +- status = "okay"; +- }; +- +- pcie@1,0 { +- status = "okay"; +- }; ++&pcie1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie1_pins>; ++ status = "okay"; + }; + + &pio { diff --git a/target/linux/mediatek/patches-5.4/0994-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch b/target/linux/mediatek/patches-5.4/0994-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch new file mode 100755 index 0000000000..4ba99d89d0 --- /dev/null +++ b/target/linux/mediatek/patches-5.4/0994-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch @@ -0,0 +1,207 @@ +From patchwork Thu May 28 06:16:48 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Chuanjia Liu +X-Patchwork-Id: 11574797 +Return-Path: + +Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org + [172.30.200.123]) + by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 30A5E1392 + for ; + Thu, 28 May 2020 06:29:05 +0000 (UTC) +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by mail.kernel.org (Postfix) with ESMTPS id 08B6320721 + for ; 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Thu, 28 May 2020 14:18:52 +0800 +From: +To: , , +Subject: [PATCH v2 4/4] ARM: dts: mediatek: Update mt7629 PCIe node +Date: Thu, 28 May 2020 14:16:48 +0800 +Message-ID: <20200528061648.32078-5-chuanjia.liu@mediatek.com> +X-Mailer: git-send-email 2.18.0 +In-Reply-To: <20200528061648.32078-1-chuanjia.liu@mediatek.com> +References: <20200528061648.32078-1-chuanjia.liu@mediatek.com> +MIME-Version: 1.0 +X-MTK: N +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20200527_232901_719172_E5A99C62 +X-CRM114-Status: GOOD ( 11.61 ) +X-Spam-Score: -0.2 (/) +X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: + Content analysis details: (-0.2 points) + pts rule name description + ---- ---------------------- + -------------------------------------------------- + -0.0 SPF_PASS SPF: sender matches SPF record + 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record + 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 + encoding + -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from + author's domain + 0.1 DKIM_SIGNED Message has a DKIM or DK signature, + not necessarily + valid + -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature + -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from + envelope-from domain + 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay + lines +X-BeenThere: linux-mediatek@lists.infradead.org +X-Mailman-Version: 2.1.29 +Precedence: list +List-Id: +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Cc: devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com, + srv_heupstream@mediatek.com, "chuanjia.liu" , + linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, + jianjun.wang@mediatek.com, linux-mediatek@lists.infradead.org, + yong.wu@mediatek.com, bhelgaas@google.com, + linux-arm-kernel@lists.infradead.org, amurray@thegoodpenguin.co.uk +Sender: "Linux-mediatek" +Errors-To: + linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org + +From: "chuanjia.liu" + +Remove unused property and add pciecfg node. + +Signed-off-by: chuanjia.liu +--- + arch/arm/boot/dts/mt7629-rfb.dts | 3 ++- + arch/arm/boot/dts/mt7629.dtsi | 23 +++++++++++++---------- + 2 files changed, 15 insertions(+), 11 deletions(-) + +diff --git a/arch/arm/boot/dts/mt7629-rfb.dts b/arch/arm/boot/dts/mt7629-rfb.dts +index 9980c10c6e29..eb536cbebd9b 100644 +--- a/arch/arm/boot/dts/mt7629-rfb.dts ++++ b/arch/arm/boot/dts/mt7629-rfb.dts +@@ -140,9 +140,10 @@ + }; + }; + +-&pcie { ++&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; ++ status = "okay"; + }; + + &pciephy1 { +diff --git a/arch/arm/boot/dts/mt7629.dtsi b/arch/arm/boot/dts/mt7629.dtsi +index 5cbb3d244c75..94567307b842 100644 +--- a/arch/arm/boot/dts/mt7629.dtsi ++++ b/arch/arm/boot/dts/mt7629.dtsi +@@ -360,16 +360,21 @@ + #reset-cells = <1>; + }; + +- pcie: pcie@1a140000 { ++ pciecfg: pciecfg@1a140000 { ++ compatible = "mediatek,mt7629-pciecfg", "syscon"; ++ reg = <0x1a140000 0x1000>; ++ }; ++ ++ pcie1: pcie@1a145000 { + compatible = "mediatek,mt7629-pcie"; + device_type = "pci"; +- reg = <0x1a140000 0x1000>, +- <0x1a145000 0x1000>; +- reg-names = "subsys","port1"; ++ reg = <0x1a145000 0x1000>; ++ reg-names = "port1"; ++ mediatek,pcie-cfg = <&pciecfg>; + #address-cells = <3>; + #size-cells = <2>; +- interrupts = , +- ; ++ interrupts = ; ++ interrupt-names = "pcie_irq"; + clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, + <&pciesys CLK_PCIE_P0_AHB_EN>, + <&pciesys CLK_PCIE_P1_AUX_EN>, +@@ -390,21 +395,19 @@ + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>; ++ status = "disabled"; + +- pcie1: pcie@1,0 { +- device_type = "pci"; ++ slot1: pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; +- num-lanes = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; +- + pcie_intc1: interrupt-controller { + interrupt-controller; + #address-cells = <0>;