From: Werner Almesberger <werner@openmoko.org>
Date: Fri, 27 Feb 2009 11:03:07 +0000 (-0300)
Subject: [ARM] S3C64XX: Fix s3c64xx_setrate_clksrc
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=efeff568677aa325f84d3ce37c219019887a79eb;p=openwrt%2Fstaging%2Fblogic.git

[ARM] S3C64XX: Fix s3c64xx_setrate_clksrc

Some of the rate selection logic in s3c64xx_setrate_clksrc uses what
appears to be parent clock selection logic. This patch corrects it.

I also added a check for overly large dividers to prevent them from
changing unrelated clocks.

Signed-off-by: Werner Almesberger <werner@openmoko.org>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
---

diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c
index 6edbeef6aa9d..05b17528041e 100644
--- a/arch/arm/plat-s3c64xx/s3c6400-clock.c
+++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c
@@ -239,10 +239,12 @@ static int s3c64xx_setrate_clksrc(struct clk *clk, unsigned long rate)
 
 	rate = clk_round_rate(clk, rate);
 	div = clk_get_rate(clk->parent) / rate;
+	if (div > 16)
+		return -EINVAL;
 
 	val = __raw_readl(reg);
-	val &= ~sclk->mask;
-	val |= (rate - 1) << sclk->shift;
+	val &= ~(0xf << sclk->shift);
+	val |= (div - 1) << sclk->shift;
 	__raw_writel(val, reg);
 
 	return 0;