From: Xing Zheng Date: Tue, 2 Aug 2016 07:22:26 +0000 (+0800) Subject: clk: rockchip: add 65MHz and 106.5MHz rates to rk3399 plls used for HDMI X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=efc4204cf7b0792374676219fefc0651a9ca1e27;p=openwrt%2Fstaging%2Fblogic.git clk: rockchip: add 65MHz and 106.5MHz rates to rk3399 plls used for HDMI We need to add more clocks for supporting more display resolution for HDMI. Signed-off-by: Xing Zheng Signed-off-by: Heiko Stuebner --- diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index c109d80e7a8a..e4ca8a983d12 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -100,8 +100,10 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = { RK3036_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0), RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), RK3036_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0), + RK3036_PLL_RATE( 106500000, 1, 71, 4, 4, 1, 0), RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), RK3036_PLL_RATE( 74250000, 2, 99, 4, 4, 1, 0), + RK3036_PLL_RATE( 65000000, 1, 65, 6, 4, 1, 0), RK3036_PLL_RATE( 54000000, 1, 54, 6, 4, 1, 0), RK3036_PLL_RATE( 27000000, 1, 27, 6, 4, 1, 0), { /* sentinel */ },