From: Mathias Kresin Date: Tue, 2 Nov 2021 22:35:32 +0000 (+0100) Subject: uboot-lantiq: danube: fix SPL boot X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=e6f8cf622318e65a00a5322509707f3f25cef68e;p=openwrt%2Fstaging%2Fxback.git uboot-lantiq: danube: fix SPL boot On danube we only have 0x6800 bytes of usable SRAM. Everything behind can't be written to and a SPL u-boot locks up during boot. Since it's a hard to debug issue and took me more than two years to fix it, I consider it worth to include fix albeit SPL u-boots are not build in OpenWrt. I faced the issue while trying to shrink the u-boot to 64K since some boards only have an u-boot partition of that size from the days ifx-uboot was used. Signed-off-by: Mathias Kresin Reviewed-by: Daniel Schwierzeck --- diff --git a/package/boot/uboot-lantiq/patches/0032-MIPS-lantiq-danube-fix-SPL-boot.patch b/package/boot/uboot-lantiq/patches/0032-MIPS-lantiq-danube-fix-SPL-boot.patch new file mode 100644 index 0000000000..6cb309b8f2 --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0032-MIPS-lantiq-danube-fix-SPL-boot.patch @@ -0,0 +1,34 @@ +From 65f1f160139c2bac83650c9c7c4aee4e5fd74c7c Mon Sep 17 00:00:00 2001 +From: Mathias Kresin +Date: Sun, 2 May 2021 02:03:05 +0200 +Subject: [PATCH] MIPS: lantiq: danube: fix SPL boot + +On danube we only have 0x6800 bytes of usable SRAM. Everything behind +can't be written to and a SPL u-boot locks up during boot. + +Signed-off-by: Mathias Kresin +Reviewed-by: Daniel Schwierzeck +--- + arch/mips/include/asm/arch-danube/config.h | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/mips/include/asm/arch-danube/config.h ++++ b/arch/mips/include/asm/arch-danube/config.h +@@ -61,7 +61,7 @@ + + /* SRAM */ + #define CONFIG_SYS_SRAM_BASE 0xBE1A0000 +-#define CONFIG_SYS_SRAM_SIZE 0x10000 ++#define CONFIG_SYS_SRAM_SIZE 0x6800 + + /* ASC/UART driver and console */ + #define CONFIG_LANTIQ_SERIAL +@@ -117,7 +117,7 @@ + #define CONFIG_CMD_NET + #endif + +-#define CONFIG_SPL_MAX_SIZE (32 * 1024) ++#define CONFIG_SPL_MAX_SIZE (18 * 1024) + #define CONFIG_SPL_BSS_MAX_SIZE (8 * 1024) + #define CONFIG_SPL_STACK_MAX_SIZE (8 * 1024) + #define CONFIG_SPL_MALLOC_MAX_SIZE (32 * 1024)