From: Aneesh Kumar K.V Date: Mon, 28 Nov 2016 06:17:03 +0000 (+0530) Subject: powerpc/mm: update radix__pte_update to not do full mm tlb flush X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=e58d1cf24309b3b58c7cff7ea1f873e498fdaa39;p=openwrt%2Fstaging%2Fblogic.git powerpc/mm: update radix__pte_update to not do full mm tlb flush When we are updating a pte, we just need to flush the tlb mapping that pte. Right now we do a full mm flush because we don't track page size. Now that we have page size details in pte use that to do the optimized flush Signed-off-by: Aneesh Kumar K.V Signed-off-by: Michael Ellerman --- diff --git a/arch/powerpc/include/asm/book3s/64/radix.h b/arch/powerpc/include/asm/book3s/64/radix.h index 36f636911ade..f4066cf31b3e 100644 --- a/arch/powerpc/include/asm/book3s/64/radix.h +++ b/arch/powerpc/include/asm/book3s/64/radix.h @@ -145,13 +145,7 @@ static inline unsigned long radix__pte_update(struct mm_struct *mm, * new value of pte */ new_pte = (old_pte | set) & ~clr; - - /* - * For now let's do heavy pid flush - * radix__flush_tlb_page_psize(mm, addr, mmu_virtual_psize); - */ - radix__flush_tlb_mm(mm); - + radix__flush_tlb_pte_p9_dd1(old_pte, mm, addr); __radix_pte_update(ptep, 0, new_pte); } else old_pte = __radix_pte_update(ptep, clr, set);