From: Imre Kaloz Date: Fri, 15 Nov 2013 12:23:17 +0000 (+0000) Subject: replace the TI patch with a smaller patchset X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=e4eef7e6;p=openwrt%2Fstaging%2Fadrian.git replace the TI patch with a smaller patchset Signed-off-by: Imre Kaloz SVN-Revision: 38816 --- diff --git a/target/linux/omap/patches-3.12/001-ti_git.patch b/target/linux/omap/patches-3.12/001-ti_git.patch deleted file mode 100644 index 9a1b6c2ef1..0000000000 --- a/target/linux/omap/patches-3.12/001-ti_git.patch +++ /dev/null @@ -1,82370 +0,0 @@ ---- a/arch/arm/boot/dts/am335x-boneblack.dts -+++ b/arch/arm/boot/dts/am335x-boneblack.dts -@@ -15,3 +15,80 @@ - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; -+ -+&mmc1 { -+ vmmc-supply = <&vmmcsd_fixed>; -+}; -+ -+&mmc2 { -+ vmmc-supply = <&vmmcsd_fixed>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emmc_pins>; -+ bus-width = <8>; -+ ti,non-removable; -+ status = "okay"; -+}; -+ -+&am33xx_pinmux { -+ nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { -+ pinctrl-single,pins = < -+ 0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */ -+ 0xa0 0x08 /* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ -+ 0xa4 0x08 /* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ -+ 0xa8 0x08 /* lcd_data2.lcd_data2, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ -+ 0xac 0x08 /* lcd_data3.lcd_data3, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ -+ 0xb0 0x08 /* lcd_data4.lcd_data4, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ -+ 0xb4 0x08 /* lcd_data5.lcd_data5, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ -+ 0xb8 0x08 /* lcd_data6.lcd_data6, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ -+ 0xbc 0x08 /* lcd_data7.lcd_data7, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ -+ 0xc0 0x08 /* lcd_data8.lcd_data8, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ -+ 0xc4 0x08 /* lcd_data9.lcd_data9, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ -+ 0xc8 0x08 /* lcd_data10.lcd_data10, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ -+ 0xcc 0x08 /* lcd_data11.lcd_data11, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ -+ 0xd0 0x08 /* lcd_data12.lcd_data12, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ -+ 0xd4 0x08 /* lcd_data13.lcd_data13, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ -+ 0xd8 0x08 /* lcd_data14.lcd_data14, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ -+ 0xdc 0x08 /* lcd_data15.lcd_data15, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ -+ 0xe0 0x00 /* lcd_vsync.lcd_vsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ -+ 0xe4 0x00 /* lcd_hsync.lcd_hsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ -+ 0xe8 0x00 /* lcd_pclk.lcd_pclk, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ -+ 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ -+ >; -+ }; -+ nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins { -+ pinctrl-single,pins = < -+ 0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */ -+ >; -+ }; -+}; -+ -+&i2c0 { -+ hdmi1: hdmi@70 { -+ compatible = "nxp,tda998x"; -+ reg = <0x70>; -+ }; -+}; -+ -+&lcdc { -+ pinctrl-names = "default", "off"; -+ pinctrl-0 = <&nxp_hdmi_bonelt_pins>; -+ pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; -+ status = "okay"; -+ hdmi = <&hdmi1>; -+ display-timings { -+ 640x480P60 { -+ clock-frequency = <25200000>; -+ hactive = <640>; -+ vactive = <480>; -+ hfront-porch = <16>; -+ hback-porch = <48>; -+ hsync-len = <96>; -+ vback-porch = <31>; -+ vfront-porch = <11>; -+ vsync-len = <2>; -+ hsync-active = <0>; -+ vsync-active = <0>; -+ }; -+ }; -+}; -+ ---- a/arch/arm/boot/dts/am335x-bone-common.dtsi -+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi -@@ -107,6 +107,27 @@ - 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; -+ -+ mmc1_pins: pinmux_mmc1_pins { -+ pinctrl-single,pins = < -+ 0x160 (PIN_INPUT | MUX_MODE7) /* GPIO0_6 */ -+ >; -+ }; -+ -+ emmc_pins: pinmux_emmc_pins { -+ pinctrl-single,pins = < -+ 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ -+ 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ -+ 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ -+ 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ -+ 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ -+ 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ -+ 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ -+ 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ -+ 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ -+ 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ -+ >; -+ }; - }; - - ocp { -@@ -183,15 +204,24 @@ - led@4 { - label = "beaglebone:green:usr2"; - gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "cpu0"; - default-state = "off"; - }; - - led@5 { - label = "beaglebone:green:usr3"; - gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "mmc1"; - default-state = "off"; - }; - }; -+ -+ vmmcsd_fixed: fixedregulator@0 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vmmcsd_fixed"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; - }; - - /include/ "tps65217.dtsi" -@@ -260,3 +290,12 @@ - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - }; -+ -+&mmc1 { -+ status = "okay"; -+ bus-width = <0x4>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc1_pins>; -+ cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; -+ cd-inverted; -+}; ---- a/arch/arm/boot/dts/am335x-bone.dts -+++ b/arch/arm/boot/dts/am335x-bone.dts -@@ -9,3 +9,13 @@ - - #include "am33xx.dtsi" - #include "am335x-bone-common.dtsi" -+ -+&ldo3_reg { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+}; -+ -+&mmc1 { -+ vmmc-supply = <&ldo3_reg>; -+}; ---- a/arch/arm/boot/dts/am335x-evm.dts -+++ b/arch/arm/boot/dts/am335x-evm.dts -@@ -149,6 +149,54 @@ - 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; -+ -+ mmc1_pins: pinmux_mmc1_pins { -+ pinctrl-single,pins = < -+ 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ -+ >; -+ }; -+ -+ lcd_pins_s0: lcd_pins_s0 { -+ pinctrl-single,pins = < -+ 0x20 0x01 /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */ -+ 0x24 0x01 /* gpmc_ad9.lcd_data17, OUTPUT | MODE1 */ -+ 0x28 0x01 /* gpmc_ad10.lcd_data18, OUTPUT | MODE1 */ -+ 0x2c 0x01 /* gpmc_ad11.lcd_data19, OUTPUT | MODE1 */ -+ 0x30 0x01 /* gpmc_ad12.lcd_data20, OUTPUT | MODE1 */ -+ 0x34 0x01 /* gpmc_ad13.lcd_data21, OUTPUT | MODE1 */ -+ 0x38 0x01 /* gpmc_ad14.lcd_data22, OUTPUT | MODE1 */ -+ 0x3c 0x01 /* gpmc_ad15.lcd_data23, OUTPUT | MODE1 */ -+ 0xa0 0x00 /* lcd_data0.lcd_data0, OUTPUT | MODE0 */ -+ 0xa4 0x00 /* lcd_data1.lcd_data1, OUTPUT | MODE0 */ -+ 0xa8 0x00 /* lcd_data2.lcd_data2, OUTPUT | MODE0 */ -+ 0xac 0x00 /* lcd_data3.lcd_data3, OUTPUT | MODE0 */ -+ 0xb0 0x00 /* lcd_data4.lcd_data4, OUTPUT | MODE0 */ -+ 0xb4 0x00 /* lcd_data5.lcd_data5, OUTPUT | MODE0 */ -+ 0xb8 0x00 /* lcd_data6.lcd_data6, OUTPUT | MODE0 */ -+ 0xbc 0x00 /* lcd_data7.lcd_data7, OUTPUT | MODE0 */ -+ 0xc0 0x00 /* lcd_data8.lcd_data8, OUTPUT | MODE0 */ -+ 0xc4 0x00 /* lcd_data9.lcd_data9, OUTPUT | MODE0 */ -+ 0xc8 0x00 /* lcd_data10.lcd_data10, OUTPUT | MODE0 */ -+ 0xcc 0x00 /* lcd_data11.lcd_data11, OUTPUT | MODE0 */ -+ 0xd0 0x00 /* lcd_data12.lcd_data12, OUTPUT | MODE0 */ -+ 0xd4 0x00 /* lcd_data13.lcd_data13, OUTPUT | MODE0 */ -+ 0xd8 0x00 /* lcd_data14.lcd_data14, OUTPUT | MODE0 */ -+ 0xdc 0x00 /* lcd_data15.lcd_data15, OUTPUT | MODE0 */ -+ 0xe0 0x00 /* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */ -+ 0xe4 0x00 /* lcd_hsync.lcd_hsync, OUTPUT | MODE0 */ -+ 0xe8 0x00 /* lcd_pclk.lcd_pclk, OUTPUT | MODE0 */ -+ 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */ -+ >; -+ }; -+ -+ am335x_evm_audio_pins: am335x_evm_audio_pins { -+ pinctrl-single,pins = < -+ 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rx_dv.mcasp1_aclkx */ -+ 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_txd3.mcasp1_fsx */ -+ 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ -+ 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ -+ >; -+ }; - }; - - ocp { -@@ -244,6 +292,18 @@ - compatible = "ti,tmp275"; - reg = <0x48>; - }; -+ -+ tlv320aic3106: tlv320aic3106@1b { -+ compatible = "ti,tlv320aic3106"; -+ reg = <0x1b>; -+ status = "okay"; -+ -+ /* Regulators */ -+ AVDD-supply = <&vaux2_reg>; -+ IOVDD-supply = <&vaux2_reg>; -+ DRVDD-supply = <&vaux2_reg>; -+ DVDD-supply = <&vbat>; -+ }; - }; - - elm: elm@48080000 { -@@ -268,8 +328,7 @@ - nand@0,0 { - reg = <0 0 0>; /* CS0, offset 0 */ - nand-bus-width = <8>; -- ti,nand-ecc-opt = "bch8"; -- gpmc,device-nand = "true"; -+ ti,nand-ecc-opt= "bch8"; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; -@@ -293,53 +352,78 @@ - gpmc,wait-monitoring-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; -- - #address-cells = <1>; - #size-cells = <1>; -- elm_id = <&elm>; -- -+ ti,elm-id = <&elm>; - /* MTD partition table */ - partition@0 { - label = "SPL1"; - reg = <0x00000000 0x000020000>; - }; -- - partition@1 { - label = "SPL2"; - reg = <0x00020000 0x00020000>; - }; -- - partition@2 { - label = "SPL3"; - reg = <0x00040000 0x00020000>; - }; -- - partition@3 { - label = "SPL4"; - reg = <0x00060000 0x00020000>; - }; -- - partition@4 { - label = "U-boot"; - reg = <0x00080000 0x001e0000>; - }; -- - partition@5 { - label = "environment"; - reg = <0x00260000 0x00020000>; - }; -- - partition@6 { - label = "Kernel"; - reg = <0x00280000 0x00500000>; - }; -- - partition@7 { - label = "File-System"; - reg = <0x00780000 0x0F880000>; - }; - }; - }; -+ -+ lcdc: lcdc@0x4830e000 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&lcd_pins_s0>; -+ status = "okay"; -+ display-timings { -+ 800x480p62 { -+ clock-frequency = <30000000>; -+ hactive = <800>; -+ vactive = <480>; -+ hfront-porch = <39>; -+ hback-porch = <39>; -+ hsync-len = <47>; -+ vback-porch = <29>; -+ vfront-porch = <13>; -+ vsync-len = <2>; -+ hsync-active = <1>; -+ vsync-active = <1>; -+ }; -+ }; -+ }; -+ -+ sound { -+ compatible = "ti,da830-evm-audio"; -+ ti,model = "AM335x-EVM"; -+ ti,audio-codec = <&tlv320aic3106>; -+ ti,mcasp-controller = <&mcasp1>; -+ ti,codec-clock-rate = <12000000>; -+ ti,audio-routing = -+ "Headphone Jack", "HPLOUT", -+ "Headphone Jack", "HPROUT", -+ "LINE1L", "Line In", -+ "LINE1R", "Line In"; -+ }; - }; - - vbat: fixedregulator@0 { -@@ -403,10 +487,63 @@ - brightness-levels = <0 51 53 56 62 75 101 152 255>; - default-brightness-level = <8>; - }; -+ -+ panel { -+ compatible = "ti,tilcdc,panel"; -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&lcd_pins_s0>; -+ panel-info { -+ ac-bias = <255>; -+ ac-bias-intrpt = <0>; -+ dma-burst-sz = <16>; -+ bpp = <32>; -+ fdd = <0x80>; -+ sync-edge = <0>; -+ sync-ctrl = <1>; -+ raster-order = <0>; -+ fifo-th = <0>; -+ }; -+ -+ display-timings { -+ 800x480p62 { -+ clock-frequency = <30000000>; -+ hactive = <800>; -+ vactive = <480>; -+ hfront-porch = <39>; -+ hback-porch = <39>; -+ hsync-len = <47>; -+ vback-porch = <29>; -+ vfront-porch = <13>; -+ vsync-len = <2>; -+ hsync-active = <1>; -+ vsync-active = <1>; -+ }; -+ }; -+ }; - }; - - #include "tps65910.dtsi" - -+&mcasp1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&am335x_evm_audio_pins>; -+ -+ status = "okay"; -+ -+ op-mode = <0>; /* MCASP_IIS_MODE */ -+ tdm-slots = <2>; -+ /* 16 serializer */ -+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ -+ 0 0 1 2 -+ 0 0 0 0 -+ 0 0 0 0 -+ 0 0 0 0 -+ >; -+ tx-num-evt = <1>; -+ rx-num-evt = <1>; -+}; -+ - &tps { - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; -@@ -477,6 +614,8 @@ - }; - - vmmc_reg: regulator@12 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -@@ -509,7 +648,7 @@ - tsc { - ti,wires = <4>; - ti,x-plate-resistance = <200>; -- ti,coordiante-readouts = <5>; -+ ti,coordinate-readouts = <5>; - ti,wire-config = <0x00 0x11 0x22 0x33>; - }; - -@@ -517,3 +656,12 @@ - ti,adc-channels = <4 5 6 7>; - }; - }; -+ -+&mmc1 { -+ status = "okay"; -+ vmmc-supply = <&vmmc_reg>; -+ bus-width = <4>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc1_pins>; -+ cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/am335x-evm-profile2.dts -@@ -0,0 +1,296 @@ -+/* -+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+/dts-v1/; -+ -+#include "am33xx.dtsi" -+ -+/ { -+ model = "TI AM335x EVM"; -+ compatible = "ti,am335x-evm", "ti,am33xx"; -+ -+ cpus { -+ cpu@0 { -+ cpu0-supply = <&vdd1_reg>; -+ }; -+ }; -+ -+ memory { -+ device_type = "memory"; -+ reg = <0x80000000 0x10000000>; /* 256 MB */ -+ }; -+ -+ am33xx_pinmux: pinmux@44e10800 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&matrix_keypad_s0 &clkout2_pin>; -+ -+ matrix_keypad_s0: matrix_keypad_s0 { -+ pinctrl-single,pins = < -+ 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ -+ 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */ -+ 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */ -+ 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */ -+ 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */ -+ >; -+ }; -+ -+ i2c0_pins: pinmux_i2c0_pins { -+ pinctrl-single,pins = < -+ 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ -+ 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ -+ >; -+ }; -+ -+ spi0_pins: pinmux_spi0_pins { -+ pinctrl-single,pins = < -+ 0x150 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_clk.spi0_clk */ -+ 0x154 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */ -+ 0x158 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */ -+ 0x15c (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ -+ >; -+ }; -+ -+ uart0_pins: pinmux_uart0_pins { -+ pinctrl-single,pins = < -+ 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ -+ 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ -+ >; -+ }; -+ -+ clkout2_pin: pinmux_clkout2_pin { -+ pinctrl-single,pins = < -+ 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ -+ >; -+ }; -+ -+ cpsw_default: cpsw_default { -+ pinctrl-single,pins = < -+ /* Slave 1 */ -+ 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ -+ 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ -+ 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ -+ 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ -+ 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ -+ 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ -+ 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ -+ 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ -+ 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ -+ 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ -+ 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ -+ 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ -+ >; -+ }; -+ -+ cpsw_sleep: cpsw_sleep { -+ pinctrl-single,pins = < -+ /* Slave 1 reset value */ -+ 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ >; -+ }; -+ -+ davinci_mdio_default: davinci_mdio_default { -+ pinctrl-single,pins = < -+ /* MDIO */ -+ 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ -+ 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ -+ >; -+ }; -+ -+ davinci_mdio_sleep: davinci_mdio_sleep { -+ pinctrl-single,pins = < -+ /* MDIO reset value */ -+ 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ >; -+ }; -+ }; -+ -+ ocp { -+ uart0: serial@44e09000 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pins>; -+ -+ status = "okay"; -+ }; -+ -+ i2c0: i2c@44e0b000 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; -+ -+ status = "okay"; -+ clock-frequency = <400000>; -+ -+ tps: tps@2d { -+ reg = <0x2d>; -+ }; -+ }; -+ -+ spi0: spi@48030000 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins>; -+ -+ status = "okay"; -+ m25p80@0 { -+ compatible = "w25q64"; -+ spi-max-frequency = <24000000>; -+ reg = <0x0>; -+ }; -+ }; -+ }; -+ -+ vbat: fixedregulator@0 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vbat"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-boot-on; -+ }; -+ -+ lis3_reg: fixedregulator@1 { -+ compatible = "regulator-fixed"; -+ regulator-name = "lis3_reg"; -+ regulator-boot-on; -+ }; -+ -+ matrix_keypad: matrix_keypad@0 { -+ compatible = "gpio-matrix-keypad"; -+ debounce-delay-ms = <5>; -+ col-scan-delay-us = <2>; -+ -+ row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */ -+ &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */ -+ &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */ -+ -+ col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */ -+ &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */ -+ -+ linux,keymap = <0x0000008b /* MENU */ -+ 0x0100009e /* BACK */ -+ 0x02000069 /* LEFT */ -+ 0x0001006a /* RIGHT */ -+ 0x0101001c /* ENTER */ -+ 0x0201006c>; /* DOWN */ -+ }; -+}; -+ -+#include "tps65910.dtsi" -+ -+&tps { -+ vcc1-supply = <&vbat>; -+ vcc2-supply = <&vbat>; -+ vcc3-supply = <&vbat>; -+ vcc4-supply = <&vbat>; -+ vcc5-supply = <&vbat>; -+ vcc6-supply = <&vbat>; -+ vcc7-supply = <&vbat>; -+ vccio-supply = <&vbat>; -+ -+ regulators { -+ vrtc_reg: regulator@0 { -+ regulator-always-on; -+ }; -+ -+ vio_reg: regulator@1 { -+ regulator-always-on; -+ }; -+ -+ vdd1_reg: regulator@2 { -+ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ -+ regulator-name = "vdd_mpu"; -+ regulator-min-microvolt = <912500>; -+ regulator-max-microvolt = <1312500>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ vdd2_reg: regulator@3 { -+ /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ -+ regulator-name = "vdd_core"; -+ regulator-min-microvolt = <912500>; -+ regulator-max-microvolt = <1150000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ vdd3_reg: regulator@4 { -+ regulator-always-on; -+ }; -+ -+ vdig1_reg: regulator@5 { -+ regulator-always-on; -+ }; -+ -+ vdig2_reg: regulator@6 { -+ regulator-always-on; -+ }; -+ -+ vpll_reg: regulator@7 { -+ regulator-always-on; -+ }; -+ -+ vdac_reg: regulator@8 { -+ regulator-always-on; -+ }; -+ -+ vaux1_reg: regulator@9 { -+ regulator-always-on; -+ }; -+ -+ vaux2_reg: regulator@10 { -+ regulator-always-on; -+ }; -+ -+ vaux33_reg: regulator@11 { -+ regulator-always-on; -+ }; -+ -+ vmmc_reg: regulator@12 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ }; -+}; -+ -+&mac { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&cpsw_default>; -+ pinctrl-1 = <&cpsw_sleep>; -+}; -+ -+&davinci_mdio { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&davinci_mdio_default>; -+ pinctrl-1 = <&davinci_mdio_sleep>; -+}; -+ -+&cpsw_emac0 { -+ phy_id = <&davinci_mdio>, <0>; -+ phy-mode = "rgmii-txid"; -+}; -+ -+&cpsw_emac1 { -+ phy_id = <&davinci_mdio>, <1>; -+ phy-mode = "rgmii-txid"; -+}; -+ -+&mmc1 { -+ status = "okay"; -+ vmmc-supply = <&vmmc_reg>; -+ bus-width = <4>; -+}; ---- a/arch/arm/boot/dts/am335x-evmsk.dts -+++ b/arch/arm/boot/dts/am335x-evmsk.dts -@@ -35,6 +35,39 @@ - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>; - -+ lcd_pins_s0: lcd_pins_s0 { -+ pinctrl-single,pins = < -+ 0x20 0x01 /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */ -+ 0x24 0x01 /* gpmc_ad9.lcd_data17, OUTPUT | MODE1 */ -+ 0x28 0x01 /* gpmc_ad10.lcd_data18, OUTPUT | MODE1 */ -+ 0x2c 0x01 /* gpmc_ad11.lcd_data19, OUTPUT | MODE1 */ -+ 0x30 0x01 /* gpmc_ad12.lcd_data20, OUTPUT | MODE1 */ -+ 0x34 0x01 /* gpmc_ad13.lcd_data21, OUTPUT | MODE1 */ -+ 0x38 0x01 /* gpmc_ad14.lcd_data22, OUTPUT | MODE1 */ -+ 0x3c 0x01 /* gpmc_ad15.lcd_data23, OUTPUT | MODE1 */ -+ 0xa0 0x00 /* lcd_data0.lcd_data0, OUTPUT | MODE0 */ -+ 0xa4 0x00 /* lcd_data1.lcd_data1, OUTPUT | MODE0 */ -+ 0xa8 0x00 /* lcd_data2.lcd_data2, OUTPUT | MODE0 */ -+ 0xac 0x00 /* lcd_data3.lcd_data3, OUTPUT | MODE0 */ -+ 0xb0 0x00 /* lcd_data4.lcd_data4, OUTPUT | MODE0 */ -+ 0xb4 0x00 /* lcd_data5.lcd_data5, OUTPUT | MODE0 */ -+ 0xb8 0x00 /* lcd_data6.lcd_data6, OUTPUT | MODE0 */ -+ 0xbc 0x00 /* lcd_data7.lcd_data7, OUTPUT | MODE0 */ -+ 0xc0 0x00 /* lcd_data8.lcd_data8, OUTPUT | MODE0 */ -+ 0xc4 0x00 /* lcd_data9.lcd_data9, OUTPUT | MODE0 */ -+ 0xc8 0x00 /* lcd_data10.lcd_data10, OUTPUT | MODE0 */ -+ 0xcc 0x00 /* lcd_data11.lcd_data11, OUTPUT | MODE0 */ -+ 0xd0 0x00 /* lcd_data12.lcd_data12, OUTPUT | MODE0 */ -+ 0xd4 0x00 /* lcd_data13.lcd_data13, OUTPUT | MODE0 */ -+ 0xd8 0x00 /* lcd_data14.lcd_data14, OUTPUT | MODE0 */ -+ 0xdc 0x00 /* lcd_data15.lcd_data15, OUTPUT | MODE0 */ -+ 0xe0 0x00 /* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */ -+ 0xe4 0x00 /* lcd_hsync.lcd_hsync, OUTPUT | MODE0 */ -+ 0xe8 0x00 /* lcd_pclk.lcd_pclk, OUTPUT | MODE0 */ -+ 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */ -+ >; -+ }; -+ - user_leds_s0: user_leds_s0 { - pinctrl-single,pins = < - 0x10 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */ -@@ -158,6 +191,21 @@ - 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; -+ -+ mmc1_pins: pinmux_mmc1_pins { -+ pinctrl-single,pins = < -+ 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ -+ >; -+ }; -+ -+ mcasp1_pins: mcasp1_pins { -+ pinctrl-single,pins = < -+ 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ -+ 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ -+ 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ -+ 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ -+ >; -+ }; - }; - - ocp { -@@ -206,6 +254,18 @@ - st,max-limit-y = <550>; - st,max-limit-z = <750>; - }; -+ -+ tlv320aic3106: tlv320aic3106@1b { -+ compatible = "ti,tlv320aic3106"; -+ reg = <0x1b>; -+ status = "okay"; -+ -+ /* Regulators */ -+ AVDD-supply = <&vaux2_reg>; -+ IOVDD-supply = <&vaux2_reg>; -+ DRVDD-supply = <&vaux2_reg>; -+ DVDD-supply = <&vbat>; -+ }; - }; - - musb: usb@47400000 { -@@ -219,9 +279,22 @@ - status = "okay"; - }; - -+ usb-phy@47401b00 { -+ status = "okay"; -+ }; -+ - usb@47401000 { - status = "okay"; - }; -+ -+ usb@47401800 { -+ status = "okay"; -+ dr_mode = "host"; -+ }; -+ -+ dma-controller@07402000 { -+ status = "okay"; -+ }; - }; - - epwmss2: epwmss@48304000 { -@@ -233,6 +306,38 @@ - pinctrl-0 = <&ecap2_pins>; - }; - }; -+ -+ lcdc: lcdc@0x4830e000 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&lcd_pins_s0>; -+ status = "okay"; -+ display-timings { -+ 480x272 { -+ hactive = <480>; -+ vactive = <272>; -+ hback-porch = <43>; -+ hfront-porch = <8>; -+ hsync-len = <4>; -+ vback-porch = <12>; -+ vfront-porch = <4>; -+ vsync-len = <10>; -+ clock-frequency = <9000000>; -+ hsync-active = <0>; -+ vsync-active = <0>; -+ }; -+ }; -+ }; -+ -+ sound { -+ compatible = "ti,da830-evm-audio"; -+ ti,model = "AM335x-EVMSK"; -+ ti,audio-codec = <&tlv320aic3106>; -+ ti,mcasp-controller = <&mcasp1>; -+ ti,codec-clock-rate = <24576000>; -+ ti,audio-routing = -+ "Headphone Jack", "HPLOUT", -+ "Headphone Jack", "HPROUT"; -+ }; - }; - - vbat: fixedregulator@0 { -@@ -393,6 +498,8 @@ - }; - - vmmc_reg: regulator@12 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -@@ -419,3 +526,45 @@ - phy_id = <&davinci_mdio>, <1>; - phy-mode = "rgmii-txid"; - }; -+ -+&tscadc { -+ status = "okay"; -+ tsc { -+ ti,wires = <4>; -+ ti,x-plate-resistance = <200>; -+ ti,coordinate-readouts = <5>; -+ ti,wire-config = <0x00 0x11 0x22 0x33>; -+ }; -+}; -+ -+&gpio0 { -+ ti,no-reset; -+}; -+ -+&mmc1 { -+ status = "okay"; -+ vmmc-supply = <&vmmc_reg>; -+ bus-width = <4>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc1_pins>; -+ cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; -+}; -+ -+&mcasp1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mcasp1_pins>; -+ -+ status = "okay"; -+ -+ op-mode = <0>; /* MCASP_IIS_MODE */ -+ tdm-slots = <2>; -+ /* 16 serializer */ -+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ -+ 0 0 1 2 -+ 0 0 0 0 -+ 0 0 0 0 -+ 0 0 0 0 -+ >; -+ tx-num-evt = <1>; -+ rx-num-evt = <1>; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi -@@ -0,0 +1,661 @@ -+/* -+ * Device Tree Source for AM33xx clock data -+ * -+ * Copyright (C) 2013 Texas Instruments, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+clk_32768_ck: clk_32768_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <32768>; -+}; -+ -+clk_rc32k_ck: clk_rc32k_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <32000>; -+}; -+ -+virt_19200000_ck: virt_19200000_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <19200000>; -+}; -+ -+virt_24000000_ck: virt_24000000_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <24000000>; -+}; -+ -+virt_25000000_ck: virt_25000000_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <25000000>; -+}; -+ -+virt_26000000_ck: virt_26000000_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <26000000>; -+}; -+ -+sys_clkin_ck: sys_clkin_ck@44e10040 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; -+ bit-shift = <22>; -+ reg = <0x44e10040 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+tclkin_ck: tclkin_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <12000000>; -+}; -+ -+dpll_core_ck: dpll_core_ck@44e00490 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-core-clock"; -+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; -+ reg = <0x44e00490 0x4>, <0x44e0045c 0x4>, <0x44e00468 0x4>; -+ reg-names = "control", "idlest", "mult-div1"; -+}; -+ -+dpll_core_x2_ck: dpll_core_x2_ck { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-x2-clock"; -+ clocks = <&dpll_core_ck>; -+}; -+ -+dpll_core_m4_ck: dpll_core_m4_ck@44e00480 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_core_x2_ck>; -+ reg = <0x44e00480 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+}; -+ -+dpll_core_m5_ck: dpll_core_m5_ck@44e00484 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_core_x2_ck>; -+ reg = <0x44e00484 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+}; -+ -+dpll_core_m6_ck: dpll_core_m6_ck@44e004d8 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_core_x2_ck>; -+ reg = <0x44e004d8 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+}; -+ -+dpll_mpu_ck: dpll_mpu_ck@44e00488 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-clock"; -+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; -+ reg = <0x44e00488 0x4>, <0x44e00420 0x4>, <0x44e0042c 0x4>; -+ reg-names = "control", "idlest", "mult-div1"; -+}; -+ -+dpll_mpu_m2_ck: dpll_mpu_m2_ck@44e004a8 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_mpu_ck>; -+ reg = <0x44e004a8 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+}; -+ -+dpll_ddr_ck: dpll_ddr_ck@44e00494 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-no-gate-clock"; -+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; -+ reg = <0x44e00494 0x4>, <0x44e00434 0x4>, <0x44e00440 0x4>; -+ reg-names = "control", "idlest", "mult-div1"; -+}; -+ -+dpll_ddr_m2_ck: dpll_ddr_m2_ck@44e004a0 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_ddr_ck>; -+ reg = <0x44e004a0 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+}; -+ -+dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_ddr_m2_ck>; -+ clock-mult = <1>; -+ clock-div = <2>; -+}; -+ -+dpll_disp_ck: dpll_disp_ck@44e00498 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-no-gate-clock"; -+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; -+ reg = <0x44e00498 0x4>, <0x44e00448 0x4>, <0x44e00454 0x4>; -+ reg-names = "control", "idlest", "mult-div1"; -+}; -+ -+dpll_disp_m2_ck: dpll_disp_m2_ck@44e004a4 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_disp_ck>; -+ reg = <0x44e004a4 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ set-rate-parent; -+}; -+ -+dpll_per_ck: dpll_per_ck@44e0048c { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-no-gate-j-type-clock"; -+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; -+ reg = <0x44e0048c 0x4>, <0x44e00470 0x4>, <0x44e0049c 0x4>; -+ reg-names = "control", "idlest", "mult-div1"; -+}; -+ -+dpll_per_m2_ck: dpll_per_m2_ck@44e004ac { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_per_ck>; -+ reg = <0x44e004ac 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+}; -+ -+dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_per_m2_ck>; -+ clock-mult = <1>; -+ clock-div = <4>; -+}; -+ -+dpll_per_m2_div4_ck: dpll_per_m2_div4_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_per_m2_ck>; -+ clock-mult = <1>; -+ clock-div = <4>; -+}; -+ -+adc_tsc_fck: adc_tsc_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&sys_clkin_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+cefuse_fck: cefuse_fck@44e00a20 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_clkin_ck>; -+ bit-shift = <1>; -+ reg = <0x44e00a20 0x4>; -+}; -+ -+clk_24mhz: clk_24mhz { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_per_m2_ck>; -+ clock-mult = <1>; -+ clock-div = <8>; -+}; -+ -+clkdiv32k_ck: clkdiv32k_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&clk_24mhz>; -+ clock-mult = <1>; -+ clock-div = <732>; -+}; -+ -+clkdiv32k_ick: clkdiv32k_ick@44e0014c { -+ #clock-cells = <0>; -+ compatible = "ti,gate-clock"; -+ clocks = <&clkdiv32k_ck>; -+ reg = <0x44e0014c 0x4>; -+ bit-shift = <1>; -+}; -+ -+dcan0_fck: dcan0_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&sys_clkin_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+dcan1_fck: dcan1_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&sys_clkin_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+l3_gclk: l3_gclk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_core_m4_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+pruss_ocp_gclk: pruss_ocp_gclk@44e00530 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&l3_gclk>, <&dpll_disp_m2_ck>; -+ reg = <0x44e00530 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+mcasp0_fck: mcasp0_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&sys_clkin_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+mcasp1_fck: mcasp1_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&sys_clkin_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+mmu_fck: mmu_fck@44e00914 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dpll_core_m4_ck>; -+ bit-shift = <1>; -+ reg = <0x44e00914 0x4>; -+}; -+ -+smartreflex0_fck: smartreflex0_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&sys_clkin_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+smartreflex1_fck: smartreflex1_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&sys_clkin_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+sha0_fck: sha0_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&sys_clkin_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+rng_fck: rng_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&sys_clkin_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+aes0_fck: aes0_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&sys_clkin_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+timer1_fck: timer1_fck@44e00528 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>; -+ reg = <0x44e00528 0x4>; -+ bit-mask = <0x7>; -+}; -+ -+timer2_fck: timer2_fck@44e00508 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; -+ reg = <0x44e00508 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+timer3_fck: timer3_fck@44e0050c { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; -+ reg = <0x44e0050c 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+timer4_fck: timer4_fck@44e00510 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; -+ reg = <0x44e00510 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+timer5_fck: timer5_fck@44e00518 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; -+ reg = <0x44e00518 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+timer6_fck: timer6_fck@44e0051c { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; -+ reg = <0x44e0051c 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+timer7_fck: timer7_fck@44e00504 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; -+ reg = <0x44e00504 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+usbotg_fck: usbotg_fck@44e0047c { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dpll_per_ck>; -+ bit-shift = <8>; -+ reg = <0x44e0047c 0x4>; -+}; -+ -+dpll_core_m4_div2_ck: dpll_core_m4_div2_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_core_m4_ck>; -+ clock-mult = <1>; -+ clock-div = <2>; -+}; -+ -+ieee5000_fck: ieee5000_fck@44e000e4 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dpll_core_m4_div2_ck>; -+ bit-shift = <1>; -+ reg = <0x44e000e4 0x4>; -+}; -+ -+wdt1_fck: wdt1_fck@44e00538 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>; -+ reg = <0x44e00538 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+l4_rtc_gclk: l4_rtc_gclk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_core_m4_ck>; -+ clock-mult = <1>; -+ clock-div = <2>; -+}; -+ -+l4hs_gclk: l4hs_gclk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_core_m4_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+l3s_gclk: l3s_gclk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_core_m4_div2_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+l4fw_gclk: l4fw_gclk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_core_m4_div2_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+l4ls_gclk: l4ls_gclk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_core_m4_div2_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+sysclk_div_ck: sysclk_div_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_core_m4_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+cpsw_125mhz_gclk: cpsw_125mhz_gclk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_core_m5_ck>; -+ clock-mult = <1>; -+ clock-div = <2>; -+}; -+ -+cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@44e00520 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>; -+ reg = <0x44e00520 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@44e0053c { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>; -+ reg = <0x44e0053c 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+gpio0_dbclk: gpio0_dbclk@44e00408 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&gpio0_dbclk_mux_ck>; -+ bit-shift = <18>; -+ reg = <0x44e00408 0x4>; -+}; -+ -+gpio1_dbclk: gpio1_dbclk@44e000ac { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&clkdiv32k_ick>; -+ bit-shift = <18>; -+ reg = <0x44e000ac 0x4>; -+}; -+ -+gpio2_dbclk: gpio2_dbclk@44e000b0 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&clkdiv32k_ick>; -+ bit-shift = <18>; -+ reg = <0x44e000b0 0x4>; -+}; -+ -+gpio3_dbclk: gpio3_dbclk@44e000b4 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&clkdiv32k_ick>; -+ bit-shift = <18>; -+ reg = <0x44e000b4 0x4>; -+}; -+ -+lcd_gclk: lcd_gclk@44e00534 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; -+ reg = <0x44e00534 0x4>; -+ bit-mask = <0x3>; -+ set-rate-parent; -+}; -+ -+mmc_clk: mmc_clk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_per_m2_ck>; -+ clock-mult = <1>; -+ clock-div = <2>; -+}; -+ -+gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@44e0052c { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>; -+ bit-shift = <1>; -+ reg = <0x44e0052c 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+gfx_fck_div_ck: gfx_fck_div_ck@44e0052c { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&gfx_fclk_clksel_ck>; -+ reg = <0x44e0052c 0x4>; -+ table = < 1 0 >, < 2 1 >; -+ bit-mask = <0x1>; -+}; -+ -+sysclkout_pre_ck: sysclkout_pre_ck@44e00700 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>; -+ reg = <0x44e00700 0x4>; -+ bit-mask = <0x7>; -+}; -+ -+clkout2_div_ck: clkout2_div_ck@44e00700 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&sysclkout_pre_ck>; -+ bit-shift = <3>; -+ reg = <0x44e00700 0x4>; -+ table = < 1 0 >, < 2 1 >, < 3 2 >, < 4 3 >, < 5 4 >, < 6 5 >, < 7 6 >, < 8 7 >; -+ bit-mask = <0x7>; -+}; -+ -+dbg_sysclk_ck: dbg_sysclk_ck@44e00414 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_clkin_ck>; -+ bit-shift = <19>; -+ reg = <0x44e00414 0x4>; -+}; -+ -+dbg_clka_ck: dbg_clka_ck@44e00414 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dpll_core_m4_ck>; -+ bit-shift = <30>; -+ reg = <0x44e00414 0x4>; -+}; -+ -+stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck@44e00414 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>; -+ bit-shift = <22>; -+ reg = <0x44e00414 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck@44e00414 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>; -+ bit-shift = <20>; -+ reg = <0x44e00414 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+stm_clk_div_ck: stm_clk_div_ck@44e00414 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&stm_pmd_clock_mux_ck>; -+ bit-shift = <27>; -+ reg = <0x44e00414 0x4>; -+ bit-mask = <0x7>; -+ index-power-of-two; -+}; -+ -+trace_clk_div_ck: trace_clk_div_ck@44e00414 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&trace_pmd_clk_mux_ck>; -+ bit-shift = <24>; -+ reg = <0x44e00414 0x4>; -+ bit-mask = <0x7>; -+ index-power-of-two; -+}; -+ -+clkout2_ck: clkout2_ck@44e00700 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&clkout2_div_ck>; -+ bit-shift = <7>; -+ reg = <0x44e00700 0x4>; -+}; -+ -+ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dpll_per_m2_ck>; -+ bit-shift = <0>; -+ reg = <0x44e10664 0x4>; -+}; -+ -+ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dpll_per_m2_ck>; -+ bit-shift = <1>; -+ reg = <0x44e10664 0x4>; -+}; -+ -+ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dpll_per_m2_ck>; -+ bit-shift = <2>; -+ reg = <0x44e10664 0x4>; -+}; ---- a/arch/arm/boot/dts/am33xx.dtsi -+++ b/arch/arm/boot/dts/am33xx.dtsi -@@ -18,6 +18,9 @@ - interrupt-parent = <&intc>; - - aliases { -+ i2c0 = &i2c0; -+ i2c1 = &i2c1; -+ i2c2 = &i2c2; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; -@@ -30,6 +33,8 @@ - usb1 = &usb1; - phy0 = &usb0_phy; - phy1 = &usb1_phy; -+ ethernet0 = &cpsw_emac0; -+ ethernet1 = &cpsw_emac1; - }; - - cpus { -@@ -53,6 +58,10 @@ - 275000 1125000 - >; - voltage-tolerance = <2>; /* 2 percentage */ -+ -+ clocks = <&dpll_mpu_ck>; -+ clock-names = "cpu"; -+ - clock-latency = <300000>; /* From omap-cpufreq driver */ - }; - }; -@@ -91,6 +100,8 @@ - #size-cells = <1>; - ranges; - ti,hwmods = "l3_main"; -+ clocks = <&l3_gclk>; -+ clock-names = "fck"; - - intc: interrupt-controller@48200000 { - compatible = "ti,omap2-intc"; -@@ -100,9 +111,23 @@ - reg = <0x48200000 0x1000>; - }; - -+ edma: edma@49000000 { -+ compatible = "ti,edma3"; -+ ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; -+ reg = <0x49000000 0x10000>, -+ <0x44e10f90 0x10>; -+ interrupts = <12 13 14>; -+ #dma-cells = <1>; -+ dma-channels = <64>; -+ ti,edma-regions = <4>; -+ ti,edma-slots = <256>; -+ }; -+ - gpio0: gpio@44e07000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio1"; -+ clocks = <&dpll_core_m4_div2_ck>, <&gpio0_dbclk>; -+ clock-names = "fck", "dbclk"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; -@@ -114,6 +139,8 @@ - gpio1: gpio@4804c000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio2"; -+ clocks = <&l4ls_gclk>, <&gpio1_dbclk>; -+ clock-names = "fck", "dbclk"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; -@@ -125,6 +152,8 @@ - gpio2: gpio@481ac000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio3"; -+ clocks = <&l4ls_gclk>, <&gpio2_dbclk>; -+ clock-names = "fck", "dbclk"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; -@@ -136,6 +165,8 @@ - gpio3: gpio@481ae000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio4"; -+ clocks = <&l4ls_gclk>, <&gpio3_dbclk>; -+ clock-names = "fck", "dbclk"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; -@@ -147,6 +178,8 @@ - uart0: serial@44e09000 { - compatible = "ti,omap3-uart"; - ti,hwmods = "uart1"; -+ clocks = <&dpll_per_m2_div4_wkupdm_ck>; -+ clock-names = "fck"; - clock-frequency = <48000000>; - reg = <0x44e09000 0x2000>; - interrupts = <72>; -@@ -156,6 +189,8 @@ - uart1: serial@48022000 { - compatible = "ti,omap3-uart"; - ti,hwmods = "uart2"; -+ clocks = <&dpll_per_m2_div4_ck>; -+ clock-names = "fck"; - clock-frequency = <48000000>; - reg = <0x48022000 0x2000>; - interrupts = <73>; -@@ -165,6 +200,8 @@ - uart2: serial@48024000 { - compatible = "ti,omap3-uart"; - ti,hwmods = "uart3"; -+ clocks = <&dpll_per_m2_div4_ck>; -+ clock-names = "fck"; - clock-frequency = <48000000>; - reg = <0x48024000 0x2000>; - interrupts = <74>; -@@ -174,6 +211,8 @@ - uart3: serial@481a6000 { - compatible = "ti,omap3-uart"; - ti,hwmods = "uart4"; -+ clocks = <&dpll_per_m2_div4_ck>; -+ clock-names = "fck"; - clock-frequency = <48000000>; - reg = <0x481a6000 0x2000>; - interrupts = <44>; -@@ -183,6 +222,8 @@ - uart4: serial@481a8000 { - compatible = "ti,omap3-uart"; - ti,hwmods = "uart5"; -+ clocks = <&dpll_per_m2_div4_ck>; -+ clock-names = "fck"; - clock-frequency = <48000000>; - reg = <0x481a8000 0x2000>; - interrupts = <45>; -@@ -192,6 +233,8 @@ - uart5: serial@481aa000 { - compatible = "ti,omap3-uart"; - ti,hwmods = "uart6"; -+ clocks = <&dpll_per_m2_div4_ck>; -+ clock-names = "fck"; - clock-frequency = <48000000>; - reg = <0x481aa000 0x2000>; - interrupts = <46>; -@@ -203,6 +246,8 @@ - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c1"; -+ clocks = <&dpll_per_m2_div4_wkupdm_ck>; -+ clock-names = "fck"; - reg = <0x44e0b000 0x1000>; - interrupts = <70>; - status = "disabled"; -@@ -213,6 +258,8 @@ - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c2"; -+ clocks = <&dpll_per_m2_div4_ck>; -+ clock-names = "fck"; - reg = <0x4802a000 0x1000>; - interrupts = <71>; - status = "disabled"; -@@ -223,14 +270,62 @@ - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c3"; -+ clocks = <&dpll_per_m2_div4_ck>; -+ clock-names = "fck"; - reg = <0x4819c000 0x1000>; - interrupts = <30>; - status = "disabled"; - }; - -+ mmc1: mmc@48060000 { -+ compatible = "ti,omap4-hsmmc"; -+ ti,hwmods = "mmc1"; -+ clocks = <&mmc_clk>, <&clkdiv32k_ick>; -+ clock-names = "fck", "mmchsdb_fck"; -+ ti,dual-volt; -+ ti,needs-special-reset; -+ ti,needs-special-hs-handling; -+ dmas = <&edma 24 -+ &edma 25>; -+ dma-names = "tx", "rx"; -+ interrupts = <64>; -+ interrupt-parent = <&intc>; -+ reg = <0x48060000 0x1000>; -+ status = "disabled"; -+ }; -+ -+ mmc2: mmc@481d8000 { -+ compatible = "ti,omap4-hsmmc"; -+ ti,hwmods = "mmc2"; -+ clocks = <&mmc_clk>, <&clkdiv32k_ick>; -+ clock-names = "fck", "mmchsdb_fck"; -+ ti,needs-special-reset; -+ dmas = <&edma 2 -+ &edma 3>; -+ dma-names = "tx", "rx"; -+ interrupts = <28>; -+ interrupt-parent = <&intc>; -+ reg = <0x481d8000 0x1000>; -+ status = "disabled"; -+ }; -+ -+ mmc3: mmc@47810000 { -+ compatible = "ti,omap4-hsmmc"; -+ ti,hwmods = "mmc3"; -+ clocks = <&mmc_clk>, <&clkdiv32k_ick>; -+ clock-names = "fck", "mmchsdb_fck"; -+ ti,needs-special-reset; -+ interrupts = <29>; -+ interrupt-parent = <&intc>; -+ reg = <0x47810000 0x1000>; -+ status = "disabled"; -+ }; -+ - wdt2: wdt@44e35000 { - compatible = "ti,omap3-wdt"; - ti,hwmods = "wd_timer2"; -+ clocks = <&wdt1_fck>; -+ clock-names = "fck"; - reg = <0x44e35000 0x1000>; - interrupts = <91>; - }; -@@ -238,6 +333,8 @@ - dcan0: d_can@481cc000 { - compatible = "bosch,d_can"; - ti,hwmods = "d_can0"; -+ clocks = <&dcan0_fck>; -+ clock-names = "fck"; - reg = <0x481cc000 0x2000 - 0x44e10644 0x4>; - interrupts = <52>; -@@ -247,17 +344,32 @@ - dcan1: d_can@481d0000 { - compatible = "bosch,d_can"; - ti,hwmods = "d_can1"; -+ clocks = <&dcan1_fck>; -+ clock-names = "fck"; - reg = <0x481d0000 0x2000 - 0x44e10644 0x4>; - interrupts = <55>; - status = "disabled"; - }; - -+ mailbox: mailbox@480C8000 { -+ compatible = "ti,omap4-mailbox"; -+ reg = <0x480C8000 0x200>; -+ interrupts = <77>; -+ ti,hwmods = "mailbox"; -+ ti,mbox-num-users = <4>; -+ ti,mbox-num-fifos = <8>; -+ ti,mbox-names = "wkup_m3"; -+ ti,mbox-data = <0 0 0 0>; -+ }; -+ - timer1: timer@44e31000 { - compatible = "ti,am335x-timer-1ms"; - reg = <0x44e31000 0x400>; - interrupts = <67>; - ti,hwmods = "timer1"; -+ clocks = <&timer1_fck>; -+ clock-names = "fck"; - ti,timer-alwon; - }; - -@@ -266,6 +378,8 @@ - reg = <0x48040000 0x400>; - interrupts = <68>; - ti,hwmods = "timer2"; -+ clocks = <&timer2_fck>; -+ clock-names = "fck"; - }; - - timer3: timer@48042000 { -@@ -273,6 +387,8 @@ - reg = <0x48042000 0x400>; - interrupts = <69>; - ti,hwmods = "timer3"; -+ clocks = <&timer3_fck>; -+ clock-names = "fck"; - }; - - timer4: timer@48044000 { -@@ -280,6 +396,8 @@ - reg = <0x48044000 0x400>; - interrupts = <92>; - ti,hwmods = "timer4"; -+ clocks = <&timer4_fck>; -+ clock-names = "fck"; - ti,timer-pwm; - }; - -@@ -288,6 +406,8 @@ - reg = <0x48046000 0x400>; - interrupts = <93>; - ti,hwmods = "timer5"; -+ clocks = <&timer5_fck>; -+ clock-names = "fck"; - ti,timer-pwm; - }; - -@@ -296,6 +416,8 @@ - reg = <0x48048000 0x400>; - interrupts = <94>; - ti,hwmods = "timer6"; -+ clocks = <&timer6_fck>; -+ clock-names = "fck"; - ti,timer-pwm; - }; - -@@ -304,6 +426,8 @@ - reg = <0x4804a000 0x400>; - interrupts = <95>; - ti,hwmods = "timer7"; -+ clocks = <&timer7_fck>; -+ clock-names = "fck"; - ti,timer-pwm; - }; - -@@ -313,6 +437,8 @@ - interrupts = <75 - 76>; - ti,hwmods = "rtc"; -+ clocks = <&clk_32768_ck>; -+ clock-names = "fck"; - }; - - spi0: spi@48030000 { -@@ -323,6 +449,13 @@ - interrupts = <65>; - ti,spi-num-cs = <2>; - ti,hwmods = "spi0"; -+ clocks = <&dpll_per_m2_div4_ck>; -+ clock-names = "fck"; -+ dmas = <&edma 16 -+ &edma 17 -+ &edma 18 -+ &edma 19>; -+ dma-names = "tx0", "rx0", "tx1", "rx1"; - status = "disabled"; - }; - -@@ -334,6 +467,13 @@ - interrupts = <125>; - ti,spi-num-cs = <2>; - ti,hwmods = "spi1"; -+ clocks = <&dpll_per_m2_div4_ck>; -+ clock-names = "fck"; -+ dmas = <&edma 42 -+ &edma 43 -+ &edma 44 -+ &edma 45>; -+ dma-names = "tx0", "rx0", "tx1", "rx1"; - status = "disabled"; - }; - -@@ -345,6 +485,8 @@ - #size-cells = <1>; - ti,hwmods = "usb_otg_hs"; - status = "disabled"; -+ clocks = <&usbotg_fck>; -+ clock-names = "fck"; - - ctrl_mod: control@44e10000 { - compatible = "ti,am335x-usb-ctrl-module"; -@@ -469,6 +611,8 @@ - compatible = "ti,am33xx-pwmss"; - reg = <0x48300000 0x10>; - ti,hwmods = "epwmss0"; -+ clocks = <&l4ls_gclk>; -+ clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; -@@ -481,6 +625,8 @@ - #pwm-cells = <3>; - reg = <0x48300100 0x80>; - ti,hwmods = "ecap0"; -+ clocks = <&l4ls_gclk>; -+ clock-names = "fck"; - status = "disabled"; - }; - -@@ -489,6 +635,8 @@ - #pwm-cells = <3>; - reg = <0x48300200 0x80>; - ti,hwmods = "ehrpwm0"; -+ clocks = <&l4ls_gclk>; -+ clock-names = "fck"; - status = "disabled"; - }; - }; -@@ -497,6 +645,8 @@ - compatible = "ti,am33xx-pwmss"; - reg = <0x48302000 0x10>; - ti,hwmods = "epwmss1"; -+ clocks = <&l4ls_gclk>; -+ clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; -@@ -509,6 +659,8 @@ - #pwm-cells = <3>; - reg = <0x48302100 0x80>; - ti,hwmods = "ecap1"; -+ clocks = <&l4ls_gclk>; -+ clock-names = "fck"; - status = "disabled"; - }; - -@@ -517,6 +669,8 @@ - #pwm-cells = <3>; - reg = <0x48302200 0x80>; - ti,hwmods = "ehrpwm1"; -+ clocks = <&l4ls_gclk>; -+ clock-names = "fck"; - status = "disabled"; - }; - }; -@@ -525,6 +679,8 @@ - compatible = "ti,am33xx-pwmss"; - reg = <0x48304000 0x10>; - ti,hwmods = "epwmss2"; -+ clocks = <&l4ls_gclk>; -+ clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; -@@ -537,6 +693,8 @@ - #pwm-cells = <3>; - reg = <0x48304100 0x80>; - ti,hwmods = "ecap2"; -+ clocks = <&l4ls_gclk>; -+ clock-names = "fck"; - status = "disabled"; - }; - -@@ -545,6 +703,8 @@ - #pwm-cells = <3>; - reg = <0x48304200 0x80>; - ti,hwmods = "ehrpwm2"; -+ clocks = <&l4ls_gclk>; -+ clock-names = "fck"; - status = "disabled"; - }; - }; -@@ -552,6 +712,8 @@ - mac: ethernet@4a100000 { - compatible = "ti,cpsw"; - ti,hwmods = "cpgmac0"; -+ clocks = <&cpsw_125mhz_gclk>; -+ clock-names = "fck"; - cpdma_channels = <8>; - ale_entries = <1024>; - bd_ram_size = <0x2000>; -@@ -581,6 +743,8 @@ - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "davinci_mdio"; -+ clocks = <&cpsw_125mhz_gclk>; -+ clock-names = "fck"; - bus_freq = <1000000>; - reg = <0x4a101000 0x100>; - }; -@@ -594,19 +758,33 @@ - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - }; -+ -+ phy_sel: cpsw-phy-sel@44e10650 { -+ compatible = "ti,am3352-cpsw-phy-sel"; -+ reg= <0x44e10650 0x4>; -+ reg-names = "gmii-sel"; -+ }; - }; - - ocmcram: ocmcram@40300000 { - compatible = "ti,am3352-ocmcram"; - reg = <0x40300000 0x10000>; - ti,hwmods = "ocmcram"; -+ clocks = <&l3_gclk>; -+ clock-names = "fck"; - }; - - wkup_m3: wkup_m3@44d00000 { - compatible = "ti,am3353-wkup-m3"; -- reg = <0x44d00000 0x4000 /* M3 UMEM */ -- 0x44d80000 0x2000>; /* M3 DMEM */ -+ reg = <0x44d00000 0x4000 -+ 0x44d80000 0x2000 -+ 0x44e11324 0x0024>; -+ reg-names = "m3_umem", "m3_dmem", "ipc_regs"; -+ interrupts = <78>; - ti,hwmods = "wkup_m3"; -+ ti,no-reset; -+ clocks = <&dpll_core_m4_div2_ck>; -+ clock-names = "fck"; - }; - - elm: elm@48080000 { -@@ -614,6 +792,8 @@ - reg = <0x48080000 0x2000>; - interrupts = <4>; - ti,hwmods = "elm"; -+ clocks = <&l4ls_gclk>; -+ clock-names = "fck"; - status = "disabled"; - }; - -@@ -623,6 +803,8 @@ - interrupt-parent = <&intc>; - interrupts = <16>; - ti,hwmods = "adc_tsc"; -+ clocks = <&adc_tsc_fck>; -+ clock-names = "fck"; - status = "disabled"; - - tsc { -@@ -637,6 +819,9 @@ - gpmc: gpmc@50000000 { - compatible = "ti,am3352-gpmc"; - ti,hwmods = "gpmc"; -+ ti,no-idle; -+ clocks = <&l3s_gclk>; -+ clock-names = "fck"; - reg = <0x50000000 0x2000>; - interrupts = <100>; - gpmc,num-cs = <7>; -@@ -645,5 +830,102 @@ - #size-cells = <1>; - status = "disabled"; - }; -+ -+ prcm: prcm@44e00000 { -+ compatible = "ti,am3352-prcm"; -+ reg = <0x44e00000 0x1300>; -+ #reset-cells = <1>; -+ }; -+ -+ sham: sham@53100000 { -+ compatible = "ti,omap4-sham"; -+ ti,hwmods = "sham"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x53100000 0x200>; -+ interrupt-parent = <&intc>; -+ interrupts = <109>; -+ dmas = <&edma 36>; -+ dma-names = "rx"; -+ clocks = <&l3_gclk>; -+ clock-names = "fck"; -+ }; -+ -+ aes: aes@53500000 { -+ compatible = "ti,omap4-aes"; -+ ti,hwmods = "aes"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x53500000 0xa0>; -+ interrupt-parent = <&intc>; -+ interrupts = <103>; -+ dmas = <&edma 6 -+ &edma 5>; -+ dma-names = "tx", "rx"; -+ clocks = <&aes0_fck>; -+ clock-names = "fck"; -+ }; -+ -+ rng: rng@48310000 { -+ compatible = "ti,omap4-rng"; -+ ti,hwmods = "rng"; -+ reg = <0x48310000 0x2000>; -+ interrupts = <111>; -+ clocks = <&rng_fck>; -+ clock-names = "fck"; -+ }; -+ -+ lcdc: lcdc@0x4830e000 { -+ compatible = "ti,am33xx-tilcdc"; -+ reg = <0x4830e000 0x1000>; -+ interrupt-parent = <&intc>; -+ interrupts = <36>; -+ clocks = <&lcd_gclk>; -+ clock-names = "fck"; -+ ti,hwmods = "lcdc"; -+ status = "disabled"; -+ }; -+ -+ mcasp0: mcasp@48038000 { -+ compatible = "ti,omap2-mcasp-audio"; -+ ti,hwmods = "mcasp0"; -+ reg = <0x48038000 0x2000>, -+ <0x46400000 0x400000>; -+ reg-names = "mpu", "dma"; -+ interrupts = <80 81>; -+ interrupts-names = "tx", "rx"; -+ status = "disabled"; -+ dmas = <&edma 8 -+ &edma 9>; -+ dma-names = "tx", "rx"; -+ }; -+ -+ mcasp1: mcasp@4803C000 { -+ compatible = "ti,omap2-mcasp-audio"; -+ ti,hwmods = "mcasp1"; -+ reg = <0x4803C000 0x2000>, -+ <0x46400000 0x400000>; -+ reg-names = "mpu", "dma"; -+ interrupts = <82 83>; -+ interrupts-names = "tx", "rx"; -+ status = "disabled"; -+ dmas = <&edma 10 -+ &edma 11>; -+ dma-names = "tx", "rx"; -+ }; -+ }; -+ -+ clocks { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ /include/ "am33xx-clocks.dtsi" - }; -+ -+ clockdomains { -+ clk_24mhz_clkdm: clk_24mhz_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&clkdiv32k_ick>; -+ }; -+ }; - }; ---- /dev/null -+++ b/arch/arm/boot/dts/am3517.dtsi -@@ -0,0 +1,116 @@ -+/* -+ * Device Tree Source for AM3517 SoC -+ * -+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ -+ * -+ * This file is licensed under the terms of the GNU General Public License -+ * version 2. This program is licensed "as is" without any warranty of any -+ * kind, whether express or implied. -+ */ -+ -+#include "omap3.dtsi" -+ -+/ { -+ cpus { -+ cpu@0 { -+ /* OMAP343x/OMAP35xx variants OPP1-5 */ -+ operating-points = < -+ /* kHz uV */ -+ 125000 975000 -+ 250000 1075000 -+ 500000 1200000 -+ 550000 1270000 -+ 600000 1350000 -+ >; -+ clock-latency = <300000>; /* From legacy driver */ -+ }; -+ }; -+ -+ clocks { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ /include/ "am35xx-clocks.dtsi" -+ /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" -+ }; -+ -+ clockdomains { -+ dss_clkdm: dss_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>; -+ }; -+ -+ usbhost_clkdm: usbhost_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&usbhost_48m_fck>, <&usbhost_ick>; -+ }; -+ -+ core_l4_clkdm: core_l4_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&mmchs1_ick>, <&mmchs2_ick>, <&hdq_fck>, -+ <&uart1_ick>, <&mcspi4_fck>, <&i2c3_fck>, -+ <&mcspi2_ick>, <&uart2_ick>, <&mcspi3_ick>, -+ <&i2c1_fck>, <&hdq_ick>, <&sha12_ick>, -+ <&mcbsp5_ick>, <&mcspi3_fck>, <&aes2_ick>, -+ <&mcspi1_ick>, <&uart2_fck>, <&mmchs2_fck>, -+ <&mmchs1_fck>, <&i2c3_ick>, <&mcspi1_fck>, -+ <&mcspi4_ick>, <&omapctrl_ick>, <&mcbsp1_ick>, -+ <&mcspi2_fck>, <&gpt10_ick>, <&i2c2_fck>, -+ <&i2c2_ick>, <&gpt11_ick>, <&i2c1_ick>, -+ <&uart1_fck>; -+ }; -+ -+ wkup_clkdm: wkup_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&wdt1_ick>, <&gpt12_ick>, <&gpio1_ick>, -+ <&gpt1_ick>, <&omap_32ksync_ick>, <&wdt2_ick>, -+ <&wdt2_fck>; -+ }; -+ -+ dpll4_clkdm: dpll4_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&dpll4_ck>; -+ }; -+ -+ core_l3_clkdm: core_l3_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&sdrc_ick>; -+ }; -+ -+ per_clkdm: per_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&gpt2_ick>, <&uart3_fck>, <&gpio3_ick>, -+ <&mcbsp2_ick>, <&gpt6_ick>, <&mcbsp4_ick>, -+ <&gpt4_ick>, <&mcbsp3_ick>, <&gpt8_ick>, -+ <&uart3_ick>, <&gpt5_ick>, <&gpt7_ick>, -+ <&gpio2_ick>, <&gpio6_ick>, <&gpt9_ick>, -+ <&gpt3_ick>, <&gpio5_ick>, <&wdt3_ick>, -+ <&gpio4_ick>, <&wdt3_fck>, <&uart4_ick>; -+ }; -+ -+ emu_clkdm: emu_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&emu_src_ck>; -+ }; -+ -+ sgx_clkdm: sgx_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&sgx_ick>; -+ }; -+ -+ dpll3_clkdm: dpll3_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&dpll3_ck>; -+ }; -+ -+ dpll5_clkdm: dpll5_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&dpll5_ck>; -+ }; -+ -+ dpll1_clkdm: dpll1_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&dpll1_ck>; -+ }; -+ }; -+}; ---- a/arch/arm/boot/dts/am3517-evm.dts -+++ b/arch/arm/boot/dts/am3517-evm.dts -@@ -7,7 +7,7 @@ - */ - /dts-v1/; - --#include "omap34xx.dtsi" -+#include "am3517.dtsi" - - / { - model = "TI AM3517 EVM (AM3517/05)"; ---- a/arch/arm/boot/dts/am3517_mt_ventoux.dts -+++ b/arch/arm/boot/dts/am3517_mt_ventoux.dts -@@ -7,7 +7,7 @@ - */ - /dts-v1/; - --#include "omap34xx.dtsi" -+#include "am3517.dtsi" - - / { - model = "TeeJet Mt.Ventoux"; ---- /dev/null -+++ b/arch/arm/boot/dts/am35xx-clocks.dtsi -@@ -0,0 +1,101 @@ -+/* -+ * Device Tree Source for AM35xx clock data -+ * -+ * Copyright (C) 2013 Texas Instruments, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+ipss_ick: ipss_ick@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,am35xx-interface-clock"; -+ clocks = <&core_l3_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <4>; -+}; -+ -+rmii_ck: rmii_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <50000000>; -+}; -+ -+pclk_ck: pclk_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <27000000>; -+}; -+ -+emac_ick: emac_ick@4800259c { -+ #clock-cells = <0>; -+ compatible = "ti,am35xx-gate-clock"; -+ clocks = <&ipss_ick>; -+ reg = <0x4800259c 0x4>; -+ ti,enable-bit = <1>; -+}; -+ -+emac_fck: emac_fck@4800259c { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&rmii_ck>; -+ reg = <0x4800259c 0x4>; -+ bit-shift = <9>; -+}; -+ -+vpfe_ick: vpfe_ick@4800259c { -+ #clock-cells = <0>; -+ compatible = "ti,am35xx-gate-clock"; -+ clocks = <&ipss_ick>; -+ reg = <0x4800259c 0x4>; -+ ti,enable-bit = <2>; -+}; -+ -+vpfe_fck: vpfe_fck@4800259c { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&pclk_ck>; -+ reg = <0x4800259c 0x4>; -+ bit-shift = <10>; -+}; -+ -+hsotgusb_ick: hsotgusb_ick@4800259c { -+ #clock-cells = <0>; -+ compatible = "ti,am35xx-gate-clock"; -+ clocks = <&ipss_ick>; -+ reg = <0x4800259c 0x4>; -+ ti,enable-bit = <0>; -+}; -+ -+hsotgusb_fck_am35xx: hsotgusb_fck_am35xx@4800259c { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_ck>; -+ reg = <0x4800259c 0x4>; -+ bit-shift = <8>; -+}; -+ -+hecc_ck: hecc_ck@4800259c { -+ #clock-cells = <0>; -+ compatible = "ti,am35xx-gate-clock"; -+ clocks = <&sys_ck>; -+ reg = <0x4800259c 0x4>; -+ ti,enable-bit = <3>; -+}; -+ -+uart4_ick_am35xx: uart4_ick_am35xx@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&core_l4_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <23>; -+}; -+ -+uart4_fck_am35xx: uart4_fck_am35xx@48004a00 { -+ #clock-cells = <0>; -+ compatible = "ti,gate-clock"; -+ clocks = <&core_48m_fck>; -+ reg = <0x48004a00 0x4>; -+ ti,enable-bit = <23>; -+}; ---- a/arch/arm/boot/dts/am4372.dtsi -+++ b/arch/arm/boot/dts/am4372.dtsi -@@ -8,6 +8,7 @@ - * kind, whether express or implied. - */ - -+#include - #include - - #include "skeleton.dtsi" -@@ -18,12 +19,21 @@ - - - aliases { -+ i2c0 = &i2c0; -+ i2c1 = &i2c1; -+ i2c2 = &i2c2; - serial0 = &uart0; -+ ethernet0 = &cpsw_emac0; -+ ethernet1 = &cpsw_emac1; - }; - - cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; - cpu@0 { - compatible = "arm,cortex-a9"; -+ device_type = "cpu"; -+ reg = <0>; - }; - }; - -@@ -35,16 +45,124 @@ - <0x48240100 0x0100>; - }; - -+ l2-cache-controller@48242000 { -+ compatible = "arm,pl310-cache"; -+ reg = <0x48242000 0x1000>; -+ cache-unified; -+ cache-level = <2>; -+ }; -+ -+ am43xx_pinmux: pinmux@44e10800 { -+ compatible = "pinctrl-single"; -+ reg = <0x44e10800 0x31c>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-single,register-width = <32>; -+ pinctrl-single,function-mask = <0xffffffff>; -+ }; -+ - ocp { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; -+ ti,hwmods = "l3_main"; -+ clocks = <&l3_gclk>; -+ clock-names = "fck"; -+ -+ edma: edma@49000000 { -+ compatible = "ti,edma3"; -+ ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; -+ reg = <0x49000000 0x10000>, -+ <0x44e10f90 0x10>; -+ interrupts = , -+ , -+ ; -+ #dma-cells = <1>; -+ dma-channels = <64>; -+ ti,edma-regions = <4>; -+ ti,edma-slots = <256>; -+ }; - - uart0: serial@44e09000 { - compatible = "ti,am4372-uart","ti,omap2-uart"; - reg = <0x44e09000 0x2000>; - interrupts = ; -+ ti,hwmods = "uart1"; -+ clocks = <&dpll_per_m2_div4_wkupdm_ck>; -+ clock-names = "fck"; -+ }; -+ -+ uart1: serial@48022000 { -+ compatible = "ti,am4372-uart","ti,omap2-uart"; -+ reg = <0x48022000 0x2000>; -+ interrupts = ; -+ ti,hwmods = "uart2"; -+ clocks = <&dpll_per_m2_div4_ck>; -+ clock-names = "fck"; -+ status = "disabled"; -+ }; -+ -+ uart2: serial@48024000 { -+ compatible = "ti,am4372-uart","ti,omap2-uart"; -+ reg = <0x48024000 0x2000>; -+ interrupts = ; -+ ti,hwmods = "uart3"; -+ clocks = <&dpll_per_m2_div4_ck>; -+ clock-names = "fck"; -+ status = "disabled"; -+ }; -+ -+ uart3: serial@481a6000 { -+ compatible = "ti,am4372-uart","ti,omap2-uart"; -+ reg = <0x481a6000 0x2000>; -+ interrupts = ; -+ ti,hwmods = "uart4"; -+ clocks = <&dpll_per_m2_div4_ck>; -+ clock-names = "fck"; -+ status = "disabled"; -+ }; -+ -+ uart4: serial@481a8000 { -+ compatible = "ti,am4372-uart","ti,omap2-uart"; -+ reg = <0x481a8000 0x2000>; -+ interrupts = ; -+ ti,hwmods = "uart5"; -+ clocks = <&dpll_per_m2_div4_ck>; -+ clock-names = "fck"; -+ status = "disabled"; -+ }; -+ -+ uart5: serial@481aa000 { -+ compatible = "ti,am4372-uart","ti,omap2-uart"; -+ reg = <0x481aa000 0x2000>; -+ interrupts = ; -+ ti,hwmods = "uart6"; -+ clocks = <&dpll_per_m2_div4_ck>; -+ clock-names = "fck"; -+ status = "disabled"; -+ }; -+ -+ mailbox: mailbox@480C8000 { -+ compatible = "ti,omap4-mailbox"; -+ reg = <0x480C8000 0x200>; -+ interrupts = ; -+ ti,hwmods = "mailbox"; -+ ti,mbox-num-users = <4>; -+ ti,mbox-num-fifos = <8>; -+ ti,mbox-names = "wkup_m3"; -+ ti,mbox-data = <0 0 0 0>; -+ }; -+ -+ qspi: qspi@47900000 { -+ compatible = "ti,am4372-qspi"; -+ reg = <0x47900000 0x100>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ ti,hwmods = "qspi"; -+ interrupts = <0 138 0x4>; -+ num-cs = <4>; -+ mmap_read; - }; - - timer1: timer@44e31000 { -@@ -52,17 +170,818 @@ - reg = <0x44e31000 0x400>; - interrupts = ; - ti,timer-alwon; -+ ti,hwmods = "timer1"; -+ clocks = <&timer1_fck>; -+ clock-names = "fck"; - }; - - timer2: timer@48040000 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x48040000 0x400>; - interrupts = ; -+ ti,hwmods = "timer2"; -+ clocks = <&timer2_fck>; -+ clock-names = "fck"; -+ }; -+ -+ timer3: timer@48042000 { -+ compatible = "ti,am4372-timer","ti,am335x-timer"; -+ reg = <0x48042000 0x400>; -+ interrupts = ; -+ ti,hwmods = "timer3"; -+ clocks = <&timer3_fck>; -+ clock-names = "fck"; -+ status = "disabled"; -+ }; -+ -+ timer4: timer@48044000 { -+ compatible = "ti,am4372-timer","ti,am335x-timer"; -+ reg = <0x48044000 0x400>; -+ interrupts = ; -+ ti,timer-pwm; -+ ti,hwmods = "timer4"; -+ clocks = <&timer4_fck>; -+ clock-names = "fck"; -+ status = "disabled"; -+ }; -+ -+ timer5: timer@48046000 { -+ compatible = "ti,am4372-timer","ti,am335x-timer"; -+ reg = <0x48046000 0x400>; -+ interrupts = ; -+ ti,timer-pwm; -+ ti,hwmods = "timer5"; -+ clocks = <&timer5_fck>; -+ clock-names = "fck"; -+ status = "disabled"; -+ }; -+ -+ timer6: timer@48048000 { -+ compatible = "ti,am4372-timer","ti,am335x-timer"; -+ reg = <0x48048000 0x400>; -+ interrupts = ; -+ ti,timer-pwm; -+ ti,hwmods = "timer6"; -+ clocks = <&timer6_fck>; -+ clock-names = "fck"; -+ status = "disabled"; -+ }; -+ -+ timer7: timer@4804a000 { -+ compatible = "ti,am4372-timer","ti,am335x-timer"; -+ reg = <0x4804a000 0x400>; -+ interrupts = ; -+ ti,timer-pwm; -+ ti,hwmods = "timer7"; -+ clocks = <&timer7_fck>; -+ clock-names = "fck"; -+ status = "disabled"; -+ }; -+ -+ timer8: timer@481c1000 { -+ compatible = "ti,am4372-timer","ti,am335x-timer"; -+ reg = <0x481c1000 0x400>; -+ interrupts = ; -+ ti,hwmods = "timer8"; -+ clocks = <&timer8_fck>; -+ clock-names = "fck"; -+ status = "disabled"; -+ }; -+ -+ timer9: timer@4833d000 { -+ compatible = "ti,am4372-timer","ti,am335x-timer"; -+ reg = <0x4833d000 0x400>; -+ interrupts = ; -+ ti,hwmods = "timer9"; -+ clocks = <&timer9_fck>; -+ clock-names = "fck"; -+ status = "disabled"; -+ }; -+ -+ timer10: timer@4833f000 { -+ compatible = "ti,am4372-timer","ti,am335x-timer"; -+ reg = <0x4833f000 0x400>; -+ interrupts = ; -+ ti,hwmods = "timer10"; -+ clocks = <&timer10_fck>; -+ clock-names = "fck"; -+ status = "disabled"; -+ }; -+ -+ timer11: timer@48341000 { -+ compatible = "ti,am4372-timer","ti,am335x-timer"; -+ reg = <0x48341000 0x400>; -+ interrupts = ; -+ ti,hwmods = "timer11"; -+ clocks = <&timer11_fck>; -+ clock-names = "fck"; -+ status = "disabled"; - }; - - counter32k: counter@44e86000 { - compatible = "ti,am4372-counter32k","ti,omap-counter32k"; - reg = <0x44e86000 0x40>; -+ ti,hwmods = "counter_32k"; -+ clocks = <&synctimer_32kclk>; -+ clock-names = "fck"; -+ }; -+ -+ rtc: rtc@44e3e000 { -+ compatible = "ti,am4372-rtc","ti,da830-rtc"; -+ reg = <0x44e3e000 0x1000>; -+ interrupts = ; -+ ti,hwmods = "rtc"; -+ clocks = <&clk_32768_ck>; -+ clock-names = "fck"; -+ status = "disabled"; -+ }; -+ -+ wdt@44e35000 { -+ compatible = "ti,am4372-wdt","ti,omap3-wdt"; -+ reg = <0x44e35000 0x1000>; -+ interrupts = ; -+ ti,hwmods = "wd_timer2"; -+ clocks = <&wdt1_fck>; -+ clock-names = "fck"; -+ }; -+ -+ gpio0: gpio@44e07000 { -+ compatible = "ti,am4372-gpio","ti,omap4-gpio"; -+ reg = <0x44e07000 0x1000>; -+ interrupts = ; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ ti,hwmods = "gpio1"; -+ clocks = <&sys_clkin_ck>, <&gpio0_dbclk>; -+ clock-names = "fck", "dbclk"; -+ status = "disabled"; -+ }; -+ -+ gpio1: gpio@4804c000 { -+ compatible = "ti,am4372-gpio","ti,omap4-gpio"; -+ reg = <0x4804c000 0x1000>; -+ interrupts = ; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ ti,hwmods = "gpio2"; -+ clocks = <&l4ls_gclk>, <&gpio1_dbclk>; -+ clock-names = "fck", "dbclk"; -+ status = "disabled"; -+ }; -+ -+ gpio2: gpio@481ac000 { -+ compatible = "ti,am4372-gpio","ti,omap4-gpio"; -+ reg = <0x481ac000 0x1000>; -+ interrupts = ; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ ti,hwmods = "gpio3"; -+ clocks = <&l4ls_gclk>, <&gpio2_dbclk>; -+ clock-names = "fck", "dbclk"; -+ status = "disabled"; -+ }; -+ -+ gpio3: gpio@481ae000 { -+ compatible = "ti,am4372-gpio","ti,omap4-gpio"; -+ reg = <0x481ae000 0x1000>; -+ interrupts = ; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ ti,hwmods = "gpio4"; -+ clocks = <&l4ls_gclk>, <&gpio3_dbclk>; -+ clock-names = "fck", "dbclk"; -+ status = "disabled"; -+ }; -+ -+ gpio4: gpio@48320000 { -+ compatible = "ti,am4372-gpio","ti,omap4-gpio"; -+ reg = <0x48320000 0x1000>; -+ interrupts = ; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ ti,hwmods = "gpio5"; -+ clocks = <&l4ls_gclk>, <&gpio4_dbclk>; -+ clock-names = "fck", "dbclk"; -+ status = "disabled"; -+ }; -+ -+ gpio5: gpio@48322000 { -+ compatible = "ti,am4372-gpio","ti,omap4-gpio"; -+ reg = <0x48322000 0x1000>; -+ interrupts = ; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ ti,hwmods = "gpio6"; -+ clocks = <&l4ls_gclk>, <&gpio5_dbclk>; -+ clock-names = "fck", "dbclk"; -+ status = "disabled"; -+ }; -+ -+ i2c0: i2c@44e0b000 { -+ compatible = "ti,am4372-i2c","ti,omap4-i2c"; -+ reg = <0x44e0b000 0x1000>; -+ interrupts = ; -+ ti,hwmods = "i2c1"; -+ clocks = <&dpll_per_m2_div4_wkupdm_ck>; -+ clock-names = "fck"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ tps: tps@24 { -+ reg = <0x24>; -+ }; -+ }; -+ -+ i2c1: i2c@4802a000 { -+ compatible = "ti,am4372-i2c","ti,omap4-i2c"; -+ reg = <0x4802a000 0x1000>; -+ interrupts = ; -+ ti,hwmods = "i2c2"; -+ clocks = <&dpll_per_m2_div4_ck>; -+ clock-names = "fck"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2c2: i2c@4819c000 { -+ compatible = "ti,am4372-i2c","ti,omap4-i2c"; -+ reg = <0x4819c000 0x1000>; -+ interrupts = ; -+ ti,hwmods = "i2c3"; -+ clocks = <&dpll_per_m2_div4_ck>; -+ clock-names = "fck"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ spi0: spi@48030000 { -+ compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; -+ reg = <0x48030000 0x400>; -+ interrupts = ; -+ ti,hwmods = "spi0"; -+ clocks = <&dpll_per_m2_div4_ck>; -+ clock-names = "fck"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; - }; -+ -+ mmc1: mmc@48060000 { -+ compatible = "ti,omap4-hsmmc"; -+ reg = <0x48060000 0x1000>; -+ ti,hwmods = "mmc1"; -+ clocks = <&mmc_clk>, <&clkdiv32k_ick>; -+ clock-names = "fck", "mmchsdb_fck"; -+ ti,dual-volt; -+ ti,needs-special-reset; -+ dmas = <&edma 24 -+ &edma 25>; -+ dma-names = "tx", "rx"; -+ interrupts = ; -+ status = "disabled"; -+ }; -+ -+ mmc2: mmc@481d8000 { -+ compatible = "ti,omap4-hsmmc"; -+ reg = <0x481d8000 0x1000>; -+ ti,hwmods = "mmc2"; -+ clocks = <&mmc_clk>, <&clkdiv32k_ick>; -+ clock-names = "fck", "mmchsdb_fck"; -+ ti,needs-special-reset; -+ dmas = <&edma 2 -+ &edma 3>; -+ dma-names = "tx", "rx"; -+ interrupts = ; -+ status = "disabled"; -+ }; -+ -+ mmc3: mmc@47810000 { -+ compatible = "ti,omap4-hsmmc"; -+ reg = <0x47810000 0x1000>; -+ ti,hwmods = "mmc3"; -+ clocks = <&mmc_clk>, <&clkdiv32k_ick>; -+ clock-names = "fck", "mmchsdb_fck"; -+ ti,needs-special-reset; -+ interrupts = ; -+ status = "disabled"; -+ }; -+ -+ spi1: spi@481a0000 { -+ compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; -+ reg = <0x481a0000 0x400>; -+ interrupts = ; -+ ti,hwmods = "spi1"; -+ clocks = <&dpll_per_m2_div4_ck>; -+ clock-names = "fck"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ spi2: spi@481a2000 { -+ compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; -+ reg = <0x481a2000 0x400>; -+ interrupts = ; -+ ti,hwmods = "spi2"; -+ clocks = <&dpll_per_m2_div4_ck>; -+ clock-names = "fck"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ spi3: spi@481a4000 { -+ compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; -+ reg = <0x481a4000 0x400>; -+ interrupts = ; -+ ti,hwmods = "spi3"; -+ clocks = <&dpll_per_m2_div4_ck>; -+ clock-names = "fck"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ spi4: spi@48345000 { -+ compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; -+ reg = <0x48345000 0x400>; -+ interrupts = ; -+ ti,hwmods = "spi4"; -+ clocks = <&dpll_per_m2_div4_ck>; -+ clock-names = "fck"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ mac: ethernet@4a100000 { -+ compatible = "ti,am4372-cpsw","ti,cpsw"; -+ reg = <0x4a100000 0x800 -+ 0x4a101200 0x100>; -+ interrupts = ; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ti,hwmods = "cpgmac0"; -+ clocks = <&cpsw_125mhz_gclk>; -+ clock-names = "fck"; -+ cpdma_channels = <8>; -+ ale_entries = <1024>; -+ bd_ram_size = <0x2000>; -+ no_bd_ram = <0>; -+ rx_descs = <64>; -+ mac_control = <0x20>; -+ slaves = <2>; -+ active_slave = <0>; -+ cpts_clock_mult = <0x80000000>; -+ cpts_clock_shift = <29>; -+ ranges; -+ status = "disabled"; -+ -+ davinci_mdio: mdio@4a101000 { -+ compatible = "ti,am4372-mdio","ti,davinci_mdio"; -+ reg = <0x4a101000 0x100>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ ti,hwmods = "davinci_mdio"; -+ clocks = <&cpsw_125mhz_gclk>; -+ clock-names = "fck"; -+ bus_freq = <1000000>; -+ status = "disabled"; -+ }; -+ -+ cpsw_emac0: slave@4a100200 { -+ /* Filled in by U-Boot */ -+ mac-address = [ 00 00 00 00 00 00 ]; -+ }; -+ -+ cpsw_emac1: slave@4a100300 { -+ /* Filled in by U-Boot */ -+ mac-address = [ 00 00 00 00 00 00 ]; -+ }; -+ -+ phy_sel: cpsw-phy-sel@44e10650 { -+ compatible = "ti,am3352-cpsw-phy-sel"; -+ reg= <0x44e10650 0x4>; -+ reg-names = "gmii-sel"; -+ }; -+ }; -+ -+ epwmss0: epwmss@48300000 { -+ compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; -+ reg = <0x48300000 0x10>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ ti,hwmods = "epwmss0"; -+ clocks = <&l4ls_gclk>; -+ clock-names = "fck"; -+ status = "disabled"; -+ -+ ecap0: ecap@48300100 { -+ compatible = "ti,am4372-ecap","ti,am33xx-ecap"; -+ reg = <0x48300100 0x80>; -+ ti,hwmods = "ecap0"; -+ clocks = <&l4ls_gclk>; -+ clock-names = "fck"; -+ status = "disabled"; -+ }; -+ -+ ehrpwm0: ehrpwm@48300200 { -+ compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; -+ reg = <0x48300200 0x80>; -+ ti,hwmods = "ehrpwm0"; -+ clocks = <&l4ls_gclk>; -+ clock-names = "fck"; -+ status = "disabled"; -+ }; -+ }; -+ -+ epwmss1: epwmss@48302000 { -+ compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; -+ reg = <0x48302000 0x10>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ ti,hwmods = "epwmss1"; -+ clocks = <&l4ls_gclk>; -+ clock-names = "fck"; -+ status = "disabled"; -+ -+ ecap1: ecap@48302100 { -+ compatible = "ti,am4372-ecap","ti,am33xx-ecap"; -+ reg = <0x48302100 0x80>; -+ ti,hwmods = "ecap1"; -+ clocks = <&l4ls_gclk>; -+ clock-names = "fck"; -+ status = "disabled"; -+ }; -+ -+ ehrpwm1: ehrpwm@48302200 { -+ compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; -+ reg = <0x48302200 0x80>; -+ ti,hwmods = "ehrpwm1"; -+ clocks = <&l4ls_gclk>; -+ clock-names = "fck"; -+ status = "disabled"; -+ }; -+ }; -+ -+ epwmss2: epwmss@48304000 { -+ compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; -+ reg = <0x48304000 0x10>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ ti,hwmods = "epwmss2"; -+ clocks = <&l4ls_gclk>; -+ clock-names = "fck"; -+ status = "disabled"; -+ -+ ecap2: ecap@48304100 { -+ compatible = "ti,am4372-ecap","ti,am33xx-ecap"; -+ reg = <0x48304100 0x80>; -+ ti,hwmods = "ecap2"; -+ clocks = <&l4ls_gclk>; -+ clock-names = "fck"; -+ status = "disabled"; -+ }; -+ -+ ehrpwm2: ehrpwm@48304200 { -+ compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; -+ reg = <0x48304200 0x80>; -+ ti,hwmods = "ehrpwm2"; -+ clocks = <&l4ls_gclk>; -+ clock-names = "fck"; -+ status = "disabled"; -+ }; -+ }; -+ -+ epwmss3: epwmss@48306000 { -+ compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; -+ reg = <0x48306000 0x10>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ ti,hwmods = "epwmss3"; -+ clocks = <&l4ls_gclk>; -+ clock-names = "fck"; -+ status = "disabled"; -+ -+ ehrpwm3: ehrpwm@48306200 { -+ compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; -+ reg = <0x48306200 0x80>; -+ ti,hwmods = "ehrpwm3"; -+ clocks = <&l4ls_gclk>; -+ clock-names = "fck"; -+ status = "disabled"; -+ }; -+ }; -+ -+ epwmss4: epwmss@48308000 { -+ compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; -+ reg = <0x48308000 0x10>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ ti,hwmods = "epwmss4"; -+ clocks = <&l4ls_gclk>; -+ clock-names = "fck"; -+ status = "disabled"; -+ -+ ehrpwm4: ehrpwm@48308200 { -+ compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; -+ reg = <0x48308200 0x80>; -+ ti,hwmods = "ehrpwm4"; -+ clocks = <&l4ls_gclk>; -+ clock-names = "fck"; -+ status = "disabled"; -+ }; -+ }; -+ -+ epwmss5: epwmss@4830a000 { -+ compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; -+ reg = <0x4830a000 0x10>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ ti,hwmods = "epwmss5"; -+ clocks = <&l4ls_gclk>; -+ clock-names = "fck"; -+ status = "disabled"; -+ -+ ehrpwm5: ehrpwm@4830a200 { -+ compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; -+ reg = <0x4830a200 0x80>; -+ ti,hwmods = "ehrpwm5"; -+ clocks = <&l4ls_gclk>; -+ clock-names = "fck"; -+ status = "disabled"; -+ }; -+ }; -+ -+ wkup_m3: wkup_m3@44d00000 { -+ compatible = "ti,am4372-wkup-m3","ti,am3353-wkup-m3"; -+ reg = <0x44d00000 0x4000 /* M3 UMEM */ -+ 0x44d80000 0x2000>; /* M3 DMEM */ -+ ti,hwmods = "wkup_m3"; -+ clocks = <&sys_clkin_ck>; -+ clock-names = "fck"; -+ status = "disabled"; -+ }; -+ -+ tscadc: tscadc@44e0d000 { -+ compatible = "ti,am4372-tscadc","ti,am3359-tscadc"; -+ reg = <0x44e0d000 0x1000>; -+ ti,hwmods = "adc_tsc"; -+ clocks = <&adc_tsc_fck>; -+ clock-names = "fck"; -+ status = "disabled"; -+ }; -+ -+ ocmcram: ocmcram@40300000 { -+ compatible = "ti,am4372-ocmcram","ti,am3352-ocmcram"; -+ reg = <0x40300000 0x40000>; -+ ti,hwmods = "ocmcram"; -+ clocks = <&l3_gclk>; -+ clock-names = "fck"; -+ status = "disabled"; -+ }; -+ -+ dcan0: d_can@481cc000 { -+ compatible = "bosch,d_can"; -+ ti,hwmods = "d_can0"; -+ clocks = <&dcan0_fck>; -+ clock-names = "fck"; -+ reg = <0x481cc000 0x2000 -+ 0x44e10644 0x4>; -+ status = "disabled"; -+ }; -+ -+ dcan1: d_can@481d0000 { -+ compatible = "bosch,d_can"; -+ ti,hwmods = "d_can1"; -+ clocks = <&dcan1_fck>; -+ clock-names = "fck"; -+ reg = <0x481d0000 0x2000 -+ 0x44e10644 0x4>; -+ status = "disabled"; -+ }; -+ -+ elm: elm@48080000 { -+ compatible = "ti,am4372-elm","ti,am3352-elm"; -+ reg = <0x48080000 0x2000>; -+ ti,hwmods = "elm"; -+ clocks = <&l4ls_gclk>; -+ clock-names = "fck"; -+ status = "disabled"; -+ }; -+ -+ gpmc: gpmc@50000000 { -+ compatible = "ti,am4372-gpmc","ti,am3352-gpmc"; -+ ti,hwmods = "gpmc"; -+ clocks = <&l3s_gclk>; -+ clock-names = "fck"; -+ reg = <0x50000000 0x2000>; -+ status = "disabled"; -+ }; -+ -+ prcm: prcm@44df0000 { -+ compatible = "ti,am4372-prcm"; -+ reg = <0x44df0000 0xa000>; -+ #reset-cells = <1>; -+ }; -+ -+ rng: rng@48310000 { -+ compatible = "ti,omap4-rng"; -+ ti,hwmods = "rng"; -+ reg = <0x48310000 0x2000>; -+ interrupts = ; -+ clocks = <&rng_fck>; -+ clock-names = "fck"; -+ }; -+ -+ sham: sham@53100000 { -+ compatible = "ti,omap5-sham"; -+ ti,hwmods = "sham"; -+ reg = <0x53100000 0x300>; -+ dmas = <&edma 36>; -+ dma-names = "rx"; -+ interrupts = ; -+ clocks = <&l3_gclk>; -+ clock-names = "fck"; -+ }; -+ -+ aes: aes@53501000 { -+ compatible = "ti,omap4-aes"; -+ ti,hwmods = "aes"; -+ reg = <0x53501000 0xa0>; -+ interrupts = ; -+ dmas = <&edma 6 -+ &edma 5>; -+ dma-names = "tx", "rx"; -+ clocks = <&aes0_fck>; -+ clock-names = "fck"; -+ }; -+ -+ des: des@53701000 { -+ compatible = "ti,omap4-des"; -+ ti,hwmods = "des"; -+ reg = <0x53701000 0xa0>; -+ interrupts = ; -+ dmas = <&edma 34 -+ &edma 33>; -+ dma-names = "tx", "rx"; -+ clocks = <&l3_gclk>; -+ clock-names = "fck"; -+ }; -+ -+ am43xx_control_usb2phy1: control-phy@44e10620 { -+ compatible = "ti,control-phy-am437usb2"; -+ reg = <0x44e10620 0x4>; -+ reg-names = "power"; -+ }; -+ -+ am43xx_control_usb2phy2: control-phy@0x44e10628 { -+ compatible = "ti,control-phy-am437usb2"; -+ reg = <0x44e10628 0x4>; -+ reg-names = "power"; -+ }; -+ -+ ocp2scp0: ocp2scp@483a8000 { -+ compatible = "ti,omap-ocp2scp"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ ti,hwmods = "ocp2scp0"; -+ -+ usb2_phy1: usb2phy1@483a8000 { -+ compatible = "ti,am437x-usb2"; -+ reg = <0x483a8000 0x8000>; -+ ctrl-module = <&am43xx_control_usb2phy1>; -+ clocks = <&clk_32768_ck>, -+ <&usb_otg_ss0_refclk960m>; -+ clock-names = "wkupclk", -+ "refclk"; -+ #phy-cells = <0>; -+ }; -+ -+ }; -+ -+ ocp2scp1: ocp2scp@483e8000 { -+ compatible = "ti,omap-ocp2scp"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ ti,hwmods = "ocp2scp1"; -+ -+ usb2_phy2: usb2phy2@483e8000 { -+ compatible = "ti,am437x-usb2"; -+ reg = <0x483e8000 0x8000>; -+ ctrl-module = <&am43xx_control_usb2phy2>; -+ clocks = <&clk_32768_ck>, -+ <&usb_otg_ss1_refclk960m>; -+ clock-names = "wkupclk", -+ "refclk"; -+ #phy-cells = <0>; -+ }; -+ -+ }; -+ -+ dwc3_1: omap_dwc3_1@48380000 { -+ compatible = "ti,am437x-dwc3"; -+ ti,hwmods = "usb_otg_ss0"; -+ reg = <0x48380000 0x10000>; -+ interrupts = ; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ utmi-mode = <1>; -+ ranges; -+ usb1: usb@48390000 { -+ compatible = "synopsys,dwc3"; -+ reg = <0x48390000 0x17000>; -+ interrupts = ; -+ phys = <&usb2_phy1>; -+ phy-names = "usb2-phy"; -+ maximum-speed = "high-speed"; -+ dr_mode = "peripheral"; -+ }; -+ }; -+ -+ dwc3_2: omap_dwc3_2@483c0000 { -+ compatible = "ti,am437x-dwc3"; -+ ti,hwmods = "usb_otg_ss1"; -+ reg = <0x483c0000 0x10000>; -+ interrupts = ; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ utmi-mode = <1>; -+ ranges; -+ usb2: usb@483d0000 { -+ compatible = "synopsys,dwc3"; -+ reg = <0x483d0000 0x17000>; -+ interrupts = ; -+ phys = <&usb2_phy2>; -+ phy-names = "usb2-phy"; -+ maximum-speed = "high-speed"; -+ dr_mode = "host"; -+ }; -+ }; -+ -+ dss: dss@4832A000 { -+ compatible = "ti,omap3-dss", "simple-bus"; -+ reg = <0x4832A000 0x200>; -+ ti,hwmods = "dss_core"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ dispc@4832A400 { -+ compatible = "ti,omap3-dispc"; -+ reg = <0x4832A400 0x400>; -+ interrupts = ; -+ ti,hwmods = "dss_dispc"; -+ }; -+ -+ dpi: encoder@0 { -+ compatible = "ti,omap3-dpi"; -+ }; -+ -+ rfbi: rfbi@4832A800 { -+ compatible = "ti,omap3-rfbi"; -+ reg = <0x4832A800 0x100>; -+ ti,hwmods = "dss_rfbi"; -+ }; -+ -+ }; -+ - }; -+ -+ clocks { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ /include/ "am43xx-clocks.dtsi" -+ }; -+ - }; -+ -+/include/ "tps65218.dtsi" ---- /dev/null -+++ b/arch/arm/boot/dts/am437x-gp-evm.dts -@@ -0,0 +1,238 @@ -+/* -+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+/* AM437x GP EVM */ -+ -+/dts-v1/; -+ -+#include "am43x-common-evm.dtsi" -+#include -+ -+/ { -+ model = "TI AM437x gp EVM"; -+ compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43"; -+ -+ vmmcsd_fixed: fixedregulator-sd { -+ compatible = "regulator-fixed"; -+ regulator-name = "vmmcsd_fixed"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ enable-active-high; -+ }; -+ -+ aliases { -+ display0 = &lcd0; -+ display1 = &hdmi0; -+ }; -+ -+ lcd0: display@0 { -+ compatible = "osddisplays,osd057T0559-34ts", "panel-dpi"; -+ video-source = <&dpi>; -+ data-lines = <24>; -+ gpios = <0 /* No Enable GPIO */ -+ &gpio0 7 GPIO_ACTIVE_LOW>; /* LCD backlight GPIO */ -+ activelow_backlight; /* LCD backlight is Active low */ -+ panel-timing { -+ clock-frequency = <33000000>; -+ hactive = <800>; -+ vactive = <480>; -+ hfront-porch = <210>; -+ hback-porch = <16>; -+ hsync-len = <30>; -+ vback-porch = <10>; -+ vfront-porch = <22>; -+ vsync-len = <13>; -+ hsync-active = <0>; -+ vsync-active = <0>; -+ de-active = <1>; -+ pixelclk-active = <1>; -+ }; -+ }; -+ -+ hdmi0: connector@1 { -+ compatible = "ti,hdmi_connector"; -+ video-source = <&sii9022>; -+ }; -+}; -+ -+&am43xx_pinmux { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&dss_pinctrl>; -+ cpsw_default: cpsw_default { -+ pinctrl-single,pins = < -+ /* Slave 1 */ -+ 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */ -+ 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */ -+ 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */ -+ 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */ -+ 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */ -+ 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */ -+ 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ -+ 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ -+ 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */ -+ 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */ -+ 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */ -+ 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */ -+ >; -+ }; -+ -+ cpsw_sleep: cpsw_sleep { -+ pinctrl-single,pins = < -+ /* Slave 1 reset value */ -+ 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ >; -+ }; -+ -+ davinci_mdio_default: davinci_mdio_default { -+ pinctrl-single,pins = < -+ /* MDIO */ -+ 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ -+ 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ -+ >; -+ }; -+ -+ davinci_mdio_sleep: davinci_mdio_sleep { -+ pinctrl-single,pins = < -+ /* MDIO reset value */ -+ 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ >; -+ }; -+ -+ mmc1_pins: pinmux_mmc1_pins { -+ pinctrl-single,pins = < -+ 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ -+ >; -+ }; -+ -+ i2c0_pins: pinmux_i2c0_pins { -+ pinctrl-single,pins = < -+ 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ -+ 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ -+ >; -+ }; -+ -+ i2c1_pins: i2c1_pins { -+ pinctrl-single,pins = < -+ 0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ -+ 0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ -+ >; -+ }; -+ -+ dss_pinctrl: dss_pinctrl { -+ pinctrl-single,pins = < -+ 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ -+ 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1) -+ 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1) -+ 0x02C (PIN_OUTPUT_PULLUP | MUX_MODE1) -+ 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1) -+ 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1) -+ 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1) -+ 0x03C (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */ -+ 0x0A0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ -+ 0x0A4 (PIN_OUTPUT_PULLUP | MUX_MODE0) -+ 0x0A8 (PIN_OUTPUT_PULLUP | MUX_MODE0) -+ 0x0AC (PIN_OUTPUT_PULLUP | MUX_MODE0) -+ 0x0B0 (PIN_OUTPUT_PULLUP | MUX_MODE0) -+ 0x0B4 (PIN_OUTPUT_PULLUP | MUX_MODE0) -+ 0x0B8 (PIN_OUTPUT_PULLUP | MUX_MODE0) -+ 0x0BC (PIN_OUTPUT_PULLUP | MUX_MODE0) -+ 0x0C0 (PIN_OUTPUT_PULLUP | MUX_MODE0) -+ 0x0C4 (PIN_OUTPUT_PULLUP | MUX_MODE0) -+ 0x0C8 (PIN_OUTPUT_PULLUP | MUX_MODE0) -+ 0x0CC (PIN_OUTPUT_PULLUP | MUX_MODE0) -+ 0x0D0 (PIN_OUTPUT_PULLUP | MUX_MODE0) -+ 0x0D4 (PIN_OUTPUT_PULLUP | MUX_MODE0) -+ 0x0D8 (PIN_OUTPUT_PULLUP | MUX_MODE0) -+ 0x0DC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ -+ 0x0E0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ -+ 0x0E4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ -+ 0x0E8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ -+ 0x0EC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ -+ 0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* GPIO 5_8 to select LCD / HDMI */ -+ 0x164 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* ECAP0_IN_PWM0_OUT -> GPIO 0_7 BACKLIGHT */ -+ >; -+ }; -+}; -+ -+&rtc { -+ status = "okay"; -+}; -+ -+&gpio0 { -+ status = "okay"; -+}; -+ -+&gpio5 { -+ status = "okay"; -+}; -+ -+&mac { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&cpsw_default>; -+ pinctrl-1 = <&cpsw_sleep>; -+ status = "okay"; -+}; -+ -+&davinci_mdio { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&davinci_mdio_default>; -+ pinctrl-1 = <&davinci_mdio_sleep>; -+ status = "okay"; -+}; -+ -+&cpsw_emac0 { -+ phy_id = <&davinci_mdio>, <0>; -+ phy-mode = "rgmii"; -+}; -+ -+&cpsw_emac1 { -+ phy_id = <&davinci_mdio>, <1>; -+ phy-mode = "rgmii"; -+}; -+ -+&mmc1 { -+ status = "okay"; -+ vmmc-supply = <&vmmcsd_fixed>; -+ bus-width = <4>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc1_pins>; -+ cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; -+}; -+ -+&i2c1 { -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins>; -+ -+ sii9022: sii9022@3b { -+ compatible = "sii,sii9022"; -+ reg = <0x3b>; -+ reset-gpio = <&gpio5 8 GPIO_ACTIVE_LOW>;/* 'SelLCDorHDMI' Gpio, LOW to select HDMI */ -+ video-source = <&dpi>; -+ data-lines = <24>; -+ }; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/am43x-common-evm.dtsi -@@ -0,0 +1,9 @@ -+/* -+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include "am4372.dtsi" ---- a/arch/arm/boot/dts/am43x-epos-evm.dts -+++ b/arch/arm/boot/dts/am43x-epos-evm.dts -@@ -10,9 +10,289 @@ - - /dts-v1/; - --#include "am4372.dtsi" -+#include "am43x-common-evm.dtsi" -+#include - - / { - model = "TI AM43x EPOS EVM"; - compatible = "ti,am43x-epos-evm","ti,am4372","ti,am43"; -+ -+ vmmcsd_fixed: fixedregulator-sd { -+ compatible = "regulator-fixed"; -+ regulator-name = "vmmcsd_fixed"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ enable-active-high; -+ }; -+ -+ aliases { -+ display0 = &lcd0; -+ display1 = &hdmi0; -+ }; -+ -+ lcd0: display@0 { -+ compatible = "osddisplays,osd057T0559-34ts", "panel-dpi"; -+ video-source = <&dpi>; -+ data-lines = <24>; -+ gpios = <0 /* No Enable GPIO */ -+ &gpio0 7 GPIO_ACTIVE_LOW>; /* LCD backlight GPIO */ -+ panel-timing { -+ clock-frequency = <33000000>; -+ hactive = <800>; -+ vactive = <480>; -+ hfront-porch = <210>; -+ hback-porch = <16>; -+ hsync-len = <30>; -+ vback-porch = <10>; -+ vfront-porch = <22>; -+ vsync-len = <13>; -+ hsync-active = <0>; -+ vsync-active = <0>; -+ de-active = <1>; -+ pixelclk-active = <1>; -+ }; -+ }; -+ -+ hdmi0: connector@1 { -+ compatible = "ti,hdmi_connector"; -+ video-source = <&sii9022>; -+ }; -+}; -+ -+&am43xx_pinmux { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&dss_pinctrl>; -+ cpsw_default: cpsw_default { -+ pinctrl-single,pins = < -+ /* Slave 1 */ -+ 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ -+ 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ -+ 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ -+ 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */ -+ 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ -+ 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ -+ 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ -+ 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ -+ 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */ -+ >; -+ }; -+ -+ cpsw_sleep: cpsw_sleep { -+ pinctrl-single,pins = < -+ /* Slave 1 reset value */ -+ 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ >; -+ }; -+ -+ davinci_mdio_default: davinci_mdio_default { -+ pinctrl-single,pins = < -+ /* MDIO */ -+ 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ -+ 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ -+ >; -+ }; -+ -+ davinci_mdio_sleep: davinci_mdio_sleep { -+ pinctrl-single,pins = < -+ /* MDIO reset value */ -+ 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) -+ >; -+ }; -+ -+ mmc1_pins: pinmux_mmc1_pins { -+ pinctrl-single,pins = < -+ 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ -+ >; -+ }; -+ -+ i2c0_pins: pinmux_i2c0_pins { -+ pinctrl-single,pins = < -+ 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ -+ 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ -+ >; -+ }; -+ -+ i2c2_pins: pinmux_i2c2_pins { -+ pinctrl-single,pins = < -+ 0x1c0 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c2_sda.i2c2_sda */ -+ 0x1c4 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c2_scl.i2c2_scl */ -+ >; -+ }; -+ -+ spi0_pins: pinmux_spi0_pins { -+ pinctrl-single,pins = < -+ 0x150 (PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */ -+ 0x154 (PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ -+ 0x158 (PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */ -+ 0x15c (PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ -+ >; -+ }; -+ -+ spi1_pins: pinmux_spi1_pins { -+ pinctrl-single,pins = < -+ 0x190 (PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */ -+ 0x194 (PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ -+ 0x198 (PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ -+ 0x19c (PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ -+ >; -+ }; -+ -+ pixcir_ts_pins: pixcir_ts_pins { -+ pinctrl-single,pins = < -+ 0x48 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ -+ >; -+ }; -+ -+ dss_pinctrl: dss_pinctrl { -+ pinctrl-single,pins = < -+ 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ -+ 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1) -+ 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1) -+ 0x02C (PIN_OUTPUT_PULLUP | MUX_MODE1) -+ 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1) -+ 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1) -+ 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1) -+ 0x03C (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */ -+ 0x0A0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ -+ 0x0A4 (PIN_OUTPUT_PULLUP | MUX_MODE0) -+ 0x0A8 (PIN_OUTPUT_PULLUP | MUX_MODE0) -+ 0x0AC (PIN_OUTPUT_PULLUP | MUX_MODE0) -+ 0x0B0 (PIN_OUTPUT_PULLUP | MUX_MODE0) -+ 0x0B4 (PIN_OUTPUT_PULLUP | MUX_MODE0) -+ 0x0B8 (PIN_OUTPUT_PULLUP | MUX_MODE0) -+ 0x0BC (PIN_OUTPUT_PULLUP | MUX_MODE0) -+ 0x0C0 (PIN_OUTPUT_PULLUP | MUX_MODE0) -+ 0x0C4 (PIN_OUTPUT_PULLUP | MUX_MODE0) -+ 0x0C8 (PIN_OUTPUT_PULLUP | MUX_MODE0) -+ 0x0CC (PIN_OUTPUT_PULLUP | MUX_MODE0) -+ 0x0D0 (PIN_OUTPUT_PULLUP | MUX_MODE0) -+ 0x0D4 (PIN_OUTPUT_PULLUP | MUX_MODE0) -+ 0x0D8 (PIN_OUTPUT_PULLUP | MUX_MODE0) -+ 0x0DC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ -+ 0x0E0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ -+ 0x0E4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ -+ 0x0E8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ -+ 0x0EC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ -+ 0x08C (PIN_OUTPUT_PULLUP | MUX_MODE7) /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */ -+ 0x164 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* ECAP0_IN_PWM0_OUT -> GPIO 0_7 BACKLIGHT */ -+ >; -+ }; -+}; -+ -+&gpio0 { -+ status = "okay"; -+}; -+ -+&gpio1 { -+ status = "okay"; -+}; -+ -+&gpio2 { -+ status = "okay"; -+}; -+ -+&qspi { -+ spi-max-frequency = <48000000>; -+ m25p80@0 { -+ compatible = "mx66l51235l"; -+ spi-max-frequency = <48000000>; -+ reg = <0>; -+ spi-cpol; -+ spi-cpha; -+ tx-nbits = <1>; -+ rx-nbits = <4>; -+ }; -+}; -+ -+&mac { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&cpsw_default>; -+ pinctrl-1 = <&cpsw_sleep>; -+ status = "okay"; -+}; -+ -+&davinci_mdio { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&davinci_mdio_default>; -+ pinctrl-1 = <&davinci_mdio_sleep>; -+ status = "okay"; -+}; -+ -+&cpsw_emac0 { -+ phy_id = <&davinci_mdio>, <16>; -+ phy-mode = "rmii"; -+}; -+ -+&cpsw_emac1 { -+ phy_id = <&davinci_mdio>, <1>; -+ phy-mode = "rmii"; -+}; -+ -+&phy_sel { -+ rmii-clock-ext; -+}; -+ -+&mmc1 { -+ status = "okay"; -+ vmmc-supply = <&vmmcsd_fixed>; -+ bus-width = <4>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc1_pins>; -+ cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; -+}; -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; -+ status = "okay"; -+ clock-frequency = <400000>; -+ -+ pixcir_ts@5c { -+ compatible = "pixcir,pixcir_tangoc"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pixcir_ts_pins>; -+ reg = <0x5c>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <17 0>; -+ -+ attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; -+ -+ x-size = <1024>; -+ y-size = <600>; -+ }; -+}; -+ -+&i2c2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c2_pins>; -+ status = "okay"; -+ -+ sii9022: sii9022@3b { -+ compatible = "sii,sii9022"; -+ reg = <0x3b>; -+ reset-gpio = <&gpio2 1 GPIO_ACTIVE_LOW>;/* 65'SelLCDorHDMI' Gpio, LOW to select HDMI */ -+ video-source = <&dpi>; -+ data-lines = <24>; -+ }; -+}; -+ -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins>; -+ status = "okay"; -+}; -+ -+&spi1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi1_pins>; -+ status = "okay"; - }; ---- /dev/null -+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi -@@ -0,0 +1,735 @@ -+/* -+ * Device Tree Source for AM43xx clock data -+ * -+ * Copyright (C) 2013 Texas Instruments, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+clk_32768_ck: clk_32768_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <32768>; -+}; -+ -+clk_rc32k_ck: clk_rc32k_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <32768>; -+}; -+ -+virt_19200000_ck: virt_19200000_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <19200000>; -+}; -+ -+virt_24000000_ck: virt_24000000_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <24000000>; -+}; -+ -+virt_25000000_ck: virt_25000000_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <25000000>; -+}; -+ -+virt_26000000_ck: virt_26000000_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <26000000>; -+}; -+ -+crystal_freq_sel_ck: crystal_freq_sel_ck@44e10040 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; -+ bit-shift = <29>; -+ reg = <0x44e10040 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; -+ bit-shift = <22>; -+ reg = <0x44e10040 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+sys_clkin_ck: sys_clkin_ck@44e10040 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>; -+ bit-shift = <31>; -+ reg = <0x44e10040 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+tclkin_ck: tclkin_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <26000000>; -+}; -+ -+dpll_core_ck: dpll_core_ck@44df2d20 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-core-clock"; -+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; -+ reg = <0x44df2d20 0x4>, <0x44df2d24 0x4>, <0x44df2d2c 0x4>; -+ reg-names = "control", "idlest", "mult-div1"; -+}; -+ -+dpll_core_x2_ck: dpll_core_x2_ck { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-x2-clock"; -+ clocks = <&dpll_core_ck>; -+}; -+ -+dpll_core_m4_ck: dpll_core_m4_ck@44df2d38 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_core_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x44df2d38 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_core_m5_ck: dpll_core_m5_ck@44df2d3c { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_core_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x44df2d3c 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_core_m6_ck: dpll_core_m6_ck@44df2d40 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_core_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x44df2d40 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_mpu_ck: dpll_mpu_ck@44df2d60 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-clock"; -+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; -+ reg = <0x44df2d60 0x4>, <0x44df2d64 0x4>, <0x44df2d6c 0x4>; -+ reg-names = "control", "idlest", "mult-div1"; -+}; -+ -+dpll_mpu_m2_ck: dpll_mpu_m2_ck@44df2d70 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_mpu_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x44df2d70 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_ddr_ck: dpll_ddr_ck@44df2da0 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-clock"; -+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; -+ reg = <0x44df2da0 0x4>, <0x44df2da4 0x4>, <0x44df2dac 0x4>; -+ reg-names = "control", "idlest", "mult-div1"; -+}; -+ -+dpll_ddr_m2_ck: dpll_ddr_m2_ck@44df2db0 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_ddr_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x44df2db0 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_disp_ck: dpll_disp_ck@44df2e20 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-clock"; -+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; -+ reg = <0x44df2e20 0x4>, <0x44df2e24 0x4>, <0x44df2e2c 0x4>; -+ reg-names = "control", "idlest", "mult-div1"; -+}; -+ -+dpll_disp_m2_ck: dpll_disp_m2_ck@44df2e30 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_disp_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x44df2e30 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_per_ck: dpll_per_ck@44df2de0 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-j-type-clock"; -+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; -+ reg = <0x44df2de0 0x4>, <0x44df2de4 0x4>, <0x44df2dec 0x4>; -+ reg-names = "control", "idlest", "mult-div1"; -+}; -+ -+dpll_per_m2_ck: dpll_per_m2_ck@44df2df0 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_per_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x44df2df0 0x4>; -+ bit-mask = <0x7f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_per_m2_ck>; -+ clock-mult = <1>; -+ clock-div = <4>; -+}; -+ -+dpll_per_m2_div4_ck: dpll_per_m2_div4_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_per_m2_ck>; -+ clock-mult = <1>; -+ clock-div = <4>; -+}; -+ -+adc_tsc_fck: adc_tsc_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&sys_clkin_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+clk_24mhz: clk_24mhz { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_per_m2_ck>; -+ clock-mult = <1>; -+ clock-div = <8>; -+}; -+ -+clkdiv32k_ck: clkdiv32k_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&clk_24mhz>; -+ clock-mult = <1>; -+ clock-div = <732>; -+}; -+ -+clkdiv32k_ick: clkdiv32k_ick@44df2a38 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&clkdiv32k_ck>; -+ bit-shift = <8>; -+ reg = <0x44df2a38 0x4>; -+}; -+ -+dcan0_fck: dcan0_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&sys_clkin_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+dcan1_fck: dcan1_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&sys_clkin_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+sysclk_div: sysclk_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_core_m4_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+pruss_ocp_gclk: pruss_ocp_gclk@44df4248 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sysclk_div>, <&dpll_disp_m2_ck>; -+ reg = <0x44df4248 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+mcasp0_fck: mcasp0_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&sys_clkin_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+mcasp1_fck: mcasp1_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&sys_clkin_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+smartreflex0_fck: smartreflex0_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&sys_clkin_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+smartreflex1_fck: smartreflex1_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&sys_clkin_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+sha0_fck: sha0_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&sys_clkin_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+rng_fck: rng_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&sys_clkin_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+aes0_fck: aes0_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&sys_clkin_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+clk_32k_tpm_ck: clk_32k_tpm_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <32768>; -+}; -+ -+timer1_fck: timer1_fck@44df4200 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>; -+ reg = <0x44df4200 0x4>; -+ bit-mask = <0x7>; -+}; -+ -+timer2_fck: timer2_fck@44df4204 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; -+ reg = <0x44df4204 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+timer3_fck: timer3_fck@44df4208 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; -+ reg = <0x44df4208 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+timer4_fck: timer4_fck@44df420c { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; -+ reg = <0x44df420c 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+timer5_fck: timer5_fck@44df4210 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; -+ reg = <0x44df4210 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+timer6_fck: timer6_fck@44df4214 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; -+ reg = <0x44df4214 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+timer7_fck: timer7_fck@44df4218 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; -+ reg = <0x44df4218 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+wdt1_fck: wdt1_fck@44df422c { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>; -+ reg = <0x44df422c 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+l3_gclk: l3_gclk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_core_m4_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+dpll_core_m4_div2_ck: dpll_core_m4_div2_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&sysclk_div>; -+ clock-mult = <1>; -+ clock-div = <2>; -+}; -+ -+l4hs_gclk: l4hs_gclk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_core_m4_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+l3s_gclk: l3s_gclk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_core_m4_div2_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+l4ls_gclk: l4ls_gclk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_core_m4_div2_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+cpsw_125mhz_gclk: cpsw_125mhz_gclk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_core_m5_ck>; -+ clock-mult = <1>; -+ clock-div = <2>; -+}; -+ -+cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@44df4238 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>; -+ reg = <0x44df4238 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+clk_32k_mosc_ck: clk_32k_mosc_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <32768>; -+}; -+ -+gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@44df4240 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>; -+ reg = <0x44df4240 0x4>; -+ bit-mask = <0x7>; -+}; -+ -+gpio0_dbclk: gpio0_dbclk@44df2b68 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&gpio0_dbclk_mux_ck>; -+ bit-shift = <8>; -+ reg = <0x44df2b68 0x4>; -+}; -+ -+gpio1_dbclk: gpio1_dbclk@44df8c78 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&clkdiv32k_ick>; -+ bit-shift = <8>; -+ reg = <0x44df8c78 0x4>; -+}; -+ -+gpio2_dbclk: gpio2_dbclk@44df8c80 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&clkdiv32k_ick>; -+ bit-shift = <8>; -+ reg = <0x44df8c80 0x4>; -+}; -+ -+gpio3_dbclk: gpio3_dbclk@44df8c88 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&clkdiv32k_ick>; -+ bit-shift = <8>; -+ reg = <0x44df8c88 0x4>; -+}; -+ -+gpio4_dbclk: gpio4_dbclk@44df8c90 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&clkdiv32k_ick>; -+ bit-shift = <8>; -+ reg = <0x44df8c90 0x4>; -+}; -+ -+gpio5_dbclk: gpio5_dbclk@44df8c98 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&clkdiv32k_ick>; -+ bit-shift = <8>; -+ reg = <0x44df8c98 0x4>; -+}; -+ -+mmc_clk: mmc_clk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_per_m2_ck>; -+ clock-mult = <1>; -+ clock-div = <2>; -+}; -+ -+gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@44df423c { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sysclk_div>, <&dpll_per_m2_ck>; -+ bit-shift = <1>; -+ reg = <0x44df423c 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+gfx_fck_div_ck: gfx_fck_div_ck@44df423c { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&gfx_fclk_clksel_ck>; -+ reg = <0x44df423c 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+disp_clk: disp_clk@44df4244 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; -+ reg = <0x44df4244 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+dpll_extdev_ck: dpll_extdev_ck@44df2e60 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-clock"; -+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; -+ reg = <0x44df2e60 0x4>, <0x44df2e64 0x4>, <0x44df2e6c 0x4>; -+ reg-names = "control", "idlest", "mult-div1"; -+}; -+ -+dpll_extdev_m2_ck: dpll_extdev_m2_ck@44df2e70 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_extdev_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x44df2e70 0x4>; -+ bit-mask = <0x7f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+mux_synctimer32k_ck: mux_synctimer32k_ck@44df4230 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>; -+ reg = <0x44df4230 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+synctimer_32kclk: synctimer_32kclk@44df2a30 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&mux_synctimer32k_ck>; -+ bit-shift = <8>; -+ reg = <0x44df2a30 0x4>; -+}; -+ -+timer8_fck: timer8_fck@44df421c { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; -+ reg = <0x44df421c 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+timer9_fck: timer9_fck@44df4220 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; -+ reg = <0x44df4220 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+timer10_fck: timer10_fck@44df4224 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; -+ reg = <0x44df4224 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+timer11_fck: timer11_fck@44df4228 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; -+ reg = <0x44df4228 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+cpsw_50m_clkdiv: cpsw_50m_clkdiv { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_core_m5_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+cpsw_5m_clkdiv: cpsw_5m_clkdiv { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&cpsw_50m_clkdiv>; -+ clock-mult = <1>; -+ clock-div = <10>; -+}; -+ -+dpll_ddr_x2_ck: dpll_ddr_x2_ck { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-x2-clock"; -+ clocks = <&dpll_ddr_ck>; -+}; -+ -+dpll_ddr_m4_ck: dpll_ddr_m4_ck@44df2db8 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_ddr_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x44df2db8 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_per_clkdcoldo: dpll_per_clkdcoldo { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_per_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+dll_aging_clk_div: dll_aging_clk_div@44df4250 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&sys_clkin_ck>; -+ reg = <0x44df4250 0x4>; -+ table = < 8 0 >, < 16 1 >, < 32 2 >; -+ bit-mask = <0x3>; -+}; -+ -+div_core_25m_ck: div_core_25m_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&sysclk_div>; -+ clock-mult = <1>; -+ clock-div = <8>; -+}; -+ -+func_12m_clk: func_12m_clk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_per_m2_ck>; -+ clock-mult = <1>; -+ clock-div = <16>; -+}; -+ -+vtp_clk_div: vtp_clk_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&sys_clkin_ck>; -+ clock-mult = <1>; -+ clock-div = <2>; -+}; -+ -+usbphy_32khz_clkmux: usbphy_32khz_clkmux@44df4260 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>; -+ reg = <0x44df4260 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m@44df8a60 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dpll_per_clkdcoldo>; -+ bit-shift = <8>; -+ reg = <0x44df8a60 0x4>; -+}; -+ -+usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@44df8a68 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dpll_per_clkdcoldo>; -+ bit-shift = <8>; -+ reg = <0x44df8a68 0x4>; -+}; -+ -+usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clocks = <&clk_32768_ck>; -+}; -+ -+usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clocks = <&clk_32768_ck>; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/dra7.dtsi -@@ -0,0 +1,1278 @@ -+/* -+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * Based on "omap4.dtsi" -+ */ -+ -+#include -+ -+#include "skeleton.dtsi" -+ -+/ { -+ compatible = "ti,dra7xx"; -+ interrupt-parent = <&gic>; -+ -+ aliases { -+ i2c0 = &i2c1; -+ i2c1 = &i2c2; -+ i2c2 = &i2c3; -+ i2c3 = &i2c4; -+ i2c4 = &i2c5; -+ serial0 = &uart1; -+ serial1 = &uart2; -+ serial2 = &uart3; -+ serial3 = &uart4; -+ serial4 = &uart5; -+ serial5 = &uart6; -+ ethernet0 = &cpsw_emac0; -+ ethernet1 = &cpsw_emac1; -+ }; -+ -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ cpu0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a15"; -+ reg = <0>; -+ -+ operating-points = < -+ /* kHz uV */ -+ 1000000 1090000 -+ 1176000 1210000 -+ >; -+ -+ clocks = <&dpll_mpu_ck>; -+ clock-names = "cpu"; -+ -+ clock-latency = <300000>; /* From omap-cpufreq driver */ -+ }; -+ cpu@1 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a15"; -+ reg = <1>; -+ }; -+ }; -+ -+ timer { -+ compatible = "arm,armv7-timer"; -+ /* PPI secure/nonsecure IRQ */ -+ interrupts = , -+ , -+ , -+ ; -+ clock-frequency = <6144000>; -+ }; -+ -+ gic: interrupt-controller@48211000 { -+ compatible = "arm,cortex-a15-gic"; -+ interrupt-controller; -+ #interrupt-cells = <3>; -+ reg = <0x48211000 0x1000>, -+ <0x48212000 0x1000>, -+ <0x48214000 0x2000>, -+ <0x48216000 0x2000>; -+ }; -+ -+ /* -+ * The soc node represents the soc top level view. It is uses for IPs -+ * that are not memory mapped in the MPU view or for the MPU itself. -+ */ -+ soc { -+ compatible = "ti,omap-infra"; -+ mpu { -+ compatible = "ti,omap5-mpu"; -+ ti,hwmods = "mpu"; -+ }; -+ }; -+ -+ /* -+ * XXX: Use a flat representation of the SOC interconnect. -+ * The real OMAP interconnect network is quite complex. -+ * Since that will not bring real advantage to represent that in DT for -+ * the moment, just use a fake OCP bus entry to represent the whole bus -+ * hierarchy. -+ */ -+ ocp { -+ compatible = "ti,omap4-l3-noc", "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ ti,hwmods = "l3_main_1", "l3_main_2"; -+ -+ crossbar_mpu: mpuirq@4a002a48 { -+ compatible = "crossbar"; -+ crossbar-name = "mpu-irq"; -+ reg = <0x4a002a48 0x0130>; -+ reg-width = <16>; -+ crossbar-lines = "mpu-irq", "rtc-ss-alarm", <0x9f 0xd9 0x12e>, -+ "mpu-irq", "mcasp3-arevt", <0x9e 0x96 0x12c>, -+ "mpu-irq", "mcasp3-axevt", <0x9d 0x97 0x12a>, -+ "mpu-irq", "mailbox5", <0x88 0xfb 0x100>, -+ "mpu-irq", "mailbox6", <0x8d 0xff 0x10a>, -+ "mpu-irq", "qspi", <0x7c 0x157 0x0ec>, -+ "mpu-irq", "vpe", <0x9c 0x162 0x128>, -+ "mpu-irq", "cpsw-rx-thresh", <0x32 0x14e 0x58>, -+ "mpu-irq", "cpsw-rx", <0x33 0x14f 0x5a>, -+ "mpu-irq", "cpsw-tx", <0x34 0x150 0x5c>, -+ "mpu-irq", "cpsw-misc", <0x35 0x151 0x5e>; -+ }; -+ -+ crossbar_dma: dmareq@4a002b78 { -+ compatible = "crossbar"; -+ crossbar-name = "dma-req"; -+ reg = <0x4a002b78 0x0100>; -+ reg-width = <16>; -+ crossbar-lines = "dma-req", "mcasp3-rx", <0x7e 0x84 0xfc>, -+ "dma-req", "mcasp3-tx", <0x7d 0x85 0xfa>; -+ }; -+ -+ prcm: prcm@4ae06000 { -+ compatible = "ti,dra7-prcm"; -+ reg = <0x4ae06000 0x1f00>; -+ #reset-cells = <1>; -+ }; -+ -+ counter32k: counter@4ae04000 { -+ compatible = "ti,omap-counter32k"; -+ reg = <0x4ae04000 0x40>; -+ ti,hwmods = "counter_32k"; -+ clocks = <&wkupaon_iclk_mux>; -+ clock-names = "fck"; -+ }; -+ -+ avs_mpu: regulator-avs@0x4A003B18 { -+ compatible = "ti,avsclass0"; -+ reg = <0x4A003B18 20>; -+ efuse-settings = <1090000 8 -+ 1210000 12 -+ 1280000 16>; -+ }; -+ -+ avs_core: regulator-avs@0x4A0025EC { -+ compatible = "ti,avsclass0"; -+ reg = <0x4A0025EC 20>; -+ efuse-settings = <1030000 8>; -+ }; -+ -+ avs_gpu: regulator-avs@0x4A003B00 { -+ compatible = "ti,avsclass0"; -+ reg = <0x4A003B00 20>; -+ efuse-settings = <1090000 8 -+ 1210000 12 -+ 1280000 16>; -+ }; -+ -+ avs_dspeve: regulator-avs@0x4A0025D8 { -+ compatible = "ti,avsclass0"; -+ reg = <0x4A0025D8 20>; -+ efuse-settings = <1055000 8 -+ 1150000 12 -+ 1250000 16>; -+ }; -+ -+ avs_iva: regulator-avs@0x4A0025C4 { -+ compatible = "ti,avsclass0"; -+ reg = <0x4A0025C4 20>; -+ efuse-settings = <1055000 8 -+ 1150000 12 -+ 1250000 16>; -+ }; -+ -+ dra7_pmx_core: pinmux@4a003400 { -+ compatible = "pinctrl-single"; -+ reg = <0x4a003400 0x0464>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-single,register-width = <32>; -+ pinctrl-single,function-mask = <0x3fffffff>; -+ }; -+ -+ sdma: dma-controller@4a056000 { -+ compatible = "ti,omap4430-sdma"; -+ reg = <0x4a056000 0x1000>; -+ interrupts = <0 12 0x4>, -+ <0 13 0x4>, -+ <0 14 0x4>, -+ <0 15 0x4>; -+ #dma-cells = <1>; -+ #dma-channels = <32>; -+ #dma-requests = <127>; -+ clocks = <&l3_iclk_div>; -+ clock-names = "fck"; -+ }; -+ -+ gpio1: gpio@4ae10000 { -+ compatible = "ti,omap4-gpio"; -+ reg = <0x4ae10000 0x200>; -+ interrupts = <0 29 0x4>; -+ ti,hwmods = "gpio1"; -+ clocks = <&wkupaon_iclk_mux>, <&gpio1_dbclk>; -+ clock-names = "fck", "dbclk"; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ -+ gpio2: gpio@48055000 { -+ compatible = "ti,omap4-gpio"; -+ reg = <0x48055000 0x200>; -+ interrupts = <0 30 0x4>; -+ ti,hwmods = "gpio2"; -+ clocks = <&l3_iclk_div>, <&gpio2_dbclk>; -+ clock-names = "fck", "dbclk"; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ -+ gpio3: gpio@48057000 { -+ compatible = "ti,omap4-gpio"; -+ reg = <0x48057000 0x200>; -+ interrupts = <0 31 0x4>; -+ ti,hwmods = "gpio3"; -+ clocks = <&l3_iclk_div>, <&gpio3_dbclk>; -+ clock-names = "fck", "dbclk"; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ -+ gpio4: gpio@48059000 { -+ compatible = "ti,omap4-gpio"; -+ reg = <0x48059000 0x200>; -+ interrupts = <0 32 0x4>; -+ ti,hwmods = "gpio4"; -+ clocks = <&l3_iclk_div>, <&gpio4_dbclk>; -+ clock-names = "fck", "dbclk"; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ -+ gpio5: gpio@4805b000 { -+ compatible = "ti,omap4-gpio"; -+ reg = <0x4805b000 0x200>; -+ interrupts = <0 33 0x4>; -+ ti,hwmods = "gpio5"; -+ clocks = <&l3_iclk_div>, <&gpio5_dbclk>; -+ clock-names = "fck", "dbclk"; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ -+ gpio6: gpio@4805d000 { -+ compatible = "ti,omap4-gpio"; -+ reg = <0x4805d000 0x200>; -+ interrupts = <0 34 0x4>; -+ ti,hwmods = "gpio6"; -+ clocks = <&l3_iclk_div>, <&gpio6_dbclk>; -+ clock-names = "fck", "dbclk"; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ -+ gpio7: gpio@48051000 { -+ compatible = "ti,omap4-gpio"; -+ reg = <0x48051000 0x200>; -+ interrupts = <0 35 0x4>; -+ ti,hwmods = "gpio7"; -+ clocks = <&l3_iclk_div>, <&gpio7_dbclk>; -+ clock-names = "fck", "dbclk"; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ -+ gpio8: gpio@48053000 { -+ compatible = "ti,omap4-gpio"; -+ reg = <0x48053000 0x200>; -+ interrupts = <0 121 0x4>; -+ ti,hwmods = "gpio8"; -+ clocks = <&l3_iclk_div>, <&gpio8_dbclk>; -+ clock-names = "fck", "dbclk"; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ -+ uart1: serial@4806a000 { -+ compatible = "ti,omap4-uart"; -+ reg = <0x4806a000 0x100>; -+ interrupts = <0 72 0x4>; -+ ti,hwmods = "uart1"; -+ clocks = <&uart1_gfclk_mux>; -+ clock-names = "fck"; -+ clock-frequency = <48000000>; -+ status = "disabled"; -+ }; -+ -+ uart2: serial@4806c000 { -+ compatible = "ti,omap4-uart"; -+ reg = <0x4806c000 0x100>; -+ interrupts = <0 73 0x4>; -+ ti,hwmods = "uart2"; -+ clocks = <&uart2_gfclk_mux>; -+ clock-names = "fck"; -+ clock-frequency = <48000000>; -+ status = "disabled"; -+ }; -+ -+ uart3: serial@48020000 { -+ compatible = "ti,omap4-uart"; -+ reg = <0x48020000 0x100>; -+ interrupts = <0 74 0x4>; -+ ti,hwmods = "uart3"; -+ clocks = <&uart3_gfclk_mux>; -+ clock-names = "fck"; -+ clock-frequency = <48000000>; -+ status = "disabled"; -+ }; -+ -+ uart4: serial@4806e000 { -+ compatible = "ti,omap4-uart"; -+ reg = <0x4806e000 0x100>; -+ interrupts = <0 70 0x4>; -+ ti,hwmods = "uart4"; -+ clocks = <&uart4_gfclk_mux>; -+ clock-names = "fck"; -+ clock-frequency = <48000000>; -+ status = "disabled"; -+ }; -+ -+ uart5: serial@48066000 { -+ compatible = "ti,omap4-uart"; -+ reg = <0x48066000 0x100>; -+ interrupts = <0 105 0x4>; -+ ti,hwmods = "uart5"; -+ clocks = <&uart5_gfclk_mux>; -+ clock-names = "fck"; -+ clock-frequency = <48000000>; -+ status = "disabled"; -+ }; -+ -+ uart6: serial@48068000 { -+ compatible = "ti,omap4-uart"; -+ reg = <0x48068000 0x100>; -+ interrupts = <0 106 0x4>; -+ ti,hwmods = "uart6"; -+ clocks = <&uart6_gfclk_mux>; -+ clock-names = "fck"; -+ clock-frequency = <48000000>; -+ status = "disabled"; -+ }; -+ -+ uart7: serial@48420000 { -+ compatible = "ti,omap4-uart"; -+ reg = <0x48420000 0x100>; -+ ti,hwmods = "uart7"; -+ clock-frequency = <48000000>; -+ status = "disabled"; -+ }; -+ -+ uart8: serial@48422000 { -+ compatible = "ti,omap4-uart"; -+ reg = <0x48422000 0x100>; -+ ti,hwmods = "uart8"; -+ clock-frequency = <48000000>; -+ status = "disabled"; -+ }; -+ -+ uart9: serial@48424000 { -+ compatible = "ti,omap4-uart"; -+ reg = <0x48424000 0x100>; -+ ti,hwmods = "uart9"; -+ clock-frequency = <48000000>; -+ status = "disabled"; -+ }; -+ -+ uart10: serial@4ae2b000 { -+ compatible = "ti,omap4-uart"; -+ reg = <0x4ae2b000 0x100>; -+ ti,hwmods = "uart10"; -+ clock-frequency = <48000000>; -+ status = "disabled"; -+ }; -+ -+ mailbox1: mailbox@4a0f4000 { -+ compatible = "ti,omap4-mailbox"; -+ reg = <0x4a0f4000 0x200>; -+ interrupts = <0 26 0x4>; -+ ti,hwmods = "mailbox1"; -+ ti,mbox-num-users = <3>; -+ ti,mbox-num-fifos = <8>; -+ #ti,mbox-data-cells = <4>; -+ ti,mbox-names = "mbox1-1", "mbox1-2"; -+ ti,mbox-data = <0 1 0 0>, <3 2 0 0>; -+ }; -+ -+ mailbox2: mailbox@4883a000 { -+ compatible = "ti,omap4-mailbox"; -+ reg = <0x4883a000 0x200>; -+ ti,hwmods = "mailbox2"; -+ ti,mbox-num-users = <4>; -+ ti,mbox-num-fifos = <12>; -+ #ti,mbox-data-cells = <4>; -+ status = "disabled"; -+ }; -+ -+ mailbox3: mailbox@4883c000 { -+ compatible = "ti,omap4-mailbox"; -+ reg = <0x4883c000 0x200>; -+ ti,hwmods = "mailbox3"; -+ ti,mbox-num-users = <4>; -+ ti,mbox-num-fifos = <12>; -+ #ti,mbox-data-cells = <4>; -+ status = "disabled"; -+ }; -+ -+ mailbox4: mailbox@4883e000 { -+ compatible = "ti,omap4-mailbox"; -+ reg = <0x4883e000 0x200>; -+ ti,hwmods = "mailbox4"; -+ ti,mbox-num-users = <4>; -+ ti,mbox-num-fifos = <12>; -+ #ti,mbox-data-cells = <4>; -+ status = "disabled"; -+ }; -+ -+ mailbox5: mailbox@48840000 { -+ compatible = "ti,omap4-mailbox"; -+ reg = <0x48840000 0x200>; -+ interrupts = <0 136 0x4>; -+ ti,hwmods = "mailbox5"; -+ ti,mbox-num-users = <4>; -+ ti,mbox-num-fifos = <12>; -+ #ti,mbox-data-cells = <4>; -+ ti,mbox-names = "mbox-ipu1", "mbox-dsp1"; -+ ti,mbox-data = <6 4 0 2>, <5 1 0 2>; -+ }; -+ -+ mailbox6: mailbox@48842000 { -+ compatible = "ti,omap4-mailbox"; -+ reg = <0x48842000 0x200>; -+ interrupts = <0 141 0x4>; -+ ti,hwmods = "mailbox6"; -+ ti,mbox-num-users = <4>; -+ ti,mbox-num-fifos = <12>; -+ #ti,mbox-data-cells = <4>; -+ ti,mbox-names = "mbox-ipu2", "mbox-dsp2"; -+ ti,mbox-data = <6 4 0 2>, <5 1 0 2>; -+ }; -+ -+ mailbox7: mailbox@48844000 { -+ compatible = "ti,omap4-mailbox"; -+ reg = <0x48844000 0x200>; -+ ti,hwmods = "mailbox7"; -+ ti,mbox-num-users = <4>; -+ ti,mbox-num-fifos = <12>; -+ #ti,mbox-data-cells = <4>; -+ status = "disabled"; -+ }; -+ -+ mailbox8: mailbox@48846000 { -+ compatible = "ti,omap4-mailbox"; -+ reg = <0x48846000 0x200>; -+ ti,hwmods = "mailbox8"; -+ ti,mbox-num-users = <4>; -+ ti,mbox-num-fifos = <12>; -+ #ti,mbox-data-cells = <4>; -+ status = "disabled"; -+ }; -+ -+ mailbox9: mailbox@4885e000 { -+ compatible = "ti,omap4-mailbox"; -+ reg = <0x4885e000 0x200>; -+ ti,hwmods = "mailbox9"; -+ ti,mbox-num-users = <4>; -+ ti,mbox-num-fifos = <12>; -+ #ti,mbox-data-cells = <4>; -+ status = "disabled"; -+ }; -+ -+ mailbox10: mailbox@48860000 { -+ compatible = "ti,omap4-mailbox"; -+ reg = <0x48860000 0x200>; -+ ti,hwmods = "mailbox10"; -+ ti,mbox-num-users = <4>; -+ ti,mbox-num-fifos = <12>; -+ #ti,mbox-data-cells = <4>; -+ status = "disabled"; -+ }; -+ -+ mailbox11: mailbox@48862000 { -+ compatible = "ti,omap4-mailbox"; -+ reg = <0x48862000 0x200>; -+ ti,hwmods = "mailbox11"; -+ ti,mbox-num-users = <4>; -+ ti,mbox-num-fifos = <12>; -+ #ti,mbox-data-cells = <4>; -+ status = "disabled"; -+ }; -+ -+ mailbox12: mailbox@48864000 { -+ compatible = "ti,omap4-mailbox"; -+ reg = <0x48864000 0x200>; -+ ti,hwmods = "mailbox12"; -+ ti,mbox-num-users = <4>; -+ ti,mbox-num-fifos = <12>; -+ #ti,mbox-data-cells = <4>; -+ status = "disabled"; -+ }; -+ -+ mailbox13: mailbox@48802000 { -+ compatible = "ti,omap4-mailbox"; -+ reg = <0x48802000 0x200>; -+ ti,hwmods = "mailbox13"; -+ ti,mbox-num-users = <4>; -+ ti,mbox-num-fifos = <12>; -+ #ti,mbox-data-cells = <4>; -+ status = "disabled"; -+ }; -+ -+ timer1: timer@4ae18000 { -+ compatible = "ti,omap5430-timer"; -+ reg = <0x4ae18000 0x80>; -+ interrupts = <0 37 0x4>; -+ ti,hwmods = "timer1"; -+ clocks = <&timer1_gfclk_mux>; -+ clock-names = "fck"; -+ ti,timer-alwon; -+ }; -+ -+ timer2: timer@48032000 { -+ compatible = "ti,omap5430-timer"; -+ reg = <0x48032000 0x80>; -+ interrupts = <0 38 0x4>; -+ ti,hwmods = "timer2"; -+ clocks = <&timer2_gfclk_mux>; -+ clock-names = "fck"; -+ }; -+ -+ timer3: timer@48034000 { -+ compatible = "ti,omap5430-timer"; -+ reg = <0x48034000 0x80>; -+ interrupts = <0 39 0x4>; -+ ti,hwmods = "timer3"; -+ clocks = <&timer3_gfclk_mux>; -+ clock-names = "fck"; -+ }; -+ -+ timer4: timer@48036000 { -+ compatible = "ti,omap5430-timer"; -+ reg = <0x48036000 0x80>; -+ interrupts = <0 40 0x4>; -+ ti,hwmods = "timer4"; -+ clocks = <&timer4_gfclk_mux>; -+ clock-names = "fck"; -+ }; -+ -+ timer5: timer@48820000 { -+ compatible = "ti,omap5430-timer"; -+ reg = <0x48820000 0x80>; -+ interrupts = <0 41 0x4>; -+ ti,hwmods = "timer5"; -+ clocks = <&timer5_gfclk_mux>; -+ clock-names = "fck"; -+ ti,timer-dsp; -+ }; -+ -+ timer6: timer@48822000 { -+ compatible = "ti,omap5430-timer"; -+ reg = <0x48822000 0x80>; -+ interrupts = <0 42 0x4>; -+ ti,hwmods = "timer6"; -+ clocks = <&timer6_gfclk_mux>; -+ clock-names = "fck"; -+ ti,timer-dsp; -+ ti,timer-pwm; -+ }; -+ -+ timer7: timer@48824000 { -+ compatible = "ti,omap5430-timer"; -+ reg = <0x48824000 0x80>; -+ interrupts = <0 43 0x4>; -+ ti,hwmods = "timer7"; -+ clocks = <&timer7_gfclk_mux>; -+ clock-names = "fck"; -+ ti,timer-dsp; -+ }; -+ -+ timer8: timer@48826000 { -+ compatible = "ti,omap5430-timer"; -+ reg = <0x48826000 0x80>; -+ interrupts = <0 44 0x4>; -+ ti,hwmods = "timer8"; -+ clocks = <&timer8_gfclk_mux>; -+ clock-names = "fck"; -+ ti,timer-dsp; -+ ti,timer-pwm; -+ }; -+ -+ timer9: timer@4803e000 { -+ compatible = "ti,omap5430-timer"; -+ reg = <0x4803e000 0x80>; -+ interrupts = <0 45 0x4>; -+ ti,hwmods = "timer9"; -+ clocks = <&timer9_gfclk_mux>; -+ clock-names = "fck"; -+ }; -+ -+ timer10: timer@48086000 { -+ compatible = "ti,omap5430-timer"; -+ reg = <0x48086000 0x80>; -+ interrupts = <0 46 0x4>; -+ ti,hwmods = "timer10"; -+ clocks = <&timer10_gfclk_mux>; -+ clock-names = "fck"; -+ }; -+ -+ timer11: timer@48088000 { -+ compatible = "ti,omap5430-timer"; -+ reg = <0x48088000 0x80>; -+ interrupts = <0 47 0x4>; -+ ti,hwmods = "timer11"; -+ clocks = <&timer11_gfclk_mux>; -+ clock-names = "fck"; -+ ti,timer-pwm; -+ }; -+ -+ timer13: timer@48828000 { -+ compatible = "ti,omap5430-timer"; -+ reg = <0x48828000 0x80>; -+ ti,hwmods = "timer13"; -+ status = "disabled"; -+ }; -+ -+ timer14: timer@4882a000 { -+ compatible = "ti,omap5430-timer"; -+ reg = <0x4882a000 0x80>; -+ ti,hwmods = "timer14"; -+ status = "disabled"; -+ }; -+ -+ timer15: timer@4882c000 { -+ compatible = "ti,omap5430-timer"; -+ reg = <0x4882c000 0x80>; -+ ti,hwmods = "timer15"; -+ status = "disabled"; -+ }; -+ -+ timer16: timer@4882e000 { -+ compatible = "ti,omap5430-timer"; -+ reg = <0x4882e000 0x80>; -+ ti,hwmods = "timer16"; -+ status = "disabled"; -+ }; -+ -+ wdt2: wdt@4ae14000 { -+ compatible = "ti,omap4-wdt"; -+ reg = <0x4ae14000 0x80>; -+ interrupts = <0 80 0x4>; -+ ti,hwmods = "wd_timer2"; -+ clocks = <&sys_32k_ck>; -+ clock-names = "fck"; -+ }; -+ -+ i2c1: i2c@48070000 { -+ compatible = "ti,omap4-i2c"; -+ reg = <0x48070000 0x100>; -+ interrupts = <0 56 0x4>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ ti,hwmods = "i2c1"; -+ clocks = <&func_96m_fclk>; -+ clock-names = "fck"; -+ status = "disabled"; -+ }; -+ -+ i2c2: i2c@48072000 { -+ compatible = "ti,omap4-i2c"; -+ reg = <0x48072000 0x100>; -+ interrupts = <0 57 0x4>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ ti,hwmods = "i2c2"; -+ clocks = <&func_96m_fclk>; -+ clock-names = "fck"; -+ status = "disabled"; -+ }; -+ -+ i2c3: i2c@48060000 { -+ compatible = "ti,omap4-i2c"; -+ reg = <0x48060000 0x100>; -+ interrupts = <0 61 0x4>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ ti,hwmods = "i2c3"; -+ clocks = <&func_96m_fclk>; -+ clock-names = "fck"; -+ status = "disabled"; -+ }; -+ -+ i2c4: i2c@4807a000 { -+ compatible = "ti,omap4-i2c"; -+ reg = <0x4807a000 0x100>; -+ interrupts = <0 62 0x4>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ ti,hwmods = "i2c4"; -+ clocks = <&func_96m_fclk>; -+ clock-names = "fck"; -+ status = "disabled"; -+ }; -+ -+ i2c5: i2c@4807c000 { -+ compatible = "ti,omap4-i2c"; -+ reg = <0x4807c000 0x100>; -+ interrupts = <0 60 0x4>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ ti,hwmods = "i2c5"; -+ clocks = <&func_96m_fclk>; -+ clock-names = "fck"; -+ status = "disabled"; -+ }; -+ -+ mmc1: mmc@4809c000 { -+ compatible = "ti,omap4-hsmmc"; -+ reg = <0x4809c000 0x400>; -+ interrupts = <0 83 0x4>; -+ ti,hwmods = "mmc1"; -+ clocks = <&mmc1_fclk_div>, <&mmc1_clk32k>; -+ clock-names = "fck", "clk32k"; -+ ti,dual-volt; -+ ti,needs-special-reset; -+ dmas = <&sdma 61>, <&sdma 62>; -+ dma-names = "tx", "rx"; -+ status = "disabled"; -+ }; -+ -+ mmc2: mmc@480b4000 { -+ compatible = "ti,omap4-hsmmc"; -+ reg = <0x480b4000 0x400>; -+ interrupts = <0 86 0x4>; -+ ti,hwmods = "mmc2"; -+ clocks = <&mmc2_fclk_div>, <&mmc2_clk32k>; -+ clock-names = "fck", "clk32k"; -+ ti,needs-special-reset; -+ dmas = <&sdma 47>, <&sdma 48>; -+ dma-names = "tx", "rx"; -+ status = "disabled"; -+ }; -+ -+ mmc3: mmc@480ad000 { -+ compatible = "ti,omap4-hsmmc"; -+ reg = <0x480ad000 0x400>; -+ interrupts = <0 94 0x4>; -+ ti,hwmods = "mmc3"; -+ clocks = <&mmc3_gfclk_div>, <&mmc3_clk32k>; -+ clock-names = "fck", "clk32k"; -+ ti,needs-special-reset; -+ dmas = <&sdma 77>, <&sdma 78>; -+ dma-names = "tx", "rx"; -+ status = "disabled"; -+ }; -+ -+ mmc4: mmc@480d1000 { -+ compatible = "ti,omap4-hsmmc"; -+ reg = <0x480d1000 0x400>; -+ interrupts = <0 96 0x4>; -+ ti,hwmods = "mmc4"; -+ clocks = <&mmc4_gfclk_div>, <&mmc4_clk32k>; -+ clock-names = "fck", "clk32k"; -+ ti,needs-special-reset; -+ dmas = <&sdma 57>, <&sdma 58>; -+ dma-names = "tx", "rx"; -+ status = "disabled"; -+ }; -+ -+ qspi: qspi@4b300000 { -+ compatible = "ti,dra7xxx-qspi"; -+ reg = <0x4b300000 0x100>, <0x4a002558 0x4>, -+ <0x5c000000 0x3ffffff>; -+ reg-names = "qspi_base", -+ "qspi_ctrlmod", -+ "qspi_mmap"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ ti,hwmods = "qspi"; -+ ti,spi-num-cs = <4>; -+ interrupts = <0 124 0x4>; -+ mmap_read; -+ }; -+ -+ omap_control_sata: control-phy@4a002374 { -+ compatible = "ti,control-phy-pipe3"; -+ reg = <0x4a002374 0x4>; -+ reg-names = "power"; -+ clocks = <&sys_clkin1>; -+ clock-names = "sysclk"; -+ }; -+ -+ ocp2scp@4a090000 { -+ compatible = "ti,omap-ocp2scp"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ ti,hwmods = "ocp2scp3"; -+ reg = <0x4a090000 0x400>; /* ocp2scp3 */ -+ sata_phy: sata-phy@4A096000 { -+ compatible = "ti,phy-pipe3-sata"; -+ reg = <0x4A096000 0x80>, /* phy_rx */ -+ <0x4A096400 0x64>, /* phy_tx */ -+ <0x4A096800 0x40>; /* pll_ctrl */ -+ reg-names = "phy_rx", "phy_tx", "pll_ctrl"; -+ ctrl-module = <&omap_control_sata>; -+ clocks = <&sata_ref_clk>; -+ clock-names = "refclk"; -+ #phy-cells = <0>; -+ }; -+ }; -+ -+ sata@4a141100 { -+ compatible = "ti,sata"; -+ ti,hwmods = "sata"; -+ reg = <0x4a141100 0x100>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ sata@4a140000 { -+ compatible = "snps,dwc-ahci"; -+ reg = <0x4a140000 0x1100>; -+ interrupts = <0 54 0x4>; -+ phys = <&sata_phy>; -+ phy-names = "sata-phy"; -+ }; -+ }; -+ -+ -+ mcspi1: spi@48098000 { -+ compatible = "ti,omap4-mcspi"; -+ reg = <0x48098000 0x200>; -+ interrupts = <0 65 0x4>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ ti,hwmods = "mcspi1"; -+ clocks = <&func_48m_fclk>; -+ clock-names = "fck"; -+ ti,spi-num-cs = <4>; -+ dmas = <&sdma 35>, -+ <&sdma 36>, -+ <&sdma 37>, -+ <&sdma 38>, -+ <&sdma 39>, -+ <&sdma 40>, -+ <&sdma 41>, -+ <&sdma 42>; -+ dma-names = "tx0", "rx0", "tx1", "rx1", -+ "tx2", "rx2", "tx3", "rx3"; -+ status = "disabled"; -+ }; -+ -+ mcspi2: spi@4809a000 { -+ compatible = "ti,omap4-mcspi"; -+ reg = <0x4809a000 0x200>; -+ interrupts = <0 66 0x4>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ ti,hwmods = "mcspi2"; -+ clocks = <&func_48m_fclk>; -+ clock-names = "fck"; -+ ti,spi-num-cs = <2>; -+ dmas = <&sdma 43>, -+ <&sdma 44>, -+ <&sdma 45>, -+ <&sdma 46>; -+ dma-names = "tx0", "rx0", "tx1", "rx1"; -+ status = "disabled"; -+ }; -+ -+ mcspi3: spi@480b8000 { -+ compatible = "ti,omap4-mcspi"; -+ reg = <0x480b8000 0x200>; -+ interrupts = <0 91 0x4>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ ti,hwmods = "mcspi3"; -+ clocks = <&func_48m_fclk>; -+ clock-names = "fck"; -+ ti,spi-num-cs = <2>; -+ dmas = <&sdma 15>, <&sdma 16>; -+ dma-names = "tx0", "rx0"; -+ status = "disabled"; -+ }; -+ -+ mcspi4: spi@480ba000 { -+ compatible = "ti,omap4-mcspi"; -+ reg = <0x480ba000 0x200>; -+ interrupts = <0 48 0x4>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ ti,hwmods = "mcspi4"; -+ clocks = <&func_48m_fclk>; -+ clock-names = "fck"; -+ ti,spi-num-cs = <1>; -+ dmas = <&sdma 70>, <&sdma 71>; -+ dma-names = "tx0", "rx0"; -+ status = "disabled"; -+ }; -+ -+ rtcss@48838000 { -+ compatible = "ti,da830-rtc"; -+ reg = <0x48838000 0x100>; -+ interrupts = <0 159 0x4>, -+ <0 159 0x4>; -+ ti,hwmods = "rtcss"; -+ clocks = <&sys_32k_ck>; -+ clock-names = "fck"; -+ }; -+ -+ omap_control_usb2phy1: control-phy@4a002300 { -+ compatible = "ti,control-phy-usb2"; -+ reg = <0x4a002300 0x4>; -+ reg-names = "power"; -+ }; -+ -+ omap_control_usb3phy1: control-phy@4a002370 { -+ compatible = "ti,control-phy-pipe3"; -+ reg = <0x4a002370 0x4>; -+ reg-names = "power"; -+ }; -+ -+ omap_control_usb2phy2: control-phy@0x4a002e74 { -+ compatible = "ti,control-phy-dra7usb2"; -+ reg = <0x4a002e74 0x4>; -+ reg-names = "power"; -+ }; -+ -+ ocp2scp@4a080000 { -+ compatible = "ti,omap-ocp2scp"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ ti,hwmods = "ocp2scp1"; -+ reg = <0x4a080000 0x400>; /* ocp2scp1 */ -+ -+ usb2_phy1: usb2phy1@4a084000 { -+ compatible = "ti,omap-usb2"; -+ reg = <0x4a084000 0x400>; -+ ctrl-module = <&omap_control_usb2phy1>; -+ clocks = <&usb_phy1_always_on_clk32k>, -+ <&usb_otg_ss1_refclk960m>; -+ clock-names = "wkupclk", -+ "refclk"; -+ #phy-cells = <0>; -+ }; -+ -+ usb2_phy2: usb2phy2@4a085000 { -+ compatible = "ti,omap-usb2"; -+ reg = <0x4a085000 0x400>; -+ ctrl-module = <&omap_control_usb2phy2>; -+ clocks = <&usb_phy2_always_on_clk32k>, -+ <&usb_otg_ss2_refclk960m>; -+ clock-names = "wkupclk", -+ "refclk"; -+ #phy-cells = <0>; -+ }; -+ -+ usb3_phy1: usb3phy@4a084400 { -+ compatible = "ti,phy-pipe3-usb3"; -+ reg = <0x4a084400 0x80>, -+ <0x4a084800 0x64>, -+ <0x4a084c00 0x40>; -+ reg-names = "phy_rx", "phy_tx", "pll_ctrl"; -+ ctrl-module = <&omap_control_usb3phy1>; -+ clocks = <&usb_phy1_always_on_clk32k>, -+ <&usb_otg_ss1_refclk960m>, -+ <&dpll_core_h13x2_ck>; -+ clock-names = "wkupclk", -+ "refclk", -+ "refclk2"; -+ #phy-cells = <0>; -+ }; -+ }; -+ -+ dwc3_1: omap_dwc3_1@48880000 { -+ compatible = "ti,dwc3"; -+ ti,hwmods = "usb_otg_ss1"; -+ reg = <0x48880000 0x10000>; -+ interrupts = <0 77 4>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ utmi-mode = <2>; -+ ranges; -+ usb1: usb@48890000 { -+ compatible = "synopsys,dwc3"; -+ reg = <0x48890000 0x17000>; -+ interrupts = <0 76 4>; -+ phys = <&usb2_phy1>, <&usb3_phy1>; -+ phy-names = "usb2-phy", "usb3-phy"; -+ tx-fifo-resize; -+ maximum-speed = "super-speed"; -+ dr_mode = "otg"; -+ }; -+ }; -+ -+ dwc3_2: omap_dwc3_2@488c0000 { -+ compatible = "ti,dwc3"; -+ ti,hwmods = "usb_otg_ss2"; -+ reg = <0x488c0000 0x10000>; -+ interrupts = <0 92 4>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ utmi-mode = <2>; -+ ranges; -+ usb2: usb@488d0000 { -+ compatible = "synopsys,dwc3"; -+ reg = <0x488d0000 0x17000>; -+ interrupts = <0 78 4>; -+ phys = <&usb2_phy2>; -+ phy-names = "usb2-phy"; -+ tx-fifo-resize; -+ maximum-speed = "high-speed"; -+ dr_mode = "otg"; -+ }; -+ }; -+ -+ /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ -+ dwc3_3: omap_dwc3_3@48900000 { -+ compatible = "ti,dwc3"; -+ ti,hwmods = "usb_otg_ss3"; -+ reg = <0x48900000 0x10000>; -+ /* interrupts = <0 TBD 4>; */ -+ #address-cells = <1>; -+ #size-cells = <1>; -+ utmi-mode = <2>; -+ ranges; -+ status = "disabled"; -+ usb3: usb@48910000 { -+ compatible = "synopsys,dwc3"; -+ reg = <0x48910000 0x17000>; -+ /* interrupts = <0 93 4>; */ -+ tx-fifo-resize; -+ maximum-speed = "high-speed"; -+ dr_mode = "otg"; -+ }; -+ }; -+ -+ dwc3_4: omap_dwc3_4@48940000 { -+ compatible = "ti,dwc3"; -+ ti,hwmods = "usb_otg_ss4"; -+ reg = <0x48940000 0x10000>; -+ /* interrupts = <0 TBD 4>; */ -+ #address-cells = <1>; -+ #size-cells = <1>; -+ utmi-mode = <2>; -+ ranges; -+ status = "disabled"; -+ usb4: usb@48950000 { -+ compatible = "synopsys,dwc3"; -+ reg = <0x48950000 0x17000>; -+ /* interrupts = <0 TBD 4>; */ -+ tx-fifo-resize; -+ maximum-speed = "high-speed"; -+ dr_mode = "otg"; -+ }; -+ }; -+ -+ dmm: dmm@4e000000 { -+ compatible = "ti,omap5-dmm"; -+ reg = <0x4e000000 0x800>; -+ interrupts = <0 113 0x4>; -+ ti,hwmods = "dmm"; -+ }; -+ -+ dss: dss@58000000 { -+ compatible = "ti,omap4-dss", "simple-bus"; -+ reg = <0x58000000 0x80>, -+ <0x58004000 0x340>, -+ <0x58009000 0x340>; -+ ti,hwmods = "dss_core"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ dispc@58001000 { -+ compatible = "ti,omap4-dispc"; -+ reg = <0x58001000 0x1000>; -+ interrupts = <0 25 0x4>; -+ ti,hwmods = "dss_dispc"; -+ }; -+ -+ dpi1: encoder@0 { -+ compatible = "ti,dra7xx-dpi"; -+ id = <0>; -+ channel = <0>; -+ }; -+ -+ dpi2: encoder@1 { -+ compatible = "ti,dra7xx-dpi"; -+ id = <1>; -+ }; -+ -+ dpi3: encoder@2 { -+ compatible = "ti,dra7xx-dpi"; -+ id = <2>; -+ }; -+ -+ hdmi: encoder@58040000 { -+ compatible = "ti,omap5-hdmi"; -+ reg = <0x58040000 0x100>, -+ <0x58040200 0x40>, -+ <0x58040300 0x40>, -+ <0x58060000 0x19000>; -+ reg-names = "hdmi_wp", "hdmi_pllctrl", -+ "hdmi_txphy", "hdmi_core"; -+ interrupts = <0 101 0x4>; -+ ti,hwmods = "dss_hdmi"; -+ }; -+ }; -+ -+ vpe { -+ compatible = "ti,vpe"; -+ ti,hwmods = "vpe"; -+ reg = <0x489d0000 0x120>, -+ <0x489d0300 0x20>, -+ <0x489d0400 0x20>, -+ <0x489d0500 0x20>, -+ <0x489d0600 0x3c>, -+ <0x489d0700 0x80>, -+ <0x489d5700 0x18>, -+ <0x489dd000 0x400>; -+ reg-names = "vpe_top", -+ "vpe_chr_us0", -+ "vpe_chr_us1", -+ "vpe_chr_us2", -+ "vpe_dei", -+ "vpe_sc", -+ "vpe_csc", -+ "vpdma"; -+ interrupts = <0 0x9c 0x4>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mac: ethernet@4a100000 { -+ compatible = "ti,cpsw"; -+ ti,hwmods = "gmac"; -+ cpdma_channels = <8>; -+ ale_entries = <1024>; -+ bd_ram_size = <0x2000>; -+ no_bd_ram = <0>; -+ rx_descs = <64>; -+ mac_control = <0x20>; -+ slaves = <2>; -+ active_slave = <0>; -+ cpts_clock_mult = <0x80000000>; -+ cpts_clock_shift = <29>; -+ reg = <0x48484000 0x800 -+ 0x48485200 0x100>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ /* -+ * rx_thresh_pend -+ * rx_pend -+ * tx_pend -+ * misc_pend -+ */ -+ interrupts = , -+ , -+ , -+ ; -+ ranges; -+ status = "disabled"; -+ -+ davinci_mdio: mdio@4a101000 { -+ compatible = "ti,davinci_mdio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ ti,hwmods = "davinci_mdio"; -+ bus_freq = <1000000>; -+ reg = <0x48485000 0x100>; -+ }; -+ -+ cpsw_emac0: slave@4a100200 { -+ /* Filled in by U-Boot */ -+ mac-address = [ 00 00 00 00 00 00 ]; -+ }; -+ -+ cpsw_emac1: slave@4a100300 { -+ /* Filled in by U-Boot */ -+ mac-address = [ 00 00 00 00 00 00 ]; -+ }; -+ }; -+ -+ elm: elm@48078000 { -+ compatible = "ti,am3352-elm"; -+ /* compatible = "ti,elm"; */ -+ reg = <0x48078000 0x2000>; -+ interrupts = ; -+ ti,hwmods = "elm"; -+ status = "disabled"; -+ }; -+ -+ gpmc: gpmc@50000000 { -+ compatible = "ti,am3352-gpmc"; -+ /* compatible = "ti,gpmc"; */ -+ ti,hwmods = "gpmc"; -+ reg = <0x50000000 0x2000>; -+ interrupts = ; -+ gpmc,num-cs = <8>; -+ gpmc,num-waitpins = <2>; -+ #address-cells = <2>; -+ #size-cells = <1>; -+ status = "disabled"; -+ }; -+ -+ aes: aes@4b500000 { -+ compatible = "ti,omap4-aes"; -+ ti,hwmods = "aes"; -+ reg = <0x4b500000 0xa0>; -+ interrupts = ; -+ dmas = <&sdma 111>, <&sdma 110>; -+ dma-names = "tx", "rx"; -+ clocks = <&l3_iclk_div>; -+ clock-names = "fck"; -+ }; -+ -+ des: des@480a5000 { -+ compatible = "ti,omap4-des"; -+ ti,hwmods = "des"; -+ reg = <0x480a5000 0xa0>; -+ interrupts = ; -+ dmas = <&sdma 117>, <&sdma 116>; -+ dma-names = "tx", "rx"; -+ clocks = <&l3_iclk_div>; -+ clock-names = "fck"; -+ }; -+ }; -+ -+ clocks { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ /include/ "dra7xx-clocks.dtsi" -+ }; -+ -+ clockdomains { -+ coreaon_clkdm: coreaon_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&dpll_usb_ck>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/dra7-evm.dts -@@ -0,0 +1,761 @@ -+/* -+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+/dts-v1/; -+ -+#include "dra7.dtsi" -+#include -+ -+/ { -+ model = "TI DRA7"; -+ compatible = "ti,dra7-evm", "ti,dra752", "ti,dra7"; -+ -+ memory { -+ device_type = "memory"; -+ reg = <0x80000000 0x60000000>; /* 1536 MB */ -+ }; -+ -+ extcon1: gpio_usbvid_extcon1 { -+ compatible = "ti,gpio-usb-id"; -+ gpios = <&gpio21 1 0>; -+ }; -+ -+ extcon2: gpio_usbvid_extcon2 { -+ compatible = "ti,gpio-usb-id"; -+ gpios = <&gpio21 2 0>; -+ }; -+ -+ mmc2_3v3: fixedregulator-mmc2 { -+ compatible = "regulator-fixed"; -+ regulator-name = "mmc2_3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+}; -+ -+&dra7_pmx_core { -+ pinctrl-names = "default"; -+ pinctrl-0 = < -+ &vout1_pins -+ &irq_pins -+ >; -+ -+ i2c1_pins: pinmux_i2c1_pins { -+ pinctrl-single,pins = < -+ 0x400 0x60000 /* i2c1_sda */ -+ 0x404 0x60000 /* i2c1_scl */ -+ >; -+ }; -+ -+ i2c2_pins: pinmux_i2c2_pins { -+ pinctrl-single,pins = < -+ 0x408 0x60000 /* i2c2_sda */ -+ 0x40c 0x60000 /* i2c2_scl */ -+ >; -+ }; -+ -+ i2c3_pins: pinmux_i2c3_pins { -+ pinctrl-single,pins = < -+ 0x410 0x60000 /* i2c3_sda */ -+ 0x414 0x60000 /* i2c3_scl */ -+ >; -+ }; -+ -+ irq_pins: pinmux_irq_pins { -+ pinctrl-single,pins = < -+ 0x420 0x1 /* Wakeup2 INPUT | MODE1 */ -+ >; -+ }; -+ -+ mmc1_pins: pinmux_mmc1_pins { -+ pinctrl-single,pins = < -+ 0x36c 0x4000e /* mmc1sdcd.gpio INPUT | MODE15 */ -+ >; -+ }; -+ -+ mcspi1_pins: pinmux_mcspi1_pins { -+ pinctrl-single,pins = < -+ 0x3a4 0x40000 /* spi2_clk */ -+ 0x3a8 0x40000 /* spi2_d1 */ -+ 0x3ac 0x40000 /* spi2_d0 */ -+ 0x3b0 0xc0000 /* spi2_cs0 */ -+ 0x3b4 0xc0000 /* spi2_cs1 */ -+ 0x3b8 0xe0006 /* spi2_cs2 */ -+ 0x3bc 0xe0006 /* spi2_cs3 */ -+ >; -+ }; -+ -+ mcspi2_pins: pinmux_mcspi2_pins { -+ pinctrl-single,pins = < -+ 0x3c0 0x40000 /* spi2_sclk */ -+ 0x3c4 0xc0000 /* spi2_d1 */ -+ 0x3c8 0xc0000 /* spi2_d1 */ -+ 0x3cc 0xe0000 /* spi2_cs0 */ -+ >; -+ }; -+ -+ uart1_pins: pinmux_uart1_pins { -+ pinctrl-single,pins = < -+ 0x3e0 0xe0000 /* uart1_rxd */ -+ 0x3e4 0xe0000 /* uart1_txd */ -+ 0x3e8 0x60003 /* uart1_ctsn */ -+ 0x3ec 0x60003 /* uart1_rtsn */ -+ >; -+ }; -+ -+ uart2_pins: pinmux_uart2_pins { -+ pinctrl-single,pins = < -+ 0x3f0 0x60000 /* uart2_rxd */ -+ 0x3f4 0x60000 /* uart2_txd */ -+ 0x3f8 0x60000 /* uart2_ctsn */ -+ 0x3fc 0x60000 /* uart2_rtsn */ -+ >; -+ }; -+ -+ uart3_pins: pinmux_uart3_pins { -+ pinctrl-single,pins = < -+ 0x248 0xc0000 /* uart3_rxd */ -+ 0x24c 0xc0000 /* uart3_txd */ -+ >; -+ }; -+ -+ qspi1_pins: pinmux_qspi1_pins { -+ pinctrl-single,pins = < -+ 0x4c 0x40001 /* gpmc_a3.qspi1_cs2 */ -+ 0x50 0x40001 /* gpmc_a4.qspi1_cs3 */ -+ 0x74 0x40001 /* gpmc_a13.qspi1_rtclk */ -+ 0x78 0x40001 /* gpmc_a14.qspi1_d3 */ -+ 0x7c 0x40001 /* gpmc_a15.qspi1_d2 */ -+ 0x80 0x40001 /* gpmc_a16.qspi1_d1 */ -+ 0x84 0x40001 /* gpmc_a17.qspi1_d0 */ -+ 0x88 0x40001 /* qpmc_a18.qspi1_sclk */ -+ 0xb8 0x60001 /* gpmc_cs2.qspi1_cs0 */ -+ 0xbc 0x60001 /* gpmc_cs3.qspi1_cs1 */ -+ >; -+ }; -+ -+ usb1_pins: pinmux_usb1_pins { -+ pinctrl-single,pins = < -+ 0x280 0xc0000 /* usb1_drvvbus, SLOW_SLEW | PULLUPEN | MODE0 */ -+ >; -+ }; -+ -+ usb2_pins: pinmux_usb2_pins { -+ pinctrl-single,pins = < -+ 0x284 0xc0000 /* usb2_drvvbus, SLOW_SLEW | PULLUPEN | MODE0 */ -+ >; -+ }; -+ -+ vout1_pins: pinmux_vout1_pins { -+ pinctrl-single,pins = < -+ 0x1C8 0x0 /* vout1_clk OUTPUT | MODE0 */ -+ 0x1CC 0x0 /* vout1_de OUTPUT | MODE0 */ -+ 0x1D0 0x0 /* vout1_fld OUTPUT | MODE0 */ -+ 0x1D4 0x0 /* vout1_hsync OUTPUT | MODE0 */ -+ 0x1D8 0x0 /* vout1_vsync OUTPUT | MODE0 */ -+ 0x1DC 0x0 /* vout1_d0 OUTPUT | MODE0 */ -+ 0x1E0 0x0 /* vout1_d1 OUTPUT | MODE0 */ -+ 0x1E4 0x0 /* vout1_d2 OUTPUT | MODE0 */ -+ 0x1E8 0x0 /* vout1_d3 OUTPUT | MODE0 */ -+ 0x1EC 0x0 /* vout1_d4 OUTPUT | MODE0 */ -+ 0x1F0 0x0 /* vout1_d5 OUTPUT | MODE0 */ -+ 0x1F4 0x0 /* vout1_d6 OUTPUT | MODE0 */ -+ 0x1F8 0x0 /* vout1_d7 OUTPUT | MODE0 */ -+ 0x1FC 0x0 /* vout1_d8 OUTPUT | MODE0 */ -+ 0x200 0x0 /* vout1_d9 OUTPUT | MODE0 */ -+ 0x204 0x0 /* vout1_d10 OUTPUT | MODE0 */ -+ 0x208 0x0 /* vout1_d11 OUTPUT | MODE0 */ -+ 0x20C 0x0 /* vout1_d12 OUTPUT | MODE0 */ -+ 0x210 0x0 /* vout1_d13 OUTPUT | MODE0 */ -+ 0x214 0x0 /* vout1_d14 OUTPUT | MODE0 */ -+ 0x218 0x0 /* vout1_d15 OUTPUT | MODE0 */ -+ 0x21C 0x0 /* vout1_d16 OUTPUT | MODE0 */ -+ 0x220 0x0 /* vout1_d17 OUTPUT | MODE0 */ -+ 0x224 0x0 /* vout1_d18 OUTPUT | MODE0 */ -+ 0x228 0x0 /* vout1_d19 OUTPUT | MODE0 */ -+ 0x22C 0x0 /* vout1_d20 OUTPUT | MODE0 */ -+ 0x230 0x0 /* vout1_d21 OUTPUT | MODE0 */ -+ 0x234 0x0 /* vout1_d22 OUTPUT | MODE0 */ -+ 0x238 0x0 /* vout1_d23 OUTPUT | MODE0 */ -+ >; -+ }; -+ -+ cpsw_default: cpsw_default { -+ pinctrl-single,pins = < -+ /* Slave 1 */ -+ 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tclk */ -+ 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tctl */ -+ 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td3 */ -+ 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td2 */ -+ 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td1 */ -+ 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td0 */ -+ 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii1_rclk */ -+ 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii1_rctl */ -+ 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd3 */ -+ 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd2 */ -+ 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd1 */ -+ 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii1_rd0 */ -+ -+ /* Slave 2 */ -+ 0x198 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tclk */ -+ 0x19c (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tctl */ -+ 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td3 */ -+ 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td2 */ -+ 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td1 */ -+ 0x1ac (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td0 */ -+ 0x1b0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rclk */ -+ 0x1b4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rctl */ -+ 0x1b8 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd3 */ -+ 0x1bc (PIN_INPUT | MUX_MODE3) /* rgmii2_rd2 */ -+ 0x1c0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd1 */ -+ 0x1c4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd0 */ -+ >; -+ -+ }; -+ cpsw_sleep: cpsw_sleep { -+ pinctrl-single,pins = < -+ /* Slave 1 */ -+ 0x250 (PIN_OFF_NONE) -+ 0x254 (PIN_OFF_NONE) -+ 0x258 (PIN_OFF_NONE) -+ 0x25c (PIN_OFF_NONE) -+ 0x260 (PIN_OFF_NONE) -+ 0x264 (PIN_OFF_NONE) -+ 0x268 (PIN_OFF_NONE) -+ 0x26c (PIN_OFF_NONE) -+ 0x270 (PIN_OFF_NONE) -+ 0x274 (PIN_OFF_NONE) -+ 0x278 (PIN_OFF_NONE) -+ 0x27c (PIN_OFF_NONE) -+ -+ /* Slave 1 */ -+ 0x198 (PIN_OFF_NONE) -+ 0x19c (PIN_OFF_NONE) -+ 0x1a0 (PIN_OFF_NONE) -+ 0x1a4 (PIN_OFF_NONE) -+ 0x1a8 (PIN_OFF_NONE) -+ 0x1ac (PIN_OFF_NONE) -+ 0x1b0 (PIN_OFF_NONE) -+ 0x1b4 (PIN_OFF_NONE) -+ 0x1b8 (PIN_OFF_NONE) -+ 0x1bc (PIN_OFF_NONE) -+ 0x1c0 (PIN_OFF_NONE) -+ 0x1c4 (PIN_OFF_NONE) -+ >; -+ }; -+ -+ davinci_mdio_default: davinci_mdio_default { -+ pinctrl-single,pins = < -+ /* MDIO */ -+ 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_data */ -+ 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk */ -+ >; -+ }; -+ -+ davinci_mdio_sleep: davinci_mdio_sleep { -+ pinctrl-single,pins = < -+ 0x23c (PIN_OFF_NONE) -+ 0x240 (PIN_OFF_NONE) -+ >; -+ }; -+ -+ nand_flash_x16: nand_flash_x16 { -+ /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch -+ * So NAND flash requires following switch settings: -+ * SW5.9 (GPMC_WPN) = LOW -+ * SW5.1 (NAND_BOOTn) = HIGH */ -+ pinctrl-single,pins = < -+ 0x0 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad0 */ -+ 0x4 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad1 */ -+ 0x8 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad2 */ -+ 0xc 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad3 */ -+ 0x10 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad4 */ -+ 0x14 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad5 */ -+ 0x18 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad6 */ -+ 0x1c 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad7 */ -+ 0x20 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad8 */ -+ 0x24 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad9 */ -+ 0x28 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad10 */ -+ 0x2c 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad11 */ -+ 0x30 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad12 */ -+ 0x34 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad13 */ -+ 0x38 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad14 */ -+ 0x3c 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad15 */ -+ 0xD8 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_wait0 */ -+ 0xCC 0x0 /* (PIN_OUTPUT | MUX_MODE0) gpmc_wen */ -+ 0xB4 0x0 /* (PIN_OUTPUT | MUX_MODE0) gpmc_csn0 */ -+ 0xC4 0x0 /* (PIN_OUTPUT | MUX_MODE0) gpmc_advn_ale */ -+ 0xC8 0x0 /* (PIN_OUTPUT | MUX_MODE0) gpmc_oen_ren */ -+ 0xD0 0x0 /* (PIN_OUTPUT | MUX_MODE0) gpmc_be0n_cle */ -+ >; -+ }; -+}; -+ -+&i2c1 { -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins>; -+ clock-frequency = <400000>; -+ -+ tps659038: tps659038@58 { -+ compatible = "ti,tps659038"; -+ reg = <0x58>; -+ -+ tps659038_pmic { -+ compatible = "ti,tps659038-pmic"; -+ -+ regulators { -+ smps123_reg: smps123 { -+ /* VDD_MPU */ -+ regulator-name = "smps123"; -+ regulator-min-microvolt = < 850000>; -+ regulator-max-microvolt = <1250000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ smps45_reg: smps45 { -+ /* VDD_DSPEVE */ -+ regulator-name = "smps45"; -+ regulator-min-microvolt = < 850000>; -+ regulator-max-microvolt = <1150000>; -+ regulator-boot-on; -+ }; -+ -+ smps6_reg: smps6 { -+ /* VDD_GPU - over VDD_SMPS6 */ -+ regulator-name = "smps6"; -+ regulator-min-microvolt = <850000>; -+ regulator-max-microvolt = <12500000>; -+ regulator-boot-on; -+ }; -+ -+ smps7_reg: smps7 { -+ /* CORE_VDD */ -+ regulator-name = "smps7"; -+ regulator-min-microvolt = <850000>; -+ regulator-max-microvolt = <1030000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ smps8_reg: smps8 { -+ /* VDD_IVAHD */ -+ regulator-name = "smps8"; -+ regulator-min-microvolt = < 850000>; -+ regulator-max-microvolt = <1250000>; -+ regulator-boot-on; -+ }; -+ -+ smps9_reg: smps9 { -+ /* VDDS1V8 */ -+ regulator-name = "smps9"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ ldo1_reg: ldo1 { -+ /* LDO1_OUT --> SDIO */ -+ regulator-name = "ldo1"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ }; -+ -+ ldo2_reg: ldo2 { -+ /* VDD_RTCIO */ -+ /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */ -+ regulator-name = "ldo2"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ }; -+ -+ ldo3_reg: ldo3 { -+ /* VDDA_1V8_PHY */ -+ regulator-name = "ldo3"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ }; -+ -+ ldo9_reg: ldo9 { -+ /* VDD_RTC */ -+ regulator-name = "ldo9"; -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-boot-on; -+ }; -+ -+ ldoln_reg: ldoln { -+ /* VDDA_1V8_PLL */ -+ regulator-name = "ldoln"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ ldousb_reg: ldousb { -+ /* VDDA_3V_USB: VDDA_USBHS33 */ -+ regulator-name = "ldousb"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ }; -+ -+ }; -+ }; -+ }; -+ -+ pcf_gpio_20: gpio@20 { -+ compatible = "ti,pcf8575"; -+ reg = <0x20>; -+ lines-initial-states = <0x4000>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-parent = <&gpio6>; -+ interrupts = <11 2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio21: gpio@21 { -+ compatible = "ti,pcf8575"; -+ reg = <0x21>; -+ lines-initial-states = <0x1408>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-parent = <&pcf_gpio_20>; -+ interrupts = <14 2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ /* TLC chip for LCD panel power and backlight */ -+ tlc59108: tlc59108@40 { -+ compatible = "ti,tlc59108"; -+ reg = <0x40>; -+ gpios = <&pcf_gpio_20 13 0>; /* P15, CON_LCD_PWR_DN */ -+ video-source = <&dpi1>; -+ data-lines = <24>; -+ }; -+ -+ mxt244: touchscreen@4a { -+ compatible = "atmel,mXT244"; -+ status = "okay"; -+ reg = <0x4a>; -+ interrupts = <0 119 0x4>; -+ -+ atmel,config = < -+ /* MXT244_GEN_COMMAND(6) */ -+ 0x00 0x00 0x00 0x00 0x00 0x00 -+ /* MXT244_GEN_POWER(7) */ -+ 0x20 0xff 0x32 -+ /* MXT244_GEN_ACQUIRE(8) */ -+ 0x0a 0x00 0x05 0x00 0x00 0x00 0x09 0x23 -+ /* MXT244_TOUCH_MULTI(9) */ -+ 0x00 0x00 0x00 0x13 0x0b 0x00 0x00 0x00 0x02 0x00 -+ 0x00 0x01 0x01 0x0e 0x0a 0x0a 0x0a 0x0a 0x00 0x00 -+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 -+ 0x00 -+ /* MXT244_TOUCH_KEYARRAY(15) */ -+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 -+ 0x00 -+ /* MXT244_COMMSCONFIG_T18(2) */ -+ 0x00 0x00 -+ /* MXT244_SPT_GPIOPWM(19) */ -+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 -+ 0x00 0x00 0x00 0x00 0x00 0x00 -+ /* MXT244_PROCI_GRIPFACE(20) */ -+ 0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x50 0x28 0x04 -+ 0x0f 0x0a -+ /* MXT244_PROCG_NOISE(22) */ -+ 0x05 0x00 0x00 0x00 0x00 0x00 0x00 0x03 0x23 0x00 -+ 0x00 0x05 0x0f 0x19 0x23 0x2d 0x03 -+ /* MXT244_TOUCH_PROXIMITY(23) */ -+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 -+ 0x00 0x00 0x00 0x00 0x00 -+ /* MXT244_PROCI_ONETOUCH(24) */ -+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 -+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 -+ /* MXT244_SPT_SELFTEST(25) */ -+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 -+ 0x00 0x00 0x00 0x00 -+ /* MXT244_PROCI_TWOTOUCH(27) */ -+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00 -+ /* MXT244_SPT_CTECONFIG(28) */ -+ 0x00 0x00 0x02 0x08 0x10 0x00 -+ >; -+ -+ atmel,x_line = <18>; -+ atmel,y_line = <12>; -+ atmel,x_size = <800>; -+ atmel,y_size = <480>; -+ atmel,blen = <0x01>; -+ atmel,threshold = <30>; -+ atmel,voltage = <2800000>; -+ atmel,orient = <0x4>; -+ }; -+}; -+ -+&i2c2 { -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c2_pins>; -+ clock-frequency = <400000>; -+ -+ pcf_hdmi: gpio@26 { -+ compatible = "nxp,pcf8575"; -+ reg = <0x26>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+}; -+ -+&i2c3 { -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c3_pins>; -+ clock-frequency = <3400000>; -+}; -+ -+&mcspi1 { -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mcspi1_pins>; -+}; -+ -+&mcspi2 { -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mcspi2_pins>; -+}; -+ -+&uart1 { -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>; -+}; -+ -+&uart2 { -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart2_pins>; -+}; -+ -+&uart3 { -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart3_pins>; -+}; -+ -+&qspi { -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&qspi1_pins>; -+ -+ spi-max-frequency = <48000000>; -+ m25p80@0 { -+ compatible = "s25fl256s1"; -+ spi-max-frequency = <48000000>; -+ reg = <0>; -+ spi-tx-bus-width = <1>; -+ spi-rx-bus-width = <4>; -+ spi-cpol; -+ spi-cpha; -+ }; -+}; -+ -+&usb1 { -+ dr_mode = "peripheral"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&usb1_pins>; -+}; -+ -+&usb2 { -+ dr_mode = "host"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&usb2_pins>; -+}; -+ -+&dwc3_1 { -+ extcon = <&extcon1>; -+}; -+ -+&dwc3_2 { -+ extcon = <&extcon2>; -+}; -+ -+&mmc1 { -+ status = "okay"; -+ vmmc-supply = <&ldo1_reg>; -+ bus-width = <4>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc1_pins>; -+ cd-gpios = <&gpio6 27 0>; /* gpio 187 */ -+}; -+ -+&mmc2 { -+ status = "okay"; -+ vmmc-supply = <&mmc2_3v3>; -+ bus-width = <8>; -+ ti,non-removable; -+}; -+ -+&dss { -+ vdda_video-supply = <&ldoln_reg>; -+}; -+ -+&hdmi { -+ vdda_hdmi_dac-supply = <&ldo3_reg>; -+}; -+ -+&avs_mpu { -+ avs-supply = <&smps123_reg>; -+}; -+ -+&avs_core { -+ avs-supply = <&smps7_reg>; -+}; -+ -+&avs_gpu { -+ avs-supply = <&smps6_reg>; -+}; -+ -+&avs_dspeve { -+ avs-supply = <&smps45_reg>; -+}; -+ -+&avs_iva { -+ avs-supply = <&smps8_reg>; -+}; -+ -+&cpu0 { -+ cpu0-supply = <&avs_mpu>; -+}; -+ -+/ { -+ aliases { -+ display0 = &tlc59108; -+ display1 = &hdmi0; -+ }; -+ -+ tpd12s015: encoder@0 { -+ compatible = "ti,draevm-tpd12s015"; -+ -+ video-source = <&hdmi>; -+ -+ gpios = <&pcf_hdmi 4 0>, /* P4, CT CP HPD */ -+ <&pcf_hdmi 5 0>, /* P5, LS OE */ -+ <&gpio7 12 0>; /* gpio7_12/sp1_cs2, HPD */ -+ }; -+ -+ hdmi0: connector@0 { -+ compatible = "ti,hdmi_connector"; -+ -+ video-source = <&tpd12s015>; -+ }; -+}; -+ -+&mac { -+ status = "okay"; -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&cpsw_default>; -+ pinctrl-1 = <&cpsw_sleep>; -+}; -+ -+&cpsw_emac0 { -+ phy_id = <&davinci_mdio>, <2>; -+}; -+ -+&cpsw_emac1 { -+ phy_id = <&davinci_mdio>, <3>; -+}; -+ -+&davinci_mdio { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&davinci_mdio_default>; -+ pinctrl-1 = <&davinci_mdio_sleep>; -+}; -+ -+&elm { -+ status = "okay"; -+}; -+ -+&gpmc { -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&nand_flash_x16>; -+ ranges = <0 0 0x08000000 0x10000000>; -+ nand@0,0 { -+ reg = <0 0 0>; -+ nand-bus-width = <16>; -+ ti,nand-ecc-opt = "bch8"; -+ gpmc,device-width = <2>; -+ gpmc,sync-clk-ps = <0>; -+ gpmc,cs-on-ns = <0>; -+ gpmc,cs-rd-off-ns = <55>; -+ gpmc,cs-wr-off-ns = <55>; -+ gpmc,adv-on-ns = <0>; -+ gpmc,adv-rd-off-ns = <55>; -+ gpmc,adv-wr-off-ns = <55>; -+ gpmc,we-on-ns = <5>; -+ gpmc,we-off-ns = <40>; -+ gpmc,oe-on-ns = <2>; -+ gpmc,oe-off-ns = <45>; -+ gpmc,access-ns = <40>; -+ gpmc,wr-access-ns = <37>; -+ gpmc,rd-cycle-ns = <55>; -+ gpmc,wr-cycle-ns = <55>; -+ gpmc,wait-on-read = "true"; -+ gpmc,wait-on-write = "true"; -+ gpmc,bus-turnaround-ns = <0>; -+ gpmc,cycle2cycle-delay-ns = <0>; -+ gpmc,clk-activation-ns = <0>; -+ gpmc,wait-monitoring-ns = <0>; -+ gpmc,wr-data-mux-bus-ns = <0>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ti,elm-id = <&elm>; -+ /* MTD partition table */ -+ partition@0 { -+ label = "SPL1"; -+ reg = <0x00000000 0x000020000>; -+ }; -+ partition@1 { -+ label = "SPL2"; -+ reg = <0x00020000 0x00020000>; -+ }; -+ partition@2 { -+ label = "SPL3"; -+ reg = <0x00040000 0x00020000>; -+ }; -+ partition@3 { -+ label = "SPL4"; -+ reg = <0x00060000 0x00020000>; -+ }; -+ partition@4 { -+ label = "U-boot"; -+ reg = <0x00080000 0x001e0000>; -+ }; -+ partition@5 { -+ label = "environment"; -+ reg = <0x00260000 0x00020000>; -+ }; -+ partition@6 { -+ label = "Kernel"; -+ reg = <0x00280000 0x00500000>; -+ }; -+ partition@7 { -+ label = "File-System"; -+ reg = <0x00780000 0x0F880000>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi -@@ -0,0 +1,2103 @@ -+/* -+ * Device Tree Source for DRA7xx clock data -+ * -+ * Copyright (C) 2013 Texas Instruments, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+atl_clkin0_ck: atl_clkin0_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <0>; -+}; -+ -+atl_clkin1_ck: atl_clkin1_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <0>; -+}; -+ -+atl_clkin2_ck: atl_clkin2_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <0>; -+}; -+ -+atlclkin3_ck: atlclkin3_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <0>; -+}; -+ -+hdmi_clkin_ck: hdmi_clkin_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <0>; -+}; -+ -+mlb_clkin_ck: mlb_clkin_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <0>; -+}; -+ -+mlbp_clkin_ck: mlbp_clkin_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <0>; -+}; -+ -+pciesref_acs_clk_ck: pciesref_acs_clk_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <100000000>; -+}; -+ -+ref_clkin0_ck: ref_clkin0_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <0>; -+}; -+ -+ref_clkin1_ck: ref_clkin1_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <0>; -+}; -+ -+ref_clkin2_ck: ref_clkin2_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <0>; -+}; -+ -+ref_clkin3_ck: ref_clkin3_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <0>; -+}; -+ -+rmii_clk_ck: rmii_clk_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <0>; -+}; -+ -+sdvenc_clkin_ck: sdvenc_clkin_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <0>; -+}; -+ -+secure_32k_clk_src_ck: secure_32k_clk_src_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <32768>; -+}; -+ -+sys_32k_ck: sys_32k_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <32768>; -+}; -+ -+virt_12000000_ck: virt_12000000_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <12000000>; -+}; -+ -+virt_13000000_ck: virt_13000000_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <13000000>; -+}; -+ -+virt_16800000_ck: virt_16800000_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <16800000>; -+}; -+ -+virt_19200000_ck: virt_19200000_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <19200000>; -+}; -+ -+virt_20000000_ck: virt_20000000_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <20000000>; -+}; -+ -+virt_26000000_ck: virt_26000000_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <26000000>; -+}; -+ -+virt_27000000_ck: virt_27000000_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <27000000>; -+}; -+ -+virt_38400000_ck: virt_38400000_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <38400000>; -+}; -+ -+sys_clkin1: sys_clkin1@4ae06110 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; -+ reg = <0x4ae06110 0x4>; -+ bit-mask = <0x7>; -+ index-starts-at-one; -+}; -+ -+sys_clkin2: sys_clkin2 { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <22579200>; -+}; -+ -+usb_otg_clkin_ck: usb_otg_clkin_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <0>; -+}; -+ -+video1_clkin_ck: video1_clkin_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <0>; -+}; -+ -+video1_m2_clkin_ck: video1_m2_clkin_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <0>; -+}; -+ -+video2_clkin_ck: video2_clkin_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <0>; -+}; -+ -+video2_m2_clkin_ck: video2_m2_clkin_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <0>; -+}; -+ -+abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@4ae06118 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin1>, <&sys_clkin2>; -+ reg = <0x4ae06118 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@4ae06114 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; -+ reg = <0x4ae06114 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+abe_dpll_clk_mux: abe_dpll_clk_mux@4ae0610c { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; -+ reg = <0x4ae0610c 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+dpll_abe_ck: dpll_abe_ck@4a0051e0 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-m4xen-clock"; -+ clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; -+ reg = <0x4a0051e0 0x4>, <0x4a0051e4 0x4>, <0x4a0051e8 0x4>, <0x4a0051ec 0x4>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+}; -+ -+dpll_abe_x2_ck: dpll_abe_x2_ck { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-x2-clock"; -+ clocks = <&dpll_abe_ck>; -+}; -+ -+dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@4a0051f0 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_abe_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a0051f0 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+abe_24m_fclk: abe_24m_fclk@4ae0611c { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_abe_m2x2_ck>; -+ reg = <0x4ae0611c 0x4>; -+ table = < 8 0 >, < 16 1 >; -+ bit-mask = <0x1>; -+}; -+ -+abe_clk: abe_clk@4a005108 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_abe_m2x2_ck>; -+ reg = <0x4a005108 0x4>; -+ bit-mask = <0x3>; -+ index-power-of-two; -+}; -+ -+aess_fclk: aess_fclk@4ae06178 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&abe_clk>; -+ reg = <0x4ae06178 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+abe_giclk_div: abe_giclk_div@4ae06174 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&aess_fclk>; -+ reg = <0x4ae06174 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+abe_lp_clk_div: abe_lp_clk_div@4ae061d8 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_abe_m2x2_ck>; -+ reg = <0x4ae061d8 0x4>; -+ table = < 16 0 >, < 32 1 >; -+ bit-mask = <0x1>; -+}; -+ -+abe_sys_clk_div: abe_sys_clk_div@4ae06120 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&sys_clkin1>; -+ reg = <0x4ae06120 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+adc_gfclk_mux: adc_gfclk_mux@4ae061dc { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>; -+ reg = <0x4ae061dc 0x4>; -+ bit-mask = <0x7>; -+}; -+ -+dpll_pcie_ref_ck: dpll_pcie_ref_ck@4a008200 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-clock"; -+ clocks = <&sys_clkin1>, <&sys_clkin1>; -+ reg = <0x4a008200 0x4>, <0x4a008204 0x4>, <0x4a008208 0x4>, <0x4a00820c 0x4>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+}; -+ -+dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@4a008210 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_pcie_ref_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a008210 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 { -+ compatible = "mux-clock"; -+ clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>; -+ #clock-cells = <0>; -+ reg = <0x4a00821c 0x4>; -+ bit-mask = <0x80>; -+}; -+ -+apll_pcie_ck: apll_pcie_ck@4a008200 { -+ #clock-cells = <0>; -+ compatible = "ti,dra7-apll-clock"; -+ clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>; -+ reg = <0x4a00821c 0x4>, <0x4a008220 0x4>; -+ reg-names = "control", "idlest"; -+}; -+ -+apll_pcie_clkvcoldo: apll_pcie_clkvcoldo { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&apll_pcie_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&apll_pcie_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+apll_pcie_m2_ck: apll_pcie_m2_ck@4a008224 { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&apll_pcie_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+sys_clk1_dclk_div: sys_clk1_dclk_div@4ae061c8 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&sys_clkin1>; -+ reg = <0x4ae061c8 0x4>; -+ bit-mask = <0x7>; -+ index-power-of-two; -+}; -+ -+sys_clk2_dclk_div: sys_clk2_dclk_div@4ae061cc { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&sys_clkin2>; -+ reg = <0x4ae061cc 0x4>; -+ bit-mask = <0x7>; -+ index-power-of-two; -+}; -+ -+dpll_abe_m2_ck: dpll_abe_m2_ck@4a0051f0 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_abe_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a0051f0 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+per_abe_x1_dclk_div: per_abe_x1_dclk_div@4ae061bc { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_abe_m2_ck>; -+ reg = <0x4ae061bc 0x4>; -+ bit-mask = <0x7>; -+ index-power-of-two; -+}; -+ -+dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@4a0051f4 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_abe_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a0051f4 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_core_ck: dpll_core_ck@4a005120 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-core-clock"; -+ clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; -+ reg = <0x4a005120 0x4>, <0x4a005124 0x4>, <0x4a005128 0x4>, <0x4a00512c 0x4>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+}; -+ -+dpll_core_x2_ck: dpll_core_x2_ck { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-x2-clock"; -+ clocks = <&dpll_core_ck>; -+}; -+ -+dpll_core_h12x2_ck: dpll_core_h12x2_ck@4a00513c { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_core_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a00513c 0x4>; -+ bit-mask = <0x3f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_core_h12x2_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+dpll_mpu_ck: dpll_mpu_ck@4a005160 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-clock"; -+ clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>; -+ reg = <0x4a005160 0x4>, <0x4a005164 0x4>, <0x4a005168 0x4>, <0x4a00516c 0x4>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+}; -+ -+dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a005170 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_mpu_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a005170 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+mpu_dclk_div: mpu_dclk_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_mpu_m2_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_core_h12x2_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+dpll_dsp_ck: dpll_dsp_ck@4a005234 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-clock"; -+ clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>; -+ reg = <0x4a005234 0x4>, <0x4a005238 0x4>, <0x4a00523c 0x4>, <0x4a005240 0x4>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+}; -+ -+dpll_dsp_m2_ck: dpll_dsp_m2_ck@4a005244 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_dsp_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a005244 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dsp_gclk_div: dsp_gclk_div@4ae0618c { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_dsp_m2_ck>; -+ reg = <0x4ae0618c 0x4>; -+ bit-mask = <0x7>; -+ index-power-of-two; -+}; -+ -+iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_core_h12x2_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+dpll_iva_ck: dpll_iva_ck@4a0051a0 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-clock"; -+ clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>; -+ reg = <0x4a0051a0 0x4>, <0x4a0051a4 0x4>, <0x4a0051a8 0x4>, <0x4a0051ac 0x4>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+}; -+ -+dpll_iva_m2_ck: dpll_iva_m2_ck@4a0051b0 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_iva_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a0051b0 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+iva_dclk: iva_dclk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_iva_m2_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+dpll_gpu_ck: dpll_gpu_ck@4a0052d8 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-clock"; -+ clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; -+ reg = <0x4a0052d8 0x4>, <0x4a0052dc 0x4>, <0x4a0052e0 0x4>, <0x4a0052e4 0x4>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+}; -+ -+dpll_gpu_m2_ck: dpll_gpu_m2_ck@4a0052e8 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_gpu_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a0052e8 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+gpu_dclk: gpu_dclk@4ae061a0 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_gpu_m2_ck>; -+ reg = <0x4ae061a0 0x4>; -+ bit-mask = <0x7>; -+ index-power-of-two; -+}; -+ -+dpll_core_m2_ck: dpll_core_m2_ck@4a005130 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_core_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a005130 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+core_dpll_out_dclk_div: core_dpll_out_dclk_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_core_m2_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+dpll_ddr_ck: dpll_ddr_ck@4a005210 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-clock"; -+ clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; -+ reg = <0x4a005210 0x4>, <0x4a005214 0x4>, <0x4a005218 0x4>, <0x4a00521c 0x4>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+}; -+ -+dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a005220 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_ddr_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a005220 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+emif_phy_dclk_div: emif_phy_dclk_div@4ae06190 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_ddr_m2_ck>; -+ reg = <0x4ae06190 0x4>; -+ bit-mask = <0x7>; -+ index-power-of-two; -+}; -+ -+dpll_gmac_ck: dpll_gmac_ck@4a0052a8 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-clock"; -+ clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; -+ reg = <0x4a0052a8 0x4>, <0x4a0052ac 0x4>, <0x4a0052b0 0x4>, <0x4a0052b4 0x4>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+}; -+ -+dpll_gmac_m2_ck: dpll_gmac_m2_ck@4a0052b8 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_gmac_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a0052b8 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+gmac_250m_dclk_div: gmac_250m_dclk_div@4ae0619c { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_gmac_m2_ck>; -+ reg = <0x4ae0619c 0x4>; -+ bit-mask = <0x7>; -+ index-power-of-two; -+}; -+ -+video2_dclk_div: video2_dclk_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&video2_m2_clkin_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+video1_dclk_div: video1_dclk_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&video1_m2_clkin_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+hdmi_dclk_div: hdmi_dclk_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&hdmi_clkin_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+per_dpll_hs_clk_div: per_dpll_hs_clk_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_abe_m3x2_ck>; -+ clock-mult = <1>; -+ clock-div = <2>; -+}; -+ -+dpll_per_ck: dpll_per_ck@4a008140 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-clock"; -+ clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>; -+ reg = <0x4a008140 0x4>, <0x4a008144 0x4>, <0x4a008148 0x4>, <0x4a00814c 0x4>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+}; -+ -+dpll_per_m2_ck: dpll_per_m2_ck@4a008150 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_per_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a008150 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+func_96m_aon_dclk_div: func_96m_aon_dclk_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_per_m2_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+usb_dpll_hs_clk_div: usb_dpll_hs_clk_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_abe_m3x2_ck>; -+ clock-mult = <1>; -+ clock-div = <3>; -+}; -+ -+dpll_usb_ck: dpll_usb_ck@4a008180 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-j-type-clock"; -+ clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>; -+ reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>, <0x4a00818c 0x4>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+}; -+ -+dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_usb_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a008190 0x4>; -+ bit-mask = <0x7f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+l3init_480m_dclk_div: l3init_480m_dclk_div@4ae061ac { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_usb_m2_ck>; -+ reg = <0x4ae061ac 0x4>; -+ bit-mask = <0x7>; -+ index-power-of-two; -+}; -+ -+usb_otg_dclk_div: usb_otg_dclk_div@4ae06184 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&usb_otg_clkin_ck>; -+ reg = <0x4ae06184 0x4>; -+ bit-mask = <0x7>; -+ index-power-of-two; -+}; -+ -+sata_dclk_div: sata_dclk_div@4ae061c0 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&sys_clkin1>; -+ reg = <0x4ae061c0 0x4>; -+ bit-mask = <0x7>; -+ index-power-of-two; -+}; -+ -+dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@4a008210 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_pcie_ref_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a008210 0x4>; -+ bit-mask = <0x7f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+pcie2_dclk_div: pcie2_dclk_div@4ae061b8 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_pcie_ref_m2_ck>; -+ reg = <0x4ae061b8 0x4>; -+ bit-mask = <0x7>; -+ index-power-of-two; -+}; -+ -+pcie_dclk_div: pcie_dclk_div@4ae061b4 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&apll_pcie_m2_ck>; -+ reg = <0x4ae061b4 0x4>; -+ bit-mask = <0x7>; -+ index-power-of-two; -+}; -+ -+emu_dclk_div: emu_dclk_div@4ae06194 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&sys_clkin1>; -+ reg = <0x4ae06194 0x4>; -+ bit-mask = <0x7>; -+ index-power-of-two; -+}; -+ -+secure_32k_dclk_div: secure_32k_dclk_div@4ae061c4 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&secure_32k_clk_src_ck>; -+ reg = <0x4ae061c4 0x4>; -+ bit-mask = <0x7>; -+ index-power-of-two; -+}; -+ -+eve_dpll_hs_clk_div: eve_dpll_hs_clk_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_core_h12x2_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+dpll_eve_ck: dpll_eve_ck@4a005284 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-clock"; -+ clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>; -+ reg = <0x4a005284 0x4>, <0x4a005288 0x4>, <0x4a00528c 0x4>, <0x4a005290 0x4>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+}; -+ -+dpll_eve_m2_ck: dpll_eve_m2_ck@4a005294 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_eve_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a005294 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+eve_dclk_div: eve_dclk_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_eve_m2_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+clkoutmux0_clk_mux: clkoutmux0_clk_mux@4ae06158 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; -+ reg = <0x4ae06158 0x4>; -+ bit-mask = <0x1f>; -+}; -+ -+clkoutmux1_clk_mux: clkoutmux1_clk_mux@4ae0615c { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; -+ reg = <0x4ae0615c 0x4>; -+ bit-mask = <0x1f>; -+}; -+ -+clkoutmux2_clk_mux: clkoutmux2_clk_mux@4ae06160 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; -+ reg = <0x4ae06160 0x4>; -+ bit-mask = <0x1f>; -+}; -+ -+custefuse_sys_gfclk_div: custefuse_sys_gfclk_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&sys_clkin1>; -+ clock-mult = <1>; -+ clock-div = <2>; -+}; -+ -+dpll_core_h13x2_ck: dpll_core_h13x2_ck@4a005140 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_core_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a005140 0x4>; -+ bit-mask = <0x3f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_core_h14x2_ck: dpll_core_h14x2_ck@4a005144 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_core_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a005144 0x4>; -+ bit-mask = <0x3f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_core_h22x2_ck: dpll_core_h22x2_ck@4a005154 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_core_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a005154 0x4>; -+ bit-mask = <0x3f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_core_h23x2_ck: dpll_core_h23x2_ck@4a005158 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_core_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a005158 0x4>; -+ bit-mask = <0x3f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_core_h24x2_ck: dpll_core_h24x2_ck@4a00515c { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_core_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a00515c 0x4>; -+ bit-mask = <0x3f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_ddr_x2_ck: dpll_ddr_x2_ck { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-x2-clock"; -+ clocks = <&dpll_ddr_ck>; -+}; -+ -+dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@4a005228 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_ddr_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a005228 0x4>; -+ bit-mask = <0x3f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_dsp_x2_ck: dpll_dsp_x2_ck { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-x2-clock"; -+ clocks = <&dpll_dsp_ck>; -+}; -+ -+dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@4a005248 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_dsp_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a005248 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_gmac_x2_ck: dpll_gmac_x2_ck { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-x2-clock"; -+ clocks = <&dpll_gmac_ck>; -+}; -+ -+dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@4a0052c0 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_gmac_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a0052c0 0x4>; -+ bit-mask = <0x3f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@4a0052c4 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_gmac_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a0052c4 0x4>; -+ bit-mask = <0x3f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@4a0052c8 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_gmac_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a0052c8 0x4>; -+ bit-mask = <0x3f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@4a0052bc { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_gmac_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a0052bc 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_per_x2_ck: dpll_per_x2_ck { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-x2-clock"; -+ clocks = <&dpll_per_ck>; -+}; -+ -+dpll_per_h11x2_ck: dpll_per_h11x2_ck@4a008158 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_per_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a008158 0x4>; -+ bit-mask = <0x3f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_per_h12x2_ck: dpll_per_h12x2_ck@4a00815c { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_per_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a00815c 0x4>; -+ bit-mask = <0x3f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_per_h13x2_ck: dpll_per_h13x2_ck@4a008160 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_per_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a008160 0x4>; -+ bit-mask = <0x3f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_per_h14x2_ck: dpll_per_h14x2_ck@4a008164 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_per_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a008164 0x4>; -+ bit-mask = <0x3f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_per_m2x2_ck: dpll_per_m2x2_ck@4a008150 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_per_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a008150 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_usb_clkdcoldo: dpll_usb_clkdcoldo { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_usb_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+eve_clk: eve_clk@4ae06180 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>; -+ reg = <0x4ae06180 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+func_128m_clk: func_128m_clk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_per_h11x2_ck>; -+ clock-mult = <1>; -+ clock-div = <2>; -+}; -+ -+func_12m_fclk: func_12m_fclk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_per_m2x2_ck>; -+ clock-mult = <1>; -+ clock-div = <16>; -+}; -+ -+func_24m_clk: func_24m_clk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_per_m2_ck>; -+ clock-mult = <1>; -+ clock-div = <4>; -+}; -+ -+func_48m_fclk: func_48m_fclk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_per_m2x2_ck>; -+ clock-mult = <1>; -+ clock-div = <4>; -+}; -+ -+func_96m_fclk: func_96m_fclk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_per_m2x2_ck>; -+ clock-mult = <1>; -+ clock-div = <2>; -+}; -+ -+gmii_m_clk_div: gmii_m_clk_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_gmac_h11x2_ck>; -+ clock-mult = <1>; -+ clock-div = <2>; -+}; -+ -+hdmi_clk2_div: hdmi_clk2_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&hdmi_clkin_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+hdmi_div_clk: hdmi_div_clk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&hdmi_clkin_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@4ae061a4 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin1>, <&sys_clkin2>; -+ reg = <0x4ae061a4 0x4>; -+ bit-mask = <0x7>; -+}; -+ -+l3_iclk_div: l3_iclk_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_core_h12x2_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+l3init_60m_fclk: l3init_60m_fclk@4a008104 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_usb_m2_ck>; -+ reg = <0x4a008104 0x4>; -+ table = < 1 0 >, < 8 1 >; -+ bit-mask = <0x1>; -+}; -+ -+l3init_960m_gfclk: l3init_960m_gfclk@4a0086c0 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dpll_usb_clkdcoldo>; -+ bit-shift = <8>; -+ reg = <0x4a0086c0 0x4>; -+}; -+ -+l4_root_clk_div: l4_root_clk_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&l3_iclk_div>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+mlb_clk: mlb_clk@4ae06134 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&mlb_clkin_ck>; -+ reg = <0x4ae06134 0x4>; -+ bit-mask = <0x7>; -+ index-power-of-two; -+}; -+ -+mlbp_clk: mlbp_clk@4ae06130 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&mlbp_clkin_ck>; -+ reg = <0x4ae06130 0x4>; -+ bit-mask = <0x7>; -+ index-power-of-two; -+}; -+ -+per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@4ae06138 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_abe_m2_ck>; -+ reg = <0x4ae06138 0x4>; -+ bit-mask = <0x7>; -+ index-power-of-two; -+}; -+ -+timer_sys_clk_div: timer_sys_clk_div@4ae06144 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&sys_clkin1>; -+ reg = <0x4ae06144 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+video1_clk2_div: video1_clk2_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&video1_clkin_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+video1_div_clk: video1_div_clk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&video1_clkin_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+video1_dpll_clk_mux: video1_dpll_clk_mux@4ae061d0 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin1>, <&sys_clkin2>; -+ reg = <0x4ae061d0 0x4>; -+ bit-mask = <0x7>; -+}; -+ -+video2_clk2_div: video2_clk2_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&video2_clkin_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+video2_div_clk: video2_div_clk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&video2_clkin_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+video2_dpll_clk_mux: video2_dpll_clk_mux@4ae061d4 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin1>, <&sys_clkin2>; -+ reg = <0x4ae061d4 0x4>; -+ bit-mask = <0x7>; -+}; -+ -+wkupaon_iclk_mux: wkupaon_iclk_mux@4ae06108 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin1>, <&abe_lp_clk_div>; -+ reg = <0x4ae06108 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+dss_32khz_clk: dss_32khz_clk@4a009120 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <11>; -+ reg = <0x4a009120 0x4>; -+}; -+ -+dss_48mhz_clk: dss_48mhz_clk@4a009120 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&func_48m_fclk>; -+ bit-shift = <9>; -+ reg = <0x4a009120 0x4>; -+}; -+ -+dss_dss_clk: dss_dss_clk@4a009120 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dpll_per_h12x2_ck>; -+ bit-shift = <8>; -+ reg = <0x4a009120 0x4>; -+}; -+ -+dss_hdmi_clk: dss_hdmi_clk@4a009120 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&hdmi_dpll_clk_mux>; -+ bit-shift = <10>; -+ reg = <0x4a009120 0x4>; -+}; -+ -+dss_video1_clk: dss_video1_clk@4a009120 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&video1_dpll_clk_mux>; -+ bit-shift = <12>; -+ reg = <0x4a009120 0x4>; -+}; -+ -+dss_video2_clk: dss_video2_clk@4a009120 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&video2_dpll_clk_mux>; -+ bit-shift = <13>; -+ reg = <0x4a009120 0x4>; -+}; -+ -+dss_deshdcp_clk: dss_deshdcp_clk@4a002558 { -+ compatible = "gate-clock"; -+ clocks = <&l3_iclk_div>; -+ #clock-cells = <0>; -+ reg = <0x4a002558 0x1>; -+ bit-shift = <0>; -+}; -+ -+gpio1_dbclk: gpio1_dbclk@4ae07838 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4ae07838 0x4>; -+}; -+ -+gpio2_dbclk: gpio2_dbclk@4a009760 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4a009760 0x4>; -+}; -+ -+gpio3_dbclk: gpio3_dbclk@4a009768 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4a009768 0x4>; -+}; -+ -+gpio4_dbclk: gpio4_dbclk@4a009770 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4a009770 0x4>; -+}; -+ -+gpio5_dbclk: gpio5_dbclk@4a009778 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4a009778 0x4>; -+}; -+ -+gpio6_dbclk: gpio6_dbclk@4a009780 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4a009780 0x4>; -+}; -+ -+gpio7_dbclk: gpio7_dbclk@4a009810 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4a009810 0x4>; -+}; -+ -+gpio8_dbclk: gpio8_dbclk@4a009818 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4a009818 0x4>; -+}; -+ -+mmc1_clk32k: mmc1_clk32k@4a009328 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4a009328 0x4>; -+}; -+ -+mmc2_clk32k: mmc2_clk32k@4a009330 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4a009330 0x4>; -+}; -+ -+mmc3_clk32k: mmc3_clk32k@4a009820 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4a009820 0x4>; -+}; -+ -+mmc4_clk32k: mmc4_clk32k@4a009828 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4a009828 0x4>; -+}; -+ -+sata_ref_clk: sata_ref_clk@4a009388 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_clkin1>; -+ bit-shift = <8>; -+ reg = <0x4a009388 0x4>; -+}; -+ -+usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@4a0093f0 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&l3init_960m_gfclk>; -+ bit-shift = <8>; -+ reg = <0x4a0093f0 0x4>; -+}; -+ -+usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m@4a009340 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&l3init_960m_gfclk>; -+ bit-shift = <8>; -+ reg = <0x4a009340 0x4>; -+}; -+ -+usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@4a008640 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4a008640 0x4>; -+}; -+ -+usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@4a008688 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4a008688 0x4>; -+}; -+ -+usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@4a008698 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4a008698 0x4>; -+}; -+ -+atl_dpll_clk_mux: atl_dpll_clk_mux@4a008c00 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>; -+ bit-shift = <24>; -+ reg = <0x4a008c00 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+atl_gfclk_mux: atl_gfclk_mux@4a008c00 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>; -+ bit-shift = <26>; -+ reg = <0x4a008c00 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+dcan1_sys_clk_mux: dcan1_sys_clk_mux@4ae07888 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin1>, <&sys_clkin2>; -+ bit-shift = <24>; -+ reg = <0x4ae07888 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div@4a0093d0 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_gmac_m2_ck>; -+ bit-shift = <24>; -+ reg = <0x4a0093d0 0x4>; -+ table = < 2 0 >; -+ bit-mask = <0x1>; -+}; -+ -+gmac_rft_clk_mux: gmac_rft_clk_mux@4a0093d0 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>; -+ bit-shift = <25>; -+ reg = <0x4a0093d0 0x4>; -+ bit-mask = <0x7>; -+}; -+ -+gpu_core_gclk_mux: gpu_core_gclk_mux@4a009220 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009220 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@4a009220 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; -+ bit-shift = <26>; -+ reg = <0x4a009220 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+ipu1_gfclk_mux: ipu1_gfclk_mux@4a005520 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>; -+ bit-shift = <24>; -+ reg = <0x4a005520 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+l3instr_ts_gclk_div: l3instr_ts_gclk_div@4a008e50 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&wkupaon_iclk_mux>; -+ bit-shift = <24>; -+ reg = <0x4a008e50 0x4>; -+ table = < 8 0 >, < 16 1 >, < 32 2 >; -+ bit-mask = <0x3>; -+}; -+ -+mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@4a005550 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; -+ bit-shift = <28>; -+ reg = <0x4a005550 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+mcasp1_ahclkx_mux: mcasp1_ahclkx_mux@4a005550 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; -+ bit-shift = <24>; -+ reg = <0x4a005550 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux@4a005550 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; -+ bit-shift = <22>; -+ reg = <0x4a005550 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+mcasp2_ahclkr_mux: mcasp2_ahclkr_mux@4a009860 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; -+ bit-shift = <28>; -+ reg = <0x4a009860 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+mcasp2_ahclkx_mux: mcasp2_ahclkx_mux@4a009860 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; -+ bit-shift = <28>; -+ reg = <0x4a009860 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux@4a009860 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; -+ bit-shift = <22>; -+ reg = <0x4a009860 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+mcasp3_ahclkx_mux: mcasp3_ahclkx_mux@4a009868 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; -+ bit-shift = <24>; -+ reg = <0x4a009868 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux@4a009868 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; -+ bit-shift = <22>; -+ reg = <0x4a009868 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+mcasp4_ahclkx_mux: mcasp4_ahclkx_mux@4a009898 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; -+ bit-shift = <24>; -+ reg = <0x4a009898 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux@4a009898 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; -+ bit-shift = <22>; -+ reg = <0x4a009898 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+mcasp5_ahclkx_mux: mcasp5_ahclkx_mux@4a009878 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; -+ bit-shift = <24>; -+ reg = <0x4a009878 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux@4a009878 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; -+ bit-shift = <22>; -+ reg = <0x4a009878 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+mcasp6_ahclkx_mux: mcasp6_ahclkx_mux@4a009904 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; -+ bit-shift = <24>; -+ reg = <0x4a009904 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux@4a009904 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; -+ bit-shift = <22>; -+ reg = <0x4a009904 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+mcasp7_ahclkx_mux: mcasp7_ahclkx_mux@4a009908 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; -+ bit-shift = <24>; -+ reg = <0x4a009908 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux@4a009908 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; -+ bit-shift = <22>; -+ reg = <0x4a009908 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+mcasp8_ahclk_mux: mcasp8_ahclk_mux@4a009890 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; -+ bit-shift = <22>; -+ reg = <0x4a009890 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux@4a009890 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; -+ bit-shift = <24>; -+ reg = <0x4a009890 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+mmc1_fclk_mux: mmc1_fclk_mux@4a009328 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009328 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+mmc1_fclk_div: mmc1_fclk_div@4a009328 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&mmc1_fclk_mux>; -+ bit-shift = <25>; -+ reg = <0x4a009328 0x4>; -+ bit-mask = <0x3>; -+ index-power-of-two; -+}; -+ -+mmc2_fclk_mux: mmc2_fclk_mux@4a009330 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009330 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+mmc2_fclk_div: mmc2_fclk_div@4a009330 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&mmc2_fclk_mux>; -+ bit-shift = <25>; -+ reg = <0x4a009330 0x4>; -+ bit-mask = <0x3>; -+ index-power-of-two; -+}; -+ -+mmc3_gfclk_mux: mmc3_gfclk_mux@4a009820 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009820 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+mmc3_gfclk_div: mmc3_gfclk_div@4a009820 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&mmc3_gfclk_mux>; -+ bit-shift = <25>; -+ reg = <0x4a009820 0x4>; -+ bit-mask = <0x3>; -+ index-power-of-two; -+}; -+ -+mmc4_gfclk_mux: mmc4_gfclk_mux@4a009828 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009828 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+mmc4_gfclk_div: mmc4_gfclk_div@4a009828 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&mmc4_gfclk_mux>; -+ bit-shift = <25>; -+ reg = <0x4a009828 0x4>; -+ bit-mask = <0x3>; -+ index-power-of-two; -+}; -+ -+qspi_gfclk_mux: qspi_gfclk_mux@4a009838 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009838 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+qspi_gfclk_div: qspi_gfclk_div@4a009838 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&qspi_gfclk_mux>; -+ bit-shift = <25>; -+ reg = <0x4a009838 0x4>; -+ bit-mask = <0x3>; -+ index-power-of-two; -+}; -+ -+timer10_gfclk_mux: timer10_gfclk_mux@4a009728 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; -+ bit-shift = <24>; -+ reg = <0x4a009728 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+timer11_gfclk_mux: timer11_gfclk_mux@4a009730 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; -+ bit-shift = <24>; -+ reg = <0x4a009730 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+timer13_gfclk_mux: timer13_gfclk_mux@4a0097c8 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; -+ bit-shift = <24>; -+ reg = <0x4a0097c8 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+timer14_gfclk_mux: timer14_gfclk_mux@4a0097d0 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; -+ bit-shift = <24>; -+ reg = <0x4a0097d0 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+timer15_gfclk_mux: timer15_gfclk_mux@4a0097d8 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; -+ bit-shift = <24>; -+ reg = <0x4a0097d8 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+timer16_gfclk_mux: timer16_gfclk_mux@4a009830 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; -+ bit-shift = <24>; -+ reg = <0x4a009830 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+timer1_gfclk_mux: timer1_gfclk_mux@4ae07840 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; -+ bit-shift = <24>; -+ reg = <0x4ae07840 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+timer2_gfclk_mux: timer2_gfclk_mux@4a009738 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; -+ bit-shift = <24>; -+ reg = <0x4a009738 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+timer3_gfclk_mux: timer3_gfclk_mux@4a009740 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; -+ bit-shift = <24>; -+ reg = <0x4a009740 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+timer4_gfclk_mux: timer4_gfclk_mux@4a009748 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; -+ bit-shift = <24>; -+ reg = <0x4a009748 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+timer5_gfclk_mux: timer5_gfclk_mux@4a005558 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>; -+ bit-shift = <24>; -+ reg = <0x4a005558 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+timer6_gfclk_mux: timer6_gfclk_mux@4a005560 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>; -+ bit-shift = <24>; -+ reg = <0x4a005560 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+timer7_gfclk_mux: timer7_gfclk_mux@4a005568 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>; -+ bit-shift = <24>; -+ reg = <0x4a005568 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+timer8_gfclk_mux: timer8_gfclk_mux@4a005570 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>; -+ bit-shift = <24>; -+ reg = <0x4a005570 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+timer9_gfclk_mux: timer9_gfclk_mux@4a009750 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; -+ bit-shift = <24>; -+ reg = <0x4a009750 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+uart10_gfclk_mux: uart10_gfclk_mux@4ae07880 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; -+ bit-shift = <24>; -+ reg = <0x4ae07880 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+uart1_gfclk_mux: uart1_gfclk_mux@4a009840 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009840 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+uart2_gfclk_mux: uart2_gfclk_mux@4a009848 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009848 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+uart3_gfclk_mux: uart3_gfclk_mux@4a009850 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009850 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+uart4_gfclk_mux: uart4_gfclk_mux@4a009858 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009858 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+uart5_gfclk_mux: uart5_gfclk_mux@4a009870 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009870 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+uart6_gfclk_mux: uart6_gfclk_mux@4a005580 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; -+ bit-shift = <24>; -+ reg = <0x4a005580 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+uart7_gfclk_mux: uart7_gfclk_mux@4a0098d0 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; -+ bit-shift = <24>; -+ reg = <0x4a0098d0 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+uart8_gfclk_mux: uart8_gfclk_mux@4a0098e0 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; -+ bit-shift = <24>; -+ reg = <0x4a0098e0 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+uart9_gfclk_mux: uart9_gfclk_mux@4a0098e8 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; -+ bit-shift = <24>; -+ reg = <0x4a0098e8 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+vip1_gclk_mux: vip1_gclk_mux@4a009020 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009020 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+vip2_gclk_mux: vip2_gclk_mux@4a009028 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009028 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+vip3_gclk_mux: vip3_gclk_mux@4a009030 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009030 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { -+ compatible = "divider-clock"; -+ clocks = <&apll_pcie_ck>; -+ #clock-cells = <0>; -+ reg = <0x4a00821c 0x4>; -+ bit-mask = <0x100>; -+}; -+ -+optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 { -+ compatible = "gate-clock"; -+ clocks = <&apll_pcie_ck>; -+ #clock-cells = <0>; -+ reg = <0x4a0093b0 0x4>; -+ bit-shift = <9>; -+}; -+ -+optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 { -+ compatible = "gate-clock"; -+ clocks = <&optfclk_pciephy_div>; -+ #clock-cells = <0>; -+ reg = <0x4a0093b0 0x4>; -+ bit-shift = <10>; -+}; ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -186,9 +186,12 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420 - am335x-evmsk.dtb \ - am335x-bone.dtb \ - am335x-boneblack.dtb \ -+ am335x-evm-profile2.dtb \ - am3517-evm.dtb \ - am3517_mt_ventoux.dtb \ -- am43x-epos-evm.dtb -+ am43x-epos-evm.dtb \ -+ am437x-gp-evm.dtb \ -+ dra7-evm.dtb - dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb - dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb - dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \ ---- a/arch/arm/boot/dts/omap2420.dtsi -+++ b/arch/arm/boot/dts/omap2420.dtsi -@@ -114,6 +114,18 @@ - dma-names = "tx", "rx"; - }; - -+ mailbox: mailbox@48094000 { -+ compatible = "ti,omap2-mailbox"; -+ reg = <0x48094000 0x200>; -+ interrupts = <26>, /* DSP Interrupt */ -+ <34>; /* IVA Interrupt */ -+ ti,hwmods = "mailbox"; -+ ti,mbox-num-users = <4>; -+ ti,mbox-num-fifos = <6>; -+ ti,mbox-names = "dsp", "iva"; -+ ti,mbox-data = <0 1 0 0>, <2 3 1 3>; -+ }; -+ - timer1: timer@48028000 { - compatible = "ti,omap2420-timer"; - reg = <0x48028000 0x400>; ---- a/arch/arm/boot/dts/omap2430.dtsi -+++ b/arch/arm/boot/dts/omap2430.dtsi -@@ -175,6 +175,17 @@ - dma-names = "tx", "rx"; - }; - -+ mailbox: mailbox@48094000 { -+ compatible = "ti,omap2-mailbox"; -+ reg = <0x48094000 0x200>; -+ interrupts = <26>; -+ ti,hwmods = "mailbox"; -+ ti,mbox-num-users = <4>; -+ ti,mbox-num-fifos = <6>; -+ ti,mbox-names = "dsp"; -+ ti,mbox-data = <0 1 0 0>; -+ }; -+ - timer1: timer@49018000 { - compatible = "ti,omap2420-timer"; - reg = <0x49018000 0x400>; ---- /dev/null -+++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi -@@ -0,0 +1,158 @@ -+/* -+ * Device Tree Source for OMAP3430 ES1 clock data -+ * -+ * Copyright (C) 2013 Texas Instruments, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+gfx_l3_ck: gfx_l3_ck@48004b10 { -+ #clock-cells = <0>; -+ compatible = "ti,gate-clock"; -+ clocks = <&l3_ick>; -+ reg = <0x48004b10 0x4>; -+ ti,enable-bit = <0>; -+}; -+ -+gfx_l3_fck: gfx_l3_fck@48004b40 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&l3_ick>; -+ reg = <0x48004b40 0x4>; -+ bit-mask = <0x7>; -+ index-starts-at-one; -+}; -+ -+gfx_l3_ick: gfx_l3_ick { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&gfx_l3_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+gfx_cg1_ck: gfx_cg1_ck@48004b00 { -+ #clock-cells = <0>; -+ compatible = "ti,gate-clock"; -+ clocks = <&gfx_l3_fck>; -+ reg = <0x48004b00 0x4>; -+ ti,enable-bit = <1>; -+}; -+ -+gfx_cg2_ck: gfx_cg2_ck@48004b00 { -+ #clock-cells = <0>; -+ compatible = "ti,gate-clock"; -+ clocks = <&gfx_l3_fck>; -+ reg = <0x48004b00 0x4>; -+ ti,enable-bit = <2>; -+}; -+ -+d2d_26m_fck: d2d_26m_fck@48004a00 { -+ #clock-cells = <0>; -+ compatible = "ti,gate-clock"; -+ clocks = <&sys_ck>; -+ reg = <0x48004a00 0x4>; -+ ti,enable-bit = <3>; -+}; -+ -+fshostusb_fck: fshostusb_fck@48004a00 { -+ #clock-cells = <0>; -+ compatible = "ti,gate-clock"; -+ clocks = <&core_48m_fck>; -+ reg = <0x48004a00 0x4>; -+ ti,enable-bit = <5>; -+}; -+ -+ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1@48004a40 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&corex2_fck>; -+ bit-shift = <8>; -+ reg = <0x48004a40 0x4>; -+ table = < 1 1 >, < 2 2 >, < 3 3 >, < 4 4 >, < 6 6 >, < 8 8 >; -+ bit-mask = <0xf>; -+}; -+ -+ssi_ssr_fck_3430es1: ssi_ssr_fck_3430es1@48004a00 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&ssi_ssr_div_fck_3430es1>; -+ bit-shift = <0>; -+ reg = <0x48004a00 0x4>; -+}; -+ -+ssi_sst_fck_3430es1: ssi_sst_fck_3430es1 { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&ssi_ssr_fck_3430es1>; -+ clock-mult = <1>; -+ clock-div = <2>; -+}; -+ -+hsotgusb_ick: hsotgusb_ick@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-no-wait-interface-clock"; -+ clocks = <&core_l3_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <4>; -+}; -+ -+fac_ick: fac_ick@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&core_l4_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <8>; -+}; -+ -+ssi_l4_ick: ssi_l4_ick { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&l4_ick>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+ssi_ick_3430es1: ssi_ick_3430es1@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-no-wait-interface-clock"; -+ clocks = <&ssi_l4_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <0>; -+}; -+ -+usb_l4_div_ick: usb_l4_div_ick@48004a40 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&l4_ick>; -+ bit-shift = <4>; -+ reg = <0x48004a40 0x4>; -+ bit-mask = <0x3>; -+ index-starts-at-one; -+}; -+ -+usb_l4_ick: usb_l4_ick@48004a10 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&usb_l4_div_ick>; -+ bit-shift = <5>; -+ reg = <0x48004a10 0x4>; -+}; -+ -+dss1_alwon_fck_3430es1: dss1_alwon_fck_3430es1@48004e00 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dpll4_m4x2_ck>; -+ reg = <0x48004e00 0x4>; -+ bit-shift = <0>; -+}; -+ -+dss_ick_3430es1: dss_ick_3430es1@48004e10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-no-wait-interface-clock"; -+ clocks = <&l4_ick>; -+ reg = <0x48004e10 0x4>; -+ ti,enable-bit = <0>; -+}; ---- a/arch/arm/boot/dts/omap34xx.dtsi -+++ b/arch/arm/boot/dts/omap34xx.dtsi -@@ -25,4 +25,113 @@ - clock-latency = <300000>; /* From legacy driver */ - }; - }; --}; -+ -+ clocks { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ /include/ "omap34xx-omap36xx-clocks.dtsi" -+ /include/ "omap36xx-omap3430es2plus-clocks.dtsi" -+ /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" -+ }; -+ -+ clockdomains { -+ usbhost_clkdm: usbhost_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&usbhost_48m_fck>, <&usbhost_ick>; -+ }; -+ -+ wkup_clkdm: wkup_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&wdt1_ick>, <&gpt12_ick>, <&gpio1_ick>, -+ <&gpt1_ick>, <&omap_32ksync_ick>, <&wdt2_ick>, -+ <&wdt2_fck>; -+ }; -+ -+ cam_clkdm: cam_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&cam_ick>; -+ }; -+ -+ dpll4_clkdm: dpll4_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&dpll4_ck>; -+ }; -+ -+ sgx_clkdm: sgx_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&sgx_ick>; -+ }; -+ -+ dpll3_clkdm: dpll3_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&dpll3_ck>; -+ }; -+ -+ iva2_clkdm: iva2_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&iva2_ck>; -+ }; -+ -+ dpll1_clkdm: dpll1_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&dpll1_ck>; -+ }; -+ -+ dpll2_clkdm: dpll2_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&dpll2_ck>; -+ }; -+ -+ dpll5_clkdm: dpll5_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&dpll5_ck>; -+ }; -+ -+ dss_clkdm: dss_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>; -+ }; -+ -+ core_l4_clkdm: core_l4_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&mmchs1_ick>, <&mmchs2_ick>, <&hdq_fck>, -+ <&uart1_ick>, <&mcspi4_fck>, <&i2c3_fck>, -+ <&mcspi2_ick>, <&uart2_ick>, <&mcspi3_ick>, -+ <&i2c1_fck>, <&hdq_ick>, <&sha12_ick>, -+ <&mcbsp5_ick>, <&mcspi3_fck>, <&aes2_ick>, -+ <&mcspi1_ick>, <&uart2_fck>, <&mmchs2_fck>, -+ <&mmchs1_fck>, <&i2c3_ick>, <&mcspi1_fck>, -+ <&mcspi4_ick>, <&omapctrl_ick>, <&mcbsp1_ick>, -+ <&mcspi2_fck>, <&gpt10_ick>, <&i2c2_fck>, -+ <&i2c2_ick>, <&gpt11_ick>, <&i2c1_ick>, -+ <&uart1_fck>; -+ }; -+ -+ core_l3_clkdm: core_l3_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&sdrc_ick>; -+ }; -+ -+ per_clkdm: per_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&gpt2_ick>, <&uart3_fck>, <&gpio3_ick>, -+ <&mcbsp2_ick>, <&gpt6_ick>, <&mcbsp4_ick>, -+ <&gpt4_ick>, <&mcbsp3_ick>, <&gpt8_ick>, -+ <&uart3_ick>, <&gpt5_ick>, <&gpt7_ick>, -+ <&gpio2_ick>, <&gpio6_ick>, <&gpt9_ick>, -+ <&gpt3_ick>, <&gpio5_ick>, <&wdt3_ick>, -+ <&gpio4_ick>, <&wdt3_fck>, <&uart4_ick>; -+ }; -+ -+ emu_clkdm: emu_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&emu_src_ck>; -+ }; -+ -+ d2d_clkdm: d2d_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&mad2d_ick>, <&sad2d_ick>, <&modem_fck>; -+ }; -+ }; -+}; -\ No newline at end of file ---- /dev/null -+++ b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi -@@ -0,0 +1,222 @@ -+/* -+ * Device Tree Source for OMAP34xx/OMAP36xx clock data -+ * -+ * Copyright (C) 2013 Texas Instruments, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+security_l4_ick2: security_l4_ick2 { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&l4_ick>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+aes1_ick: aes1_ick@48004a14 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&security_l4_ick2>; -+ reg = <0x48004a14 0x4>; -+ ti,enable-bit = <3>; -+}; -+ -+rng_ick: rng_ick@48004a14 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&security_l4_ick2>; -+ reg = <0x48004a14 0x4>; -+ ti,enable-bit = <2>; -+}; -+ -+sha11_ick: sha11_ick@48004a14 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&security_l4_ick2>; -+ reg = <0x48004a14 0x4>; -+ ti,enable-bit = <1>; -+}; -+ -+des1_ick: des1_ick@48004a14 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&security_l4_ick2>; -+ reg = <0x48004a14 0x4>; -+ ti,enable-bit = <0>; -+}; -+ -+cam_mclk: cam_mclk@48004f00 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dpll4_m5x2_ck>; -+ bit-shift = <0>; -+ reg = <0x48004f00 0x4>; -+ set-rate-parent; -+}; -+ -+cam_ick: cam_ick@48004f10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-no-wait-interface-clock"; -+ clocks = <&l4_ick>; -+ reg = <0x48004f10 0x4>; -+ ti,enable-bit = <0>; -+}; -+ -+csi2_96m_fck: csi2_96m_fck@48004f00 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&core_96m_fck>; -+ reg = <0x48004f00 0x4>; -+ bit-shift = <1>; -+}; -+ -+security_l3_ick: security_l3_ick { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&l3_ick>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+pka_ick: pka_ick@48004a14 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&security_l3_ick>; -+ reg = <0x48004a14 0x4>; -+ ti,enable-bit = <4>; -+}; -+ -+icr_ick: icr_ick@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&core_l4_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <29>; -+}; -+ -+des2_ick: des2_ick@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&core_l4_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <26>; -+}; -+ -+mspro_ick: mspro_ick@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&core_l4_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <23>; -+}; -+ -+mailboxes_ick: mailboxes_ick@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&core_l4_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <7>; -+}; -+ -+ssi_l4_ick: ssi_l4_ick { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&l4_ick>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+sr1_fck: sr1_fck@48004c00 { -+ #clock-cells = <0>; -+ compatible = "ti,gate-clock"; -+ clocks = <&sys_ck>; -+ reg = <0x48004c00 0x4>; -+ ti,enable-bit = <6>; -+}; -+ -+sr2_fck: sr2_fck@48004c00 { -+ #clock-cells = <0>; -+ compatible = "ti,gate-clock"; -+ clocks = <&sys_ck>; -+ reg = <0x48004c00 0x4>; -+ ti,enable-bit = <7>; -+}; -+ -+sr_l4_ick: sr_l4_ick { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&l4_ick>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+dpll2_fck: dpll2_fck@48004040 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&core_ck>; -+ bit-shift = <19>; -+ reg = <0x48004040 0x4>; -+ bit-mask = <0x7>; -+ index-starts-at-one; -+}; -+ -+dpll2_ck: dpll2_ck@48004004 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-dpll-clock"; -+ clocks = <&sys_ck>, <&dpll2_fck>; -+ ti,modes = <0xa2>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+ reg = <0x48004004 0x4>, <0x48004024 0x4>, <0x48004034 0x4>, <0x48004040 0x4>; -+}; -+ -+dpll2_m2_ck: dpll2_m2_ck@48004044 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll2_ck>; -+ reg = <0x48004044 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+}; -+ -+iva2_ck: iva2_ck@48004000 { -+ #clock-cells = <0>; -+ compatible = "ti,gate-clock"; -+ clocks = <&dpll2_m2_ck>; -+ reg = <0x48004000 0x4>; -+ ti,enable-bit = <0>; -+}; -+ -+modem_fck: modem_fck@48004a00 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&sys_ck>; -+ reg = <0x48004a00 0x4>; -+ ti,enable-bit = <31>; -+}; -+ -+sad2d_ick: sad2d_ick@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&l3_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <3>; -+}; -+ -+mad2d_ick: mad2d_ick@48004a18 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&l3_ick>; -+ reg = <0x48004a18 0x4>; -+ ti,enable-bit = <3>; -+}; -+ -+mspro_fck: mspro_fck@48004a00 { -+ #clock-cells = <0>; -+ compatible = "ti,gate-clock"; -+ clocks = <&core_96m_fck>; -+ reg = <0x48004a00 0x4>; -+ ti,enable-bit = <23>; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi -@@ -0,0 +1,196 @@ -+/* -+ * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data -+ * -+ * Copyright (C) 2013 Texas Instruments, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+dpll5_ck: dpll5_ck@48004d04 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-dpll-clock"; -+ clocks = <&sys_ck>, <&sys_ck>; -+ ti,modes = <0x82>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+ reg = <0x48004d04 0x4>, <0x48004d24 0x4>, <0x48004d34 0x4>, <0x48004d4c 0x4>; -+}; -+ -+dpll5_m2_ck: dpll5_m2_ck@48004d50 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll5_ck>; -+ reg = <0x48004d50 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+}; -+ -+core_d3_ck: core_d3_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&core_ck>; -+ clock-mult = <1>; -+ clock-div = <3>; -+}; -+ -+core_d4_ck: core_d4_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&core_ck>; -+ clock-mult = <1>; -+ clock-div = <4>; -+}; -+ -+core_d6_ck: core_d6_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&core_ck>; -+ clock-mult = <1>; -+ clock-div = <6>; -+}; -+ -+omap_192m_alwon_fck: omap_192m_alwon_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll4_m2x2_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+core_d2_ck: core_d2_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&core_ck>; -+ clock-mult = <1>; -+ clock-div = <2>; -+}; -+ -+corex2_d3_fck: corex2_d3_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&corex2_fck>; -+ clock-mult = <1>; -+ clock-div = <3>; -+}; -+ -+corex2_d5_fck: corex2_d5_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&corex2_fck>; -+ clock-mult = <1>; -+ clock-div = <5>; -+}; -+ -+sgx_mux_fck: sgx_mux_fck@48004b40 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>; -+ reg = <0x48004b40 0x4>; -+ table = <&core_d3_ck 0>, <&core_d4_ck 1>, <&core_d6_ck 2>, <&cm_96m_fck 3>, <&omap_192m_alwon_fck 4>, <&core_d2_ck 5>, <&corex2_d3_fck 6>, <&corex2_d5_fck 7>; -+ bit-mask = <0x7>; -+}; -+ -+sgx_fck: sgx_fck@48004b00 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sgx_mux_fck>; -+ bit-shift = <1>; -+ reg = <0x48004b00 0x4>; -+}; -+ -+sgx_ick: sgx_ick@48004b10 { -+ #clock-cells = <0>; -+ compatible = "ti,gate-clock"; -+ clocks = <&l3_ick>; -+ reg = <0x48004b10 0x4>; -+ ti,enable-bit = <0>; -+}; -+ -+cpefuse_fck: cpefuse_fck@48004a08 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_ck>; -+ reg = <0x48004a08 0x4>; -+ bit-shift = <0>; -+}; -+ -+ts_fck: ts_fck@48004a08 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&omap_32k_fck>; -+ reg = <0x48004a08 0x4>; -+ bit-shift = <1>; -+}; -+ -+usbtll_fck: usbtll_fck@48004a08 { -+ #clock-cells = <0>; -+ compatible = "ti,gate-clock"; -+ clocks = <&dpll5_m2_ck>; -+ reg = <0x48004a08 0x4>; -+ ti,enable-bit = <2>; -+}; -+ -+usbtll_ick: usbtll_ick@48004a18 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&core_l4_ick>; -+ reg = <0x48004a18 0x4>; -+ ti,enable-bit = <2>; -+}; -+ -+mmchs3_ick: mmchs3_ick@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&core_l4_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <30>; -+}; -+ -+mmchs3_fck: mmchs3_fck@48004a00 { -+ #clock-cells = <0>; -+ compatible = "ti,gate-clock"; -+ clocks = <&core_96m_fck>; -+ reg = <0x48004a00 0x4>; -+ ti,enable-bit = <30>; -+}; -+ -+dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2@48004e00 { -+ #clock-cells = <0>; -+ compatible = "ti,dss-gate-clock"; -+ clocks = <&dpll4_m4x2_ck>; -+ reg = <0x48004e00 0x4>; -+ ti,enable-bit = <0>; -+}; -+ -+dss_ick_3430es2: dss_ick_3430es2@48004e10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-dss-interface-clock"; -+ clocks = <&l4_ick>; -+ reg = <0x48004e10 0x4>; -+ ti,enable-bit = <0>; -+}; -+ -+usbhost_120m_fck: usbhost_120m_fck@48005400 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dpll5_m2_ck>; -+ reg = <0x48005400 0x4>; -+ bit-shift = <1>; -+}; -+ -+usbhost_48m_fck: usbhost_48m_fck@48005400 { -+ #clock-cells = <0>; -+ compatible = "ti,dss-gate-clock"; -+ clocks = <&omap_48m_fck>; -+ reg = <0x48005400 0x4>; -+ ti,enable-bit = <0>; -+}; -+ -+usbhost_ick: usbhost_ick@48005410 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-dss-interface-clock"; -+ clocks = <&l4_ick>; -+ reg = <0x48005410 0x4>; -+ ti,enable-bit = <0>; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/omap36xx-clocks.dtsi -@@ -0,0 +1,80 @@ -+/* -+ * Device Tree Source for OMAP36xx clock data -+ * -+ * Copyright (C) 2013 Texas Instruments, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+dpll4_ck: dpll4_ck@48004d00 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-dpll-per-j-type-clock"; -+ clocks = <&sys_ck>, <&sys_ck>; -+ ti,modes = <0x82>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+ reg = <0x48004d00 0x4>, <0x48004d20 0x4>, <0x48004d30 0x4>, <0x48004d44 0x4>; -+}; -+ -+dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 { -+ #clock-cells = <0>; -+ compatible = "ti,hsdiv-gate-clock"; -+ clocks = <&dpll4_m2x2_mul_ck>; -+ reg = <0x48004d00 0x4>; -+ ti,enable-bit = <0x1b>; -+ ti,set-bit-to-disable; -+}; -+ -+dpll3_m3x2_ck: dpll3_m3x2_ck@48004d00 { -+ #clock-cells = <0>; -+ compatible = "ti,hsdiv-gate-clock"; -+ clocks = <&dpll3_m3x2_mul_ck>; -+ reg = <0x48004d00 0x4>; -+ ti,enable-bit = <0xc>; -+ ti,set-bit-to-disable; -+}; -+ -+dpll4_m3x2_ck: dpll4_m3x2_ck@48004d00 { -+ #clock-cells = <0>; -+ compatible = "ti,hsdiv-gate-clock"; -+ clocks = <&dpll4_m3x2_mul_ck>; -+ reg = <0x48004d00 0x4>; -+ ti,enable-bit = <0x1c>; -+ ti,set-bit-to-disable; -+}; -+ -+dpll4_m5x2_ck: dpll4_m5x2_ck@48004d00 { -+ #clock-cells = <0>; -+ compatible = "ti,hsdiv-gate-clock"; -+ clocks = <&dpll4_m5x2_mul_ck>; -+ reg = <0x48004d00 0x4>; -+ ti,enable-bit = <0x1e>; -+ ti,set-rate-parent; -+ ti,set-bit-to-disable; -+}; -+ -+dpll4_m6x2_ck: dpll4_m6x2_ck@48004d00 { -+ #clock-cells = <0>; -+ compatible = "ti,hsdiv-gate-clock"; -+ clocks = <&dpll4_m6x2_mul_ck>; -+ reg = <0x48004d00 0x4>; -+ ti,enable-bit = <0x1f>; -+ ti,set-bit-to-disable; -+}; -+ -+omap_192m_alwon_fck: omap_192m_alwon_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll4_m2x2_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+uart4_fck: uart4_fck@48005000 { -+ #clock-cells = <0>; -+ compatible = "ti,gate-clock"; -+ clocks = <&per_48m_fck>; -+ reg = <0x48005000 0x4>; -+ ti,enable-bit = <18>; -+}; ---- a/arch/arm/boot/dts/omap36xx.dtsi -+++ b/arch/arm/boot/dts/omap36xx.dtsi -@@ -35,4 +35,114 @@ - clock-frequency = <48000000>; - }; - }; --}; -+ -+ clocks { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ /include/ "omap36xx-clocks.dtsi" -+ /include/ "omap34xx-omap36xx-clocks.dtsi" -+ /include/ "omap36xx-omap3430es2plus-clocks.dtsi" -+ /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" -+ }; -+ -+ clockdomains { -+ usbhost_clkdm: usbhost_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&usbhost_48m_fck>, <&usbhost_ick>; -+ }; -+ -+ wkup_clkdm: wkup_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&wdt1_ick>, <&gpt12_ick>, <&gpio1_ick>, -+ <&gpt1_ick>, <&omap_32ksync_ick>, <&wdt2_ick>, -+ <&wdt2_fck>; -+ }; -+ -+ cam_clkdm: cam_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&cam_ick>; -+ }; -+ -+ dpll4_clkdm: dpll4_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&dpll4_ck>; -+ }; -+ -+ sgx_clkdm: sgx_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&sgx_ick>; -+ }; -+ -+ dpll3_clkdm: dpll3_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&dpll3_ck>; -+ }; -+ -+ iva2_clkdm: iva2_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&iva2_ck>; -+ }; -+ -+ dpll1_clkdm: dpll1_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&dpll1_ck>; -+ }; -+ -+ dpll5_clkdm: dpll5_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&dpll5_ck>; -+ }; -+ -+ dpll2_clkdm: dpll2_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&dpll2_ck>; -+ }; -+ -+ dss_clkdm: dss_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>; -+ }; -+ -+ core_l4_clkdm: core_l4_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&mmchs1_ick>, <&mmchs2_ick>, <&hdq_fck>, -+ <&uart1_ick>, <&mcspi4_fck>, <&i2c3_fck>, -+ <&mcspi2_ick>, <&uart2_ick>, <&mcspi3_ick>, -+ <&i2c1_fck>, <&hdq_ick>, <&sha12_ick>, -+ <&mcbsp5_ick>, <&mcspi3_fck>, <&aes2_ick>, -+ <&mcspi1_ick>, <&uart2_fck>, <&mmchs2_fck>, -+ <&mmchs1_fck>, <&i2c3_ick>, <&mcspi1_fck>, -+ <&mcspi4_ick>, <&omapctrl_ick>, <&mcbsp1_ick>, -+ <&mcspi2_fck>, <&gpt10_ick>, <&i2c2_fck>, -+ <&i2c2_ick>, <&gpt11_ick>, <&i2c1_ick>, -+ <&uart1_fck>; -+ }; -+ -+ core_l3_clkdm: core_l3_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&sdrc_ick>; -+ }; -+ -+ per_clkdm: per_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&gpt2_ick>, <&uart3_fck>, <&gpio3_ick>, -+ <&mcbsp2_ick>, <&gpt6_ick>, <&mcbsp4_ick>, -+ <&gpt4_ick>, <&mcbsp3_ick>, <&gpt8_ick>, -+ <&uart3_ick>, <&gpt5_ick>, <&gpt7_ick>, -+ <&gpio2_ick>, <&gpio6_ick>, <&gpt9_ick>, -+ <&gpt3_ick>, <&gpio5_ick>, <&wdt3_ick>, -+ <&gpio4_ick>, <&wdt3_fck>, <&uart4_ick>; -+ }; -+ -+ emu_clkdm: emu_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&emu_src_ck>; -+ }; -+ -+ d2d_clkdm: d2d_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&mad2d_ick>, <&sad2d_ick>, <&modem_fck>; -+ }; -+ }; -+}; -\ No newline at end of file ---- /dev/null -+++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi -@@ -0,0 +1,175 @@ -+/* -+ * Device Tree Source for OMAP34xx/OMAP36xx clock data -+ * -+ * Copyright (C) 2013 Texas Instruments, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@48004a40 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&corex2_fck>; -+ bit-shift = <8>; -+ reg = <0x48004a40 0x4>; -+ table = < 1 1 >, < 2 2 >, < 3 3 >, < 4 4 >, < 6 6 >, < 8 8 >; -+ bit-mask = <0xf>; -+}; -+ -+ssi_ssr_fck_3430es2: ssi_ssr_fck_3430es2@48004a00 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&ssi_ssr_div_fck_3430es2>; -+ bit-shift = <0>; -+ reg = <0x48004a00 0x4>; -+}; -+ -+ssi_sst_fck_3430es2: ssi_sst_fck_3430es2 { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&ssi_ssr_fck_3430es2>; -+ clock-mult = <1>; -+ clock-div = <2>; -+}; -+ -+hsotgusb_ick: hsotgusb_ick@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-hsotgusb-interface-clock"; -+ clocks = <&core_l3_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <4>; -+}; -+ -+ssi_l4_ick: ssi_l4_ick { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&l4_ick>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+ssi_ick_3430es2: ssi_ick_3430es2@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-ssi-interface-clock"; -+ clocks = <&ssi_l4_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <0>; -+}; -+ -+dpll5_ck: dpll5_ck@48004d04 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-dpll-clock"; -+ clocks = <&sys_ck>, <&sys_ck>; -+ ti,modes = <0x82>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+ reg = <0x48004d04 0x4>, <0x48004d24 0x4>, <0x48004d34 0x4>, <0x48004d4c 0x4>; -+}; -+ -+dpll5_m2_ck: dpll5_m2_ck@48004d50 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll5_ck>; -+ reg = <0x48004d50 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+}; -+ -+dpll5_m2_d20_ck: dpll5_m2_d20_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll5_m2_ck>; -+ clock-mult = <1>; -+ clock-div = <20>; -+}; -+ -+sys_d2_ck: sys_d2_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&sys_ck>; -+ clock-mult = <1>; -+ clock-div = <2>; -+}; -+ -+omap_96m_d2_fck: omap_96m_d2_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&omap_96m_fck>; -+ clock-mult = <1>; -+ clock-div = <2>; -+}; -+ -+omap_96m_d4_fck: omap_96m_d4_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&omap_96m_fck>; -+ clock-mult = <1>; -+ clock-div = <4>; -+}; -+ -+omap_96m_d8_fck: omap_96m_d8_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&omap_96m_fck>; -+ clock-mult = <1>; -+ clock-div = <8>; -+}; -+ -+omap_96m_d10_fck: omap_96m_d10_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&omap_96m_fck>; -+ clock-mult = <1>; -+ clock-div = <10>; -+}; -+ -+dpll5_m2_d4_ck: dpll5_m2_d4_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll5_m2_ck>; -+ clock-mult = <1>; -+ clock-div = <4>; -+}; -+ -+dpll5_m2_d8_ck: dpll5_m2_d8_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll5_m2_ck>; -+ clock-mult = <1>; -+ clock-div = <8>; -+}; -+ -+dpll5_m2_d16_ck: dpll5_m2_d16_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll5_m2_ck>; -+ clock-mult = <1>; -+ clock-div = <16>; -+}; -+ -+usim_mux_fck: usim_mux_fck@48004c40 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_ck>, <&dpll5_m2_d20_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>; -+ bit-shift = <3>; -+ reg = <0x48004c40 0x4>; -+ table = <&sys_ck 1>, <&dpll5_m2_d20_ck 10>, <&sys_d2_ck 2>, <&omap_96m_d2_fck 3>, <&omap_96m_d4_fck 4>, <&omap_96m_d8_fck 5>, <&omap_96m_d10_fck 6>, <&dpll5_m2_d4_ck 7>, <&dpll5_m2_d8_ck 8>, <&dpll5_m2_d16_ck 9>; -+ bit-mask = <0xf>; -+}; -+ -+usim_fck: usim_fck@48004c00 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&usim_mux_fck>; -+ bit-shift = <9>; -+ reg = <0x48004c00 0x4>; -+}; -+ -+usim_ick: usim_ick@48004c10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&wkup_l4_ick>; -+ reg = <0x48004c10 0x4>; -+ ti,enable-bit = <9>; -+}; ---- a/arch/arm/boot/dts/omap3-beagle.dts -+++ b/arch/arm/boot/dts/omap3-beagle.dts -@@ -44,17 +44,6 @@ - }; - }; - -- /* HS USB Port 2 RESET */ -- hsusb2_reset: hsusb2_reset_reg { -- compatible = "regulator-fixed"; -- regulator-name = "hsusb2_reset"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- gpio = <&gpio5 19 0>; /* gpio_147 */ -- startup-delay-us = <70000>; -- enable-active-high; -- }; -- - /* HS USB Port 2 Power */ - hsusb2_power: hsusb2_power_reg { - compatible = "regulator-fixed"; -@@ -68,7 +57,7 @@ - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { - compatible = "usb-nop-xceiv"; -- reset-supply = <&hsusb2_reset>; -+ reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */ - vcc-supply = <&hsusb2_power>; - }; - -@@ -101,18 +90,18 @@ - - hsusbb2_pins: pinmux_hsusbb2_pins { - pinctrl-single,pins = < -- 0x5c0 (PIN_OUTPUT | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_clk */ -- 0x5c2 (PIN_OUTPUT | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_stp */ -- 0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dir */ -- 0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_nxt */ -- 0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat0 */ -- 0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat1 */ -- 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat2 */ -- 0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat3 */ -- 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat4 */ -- 0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat5 */ -- 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat6 */ -- 0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat7 */ -+ 0x5c0 (PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ -+ 0x5c2 (PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ -+ 0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ -+ 0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ -+ 0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ -+ 0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ -+ 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ -+ 0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ -+ 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ -+ 0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ -+ 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ -+ 0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ - >; - }; - -@@ -180,3 +169,39 @@ - pinctrl-names = "default"; - pinctrl-0 = <&gpio1_pins>; - }; -+ -+&usb_otg_hs { -+ interface-type = <0>; -+ usb-phy = <&usb2_phy>; -+ mode = <3>; -+ power = <50>; -+}; -+ -+&dpi { -+ vdds_dsi-supply = <&vpll2>; -+}; -+ -+/ { -+ aliases { -+ display0 = &dvi0; -+ display1 = &tv0; -+ }; -+ -+ tfp410: encoder@0 { -+ compatible = "ti,tfp410"; -+ video-source = <&dpi>; -+ data-lines = <24>; -+ gpios = <&gpio5 10 0>; /* 170, power-down */ -+ }; -+ -+ dvi0: connector@0 { -+ compatible = "ti,dvi_connector"; -+ video-source = <&tfp410>; -+ i2c-bus = <&i2c3>; -+ }; -+ -+ tv0: connector@1 { -+ compatible = "ti,svideo_connector"; -+ video-source = <&venc>; -+ }; -+}; ---- a/arch/arm/boot/dts/omap3-beagle-xm.dts -+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts -@@ -69,6 +69,23 @@ - }; - - }; -+ -+ /* HS USB Port 2 Power */ -+ hsusb2_power: hsusb2_power_reg { -+ compatible = "regulator-fixed"; -+ regulator-name = "hsusb2_vbus"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&twl_gpio 18 0>; /* GPIO LEDA */ -+ startup-delay-us = <70000>; -+ }; -+ -+ /* HS USB Host PHY on PORT 2 */ -+ hsusb2_phy: hsusb2_phy { -+ compatible = "usb-nop-xceiv"; -+ reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */ -+ vcc-supply = <&hsusb2_power>; -+ }; - }; - - &omap3_pmx_wkup { -@@ -79,6 +96,37 @@ - }; - }; - -+&omap3_pmx_core { -+ pinctrl-names = "default"; -+ pinctrl-0 = < -+ &hsusbb2_pins -+ >; -+ -+ uart3_pins: pinmux_uart3_pins { -+ pinctrl-single,pins = < -+ 0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ -+ 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */ -+ >; -+ }; -+ -+ hsusbb2_pins: pinmux_hsusbb2_pins { -+ pinctrl-single,pins = < -+ 0x5c0 (PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ -+ 0x5c2 (PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ -+ 0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ -+ 0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ -+ 0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ -+ 0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ -+ 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ -+ 0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ -+ 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ -+ 0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ -+ 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ -+ 0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ -+ >; -+ }; -+}; -+ - &i2c1 { - clock-frequency = <2600000>; - -@@ -144,19 +192,12 @@ - &usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; -+ phys = <&usb2_phy>; -+ phy-names = "usb2-phy"; - mode = <3>; - power = <50>; - }; - --&omap3_pmx_core { -- uart3_pins: pinmux_uart3_pins { -- pinctrl-single,pins = < -- 0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ -- 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */ -- >; -- }; --}; -- - &uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -@@ -166,3 +207,11 @@ - pinctrl-names = "default"; - pinctrl-0 = <&gpio1_pins>; - }; -+ -+&usbhshost { -+ port2-mode = "ehci-phy"; -+}; -+ -+&usbhsehci { -+ phys = <0 &hsusb2_phy>; -+}; ---- a/arch/arm/boot/dts/omap3.dtsi -+++ b/arch/arm/boot/dts/omap3.dtsi -@@ -19,6 +19,9 @@ - interrupt-parent = <&intc>; - - aliases { -+ i2c0 = &i2c1; -+ i2c1 = &i2c2; -+ i2c2 = &i2c3; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; -@@ -32,6 +35,11 @@ - compatible = "arm,cortex-a8"; - device_type = "cpu"; - reg = <0x0>; -+ -+ clocks = <&dpll1_ck>; -+ clock-names = "cpu"; -+ -+ clock-latency = <300000>; /* From omap-cpufreq driver */ - }; - }; - -@@ -80,6 +88,8 @@ - compatible = "ti,omap-counter32k"; - reg = <0x48320000 0x20>; - ti,hwmods = "counter_32k"; -+ clocks = <&wkup_32k_fck>; -+ clock-names = "fck"; - }; - - intc: interrupt-controller@48200000 { -@@ -100,6 +110,8 @@ - #dma-cells = <1>; - #dma-channels = <32>; - #dma-requests = <96>; -+ clocks = <&core_l3_ick>; -+ clock-names = "fck"; - }; - - omap3_pmx_core: pinmux@48002030 { -@@ -125,6 +137,8 @@ - reg = <0x48310000 0x200>; - interrupts = <29>; - ti,hwmods = "gpio1"; -+ clocks = <&gpio1_ick>, <&gpio1_dbck>; -+ clock-names = "fck", "dbclk"; - ti,gpio-always-on; - gpio-controller; - #gpio-cells = <2>; -@@ -137,6 +151,8 @@ - reg = <0x49050000 0x200>; - interrupts = <30>; - ti,hwmods = "gpio2"; -+ clocks = <&gpio2_ick>, <&gpio2_dbck>; -+ clock-names = "fck", "dbclk"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; -@@ -148,6 +164,8 @@ - reg = <0x49052000 0x200>; - interrupts = <31>; - ti,hwmods = "gpio3"; -+ clocks = <&gpio3_ick>, <&gpio3_dbck>; -+ clock-names = "fck", "dbclk"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; -@@ -159,6 +177,8 @@ - reg = <0x49054000 0x200>; - interrupts = <32>; - ti,hwmods = "gpio4"; -+ clocks = <&gpio4_ick>, <&gpio4_dbck>; -+ clock-names = "fck", "dbclk"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; -@@ -170,6 +190,8 @@ - reg = <0x49056000 0x200>; - interrupts = <33>; - ti,hwmods = "gpio5"; -+ clocks = <&gpio5_ick>, <&gpio5_dbck>; -+ clock-names = "fck", "dbclk"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; -@@ -181,6 +203,8 @@ - reg = <0x49058000 0x200>; - interrupts = <34>; - ti,hwmods = "gpio6"; -+ clocks = <&gpio6_ick>, <&gpio6_dbck>; -+ clock-names = "fck", "dbclk"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; -@@ -190,18 +214,24 @@ - uart1: serial@4806a000 { - compatible = "ti,omap3-uart"; - ti,hwmods = "uart1"; -+ clocks = <&uart1_fck>; -+ clock-names = "fck"; - clock-frequency = <48000000>; - }; - - uart2: serial@4806c000 { - compatible = "ti,omap3-uart"; - ti,hwmods = "uart2"; -+ clocks = <&uart2_fck>; -+ clock-names = "fck"; - clock-frequency = <48000000>; - }; - - uart3: serial@49020000 { - compatible = "ti,omap3-uart"; - ti,hwmods = "uart3"; -+ clocks = <&uart3_fck>; -+ clock-names = "fck"; - clock-frequency = <48000000>; - }; - -@@ -210,6 +240,8 @@ - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c1"; -+ clocks = <&i2c1_fck>; -+ clock-names = "fck"; - }; - - i2c2: i2c@48072000 { -@@ -217,6 +249,8 @@ - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c2"; -+ clocks = <&i2c2_fck>; -+ clock-names = "fck"; - }; - - i2c3: i2c@48060000 { -@@ -224,6 +258,8 @@ - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c3"; -+ clocks = <&i2c3_fck>; -+ clock-names = "fck"; - }; - - mcspi1: spi@48098000 { -@@ -231,6 +267,8 @@ - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi1"; -+ clocks = <&mcspi1_fck>; -+ clock-names = "fck"; - ti,spi-num-cs = <4>; - dmas = <&sdma 35>, - <&sdma 36>, -@@ -249,6 +287,8 @@ - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi2"; -+ clocks = <&mcspi2_fck>; -+ clock-names = "fck"; - ti,spi-num-cs = <2>; - dmas = <&sdma 43>, - <&sdma 44>, -@@ -262,6 +302,8 @@ - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi3"; -+ clocks = <&mcspi3_fck>; -+ clock-names = "fck"; - ti,spi-num-cs = <2>; - dmas = <&sdma 15>, - <&sdma 16>, -@@ -275,6 +317,8 @@ - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi4"; -+ clocks = <&mcspi4_fck>; -+ clock-names = "fck"; - ti,spi-num-cs = <1>; - dmas = <&sdma 70>, <&sdma 71>; - dma-names = "tx0", "rx0"; -@@ -283,6 +327,8 @@ - mmc1: mmc@4809c000 { - compatible = "ti,omap3-hsmmc"; - ti,hwmods = "mmc1"; -+ clocks = <&mmchs1_fck>, <&omap_32k_fck>; -+ clock-names = "fck", "dbck"; - ti,dual-volt; - dmas = <&sdma 61>, <&sdma 62>; - dma-names = "tx", "rx"; -@@ -291,6 +337,8 @@ - mmc2: mmc@480b4000 { - compatible = "ti,omap3-hsmmc"; - ti,hwmods = "mmc2"; -+ clocks = <&mmchs2_fck>, <&omap_32k_fck>; -+ clock-names = "fck", "dbck"; - dmas = <&sdma 47>, <&sdma 48>; - dma-names = "tx", "rx"; - }; -@@ -298,6 +346,8 @@ - mmc3: mmc@480ad000 { - compatible = "ti,omap3-hsmmc"; - ti,hwmods = "mmc3"; -+ clocks = <&mmchs3_fck>, <&omap_32k_fck>; -+ clock-names = "fck", "dbck"; - dmas = <&sdma 77>, <&sdma 78>; - dma-names = "tx", "rx"; - }; -@@ -305,6 +355,8 @@ - wdt2: wdt@48314000 { - compatible = "ti,omap3-wdt"; - ti,hwmods = "wd_timer2"; -+ clocks = <&wdt2_fck>; -+ clock-names = "fck"; - }; - - mcbsp1: mcbsp@48074000 { -@@ -317,6 +369,8 @@ - interrupt-names = "common", "tx", "rx"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp1"; -+ clocks = <&mcbsp1_fck>, <&mcbsp_clks>, <&core_96m_fck>; -+ clock-names = "fck", "pad_fck", "prcm_fck"; - dmas = <&sdma 31>, - <&sdma 32>; - dma-names = "tx", "rx"; -@@ -366,6 +420,8 @@ - interrupt-names = "common", "tx", "rx"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp4"; -+ clocks = <&mcbsp4_fck>, <&mcbsp_clks>, <&per_96m_fck>; -+ clock-names = "fck", "pad_fck", "prcm_fck"; - dmas = <&sdma 19>, - <&sdma 20>; - dma-names = "tx", "rx"; -@@ -381,16 +437,31 @@ - interrupt-names = "common", "tx", "rx"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp5"; -+ clocks = <&mcbsp5_fck>, <&mcbsp_clks>, <&core_96m_fck>; -+ clock-names = "fck", "pad_fck", "prcm_fck"; - dmas = <&sdma 21>, - <&sdma 22>; - dma-names = "tx", "rx"; - }; - -+ mailbox: mailbox@48094000 { -+ compatible = "ti,omap2-mailbox"; -+ reg = <0x48094000 0x200>; -+ interrupts = <26>; -+ ti,hwmods = "mailbox"; -+ ti,mbox-num-users = <2>; -+ ti,mbox-num-fifos = <2>; -+ ti,mbox-names = "dsp"; -+ ti,mbox-data = <0 1 0 0>; -+ }; -+ - timer1: timer@48318000 { - compatible = "ti,omap3430-timer"; - reg = <0x48318000 0x400>; - interrupts = <37>; - ti,hwmods = "timer1"; -+ clocks = <&gpt1_fck>; -+ clock-names = "fck"; - ti,timer-alwon; - }; - -@@ -399,6 +470,8 @@ - reg = <0x49032000 0x400>; - interrupts = <38>; - ti,hwmods = "timer2"; -+ clocks = <&gpt2_fck>; -+ clock-names = "fck"; - }; - - timer3: timer@49034000 { -@@ -406,6 +479,8 @@ - reg = <0x49034000 0x400>; - interrupts = <39>; - ti,hwmods = "timer3"; -+ clocks = <&gpt3_fck>; -+ clock-names = "fck"; - }; - - timer4: timer@49036000 { -@@ -413,6 +488,8 @@ - reg = <0x49036000 0x400>; - interrupts = <40>; - ti,hwmods = "timer4"; -+ clocks = <&gpt4_fck>; -+ clock-names = "fck"; - }; - - timer5: timer@49038000 { -@@ -420,6 +497,8 @@ - reg = <0x49038000 0x400>; - interrupts = <41>; - ti,hwmods = "timer5"; -+ clocks = <&gpt5_fck>; -+ clock-names = "fck"; - ti,timer-dsp; - }; - -@@ -428,6 +507,8 @@ - reg = <0x4903a000 0x400>; - interrupts = <42>; - ti,hwmods = "timer6"; -+ clocks = <&gpt6_fck>; -+ clock-names = "fck"; - ti,timer-dsp; - }; - -@@ -436,6 +517,8 @@ - reg = <0x4903c000 0x400>; - interrupts = <43>; - ti,hwmods = "timer7"; -+ clocks = <&gpt7_fck>; -+ clock-names = "fck"; - ti,timer-dsp; - }; - -@@ -444,6 +527,8 @@ - reg = <0x4903e000 0x400>; - interrupts = <44>; - ti,hwmods = "timer8"; -+ clocks = <&gpt8_fck>; -+ clock-names = "fck"; - ti,timer-pwm; - ti,timer-dsp; - }; -@@ -453,6 +538,8 @@ - reg = <0x49040000 0x400>; - interrupts = <45>; - ti,hwmods = "timer9"; -+ clocks = <&gpt9_fck>; -+ clock-names = "fck"; - ti,timer-pwm; - }; - -@@ -461,6 +548,8 @@ - reg = <0x48086000 0x400>; - interrupts = <46>; - ti,hwmods = "timer10"; -+ clocks = <&gpt10_fck>; -+ clock-names = "fck"; - ti,timer-pwm; - }; - -@@ -469,6 +558,8 @@ - reg = <0x48088000 0x400>; - interrupts = <47>; - ti,hwmods = "timer11"; -+ clocks = <&gpt11_fck>; -+ clock-names = "fck"; - ti,timer-pwm; - }; - -@@ -477,6 +568,8 @@ - reg = <0x48304000 0x400>; - interrupts = <95>; - ti,hwmods = "timer12"; -+ clocks = <&gpt12_fck>; -+ clock-names = "fck"; - ti,timer-alwon; - ti,timer-secure; - }; -@@ -486,12 +579,16 @@ - reg = <0x48062000 0x1000>; - interrupts = <78>; - ti,hwmods = "usb_tll_hs"; -+ clocks = <&usbtll_fck>; -+ clock-names = "fck"; - }; - - usbhshost: usbhshost@48064000 { - compatible = "ti,usbhs-host"; - reg = <0x48064000 0x400>; - ti,hwmods = "usb_host_hs"; -+ clocks = <&usbhost_48m_fck>, <&usbhost_120m_fck>; -+ clock-names = "fck", "ehci_logic_fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges; -@@ -514,6 +611,8 @@ - gpmc: gpmc@6e000000 { - compatible = "ti,omap3430-gpmc"; - ti,hwmods = "gpmc"; -+ clocks = <&gpmc_fck>; -+ clock-names = "fck"; - reg = <0x6e000000 0x02d0>; - interrupts = <20>; - gpmc,num-cs = <8>; -@@ -528,9 +627,61 @@ - interrupts = <92>, <93>; - interrupt-names = "mc", "dma"; - ti,hwmods = "usb_otg_hs"; -+ clocks = <&hsotgusb_ick>; -+ clock-names = "fck"; - multipoint = <1>; - num-eps = <16>; - ram-bits = <12>; - }; -+ -+ dss@48050000 { -+ compatible = "ti,omap3-dss", "simple-bus"; -+ reg = <0x48050000 0x200>; -+ ti,hwmods = "dss_core"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ dispc@48050400 { -+ compatible = "ti,omap3-dispc"; -+ reg = <0x48050400 0x400>; -+ interrupts = <25>; -+ ti,hwmods = "dss_dispc"; -+ }; -+ -+ dpi: encoder@0 { -+ compatible = "ti,omap3-dpi"; -+ }; -+ -+ sdi: encoder@1 { -+ compatible = "ti,omap3-sdi"; -+ }; -+ -+ dsi: encoder@4804fc00 { -+ compatible = "ti,omap3-dsi"; -+ reg = <0x4804fc00 0x400>; -+ interrupts = <25>; -+ ti,hwmods = "dss_dsi1"; -+ }; -+ -+ rfbi: encoder@48050800 { -+ compatible = "ti,omap3-rfbi"; -+ reg = <0x48050800 0x100>; -+ ti,hwmods = "dss_rfbi"; -+ }; -+ -+ venc: encoder@48050c00 { -+ compatible = "ti,omap3-venc"; -+ reg = <0x48050c00 0x100>; -+ ti,hwmods = "dss_venc"; -+ }; -+ }; -+ }; -+ -+ clocks { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ /include/ "omap3xxx-clocks.dtsi" - }; - }; ---- a/arch/arm/boot/dts/omap3-evm.dts -+++ b/arch/arm/boot/dts/omap3-evm.dts -@@ -70,6 +70,8 @@ - &usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; -+ phys = <&usb2_phy>; -+ phy-names = "usb2-phy"; - mode = <3>; - power = <50>; - }; ---- a/arch/arm/boot/dts/omap3-overo.dtsi -+++ b/arch/arm/boot/dts/omap3-overo.dtsi -@@ -76,6 +76,8 @@ - &usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; -+ phys = <&usb2_phy>; -+ phy-names = "usb2-phy"; - mode = <3>; - power = <50>; - }; ---- a/arch/arm/boot/dts/omap3-tobi.dts -+++ b/arch/arm/boot/dts/omap3-tobi.dts -@@ -81,3 +81,36 @@ - &mmc3 { - status = "disabled"; - }; -+ -+&dpi { -+ vdds_dsi-supply = <&vpll2>; -+}; -+ -+/ { -+ aliases { -+ display0 = &lcd0; -+ }; -+ -+ lcd0: display@0 { -+ compatible = "samsung,lte430wq-f0c", "panel-dpi"; -+ video-source = <&dpi>; -+ data-lines = <24>; -+ -+ panel-timing { -+ clock-frequency = <9200000>; -+ hactive = <480>; -+ vactive = <272>; -+ hfront-porch = <8>; -+ hback-porch = <4>; -+ hsync-len = <41>; -+ vback-porch = <2>; -+ vfront-porch = <4>; -+ vsync-len = <10>; -+ -+ hsync-active = <0>; -+ vsync-active = <0>; -+ de-active = <1>; -+ pixelclk-active = <1>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi -@@ -0,0 +1,1513 @@ -+/* -+ * Device Tree Source for OMAP3 clock data -+ * -+ * Copyright (C) 2013 Texas Instruments, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+dummy_apb_pclk: dummy_apb_pclk { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <0x0>; -+}; -+ -+omap_32k_fck: omap_32k_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <32768>; -+}; -+ -+virt_12m_ck: virt_12m_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <12000000>; -+}; -+ -+virt_13m_ck: virt_13m_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <13000000>; -+}; -+ -+virt_19200000_ck: virt_19200000_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <19200000>; -+}; -+ -+virt_26000000_ck: virt_26000000_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <26000000>; -+}; -+ -+virt_38_4m_ck: virt_38_4m_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <38400000>; -+}; -+ -+virt_16_8m_ck: virt_16_8m_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <16800000>; -+}; -+ -+osc_sys_ck: osc_sys_ck@48306d40 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>; -+ reg = <0x48306d40 0x4>; -+ bit-mask = <0x7>; -+}; -+ -+sys_ck: sys_ck@48307270 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&osc_sys_ck>; -+ bit-shift = <6>; -+ reg = <0x48307270 0x4>; -+ bit-mask = <0x3>; -+ index-starts-at-one; -+}; -+ -+dpll4_ck: dpll4_ck@48004d00 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-dpll-per-clock"; -+ clocks = <&sys_ck>, <&sys_ck>; -+ ti,modes = <0x82>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+ reg = <0x48004d00 0x4>, <0x48004d20 0x4>, <0x48004d30 0x4>, <0x48004d44 0x4>; -+}; -+ -+dpll4_m2_ck: dpll4_m2_ck@48004d48 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll4_ck>; -+ reg = <0x48004d48 0x4>; -+ bit-mask = <0x3f>; -+ index-starts-at-one; -+}; -+ -+dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll4_m2_ck>; -+ clock-mult = <2>; -+ clock-div = <1>; -+}; -+ -+dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dpll4_m2x2_mul_ck>; -+ bit-shift = <0x1b>; -+ reg = <0x48004d00 0x4>; -+ set-bit-to-disable; -+}; -+ -+omap_96m_alwon_fck: omap_96m_alwon_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll4_m2x2_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+dpll3_ck: dpll3_ck@48004d00 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-dpll-core-clock"; -+ clocks = <&sys_ck>, <&sys_ck>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+ reg = <0x48004d00 0x4>, <0x48004d20 0x4>, <0x48004d30 0x4>, <0x48004d40 0x4>; -+}; -+ -+dpll3_m3_ck: dpll3_m3_ck@48005140 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll3_ck>; -+ bit-shift = <16>; -+ reg = <0x48005140 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+}; -+ -+dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll3_m3_ck>; -+ clock-mult = <2>; -+ clock-div = <1>; -+}; -+ -+dpll3_m3x2_ck: dpll3_m3x2_ck@48004d00 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dpll3_m3x2_mul_ck>; -+ bit-shift = <0xc>; -+ reg = <0x48004d00 0x4>; -+ set-bit-to-disable; -+}; -+ -+emu_core_alwon_ck: emu_core_alwon_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll3_m3x2_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+sys_altclk: sys_altclk { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <0x0>; -+}; -+ -+mcbsp_clks: mcbsp_clks { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <0x0>; -+}; -+ -+sys_clkout1: sys_clkout1@48306d70 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&osc_sys_ck>; -+ reg = <0x48306d70 0x4>; -+ bit-shift = <7>; -+}; -+ -+dpll3_m2_ck: dpll3_m2_ck@48004d40 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll3_ck>; -+ bit-shift = <27>; -+ reg = <0x48004d40 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+}; -+ -+core_ck: core_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll3_m2_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+dpll1_fck: dpll1_fck@48004940 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&core_ck>; -+ bit-shift = <19>; -+ reg = <0x48004940 0x4>; -+ bit-mask = <0x7>; -+ index-starts-at-one; -+}; -+ -+dpll1_ck: dpll1_ck@48004904 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-dpll-clock"; -+ clocks = <&sys_ck>, <&dpll1_fck>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+ reg = <0x48004904 0x4>, <0x48004924 0x4>, <0x48004934 0x4>, <0x48004940 0x4>; -+}; -+ -+dpll1_x2_ck: dpll1_x2_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll1_ck>; -+ clock-mult = <2>; -+ clock-div = <1>; -+}; -+ -+dpll1_x2m2_ck: dpll1_x2m2_ck@48004944 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll1_x2_ck>; -+ reg = <0x48004944 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+}; -+ -+dpll3_x2_ck: dpll3_x2_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll3_ck>; -+ clock-mult = <2>; -+ clock-div = <1>; -+}; -+ -+dpll3_m2x2_ck: dpll3_m2x2_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll3_m2_ck>; -+ clock-mult = <2>; -+ clock-div = <1>; -+}; -+ -+dpll4_x2_ck: dpll4_x2_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll4_ck>; -+ clock-mult = <2>; -+ clock-div = <1>; -+}; -+ -+cm_96m_fck: cm_96m_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&omap_96m_alwon_fck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+omap_96m_fck: omap_96m_fck@48004d40 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&cm_96m_fck>, <&sys_ck>; -+ bit-shift = <6>; -+ reg = <0x48004d40 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+dpll4_m3_ck: dpll4_m3_ck@48004e40 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll4_ck>; -+ bit-shift = <8>; -+ reg = <0x48004e40 0x4>; -+ bit-mask = <0x3f>; -+ index-starts-at-one; -+}; -+ -+dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll4_m3_ck>; -+ clock-mult = <2>; -+ clock-div = <1>; -+}; -+ -+dpll4_m3x2_ck: dpll4_m3x2_ck@48004d00 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dpll4_m3x2_mul_ck>; -+ bit-shift = <0x1c>; -+ reg = <0x48004d00 0x4>; -+ set-bit-to-disable; -+}; -+ -+omap_54m_fck: omap_54m_fck@48004d40 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&dpll4_m3x2_ck>, <&sys_altclk>; -+ bit-shift = <5>; -+ reg = <0x48004d40 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+cm_96m_d2_fck: cm_96m_d2_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&cm_96m_fck>; -+ clock-mult = <1>; -+ clock-div = <2>; -+}; -+ -+omap_48m_fck: omap_48m_fck@48004d40 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&cm_96m_d2_fck>, <&sys_altclk>; -+ bit-shift = <3>; -+ reg = <0x48004d40 0x4>; -+ table = <&cm_96m_d2_fck 0>, <&sys_altclk 1>; -+ bit-mask = <0x1>; -+}; -+ -+omap_12m_fck: omap_12m_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&omap_48m_fck>; -+ clock-mult = <1>; -+ clock-div = <4>; -+}; -+ -+dpll4_m4_ck: dpll4_m4_ck@48004e40 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll4_ck>; -+ reg = <0x48004e40 0x4>; -+ bit-mask = <0x3f>; -+ index-starts-at-one; -+}; -+ -+dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll4_m4_ck>; -+ clock-mult = <2>; -+ clock-div = <1>; -+}; -+ -+dpll4_m4x2_ck: dpll4_m4x2_ck@48004d00 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dpll4_m4x2_mul_ck>; -+ bit-shift = <0x1d>; -+ reg = <0x48004d00 0x4>; -+ set-bit-to-disable; -+}; -+ -+dpll4_m5_ck: dpll4_m5_ck@48004f40 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll4_ck>; -+ reg = <0x48004f40 0x4>; -+ bit-mask = <0x3f>; -+ index-starts-at-one; -+}; -+ -+dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll4_m5_ck>; -+ clock-mult = <2>; -+ clock-div = <1>; -+}; -+ -+dpll4_m5x2_ck: dpll4_m5x2_ck@48004d00 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dpll4_m5x2_mul_ck>; -+ bit-shift = <0x1e>; -+ reg = <0x48004d00 0x4>; -+ set-bit-to-disable; -+}; -+ -+dpll4_m6_ck: dpll4_m6_ck@48005140 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll4_ck>; -+ bit-shift = <24>; -+ reg = <0x48005140 0x4>; -+ bit-mask = <0x3f>; -+ index-starts-at-one; -+}; -+ -+dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll4_m6_ck>; -+ clock-mult = <2>; -+ clock-div = <1>; -+}; -+ -+dpll4_m6x2_ck: dpll4_m6x2_ck@48004d00 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dpll4_m6x2_mul_ck>; -+ bit-shift = <0x1f>; -+ reg = <0x48004d00 0x4>; -+ set-bit-to-disable; -+}; -+ -+emu_per_alwon_ck: emu_per_alwon_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll4_m6x2_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+clkout2_src_mux_ck: clkout2_src_mux_ck@48004d70 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>; -+ reg = <0x48004d70 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+clkout2_src_ck: clkout2_src_ck@48004d70 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&clkout2_src_mux_ck>; -+ bit-shift = <7>; -+ reg = <0x48004d70 0x4>; -+}; -+ -+sys_clkout2: sys_clkout2@48004d70 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&clkout2_src_ck>; -+ bit-shift = <3>; -+ reg = <0x48004d70 0x4>; -+ bit-mask = <0x7>; -+ index-power-of-two; -+}; -+ -+corex2_fck: corex2_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll3_m2x2_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+mpu_ck: mpu_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll1_x2m2_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+arm_fck: arm_fck@48004924 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&mpu_ck>; -+ reg = <0x48004924 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+emu_mpu_alwon_ck: emu_mpu_alwon_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&mpu_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+l3_ick: l3_ick@48004a40 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&core_ck>; -+ reg = <0x48004a40 0x4>; -+ bit-mask = <0x3>; -+ index-starts-at-one; -+}; -+ -+l4_ick: l4_ick@48004a40 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&l3_ick>; -+ bit-shift = <2>; -+ reg = <0x48004a40 0x4>; -+ bit-mask = <0x3>; -+ index-starts-at-one; -+}; -+ -+rm_ick: rm_ick@48004c40 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&l4_ick>; -+ bit-shift = <1>; -+ reg = <0x48004c40 0x4>; -+ bit-mask = <0x3>; -+ index-starts-at-one; -+}; -+ -+gpt10_mux_fck: gpt10_mux_fck@48004a40 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&omap_32k_fck>, <&sys_ck>; -+ bit-shift = <6>; -+ reg = <0x48004a40 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+gpt10_fck: gpt10_fck@48004a00 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&gpt10_mux_fck>; -+ bit-shift = <11>; -+ reg = <0x48004a00 0x4>; -+}; -+ -+gpt11_mux_fck: gpt11_mux_fck@48004a40 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&omap_32k_fck>, <&sys_ck>; -+ bit-shift = <7>; -+ reg = <0x48004a40 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+gpt11_fck: gpt11_fck@48004a00 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&gpt11_mux_fck>; -+ bit-shift = <12>; -+ reg = <0x48004a00 0x4>; -+}; -+ -+core_96m_fck: core_96m_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&omap_96m_fck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+mmchs2_fck: mmchs2_fck@48004a00 { -+ #clock-cells = <0>; -+ compatible = "ti,gate-clock"; -+ clocks = <&core_96m_fck>; -+ reg = <0x48004a00 0x4>; -+ ti,enable-bit = <25>; -+}; -+ -+mmchs1_fck: mmchs1_fck@48004a00 { -+ #clock-cells = <0>; -+ compatible = "ti,gate-clock"; -+ clocks = <&core_96m_fck>; -+ reg = <0x48004a00 0x4>; -+ ti,enable-bit = <24>; -+}; -+ -+i2c3_fck: i2c3_fck@48004a00 { -+ #clock-cells = <0>; -+ compatible = "ti,gate-clock"; -+ clocks = <&core_96m_fck>; -+ reg = <0x48004a00 0x4>; -+ ti,enable-bit = <17>; -+}; -+ -+i2c2_fck: i2c2_fck@48004a00 { -+ #clock-cells = <0>; -+ compatible = "ti,gate-clock"; -+ clocks = <&core_96m_fck>; -+ reg = <0x48004a00 0x4>; -+ ti,enable-bit = <16>; -+}; -+ -+i2c1_fck: i2c1_fck@48004a00 { -+ #clock-cells = <0>; -+ compatible = "ti,gate-clock"; -+ clocks = <&core_96m_fck>; -+ reg = <0x48004a00 0x4>; -+ ti,enable-bit = <15>; -+}; -+ -+mcbsp5_mux_fck: mcbsp5_mux_fck@480022d8 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&core_96m_fck>, <&mcbsp_clks>; -+ bit-shift = <4>; -+ reg = <0x480022d8 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+mcbsp5_fck: mcbsp5_fck@48004a00 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&mcbsp5_mux_fck>; -+ bit-shift = <10>; -+ reg = <0x48004a00 0x4>; -+}; -+ -+mcbsp1_mux_fck: mcbsp1_mux_fck@48002274 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&core_96m_fck>, <&mcbsp_clks>; -+ bit-shift = <2>; -+ reg = <0x48002274 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+mcbsp1_fck: mcbsp1_fck@48004a00 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&mcbsp1_mux_fck>; -+ bit-shift = <9>; -+ reg = <0x48004a00 0x4>; -+}; -+ -+core_48m_fck: core_48m_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&omap_48m_fck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+mcspi4_fck: mcspi4_fck@48004a00 { -+ #clock-cells = <0>; -+ compatible = "ti,gate-clock"; -+ clocks = <&core_48m_fck>; -+ reg = <0x48004a00 0x4>; -+ ti,enable-bit = <21>; -+}; -+ -+mcspi3_fck: mcspi3_fck@48004a00 { -+ #clock-cells = <0>; -+ compatible = "ti,gate-clock"; -+ clocks = <&core_48m_fck>; -+ reg = <0x48004a00 0x4>; -+ ti,enable-bit = <20>; -+}; -+ -+mcspi2_fck: mcspi2_fck@48004a00 { -+ #clock-cells = <0>; -+ compatible = "ti,gate-clock"; -+ clocks = <&core_48m_fck>; -+ reg = <0x48004a00 0x4>; -+ ti,enable-bit = <19>; -+}; -+ -+mcspi1_fck: mcspi1_fck@48004a00 { -+ #clock-cells = <0>; -+ compatible = "ti,gate-clock"; -+ clocks = <&core_48m_fck>; -+ reg = <0x48004a00 0x4>; -+ ti,enable-bit = <18>; -+}; -+ -+uart2_fck: uart2_fck@48004a00 { -+ #clock-cells = <0>; -+ compatible = "ti,gate-clock"; -+ clocks = <&core_48m_fck>; -+ reg = <0x48004a00 0x4>; -+ ti,enable-bit = <14>; -+}; -+ -+uart1_fck: uart1_fck@48004a00 { -+ #clock-cells = <0>; -+ compatible = "ti,gate-clock"; -+ clocks = <&core_48m_fck>; -+ reg = <0x48004a00 0x4>; -+ ti,enable-bit = <13>; -+}; -+ -+core_12m_fck: core_12m_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&omap_12m_fck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+hdq_fck: hdq_fck@48004a00 { -+ #clock-cells = <0>; -+ compatible = "ti,gate-clock"; -+ clocks = <&core_12m_fck>; -+ reg = <0x48004a00 0x4>; -+ ti,enable-bit = <22>; -+}; -+ -+core_l3_ick: core_l3_ick { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&l3_ick>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+sdrc_ick: sdrc_ick@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,gate-clock"; -+ clocks = <&core_l3_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <1>; -+}; -+ -+gpmc_fck: gpmc_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&core_l3_ick>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+core_l4_ick: core_l4_ick { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&l4_ick>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+mmchs2_ick: mmchs2_ick@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&core_l4_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <25>; -+}; -+ -+mmchs1_ick: mmchs1_ick@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&core_l4_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <24>; -+}; -+ -+hdq_ick: hdq_ick@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&core_l4_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <22>; -+}; -+ -+mcspi4_ick: mcspi4_ick@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&core_l4_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <21>; -+}; -+ -+mcspi3_ick: mcspi3_ick@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&core_l4_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <20>; -+}; -+ -+mcspi2_ick: mcspi2_ick@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&core_l4_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <19>; -+}; -+ -+mcspi1_ick: mcspi1_ick@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&core_l4_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <18>; -+}; -+ -+i2c3_ick: i2c3_ick@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&core_l4_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <17>; -+}; -+ -+i2c2_ick: i2c2_ick@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&core_l4_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <16>; -+}; -+ -+i2c1_ick: i2c1_ick@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&core_l4_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <15>; -+}; -+ -+uart2_ick: uart2_ick@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&core_l4_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <14>; -+}; -+ -+uart1_ick: uart1_ick@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&core_l4_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <13>; -+}; -+ -+gpt11_ick: gpt11_ick@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&core_l4_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <12>; -+}; -+ -+gpt10_ick: gpt10_ick@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&core_l4_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <11>; -+}; -+ -+mcbsp5_ick: mcbsp5_ick@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&core_l4_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <10>; -+}; -+ -+mcbsp1_ick: mcbsp1_ick@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&core_l4_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <9>; -+}; -+ -+omapctrl_ick: omapctrl_ick@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&core_l4_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <6>; -+}; -+ -+dss_tv_fck: dss_tv_fck@48004e00 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&omap_54m_fck>; -+ reg = <0x48004e00 0x4>; -+ bit-shift = <2>; -+}; -+ -+dss_96m_fck: dss_96m_fck@48004e00 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&omap_96m_fck>; -+ reg = <0x48004e00 0x4>; -+ bit-shift = <2>; -+}; -+ -+dss2_alwon_fck: dss2_alwon_fck@48004e00 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_ck>; -+ reg = <0x48004e00 0x4>; -+ bit-shift = <1>; -+}; -+ -+gpt1_mux_fck: gpt1_mux_fck@48004c40 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&omap_32k_fck>, <&sys_ck>; -+ reg = <0x48004c40 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+gpt1_fck: gpt1_fck@48004c00 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&gpt1_mux_fck>; -+ bit-shift = <0>; -+ reg = <0x48004c00 0x4>; -+}; -+ -+aes2_ick: aes2_ick@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&core_l4_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <28>; -+}; -+ -+wkup_32k_fck: wkup_32k_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&omap_32k_fck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+gpio1_dbck: gpio1_dbck@48004c00 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&wkup_32k_fck>; -+ reg = <0x48004c00 0x4>; -+ bit-shift = <3>; -+}; -+ -+sha12_ick: sha12_ick@48004a10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&core_l4_ick>; -+ reg = <0x48004a10 0x4>; -+ ti,enable-bit = <27>; -+}; -+ -+wdt2_fck: wdt2_fck@48004c00 { -+ #clock-cells = <0>; -+ compatible = "ti,gate-clock"; -+ clocks = <&wkup_32k_fck>; -+ reg = <0x48004c00 0x4>; -+ ti,enable-bit = <5>; -+}; -+ -+wkup_l4_ick: wkup_l4_ick { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&sys_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+wdt2_ick: wdt2_ick@48004c10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&wkup_l4_ick>; -+ reg = <0x48004c10 0x4>; -+ ti,enable-bit = <5>; -+}; -+ -+wdt1_ick: wdt1_ick@48004c10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&wkup_l4_ick>; -+ reg = <0x48004c10 0x4>; -+ ti,enable-bit = <4>; -+}; -+ -+gpio1_ick: gpio1_ick@48004c10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&wkup_l4_ick>; -+ reg = <0x48004c10 0x4>; -+ ti,enable-bit = <3>; -+}; -+ -+omap_32ksync_ick: omap_32ksync_ick@48004c10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&wkup_l4_ick>; -+ reg = <0x48004c10 0x4>; -+ ti,enable-bit = <2>; -+}; -+ -+gpt12_ick: gpt12_ick@48004c10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&wkup_l4_ick>; -+ reg = <0x48004c10 0x4>; -+ ti,enable-bit = <1>; -+}; -+ -+gpt1_ick: gpt1_ick@48004c10 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&wkup_l4_ick>; -+ reg = <0x48004c10 0x4>; -+ ti,enable-bit = <0>; -+}; -+ -+per_96m_fck: per_96m_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&omap_96m_alwon_fck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+per_48m_fck: per_48m_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&omap_48m_fck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+uart3_fck: uart3_fck@48005000 { -+ #clock-cells = <0>; -+ compatible = "ti,gate-clock"; -+ clocks = <&per_48m_fck>; -+ reg = <0x48005000 0x4>; -+ ti,enable-bit = <11>; -+}; -+ -+gpt2_mux_fck: gpt2_mux_fck@48005040 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&omap_32k_fck>, <&sys_ck>; -+ reg = <0x48005040 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+gpt2_fck: gpt2_fck@48005000 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&gpt2_mux_fck>; -+ bit-shift = <3>; -+ reg = <0x48005000 0x4>; -+}; -+ -+gpt3_mux_fck: gpt3_mux_fck@48005040 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&omap_32k_fck>, <&sys_ck>; -+ bit-shift = <1>; -+ reg = <0x48005040 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+gpt3_fck: gpt3_fck@48005000 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&gpt3_mux_fck>; -+ bit-shift = <4>; -+ reg = <0x48005000 0x4>; -+}; -+ -+gpt4_mux_fck: gpt4_mux_fck@48005040 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&omap_32k_fck>, <&sys_ck>; -+ bit-shift = <2>; -+ reg = <0x48005040 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+gpt4_fck: gpt4_fck@48005000 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&gpt4_mux_fck>; -+ bit-shift = <5>; -+ reg = <0x48005000 0x4>; -+}; -+ -+gpt5_mux_fck: gpt5_mux_fck@48005040 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&omap_32k_fck>, <&sys_ck>; -+ bit-shift = <3>; -+ reg = <0x48005040 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+gpt5_fck: gpt5_fck@48005000 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&gpt5_mux_fck>; -+ bit-shift = <6>; -+ reg = <0x48005000 0x4>; -+}; -+ -+gpt6_mux_fck: gpt6_mux_fck@48005040 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&omap_32k_fck>, <&sys_ck>; -+ bit-shift = <4>; -+ reg = <0x48005040 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+gpt6_fck: gpt6_fck@48005000 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&gpt6_mux_fck>; -+ bit-shift = <7>; -+ reg = <0x48005000 0x4>; -+}; -+ -+gpt7_mux_fck: gpt7_mux_fck@48005040 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&omap_32k_fck>, <&sys_ck>; -+ bit-shift = <5>; -+ reg = <0x48005040 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+gpt7_fck: gpt7_fck@48005000 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&gpt7_mux_fck>; -+ bit-shift = <8>; -+ reg = <0x48005000 0x4>; -+}; -+ -+gpt8_mux_fck: gpt8_mux_fck@48005040 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&omap_32k_fck>, <&sys_ck>; -+ bit-shift = <6>; -+ reg = <0x48005040 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+gpt8_fck: gpt8_fck@48005000 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&gpt8_mux_fck>; -+ bit-shift = <9>; -+ reg = <0x48005000 0x4>; -+}; -+ -+gpt9_mux_fck: gpt9_mux_fck@48005040 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&omap_32k_fck>, <&sys_ck>; -+ bit-shift = <7>; -+ reg = <0x48005040 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+gpt9_fck: gpt9_fck@48005000 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&gpt9_mux_fck>; -+ bit-shift = <10>; -+ reg = <0x48005000 0x4>; -+}; -+ -+per_32k_alwon_fck: per_32k_alwon_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&omap_32k_fck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+gpio6_dbck: gpio6_dbck@48005000 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&per_32k_alwon_fck>; -+ reg = <0x48005000 0x4>; -+ bit-shift = <17>; -+}; -+ -+gpio5_dbck: gpio5_dbck@48005000 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&per_32k_alwon_fck>; -+ reg = <0x48005000 0x4>; -+ bit-shift = <16>; -+}; -+ -+gpio4_dbck: gpio4_dbck@48005000 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&per_32k_alwon_fck>; -+ reg = <0x48005000 0x4>; -+ bit-shift = <15>; -+}; -+ -+gpio3_dbck: gpio3_dbck@48005000 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&per_32k_alwon_fck>; -+ reg = <0x48005000 0x4>; -+ bit-shift = <14>; -+}; -+ -+gpio2_dbck: gpio2_dbck@48005000 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&per_32k_alwon_fck>; -+ reg = <0x48005000 0x4>; -+ bit-shift = <13>; -+}; -+ -+wdt3_fck: wdt3_fck@48005000 { -+ #clock-cells = <0>; -+ compatible = "ti,gate-clock"; -+ clocks = <&per_32k_alwon_fck>; -+ reg = <0x48005000 0x4>; -+ ti,enable-bit = <12>; -+}; -+ -+per_l4_ick: per_l4_ick { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&l4_ick>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+gpio6_ick: gpio6_ick@48005010 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&per_l4_ick>; -+ reg = <0x48005010 0x4>; -+ ti,enable-bit = <17>; -+}; -+ -+gpio5_ick: gpio5_ick@48005010 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&per_l4_ick>; -+ reg = <0x48005010 0x4>; -+ ti,enable-bit = <16>; -+}; -+ -+gpio4_ick: gpio4_ick@48005010 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&per_l4_ick>; -+ reg = <0x48005010 0x4>; -+ ti,enable-bit = <15>; -+}; -+ -+gpio3_ick: gpio3_ick@48005010 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&per_l4_ick>; -+ reg = <0x48005010 0x4>; -+ ti,enable-bit = <14>; -+}; -+ -+gpio2_ick: gpio2_ick@48005010 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&per_l4_ick>; -+ reg = <0x48005010 0x4>; -+ ti,enable-bit = <13>; -+}; -+ -+wdt3_ick: wdt3_ick@48005010 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&per_l4_ick>; -+ reg = <0x48005010 0x4>; -+ ti,enable-bit = <12>; -+}; -+ -+uart3_ick: uart3_ick@48005010 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&per_l4_ick>; -+ reg = <0x48005010 0x4>; -+ ti,enable-bit = <11>; -+}; -+ -+uart4_ick: uart4_ick@48005010 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&per_l4_ick>; -+ reg = <0x48005010 0x4>; -+ ti,enable-bit = <18>; -+}; -+ -+gpt9_ick: gpt9_ick@48005010 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&per_l4_ick>; -+ reg = <0x48005010 0x4>; -+ ti,enable-bit = <10>; -+}; -+ -+gpt8_ick: gpt8_ick@48005010 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&per_l4_ick>; -+ reg = <0x48005010 0x4>; -+ ti,enable-bit = <9>; -+}; -+ -+gpt7_ick: gpt7_ick@48005010 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&per_l4_ick>; -+ reg = <0x48005010 0x4>; -+ ti,enable-bit = <8>; -+}; -+ -+gpt6_ick: gpt6_ick@48005010 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&per_l4_ick>; -+ reg = <0x48005010 0x4>; -+ ti,enable-bit = <7>; -+}; -+ -+gpt5_ick: gpt5_ick@48005010 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&per_l4_ick>; -+ reg = <0x48005010 0x4>; -+ ti,enable-bit = <6>; -+}; -+ -+gpt4_ick: gpt4_ick@48005010 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&per_l4_ick>; -+ reg = <0x48005010 0x4>; -+ ti,enable-bit = <5>; -+}; -+ -+gpt3_ick: gpt3_ick@48005010 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&per_l4_ick>; -+ reg = <0x48005010 0x4>; -+ ti,enable-bit = <4>; -+}; -+ -+gpt2_ick: gpt2_ick@48005010 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&per_l4_ick>; -+ reg = <0x48005010 0x4>; -+ ti,enable-bit = <3>; -+}; -+ -+mcbsp2_ick: mcbsp2_ick@48005010 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&per_l4_ick>; -+ reg = <0x48005010 0x4>; -+ ti,enable-bit = <0>; -+}; -+ -+mcbsp3_ick: mcbsp3_ick@48005010 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&per_l4_ick>; -+ reg = <0x48005010 0x4>; -+ ti,enable-bit = <1>; -+}; -+ -+mcbsp4_ick: mcbsp4_ick@48005010 { -+ #clock-cells = <0>; -+ compatible = "ti,omap3-interface-clock"; -+ clocks = <&per_l4_ick>; -+ reg = <0x48005010 0x4>; -+ ti,enable-bit = <2>; -+}; -+ -+mcbsp2_mux_fck: mcbsp2_mux_fck@48002274 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&per_96m_fck>, <&mcbsp_clks>; -+ bit-shift = <6>; -+ reg = <0x48002274 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+mcbsp2_fck: mcbsp2_fck@48005000 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&mcbsp2_mux_fck>; -+ bit-shift = <0>; -+ reg = <0x48005000 0x4>; -+}; -+ -+mcbsp3_mux_fck: mcbsp3_mux_fck@480022d8 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&per_96m_fck>, <&mcbsp_clks>; -+ reg = <0x480022d8 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+mcbsp3_fck: mcbsp3_fck@48005000 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&mcbsp3_mux_fck>; -+ bit-shift = <1>; -+ reg = <0x48005000 0x4>; -+}; -+ -+mcbsp4_mux_fck: mcbsp4_mux_fck@480022d8 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&per_96m_fck>, <&mcbsp_clks>; -+ bit-shift = <2>; -+ reg = <0x480022d8 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+mcbsp4_fck: mcbsp4_fck@48005000 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&mcbsp4_mux_fck>; -+ bit-shift = <2>; -+ reg = <0x48005000 0x4>; -+}; -+ -+emu_src_mux_ck: emu_src_mux_ck@48005140 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; -+ reg = <0x48005140 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+emu_src_ck: emu_src_ck { -+ #clock-cells = <0>; -+ compatible = "ti,clkdm-gate-clock"; -+ clocks = <&emu_src_mux_ck>; -+}; -+ -+pclk_fck: pclk_fck@48005140 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&emu_src_ck>; -+ bit-shift = <8>; -+ reg = <0x48005140 0x4>; -+ bit-mask = <0x7>; -+ index-starts-at-one; -+}; -+ -+pclkx2_fck: pclkx2_fck@48005140 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&emu_src_ck>; -+ bit-shift = <6>; -+ reg = <0x48005140 0x4>; -+ bit-mask = <0x3>; -+ index-starts-at-one; -+}; -+ -+atclk_fck: atclk_fck@48005140 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&emu_src_ck>; -+ bit-shift = <4>; -+ reg = <0x48005140 0x4>; -+ bit-mask = <0x3>; -+ index-starts-at-one; -+}; -+ -+traceclk_src_fck: traceclk_src_fck@48005140 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; -+ bit-shift = <2>; -+ reg = <0x48005140 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+traceclk_fck: traceclk_fck@48005140 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&traceclk_src_fck>; -+ bit-shift = <11>; -+ reg = <0x48005140 0x4>; -+ bit-mask = <0x7>; -+ index-starts-at-one; -+}; -+ -+secure_32k_fck: secure_32k_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <32768>; -+}; -+ -+gpt12_fck: gpt12_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&secure_32k_fck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+wdt1_fck: wdt1_fck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&secure_32k_fck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/omap443x-clocks.dtsi -@@ -0,0 +1,17 @@ -+/* -+ * Device Tree Source for OMAP443x clock data -+ * -+ * Copyright (C) 2013 Texas Instruments, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+bandgap_fclk: bandgap_fclk@4a307888 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4a307888 0x4>; -+}; ---- a/arch/arm/boot/dts/omap443x.dtsi -+++ b/arch/arm/boot/dts/omap443x.dtsi -@@ -30,4 +30,24 @@ - 0x4a00232C 0x4>; - compatible = "ti,omap4430-bandgap"; - }; -+ -+ clocks { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ /include/ "omap44xx-clocks.dtsi" -+ /include/ "omap443x-clocks.dtsi" -+ }; -+ -+ clockdomains { -+ l3_init_clkdm: l3_init_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&dpll_usb_ck>; -+ }; -+ -+ emu_sys_clkdm: emu_sys_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&trace_clk_div_ck>; -+ }; -+ }; - }; ---- a/arch/arm/boot/dts/omap4460.dtsi -+++ b/arch/arm/boot/dts/omap4460.dtsi -@@ -38,4 +38,24 @@ - interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */ - gpios = <&gpio3 22 0>; /* tshut */ - }; -+ -+ clocks { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ /include/ "omap44xx-clocks.dtsi" -+ /include/ "omap446x-clocks.dtsi" -+ }; -+ -+ clockdomains { -+ l3_init_clkdm: l3_init_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&dpll_usb_ck>; -+ }; -+ -+ emu_sys_clkdm: emu_sys_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&trace_clk_div_ck>; -+ }; -+ }; - }; ---- /dev/null -+++ b/arch/arm/boot/dts/omap446x-clocks.dtsi -@@ -0,0 +1,27 @@ -+/* -+ * Device Tree Source for OMAP446x clock data -+ * -+ * Copyright (C) 2013 Texas Instruments, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+div_ts_ck: div_ts_ck@4a307888 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&l4_wkup_clk_mux_ck>; -+ bit-shift = <24>; -+ reg = <0x4a307888 0x4>; -+ table = < 8 0 >, < 16 1 >, < 32 2 >; -+ bit-mask = <0x3>; -+}; -+ -+bandgap_ts_fclk: bandgap_ts_fclk@4a307888 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&div_ts_ck>; -+ bit-shift = <8>; -+ reg = <0x4a307888 0x4>; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi -@@ -0,0 +1,1639 @@ -+/* -+ * Device Tree Source for OMAP4 clock data -+ * -+ * Copyright (C) 2013 Texas Instruments, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+extalt_clkin_ck: extalt_clkin_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <59000000>; -+}; -+ -+pad_clks_src_ck: pad_clks_src_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <12000000>; -+}; -+ -+pad_clks_ck: pad_clks_ck@4a004108 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&pad_clks_src_ck>; -+ bit-shift = <8>; -+ reg = <0x4a004108 0x4>; -+}; -+ -+pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <12000000>; -+}; -+ -+secure_32k_clk_src_ck: secure_32k_clk_src_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <32768>; -+}; -+ -+slimbus_src_clk: slimbus_src_clk { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <12000000>; -+}; -+ -+slimbus_clk: slimbus_clk@4a004108 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&slimbus_src_clk>; -+ bit-shift = <10>; -+ reg = <0x4a004108 0x4>; -+}; -+ -+sys_32k_ck: sys_32k_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <32768>; -+}; -+ -+virt_12000000_ck: virt_12000000_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <12000000>; -+}; -+ -+virt_13000000_ck: virt_13000000_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <13000000>; -+}; -+ -+virt_16800000_ck: virt_16800000_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <16800000>; -+}; -+ -+virt_19200000_ck: virt_19200000_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <19200000>; -+}; -+ -+virt_26000000_ck: virt_26000000_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <26000000>; -+}; -+ -+virt_27000000_ck: virt_27000000_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <27000000>; -+}; -+ -+virt_38400000_ck: virt_38400000_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <38400000>; -+}; -+ -+sys_clkin_ck: sys_clkin_ck@4a306110 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; -+ reg = <0x4a306110 0x4>; -+ bit-mask = <0x7>; -+ index-starts-at-one; -+}; -+ -+tie_low_clock_ck: tie_low_clock_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <0>; -+}; -+ -+utmi_phy_clkout_ck: utmi_phy_clkout_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <60000000>; -+}; -+ -+xclk60mhsp1_ck: xclk60mhsp1_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <60000000>; -+}; -+ -+xclk60mhsp2_ck: xclk60mhsp2_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <60000000>; -+}; -+ -+xclk60motg_ck: xclk60motg_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <60000000>; -+}; -+ -+abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@4a306108 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>; -+ bit-shift = <24>; -+ reg = <0x4a306108 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@4a30610c { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>; -+ reg = <0x4a30610c 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+dpll_abe_ck: dpll_abe_ck@4a0041e0 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-m4xen-clock"; -+ clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>; -+ reg = <0x4a0041e0 0x4>, <0x4a0041e4 0x4>, <0x4a0041e8 0x4>, <0x4a0041ec 0x4>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+}; -+ -+dpll_abe_x2_ck: dpll_abe_x2_ck@4a0041f0 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-x2-clock"; -+ clocks = <&dpll_abe_ck>; -+ reg = <0x4a0041f0 0x4>; -+}; -+ -+dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@4a0041f0 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_abe_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a0041f0 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+abe_24m_fclk: abe_24m_fclk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_abe_m2x2_ck>; -+ clock-mult = <1>; -+ clock-div = <8>; -+}; -+ -+abe_clk: abe_clk@4a004108 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_abe_m2x2_ck>; -+ reg = <0x4a004108 0x4>; -+ bit-mask = <0x3>; -+ index-power-of-two; -+}; -+ -+aess_fclk: aess_fclk@4a004528 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&abe_clk>; -+ bit-shift = <24>; -+ reg = <0x4a004528 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@4a0041f4 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_abe_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a0041f4 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@4a00412c { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>; -+ bit-shift = <23>; -+ reg = <0x4a00412c 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+dpll_core_ck: dpll_core_ck@4a004120 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-core-clock"; -+ clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>; -+ reg = <0x4a004120 0x4>, <0x4a004124 0x4>, <0x4a004128 0x4>, <0x4a00412c 0x4>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+}; -+ -+dpll_core_x2_ck: dpll_core_x2_ck { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-x2-clock"; -+ clocks = <&dpll_core_ck>; -+}; -+ -+dpll_core_m6x2_ck: dpll_core_m6x2_ck@4a004140 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_core_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a004140 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dbgclk_mux_ck: dbgclk_mux_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&sys_clkin_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+dpll_core_m2_ck: dpll_core_m2_ck@4a004130 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_core_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a004130 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+ddrphy_ck: ddrphy_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_core_m2_ck>; -+ clock-mult = <1>; -+ clock-div = <2>; -+}; -+ -+dpll_core_m5x2_ck: dpll_core_m5x2_ck@4a00413c { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_core_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a00413c 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+div_core_ck: div_core_ck@4a004100 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_core_m5x2_ck>; -+ reg = <0x4a004100 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+div_iva_hs_clk: div_iva_hs_clk@4a0041dc { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_core_m5x2_ck>; -+ reg = <0x4a0041dc 0x4>; -+ bit-mask = <0x3>; -+ index-power-of-two; -+}; -+ -+div_mpu_hs_clk: div_mpu_hs_clk@4a00419c { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_core_m5x2_ck>; -+ reg = <0x4a00419c 0x4>; -+ bit-mask = <0x3>; -+ index-power-of-two; -+}; -+ -+dpll_core_m4x2_ck: dpll_core_m4x2_ck@4a004138 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_core_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a004138 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dll_clk_div_ck: dll_clk_div_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_core_m4x2_ck>; -+ clock-mult = <1>; -+ clock-div = <2>; -+}; -+ -+dpll_abe_m2_ck: dpll_abe_m2_ck@4a0041f0 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_abe_ck>; -+ reg = <0x4a0041f0 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+}; -+ -+dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck@4a004134 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_core_x2_ck>; -+ reg = <0x4a004134 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+}; -+ -+dpll_core_m3x2_ck: dpll_core_m3x2_ck@4a004134 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dpll_core_m3x2_div_ck>; -+ bit-shift = <8>; -+ reg = <0x4a004134 0x4>; -+}; -+ -+dpll_core_m7x2_ck: dpll_core_m7x2_ck@4a004144 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_core_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a004144 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@4a0041ac { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>; -+ bit-shift = <23>; -+ reg = <0x4a0041ac 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+dpll_iva_ck: dpll_iva_ck@4a0041a0 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-clock"; -+ clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>; -+ reg = <0x4a0041a0 0x4>, <0x4a0041a4 0x4>, <0x4a0041a8 0x4>, <0x4a0041ac 0x4>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+}; -+ -+dpll_iva_x2_ck: dpll_iva_x2_ck { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-x2-clock"; -+ clocks = <&dpll_iva_ck>; -+}; -+ -+dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@4a0041b8 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_iva_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a0041b8 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@4a0041bc { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_iva_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a0041bc 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_mpu_ck: dpll_mpu_ck@4a004160 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-clock"; -+ clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>; -+ reg = <0x4a004160 0x4>, <0x4a004164 0x4>, <0x4a004168 0x4>, <0x4a00416c 0x4>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+}; -+ -+dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a004170 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_mpu_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a004170 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+per_hs_clk_div_ck: per_hs_clk_div_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_abe_m3x2_ck>; -+ clock-mult = <1>; -+ clock-div = <2>; -+}; -+ -+per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@4a00814c { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>; -+ bit-shift = <23>; -+ reg = <0x4a00814c 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+dpll_per_ck: dpll_per_ck@4a008140 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-clock"; -+ clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>; -+ reg = <0x4a008140 0x4>, <0x4a008144 0x4>, <0x4a008148 0x4>, <0x4a00814c 0x4>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+}; -+ -+dpll_per_m2_ck: dpll_per_m2_ck@4a008150 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_per_ck>; -+ reg = <0x4a008150 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+}; -+ -+dpll_per_x2_ck: dpll_per_x2_ck@4a008150 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-x2-clock"; -+ clocks = <&dpll_per_ck>; -+ reg = <0x4a008150 0x4>; -+}; -+ -+dpll_per_m2x2_ck: dpll_per_m2x2_ck@4a008150 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_per_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a008150 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck@4a008154 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_per_x2_ck>; -+ reg = <0x4a008154 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+}; -+ -+dpll_per_m3x2_ck: dpll_per_m3x2_ck@4a008154 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dpll_per_m3x2_div_ck>; -+ bit-shift = <8>; -+ reg = <0x4a008154 0x4>; -+}; -+ -+dpll_per_m4x2_ck: dpll_per_m4x2_ck@4a008158 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_per_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a008158 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_per_m5x2_ck: dpll_per_m5x2_ck@4a00815c { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_per_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a00815c 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_per_m6x2_ck: dpll_per_m6x2_ck@4a008160 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_per_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a008160 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_per_m7x2_ck: dpll_per_m7x2_ck@4a008164 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_per_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a008164 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+usb_hs_clk_div_ck: usb_hs_clk_div_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_abe_m3x2_ck>; -+ clock-mult = <1>; -+ clock-div = <3>; -+}; -+ -+dpll_usb_ck: dpll_usb_ck@4a008180 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-j-type-clock"; -+ clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>; -+ reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>, <0x4a00818c 0x4>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+}; -+ -+dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@4a0081b4 { -+ #clock-cells = <0>; -+ compatible = "ti,fixed-factor-clock"; -+ clocks = <&dpll_usb_ck>; -+ ti,autoidle-shift = <8>; -+ clock-div = <1>; -+ reg = <0x4a0081b4 0x4>; -+ clock-mult = <1>; -+ ti,autoidle-low; -+}; -+ -+dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_usb_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a008190 0x4>; -+ bit-mask = <0x7f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+ducati_clk_mux_ck: ducati_clk_mux_ck@4a008100 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>; -+ reg = <0x4a008100 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+func_12m_fclk: func_12m_fclk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_per_m2x2_ck>; -+ clock-mult = <1>; -+ clock-div = <16>; -+}; -+ -+func_24m_clk: func_24m_clk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_per_m2_ck>; -+ clock-mult = <1>; -+ clock-div = <4>; -+}; -+ -+func_24mc_fclk: func_24mc_fclk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_per_m2x2_ck>; -+ clock-mult = <1>; -+ clock-div = <8>; -+}; -+ -+func_48m_fclk: func_48m_fclk@4a008108 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_per_m2x2_ck>; -+ reg = <0x4a008108 0x4>; -+ table = < 4 0 >, < 8 1 >; -+ bit-mask = <0x1>; -+}; -+ -+func_48mc_fclk: func_48mc_fclk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_per_m2x2_ck>; -+ clock-mult = <1>; -+ clock-div = <4>; -+}; -+ -+func_64m_fclk: func_64m_fclk@4a008108 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_per_m4x2_ck>; -+ reg = <0x4a008108 0x4>; -+ table = < 2 0 >, < 4 1 >; -+ bit-mask = <0x1>; -+}; -+ -+func_96m_fclk: func_96m_fclk@4a008108 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_per_m2x2_ck>; -+ reg = <0x4a008108 0x4>; -+ table = < 2 0 >, < 4 1 >; -+ bit-mask = <0x1>; -+}; -+ -+init_60m_fclk: init_60m_fclk@4a008104 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_usb_m2_ck>; -+ reg = <0x4a008104 0x4>; -+ table = < 1 0 >, < 8 1 >; -+ bit-mask = <0x1>; -+}; -+ -+l3_div_ck: l3_div_ck@4a004100 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&div_core_ck>; -+ bit-shift = <4>; -+ reg = <0x4a004100 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+l4_div_ck: l4_div_ck@4a004100 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&l3_div_ck>; -+ bit-shift = <8>; -+ reg = <0x4a004100 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+lp_clk_div_ck: lp_clk_div_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_abe_m2x2_ck>; -+ clock-mult = <1>; -+ clock-div = <16>; -+}; -+ -+l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@4a306108 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>; -+ reg = <0x4a306108 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+mpu_periphclk: mpu_periphclk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_mpu_ck>; -+ clock-mult = <1>; -+ clock-div = <2>; -+}; -+ -+ocp_abe_iclk: ocp_abe_iclk@4a004528 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&aess_fclk>; -+ bit-shift = <24>; -+ reg = <0x4a004528 0x4>; -+ table = < 2 0 >, < 1 1 >; -+ bit-mask = <0x1>; -+}; -+ -+per_abe_24m_fclk: per_abe_24m_fclk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_abe_m2_ck>; -+ clock-mult = <1>; -+ clock-div = <4>; -+}; -+ -+per_abe_nc_fclk: per_abe_nc_fclk@4a008108 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_abe_m2_ck>; -+ reg = <0x4a008108 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+syc_clk_div_ck: syc_clk_div_ck@4a306100 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&sys_clkin_ck>; -+ reg = <0x4a306100 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+aes1_fck: aes1_fck@4a0095a0 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&l3_div_ck>; -+ bit-shift = <1>; -+ reg = <0x4a0095a0 0x4>; -+}; -+ -+aes2_fck: aes2_fck@4a0095a8 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&l3_div_ck>; -+ bit-shift = <1>; -+ reg = <0x4a0095a8 0x4>; -+}; -+ -+dmic_sync_mux_ck: dmic_sync_mux_ck@4a004538 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; -+ bit-shift = <25>; -+ reg = <0x4a004538 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+func_dmic_abe_gfclk: func_dmic_abe_gfclk@4a004538 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; -+ bit-shift = <24>; -+ reg = <0x4a004538 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+dss_sys_clk: dss_sys_clk@4a009120 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&syc_clk_div_ck>; -+ bit-shift = <10>; -+ reg = <0x4a009120 0x4>; -+}; -+ -+dss_tv_clk: dss_tv_clk@4a009120 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&extalt_clkin_ck>; -+ bit-shift = <11>; -+ reg = <0x4a009120 0x4>; -+}; -+ -+dss_dss_clk: dss_dss_clk@4a009120 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dpll_per_m5x2_ck>; -+ bit-shift = <8>; -+ reg = <0x4a009120 0x4>; -+}; -+ -+dss_48mhz_clk: dss_48mhz_clk@4a009120 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&func_48mc_fclk>; -+ bit-shift = <9>; -+ reg = <0x4a009120 0x4>; -+}; -+ -+dss_fck: dss_fck@4a009120 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&l3_div_ck>; -+ bit-shift = <1>; -+ reg = <0x4a009120 0x4>; -+}; -+ -+fdif_fck: fdif_fck@4a009028 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_per_m4x2_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009028 0x4>; -+ bit-mask = <0x3>; -+ index-power-of-two; -+}; -+ -+gpio1_dbclk: gpio1_dbclk@4a307838 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4a307838 0x4>; -+}; -+ -+gpio2_dbclk: gpio2_dbclk@4a009460 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4a009460 0x4>; -+}; -+ -+gpio3_dbclk: gpio3_dbclk@4a009468 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4a009468 0x4>; -+}; -+ -+gpio4_dbclk: gpio4_dbclk@4a009470 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4a009470 0x4>; -+}; -+ -+gpio5_dbclk: gpio5_dbclk@4a009478 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4a009478 0x4>; -+}; -+ -+gpio6_dbclk: gpio6_dbclk@4a009480 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4a009480 0x4>; -+}; -+ -+sgx_clk_mux: sgx_clk_mux@4a009220 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&dpll_core_m7x2_ck>, <&dpll_per_m7x2_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009220 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+hsi_fck: hsi_fck@4a009338 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_per_m2x2_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009338 0x4>; -+ bit-mask = <0x3>; -+ index-power-of-two; -+}; -+ -+iss_ctrlclk: iss_ctrlclk@4a009020 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&func_96m_fclk>; -+ bit-shift = <8>; -+ reg = <0x4a009020 0x4>; -+}; -+ -+mcasp_sync_mux_ck: mcasp_sync_mux_ck@4a004540 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; -+ bit-shift = <25>; -+ reg = <0x4a004540 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+func_mcasp_abe_gfclk: func_mcasp_abe_gfclk@4a004540 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; -+ bit-shift = <24>; -+ reg = <0x4a004540 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck@4a004548 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; -+ bit-shift = <25>; -+ reg = <0x4a004548 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+func_mcbsp1_gfclk: func_mcbsp1_gfclk@4a004548 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; -+ bit-shift = <24>; -+ reg = <0x4a004548 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@4a004550 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; -+ bit-shift = <25>; -+ reg = <0x4a004550 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+func_mcbsp2_gfclk: func_mcbsp2_gfclk@4a004550 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; -+ bit-shift = <24>; -+ reg = <0x4a004550 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@4a004558 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; -+ bit-shift = <25>; -+ reg = <0x4a004558 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+func_mcbsp3_gfclk: func_mcbsp3_gfclk@4a004558 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; -+ bit-shift = <24>; -+ reg = <0x4a004558 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck@4a0094e0 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&func_96m_fclk>, <&per_abe_nc_fclk>; -+ bit-shift = <25>; -+ reg = <0x4a0094e0 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+per_mcbsp4_gfclk: per_mcbsp4_gfclk@4a0094e0 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&mcbsp4_sync_mux_ck>, <&pad_clks_ck>; -+ bit-shift = <24>; -+ reg = <0x4a0094e0 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+hsmmc1_fclk: hsmmc1_fclk@4a009328 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&func_64m_fclk>, <&func_96m_fclk>; -+ bit-shift = <24>; -+ reg = <0x4a009328 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+hsmmc2_fclk: hsmmc2_fclk@4a009330 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&func_64m_fclk>, <&func_96m_fclk>; -+ bit-shift = <24>; -+ reg = <0x4a009330 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m@4a0093e0 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&func_48m_fclk>; -+ bit-shift = <8>; -+ reg = <0x4a0093e0 0x4>; -+}; -+ -+sha2md5_fck: sha2md5_fck@4a0095c8 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&l3_div_ck>; -+ bit-shift = <1>; -+ reg = <0x4a0095c8 0x4>; -+}; -+ -+slimbus1_fclk_1: slimbus1_fclk_1@4a004560 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&func_24m_clk>; -+ bit-shift = <9>; -+ reg = <0x4a004560 0x4>; -+}; -+ -+slimbus1_fclk_0: slimbus1_fclk_0@4a004560 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&abe_24m_fclk>; -+ bit-shift = <8>; -+ reg = <0x4a004560 0x4>; -+}; -+ -+slimbus1_fclk_2: slimbus1_fclk_2@4a004560 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&pad_clks_ck>; -+ bit-shift = <10>; -+ reg = <0x4a004560 0x4>; -+}; -+ -+slimbus1_slimbus_clk: slimbus1_slimbus_clk@4a004560 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&slimbus_clk>; -+ bit-shift = <11>; -+ reg = <0x4a004560 0x4>; -+}; -+ -+slimbus2_fclk_1: slimbus2_fclk_1@4a009538 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&per_abe_24m_fclk>; -+ bit-shift = <9>; -+ reg = <0x4a009538 0x4>; -+}; -+ -+slimbus2_fclk_0: slimbus2_fclk_0@4a009538 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&func_24mc_fclk>; -+ bit-shift = <8>; -+ reg = <0x4a009538 0x4>; -+}; -+ -+slimbus2_slimbus_clk: slimbus2_slimbus_clk@4a009538 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&pad_slimbus_core_clks_ck>; -+ bit-shift = <10>; -+ reg = <0x4a009538 0x4>; -+}; -+ -+smartreflex_core_fck: smartreflex_core_fck@4a008638 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&l4_wkup_clk_mux_ck>; -+ bit-shift = <1>; -+ reg = <0x4a008638 0x4>; -+}; -+ -+smartreflex_iva_fck: smartreflex_iva_fck@4a008630 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&l4_wkup_clk_mux_ck>; -+ bit-shift = <1>; -+ reg = <0x4a008630 0x4>; -+}; -+ -+smartreflex_mpu_fck: smartreflex_mpu_fck@4a008628 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&l4_wkup_clk_mux_ck>; -+ bit-shift = <1>; -+ reg = <0x4a008628 0x4>; -+}; -+ -+dmt1_clk_mux: dmt1_clk_mux@4a307840 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>; -+ bit-shift = <24>; -+ reg = <0x4a307840 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+cm2_dm10_mux: cm2_dm10_mux@4a009428 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009428 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+cm2_dm11_mux: cm2_dm11_mux@4a009430 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009430 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+cm2_dm2_mux: cm2_dm2_mux@4a009438 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009438 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+cm2_dm3_mux: cm2_dm3_mux@4a009440 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009440 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+cm2_dm4_mux: cm2_dm4_mux@4a009448 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009448 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+timer5_sync_mux: timer5_sync_mux@4a004568 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; -+ bit-shift = <24>; -+ reg = <0x4a004568 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+timer6_sync_mux: timer6_sync_mux@4a004570 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; -+ bit-shift = <24>; -+ reg = <0x4a004570 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+timer7_sync_mux: timer7_sync_mux@4a004578 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; -+ bit-shift = <24>; -+ reg = <0x4a004578 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+timer8_sync_mux: timer8_sync_mux@4a004580 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; -+ bit-shift = <24>; -+ reg = <0x4a004580 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+cm2_dm9_mux: cm2_dm9_mux@4a009450 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009450 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+usb_host_fs_fck: usb_host_fs_fck@4a0093d0 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&func_48mc_fclk>; -+ reg = <0x4a0093d0 0x4>; -+ bit-shift = <1>; -+}; -+ -+utmi_p1_gfclk: utmi_p1_gfclk@4a009358 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&init_60m_fclk>, <&xclk60mhsp1_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009358 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk@4a009358 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&utmi_p1_gfclk>; -+ bit-shift = <8>; -+ reg = <0x4a009358 0x4>; -+}; -+ -+utmi_p2_gfclk: utmi_p2_gfclk@4a009358 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&init_60m_fclk>, <&xclk60mhsp2_ck>; -+ bit-shift = <25>; -+ reg = <0x4a009358 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk@4a009358 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&utmi_p2_gfclk>; -+ bit-shift = <9>; -+ reg = <0x4a009358 0x4>; -+}; -+ -+usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk@4a009358 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&init_60m_fclk>; -+ bit-shift = <10>; -+ reg = <0x4a009358 0x4>; -+}; -+ -+usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@4a009358 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dpll_usb_m2_ck>; -+ bit-shift = <13>; -+ reg = <0x4a009358 0x4>; -+}; -+ -+usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk@4a009358 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&init_60m_fclk>; -+ bit-shift = <11>; -+ reg = <0x4a009358 0x4>; -+}; -+ -+usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk@4a009358 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&init_60m_fclk>; -+ bit-shift = <12>; -+ reg = <0x4a009358 0x4>; -+}; -+ -+usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk@4a009358 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dpll_usb_m2_ck>; -+ bit-shift = <14>; -+ reg = <0x4a009358 0x4>; -+}; -+ -+usb_host_hs_func48mclk: usb_host_hs_func48mclk@4a009358 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&func_48mc_fclk>; -+ bit-shift = <15>; -+ reg = <0x4a009358 0x4>; -+}; -+ -+usb_host_hs_fck: usb_host_hs_fck@4a009358 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&init_60m_fclk>; -+ bit-shift = <1>; -+ reg = <0x4a009358 0x4>; -+}; -+ -+otg_60m_gfclk: otg_60m_gfclk@4a009360 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&utmi_phy_clkout_ck>, <&xclk60motg_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009360 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+usb_otg_hs_xclk: usb_otg_hs_xclk@4a009360 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&otg_60m_gfclk>; -+ bit-shift = <8>; -+ reg = <0x4a009360 0x4>; -+}; -+ -+usb_otg_hs_ick: usb_otg_hs_ick@4a009360 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&l3_div_ck>; -+ bit-shift = <0>; -+ reg = <0x4a009360 0x4>; -+}; -+ -+usb_phy_cm_clk32k: usb_phy_cm_clk32k@4a008640 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4a008640 0x4>; -+}; -+ -+usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@4a009368 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&init_60m_fclk>; -+ bit-shift = <10>; -+ reg = <0x4a009368 0x4>; -+}; -+ -+usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@4a009368 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&init_60m_fclk>; -+ bit-shift = <8>; -+ reg = <0x4a009368 0x4>; -+}; -+ -+usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@4a009368 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&init_60m_fclk>; -+ bit-shift = <9>; -+ reg = <0x4a009368 0x4>; -+}; -+ -+usb_tll_hs_ick: usb_tll_hs_ick@4a009368 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&l4_div_ck>; -+ bit-shift = <0>; -+ reg = <0x4a009368 0x4>; -+}; -+ -+usim_ck: usim_ck@4a307858 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_per_m4x2_ck>; -+ bit-shift = <24>; -+ reg = <0x4a307858 0x4>; -+ table = < 14 0 >, < 18 1 >; -+ bit-mask = <0x1>; -+}; -+ -+usim_fclk: usim_fclk@4a307858 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&usim_ck>; -+ bit-shift = <8>; -+ reg = <0x4a307858 0x4>; -+}; -+ -+pmd_stm_clock_mux_ck: pmd_stm_clock_mux_ck@4a307a20 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>; -+ bit-shift = <20>; -+ reg = <0x4a307a20 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+pmd_trace_clk_mux_ck: pmd_trace_clk_mux_ck@4a307a20 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>; -+ bit-shift = <22>; -+ reg = <0x4a307a20 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+stm_clk_div_ck: stm_clk_div_ck@4a307a20 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&pmd_stm_clock_mux_ck>; -+ bit-shift = <27>; -+ reg = <0x4a307a20 0x4>; -+ bit-mask = <0x7>; -+ index-power-of-two; -+}; -+ -+trace_clk_div_div_ck: trace_clk_div_div_ck@4a307a20 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ bit-shift = <24>; -+ reg = <0x4a307a20 0x4>; -+ bit-mask = <0x7>; -+ index-power-of-two; -+}; -+ -+trace_clk_div_ck: trace_clk_div_ck { -+ #clock-cells = <0>; -+ compatible = "ti,clkdm-gate-clock"; -+ clocks = <&trace_clk_div_div_ck>; -+}; -+ -+auxclk0_src_mux_ck: auxclk0_src_mux_ck@4a30a310 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; -+ bit-shift = <1>; -+ reg = <0x4a30a310 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+auxclk0_src_ck: auxclk0_src_ck@4a30a310 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&auxclk0_src_mux_ck>; -+ bit-shift = <8>; -+ reg = <0x4a30a310 0x4>; -+}; -+ -+auxclk0_ck: auxclk0_ck@4a30a310 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&auxclk0_src_ck>; -+ bit-shift = <16>; -+ reg = <0x4a30a310 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+auxclk1_src_mux_ck: auxclk1_src_mux_ck@4a30a314 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; -+ bit-shift = <1>; -+ reg = <0x4a30a314 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+auxclk1_src_ck: auxclk1_src_ck@4a30a314 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&auxclk1_src_mux_ck>; -+ bit-shift = <8>; -+ reg = <0x4a30a314 0x4>; -+}; -+ -+auxclk1_ck: auxclk1_ck@4a30a314 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&auxclk1_src_ck>; -+ bit-shift = <16>; -+ reg = <0x4a30a314 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+auxclk2_src_mux_ck: auxclk2_src_mux_ck@4a30a318 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; -+ bit-shift = <1>; -+ reg = <0x4a30a318 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+auxclk2_src_ck: auxclk2_src_ck@4a30a318 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&auxclk2_src_mux_ck>; -+ bit-shift = <8>; -+ reg = <0x4a30a318 0x4>; -+}; -+ -+auxclk2_ck: auxclk2_ck@4a30a318 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&auxclk2_src_ck>; -+ bit-shift = <16>; -+ reg = <0x4a30a318 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+auxclk3_src_mux_ck: auxclk3_src_mux_ck@4a30a31c { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; -+ bit-shift = <1>; -+ reg = <0x4a30a31c 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+auxclk3_src_ck: auxclk3_src_ck@4a30a31c { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&auxclk3_src_mux_ck>; -+ bit-shift = <8>; -+ reg = <0x4a30a31c 0x4>; -+}; -+ -+auxclk3_ck: auxclk3_ck@4a30a31c { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&auxclk3_src_ck>; -+ bit-shift = <16>; -+ reg = <0x4a30a31c 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+auxclk4_src_mux_ck: auxclk4_src_mux_ck@4a30a320 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; -+ bit-shift = <1>; -+ reg = <0x4a30a320 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+auxclk4_src_ck: auxclk4_src_ck@4a30a320 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&auxclk4_src_mux_ck>; -+ bit-shift = <8>; -+ reg = <0x4a30a320 0x4>; -+}; -+ -+auxclk4_ck: auxclk4_ck@4a30a320 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&auxclk4_src_ck>; -+ bit-shift = <16>; -+ reg = <0x4a30a320 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+auxclk5_src_mux_ck: auxclk5_src_mux_ck@4a30a324 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; -+ bit-shift = <1>; -+ reg = <0x4a30a324 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+auxclk5_src_ck: auxclk5_src_ck@4a30a324 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&auxclk5_src_mux_ck>; -+ bit-shift = <8>; -+ reg = <0x4a30a324 0x4>; -+}; -+ -+auxclk5_ck: auxclk5_ck@4a30a324 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&auxclk5_src_ck>; -+ bit-shift = <16>; -+ reg = <0x4a30a324 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+auxclkreq0_ck: auxclkreq0_ck@4a30a210 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; -+ bit-shift = <2>; -+ reg = <0x4a30a210 0x4>; -+ bit-mask = <0x7>; -+}; -+ -+auxclkreq1_ck: auxclkreq1_ck@4a30a214 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; -+ bit-shift = <2>; -+ reg = <0x4a30a214 0x4>; -+ bit-mask = <0x7>; -+}; -+ -+auxclkreq2_ck: auxclkreq2_ck@4a30a218 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; -+ bit-shift = <2>; -+ reg = <0x4a30a218 0x4>; -+ bit-mask = <0x7>; -+}; -+ -+auxclkreq3_ck: auxclkreq3_ck@4a30a21c { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; -+ bit-shift = <2>; -+ reg = <0x4a30a21c 0x4>; -+ bit-mask = <0x7>; -+}; -+ -+auxclkreq4_ck: auxclkreq4_ck@4a30a220 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; -+ bit-shift = <2>; -+ reg = <0x4a30a220 0x4>; -+ bit-mask = <0x7>; -+}; -+ -+auxclkreq5_ck: auxclkreq5_ck@4a30a224 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; -+ bit-shift = <2>; -+ reg = <0x4a30a224 0x4>; -+ bit-mask = <0x7>; -+}; ---- a/arch/arm/boot/dts/omap4.dtsi -+++ b/arch/arm/boot/dts/omap4.dtsi -@@ -17,6 +17,10 @@ - interrupt-parent = <&gic>; - - aliases { -+ i2c0 = &i2c1; -+ i2c1 = &i2c2; -+ i2c2 = &i2c3; -+ i2c3 = &i2c4; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; -@@ -32,6 +36,11 @@ - device_type = "cpu"; - next-level-cache = <&L2>; - reg = <0x0>; -+ -+ clocks = <&dpll_mpu_ck>; -+ clock-names = "cpu"; -+ -+ clock-latency = <300000>; /* From omap-cpufreq driver */ - }; - cpu@1 { - compatible = "arm,cortex-a9"; -@@ -107,6 +116,8 @@ - compatible = "ti,omap-counter32k"; - reg = <0x4a304000 0x20>; - ti,hwmods = "counter_32k"; -+ clocks = <&sys_32k_ck>; -+ clock-names = "fck"; - }; - - omap4_pmx_core: pinmux@4a100040 { -@@ -136,6 +147,8 @@ - #dma-cells = <1>; - #dma-channels = <32>; - #dma-requests = <127>; -+ clocks = <&l3_div_ck>; -+ clock-names = "fck"; - }; - - gpio1: gpio@4a310000 { -@@ -143,6 +156,8 @@ - reg = <0x4a310000 0x200>; - interrupts = ; - ti,hwmods = "gpio1"; -+ clocks = <&l4_wkup_clk_mux_ck>, <&gpio1_dbclk>; -+ clock-names = "fck", "dbclk"; - ti,gpio-always-on; - gpio-controller; - #gpio-cells = <2>; -@@ -155,6 +170,8 @@ - reg = <0x48055000 0x200>; - interrupts = ; - ti,hwmods = "gpio2"; -+ clocks = <&l4_div_ck>, <&gpio2_dbclk>; -+ clock-names = "fck", "dbclk"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; -@@ -166,6 +183,8 @@ - reg = <0x48057000 0x200>; - interrupts = ; - ti,hwmods = "gpio3"; -+ clocks = <&l4_div_ck>, <&gpio3_dbclk>; -+ clock-names = "fck", "dbclk"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; -@@ -177,6 +196,8 @@ - reg = <0x48059000 0x200>; - interrupts = ; - ti,hwmods = "gpio4"; -+ clocks = <&l4_div_ck>, <&gpio4_dbclk>; -+ clock-names = "fck", "dbclk"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; -@@ -188,6 +209,8 @@ - reg = <0x4805b000 0x200>; - interrupts = ; - ti,hwmods = "gpio5"; -+ clocks = <&l4_div_ck>, <&gpio5_dbclk>; -+ clock-names = "fck", "dbclk"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; -@@ -199,6 +222,8 @@ - reg = <0x4805d000 0x200>; - interrupts = ; - ti,hwmods = "gpio6"; -+ clocks = <&l4_div_ck>, <&gpio6_dbclk>; -+ clock-names = "fck", "dbclk"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; -@@ -214,6 +239,7 @@ - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - ti,hwmods = "gpmc"; -+ ti,no-idle; - }; - - uart1: serial@4806a000 { -@@ -221,6 +247,8 @@ - reg = <0x4806a000 0x100>; - interrupts = ; - ti,hwmods = "uart1"; -+ clocks = <&func_48m_fclk>; -+ clock-names = "fck"; - clock-frequency = <48000000>; - }; - -@@ -229,6 +257,8 @@ - reg = <0x4806c000 0x100>; - interrupts = ; - ti,hwmods = "uart2"; -+ clocks = <&func_48m_fclk>; -+ clock-names = "fck"; - clock-frequency = <48000000>; - }; - -@@ -237,6 +267,8 @@ - reg = <0x48020000 0x100>; - interrupts = ; - ti,hwmods = "uart3"; -+ clocks = <&func_48m_fclk>; -+ clock-names = "fck"; - clock-frequency = <48000000>; - }; - -@@ -245,6 +277,8 @@ - reg = <0x4806e000 0x100>; - interrupts = ; - ti,hwmods = "uart4"; -+ clocks = <&func_48m_fclk>; -+ clock-names = "fck"; - clock-frequency = <48000000>; - }; - -@@ -255,6 +289,8 @@ - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c1"; -+ clocks = <&func_96m_fclk>; -+ clock-names = "fck"; - }; - - i2c2: i2c@48072000 { -@@ -264,6 +300,8 @@ - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c2"; -+ clocks = <&func_96m_fclk>; -+ clock-names = "fck"; - }; - - i2c3: i2c@48060000 { -@@ -273,6 +311,8 @@ - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c3"; -+ clocks = <&func_96m_fclk>; -+ clock-names = "fck"; - }; - - i2c4: i2c@48350000 { -@@ -282,6 +322,8 @@ - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c4"; -+ clocks = <&func_96m_fclk>; -+ clock-names = "fck"; - }; - - mcspi1: spi@48098000 { -@@ -291,6 +333,8 @@ - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi1"; -+ clocks = <&func_48m_fclk>; -+ clock-names = "fck"; - ti,spi-num-cs = <4>; - dmas = <&sdma 35>, - <&sdma 36>, -@@ -311,6 +355,8 @@ - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi2"; -+ clocks = <&func_48m_fclk>; -+ clock-names = "fck"; - ti,spi-num-cs = <2>; - dmas = <&sdma 43>, - <&sdma 44>, -@@ -326,6 +372,8 @@ - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi3"; -+ clocks = <&func_48m_fclk>; -+ clock-names = "fck"; - ti,spi-num-cs = <2>; - dmas = <&sdma 15>, <&sdma 16>; - dma-names = "tx0", "rx0"; -@@ -338,6 +386,8 @@ - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi4"; -+ clocks = <&func_48m_fclk>; -+ clock-names = "fck"; - ti,spi-num-cs = <1>; - dmas = <&sdma 70>, <&sdma 71>; - dma-names = "tx0", "rx0"; -@@ -348,6 +398,8 @@ - reg = <0x4809c000 0x400>; - interrupts = ; - ti,hwmods = "mmc1"; -+ clocks = <&hsmmc1_fclk>; -+ clock-names = "fck"; - ti,dual-volt; - ti,needs-special-reset; - dmas = <&sdma 61>, <&sdma 62>; -@@ -359,6 +411,8 @@ - reg = <0x480b4000 0x400>; - interrupts = ; - ti,hwmods = "mmc2"; -+ clocks = <&hsmmc2_fclk>; -+ clock-names = "fck"; - ti,needs-special-reset; - dmas = <&sdma 47>, <&sdma 48>; - dma-names = "tx", "rx"; -@@ -369,6 +423,8 @@ - reg = <0x480ad000 0x400>; - interrupts = ; - ti,hwmods = "mmc3"; -+ clocks = <&func_48m_fclk>; -+ clock-names = "fck"; - ti,needs-special-reset; - dmas = <&sdma 77>, <&sdma 78>; - dma-names = "tx", "rx"; -@@ -379,6 +435,8 @@ - reg = <0x480d1000 0x400>; - interrupts = ; - ti,hwmods = "mmc4"; -+ clocks = <&func_48m_fclk>; -+ clock-names = "fck"; - ti,needs-special-reset; - dmas = <&sdma 57>, <&sdma 58>; - dma-names = "tx", "rx"; -@@ -389,16 +447,20 @@ - reg = <0x480d5000 0x400>; - interrupts = ; - ti,hwmods = "mmc5"; -+ clocks = <&func_48m_fclk>; -+ clock-names = "fck"; - ti,needs-special-reset; - dmas = <&sdma 59>, <&sdma 60>; - dma-names = "tx", "rx"; - }; - - wdt2: wdt@4a314000 { -- compatible = "ti,omap4-wdt", "ti,omap3-wdt"; -+ compatible = "ti,omap4-wdt"; - reg = <0x4a314000 0x80>; - interrupts = ; - ti,hwmods = "wd_timer2"; -+ clocks = <&sys_32k_ck>; -+ clock-names = "fck"; - }; - - mcpdm: mcpdm@40132000 { -@@ -408,6 +470,8 @@ - reg-names = "mpu", "dma"; - interrupts = ; - ti,hwmods = "mcpdm"; -+ clocks = <&pad_clks_ck>; -+ clock-names = "fck"; - dmas = <&sdma 65>, - <&sdma 66>; - dma-names = "up_link", "dn_link"; -@@ -420,6 +484,8 @@ - reg-names = "mpu", "dma"; - interrupts = ; - ti,hwmods = "dmic"; -+ clocks = <&func_dmic_abe_gfclk>; -+ clock-names = "fck"; - dmas = <&sdma 67>; - dma-names = "up_link"; - }; -@@ -433,6 +499,8 @@ - interrupt-names = "common"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp1"; -+ clocks = <&func_mcbsp1_gfclk>, <&pad_clks_ck>, <&mcbsp1_sync_mux_ck>; -+ clock-names = "fck", "pad_fck", "prcm_fck"; - dmas = <&sdma 33>, - <&sdma 34>; - dma-names = "tx", "rx"; -@@ -447,6 +515,8 @@ - interrupt-names = "common"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp2"; -+ clocks = <&func_mcbsp2_gfclk>, <&pad_clks_ck>, <&mcbsp2_sync_mux_ck>; -+ clock-names = "fck", "pad_fck", "prcm_fck"; - dmas = <&sdma 17>, - <&sdma 18>; - dma-names = "tx", "rx"; -@@ -461,6 +531,8 @@ - interrupt-names = "common"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp3"; -+ clocks = <&func_mcbsp3_gfclk>, <&pad_clks_ck>, <&mcbsp3_sync_mux_ck>; -+ clock-names = "fck", "pad_fck", "prcm_fck"; - dmas = <&sdma 19>, - <&sdma 20>; - dma-names = "tx", "rx"; -@@ -474,6 +546,8 @@ - interrupt-names = "common"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp4"; -+ clocks = <&per_mcbsp4_gfclk>, <&pad_clks_ck>, <&mcbsp4_sync_mux_ck>; -+ clock-names = "fck", "pad_fck", "prcm_fck"; - dmas = <&sdma 31>, - <&sdma 32>; - dma-names = "tx", "rx"; -@@ -485,6 +559,15 @@ - interrupts = ; - reg-names = "mpu"; - ti,hwmods = "kbd"; -+ clocks = <&sys_32k_ck>; -+ clock-names = "fck"; -+ }; -+ -+ dmm: dmm@4e000000 { -+ compatible = "ti,omap4-dmm"; -+ reg = <0x4e000000 0x800>; -+ interrupts = <0 113 0x4>; -+ ti,hwmods = "dmm"; - }; - - emif1: emif@4c000000 { -@@ -492,6 +575,9 @@ - reg = <0x4c000000 0x100>; - interrupts = ; - ti,hwmods = "emif1"; -+ ti,no-idle; -+ clocks = <&ddrphy_ck>; -+ clock-names = "fck"; - phy-type = <1>; - hw-caps-read-idle-ctrl; - hw-caps-ll-interface; -@@ -503,6 +589,9 @@ - reg = <0x4d000000 0x100>; - interrupts = ; - ti,hwmods = "emif2"; -+ ti,no-idle; -+ clocks = <&ddrphy_ck>; -+ clock-names = "fck"; - phy-type = <1>; - hw-caps-read-idle-ctrl; - hw-caps-ll-interface; -@@ -516,18 +605,36 @@ - #size-cells = <1>; - ranges; - ti,hwmods = "ocp2scp_usb_phy"; -+ clocks = <&ocp2scp_usb_phy_phy_48m>; -+ clock-names = "fck"; - usb2_phy: usb2phy@4a0ad080 { - compatible = "ti,omap-usb2"; - reg = <0x4a0ad080 0x58>; -- ctrl-module = <&omap_control_usb>; -+ ctrl-module = <&omap_control_usb2phy>; -+ clocks = <&usb_phy_cm_clk32k>, <&ocp2scp_usb_phy_phy_48m>; -+ clock-names = "wkupclk", "refclk"; -+ #phy-cells = <0>; - }; - }; - -+ mailbox: mailbox@4a0f4000 { -+ compatible = "ti,omap4-mailbox"; -+ reg = <0x4a0f4000 0x200>; -+ interrupts = ; -+ ti,hwmods = "mailbox"; -+ ti,mbox-num-users = <3>; -+ ti,mbox-num-fifos = <8>; -+ ti,mbox-names = "mbox-ipu", "mbox-dsp"; -+ ti,mbox-data = <0 1 0 0>, <3 2 0 0>; -+ }; -+ - timer1: timer@4a318000 { - compatible = "ti,omap3430-timer"; - reg = <0x4a318000 0x80>; - interrupts = ; - ti,hwmods = "timer1"; -+ clocks = <&dmt1_clk_mux>; -+ clock-names = "fck"; - ti,timer-alwon; - }; - -@@ -536,6 +643,8 @@ - reg = <0x48032000 0x80>; - interrupts = ; - ti,hwmods = "timer2"; -+ clocks = <&cm2_dm2_mux>; -+ clock-names = "fck"; - }; - - timer3: timer@48034000 { -@@ -543,6 +652,8 @@ - reg = <0x48034000 0x80>; - interrupts = ; - ti,hwmods = "timer3"; -+ clocks = <&cm2_dm3_mux>; -+ clock-names = "fck"; - }; - - timer4: timer@48036000 { -@@ -550,6 +661,8 @@ - reg = <0x48036000 0x80>; - interrupts = ; - ti,hwmods = "timer4"; -+ clocks = <&cm2_dm4_mux>; -+ clock-names = "fck"; - }; - - timer5: timer@40138000 { -@@ -558,6 +671,8 @@ - <0x49038000 0x80>; - interrupts = ; - ti,hwmods = "timer5"; -+ clocks = <&timer5_sync_mux>; -+ clock-names = "fck"; - ti,timer-dsp; - }; - -@@ -567,6 +682,8 @@ - <0x4903a000 0x80>; - interrupts = ; - ti,hwmods = "timer6"; -+ clocks = <&timer6_sync_mux>; -+ clock-names = "fck"; - ti,timer-dsp; - }; - -@@ -576,6 +693,8 @@ - <0x4903c000 0x80>; - interrupts = ; - ti,hwmods = "timer7"; -+ clocks = <&timer7_sync_mux>; -+ clock-names = "fck"; - ti,timer-dsp; - }; - -@@ -585,6 +704,8 @@ - <0x4903e000 0x80>; - interrupts = ; - ti,hwmods = "timer8"; -+ clocks = <&timer8_sync_mux>; -+ clock-names = "fck"; - ti,timer-pwm; - ti,timer-dsp; - }; -@@ -594,6 +715,8 @@ - reg = <0x4803e000 0x80>; - interrupts = ; - ti,hwmods = "timer9"; -+ clocks = <&cm2_dm9_mux>; -+ clock-names = "fck"; - ti,timer-pwm; - }; - -@@ -602,6 +725,8 @@ - reg = <0x48086000 0x80>; - interrupts = ; - ti,hwmods = "timer10"; -+ clocks = <&cm2_dm10_mux>; -+ clock-names = "fck"; - ti,timer-pwm; - }; - -@@ -610,6 +735,8 @@ - reg = <0x48088000 0x80>; - interrupts = ; - ti,hwmods = "timer11"; -+ clocks = <&cm2_dm11_mux>; -+ clock-names = "fck"; - ti,timer-pwm; - }; - -@@ -618,12 +745,16 @@ - reg = <0x4a062000 0x1000>; - interrupts = ; - ti,hwmods = "usb_tll_hs"; -+ clocks = <&usb_tll_hs_ick>; -+ clock-names = "fck"; - }; - - usbhshost: usbhshost@4a064000 { - compatible = "ti,usbhs-host"; - reg = <0x4a064000 0x800>; - ti,hwmods = "usb_host_hs"; -+ clocks = <&usb_host_hs_fck>; -+ clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges; -@@ -643,12 +774,16 @@ - }; - }; - -- omap_control_usb: omap-control-usb@4a002300 { -- compatible = "ti,omap-control-usb"; -- reg = <0x4a002300 0x4>, -- <0x4a00233c 0x4>; -- reg-names = "control_dev_conf", "otghs_control"; -- ti,type = <1>; -+ omap_control_usb2phy: control-phy@4a002300 { -+ compatible = "ti,control-phy-usb2"; -+ reg = <0x4a002300 0x4>; -+ reg-names = "power"; -+ }; -+ -+ omap_control_usbotg: control-phy@4a00233c { -+ compatible = "ti,control-phy-otghs"; -+ reg = <0x4a00233c 0x4>; -+ reg-names = "otghs_control"; - }; - - usb_otg_hs: usb_otg_hs@4a0ab000 { -@@ -657,11 +792,98 @@ - interrupts = , ; - interrupt-names = "mc", "dma"; - ti,hwmods = "usb_otg_hs"; -+ clocks = <&usb_otg_hs_ick>, <&usb_otg_hs_xclk>; -+ clock-names = "fck", "xclk"; - usb-phy = <&usb2_phy>; -+ phys = <&usb2_phy>; -+ phy-names = "usb2-phy"; - multipoint = <1>; - num-eps = <16>; - ram-bits = <12>; -- ti,has-mailbox; -+ ctrl-module = <&omap_control_usbotg>; -+ dr_mode = "peripheral"; -+ }; -+ -+ dss@58000000 { -+ compatible = "ti,omap4-dss", "simple-bus"; -+ reg = <0x58000000 0x80>; -+ ti,hwmods = "dss_core"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ dispc@58001000 { -+ compatible = "ti,omap4-dispc"; -+ reg = <0x58001000 0x1000>; -+ interrupts = <0 25 0x4>; -+ ti,hwmods = "dss_dispc"; -+ }; -+ -+ dpi: encoder@0 { -+ compatible = "ti,omap4-dpi"; -+ }; -+ -+ rfbi: encoder@58002000 { -+ compatible = "ti,omap4-rfbi"; -+ reg = <0x58002000 0x1000>; -+ ti,hwmods = "dss_rfbi"; -+ }; -+ -+ /* -+ * Accessing venc registers cause a crash on omap4, so -+ * this is disabled for now. -+ */ -+ /* -+ venc: encoder@58003000 { -+ compatible = "ti,omap4-venc"; -+ reg = <0x58003000 0x1000>; -+ ti,hwmods = "dss_venc"; -+ }; -+ */ -+ -+ dsi1: encoder@58004000 { -+ compatible = "ti,omap4-dsi"; -+ reg = <0x58004000 0x200>; -+ interrupts = <0 53 0x4>; -+ ti,hwmods = "dss_dsi1"; -+ }; -+ -+ dsi2: encoder@58005000 { -+ compatible = "ti,omap4-dsi"; -+ reg = <0x58005000 0x200>; -+ interrupts = <0 84 0x4>; -+ ti,hwmods = "dss_dsi2"; -+ }; -+ -+ hdmi: encoder@58006000 { -+ compatible = "ti,omap4-hdmi"; -+ reg = <0x58006000 0x200>, -+ <0x58006200 0x100>, -+ <0x58006300 0x100>, -+ <0x58006400 0x1000>; -+ reg-names = "hdmi_wp", "hdmi_pllctrl", -+ "hdmi_txphy", "hdmi_core"; -+ interrupts = <0 101 0x4>; -+ ti,hwmods = "dss_hdmi"; -+ }; -+ }; -+ -+ aes: aes@4b501000 { -+ compatible = "ti,omap4-aes"; -+ ti,hwmods = "aes"; -+ reg = <0x4b501000 0xa0>; -+ interrupts = ; -+ dmas = <&sdma 111>, <&sdma 110>; -+ dma-names = "tx", "rx"; -+ }; -+ -+ des: des@480a5000 { -+ compatible = "ti,omap4-des"; -+ ti,hwmods = "des"; -+ reg = <0x480a5000 0xa0>; -+ interrupts = ; -+ dmas = <&sdma 117>, <&sdma 116>; -+ dma-names = "tx", "rx"; - }; - }; - }; ---- a/arch/arm/boot/dts/omap4-panda-common.dtsi -+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi -@@ -60,22 +60,6 @@ - "AFMR", "Line In"; - }; - -- /* -- * Temp hack: Need to be replaced with the proper gpio-controlled -- * reset driver as soon it will be merged. -- * http://thread.gmane.org/gmane.linux.drivers.devicetree/36830 -- */ -- /* HS USB Port 1 RESET */ -- hsusb1_reset: hsusb1_reset_reg { -- compatible = "regulator-fixed"; -- regulator-name = "hsusb1_reset"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- gpio = <&gpio2 30 0>; /* gpio_62 */ -- startup-delay-us = <70000>; -- enable-active-high; -- }; -- - /* HS USB Port 1 Power */ - hsusb1_power: hsusb1_power_reg { - compatible = "regulator-fixed"; -@@ -97,14 +81,10 @@ - /* HS USB Host PHY on PORT 1 */ - hsusb1_phy: hsusb1_phy { - compatible = "usb-nop-xceiv"; -- reset-supply = <&hsusb1_reset>; -+ reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */ - vcc-supply = <&hsusb1_power>; -- /** -- * FIXME: -- * put the right clock phandle here when available -- * clocks = <&auxclk3>; -- * clock-names = "main_clk"; -- */ -+ clocks = <&auxclk3_ck>; -+ clock-names = "main_clk"; - clock-frequency = <19200000>; - }; - -@@ -401,3 +381,51 @@ - &usbhsehci { - phys = <&hsusb1_phy>; - }; -+ -+&dsi1 { -+ vdds_dsi-supply = <&vcxio>; -+}; -+ -+&dsi2 { -+ vdds_dsi-supply = <&vcxio>; -+}; -+ -+&hdmi { -+ vdda_hdmi_dac-supply = <&vdac>; -+}; -+ -+/ { -+ aliases { -+ display0 = &dvi0; -+ display1 = &hdmi0; -+ }; -+ -+ tfp410: encoder@0 { -+ compatible = "ti,tfp410"; -+ video-source = <&dpi>; -+ data-lines = <24>; -+ gpios = <&gpio1 0 0>; /* 0, power-down */ -+ }; -+ -+ dvi0: connector@0 { -+ compatible = "ti,dvi_connector"; -+ video-source = <&tfp410>; -+ i2c-bus = <&i2c3>; -+ }; -+ -+ tpd12s015: encoder@1 { -+ compatible = "ti,tpd12s015"; -+ -+ video-source = <&hdmi>; -+ -+ gpios = <&gpio2 28 0>, /* 60, CT CP HPD */ -+ <&gpio2 9 0>, /* 41, LS OE */ -+ <&gpio2 31 0>; /* 63, HPD */ -+ }; -+ -+ hdmi0: connector@1 { -+ compatible = "ti,hdmi_connector"; -+ -+ video-source = <&tpd12s015>; -+ }; -+}; ---- a/arch/arm/boot/dts/omap4-sdp.dts -+++ b/arch/arm/boot/dts/omap4-sdp.dts -@@ -569,3 +569,73 @@ - mode = <3>; - power = <50>; - }; -+ -+&dsi1 { -+ vdds_dsi-supply = <&vcxio>; -+}; -+ -+&dsi2 { -+ vdds_dsi-supply = <&vcxio>; -+}; -+ -+&hdmi { -+ vdda_hdmi_dac-supply = <&vdac>; -+}; -+ -+/ { -+ aliases { -+ display0 = &lcd0; -+ display1 = &lcd1; -+ display2 = &hdmi0; -+ }; -+ -+ lcd0: display@0 { -+ compatible = "tpo,taal", "panel-dsi-cm"; -+ -+ video-source = <&dsi1>; -+ -+ lanes = < -+ 0 /* clk + */ -+ 1 /* clk - */ -+ 2 /* data1 + */ -+ 3 /* data1 - */ -+ 4 /* data2 + */ -+ 5 /* data2 - */ -+ >; -+ -+ gpios = <&gpio4 6 0>; /* 102, reset */ -+ }; -+ -+ lcd1: display@1 { -+ compatible = "tpo,taal", "panel-dsi-cm"; -+ -+ video-source = <&dsi2>; -+ -+ lanes = < -+ 0 /* clk + */ -+ 1 /* clk - */ -+ 2 /* data1 + */ -+ 3 /* data1 - */ -+ 4 /* data2 + */ -+ 5 /* data2 - */ -+ >; -+ -+ gpios = <&gpio4 8 0>; /* 104, reset */ -+ }; -+ -+ tpd12s015: encoder@0 { -+ compatible = "ti,tpd12s015"; -+ -+ video-source = <&hdmi>; -+ -+ gpios = <&gpio2 28 0>, /* 60, CT CP HPD */ -+ <&gpio2 9 0>, /* 41, LS OE */ -+ <&gpio2 31 0>; /* 63, HPD */ -+ }; -+ -+ hdmi0: connector@0 { -+ compatible = "ti,hdmi_connector"; -+ -+ video-source = <&tpd12s015>; -+ }; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi -@@ -0,0 +1,1400 @@ -+/* -+ * Device Tree Source for OMAP5 clock data -+ * -+ * Copyright (C) 2013 Texas Instruments, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+pad_clks_src_ck: pad_clks_src_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <12000000>; -+}; -+ -+pad_clks_ck: pad_clks_ck@4a004108 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&pad_clks_src_ck>; -+ bit-shift = <8>; -+ reg = <0x4a004108 0x4>; -+}; -+ -+secure_32k_clk_src_ck: secure_32k_clk_src_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <32768>; -+}; -+ -+slimbus_src_clk: slimbus_src_clk { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <12000000>; -+}; -+ -+slimbus_clk: slimbus_clk@4a004108 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&slimbus_src_clk>; -+ bit-shift = <10>; -+ reg = <0x4a004108 0x4>; -+}; -+ -+sys_32k_ck: sys_32k_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <32768>; -+}; -+ -+virt_12000000_ck: virt_12000000_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <12000000>; -+}; -+ -+virt_13000000_ck: virt_13000000_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <13000000>; -+}; -+ -+virt_16800000_ck: virt_16800000_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <16800000>; -+}; -+ -+virt_19200000_ck: virt_19200000_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <19200000>; -+}; -+ -+virt_26000000_ck: virt_26000000_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <26000000>; -+}; -+ -+virt_27000000_ck: virt_27000000_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <27000000>; -+}; -+ -+virt_38400000_ck: virt_38400000_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <38400000>; -+}; -+ -+sys_clkin: sys_clkin@4ae06110 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; -+ reg = <0x4ae06110 0x4>; -+ bit-mask = <0x7>; -+ index-starts-at-one; -+}; -+ -+xclk60mhsp1_ck: xclk60mhsp1_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <60000000>; -+}; -+ -+xclk60mhsp2_ck: xclk60mhsp2_ck { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <60000000>; -+}; -+ -+abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@4ae06108 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin>, <&sys_32k_ck>; -+ reg = <0x4ae06108 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+abe_dpll_clk_mux: abe_dpll_clk_mux@4ae0610c { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin>, <&sys_32k_ck>; -+ reg = <0x4ae0610c 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+dpll_abe_ck: dpll_abe_ck@4a0041e0 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-m4xen-clock"; -+ clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; -+ reg = <0x4a0041e0 0x4>, <0x4a0041e4 0x4>, <0x4a0041e8 0x4>, <0x4a0041ec 0x4>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+}; -+ -+dpll_abe_x2_ck: dpll_abe_x2_ck { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-x2-clock"; -+ clocks = <&dpll_abe_ck>; -+}; -+ -+dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@4a0041f0 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_abe_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a0041f0 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+abe_24m_fclk: abe_24m_fclk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_abe_m2x2_ck>; -+ clock-mult = <1>; -+ clock-div = <8>; -+}; -+ -+abe_clk: abe_clk@4a004108 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_abe_m2x2_ck>; -+ reg = <0x4a004108 0x4>; -+ bit-mask = <0x3>; -+ index-power-of-two; -+}; -+ -+abe_iclk: abe_iclk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&abe_clk>; -+ clock-mult = <1>; -+ clock-div = <2>; -+}; -+ -+abe_lp_clk_div: abe_lp_clk_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_abe_m2x2_ck>; -+ clock-mult = <1>; -+ clock-div = <16>; -+}; -+ -+dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@4a0041f4 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_abe_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a0041f4 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_core_ck: dpll_core_ck@4a004120 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-core-clock"; -+ clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>; -+ reg = <0x4a004120 0x4>, <0x4a004124 0x4>, <0x4a004128 0x4>, <0x4a00412c 0x4>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+}; -+ -+dpll_core_x2_ck: dpll_core_x2_ck { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-x2-clock"; -+ clocks = <&dpll_core_ck>; -+}; -+ -+dpll_core_h21x2_ck: dpll_core_h21x2_ck@4a004150 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_core_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a004150 0x4>; -+ bit-mask = <0x3f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+c2c_fclk: c2c_fclk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_core_h21x2_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+c2c_iclk: c2c_iclk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&c2c_fclk>; -+ clock-mult = <1>; -+ clock-div = <2>; -+}; -+ -+custefuse_sys_gfclk_div: custefuse_sys_gfclk_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&sys_clkin>; -+ clock-mult = <1>; -+ clock-div = <2>; -+}; -+ -+dpll_core_h11x2_ck: dpll_core_h11x2_ck@4a004138 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_core_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a004138 0x4>; -+ bit-mask = <0x3f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_core_h12x2_ck: dpll_core_h12x2_ck@4a00413c { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_core_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a00413c 0x4>; -+ bit-mask = <0x3f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_core_h13x2_ck: dpll_core_h13x2_ck@4a004140 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_core_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a004140 0x4>; -+ bit-mask = <0x3f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_core_h14x2_ck: dpll_core_h14x2_ck@4a004144 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_core_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a004144 0x4>; -+ bit-mask = <0x3f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_core_h22x2_ck: dpll_core_h22x2_ck@4a004154 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_core_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a004154 0x4>; -+ bit-mask = <0x3f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_core_h23x2_ck: dpll_core_h23x2_ck@4a004158 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_core_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a004158 0x4>; -+ bit-mask = <0x3f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_core_h24x2_ck: dpll_core_h24x2_ck@4a00415c { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_core_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a00415c 0x4>; -+ bit-mask = <0x3f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_core_m2_ck: dpll_core_m2_ck@4a004130 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_core_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a004130 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_core_m3x2_ck: dpll_core_m3x2_ck@4a004134 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_core_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a004134 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_core_h12x2_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+dpll_iva_ck: dpll_iva_ck@4a0041a0 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-clock"; -+ clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>; -+ reg = <0x4a0041a0 0x4>, <0x4a0041a4 0x4>, <0x4a0041a8 0x4>, <0x4a0041ac 0x4>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+}; -+ -+dpll_iva_x2_ck: dpll_iva_x2_ck { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-x2-clock"; -+ clocks = <&dpll_iva_ck>; -+}; -+ -+dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@4a0041b8 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_iva_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a0041b8 0x4>; -+ bit-mask = <0x3f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@4a0041bc { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_iva_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a0041bc 0x4>; -+ bit-mask = <0x3f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_core_h12x2_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+dpll_mpu_ck: dpll_mpu_ck@4a004160 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-clock"; -+ clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>; -+ reg = <0x4a004160 0x4>, <0x4a004164 0x4>, <0x4a004168 0x4>, <0x4a00416c 0x4>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+}; -+ -+dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a004170 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_mpu_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a004170 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+per_dpll_hs_clk_div: per_dpll_hs_clk_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_abe_m3x2_ck>; -+ clock-mult = <1>; -+ clock-div = <2>; -+}; -+ -+dpll_per_ck: dpll_per_ck@4a008140 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-clock"; -+ clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>; -+ reg = <0x4a008140 0x4>, <0x4a008144 0x4>, <0x4a008148 0x4>, <0x4a00814c 0x4>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+}; -+ -+dpll_per_x2_ck: dpll_per_x2_ck { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-x2-clock"; -+ clocks = <&dpll_per_ck>; -+}; -+ -+dpll_per_h11x2_ck: dpll_per_h11x2_ck@4a008158 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_per_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a008158 0x4>; -+ bit-mask = <0x3f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_per_h12x2_ck: dpll_per_h12x2_ck@4a00815c { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_per_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a00815c 0x4>; -+ bit-mask = <0x3f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_per_h14x2_ck: dpll_per_h14x2_ck@4a008164 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_per_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a008164 0x4>; -+ bit-mask = <0x3f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_per_m2_ck: dpll_per_m2_ck@4a008150 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_per_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a008150 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_per_m2x2_ck: dpll_per_m2x2_ck@4a008150 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_per_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a008150 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_per_m3x2_ck: dpll_per_m3x2_ck@4a008154 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_per_x2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a008154 0x4>; -+ bit-mask = <0x1f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_unipro1_ck: dpll_unipro1_ck@4a008200 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-clock"; -+ clocks = <&sys_clkin>, <&sys_clkin>; -+ reg = <0x4a008200 0x4>, <0x4a008204 0x4>, <0x4a008208 0x4>, <0x4a00820c 0x4>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+}; -+ -+dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_unipro1_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@4a008210 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_unipro1_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a008210 0x4>; -+ bit-mask = <0x7f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dpll_unipro2_ck: dpll_unipro2_ck@4a0081c0 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-clock"; -+ clocks = <&sys_clkin>, <&sys_clkin>; -+ reg = <0x4a0081c0 0x4>, <0x4a0081c4 0x4>, <0x4a0081c8 0x4>, <0x4a0081cc 0x4>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+}; -+ -+dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_unipro2_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@4a0081d0 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_unipro2_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a0081d0 0x4>; -+ bit-mask = <0x7f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+usb_dpll_hs_clk_div: usb_dpll_hs_clk_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_abe_m3x2_ck>; -+ clock-mult = <1>; -+ clock-div = <3>; -+}; -+ -+dpll_usb_ck: dpll_usb_ck@4a008180 { -+ #clock-cells = <0>; -+ compatible = "ti,omap4-dpll-j-type-clock"; -+ clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>; -+ reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>, <0x4a00818c 0x4>; -+ reg-names = "control", "idlest", "autoidle", "mult-div1"; -+}; -+ -+dpll_usb_clkdcoldo: dpll_usb_clkdcoldo { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_usb_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 { -+ #clock-cells = <0>; -+ compatible = "ti,divider-clock"; -+ clocks = <&dpll_usb_ck>; -+ ti,autoidle-shift = <8>; -+ reg = <0x4a008190 0x4>; -+ bit-mask = <0x7f>; -+ index-starts-at-one; -+ ti,autoidle-low; -+}; -+ -+dss_syc_gfclk_div: dss_syc_gfclk_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&sys_clkin>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+func_128m_clk: func_128m_clk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_per_h11x2_ck>; -+ clock-mult = <1>; -+ clock-div = <2>; -+}; -+ -+func_12m_fclk: func_12m_fclk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_per_m2x2_ck>; -+ clock-mult = <1>; -+ clock-div = <16>; -+}; -+ -+func_24m_clk: func_24m_clk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_per_m2_ck>; -+ clock-mult = <1>; -+ clock-div = <4>; -+}; -+ -+func_48m_fclk: func_48m_fclk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_per_m2x2_ck>; -+ clock-mult = <1>; -+ clock-div = <4>; -+}; -+ -+func_96m_fclk: func_96m_fclk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_per_m2x2_ck>; -+ clock-mult = <1>; -+ clock-div = <2>; -+}; -+ -+l3_iclk_div: l3_iclk_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&dpll_core_h12x2_ck>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+gpu_l3_iclk: gpu_l3_iclk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&l3_iclk_div>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+l3init_60m_fclk: l3init_60m_fclk@4a008104 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_usb_m2_ck>; -+ reg = <0x4a008104 0x4>; -+ table = < 1 0 >, < 8 1 >; -+ bit-mask = <0x1>; -+}; -+ -+wkupaon_iclk_mux: wkupaon_iclk_mux@4ae06108 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin>, <&abe_lp_clk_div>; -+ reg = <0x4ae06108 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+l3instr_ts_gclk_div: l3instr_ts_gclk_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&wkupaon_iclk_mux>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+l4_root_clk_div: l4_root_clk_div { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&l3_iclk_div>; -+ clock-mult = <1>; -+ clock-div = <1>; -+}; -+ -+dss_32khz_clk: dss_32khz_clk@4a009420 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <11>; -+ reg = <0x4a009420 0x4>; -+}; -+ -+dss_48mhz_clk: dss_48mhz_clk@4a009420 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&func_48m_fclk>; -+ bit-shift = <9>; -+ reg = <0x4a009420 0x4>; -+}; -+ -+dss_dss_clk: dss_dss_clk@4a009420 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dpll_per_h12x2_ck>; -+ bit-shift = <8>; -+ reg = <0x4a009420 0x4>; -+}; -+ -+dss_sys_clk: dss_sys_clk@4a009420 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dss_syc_gfclk_div>; -+ bit-shift = <10>; -+ reg = <0x4a009420 0x4>; -+}; -+ -+gpio1_dbclk: gpio1_dbclk@4ae07938 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4ae07938 0x4>; -+}; -+ -+gpio2_dbclk: gpio2_dbclk@4a009060 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4a009060 0x4>; -+}; -+ -+gpio3_dbclk: gpio3_dbclk@4a009068 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4a009068 0x4>; -+}; -+ -+gpio4_dbclk: gpio4_dbclk@4a009070 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4a009070 0x4>; -+}; -+ -+gpio5_dbclk: gpio5_dbclk@4a009078 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4a009078 0x4>; -+}; -+ -+gpio6_dbclk: gpio6_dbclk@4a009080 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4a009080 0x4>; -+}; -+ -+gpio7_dbclk: gpio7_dbclk@4a009110 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4a009110 0x4>; -+}; -+ -+gpio8_dbclk: gpio8_dbclk@4a009118 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4a009118 0x4>; -+}; -+ -+iss_ctrlclk: iss_ctrlclk@4a009320 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&func_96m_fclk>; -+ bit-shift = <8>; -+ reg = <0x4a009320 0x4>; -+}; -+ -+lli_txphy_clk: lli_txphy_clk@4a008f20 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dpll_unipro1_clkdcoldo>; -+ bit-shift = <8>; -+ reg = <0x4a008f20 0x4>; -+}; -+ -+lli_txphy_ls_clk: lli_txphy_ls_clk@4a008f20 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dpll_unipro1_m2_ck>; -+ bit-shift = <9>; -+ reg = <0x4a008f20 0x4>; -+}; -+ -+mmc1_32khz_clk: mmc1_32khz_clk@4a009628 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4a009628 0x4>; -+}; -+ -+sata_ref_clk: sata_ref_clk@4a009688 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_clkin>; -+ bit-shift = <8>; -+ reg = <0x4a009688 0x4>; -+}; -+ -+slimbus1_slimbus_clk: slimbus1_slimbus_clk@4a004560 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&slimbus_clk>; -+ bit-shift = <11>; -+ reg = <0x4a004560 0x4>; -+}; -+ -+usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@4a009658 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dpll_usb_m2_ck>; -+ bit-shift = <13>; -+ reg = <0x4a009658 0x4>; -+}; -+ -+usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk@4a009658 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dpll_usb_m2_ck>; -+ bit-shift = <14>; -+ reg = <0x4a009658 0x4>; -+}; -+ -+usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk@4a009658 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dpll_usb_m2_ck>; -+ bit-shift = <7>; -+ reg = <0x4a009658 0x4>; -+}; -+ -+usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk@4a009658 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&l3init_60m_fclk>; -+ bit-shift = <11>; -+ reg = <0x4a009658 0x4>; -+}; -+ -+usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk@4a009658 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&l3init_60m_fclk>; -+ bit-shift = <12>; -+ reg = <0x4a009658 0x4>; -+}; -+ -+usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk@4a009658 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&l3init_60m_fclk>; -+ bit-shift = <6>; -+ reg = <0x4a009658 0x4>; -+}; -+ -+utmi_p1_gfclk: utmi_p1_gfclk@4a009658 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009658 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk@4a009658 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&utmi_p1_gfclk>; -+ bit-shift = <8>; -+ reg = <0x4a009658 0x4>; -+}; -+ -+utmi_p2_gfclk: utmi_p2_gfclk@4a009658 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>; -+ bit-shift = <25>; -+ reg = <0x4a009658 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk@4a009658 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&utmi_p2_gfclk>; -+ bit-shift = <9>; -+ reg = <0x4a009658 0x4>; -+}; -+ -+usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk@4a009658 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&l3init_60m_fclk>; -+ bit-shift = <10>; -+ reg = <0x4a009658 0x4>; -+}; -+ -+usb_otg_ss_refclk960m: usb_otg_ss_refclk960m@4a0096f0 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&dpll_usb_clkdcoldo>; -+ bit-shift = <8>; -+ reg = <0x4a0096f0 0x4>; -+}; -+ -+usb_phy_cm_clk32k: usb_phy_cm_clk32k@4a008640 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&sys_32k_ck>; -+ bit-shift = <8>; -+ reg = <0x4a008640 0x4>; -+}; -+ -+usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@4a009668 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&l3init_60m_fclk>; -+ bit-shift = <8>; -+ reg = <0x4a009668 0x4>; -+}; -+ -+usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@4a009668 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&l3init_60m_fclk>; -+ bit-shift = <9>; -+ reg = <0x4a009668 0x4>; -+}; -+ -+usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@4a009668 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&l3init_60m_fclk>; -+ bit-shift = <10>; -+ reg = <0x4a009668 0x4>; -+}; -+ -+aess_fclk: aess_fclk@4a004528 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&abe_clk>; -+ bit-shift = <24>; -+ reg = <0x4a004528 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+dmic_sync_mux_ck: dmic_sync_mux_ck@4a004538 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; -+ bit-shift = <26>; -+ reg = <0x4a004538 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+dmic_gfclk: dmic_gfclk@4a004538 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; -+ bit-shift = <24>; -+ reg = <0x4a004538 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+fdif_fclk: fdif_fclk@4a009328 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_per_h11x2_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009328 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+gpu_core_gclk_mux: gpu_core_gclk_mux@4a009520 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009520 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@4a009520 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; -+ bit-shift = <25>; -+ reg = <0x4a009520 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+hsi_fclk: hsi_fclk@4a009638 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&dpll_per_m2x2_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009638 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+mcasp_sync_mux_ck: mcasp_sync_mux_ck@4a004540 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; -+ bit-shift = <26>; -+ reg = <0x4a004540 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+mcasp_gfclk: mcasp_gfclk@4a004540 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; -+ bit-shift = <24>; -+ reg = <0x4a004540 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck@4a004548 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; -+ bit-shift = <26>; -+ reg = <0x4a004548 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+mcbsp1_gfclk: mcbsp1_gfclk@4a004548 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; -+ bit-shift = <24>; -+ reg = <0x4a004548 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@4a004550 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; -+ bit-shift = <26>; -+ reg = <0x4a004550 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+mcbsp2_gfclk: mcbsp2_gfclk@4a004550 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; -+ bit-shift = <24>; -+ reg = <0x4a004550 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@4a004558 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; -+ bit-shift = <26>; -+ reg = <0x4a004558 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+mcbsp3_gfclk: mcbsp3_gfclk@4a004558 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; -+ bit-shift = <24>; -+ reg = <0x4a004558 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+mmc1_fclk_mux: mmc1_fclk_mux@4a009628 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009628 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+mmc1_fclk: mmc1_fclk@4a009628 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&mmc1_fclk_mux>; -+ bit-shift = <25>; -+ reg = <0x4a009628 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+mmc2_fclk_mux: mmc2_fclk_mux@4a009630 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009630 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+mmc2_fclk: mmc2_fclk@4a009630 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&mmc2_fclk_mux>; -+ bit-shift = <25>; -+ reg = <0x4a009630 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+timer10_gfclk_mux: timer10_gfclk_mux@4a009028 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin>, <&sys_32k_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009028 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+timer11_gfclk_mux: timer11_gfclk_mux@4a009030 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin>, <&sys_32k_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009030 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+timer1_gfclk_mux: timer1_gfclk_mux@4ae07940 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin>, <&sys_32k_ck>; -+ bit-shift = <24>; -+ reg = <0x4ae07940 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+timer2_gfclk_mux: timer2_gfclk_mux@4a009038 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin>, <&sys_32k_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009038 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+timer3_gfclk_mux: timer3_gfclk_mux@4a009040 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin>, <&sys_32k_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009040 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+timer4_gfclk_mux: timer4_gfclk_mux@4a009048 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin>, <&sys_32k_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009048 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+timer5_gfclk_mux: timer5_gfclk_mux@4a004568 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; -+ bit-shift = <24>; -+ reg = <0x4a004568 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+timer6_gfclk_mux: timer6_gfclk_mux@4a004570 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; -+ bit-shift = <24>; -+ reg = <0x4a004570 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+timer7_gfclk_mux: timer7_gfclk_mux@4a004578 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; -+ bit-shift = <24>; -+ reg = <0x4a004578 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+timer8_gfclk_mux: timer8_gfclk_mux@4a004580 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; -+ bit-shift = <24>; -+ reg = <0x4a004580 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+timer9_gfclk_mux: timer9_gfclk_mux@4a009050 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin>, <&sys_32k_ck>; -+ bit-shift = <24>; -+ reg = <0x4a009050 0x4>; -+ bit-mask = <0x1>; -+}; -+ -+auxclk0_src_mux_ck: auxclk0_src_mux_ck@4ae0a310 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; -+ bit-shift = <1>; -+ reg = <0x4ae0a310 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+auxclk0_src_ck: auxclk0_src_ck@4ae0a310 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&auxclk0_src_mux_ck>; -+ bit-shift = <8>; -+ reg = <0x4ae0a310 0x4>; -+}; -+ -+auxclk0_ck: auxclk0_ck@4ae0a310 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&auxclk0_src_ck>; -+ bit-shift = <16>; -+ reg = <0x4ae0a310 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+auxclk1_src_mux_ck: auxclk1_src_mux_ck@4ae0a314 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; -+ bit-shift = <1>; -+ reg = <0x4ae0a314 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+auxclk1_src_ck: auxclk1_src_ck@4ae0a314 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&auxclk1_src_mux_ck>; -+ bit-shift = <8>; -+ reg = <0x4ae0a314 0x4>; -+}; -+ -+auxclk1_ck: auxclk1_ck@4ae0a314 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&auxclk1_src_ck>; -+ bit-shift = <16>; -+ reg = <0x4ae0a314 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+auxclk2_src_mux_ck: auxclk2_src_mux_ck@4ae0a318 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; -+ bit-shift = <1>; -+ reg = <0x4ae0a318 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+auxclk2_src_ck: auxclk2_src_ck@4ae0a318 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&auxclk2_src_mux_ck>; -+ bit-shift = <8>; -+ reg = <0x4ae0a318 0x4>; -+}; -+ -+auxclk2_ck: auxclk2_ck@4ae0a318 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&auxclk2_src_ck>; -+ bit-shift = <16>; -+ reg = <0x4ae0a318 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+auxclk3_src_mux_ck: auxclk3_src_mux_ck@4ae0a31c { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; -+ bit-shift = <1>; -+ reg = <0x4ae0a31c 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+auxclk3_src_ck: auxclk3_src_ck@4ae0a31c { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&auxclk3_src_mux_ck>; -+ bit-shift = <8>; -+ reg = <0x4ae0a31c 0x4>; -+}; -+ -+auxclk3_ck: auxclk3_ck@4ae0a31c { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&auxclk3_src_ck>; -+ bit-shift = <16>; -+ reg = <0x4ae0a31c 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+auxclk4_src_mux_ck: auxclk4_src_mux_ck@4ae0a320 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; -+ bit-shift = <1>; -+ reg = <0x4ae0a320 0x4>; -+ bit-mask = <0x3>; -+}; -+ -+auxclk4_src_ck: auxclk4_src_ck@4ae0a320 { -+ #clock-cells = <0>; -+ compatible = "gate-clock"; -+ clocks = <&auxclk4_src_mux_ck>; -+ bit-shift = <8>; -+ reg = <0x4ae0a320 0x4>; -+}; -+ -+auxclk4_ck: auxclk4_ck@4ae0a320 { -+ #clock-cells = <0>; -+ compatible = "divider-clock"; -+ clocks = <&auxclk4_src_ck>; -+ bit-shift = <16>; -+ reg = <0x4ae0a320 0x4>; -+ bit-mask = <0xf>; -+}; -+ -+auxclkreq0_ck: auxclkreq0_ck@4ae0a210 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; -+ bit-shift = <2>; -+ reg = <0x4ae0a210 0x4>; -+ bit-mask = <0x7>; -+}; -+ -+auxclkreq1_ck: auxclkreq1_ck@4ae0a214 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; -+ bit-shift = <2>; -+ reg = <0x4ae0a214 0x4>; -+ bit-mask = <0x7>; -+}; -+ -+auxclkreq2_ck: auxclkreq2_ck@4ae0a218 { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; -+ bit-shift = <2>; -+ reg = <0x4ae0a218 0x4>; -+ bit-mask = <0x7>; -+}; -+ -+auxclkreq3_ck: auxclkreq3_ck@4ae0a21c { -+ #clock-cells = <0>; -+ compatible = "mux-clock"; -+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; -+ bit-shift = <2>; -+ reg = <0x4ae0a21c 0x4>; -+ bit-mask = <0x7>; -+}; ---- a/arch/arm/boot/dts/omap5.dtsi -+++ b/arch/arm/boot/dts/omap5.dtsi -@@ -21,6 +21,11 @@ - interrupt-parent = <&gic>; - - aliases { -+ i2c0 = &i2c1; -+ i2c1 = &i2c2; -+ i2c2 = &i2c3; -+ i2c3 = &i2c4; -+ i2c4 = &i2c5; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; -@@ -33,10 +38,23 @@ - #address-cells = <1>; - #size-cells = <0>; - -- cpu@0 { -+ cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x0>; -+ -+ operating-points = < -+ /* kHz uV */ -+ 500000 880000 -+ 1000000 1060000 -+ 1500000 1250000 -+ >; -+ -+ clocks = <&dpll_mpu_ck>; -+ clock-names = "cpu"; -+ -+ clock-latency = <300000>; /* From omap-cpufreq driver */ -+ - }; - cpu@1 { - device_type = "cpu"; -@@ -52,7 +70,6 @@ - , - , - ; -- clock-frequency = <6144000>; - }; - - gic: interrupt-controller@48211000 { -@@ -100,6 +117,8 @@ - compatible = "ti,omap-counter32k"; - reg = <0x4ae04000 0x40>; - ti,hwmods = "counter_32k"; -+ clocks = <&wkupaon_iclk_mux>; -+ clock-names = "fck"; - }; - - omap5_pmx_core: pinmux@4a002840 { -@@ -129,6 +148,8 @@ - #dma-cells = <1>; - #dma-channels = <32>; - #dma-requests = <127>; -+ clocks = <&l3_iclk_div>; -+ clock-names = "fck"; - }; - - gpio1: gpio@4ae10000 { -@@ -136,6 +157,8 @@ - reg = <0x4ae10000 0x200>; - interrupts = ; - ti,hwmods = "gpio1"; -+ clocks = <&wkupaon_iclk_mux>, <&gpio1_dbclk>; -+ clock-names = "fck", "dbclk"; - ti,gpio-always-on; - gpio-controller; - #gpio-cells = <2>; -@@ -148,6 +171,8 @@ - reg = <0x48055000 0x200>; - interrupts = ; - ti,hwmods = "gpio2"; -+ clocks = <&l4_root_clk_div>, <&gpio2_dbclk>; -+ clock-names = "fck", "dbclk"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; -@@ -159,6 +184,8 @@ - reg = <0x48057000 0x200>; - interrupts = ; - ti,hwmods = "gpio3"; -+ clocks = <&l4_root_clk_div>, <&gpio3_dbclk>; -+ clock-names = "fck", "dbclk"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; -@@ -170,6 +197,8 @@ - reg = <0x48059000 0x200>; - interrupts = ; - ti,hwmods = "gpio4"; -+ clocks = <&l4_root_clk_div>, <&gpio4_dbclk>; -+ clock-names = "fck", "dbclk"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; -@@ -181,6 +210,8 @@ - reg = <0x4805b000 0x200>; - interrupts = ; - ti,hwmods = "gpio5"; -+ clocks = <&l4_root_clk_div>, <&gpio5_dbclk>; -+ clock-names = "fck", "dbclk"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; -@@ -192,6 +223,8 @@ - reg = <0x4805d000 0x200>; - interrupts = ; - ti,hwmods = "gpio6"; -+ clocks = <&l4_root_clk_div>, <&gpio6_dbclk>; -+ clock-names = "fck", "dbclk"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; -@@ -203,6 +236,8 @@ - reg = <0x48051000 0x200>; - interrupts = ; - ti,hwmods = "gpio7"; -+ clocks = <&l4_root_clk_div>, <&gpio7_dbclk>; -+ clock-names = "fck", "dbclk"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; -@@ -214,6 +249,8 @@ - reg = <0x48053000 0x200>; - interrupts = ; - ti,hwmods = "gpio8"; -+ clocks = <&l4_root_clk_div>, <&gpio8_dbclk>; -+ clock-names = "fck", "dbclk"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; -@@ -238,6 +275,9 @@ - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c1"; -+ clocks = <&func_96m_fclk>; -+ clock-names = "fck"; -+ status = "disabled"; - }; - - i2c2: i2c@48072000 { -@@ -247,6 +287,9 @@ - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c2"; -+ clocks = <&func_96m_fclk>; -+ clock-names = "fck"; -+ status = "disabled"; - }; - - i2c3: i2c@48060000 { -@@ -256,6 +299,9 @@ - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c3"; -+ clocks = <&func_96m_fclk>; -+ clock-names = "fck"; -+ status = "disabled"; - }; - - i2c4: i2c@4807a000 { -@@ -265,6 +311,9 @@ - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c4"; -+ clocks = <&func_96m_fclk>; -+ clock-names = "fck"; -+ status = "disabled"; - }; - - i2c5: i2c@4807c000 { -@@ -274,6 +323,9 @@ - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c5"; -+ clocks = <&func_96m_fclk>; -+ clock-names = "fck"; -+ status = "disabled"; - }; - - mcspi1: spi@48098000 { -@@ -283,6 +335,8 @@ - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi1"; -+ clocks = <&func_48m_fclk>; -+ clock-names = "fck"; - ti,spi-num-cs = <4>; - dmas = <&sdma 35>, - <&sdma 36>, -@@ -294,6 +348,7 @@ - <&sdma 42>; - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; -+ status = "disabled"; - }; - - mcspi2: spi@4809a000 { -@@ -303,12 +358,15 @@ - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi2"; -+ clocks = <&func_48m_fclk>; -+ clock-names = "fck"; - ti,spi-num-cs = <2>; - dmas = <&sdma 43>, - <&sdma 44>, - <&sdma 45>, - <&sdma 46>; - dma-names = "tx0", "rx0", "tx1", "rx1"; -+ status = "disabled"; - }; - - mcspi3: spi@480b8000 { -@@ -318,9 +376,12 @@ - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi3"; -+ clocks = <&func_48m_fclk>; -+ clock-names = "fck"; - ti,spi-num-cs = <2>; - dmas = <&sdma 15>, <&sdma 16>; - dma-names = "tx0", "rx0"; -+ status = "disabled"; - }; - - mcspi4: spi@480ba000 { -@@ -330,9 +391,12 @@ - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi4"; -+ clocks = <&func_48m_fclk>; -+ clock-names = "fck"; - ti,spi-num-cs = <1>; - dmas = <&sdma 70>, <&sdma 71>; - dma-names = "tx0", "rx0"; -+ status = "disabled"; - }; - - uart1: serial@4806a000 { -@@ -340,7 +404,10 @@ - reg = <0x4806a000 0x100>; - interrupts = ; - ti,hwmods = "uart1"; -+ clocks = <&func_48m_fclk>; -+ clock-names = "fck"; - clock-frequency = <48000000>; -+ status = "disabled"; - }; - - uart2: serial@4806c000 { -@@ -348,7 +415,10 @@ - reg = <0x4806c000 0x100>; - interrupts = ; - ti,hwmods = "uart2"; -+ clocks = <&func_48m_fclk>; -+ clock-names = "fck"; - clock-frequency = <48000000>; -+ status = "disabled"; - }; - - uart3: serial@48020000 { -@@ -356,7 +426,10 @@ - reg = <0x48020000 0x100>; - interrupts = ; - ti,hwmods = "uart3"; -+ clocks = <&func_48m_fclk>; -+ clock-names = "fck"; - clock-frequency = <48000000>; -+ status = "disabled"; - }; - - uart4: serial@4806e000 { -@@ -364,7 +437,10 @@ - reg = <0x4806e000 0x100>; - interrupts = ; - ti,hwmods = "uart4"; -+ clocks = <&func_48m_fclk>; -+ clock-names = "fck"; - clock-frequency = <48000000>; -+ status = "disabled"; - }; - - uart5: serial@48066000 { -@@ -372,7 +448,10 @@ - reg = <0x48066000 0x100>; - interrupts = ; - ti,hwmods = "uart5"; -+ clocks = <&func_48m_fclk>; -+ clock-names = "fck"; - clock-frequency = <48000000>; -+ status = "disabled"; - }; - - uart6: serial@48068000 { -@@ -380,7 +459,10 @@ - reg = <0x48068000 0x100>; - interrupts = ; - ti,hwmods = "uart6"; -+ clocks = <&func_48m_fclk>; -+ clock-names = "fck"; - clock-frequency = <48000000>; -+ status = "disabled"; - }; - - mmc1: mmc@4809c000 { -@@ -388,6 +470,8 @@ - reg = <0x4809c000 0x400>; - interrupts = ; - ti,hwmods = "mmc1"; -+ clocks = <&mmc1_fclk>, <&mmc1_32khz_clk>; -+ clock-names = "fck", "32khz_clk"; - ti,dual-volt; - ti,needs-special-reset; - dmas = <&sdma 61>, <&sdma 62>; -@@ -399,6 +483,8 @@ - reg = <0x480b4000 0x400>; - interrupts = ; - ti,hwmods = "mmc2"; -+ clocks = <&mmc2_fclk>; -+ clock-names = "fck"; - ti,needs-special-reset; - dmas = <&sdma 47>, <&sdma 48>; - dma-names = "tx", "rx"; -@@ -409,6 +495,8 @@ - reg = <0x480ad000 0x400>; - interrupts = ; - ti,hwmods = "mmc3"; -+ clocks = <&func_48m_fclk>; -+ clock-names = "fck"; - ti,needs-special-reset; - dmas = <&sdma 77>, <&sdma 78>; - dma-names = "tx", "rx"; -@@ -419,6 +507,8 @@ - reg = <0x480d1000 0x400>; - interrupts = ; - ti,hwmods = "mmc4"; -+ clocks = <&func_48m_fclk>; -+ clock-names = "fck"; - ti,needs-special-reset; - dmas = <&sdma 57>, <&sdma 58>; - dma-names = "tx", "rx"; -@@ -429,15 +519,63 @@ - reg = <0x480d5000 0x400>; - interrupts = ; - ti,hwmods = "mmc5"; -+ clocks = <&func_96m_fclk>; -+ clock-names = "fck"; - ti,needs-special-reset; - dmas = <&sdma 59>, <&sdma 60>; - dma-names = "tx", "rx"; - }; - -+ omap_control_sata: control-phy@4a002374 { -+ compatible = "ti,control-phy-pipe3"; -+ reg = <0x4a002374 0x4>; -+ reg-names = "power"; -+ clocks = <&sys_clkin>; -+ clock-names = "sysclk"; -+ }; -+ -+ ocp2scp@4a090000 { -+ compatible = "ti,omap-ocp2scp"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ ti,hwmods = "ocp2scp3"; -+ reg = <0x4a090000 0x1c>; /* ocp2scp3 */ -+ sata_phy: sata-phy@4A096000 { -+ compatible = "ti,phy-pipe3-sata"; -+ reg = <0x4A096000 0x80>, /* phy_rx */ -+ <0x4A096400 0x64>, /* phy_tx */ -+ <0x4A096800 0x40>; /* pll_ctrl */ -+ reg-names = "phy_rx", "phy_tx", "pll_ctrl"; -+ ctrl-module = <&omap_control_sata>; -+ #phy-cells = <0>; -+ clocks = <&sata_ref_clk>; -+ clock-names = "refclk"; -+ }; -+ }; -+ -+ sata@4a141100 { -+ compatible = "ti,sata"; -+ ti,hwmods = "sata"; -+ reg = <0x4a141100 0x100>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ sata@4a140000 { -+ compatible = "snps,dwc-ahci"; -+ reg = <0x4a140000 0x1100>; -+ interrupts = ; -+ phys = <&sata_phy>; -+ phy-names = "sata-phy"; -+ }; -+ }; -+ - keypad: keypad@4ae1c000 { - compatible = "ti,omap4-keypad"; - reg = <0x4ae1c000 0x400>; - ti,hwmods = "kbd"; -+ clocks = <&sys_32k_ck>; -+ clock-names = "fck"; - }; - - mcpdm: mcpdm@40132000 { -@@ -447,6 +585,8 @@ - reg-names = "mpu", "dma"; - interrupts = ; - ti,hwmods = "mcpdm"; -+ clocks = <&pad_clks_ck>; -+ clock-names = "fck"; - dmas = <&sdma 65>, - <&sdma 66>; - dma-names = "up_link", "dn_link"; -@@ -459,6 +599,8 @@ - reg-names = "mpu", "dma"; - interrupts = ; - ti,hwmods = "dmic"; -+ clocks = <&dmic_gfclk>; -+ clock-names = "fck"; - dmas = <&sdma 67>; - dma-names = "up_link"; - }; -@@ -472,6 +614,8 @@ - interrupt-names = "common"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp1"; -+ clocks = <&mcbsp1_gfclk>, <&pad_clks_ck>, <&mcbsp1_sync_mux_ck>; -+ clock-names = "fck", "pad_fck", "prcm_fck"; - dmas = <&sdma 33>, - <&sdma 34>; - dma-names = "tx", "rx"; -@@ -486,6 +630,8 @@ - interrupt-names = "common"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp2"; -+ clocks = <&mcbsp2_gfclk>, <&pad_clks_ck>, <&mcbsp2_sync_mux_ck>; -+ clock-names = "fck", "pad_fck", "prcm_fck"; - dmas = <&sdma 17>, - <&sdma 18>; - dma-names = "tx", "rx"; -@@ -500,16 +646,31 @@ - interrupt-names = "common"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp3"; -+ clocks = <&mcbsp3_gfclk>, <&pad_clks_ck>, <&mcbsp3_sync_mux_ck>; -+ clock-names = "fck", "pad_fck", "prcm_fck"; - dmas = <&sdma 19>, - <&sdma 20>; - dma-names = "tx", "rx"; - }; - -+ mailbox: mailbox@4a0f4000 { -+ compatible = "ti,omap4-mailbox"; -+ reg = <0x4a0f4000 0x200>; -+ interrupts = ; -+ ti,hwmods = "mailbox"; -+ ti,mbox-num-users = <3>; -+ ti,mbox-num-fifos = <8>; -+ ti,mbox-names = "mbox-ipu", "mbox-dsp"; -+ ti,mbox-data = <0 1 0 0>, <3 2 0 0>; -+ }; -+ - timer1: timer@4ae18000 { - compatible = "ti,omap5430-timer"; - reg = <0x4ae18000 0x80>; - interrupts = ; - ti,hwmods = "timer1"; -+ clocks = <&timer1_gfclk_mux>; -+ clock-names = "fck"; - ti,timer-alwon; - }; - -@@ -518,6 +679,8 @@ - reg = <0x48032000 0x80>; - interrupts = ; - ti,hwmods = "timer2"; -+ clocks = <&timer2_gfclk_mux>; -+ clock-names = "fck"; - }; - - timer3: timer@48034000 { -@@ -525,6 +688,8 @@ - reg = <0x48034000 0x80>; - interrupts = ; - ti,hwmods = "timer3"; -+ clocks = <&timer3_gfclk_mux>; -+ clock-names = "fck"; - }; - - timer4: timer@48036000 { -@@ -532,6 +697,8 @@ - reg = <0x48036000 0x80>; - interrupts = ; - ti,hwmods = "timer4"; -+ clocks = <&timer4_gfclk_mux>; -+ clock-names = "fck"; - }; - - timer5: timer@40138000 { -@@ -540,6 +707,8 @@ - <0x49038000 0x80>; - interrupts = ; - ti,hwmods = "timer5"; -+ clocks = <&timer5_gfclk_mux>; -+ clock-names = "fck"; - ti,timer-dsp; - ti,timer-pwm; - }; -@@ -550,6 +719,8 @@ - <0x4903a000 0x80>; - interrupts = ; - ti,hwmods = "timer6"; -+ clocks = <&timer6_gfclk_mux>; -+ clock-names = "fck"; - ti,timer-dsp; - ti,timer-pwm; - }; -@@ -560,6 +731,8 @@ - <0x4903c000 0x80>; - interrupts = ; - ti,hwmods = "timer7"; -+ clocks = <&timer7_gfclk_mux>; -+ clock-names = "fck"; - ti,timer-dsp; - }; - -@@ -569,6 +742,8 @@ - <0x4903e000 0x80>; - interrupts = ; - ti,hwmods = "timer8"; -+ clocks = <&timer8_gfclk_mux>; -+ clock-names = "fck"; - ti,timer-dsp; - ti,timer-pwm; - }; -@@ -578,6 +753,8 @@ - reg = <0x4803e000 0x80>; - interrupts = ; - ti,hwmods = "timer9"; -+ clocks = <&timer9_gfclk_mux>; -+ clock-names = "fck"; - ti,timer-pwm; - }; - -@@ -586,6 +763,8 @@ - reg = <0x48086000 0x80>; - interrupts = ; - ti,hwmods = "timer10"; -+ clocks = <&timer10_gfclk_mux>; -+ clock-names = "fck"; - ti,timer-pwm; - }; - -@@ -594,19 +773,33 @@ - reg = <0x48088000 0x80>; - interrupts = ; - ti,hwmods = "timer11"; -+ clocks = <&timer11_gfclk_mux>; -+ clock-names = "fck"; - ti,timer-pwm; - }; - - wdt2: wdt@4ae14000 { -- compatible = "ti,omap5-wdt", "ti,omap3-wdt"; -+ compatible = "ti,omap5-wdt", "ti,omap4-wdt"; - reg = <0x4ae14000 0x80>; - interrupts = ; - ti,hwmods = "wd_timer2"; -+ clocks = <&sys_32k_ck>; -+ clock-names = "fck"; -+ }; -+ -+ dmm: dmm@4e000000 { -+ compatible = "ti,omap5-dmm"; -+ reg = <0x4e000000 0x800>; -+ interrupts = <0 113 0x4>; -+ ti,hwmods = "dmm"; - }; - - emif1: emif@0x4c000000 { - compatible = "ti,emif-4d5"; - ti,hwmods = "emif1"; -+ ti,no-idle; -+ clocks = <&dpll_core_h11x2_ck>; -+ clock-names = "fck"; - phy-type = <2>; /* DDR PHY type: Intelli PHY */ - reg = <0x4c000000 0x400>; - interrupts = ; -@@ -618,6 +811,9 @@ - emif2: emif@0x4d000000 { - compatible = "ti,emif-4d5"; - ti,hwmods = "emif2"; -+ ti,no-idle; -+ clocks = <&dpll_core_h11x2_ck>; -+ clock-names = "fck"; - phy-type = <2>; /* DDR PHY type: Intelli PHY */ - reg = <0x4d000000 0x400>; - interrupts = ; -@@ -626,18 +822,25 @@ - hw-caps-temp-alert; - }; - -- omap_control_usb: omap-control-usb@4a002300 { -- compatible = "ti,omap-control-usb"; -- reg = <0x4a002300 0x4>, -- <0x4a002370 0x4>; -- reg-names = "control_dev_conf", "phy_power_usb"; -- ti,type = <2>; -+ omap_control_usb2phy: control-phy@4a002300 { -+ compatible = "ti,control-phy-usb2"; -+ reg = <0x4a002300 0x4>; -+ reg-names = "power"; -+ }; -+ -+ omap_control_usb3phy: control-phy@4a002370 { -+ compatible = "ti,control-phy-pipe3"; -+ reg = <0x4a002370 0x4>; -+ reg-names = "power"; - }; - -- omap_dwc3@4a020000 { -+ usb3: omap_dwc3@4a020000 { - compatible = "ti,dwc3"; - ti,hwmods = "usb_otg_ss"; -+ clocks = <&dpll_core_h13x2_ck>, <&usb_otg_ss_refclk960m>; -+ clock-names = "fck", "refclk960m"; - reg = <0x4a020000 0x10000>; -+ - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; -@@ -647,7 +850,10 @@ - compatible = "snps,dwc3"; - reg = <0x4a030000 0x10000>; - interrupts = ; -- usb-phy = <&usb2_phy>, <&usb3_phy>; -+ phys = <&usb2_phy>, <&usb3_phy>; -+ phy-names = "usb2-phy", "usb3-phy"; -+ maximum-speed = "super-speed"; -+ dr_mode = "peripheral"; - tx-fifo-resize; - }; - }; -@@ -662,16 +868,26 @@ - usb2_phy: usb2phy@4a084000 { - compatible = "ti,omap-usb2"; - reg = <0x4a084000 0x7c>; -- ctrl-module = <&omap_control_usb>; -+ ctrl-module = <&omap_control_usb2phy>; -+ clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>; -+ clock-names = "wkupclk", "refclk"; -+ #phy-cells = <0>; - }; - - usb3_phy: usb3phy@4a084400 { -- compatible = "ti,omap-usb3"; -+ compatible = "ti,phy-pipe3-usb3"; - reg = <0x4a084400 0x80>, - <0x4a084800 0x64>, - <0x4a084c00 0x40>; - reg-names = "phy_rx", "phy_tx", "pll_ctrl"; -- ctrl-module = <&omap_control_usb>; -+ ctrl-module = <&omap_control_usb3phy>; -+ clocks = <&usb_phy_cm_clk32k>, -+ <&usb_otg_ss_refclk960m>, -+ <&dpll_core_h13x2_ck>; -+ clock-names = "wkupclk", -+ "refclk", -+ "refclk2"; -+ #phy-cells = <0>; - }; - }; - -@@ -689,6 +905,8 @@ - #address-cells = <1>; - #size-cells = <1>; - ranges; -+ clocks = <&l3init_60m_fclk>; -+ clock-names = "init_60m_fclk"; - - usbhsohci: ohci@4a064800 { - compatible = "ti,ohci-omap3", "usb-ohci"; -@@ -713,5 +931,71 @@ - interrupts = ; - compatible = "ti,omap5430-bandgap"; - }; -+ -+ dss@58000000 { -+ compatible = "ti,omap4-dss", "simple-bus"; -+ reg = <0x58000000 0x80>; -+ ti,hwmods = "dss_core"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ dispc@58001000 { -+ compatible = "ti,omap4-dispc"; -+ reg = <0x58001000 0x1000>; -+ interrupts = <0 25 0x4>; -+ ti,hwmods = "dss_dispc"; -+ }; -+ -+ dpi: encoder@0 { -+ compatible = "ti,omap4-dpi"; -+ }; -+ -+ rfbi: encoder@58002000 { -+ compatible = "ti,omap4-rfbi"; -+ reg = <0x58002000 0x1000>; -+ ti,hwmods = "dss_rfbi"; -+ }; -+ -+ dsi1: encoder@58004000 { -+ compatible = "ti,omap4-dsi"; -+ reg = <0x58004000 0x200>; -+ interrupts = <0 53 0x4>; -+ ti,hwmods = "dss_dsi1"; -+ }; -+ -+ dsi2: encoder@58005000 { -+ compatible = "ti,omap4-dsi"; -+ reg = <0x58005000 0x200>; -+ interrupts = <0 84 0x4>; -+ ti,hwmods = "dss_dsi2"; -+ }; -+ -+ hdmi: encoder@58060000 { -+ compatible = "ti,omap5-hdmi"; -+ reg = <0x58040000 0x200>, -+ <0x58040200 0x100>, -+ <0x58040300 0x100>, -+ <0x58060000 0x19000>; -+ reg-names = "hdmi_wp", "hdmi_pllctrl", -+ "hdmi_txphy", "hdmi_core"; -+ interrupts = <0 101 0x4>; -+ ti,hwmods = "dss_hdmi"; -+ }; -+ }; -+ }; -+ -+ clocks { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ /include/ "omap54xx-clocks.dtsi" -+ }; -+ -+ clockdomains { -+ l3init_clkdm: l3init_clkdm { -+ compatible = "ti,clockdomain"; -+ clocks = <&dpll_usb_ck>; -+ }; - }; - }; ---- a/arch/arm/boot/dts/omap5-uevm.dts -+++ b/arch/arm/boot/dts/omap5-uevm.dts -@@ -27,45 +27,19 @@ - regulator-max-microvolt = <3000000>; - }; - -- /* HS USB Port 2 RESET */ -- hsusb2_reset: hsusb2_reset_reg { -- compatible = "regulator-fixed"; -- regulator-name = "hsusb2_reset"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; /* gpio3_80 HUB_NRESET */ -- startup-delay-us = <70000>; -- enable-active-high; -- }; -- - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { - compatible = "usb-nop-xceiv"; -- reset-supply = <&hsusb2_reset>; -- /** -- * FIXME -- * Put the right clock phandle here when available -- * clocks = <&auxclk1>; -- * clock-names = "main_clk"; -- */ -+ reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; /* gpio3_80 HUB_NRESET */ -+ clocks = <&auxclk1_ck>; -+ clock-names = "main_clk"; - clock-frequency = <19200000>; - }; - -- /* HS USB Port 3 RESET */ -- hsusb3_reset: hsusb3_reset_reg { -- compatible = "regulator-fixed"; -- regulator-name = "hsusb3_reset"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; /* gpio3_79 ETH_NRESET */ -- startup-delay-us = <70000>; -- enable-active-high; -- }; -- - /* HS USB Host PHY on PORT 3 */ - hsusb3_phy: hsusb3_phy { - compatible = "usb-nop-xceiv"; -- reset-supply = <&hsusb3_reset>; -+ reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; /* gpio3_79 ETH_NRESET */ - }; - - leds { -@@ -77,6 +51,28 @@ - default-state = "off"; - }; - }; -+ -+ sound: sound { -+ compatible = "ti,abe-twl6040"; -+ ti,model = "omap5-uevm"; -+ -+ ti,mclk-freq = <19200000>; -+ -+ ti,mcpdm = <&mcpdm>; -+ -+ ti,twl6040 = <&twl6040>; -+ -+ /* Audio routing */ -+ ti,audio-routing = -+ "Headset Stereophone", "HSOL", -+ "Headset Stereophone", "HSOR", -+ "Line Out", "AUXL", -+ "Line Out", "AUXR", -+ "HSMIC", "Headset Mic", -+ "Headset Mic", "Headset Mic Bias", -+ "AFML", "Line In", -+ "AFMR", "Line In"; -+ }; - }; - - &omap5_pmx_core { -@@ -84,16 +80,18 @@ - pinctrl-0 = < - &twl6040_pins - &mcpdm_pins -- &dmic_pins - &mcbsp1_pins - &mcbsp2_pins - &usbhost_pins - &led_gpio_pins -+ &dss_hdmi_pins -+ &tpd12s015_pins -+ &palmas_pins - >; - - twl6040_pins: pinmux_twl6040_pins { - pinctrl-single,pins = < -- 0x18a (PIN_OUTPUT | MUX_MODE6) /* perslimbus2_clock.gpio5_145 */ -+ 0x17e (PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */ - >; - }; - -@@ -107,15 +105,6 @@ - >; - }; - -- dmic_pins: pinmux_dmic_pins { -- pinctrl-single,pins = < -- 0x144 (PIN_INPUT | MUX_MODE0) /* abedmic_din1.abedmic_din1 */ -- 0x146 (PIN_INPUT | MUX_MODE0) /* abedmic_din2.abedmic_din2 */ -- 0x148 (PIN_INPUT | MUX_MODE0) /* abedmic_din3.abedmic_din3 */ -- 0x14a (PIN_OUTPUT | MUX_MODE0) /* abedmic_clk1.abedmic_clk1 */ -- >; -- }; -- - mcbsp1_pins: pinmux_mcbsp1_pins { - pinctrl-single,pins = < - 0x14c (PIN_INPUT | MUX_MODE1) /* abedmic_clk2.abemcbsp1_fsx */ -@@ -143,8 +132,14 @@ - - i2c5_pins: pinmux_i2c5_pins { - pinctrl-single,pins = < -- 0x184 (PIN_INPUT | MUX_MODE0) /* i2c5_scl */ -- 0x186 (PIN_INPUT | MUX_MODE0) /* i2c5_sda */ -+ 0x186 (PIN_INPUT | MUX_MODE0) /* i2c5_scl */ -+ 0x188 (PIN_INPUT | MUX_MODE0) /* i2c5_sda */ -+ >; -+ }; -+ -+ mmc1_pins: pinmux_mmc1_pins { -+ pinctrl-single,pins = < -+ 0x194 (PIN_INPUT | MUX_MODE6) /* gpio5_152 */ - >; - }; - -@@ -153,25 +148,25 @@ - 0xbc (PIN_INPUT | MUX_MODE0) /* mcspi2_clk */ - 0xbe (PIN_INPUT | MUX_MODE0) /* mcspi2_simo */ - 0xc0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi2_somi */ -- 0xc2 (PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs */ -+ 0xc2 (PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0 */ - >; - }; - - mcspi3_pins: pinmux_mcspi3_pins { - pinctrl-single,pins = < -- 0x78 (PIN_INPUT | MUX_MODE1) /* mcspi2_somi */ -- 0x7a (PIN_INPUT | MUX_MODE1) /* mcspi2_cs */ -- 0x7c (PIN_INPUT | MUX_MODE1) /* mcspi2_simo */ -- 0x7e (PIN_INPUT | MUX_MODE1) /* mcspi2_clk */ -+ 0x78 (PIN_INPUT | MUX_MODE1) /* mcspi3_somi */ -+ 0x7a (PIN_INPUT | MUX_MODE1) /* mcspi3_cs0 */ -+ 0x7c (PIN_INPUT | MUX_MODE1) /* mcspi3_simo */ -+ 0x7e (PIN_INPUT | MUX_MODE1) /* mcspi3_clk */ - >; - }; - - mcspi4_pins: pinmux_mcspi4_pins { - pinctrl-single,pins = < -- 0x164 (PIN_INPUT | MUX_MODE1) /* mcspi2_clk */ -- 0x168 (PIN_INPUT | MUX_MODE1) /* mcspi2_simo */ -- 0x16a (PIN_INPUT | MUX_MODE1) /* mcspi2_somi */ -- 0x16c (PIN_INPUT | MUX_MODE1) /* mcspi2_cs */ -+ 0x164 (PIN_INPUT | MUX_MODE1) /* mcspi4_clk */ -+ 0x168 (PIN_INPUT | MUX_MODE1) /* mcspi4_simo */ -+ 0x16a (PIN_INPUT | MUX_MODE1) /* mcspi4_somi */ -+ 0x16c (PIN_INPUT | MUX_MODE1) /* mcspi4_cs0 */ - >; - }; - -@@ -219,6 +214,25 @@ - >; - }; - -+ dss_hdmi_pins: pinmux_dss_hdmi_pins { -+ pinctrl-single,pins = < -+ 0x0fc (PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */ -+ 0x100 (PIN_INPUT | MUX_MODE0) /* DDC-SCL */ -+ 0x102 (PIN_INPUT | MUX_MODE0) /* DDC-SDA */ -+ >; -+ }; -+ -+ tpd12s015_pins: pinmux_tpd12s015_pins { -+ pinctrl-single,pins = < -+ 0x0fe (PIN_INPUT_PULLDOWN | MUX_MODE6) /* hdmi_hpd.gpio7_193 */ -+ >; -+ }; -+ -+ palmas_pins: pinmux_palmas_pins { -+ pinctrl-single,pins = < -+ 0x140 (PIN_INPUT_PULLUP | MUX_MODE1) /* MSECURE */ -+ >; -+ }; - }; - - &omap5_pmx_wkup { -@@ -235,8 +249,11 @@ - }; - - &mmc1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&ldo9_reg>; - bus-width = <4>; -+ cd-gpios = <&gpio5 24 0>; /* gpio 152 */ - }; - - &mmc2 { -@@ -259,6 +276,7 @@ - }; - - &i2c1 { -+ status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - -@@ -272,6 +290,30 @@ - interrupt-controller; - #interrupt-cells = <2>; - -+ extcon_usb3: palmas_usb { -+ compatible = "ti,palmas-usb-vid"; -+ ti,enable-vbus-detection; -+ ti,enable-id-detection; -+ ti,wakeup; -+ }; -+ -+ palmas_rtc: rtc { -+ compatible = "ti,palmas-rtc"; -+ interrupt-parent = <&palmas>; -+ interrupts = <8 IRQ_TYPE_NONE>; -+ ti,backup-battery-chargeable; -+ }; -+ -+ clk32kg: palmas_clk32k@0 { -+ compatible = "ti,palmas-clk32kg"; -+ #clock-cells = <0>; -+ }; -+ -+ clk32kgaudio: palmas_clk32k@1 { -+ compatible = "ti,palmas-clk32kgaudio"; -+ #clock-cells = <0>; -+ }; -+ - palmas_pmic { - compatible = "ti,palmas-pmic"; - interrupt-parent = <&palmas>; -@@ -334,15 +376,22 @@ - ti,smps-range = <0x80>; - }; - -- smps10_reg: smps10 { -+ smps10_out2_reg: smps10_out2 { - /* VBUS_5V_OTG */ -- regulator-name = "smps10"; -+ regulator-name = "smps10_out2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - -+ smps10_out1_reg: smps10_out1 { -+ /* VBUS_5V_OTG */ -+ regulator-name = "smps10_out1"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ - ldo1_reg: ldo1 { - /* VDDAPHY_CAM: vdda_csiport */ - regulator-name = "ldo1"; -@@ -448,13 +497,37 @@ - }; - }; - }; -+ -+ twl6040: twl@4b { -+ compatible = "ti,twl6040"; -+ reg = <0x4b>; -+ -+ interrupts = ; /* IRQ_SYS_2N cascaded to gic */ -+ interrupt-parent = <&gic>; -+ ti,audpwron-gpio = <&gpio5 13 0>; /* gpio line 141 */ -+ -+ vio-supply = <&smps7_reg>; -+ v2v1-supply = <&smps9_reg>; -+ enable-active-high; -+ -+ clocks = <&clk32kgaudio>; -+ clock-names = "clk32k"; -+ }; - }; - - &i2c5 { -+ status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins>; - - clock-frequency = <400000>; -+ -+ tca6424a: tca6424a@22 { -+ compatible = "ti,tca6424"; -+ reg = <0x22>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; - }; - - &mcbsp3 { -@@ -470,36 +543,91 @@ - phys = <0 &hsusb2_phy &hsusb3_phy>; - }; - --&mcspi1 { -+&usb3 { -+ extcon = <&extcon_usb3>; -+ vbus-supply = <&smps10_out1_reg>; -+}; - -+&mcspi1 { -+ status = "okay"; - }; - - &mcspi2 { -+ status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcspi2_pins>; - }; - - &mcspi3 { -+ status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcspi3_pins>; - }; - - &mcspi4 { -+ status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcspi4_pins>; - }; - - &uart1 { -+ status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - }; - - &uart3 { -+ status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - }; - - &uart5 { -+ status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart5_pins>; - }; -+ -+&hdmi { -+ vdda_hdmi_dac-supply = <&ldo4_reg>; -+}; -+ -+&dsi1 { -+ vdds_dsi-supply = <&ldo4_reg>; -+}; -+ -+&dsi2 { -+ vdds_dsi-supply = <&ldo4_reg>; -+}; -+ -+&cpu0 { -+ cpu0-supply = <&smps123_reg>; -+}; -+ -+/ { -+ aliases { -+ display0 = &hdmi0; -+ ethernet0 = &smsc0; -+ }; -+ -+ tpd12s015: encoder@0 { -+ compatible = "ti,tpd12s015"; -+ -+ video-source = <&hdmi>; -+ -+ gpios = <&tca6424a 0 0>, /* TCA6424A P01, CT CP HPD */ -+ <&tca6424a 1 0>, /* TCA6424A P00, LS OE */ -+ <&gpio7 1 0>; /* GPIO 193, HPD */ -+ }; -+ -+ hdmi0: connector@0 { -+ compatible = "ti,hdmi_connector"; -+ -+ video-source = <&tpd12s015>; -+ }; -+ -+ smsc0: smsc95xx@0 { -+ /* Filled in by U-Boot */ -+ mac-address = [ 00 00 00 00 00 00 ]; -+ }; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/tps65218.dtsi -@@ -0,0 +1,41 @@ -+/* -+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+&tps { -+ compatible = "ti,tps65218"; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ -+ dcdc1: regulator-dcdc1 { -+ compatible = "ti,tps65218-dcdc1"; -+ }; -+ -+ dcdc2: regulator-dcdc2 { -+ compatible = "ti,tps65218-dcdc2"; -+ }; -+ -+ dcdc3: regulator-dcdc3 { -+ compatible = "ti,tps65218-dcdc3"; -+ }; -+ -+ dcdc4: regulator-dcdc4 { -+ compatible = "ti,tps65218-dcdc4"; -+ }; -+ -+ dcdc5: regulator-dcdc5 { -+ compatible = "ti,tps65218-dcdc5"; -+ }; -+ -+ dcdc6: regulator-dcdc6 { -+ compatible = "ti,tps65218-dcdc6"; -+ }; -+ -+ ldo1: regulator-ldo1 { -+ compatible = "ti,tps65218-ldo1"; -+ }; -+}; ---- a/arch/arm/boot/dts/twl4030.dtsi -+++ b/arch/arm/boot/dts/twl4030.dtsi -@@ -86,6 +86,7 @@ - usb1v8-supply = <&vusb1v8>; - usb3v1-supply = <&vusb3v1>; - usb_mode = <1>; -+ #phy-cells = <0>; - }; - - twl_pwm: pwm { ---- a/arch/arm/boot/Makefile -+++ b/arch/arm/boot/Makefile -@@ -55,6 +55,9 @@ $(obj)/zImage: $(obj)/compressed/vmlinux - $(call if_changed,objcopy) - @$(kecho) ' Kernel: $@ is ready' - -+$(obj)/zImage-dtb.%: $(obj)/dts/%.dtb $(obj)/zImage -+ cat $(obj)/zImage $< > $@ -+ - endif - - ifneq ($(LOADADDR),) -@@ -80,6 +83,10 @@ $(obj)/uImage: $(obj)/zImage FORCE - $(call if_changed,uimage) - @$(kecho) ' Image $@ is ready' - -+$(obj)/uImage.%: $(obj)/zImage-dtb.% FORCE -+ $(call if_changed,uimage) -+ @echo ' Image $@ is ready' -+ - $(obj)/bootp/bootp: $(obj)/zImage initrd FORCE - $(Q)$(MAKE) $(build)=$(obj)/bootp $@ - @: ---- a/arch/arm/configs/omap2plus_defconfig -+++ b/arch/arm/configs/omap2plus_defconfig -@@ -26,11 +26,13 @@ CONFIG_ARCH_OMAP2=y - CONFIG_ARCH_OMAP3=y - CONFIG_ARCH_OMAP4=y - CONFIG_SOC_AM33XX=y -+CONFIG_SOC_AM43XX=y - CONFIG_OMAP_RESET_CLOCKS=y - CONFIG_OMAP_MUX_DEBUG=y - CONFIG_ARCH_VEXPRESS_CA9X4=y - CONFIG_ARM_THUMBEE=y - CONFIG_ARM_ERRATA_411920=y -+CONFIG_OMAP4_ERRATA_I688=y - CONFIG_NO_HZ=y - CONFIG_HIGH_RES_TIMERS=y - CONFIG_SMP=y -@@ -42,6 +44,14 @@ CONFIG_ARM_APPENDED_DTB=y - CONFIG_ARM_ATAG_DTB_COMPAT=y - CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyO2,115200" - CONFIG_KEXEC=y -+CONFIG_CPU_FREQ=y -+CONFIG_CPU_FREQ_STAT_DETAILS=y -+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -+CONFIG_CPU_FREQ_GOV_POWERSAVE=y -+CONFIG_CPU_FREQ_GOV_USERSPACE=y -+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -+CONFIG_GENERIC_CPUFREQ_CPU0=y -+# CONFIG_ARM_OMAP2PLUS_CPUFREQ is not set - CONFIG_FPE_NWFPE=y - CONFIG_BINFMT_MISC=y - CONFIG_PM_DEBUG=y -@@ -60,6 +70,7 @@ CONFIG_IP_PNP_RARP=y - # CONFIG_INET_LRO is not set - # CONFIG_IPV6 is not set - CONFIG_NETFILTER=y -+CONFIG_VLAN_8021Q=y - CONFIG_CAN=m - CONFIG_CAN_RAW=m - CONFIG_CAN_BCM=m -@@ -82,6 +93,7 @@ CONFIG_DMA_CMA=y - CONFIG_CONNECTOR=y - CONFIG_DEVTMPFS=y - CONFIG_DEVTMPFS_MOUNT=y -+CONFIG_OMAP_OCP2SCP=y - CONFIG_MTD=y - CONFIG_MTD_CMDLINE_PARTS=y - CONFIG_MTD_CHAR=y -@@ -89,8 +101,11 @@ CONFIG_MTD_BLOCK=y - CONFIG_MTD_OOPS=y - CONFIG_MTD_CFI=y - CONFIG_MTD_CFI_INTELEXT=y -+CONFIG_MTD_M25P80=y -+# CONFIG_M25PXX_USE_FAST_READ is not set - CONFIG_MTD_NAND=y - CONFIG_MTD_NAND_OMAP2=y -+CONFIG_MTD_NAND_OMAP_BCH=y - CONFIG_MTD_ONENAND=y - CONFIG_MTD_ONENAND_VERIFY_WRITE=y - CONFIG_MTD_ONENAND_OMAP2=y -@@ -106,6 +121,9 @@ CONFIG_SCSI=y - CONFIG_BLK_DEV_SD=y - CONFIG_SCSI_MULTI_LUN=y - CONFIG_SCSI_SCAN_ASYNC=y -+CONFIG_ATA=y -+CONFIG_SATA_AHCI_PLATFORM=y -+CONFIG_SATA_TI=y - CONFIG_MD=y - CONFIG_NETDEVICES=y - CONFIG_SMSC_PHY=y -@@ -131,6 +149,9 @@ CONFIG_KEYBOARD_MATRIX=m - CONFIG_KEYBOARD_TWL4030=y - CONFIG_INPUT_TOUCHSCREEN=y - CONFIG_TOUCHSCREEN_ADS7846=y -+CONFIG_TOUCHSCREEN_ATMEL_MXT=y -+CONFIG_TOUCHSCREEN_TI_AM335X_TSC=y -+CONFIG_TOUCHSCREEN_PIXCIR=m - CONFIG_INPUT_MISC=y - CONFIG_INPUT_TWL4030_PWRBUTTON=y - CONFIG_VT_HW_CONSOLE_BINDING=y -@@ -151,10 +172,14 @@ CONFIG_HW_RANDOM=y - CONFIG_I2C_CHARDEV=y - CONFIG_SPI=y - CONFIG_SPI_OMAP24XX=y -+CONFIG_SPI_TI_QSPI=y - CONFIG_PINCTRL_SINGLE=y - CONFIG_DEBUG_GPIO=y - CONFIG_GPIO_SYSFS=y - CONFIG_GPIO_TWL4030=y -+CONFIG_GPIOLIB=y -+CONFIG_I2C=y -+CONFIG_GPIO_PCF857X=y - CONFIG_W1=y - CONFIG_POWER_SUPPLY=y - CONFIG_SENSORS_LM75=m -@@ -168,31 +193,52 @@ CONFIG_THERMAL_GOV_USER_SPACE=y - CONFIG_CPU_THERMAL=y - CONFIG_OMAP_WATCHDOG=y - CONFIG_TWL4030_WATCHDOG=y -+CONFIG_MFD_TI_AM335X_TSCADC=y -+CONFIG_MFD_PALMAS=y - CONFIG_MFD_TPS65217=y - CONFIG_MFD_TPS65910=y - CONFIG_TWL6040_CORE=y - CONFIG_REGULATOR_TWL4030=y -+CONFIG_REGULATOR_TIAVSCLASS0=y - CONFIG_REGULATOR_TPS65023=y - CONFIG_REGULATOR_TPS6507X=y - CONFIG_REGULATOR_TPS65217=y - CONFIG_REGULATOR_TPS65910=y -+CONFIG_REGULATOR_PALMAS=y -+CONFIG_MEDIA_SUPPORT=m -+CONFIG_MEDIA_CAMERA_SUPPORT=y -+CONFIG_VIDEO_DEV=m -+CONFIG_VIDEO_V4L2=m -+CONFIG_VIDEOBUF2_CORE=m -+CONFIG_VIDEOBUF2_MEMOPS=m -+CONFIG_VIDEOBUF2_VMALLOC=m -+CONFIG_MEDIA_USB_SUPPORT=y -+CONFIG_USB_VIDEO_CLASS=m -+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y -+CONFIG_USB_GSPCA=m - CONFIG_FB=y - CONFIG_FIRMWARE_EDID=y - CONFIG_FB_MODE_HELPERS=y - CONFIG_FB_TILEBLITTING=y - CONFIG_FB_OMAP_LCD_VGA=y --CONFIG_OMAP2_DSS=m -+CONFIG_FB_DA8XX=y -+CONFIG_FB_DA8XX_TDA998X=y -+CONFIG_OMAP2_DSS=y - CONFIG_OMAP2_DSS_RFBI=y - CONFIG_OMAP2_DSS_SDI=y - CONFIG_OMAP2_DSS_DSI=y --CONFIG_FB_OMAP2=m --CONFIG_DISPLAY_ENCODER_TFP410=m --CONFIG_DISPLAY_ENCODER_TPD12S015=m --CONFIG_DISPLAY_CONNECTOR_DVI=m --CONFIG_DISPLAY_CONNECTOR_HDMI=m --CONFIG_DISPLAY_PANEL_DPI=m -+CONFIG_FB_OMAP2=y -+CONFIG_DISPLAY_ENCODER_TFP410=y -+CONFIG_DISPLAY_ENCODER_TPD12S015=y -+CONFIG_DISPLAY_DRA_EVM_ENCODER_TPD12S015=y -+CONFIG_DISPLAY_CONNECTOR_DVI=y -+CONFIG_DISPLAY_CONNECTOR_HDMI=y -+CONFIG_DISPLAY_PANEL_DPI=y -+CONFIG_DISPLAY_PANEL_TFCS9700=y - CONFIG_BACKLIGHT_LCD_SUPPORT=y - CONFIG_LCD_CLASS_DEVICE=y -+CONFIG_BACKLIGHT_CLASS_DEVICE=y -+CONFIG_BACKLIGHT_PWM=y - CONFIG_LCD_PLATFORM=y - CONFIG_DISPLAY_SUPPORT=y - CONFIG_FRAMEBUFFER_CONSOLE=y -@@ -210,25 +256,57 @@ CONFIG_SND_DEBUG=y - CONFIG_SND_USB_AUDIO=m - CONFIG_SND_SOC=m - CONFIG_SND_OMAP_SOC=m -+CONFIG_SND_AM33XX_SOC_EVM=m -+CONFIG_SND_DAVINCI_SOC=m - CONFIG_SND_OMAP_SOC_OMAP_TWL4030=m - CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=m - CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=m - CONFIG_USB=y --CONFIG_USB_DEBUG=y - CONFIG_USB_ANNOUNCE_NEW_DEVICES=y - CONFIG_USB_DEVICEFS=y - CONFIG_USB_MON=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_PLATFORM=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_MUSB_HDRC=y -+CONFIG_USB_MUSB_OMAP2PLUS=m -+CONFIG_USB_MUSB_DSPS=m - CONFIG_USB_WDM=y - CONFIG_USB_STORAGE=y - CONFIG_USB_LIBUSUAL=y - CONFIG_USB_TEST=y -+CONFIG_AM335X_PHY_USB=y -+CONFIG_TWL6030_USB=y - CONFIG_USB_PHY=y - CONFIG_NOP_USB_XCEIV=y -+ -+CONFIG_USB_DWC3=y -+CONFIG_USB_DWC3_OMAP=y -+ - CONFIG_USB_GADGET=y - CONFIG_USB_GADGET_DEBUG=y - CONFIG_USB_GADGET_DEBUG_FILES=y - CONFIG_USB_GADGET_DEBUG_FS=y - CONFIG_USB_ZERO=m -+CONFIG_USB_AUDIO=m -+CONFIG_USB_ETH=m -+CONFIG_USB_G_NCM=m -+CONFIG_USB_GADGETFS=m -+CONFIG_USB_FUNCTIONFS=m -+CONFIG_USB_FUNCTIONFS_ETH=y -+CONFIG_USB_FUNCTIONFS_RNDIS=y -+CONFIG_USB_FUNCTIONFS_GENERIC=y -+CONFIG_USB_MASS_STORAGE=m -+CONFIG_USB_G_SERIAL=m -+CONFIG_USB_MIDI_GADGET=m -+CONFIG_USB_G_PRINTER=m -+CONFIG_USB_CDC_COMPOSITE=m -+CONFIG_USB_G_ACM_MS=m -+CONFIG_USB_G_MULTI=m -+CONFIG_USB_G_MULTI_CDC=y -+CONFIG_USB_G_HID=m -+CONFIG_USB_G_DBGP=m -+CONFIG_USB_G_WEBCAM=m - CONFIG_MMC=y - CONFIG_MMC_UNSAFE_RESUME=y - CONFIG_SDIO_UART=y -@@ -249,14 +327,35 @@ CONFIG_RTC_CLASS=y - CONFIG_RTC_DRV_TWL92330=y - CONFIG_RTC_DRV_TWL4030=y - CONFIG_RTC_DRV_OMAP=y -+CONFIG_RTC_DRV_PALMAS=y - CONFIG_DMADEVICES=y - CONFIG_TI_EDMA=y - CONFIG_DMA_OMAP=y -+CONFIG_PWM=y -+CONFIG_COMMON_CLK_DEBUG=y -+CONFIG_PWM_TIECAP=m -+CONFIG_PWM_TIEHRPWM=m - CONFIG_TI_SOC_THERMAL=y - CONFIG_TI_THERMAL=y - CONFIG_OMAP4_THERMAL=y - CONFIG_OMAP5_THERMAL=y - CONFIG_DRA752_THERMAL=y -+ -+CONFIG_EXTCON=y -+CONFIG_EXTCON_PALMAS=y -+CONFIG_EXTCON_GPIO_USBVID=y -+ -+CONFIG_GENERIC_PHY=y -+CONFIG_OMAP_CONTROL_PHY=y -+CONFIG_IIO=m -+CONFIG_IIO_BUFFER=y -+CONFIG_IIO_BUFFER_CB=y -+CONFIG_IIO_KFIFO_BUF=m -+CONFIG_TI_AM335X_ADC=m -+CONFIG_OMAP_USB2=y -+CONFIG_OMAP_PIPE3=y -+CONFIG_TWL4030_USB=y -+ - CONFIG_EXT2_FS=y - CONFIG_EXT3_FS=y - # CONFIG_EXT3_FS_XATTR is not set -@@ -295,6 +394,10 @@ CONFIG_DEBUG_INFO=y - CONFIG_SECURITY=y - CONFIG_CRYPTO_MICHAEL_MIC=y - # CONFIG_CRYPTO_ANSI_CPRNG is not set -+CONFIG_CRYPTO_DEV_OMAP_SHAM=y -+CONFIG_CRYPTO_DEV_OMAP_AES=y -+CONFIG_CRYPTO_DEV_OMAP_DES=y -+CONFIG_CRYPTO_TEST=m - CONFIG_CRC_CCITT=y - CONFIG_CRC_T10DIF=y - CONFIG_CRC_ITU_T=y -@@ -306,3 +409,4 @@ CONFIG_TI_DAVINCI_CPDMA=y - CONFIG_TI_CPSW=y - CONFIG_AT803X_PHY=y - CONFIG_SOC_DRA7XX=y -+CONFIG_GPIO_PCA953X=y ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -873,10 +873,33 @@ config ARCH_OMAP1 - help - Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) - -+config ARCH_OMAP2PLUS -+ bool "TI OMAP2+" -+ depends on MMU -+ select ARCH_HAS_BANDGAP -+ select ARCH_HAS_CPUFREQ -+ select ARCH_HAS_HOLES_MEMORYMODEL -+ select ARCH_OMAP -+ select ARCH_REQUIRE_GPIOLIB -+ select CLKDEV_LOOKUP -+ select CLKSRC_MMIO -+ select GENERIC_CLOCKEVENTS -+ select GENERIC_IRQ_CHIP -+ select HAVE_CLK -+ select OMAP_DM_TIMER -+ select PINCTRL -+ select PROC_DEVICETREE if PROC_FS -+ select SOC_BUS -+ select SPARSE_IRQ -+ select TI_PRIV_EDMA -+ select USE_OF -+ select AUTO_ZRELADDR -+ help -+ SUpport for OMAP2, OMAP3, OMAP4 and OMAP5 -+ - endchoice - - menu "Multiple platform selection" -- depends on ARCH_MULTIPLATFORM - - comment "CPU Core family selection" - -@@ -1606,6 +1629,7 @@ config ARCH_NR_GPIO - default 352 if ARCH_VT8500 - default 288 if ARCH_SUNXI - default 264 if MACH_H4700 -+ default 192 if SOC_AM43XX - default 0 - help - Maximum number of GPIOs in the system. ---- a/arch/arm/Kconfig.debug -+++ b/arch/arm/Kconfig.debug -@@ -1077,7 +1077,7 @@ config DEBUG_UNCOMPRESS - - config UNCOMPRESS_INCLUDE - string -- default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM -+ default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM || ARCH_OMAP - default "mach/uncompress.h" - - config EARLY_PRINTK ---- a/arch/arm/kernel/head.S -+++ b/arch/arm/kernel/head.S -@@ -534,7 +534,8 @@ smp_on_up: - __do_fixup_smp_on_up: - cmp r4, r5 - movhs pc, lr -- ldmia r4!, {r0, r6} -+ ldmia r4!, {r0} -+ ldmia r4!, {r6} - ARM( str r6, [r0, r3] ) - THUMB( add r0, r0, r3 ) - #ifdef __ARMEB__ ---- a/arch/arm/mach-omap2/am33xx-restart.c -+++ b/arch/arm/mach-omap2/am33xx-restart.c -@@ -9,6 +9,7 @@ - #include - - #include "common.h" -+#include "prcm43xx.h" - #include "prm-regbits-33xx.h" - #include "prm33xx.h" - -@@ -33,3 +34,25 @@ void am33xx_restart(enum reboot_mode mod - (void)am33xx_prm_read_reg(AM33XX_PRM_DEVICE_MOD, - AM33XX_PRM_RSTCTRL_OFFSET); - } -+ -+/** -+ * am43xx_restart - trigger a software restart of the SoC -+ * @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c -+ * @cmd: passed fr-om the userspace program rebooting the system (if provided) -+ * -+ * Resets the SoC. For @cmd, see the 'reboot' syscall in -+ * kernel/sys.c. No return value. -+ */ -+void am43xx_restart(enum reboot_mode mode, const char *cmd) -+{ -+ /* TODO: Handle mode and cmd if necessary */ -+ -+ am33xx_prm_rmw_reg_bits(AM33XX_RST_GLOBAL_WARM_SW_MASK, -+ AM33XX_RST_GLOBAL_WARM_SW_MASK, -+ AM43XX_PRM_DEVICE_INST, -+ AM33XX_PRM_RSTCTRL_OFFSET); -+ -+ /* OCP barrier */ -+ (void)am33xx_prm_read_reg(AM43XX_PRM_DEVICE_INST, -+ AM33XX_PRM_RSTCTRL_OFFSET); -+} ---- a/arch/arm/mach-omap2/board-2430sdp.c -+++ b/arch/arm/mach-omap2/board-2430sdp.c -@@ -246,7 +246,7 @@ static void __init omap_2430sdp_init(voi - omap_hsmmc_init(mmc); - - omap_mux_init_signal("usb0hs_stp", OMAP_PULL_ENA | OMAP_PULL_UP); -- usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); -+ usb_bind_phy("musb-hdrc.0", 0, "twl4030_usb"); - usb_musb_init(NULL); - - board_smc91x_init(); ---- a/arch/arm/mach-omap2/board-3430sdp.c -+++ b/arch/arm/mach-omap2/board-3430sdp.c -@@ -607,7 +607,7 @@ static void __init omap_3430sdp_init(voi - omap_ads7846_init(1, gpio_pendown, 310, NULL); - omap_serial_init(); - omap_sdrc_init(hyb18m512160af6_sdrc_params, NULL); -- usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); -+ usb_bind_phy("musb-hdrc.0", 0, "twl4030_usb"); - usb_musb_init(NULL); - board_smc91x_init(); - board_flash_init(sdp_flash_partitions, chip_sel_3430, 0); ---- a/arch/arm/mach-omap2/board-cm-t35.c -+++ b/arch/arm/mach-omap2/board-cm-t35.c -@@ -725,7 +725,7 @@ static void __init cm_t3x_common_init(vo - cm_t35_init_display(); - omap_twl4030_audio_init("cm-t3x", NULL); - -- usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); -+ usb_bind_phy("musb-hdrc.0", 0, "twl4030_usb"); - usb_musb_init(NULL); - cm_t35_init_usbh(); - cm_t35_init_camera(); ---- a/arch/arm/mach-omap2/board-devkit8000.c -+++ b/arch/arm/mach-omap2/board-devkit8000.c -@@ -628,7 +628,7 @@ static void __init devkit8000_init(void) - - omap_ads7846_init(2, OMAP3_DEVKIT_TS_GPIO, 0, NULL); - -- usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); -+ usb_bind_phy("musb-hdrc.0", 0, "twl4030_usb"); - usb_musb_init(NULL); - usbhs_init(&usbhs_bdata); - board_nand_init(devkit8000_nand_partitions, ---- a/arch/arm/mach-omap2/board-flash.c -+++ b/arch/arm/mach-omap2/board-flash.c -@@ -142,7 +142,7 @@ __init board_nand_init(struct mtd_partit - board_nand_data.nr_parts = nr_parts; - board_nand_data.devsize = nand_type; - -- board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT; -+ board_nand_data.ecc_opt = OMAP_ECC_BCH8_CODE_HW; - gpmc_nand_init(&board_nand_data, gpmc_t); - } - #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */ ---- a/arch/arm/mach-omap2/board-generic.c -+++ b/arch/arm/mach-omap2/board-generic.c -@@ -15,13 +15,11 @@ - #include - #include - #include --#include - - #include - - #include "common.h" - #include "common-board-devices.h" --#include "dss-common.h" - - #if !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)) - #define intc_of_init NULL -@@ -36,40 +34,13 @@ static struct of_device_id omap_dt_match - { } - }; - --/* -- * Create alias for USB host PHY clock. -- * Remove this when clock phandle can be provided via DT -- */ --static void __init legacy_init_ehci_clk(char *clkname) --{ -- int ret; -- -- ret = clk_add_alias("main_clk", NULL, clkname, NULL); -- if (ret) { -- pr_err("%s:Failed to add main_clk alias to %s :%d\n", -- __func__, clkname, ret); -- } --} -- - static void __init omap_generic_init(void) - { - omap_sdrc_init(NULL, NULL); - - of_platform_populate(NULL, omap_dt_match_table, NULL, NULL); - -- /* -- * HACK: call display setup code for selected boards to enable omapdss. -- * This will be removed when omapdss supports DT. -- */ -- if (of_machine_is_compatible("ti,omap4-panda")) { -- omap4_panda_display_init_of(); -- legacy_init_ehci_clk("auxclk3_ck"); -- -- } -- else if (of_machine_is_compatible("ti,omap4-sdp")) -- omap_4430sdp_display_init_of(); -- else if (of_machine_is_compatible("ti,omap5-uevm")) -- legacy_init_ehci_clk("auxclk1_ck"); -+ omapdss_init_of(); - } - - #ifdef CONFIG_SOC_OMAP2420 -@@ -165,6 +136,24 @@ DT_MACHINE_START(OMAP3_GP_DT, "Generic O - .dt_compat = omap3_gp_boards_compat, - .restart = omap3xxx_restart, - MACHINE_END -+ -+static const char *omap3630_gp_boards_compat[] __initdata = { -+ "ti,omap3-beagle-xm", -+ NULL, -+}; -+ -+DT_MACHINE_START(OMAP3630_GP_DT, "Generic OMAP3630-GP (Flattened Device Tree)") -+ .reserve = omap_reserve, -+ .map_io = omap3_map_io, -+ .init_early = omap3630_init_early, -+ .init_irq = omap_intc_of_init, -+ .handle_irq = omap3_intc_handle_irq, -+ .init_machine = omap_generic_init, -+ .init_late = omap3_init_late, -+ .init_time = omap3_secure_sync32k_timer_init, -+ .dt_compat = omap3630_gp_boards_compat, -+ .restart = omap3xxx_restart, -+MACHINE_END - #endif - - #ifdef CONFIG_SOC_AM33XX -@@ -174,12 +163,14 @@ static const char *am33xx_boards_compat[ - }; - - DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)") -- .reserve = omap_reserve, -+ .reserve = am33xx_reserve, - .map_io = am33xx_map_io, - .init_early = am33xx_init_early, -+ .init_late = am33xx_init_late, - .init_irq = omap_intc_of_init, - .handle_irq = omap3_intc_handle_irq, - .init_machine = omap_generic_init, -+ .init_late = am33xx_init_late, - .init_time = omap3_gptimer_timer_init, - .dt_compat = am33xx_boards_compat, - .restart = am33xx_restart, -@@ -219,6 +210,7 @@ DT_MACHINE_START(OMAP5_DT, "Generic OMAP - .init_early = omap5_init_early, - .init_irq = omap_gic_of_init, - .init_machine = omap_generic_init, -+ .init_late = omap5_init_late, - .init_time = omap5_realtime_timer_init, - .dt_compat = omap5_boards_compat, - .restart = omap44xx_restart, -@@ -232,12 +224,14 @@ static const char *am43_boards_compat[] - }; - - DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)") -+ .reserve = am33xx_reserve, - .map_io = am33xx_map_io, - .init_early = am43xx_init_early, - .init_irq = omap_gic_of_init, - .init_machine = omap_generic_init, - .init_time = omap3_sync32k_timer_init, - .dt_compat = am43_boards_compat, -+ .restart = am43xx_restart, - MACHINE_END - #endif - -@@ -254,6 +248,7 @@ DT_MACHINE_START(DRA7XX_DT, "Generic DRA - .init_early = dra7xx_init_early, - .init_irq = omap_gic_of_init, - .init_machine = omap_generic_init, -+ .init_late = dra7xx_init_late, - .init_time = omap5_realtime_timer_init, - .dt_compat = dra7xx_boards_compat, - .restart = omap44xx_restart, ---- a/arch/arm/mach-omap2/board-igep0020.c -+++ b/arch/arm/mach-omap2/board-igep0020.c -@@ -667,7 +667,7 @@ static void __init igep_init(void) - omap_serial_init(); - omap_sdrc_init(m65kxxxxam_sdrc_params, - m65kxxxxam_sdrc_params); -- usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); -+ usb_bind_phy("musb-hdrc.0", 0, "twl4030_usb"); - usb_musb_init(NULL); - - igep_flash_init(); ---- a/arch/arm/mach-omap2/board-ldp.c -+++ b/arch/arm/mach-omap2/board-ldp.c -@@ -403,7 +403,7 @@ static void __init omap_ldp_init(void) - omap_ads7846_init(1, 54, 310, NULL); - omap_serial_init(); - omap_sdrc_init(NULL, NULL); -- usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); -+ usb_bind_phy("musb-hdrc.0", 0, "twl4030_usb"); - usb_musb_init(NULL); - board_nand_init(ldp_nand_partitions, ARRAY_SIZE(ldp_nand_partitions), - ZOOM_NAND_CS, 0, nand_default_timings); ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -289,18 +289,12 @@ static struct regulator_consumer_supply - - static struct gpio_led gpio_leds[]; - --/* PHY's VCC regulator might be added later, so flag that we need it */ --static struct usb_phy_gen_xceiv_platform_data hsusb2_phy_data = { -- .needs_vcc = true, --}; -- - static struct usbhs_phy_data phy_data[] = { - { - .port = 2, - .reset_gpio = 147, - .vcc_gpio = -1, /* updated in beagle_twl_gpio_setup */ - .vcc_polarity = 1, /* updated in beagle_twl_gpio_setup */ -- .platform_data = &hsusb2_phy_data, - }, - }; - -@@ -567,7 +561,7 @@ static void __init omap3_beagle_init(voi - omap_sdrc_init(mt46h32m32lf6_sdrc_params, - mt46h32m32lf6_sdrc_params); - -- usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); -+ usb_bind_phy("musb-hdrc.0", 0, "twl4030_usb"); - usb_musb_init(NULL); - - usbhs_init(&usbhs_bdata); ---- a/arch/arm/mach-omap2/board-omap3evm.c -+++ b/arch/arm/mach-omap2/board-omap3evm.c -@@ -723,7 +723,7 @@ static void __init omap3_evm_init(void) - omap_mux_init_gpio(135, OMAP_PIN_OUTPUT); - phy_data[0].reset_gpio = 135; - } -- usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); -+ usb_bind_phy("musb-hdrc.0", 0, "twl4030_usb"); - usb_musb_init(&musb_board_data); - - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); ---- a/arch/arm/mach-omap2/board-omap3logic.c -+++ b/arch/arm/mach-omap2/board-omap3logic.c -@@ -216,7 +216,7 @@ static void __init omap3logic_init(void) - board_mmc_init(); - board_smsc911x_init(); - -- usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); -+ usb_bind_phy("musb-hdrc.0", 0, "twl4030_usb"); - usb_musb_init(NULL); - - /* Ensure SDRC pins are mux'd for self-refresh */ ---- a/arch/arm/mach-omap2/board-omap3pandora.c -+++ b/arch/arm/mach-omap2/board-omap3pandora.c -@@ -607,7 +607,7 @@ static void __init omap3pandora_init(voi - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); - usbhs_init(&usbhs_bdata); - -- usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); -+ usb_bind_phy("musb-hdrc.0", 0, "twl4030_usb"); - usb_musb_init(NULL); - gpmc_nand_init(&pandora_nand_data, NULL); - ---- a/arch/arm/mach-omap2/board-omap3stalker.c -+++ b/arch/arm/mach-omap2/board-omap3stalker.c -@@ -407,7 +407,7 @@ static void __init omap3_stalker_init(vo - - omap_serial_init(); - omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL); -- usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); -+ usb_bind_phy("musb-hdrc.0", 0, "twl4030_usb"); - usb_musb_init(NULL); - - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); ---- a/arch/arm/mach-omap2/board-omap3touchbook.c -+++ b/arch/arm/mach-omap2/board-omap3touchbook.c -@@ -367,7 +367,7 @@ static void __init omap3_touchbook_init( - - /* Touchscreen and accelerometer */ - omap_ads7846_init(4, OMAP3_TS_GPIO, 310, &ads7846_pdata); -- usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); -+ usb_bind_phy("musb-hdrc.0", 0, "twl4030_usb"); - usb_musb_init(NULL); - - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); ---- a/arch/arm/mach-omap2/board-overo.c -+++ b/arch/arm/mach-omap2/board-overo.c -@@ -511,7 +511,7 @@ static void __init overo_init(void) - mt46h32m32lf6_sdrc_params); - board_nand_init(overo_nand_partitions, - ARRAY_SIZE(overo_nand_partitions), NAND_CS, 0, NULL); -- usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); -+ usb_bind_phy("musb-hdrc.0", 0, "twl4030_usb"); - usb_musb_init(NULL); - - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); ---- a/arch/arm/mach-omap2/board-rm680.c -+++ b/arch/arm/mach-omap2/board-rm680.c -@@ -135,7 +135,7 @@ static void __init rm680_init(void) - sdrc_params = nokia_get_sdram_timings(); - omap_sdrc_init(sdrc_params, sdrc_params); - -- usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); -+ usb_bind_phy("musb-hdrc.0", 0, "twl4030_usb"); - usb_musb_init(NULL); - rm680_peripherals_init(); - } ---- a/arch/arm/mach-omap2/board-rx51.c -+++ b/arch/arm/mach-omap2/board-rx51.c -@@ -99,7 +99,7 @@ static void __init rx51_init(void) - sdrc_params = nokia_get_sdram_timings(); - omap_sdrc_init(sdrc_params, sdrc_params); - -- usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); -+ usb_bind_phy("musb-hdrc.0", 0, "twl4030_usb"); - usb_musb_init(&musb_board_data); - rx51_peripherals_init(); - ---- a/arch/arm/mach-omap2/board-zoom-peripherals.c -+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c -@@ -353,7 +353,7 @@ void __init zoom_peripherals_init(void) - omap_i2c_init(); - pwm_add_table(zoom_pwm_lookup, ARRAY_SIZE(zoom_pwm_lookup)); - platform_add_devices(zoom_devices, ARRAY_SIZE(zoom_devices)); -- usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); -+ usb_bind_phy("musb-hdrc.0", 0, "twl4030_usb"); - usb_musb_init(NULL); - enable_board_wakeup_source(); - omap_serial_init(); ---- a/arch/arm/mach-omap2/cclock33xx_data.c -+++ /dev/null -@@ -1,1064 +0,0 @@ --/* -- * AM33XX Clock data -- * -- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ -- * Vaibhav Hiremath -- * -- * This program is free software; you can redistribute it and/or -- * modify it under the terms of the GNU General Public License as -- * published by the Free Software Foundation version 2. -- * -- * This program is distributed "as is" WITHOUT ANY WARRANTY of any -- * kind, whether express or implied; without even the implied warranty -- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- */ -- --#include --#include --#include --#include --#include -- --#include "am33xx.h" --#include "soc.h" --#include "iomap.h" --#include "clock.h" --#include "control.h" --#include "cm.h" --#include "cm33xx.h" --#include "cm-regbits-33xx.h" --#include "prm.h" -- --/* Modulemode control */ --#define AM33XX_MODULEMODE_HWCTRL_SHIFT 0 --#define AM33XX_MODULEMODE_SWCTRL_SHIFT 1 -- --/*LIST_HEAD(clocks);*/ -- --/* Root clocks */ -- --/* RTC 32k */ --DEFINE_CLK_FIXED_RATE(clk_32768_ck, CLK_IS_ROOT, 32768, 0x0); -- --/* On-Chip 32KHz RC OSC */ --DEFINE_CLK_FIXED_RATE(clk_rc32k_ck, CLK_IS_ROOT, 32000, 0x0); -- --/* Crystal input clks */ --DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0); -- --DEFINE_CLK_FIXED_RATE(virt_24000000_ck, CLK_IS_ROOT, 24000000, 0x0); -- --DEFINE_CLK_FIXED_RATE(virt_25000000_ck, CLK_IS_ROOT, 25000000, 0x0); -- --DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0); -- --/* Oscillator clock */ --/* 19.2, 24, 25 or 26 MHz */ --static const char *sys_clkin_ck_parents[] = { -- "virt_19200000_ck", "virt_24000000_ck", "virt_25000000_ck", -- "virt_26000000_ck", --}; -- --/* -- * sys_clk in: input to the dpll and also used as funtional clock for, -- * adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse -- * -- */ --DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0, -- AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS), -- AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT, -- AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH, -- 0, NULL); -- --/* External clock - 12 MHz */ --DEFINE_CLK_FIXED_RATE(tclkin_ck, CLK_IS_ROOT, 12000000, 0x0); -- --/* Module clocks and DPLL outputs */ -- --/* DPLL_CORE */ --static struct dpll_data dpll_core_dd = { -- .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_CORE, -- .clk_bypass = &sys_clkin_ck, -- .clk_ref = &sys_clkin_ck, -- .control_reg = AM33XX_CM_CLKMODE_DPLL_CORE, -- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), -- .idlest_reg = AM33XX_CM_IDLEST_DPLL_CORE, -- .mult_mask = AM33XX_DPLL_MULT_MASK, -- .div1_mask = AM33XX_DPLL_DIV_MASK, -- .enable_mask = AM33XX_DPLL_EN_MASK, -- .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, -- .max_multiplier = 2047, -- .max_divider = 128, -- .min_divider = 1, --}; -- --/* CLKDCOLDO output */ --static const char *dpll_core_ck_parents[] = { -- "sys_clkin_ck", --}; -- --static struct clk dpll_core_ck; -- --static const struct clk_ops dpll_core_ck_ops = { -- .recalc_rate = &omap3_dpll_recalc, -- .get_parent = &omap2_init_dpll_parent, --}; -- --static struct clk_hw_omap dpll_core_ck_hw = { -- .hw = { -- .clk = &dpll_core_ck, -- }, -- .dpll_data = &dpll_core_dd, -- .ops = &clkhwops_omap3_dpll, --}; -- --DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops); -- --static const char *dpll_core_x2_ck_parents[] = { -- "dpll_core_ck", --}; -- --static struct clk dpll_core_x2_ck; -- --static const struct clk_ops dpll_x2_ck_ops = { -- .recalc_rate = &omap3_clkoutx2_recalc, --}; -- --static struct clk_hw_omap dpll_core_x2_ck_hw = { -- .hw = { -- .clk = &dpll_core_x2_ck, -- }, -- .flags = CLOCK_CLKOUTX2, --}; -- --DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_x2_ck_ops); -- --DEFINE_CLK_DIVIDER(dpll_core_m4_ck, "dpll_core_x2_ck", &dpll_core_x2_ck, -- 0x0, AM33XX_CM_DIV_M4_DPLL_CORE, -- AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT, -- AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, -- NULL); -- --DEFINE_CLK_DIVIDER(dpll_core_m5_ck, "dpll_core_x2_ck", &dpll_core_x2_ck, -- 0x0, AM33XX_CM_DIV_M5_DPLL_CORE, -- AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT, -- AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH, -- CLK_DIVIDER_ONE_BASED, NULL); -- --DEFINE_CLK_DIVIDER(dpll_core_m6_ck, "dpll_core_x2_ck", &dpll_core_x2_ck, -- 0x0, AM33XX_CM_DIV_M6_DPLL_CORE, -- AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT, -- AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH, -- CLK_DIVIDER_ONE_BASED, NULL); -- -- --/* DPLL_MPU */ --static struct dpll_data dpll_mpu_dd = { -- .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_MPU, -- .clk_bypass = &sys_clkin_ck, -- .clk_ref = &sys_clkin_ck, -- .control_reg = AM33XX_CM_CLKMODE_DPLL_MPU, -- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), -- .idlest_reg = AM33XX_CM_IDLEST_DPLL_MPU, -- .mult_mask = AM33XX_DPLL_MULT_MASK, -- .div1_mask = AM33XX_DPLL_DIV_MASK, -- .enable_mask = AM33XX_DPLL_EN_MASK, -- .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, -- .max_multiplier = 2047, -- .max_divider = 128, -- .min_divider = 1, --}; -- --/* CLKOUT: fdpll/M2 */ --static struct clk dpll_mpu_ck; -- --static const struct clk_ops dpll_mpu_ck_ops = { -- .enable = &omap3_noncore_dpll_enable, -- .disable = &omap3_noncore_dpll_disable, -- .recalc_rate = &omap3_dpll_recalc, -- .round_rate = &omap2_dpll_round_rate, -- .set_rate = &omap3_noncore_dpll_set_rate, -- .get_parent = &omap2_init_dpll_parent, --}; -- --static struct clk_hw_omap dpll_mpu_ck_hw = { -- .hw = { -- .clk = &dpll_mpu_ck, -- }, -- .dpll_data = &dpll_mpu_dd, -- .ops = &clkhwops_omap3_dpll, --}; -- --DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_mpu_ck_ops); -- --/* -- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2 -- * and ALT_CLK1/2) -- */ --DEFINE_CLK_DIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, -- 0x0, AM33XX_CM_DIV_M2_DPLL_MPU, AM33XX_DPLL_CLKOUT_DIV_SHIFT, -- AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -- --/* DPLL_DDR */ --static struct dpll_data dpll_ddr_dd = { -- .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DDR, -- .clk_bypass = &sys_clkin_ck, -- .clk_ref = &sys_clkin_ck, -- .control_reg = AM33XX_CM_CLKMODE_DPLL_DDR, -- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), -- .idlest_reg = AM33XX_CM_IDLEST_DPLL_DDR, -- .mult_mask = AM33XX_DPLL_MULT_MASK, -- .div1_mask = AM33XX_DPLL_DIV_MASK, -- .enable_mask = AM33XX_DPLL_EN_MASK, -- .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, -- .max_multiplier = 2047, -- .max_divider = 128, -- .min_divider = 1, --}; -- --/* CLKOUT: fdpll/M2 */ --static struct clk dpll_ddr_ck; -- --static const struct clk_ops dpll_ddr_ck_ops = { -- .recalc_rate = &omap3_dpll_recalc, -- .get_parent = &omap2_init_dpll_parent, -- .round_rate = &omap2_dpll_round_rate, -- .set_rate = &omap3_noncore_dpll_set_rate, --}; -- --static struct clk_hw_omap dpll_ddr_ck_hw = { -- .hw = { -- .clk = &dpll_ddr_ck, -- }, -- .dpll_data = &dpll_ddr_dd, -- .ops = &clkhwops_omap3_dpll, --}; -- --DEFINE_STRUCT_CLK(dpll_ddr_ck, dpll_core_ck_parents, dpll_ddr_ck_ops); -- --/* -- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2 -- * and ALT_CLK1/2) -- */ --DEFINE_CLK_DIVIDER(dpll_ddr_m2_ck, "dpll_ddr_ck", &dpll_ddr_ck, -- 0x0, AM33XX_CM_DIV_M2_DPLL_DDR, -- AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH, -- CLK_DIVIDER_ONE_BASED, NULL); -- --/* emif_fck functional clock */ --DEFINE_CLK_FIXED_FACTOR(dpll_ddr_m2_div2_ck, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, -- 0x0, 1, 2); -- --/* DPLL_DISP */ --static struct dpll_data dpll_disp_dd = { -- .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DISP, -- .clk_bypass = &sys_clkin_ck, -- .clk_ref = &sys_clkin_ck, -- .control_reg = AM33XX_CM_CLKMODE_DPLL_DISP, -- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), -- .idlest_reg = AM33XX_CM_IDLEST_DPLL_DISP, -- .mult_mask = AM33XX_DPLL_MULT_MASK, -- .div1_mask = AM33XX_DPLL_DIV_MASK, -- .enable_mask = AM33XX_DPLL_EN_MASK, -- .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, -- .max_multiplier = 2047, -- .max_divider = 128, -- .min_divider = 1, --}; -- --/* CLKOUT: fdpll/M2 */ --static struct clk dpll_disp_ck; -- --static struct clk_hw_omap dpll_disp_ck_hw = { -- .hw = { -- .clk = &dpll_disp_ck, -- }, -- .dpll_data = &dpll_disp_dd, -- .ops = &clkhwops_omap3_dpll, --}; -- --DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops); -- --/* -- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2 -- * and ALT_CLK1/2) -- */ --DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck, -- CLK_SET_RATE_PARENT, AM33XX_CM_DIV_M2_DPLL_DISP, -- AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH, -- CLK_DIVIDER_ONE_BASED, NULL); -- --/* DPLL_PER */ --static struct dpll_data dpll_per_dd = { -- .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_PERIPH, -- .clk_bypass = &sys_clkin_ck, -- .clk_ref = &sys_clkin_ck, -- .control_reg = AM33XX_CM_CLKMODE_DPLL_PER, -- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), -- .idlest_reg = AM33XX_CM_IDLEST_DPLL_PER, -- .mult_mask = AM33XX_DPLL_MULT_PERIPH_MASK, -- .div1_mask = AM33XX_DPLL_PER_DIV_MASK, -- .enable_mask = AM33XX_DPLL_EN_MASK, -- .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, -- .max_multiplier = 2047, -- .max_divider = 128, -- .min_divider = 1, -- .flags = DPLL_J_TYPE, --}; -- --/* CLKDCOLDO */ --static struct clk dpll_per_ck; -- --static struct clk_hw_omap dpll_per_ck_hw = { -- .hw = { -- .clk = &dpll_per_ck, -- }, -- .dpll_data = &dpll_per_dd, -- .ops = &clkhwops_omap3_dpll, --}; -- --DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_ddr_ck_ops); -- --/* CLKOUT: fdpll/M2 */ --DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0, -- AM33XX_CM_DIV_M2_DPLL_PER, AM33XX_DPLL_CLKOUT_DIV_SHIFT, -- AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, -- NULL); -- --DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_wkupdm_ck, "dpll_per_m2_ck", -- &dpll_per_m2_ck, 0x0, 1, 4); -- --DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_ck, "dpll_per_m2_ck", -- &dpll_per_m2_ck, 0x0, 1, 4); -- --DEFINE_CLK_FIXED_FACTOR(dpll_core_m4_div2_ck, "dpll_core_m4_ck", -- &dpll_core_m4_ck, 0x0, 1, 2); -- --DEFINE_CLK_FIXED_FACTOR(l4_rtc_gclk, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0, -- 1, 2); -- --DEFINE_CLK_FIXED_FACTOR(clk_24mhz, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, -- 8); -- --/* -- * Below clock nodes describes clockdomains derived out -- * of core clock. -- */ --static const struct clk_ops clk_ops_null = { --}; -- --static const char *l3_gclk_parents[] = { -- "dpll_core_m4_ck" --}; -- --static struct clk l3_gclk; --DEFINE_STRUCT_CLK_HW_OMAP(l3_gclk, NULL); --DEFINE_STRUCT_CLK(l3_gclk, l3_gclk_parents, clk_ops_null); -- --static struct clk l4hs_gclk; --DEFINE_STRUCT_CLK_HW_OMAP(l4hs_gclk, NULL); --DEFINE_STRUCT_CLK(l4hs_gclk, l3_gclk_parents, clk_ops_null); -- --static const char *l3s_gclk_parents[] = { -- "dpll_core_m4_div2_ck" --}; -- --static struct clk l3s_gclk; --DEFINE_STRUCT_CLK_HW_OMAP(l3s_gclk, NULL); --DEFINE_STRUCT_CLK(l3s_gclk, l3s_gclk_parents, clk_ops_null); -- --static struct clk l4fw_gclk; --DEFINE_STRUCT_CLK_HW_OMAP(l4fw_gclk, NULL); --DEFINE_STRUCT_CLK(l4fw_gclk, l3s_gclk_parents, clk_ops_null); -- --static struct clk l4ls_gclk; --DEFINE_STRUCT_CLK_HW_OMAP(l4ls_gclk, NULL); --DEFINE_STRUCT_CLK(l4ls_gclk, l3s_gclk_parents, clk_ops_null); -- --static struct clk sysclk_div_ck; --DEFINE_STRUCT_CLK_HW_OMAP(sysclk_div_ck, NULL); --DEFINE_STRUCT_CLK(sysclk_div_ck, l3_gclk_parents, clk_ops_null); -- --/* -- * In order to match the clock domain with hwmod clockdomain entry, -- * separate clock nodes is required for the modules which are -- * directly getting their funtioncal clock from sys_clkin. -- */ --static struct clk adc_tsc_fck; --DEFINE_STRUCT_CLK_HW_OMAP(adc_tsc_fck, NULL); --DEFINE_STRUCT_CLK(adc_tsc_fck, dpll_core_ck_parents, clk_ops_null); -- --static struct clk dcan0_fck; --DEFINE_STRUCT_CLK_HW_OMAP(dcan0_fck, NULL); --DEFINE_STRUCT_CLK(dcan0_fck, dpll_core_ck_parents, clk_ops_null); -- --static struct clk dcan1_fck; --DEFINE_STRUCT_CLK_HW_OMAP(dcan1_fck, NULL); --DEFINE_STRUCT_CLK(dcan1_fck, dpll_core_ck_parents, clk_ops_null); -- --static struct clk mcasp0_fck; --DEFINE_STRUCT_CLK_HW_OMAP(mcasp0_fck, NULL); --DEFINE_STRUCT_CLK(mcasp0_fck, dpll_core_ck_parents, clk_ops_null); -- --static struct clk mcasp1_fck; --DEFINE_STRUCT_CLK_HW_OMAP(mcasp1_fck, NULL); --DEFINE_STRUCT_CLK(mcasp1_fck, dpll_core_ck_parents, clk_ops_null); -- --static struct clk smartreflex0_fck; --DEFINE_STRUCT_CLK_HW_OMAP(smartreflex0_fck, NULL); --DEFINE_STRUCT_CLK(smartreflex0_fck, dpll_core_ck_parents, clk_ops_null); -- --static struct clk smartreflex1_fck; --DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL); --DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null); -- --static struct clk sha0_fck; --DEFINE_STRUCT_CLK_HW_OMAP(sha0_fck, NULL); --DEFINE_STRUCT_CLK(sha0_fck, dpll_core_ck_parents, clk_ops_null); -- --static struct clk aes0_fck; --DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL); --DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null); -- --static struct clk rng_fck; --DEFINE_STRUCT_CLK_HW_OMAP(rng_fck, NULL); --DEFINE_STRUCT_CLK(rng_fck, dpll_core_ck_parents, clk_ops_null); -- --/* -- * Modules clock nodes -- * -- * The following clock leaf nodes are added for the moment because: -- * -- * - hwmod data is not present for these modules, either hwmod -- * control is not required or its not populated. -- * - Driver code is not yet migrated to use hwmod/runtime pm -- * - Modules outside kernel access (to disable them by default) -- * -- * - mmu (gfx domain) -- * - cefuse -- * - usbotg_fck (its additional clock and not really a modulemode) -- * - ieee5000 -- */ -- --DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0, -- AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT, -- 0x0, NULL); -- --DEFINE_CLK_GATE(cefuse_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0, -- AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT, -- 0x0, NULL); -- --/* -- * clkdiv32 is generated from fixed division of 732.4219 -- */ --DEFINE_CLK_FIXED_FACTOR(clkdiv32k_ck, "clk_24mhz", &clk_24mhz, 0x0, 1, 732); -- --static struct clk clkdiv32k_ick; -- --static const char *clkdiv32k_ick_parent_names[] = { -- "clkdiv32k_ck", --}; -- --static const struct clk_ops clkdiv32k_ick_ops = { -- .enable = &omap2_dflt_clk_enable, -- .disable = &omap2_dflt_clk_disable, -- .is_enabled = &omap2_dflt_clk_is_enabled, -- .init = &omap2_init_clk_clkdm, --}; -- --static struct clk_hw_omap clkdiv32k_ick_hw = { -- .hw = { -- .clk = &clkdiv32k_ick, -- }, -- .enable_reg = AM33XX_CM_PER_CLKDIV32K_CLKCTRL, -- .enable_bit = AM33XX_MODULEMODE_SWCTRL_SHIFT, -- .clkdm_name = "clk_24mhz_clkdm", --}; -- --DEFINE_STRUCT_CLK(clkdiv32k_ick, clkdiv32k_ick_parent_names, clkdiv32k_ick_ops); -- --/* "usbotg_fck" is an additional clock and not really a modulemode */ --DEFINE_CLK_GATE(usbotg_fck, "dpll_per_ck", &dpll_per_ck, 0x0, -- AM33XX_CM_CLKDCOLDO_DPLL_PER, AM33XX_ST_DPLL_CLKDCOLDO_SHIFT, -- 0x0, NULL); -- --DEFINE_CLK_GATE(ieee5000_fck, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck, -- 0x0, AM33XX_CM_PER_IEEE5000_CLKCTRL, -- AM33XX_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); -- --/* Timers */ --static const struct clksel timer1_clkmux_sel[] = { -- { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, -- { .parent = &clkdiv32k_ick, .rates = div_1_1_rates }, -- { .parent = &tclkin_ck, .rates = div_1_2_rates }, -- { .parent = &clk_rc32k_ck, .rates = div_1_3_rates }, -- { .parent = &clk_32768_ck, .rates = div_1_4_rates }, -- { .parent = NULL }, --}; -- --static const char *timer1_ck_parents[] = { -- "sys_clkin_ck", "clkdiv32k_ick", "tclkin_ck", "clk_rc32k_ck", -- "clk_32768_ck", --}; -- --static struct clk timer1_fck; -- --static const struct clk_ops timer1_fck_ops = { -- .recalc_rate = &omap2_clksel_recalc, -- .get_parent = &omap2_clksel_find_parent_index, -- .set_parent = &omap2_clksel_set_parent, -- .init = &omap2_init_clk_clkdm, --}; -- --static struct clk_hw_omap timer1_fck_hw = { -- .hw = { -- .clk = &timer1_fck, -- }, -- .clkdm_name = "l4ls_clkdm", -- .clksel = timer1_clkmux_sel, -- .clksel_reg = AM33XX_CLKSEL_TIMER1MS_CLK, -- .clksel_mask = AM33XX_CLKSEL_0_2_MASK, --}; -- --DEFINE_STRUCT_CLK(timer1_fck, timer1_ck_parents, timer1_fck_ops); -- --static const struct clksel timer2_to_7_clk_sel[] = { -- { .parent = &tclkin_ck, .rates = div_1_0_rates }, -- { .parent = &sys_clkin_ck, .rates = div_1_1_rates }, -- { .parent = &clkdiv32k_ick, .rates = div_1_2_rates }, -- { .parent = NULL }, --}; -- --static const char *timer2_to_7_ck_parents[] = { -- "tclkin_ck", "sys_clkin_ck", "clkdiv32k_ick", --}; -- --static struct clk timer2_fck; -- --static struct clk_hw_omap timer2_fck_hw = { -- .hw = { -- .clk = &timer2_fck, -- }, -- .clkdm_name = "l4ls_clkdm", -- .clksel = timer2_to_7_clk_sel, -- .clksel_reg = AM33XX_CLKSEL_TIMER2_CLK, -- .clksel_mask = AM33XX_CLKSEL_0_1_MASK, --}; -- --DEFINE_STRUCT_CLK(timer2_fck, timer2_to_7_ck_parents, timer1_fck_ops); -- --static struct clk timer3_fck; -- --static struct clk_hw_omap timer3_fck_hw = { -- .hw = { -- .clk = &timer3_fck, -- }, -- .clkdm_name = "l4ls_clkdm", -- .clksel = timer2_to_7_clk_sel, -- .clksel_reg = AM33XX_CLKSEL_TIMER3_CLK, -- .clksel_mask = AM33XX_CLKSEL_0_1_MASK, --}; -- --DEFINE_STRUCT_CLK(timer3_fck, timer2_to_7_ck_parents, timer1_fck_ops); -- --static struct clk timer4_fck; -- --static struct clk_hw_omap timer4_fck_hw = { -- .hw = { -- .clk = &timer4_fck, -- }, -- .clkdm_name = "l4ls_clkdm", -- .clksel = timer2_to_7_clk_sel, -- .clksel_reg = AM33XX_CLKSEL_TIMER4_CLK, -- .clksel_mask = AM33XX_CLKSEL_0_1_MASK, --}; -- --DEFINE_STRUCT_CLK(timer4_fck, timer2_to_7_ck_parents, timer1_fck_ops); -- --static struct clk timer5_fck; -- --static struct clk_hw_omap timer5_fck_hw = { -- .hw = { -- .clk = &timer5_fck, -- }, -- .clkdm_name = "l4ls_clkdm", -- .clksel = timer2_to_7_clk_sel, -- .clksel_reg = AM33XX_CLKSEL_TIMER5_CLK, -- .clksel_mask = AM33XX_CLKSEL_0_1_MASK, --}; -- --DEFINE_STRUCT_CLK(timer5_fck, timer2_to_7_ck_parents, timer1_fck_ops); -- --static struct clk timer6_fck; -- --static struct clk_hw_omap timer6_fck_hw = { -- .hw = { -- .clk = &timer6_fck, -- }, -- .clkdm_name = "l4ls_clkdm", -- .clksel = timer2_to_7_clk_sel, -- .clksel_reg = AM33XX_CLKSEL_TIMER6_CLK, -- .clksel_mask = AM33XX_CLKSEL_0_1_MASK, --}; -- --DEFINE_STRUCT_CLK(timer6_fck, timer2_to_7_ck_parents, timer1_fck_ops); -- --static struct clk timer7_fck; -- --static struct clk_hw_omap timer7_fck_hw = { -- .hw = { -- .clk = &timer7_fck, -- }, -- .clkdm_name = "l4ls_clkdm", -- .clksel = timer2_to_7_clk_sel, -- .clksel_reg = AM33XX_CLKSEL_TIMER7_CLK, -- .clksel_mask = AM33XX_CLKSEL_0_1_MASK, --}; -- --DEFINE_STRUCT_CLK(timer7_fck, timer2_to_7_ck_parents, timer1_fck_ops); -- --DEFINE_CLK_FIXED_FACTOR(cpsw_125mhz_gclk, -- "dpll_core_m5_ck", -- &dpll_core_m5_ck, -- 0x0, -- 1, 2); -- --static const struct clk_ops cpsw_fck_ops = { -- .recalc_rate = &omap2_clksel_recalc, -- .get_parent = &omap2_clksel_find_parent_index, -- .set_parent = &omap2_clksel_set_parent, --}; -- --static const struct clksel cpsw_cpts_rft_clkmux_sel[] = { -- { .parent = &dpll_core_m5_ck, .rates = div_1_0_rates }, -- { .parent = &dpll_core_m4_ck, .rates = div_1_1_rates }, -- { .parent = NULL }, --}; -- --static const char *cpsw_cpts_rft_ck_parents[] = { -- "dpll_core_m5_ck", "dpll_core_m4_ck", --}; -- --static struct clk cpsw_cpts_rft_clk; -- --static struct clk_hw_omap cpsw_cpts_rft_clk_hw = { -- .hw = { -- .clk = &cpsw_cpts_rft_clk, -- }, -- .clkdm_name = "cpsw_125mhz_clkdm", -- .clksel = cpsw_cpts_rft_clkmux_sel, -- .clksel_reg = AM33XX_CM_CPTS_RFT_CLKSEL, -- .clksel_mask = AM33XX_CLKSEL_0_0_MASK, --}; -- --DEFINE_STRUCT_CLK(cpsw_cpts_rft_clk, cpsw_cpts_rft_ck_parents, cpsw_fck_ops); -- -- --/* gpio */ --static const char *gpio0_ck_parents[] = { -- "clk_rc32k_ck", "clk_32768_ck", "clkdiv32k_ick", --}; -- --static const struct clksel gpio0_dbclk_mux_sel[] = { -- { .parent = &clk_rc32k_ck, .rates = div_1_0_rates }, -- { .parent = &clk_32768_ck, .rates = div_1_1_rates }, -- { .parent = &clkdiv32k_ick, .rates = div_1_2_rates }, -- { .parent = NULL }, --}; -- --static const struct clk_ops gpio_fck_ops = { -- .recalc_rate = &omap2_clksel_recalc, -- .get_parent = &omap2_clksel_find_parent_index, -- .set_parent = &omap2_clksel_set_parent, -- .init = &omap2_init_clk_clkdm, --}; -- --static struct clk gpio0_dbclk_mux_ck; -- --static struct clk_hw_omap gpio0_dbclk_mux_ck_hw = { -- .hw = { -- .clk = &gpio0_dbclk_mux_ck, -- }, -- .clkdm_name = "l4_wkup_clkdm", -- .clksel = gpio0_dbclk_mux_sel, -- .clksel_reg = AM33XX_CLKSEL_GPIO0_DBCLK, -- .clksel_mask = AM33XX_CLKSEL_0_1_MASK, --}; -- --DEFINE_STRUCT_CLK(gpio0_dbclk_mux_ck, gpio0_ck_parents, gpio_fck_ops); -- --DEFINE_CLK_GATE(gpio0_dbclk, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, 0x0, -- AM33XX_CM_WKUP_GPIO0_CLKCTRL, -- AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT, 0x0, NULL); -- --DEFINE_CLK_GATE(gpio1_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0, -- AM33XX_CM_PER_GPIO1_CLKCTRL, -- AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT, 0x0, NULL); -- --DEFINE_CLK_GATE(gpio2_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0, -- AM33XX_CM_PER_GPIO2_CLKCTRL, -- AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT, 0x0, NULL); -- --DEFINE_CLK_GATE(gpio3_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0, -- AM33XX_CM_PER_GPIO3_CLKCTRL, -- AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT, 0x0, NULL); -- -- --static const char *pruss_ck_parents[] = { -- "l3_gclk", "dpll_disp_m2_ck", --}; -- --static const struct clksel pruss_ocp_clk_mux_sel[] = { -- { .parent = &l3_gclk, .rates = div_1_0_rates }, -- { .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates }, -- { .parent = NULL }, --}; -- --static struct clk pruss_ocp_gclk; -- --static struct clk_hw_omap pruss_ocp_gclk_hw = { -- .hw = { -- .clk = &pruss_ocp_gclk, -- }, -- .clkdm_name = "pruss_ocp_clkdm", -- .clksel = pruss_ocp_clk_mux_sel, -- .clksel_reg = AM33XX_CLKSEL_PRUSS_OCP_CLK, -- .clksel_mask = AM33XX_CLKSEL_0_0_MASK, --}; -- --DEFINE_STRUCT_CLK(pruss_ocp_gclk, pruss_ck_parents, gpio_fck_ops); -- --static const char *lcd_ck_parents[] = { -- "dpll_disp_m2_ck", "dpll_core_m5_ck", "dpll_per_m2_ck", --}; -- --static const struct clksel lcd_clk_mux_sel[] = { -- { .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates }, -- { .parent = &dpll_core_m5_ck, .rates = div_1_1_rates }, -- { .parent = &dpll_per_m2_ck, .rates = div_1_2_rates }, -- { .parent = NULL }, --}; -- --static struct clk lcd_gclk; -- --static struct clk_hw_omap lcd_gclk_hw = { -- .hw = { -- .clk = &lcd_gclk, -- }, -- .clkdm_name = "lcdc_clkdm", -- .clksel = lcd_clk_mux_sel, -- .clksel_reg = AM33XX_CLKSEL_LCDC_PIXEL_CLK, -- .clksel_mask = AM33XX_CLKSEL_0_1_MASK, --}; -- --DEFINE_STRUCT_CLK_FLAGS(lcd_gclk, lcd_ck_parents, -- gpio_fck_ops, CLK_SET_RATE_PARENT); -- --DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2); -- --static const char *gfx_ck_parents[] = { -- "dpll_core_m4_ck", "dpll_per_m2_ck", --}; -- --static const struct clksel gfx_clksel_sel[] = { -- { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates }, -- { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates }, -- { .parent = NULL }, --}; -- --static struct clk gfx_fclk_clksel_ck; -- --static struct clk_hw_omap gfx_fclk_clksel_ck_hw = { -- .hw = { -- .clk = &gfx_fclk_clksel_ck, -- }, -- .clksel = gfx_clksel_sel, -- .clksel_reg = AM33XX_CLKSEL_GFX_FCLK, -- .clksel_mask = AM33XX_CLKSEL_GFX_FCLK_MASK, --}; -- --DEFINE_STRUCT_CLK(gfx_fclk_clksel_ck, gfx_ck_parents, gpio_fck_ops); -- --static const struct clk_div_table div_1_0_2_1_rates[] = { -- { .div = 1, .val = 0, }, -- { .div = 2, .val = 1, }, -- { .div = 0 }, --}; -- --DEFINE_CLK_DIVIDER_TABLE(gfx_fck_div_ck, "gfx_fclk_clksel_ck", -- &gfx_fclk_clksel_ck, 0x0, AM33XX_CLKSEL_GFX_FCLK, -- AM33XX_CLKSEL_0_0_SHIFT, AM33XX_CLKSEL_0_0_WIDTH, -- 0x0, div_1_0_2_1_rates, NULL); -- --static const char *sysclkout_ck_parents[] = { -- "clk_32768_ck", "l3_gclk", "dpll_ddr_m2_ck", "dpll_per_m2_ck", -- "lcd_gclk", --}; -- --static const struct clksel sysclkout_pre_sel[] = { -- { .parent = &clk_32768_ck, .rates = div_1_0_rates }, -- { .parent = &l3_gclk, .rates = div_1_1_rates }, -- { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates }, -- { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates }, -- { .parent = &lcd_gclk, .rates = div_1_4_rates }, -- { .parent = NULL }, --}; -- --static struct clk sysclkout_pre_ck; -- --static struct clk_hw_omap sysclkout_pre_ck_hw = { -- .hw = { -- .clk = &sysclkout_pre_ck, -- }, -- .clksel = sysclkout_pre_sel, -- .clksel_reg = AM33XX_CM_CLKOUT_CTRL, -- .clksel_mask = AM33XX_CLKOUT2SOURCE_MASK, --}; -- --DEFINE_STRUCT_CLK(sysclkout_pre_ck, sysclkout_ck_parents, gpio_fck_ops); -- --/* Divide by 8 clock rates with default clock is 1/1*/ --static const struct clk_div_table div8_rates[] = { -- { .div = 1, .val = 0, }, -- { .div = 2, .val = 1, }, -- { .div = 3, .val = 2, }, -- { .div = 4, .val = 3, }, -- { .div = 5, .val = 4, }, -- { .div = 6, .val = 5, }, -- { .div = 7, .val = 6, }, -- { .div = 8, .val = 7, }, -- { .div = 0 }, --}; -- --DEFINE_CLK_DIVIDER_TABLE(clkout2_div_ck, "sysclkout_pre_ck", &sysclkout_pre_ck, -- 0x0, AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2DIV_SHIFT, -- AM33XX_CLKOUT2DIV_WIDTH, 0x0, div8_rates, NULL); -- --DEFINE_CLK_GATE(clkout2_ck, "clkout2_div_ck", &clkout2_div_ck, 0x0, -- AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2EN_SHIFT, 0x0, NULL); -- --static const char *wdt_ck_parents[] = { -- "clk_rc32k_ck", "clkdiv32k_ick", --}; -- --static const struct clksel wdt_clkmux_sel[] = { -- { .parent = &clk_rc32k_ck, .rates = div_1_0_rates }, -- { .parent = &clkdiv32k_ick, .rates = div_1_1_rates }, -- { .parent = NULL }, --}; -- --static struct clk wdt1_fck; -- --static struct clk_hw_omap wdt1_fck_hw = { -- .hw = { -- .clk = &wdt1_fck, -- }, -- .clkdm_name = "l4_wkup_clkdm", -- .clksel = wdt_clkmux_sel, -- .clksel_reg = AM33XX_CLKSEL_WDT1_CLK, -- .clksel_mask = AM33XX_CLKSEL_0_1_MASK, --}; -- --DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops); -- --static const char *pwmss_clk_parents[] = { -- "dpll_per_m2_ck", --}; -- --static const struct clk_ops ehrpwm_tbclk_ops = { -- .enable = &omap2_dflt_clk_enable, -- .disable = &omap2_dflt_clk_disable, --}; -- --DEFINE_CLK_OMAP_MUX_GATE(ehrpwm0_tbclk, "l4ls_clkdm", -- NULL, NULL, 0, -- AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL), -- AM33XX_PWMSS0_TBCLKEN_SHIFT, -- NULL, pwmss_clk_parents, ehrpwm_tbclk_ops); -- --DEFINE_CLK_OMAP_MUX_GATE(ehrpwm1_tbclk, "l4ls_clkdm", -- NULL, NULL, 0, -- AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL), -- AM33XX_PWMSS1_TBCLKEN_SHIFT, -- NULL, pwmss_clk_parents, ehrpwm_tbclk_ops); -- --DEFINE_CLK_OMAP_MUX_GATE(ehrpwm2_tbclk, "l4ls_clkdm", -- NULL, NULL, 0, -- AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL), -- AM33XX_PWMSS2_TBCLKEN_SHIFT, -- NULL, pwmss_clk_parents, ehrpwm_tbclk_ops); -- --/* -- * debugss optional clocks -- */ --DEFINE_CLK_GATE(dbg_sysclk_ck, "sys_clkin_ck", &sys_clkin_ck, -- 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, -- AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT, 0x0, NULL); -- --DEFINE_CLK_GATE(dbg_clka_ck, "dpll_core_m4_ck", &dpll_core_m4_ck, -- 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, -- AM33XX_OPTCLK_DEBUG_CLKA_SHIFT, 0x0, NULL); -- --static const char *stm_pmd_clock_mux_ck_parents[] = { -- "dbg_sysclk_ck", "dbg_clka_ck", --}; -- --DEFINE_CLK_MUX(stm_pmd_clock_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0, -- AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_STM_PMD_CLKSEL_SHIFT, -- AM33XX_STM_PMD_CLKSEL_WIDTH, 0x0, NULL); -- --DEFINE_CLK_MUX(trace_pmd_clk_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0, -- AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, -- AM33XX_TRC_PMD_CLKSEL_SHIFT, -- AM33XX_TRC_PMD_CLKSEL_WIDTH, 0x0, NULL); -- --DEFINE_CLK_DIVIDER(stm_clk_div_ck, "stm_pmd_clock_mux_ck", -- &stm_pmd_clock_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, -- AM33XX_STM_PMD_CLKDIVSEL_SHIFT, -- AM33XX_STM_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, -- NULL); -- --DEFINE_CLK_DIVIDER(trace_clk_div_ck, "trace_pmd_clk_mux_ck", -- &trace_pmd_clk_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, -- AM33XX_TRC_PMD_CLKDIVSEL_SHIFT, -- AM33XX_TRC_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, -- NULL); -- --/* -- * clkdev -- */ --static struct omap_clk am33xx_clks[] = { -- CLK(NULL, "clk_32768_ck", &clk_32768_ck), -- CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck), -- CLK(NULL, "virt_19200000_ck", &virt_19200000_ck), -- CLK(NULL, "virt_24000000_ck", &virt_24000000_ck), -- CLK(NULL, "virt_25000000_ck", &virt_25000000_ck), -- CLK(NULL, "virt_26000000_ck", &virt_26000000_ck), -- CLK(NULL, "sys_clkin_ck", &sys_clkin_ck), -- CLK(NULL, "tclkin_ck", &tclkin_ck), -- CLK(NULL, "dpll_core_ck", &dpll_core_ck), -- CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck), -- CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck), -- CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck), -- CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck), -- CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck), -- CLK("cpu0", NULL, &dpll_mpu_ck), -- CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck), -- CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck), -- CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck), -- CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck), -- CLK(NULL, "dpll_disp_ck", &dpll_disp_ck), -- CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck), -- CLK(NULL, "dpll_per_ck", &dpll_per_ck), -- CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck), -- CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck), -- CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck), -- CLK(NULL, "adc_tsc_fck", &adc_tsc_fck), -- CLK(NULL, "cefuse_fck", &cefuse_fck), -- CLK(NULL, "clkdiv32k_ck", &clkdiv32k_ck), -- CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick), -- CLK(NULL, "dcan0_fck", &dcan0_fck), -- CLK("481cc000.d_can", NULL, &dcan0_fck), -- CLK(NULL, "dcan1_fck", &dcan1_fck), -- CLK("481d0000.d_can", NULL, &dcan1_fck), -- CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk), -- CLK(NULL, "mcasp0_fck", &mcasp0_fck), -- CLK(NULL, "mcasp1_fck", &mcasp1_fck), -- CLK(NULL, "mmu_fck", &mmu_fck), -- CLK(NULL, "smartreflex0_fck", &smartreflex0_fck), -- CLK(NULL, "smartreflex1_fck", &smartreflex1_fck), -- CLK(NULL, "sha0_fck", &sha0_fck), -- CLK(NULL, "aes0_fck", &aes0_fck), -- CLK(NULL, "rng_fck", &rng_fck), -- CLK(NULL, "timer1_fck", &timer1_fck), -- CLK(NULL, "timer2_fck", &timer2_fck), -- CLK(NULL, "timer3_fck", &timer3_fck), -- CLK(NULL, "timer4_fck", &timer4_fck), -- CLK(NULL, "timer5_fck", &timer5_fck), -- CLK(NULL, "timer6_fck", &timer6_fck), -- CLK(NULL, "timer7_fck", &timer7_fck), -- CLK(NULL, "usbotg_fck", &usbotg_fck), -- CLK(NULL, "ieee5000_fck", &ieee5000_fck), -- CLK(NULL, "wdt1_fck", &wdt1_fck), -- CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk), -- CLK(NULL, "l3_gclk", &l3_gclk), -- CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck), -- CLK(NULL, "l4hs_gclk", &l4hs_gclk), -- CLK(NULL, "l3s_gclk", &l3s_gclk), -- CLK(NULL, "l4fw_gclk", &l4fw_gclk), -- CLK(NULL, "l4ls_gclk", &l4ls_gclk), -- CLK(NULL, "clk_24mhz", &clk_24mhz), -- CLK(NULL, "sysclk_div_ck", &sysclk_div_ck), -- CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk), -- CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk), -- CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck), -- CLK(NULL, "gpio0_dbclk", &gpio0_dbclk), -- CLK(NULL, "gpio1_dbclk", &gpio1_dbclk), -- CLK(NULL, "gpio2_dbclk", &gpio2_dbclk), -- CLK(NULL, "gpio3_dbclk", &gpio3_dbclk), -- CLK(NULL, "lcd_gclk", &lcd_gclk), -- CLK(NULL, "mmc_clk", &mmc_clk), -- CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck), -- CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck), -- CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck), -- CLK(NULL, "clkout2_div_ck", &clkout2_div_ck), -- CLK(NULL, "timer_32k_ck", &clkdiv32k_ick), -- CLK(NULL, "timer_sys_ck", &sys_clkin_ck), -- CLK(NULL, "dbg_sysclk_ck", &dbg_sysclk_ck), -- CLK(NULL, "dbg_clka_ck", &dbg_clka_ck), -- CLK(NULL, "stm_pmd_clock_mux_ck", &stm_pmd_clock_mux_ck), -- CLK(NULL, "trace_pmd_clk_mux_ck", &trace_pmd_clk_mux_ck), -- CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck), -- CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck), -- CLK(NULL, "clkout2_ck", &clkout2_ck), -- CLK("48300200.ehrpwm", "tbclk", &ehrpwm0_tbclk), -- CLK("48302200.ehrpwm", "tbclk", &ehrpwm1_tbclk), -- CLK("48304200.ehrpwm", "tbclk", &ehrpwm2_tbclk), --}; -- -- --static const char *enable_init_clks[] = { -- "dpll_ddr_m2_ck", -- "dpll_mpu_m2_ck", -- "l3_gclk", -- "l4hs_gclk", -- "l4fw_gclk", -- "l4ls_gclk", -- "clkout2_ck", /* Required for external peripherals like, Audio codecs */ --}; -- --int __init am33xx_clk_init(void) --{ -- if (soc_is_am33xx()) -- cpu_mask = RATE_IN_AM33XX; -- -- omap_clocks_register(am33xx_clks, ARRAY_SIZE(am33xx_clks)); -- -- omap2_clk_disable_autoidle_all(); -- -- omap2_clk_enable_init_clocks(enable_init_clks, -- ARRAY_SIZE(enable_init_clks)); -- -- /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always -- * physically present, in such a case HWMOD enabling of -- * clock would be failure with default parent. And timer -- * probe thinks clock is already enabled, this leads to -- * crash upon accessing timer 3 & 6 registers in probe. -- * Fix by setting parent of both these timers to master -- * oscillator clock. -- */ -- -- clk_set_parent(&timer3_fck, &sys_clkin_ck); -- clk_set_parent(&timer6_fck, &sys_clkin_ck); -- /* -- * The On-Chip 32K RC Osc clock is not an accurate clock-source as per -- * the design/spec, so as a result, for example, timer which supposed -- * to get expired @60Sec, but will expire somewhere ~@40Sec, which is -- * not expected by any use-case, so change WDT1 clock source to PRCM -- * 32KHz clock. -- */ -- clk_set_parent(&wdt1_fck, &clkdiv32k_ick); -- -- return 0; --} ---- a/arch/arm/mach-omap2/clkt_dpll.c -+++ b/arch/arm/mach-omap2/clkt_dpll.c -@@ -209,7 +209,7 @@ u8 omap2_init_dpll_parent(struct clk_hw - if (v == OMAP3XXX_EN_DPLL_LPBYPASS || - v == OMAP3XXX_EN_DPLL_FRBYPASS) - return 1; -- } else if (soc_is_am33xx() || cpu_is_omap44xx()) { -+ } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) { - if (v == OMAP4XXX_EN_DPLL_LPBYPASS || - v == OMAP4XXX_EN_DPLL_FRBYPASS || - v == OMAP4XXX_EN_DPLL_MNBYPASS) -@@ -255,7 +255,7 @@ unsigned long omap2_get_dpll_rate(struct - if (v == OMAP3XXX_EN_DPLL_LPBYPASS || - v == OMAP3XXX_EN_DPLL_FRBYPASS) - return __clk_get_rate(dd->clk_bypass); -- } else if (soc_is_am33xx() || cpu_is_omap44xx()) { -+ } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) { - if (v == OMAP4XXX_EN_DPLL_LPBYPASS || - v == OMAP4XXX_EN_DPLL_FRBYPASS || - v == OMAP4XXX_EN_DPLL_MNBYPASS) ---- a/arch/arm/mach-omap2/clock3xxx.h -+++ b/arch/arm/mach-omap2/clock3xxx.h -@@ -9,11 +9,12 @@ - #define __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H - - int omap3xxx_clk_init(void); --int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate, -- unsigned long parent_rate); -+int omap3430_clk_init(void); -+int omap3630_clk_init(void); -+int ti81xx_clk_init(void); -+int am35xx_clk_init(void); - int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate, - unsigned long parent_rate); --void omap3_clk_lock_dpll5(void); - - extern struct clk *sdrc_ick_p; - extern struct clk *arm_fck_p; ---- a/arch/arm/mach-omap2/clock.c -+++ b/arch/arm/mach-omap2/clock.c -@@ -520,6 +520,9 @@ int omap2_clk_enable_autoidle_all(void) - list_for_each_entry(c, &clk_hw_omap_clocks, node) - if (c->ops && c->ops->allow_idle) - c->ops->allow_idle(c); -+ -+ of_omap_clk_allow_autoidle_all(); -+ - return 0; - } - -@@ -539,6 +542,9 @@ int omap2_clk_disable_autoidle_all(void) - list_for_each_entry(c, &clk_hw_omap_clocks, node) - if (c->ops && c->ops->deny_idle) - c->ops->deny_idle(c); -+ -+ of_omap_clk_deny_autoidle_all(); -+ - return 0; - } - ---- a/arch/arm/mach-omap2/clockdomain.h -+++ b/arch/arm/mach-omap2/clockdomain.h -@@ -132,7 +132,7 @@ struct clockdomain { - u8 _flags; - const u8 dep_bit; - const u8 prcm_partition; -- const s16 cm_inst; -+ const u16 cm_inst; - const u16 clkdm_offs; - struct clkdm_dep *wkdep_srcs; - struct clkdm_dep *sleepdep_srcs; -@@ -215,6 +215,7 @@ extern void __init omap242x_clockdomains - extern void __init omap243x_clockdomains_init(void); - extern void __init omap3xxx_clockdomains_init(void); - extern void __init am33xx_clockdomains_init(void); -+extern void am43xx_clockdomains_init(void); - extern void __init omap44xx_clockdomains_init(void); - extern void __init omap54xx_clockdomains_init(void); - extern void __init dra7xx_clockdomains_init(void); -@@ -226,6 +227,7 @@ extern struct clkdm_ops omap2_clkdm_oper - extern struct clkdm_ops omap3_clkdm_operations; - extern struct clkdm_ops omap4_clkdm_operations; - extern struct clkdm_ops am33xx_clkdm_operations; -+extern struct clkdm_ops am43xx_clkdm_operations; - - extern struct clkdm_dep gfx_24xx_wkdeps[]; - extern struct clkdm_dep dsp_24xx_wkdeps[]; ---- /dev/null -+++ b/arch/arm/mach-omap2/clockdomains43xx_data.c -@@ -0,0 +1,199 @@ -+/* -+ * AM43xx Clock domains framework -+ * -+ * Copyright (C) 2013 Texas Instruments, Inc. -+ * -+ * This file is made by modifying the file generated automatically -+ * from the OMAP hardware databases. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include "clockdomain.h" -+#include "prcm44xx.h" -+#include "prcm43xx.h" -+ -+static struct clockdomain l4_cefuse_43xx_clkdm = { -+ .name = "l4_cefuse_clkdm", -+ .pwrdm = { .name = "cefuse_pwrdm" }, -+ .prcm_partition = AM43XX_CM_PARTITION, -+ .cm_inst = AM43XX_CM_CEFUSE_INST, -+ .clkdm_offs = AM43XX_CM_CEFUSE_CEFUSE_CDOFFS, -+ .flags = CLKDM_CAN_SWSUP, -+}; -+ -+static struct clockdomain mpu_43xx_clkdm = { -+ .name = "mpu_clkdm", -+ .pwrdm = { .name = "mpu_pwrdm" }, -+ .prcm_partition = AM43XX_CM_PARTITION, -+ .cm_inst = AM43XX_CM_MPU_INST, -+ .clkdm_offs = AM43XX_CM_MPU_MPU_CDOFFS, -+ .flags = CLKDM_CAN_HWSUP_SWSUP, -+}; -+ -+static struct clockdomain l4ls_43xx_clkdm = { -+ .name = "l4ls_clkdm", -+ .pwrdm = { .name = "per_pwrdm" }, -+ .prcm_partition = AM43XX_CM_PARTITION, -+ .cm_inst = AM43XX_CM_PER_INST, -+ .clkdm_offs = AM43XX_CM_PER_L4LS_CDOFFS, -+ .flags = CLKDM_CAN_SWSUP, -+}; -+ -+static struct clockdomain tamper_43xx_clkdm = { -+ .name = "tamper_clkdm", -+ .pwrdm = { .name = "tamper_pwrdm" }, -+ .prcm_partition = AM43XX_CM_PARTITION, -+ .cm_inst = AM43XX_CM_TAMPER_INST, -+ .clkdm_offs = AM43XX_CM_TAMPER_TAMPER_CDOFFS, -+ .flags = CLKDM_CAN_SWSUP, -+}; -+ -+static struct clockdomain l4_rtc_43xx_clkdm = { -+ .name = "l4_rtc_clkdm", -+ .pwrdm = { .name = "rtc_pwrdm" }, -+ .prcm_partition = AM43XX_CM_PARTITION, -+ .cm_inst = AM43XX_CM_RTC_INST, -+ .clkdm_offs = AM43XX_CM_RTC_RTC_CDOFFS, -+ .flags = CLKDM_CAN_SWSUP, -+}; -+ -+static struct clockdomain pruss_ocp_43xx_clkdm = { -+ .name = "pruss_ocp_clkdm", -+ .pwrdm = { .name = "per_pwrdm" }, -+ .prcm_partition = AM43XX_CM_PARTITION, -+ .cm_inst = AM43XX_CM_PER_INST, -+ .clkdm_offs = AM43XX_CM_PER_ICSS_CDOFFS, -+ .flags = CLKDM_CAN_SWSUP, -+}; -+ -+static struct clockdomain ocpwp_l3_43xx_clkdm = { -+ .name = "ocpwp_l3_clkdm", -+ .pwrdm = { .name = "per_pwrdm" }, -+ .prcm_partition = AM43XX_CM_PARTITION, -+ .cm_inst = AM43XX_CM_PER_INST, -+ .clkdm_offs = AM43XX_CM_PER_OCPWP_L3_CDOFFS, -+ .flags = CLKDM_CAN_SWSUP, -+}; -+ -+static struct clockdomain l3s_tsc_43xx_clkdm = { -+ .name = "l3s_tsc_clkdm", -+ .pwrdm = { .name = "wkup_pwrdm" }, -+ .prcm_partition = AM43XX_CM_PARTITION, -+ .cm_inst = AM43XX_CM_WKUP_INST, -+ .clkdm_offs = AM43XX_CM_WKUP_L3S_TSC_CDOFFS, -+ .flags = CLKDM_CAN_SWSUP, -+}; -+ -+static struct clockdomain dss_43xx_clkdm = { -+ .name = "dss_clkdm", -+ .pwrdm = { .name = "per_pwrdm" }, -+ .prcm_partition = AM43XX_CM_PARTITION, -+ .cm_inst = AM43XX_CM_PER_INST, -+ .clkdm_offs = AM43XX_CM_PER_DSS_CDOFFS, -+ .flags = CLKDM_CAN_SWSUP, -+}; -+ -+static struct clockdomain l3_aon_43xx_clkdm = { -+ .name = "l3_aon_clkdm", -+ .pwrdm = { .name = "wkup_pwrdm" }, -+ .prcm_partition = AM43XX_CM_PARTITION, -+ .cm_inst = AM43XX_CM_WKUP_INST, -+ .clkdm_offs = AM43XX_CM_WKUP_L3_AON_CDOFFS, -+ .flags = CLKDM_CAN_SWSUP, -+}; -+ -+static struct clockdomain emif_43xx_clkdm = { -+ .name = "emif_clkdm", -+ .pwrdm = { .name = "per_pwrdm" }, -+ .prcm_partition = AM43XX_CM_PARTITION, -+ .cm_inst = AM43XX_CM_PER_INST, -+ .clkdm_offs = AM43XX_CM_PER_EMIF_CDOFFS, -+ .flags = CLKDM_CAN_SWSUP, -+}; -+ -+static struct clockdomain l4_wkup_aon_43xx_clkdm = { -+ .name = "l4_wkup_aon_clkdm", -+ .pwrdm = { .name = "wkup_pwrdm" }, -+ .prcm_partition = AM43XX_CM_PARTITION, -+ .cm_inst = AM43XX_CM_WKUP_INST, -+ .clkdm_offs = AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS, -+}; -+ -+static struct clockdomain l3_43xx_clkdm = { -+ .name = "l3_clkdm", -+ .pwrdm = { .name = "per_pwrdm" }, -+ .prcm_partition = AM43XX_CM_PARTITION, -+ .cm_inst = AM43XX_CM_PER_INST, -+ .clkdm_offs = AM43XX_CM_PER_L3_CDOFFS, -+ .flags = CLKDM_CAN_SWSUP, -+}; -+ -+static struct clockdomain l4_wkup_43xx_clkdm = { -+ .name = "l4_wkup_clkdm", -+ .pwrdm = { .name = "wkup_pwrdm" }, -+ .prcm_partition = AM43XX_CM_PARTITION, -+ .cm_inst = AM43XX_CM_WKUP_INST, -+ .clkdm_offs = AM43XX_CM_WKUP_WKUP_CDOFFS, -+ .flags = CLKDM_CAN_SWSUP, -+}; -+ -+static struct clockdomain cpsw_125mhz_43xx_clkdm = { -+ .name = "cpsw_125mhz_clkdm", -+ .pwrdm = { .name = "per_pwrdm" }, -+ .prcm_partition = AM43XX_CM_PARTITION, -+ .cm_inst = AM43XX_CM_PER_INST, -+ .clkdm_offs = AM43XX_CM_PER_CPSW_CDOFFS, -+ .flags = CLKDM_CAN_SWSUP, -+}; -+ -+static struct clockdomain gfx_l3_43xx_clkdm = { -+ .name = "gfx_l3_clkdm", -+ .pwrdm = { .name = "gfx_pwrdm" }, -+ .prcm_partition = AM43XX_CM_PARTITION, -+ .cm_inst = AM43XX_CM_GFX_INST, -+ .clkdm_offs = AM43XX_CM_GFX_GFX_L3_CDOFFS, -+ .flags = CLKDM_CAN_SWSUP, -+}; -+ -+static struct clockdomain l3s_43xx_clkdm = { -+ .name = "l3s_clkdm", -+ .pwrdm = { .name = "per_pwrdm" }, -+ .prcm_partition = AM43XX_CM_PARTITION, -+ .cm_inst = AM43XX_CM_PER_INST, -+ .clkdm_offs = AM43XX_CM_PER_L3S_CDOFFS, -+ .flags = CLKDM_CAN_SWSUP, -+}; -+ -+static struct clockdomain *clockdomains_am43xx[] __initdata = { -+ &l4_cefuse_43xx_clkdm, -+ &mpu_43xx_clkdm, -+ &l4ls_43xx_clkdm, -+ &tamper_43xx_clkdm, -+ &l4_rtc_43xx_clkdm, -+ &pruss_ocp_43xx_clkdm, -+ &ocpwp_l3_43xx_clkdm, -+ &l3s_tsc_43xx_clkdm, -+ &dss_43xx_clkdm, -+ &l3_aon_43xx_clkdm, -+ &emif_43xx_clkdm, -+ &l4_wkup_aon_43xx_clkdm, -+ &l3_43xx_clkdm, -+ &l4_wkup_43xx_clkdm, -+ &cpsw_125mhz_43xx_clkdm, -+ &gfx_l3_43xx_clkdm, -+ &l3s_43xx_clkdm, -+ NULL -+}; -+ -+void __init am43xx_clockdomains_init(void) -+{ -+ clkdm_register_platform_funcs(&am43xx_clkdm_operations); -+ clkdm_register_clkdms(clockdomains_am43xx); -+ clkdm_complete_init(); -+} ---- a/arch/arm/mach-omap2/clockdomains7xx_data.c -+++ b/arch/arm/mach-omap2/clockdomains7xx_data.c -@@ -409,7 +409,7 @@ static struct clockdomain l4sec_7xx_clkd - .dep_bit = DRA7XX_L4SEC_STATDEP_SHIFT, - .wkdep_srcs = l4sec_wkup_sleep_deps, - .sleepdep_srcs = l4sec_wkup_sleep_deps, -- .flags = CLKDM_CAN_HWSUP_SWSUP, -+ .flags = CLKDM_CAN_SWSUP, - }; - - static struct clockdomain l3main1_7xx_clkdm = { -@@ -554,7 +554,7 @@ static struct clockdomain dss_7xx_clkdm - .dep_bit = DRA7XX_DSS_STATDEP_SHIFT, - .wkdep_srcs = dss_wkup_sleep_deps, - .sleepdep_srcs = dss_wkup_sleep_deps, -- .flags = CLKDM_CAN_HWSUP_SWSUP, -+ .flags = CLKDM_CAN_SWSUP, - }; - - static struct clockdomain emif_7xx_clkdm = { ---- a/arch/arm/mach-omap2/clock.h -+++ b/arch/arm/mach-omap2/clock.h -@@ -21,6 +21,7 @@ - - #include - #include -+#include - - struct omap_clk { - u16 cpu; -@@ -37,7 +38,6 @@ struct omap_clk { - } - - struct clockdomain; --#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) - - #define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \ - static struct clk _name = { \ -@@ -178,141 +178,6 @@ struct clksel { - const struct clksel_rate *rates; - }; - --/** -- * struct dpll_data - DPLL registers and integration data -- * @mult_div1_reg: register containing the DPLL M and N bitfields -- * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg -- * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg -- * @clk_bypass: struct clk pointer to the clock's bypass clock input -- * @clk_ref: struct clk pointer to the clock's reference clock input -- * @control_reg: register containing the DPLL mode bitfield -- * @enable_mask: mask of the DPLL mode bitfield in @control_reg -- * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate() -- * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate() -- * @last_rounded_m4xen: cache of the last M4X result of -- * omap4_dpll_regm4xen_round_rate() -- * @last_rounded_lpmode: cache of the last lpmode result of -- * omap4_dpll_lpmode_recalc() -- * @max_multiplier: maximum valid non-bypass multiplier value (actual) -- * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate() -- * @min_divider: minimum valid non-bypass divider value (actual) -- * @max_divider: maximum valid non-bypass divider value (actual) -- * @modes: possible values of @enable_mask -- * @autoidle_reg: register containing the DPLL autoidle mode bitfield -- * @idlest_reg: register containing the DPLL idle status bitfield -- * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg -- * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg -- * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg -- * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg -- * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg -- * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg -- * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs -- * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs -- * @flags: DPLL type/features (see below) -- * -- * Possible values for @flags: -- * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs) -- * -- * @freqsel_mask is only used on the OMAP34xx family and AM35xx. -- * -- * XXX Some DPLLs have multiple bypass inputs, so it's not technically -- * correct to only have one @clk_bypass pointer. -- * -- * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m, -- * @last_rounded_n) should be separated from the runtime-fixed fields -- * and placed into a different structure, so that the runtime-fixed data -- * can be placed into read-only space. -- */ --struct dpll_data { -- void __iomem *mult_div1_reg; -- u32 mult_mask; -- u32 div1_mask; -- struct clk *clk_bypass; -- struct clk *clk_ref; -- void __iomem *control_reg; -- u32 enable_mask; -- unsigned long last_rounded_rate; -- u16 last_rounded_m; -- u8 last_rounded_m4xen; -- u8 last_rounded_lpmode; -- u16 max_multiplier; -- u8 last_rounded_n; -- u8 min_divider; -- u16 max_divider; -- u8 modes; -- void __iomem *autoidle_reg; -- void __iomem *idlest_reg; -- u32 autoidle_mask; -- u32 freqsel_mask; -- u32 idlest_mask; -- u32 dco_mask; -- u32 sddiv_mask; -- u32 lpmode_mask; -- u32 m4xen_mask; -- u8 auto_recal_bit; -- u8 recal_en_bit; -- u8 recal_st_bit; -- u8 flags; --}; -- --/* -- * struct clk.flags possibilities -- * -- * XXX document the rest of the clock flags here -- * -- * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL -- * bits share the same register. This flag allows the -- * omap4_dpllmx*() code to determine which GATE_CTRL bit field -- * should be used. This is a temporary solution - a better approach -- * would be to associate clock type-specific data with the clock, -- * similar to the struct dpll_data approach. -- */ --#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ --#define CLOCK_IDLE_CONTROL (1 << 1) --#define CLOCK_NO_IDLE_PARENT (1 << 2) --#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ --#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ --#define CLOCK_CLKOUTX2 (1 << 5) -- --/** -- * struct clk_hw_omap - OMAP struct clk -- * @node: list_head connecting this clock into the full clock list -- * @enable_reg: register to write to enable the clock (see @enable_bit) -- * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) -- * @flags: see "struct clk.flags possibilities" above -- * @clksel_reg: for clksel clks, register va containing src/divisor select -- * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector -- * @clksel: for clksel clks, pointer to struct clksel for this clock -- * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock -- * @clkdm_name: clockdomain name that this clock is contained in -- * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime -- * @rate_offset: bitshift for rate selection bitfield (OMAP1 only) -- * @src_offset: bitshift for source selection bitfield (OMAP1 only) -- * -- * XXX @rate_offset, @src_offset should probably be removed and OMAP1 -- * clock code converted to use clksel. -- * -- */ -- --struct clk_hw_omap_ops; -- --struct clk_hw_omap { -- struct clk_hw hw; -- struct list_head node; -- unsigned long fixed_rate; -- u8 fixed_div; -- void __iomem *enable_reg; -- u8 enable_bit; -- u8 flags; -- void __iomem *clksel_reg; -- u32 clksel_mask; -- const struct clksel *clksel; -- struct dpll_data *dpll_data; -- const char *clkdm_name; -- struct clockdomain *clkdm; -- const struct clk_hw_omap_ops *ops; --}; -- - struct clk_hw_omap_ops { - void (*find_idlest)(struct clk_hw_omap *oclk, - void __iomem **idlest_reg, -@@ -348,36 +213,13 @@ unsigned long omap_fixed_divisor_recalc( - #define OMAP4XXX_EN_DPLL_FRBYPASS 0x6 - #define OMAP4XXX_EN_DPLL_LOCKED 0x7 - --/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ --#define DPLL_LOW_POWER_STOP 0x1 --#define DPLL_LOW_POWER_BYPASS 0x5 --#define DPLL_LOCKED 0x7 -- --/* DPLL Type and DCO Selection Flags */ --#define DPLL_J_TYPE 0x1 -- --long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, -- unsigned long *parent_rate); --unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate); --int omap3_noncore_dpll_enable(struct clk_hw *hw); --void omap3_noncore_dpll_disable(struct clk_hw *hw); --int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, -- unsigned long parent_rate); - u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk); - void omap3_dpll_allow_idle(struct clk_hw_omap *clk); - void omap3_dpll_deny_idle(struct clk_hw_omap *clk); --unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, -- unsigned long parent_rate); - int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk); - void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk); - void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk); --unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, -- unsigned long parent_rate); --long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, -- unsigned long target_rate, -- unsigned long *parent_rate); - --void omap2_init_clk_clkdm(struct clk_hw *clk); - void __init omap2_clk_disable_clkdm_control(void); - - /* clkt_clksel.c public functions */ -@@ -396,22 +238,15 @@ int omap2_clksel_set_parent(struct clk_h - extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk); - extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk); - --u8 omap2_init_dpll_parent(struct clk_hw *hw); - unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk); - --int omap2_dflt_clk_enable(struct clk_hw *hw); --void omap2_dflt_clk_disable(struct clk_hw *hw); --int omap2_dflt_clk_is_enabled(struct clk_hw *hw); - void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, - void __iomem **other_reg, - u8 *other_bit); - void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, - void __iomem **idlest_reg, - u8 *idlest_bit, u8 *idlest_val); --void omap2_init_clk_hw_omap_clocks(struct clk *clk); - int omap2_clk_enable_autoidle_all(void); --int omap2_clk_disable_autoidle_all(void); --void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); - int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); - void omap2_clk_print_new_rates(const char *hfclkin_ck_name, - const char *core_ck_name, -@@ -431,19 +266,8 @@ extern const struct clksel_rate gfx_l3_r - extern const struct clksel_rate dsp_ick_rates[]; - extern struct clk dummy_ck; - --extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; --extern const struct clk_hw_omap_ops clkhwops_iclk_wait; --extern const struct clk_hw_omap_ops clkhwops_wait; --extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; --extern const struct clk_hw_omap_ops clkhwops_iclk; - extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait; --extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait; --extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; --extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait; --extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait; - extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait; --extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; --extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait; - extern const struct clk_hw_omap_ops clkhwops_apll54; - extern const struct clk_hw_omap_ops clkhwops_apll96; - extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll; -@@ -460,8 +284,5 @@ extern const struct clksel_rate div31_1t - - extern int am33xx_clk_init(void); - --extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); --extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); -- - extern void omap_clocks_register(struct omap_clk *oclks, int cnt); - #endif ---- a/arch/arm/mach-omap2/cm33xx.c -+++ b/arch/arm/mach-omap2/cm33xx.c -@@ -48,13 +48,13 @@ - /* Private functions */ - - /* Read a register in a CM instance */ --static inline u32 am33xx_cm_read_reg(s16 inst, u16 idx) -+static inline u32 am33xx_cm_read_reg(u16 inst, u16 idx) - { - return __raw_readl(cm_base + inst + idx); - } - - /* Write into a register in a CM */ --static inline void am33xx_cm_write_reg(u32 val, s16 inst, u16 idx) -+static inline void am33xx_cm_write_reg(u32 val, u16 inst, u16 idx) - { - __raw_writel(val, cm_base + inst + idx); - } -@@ -82,7 +82,7 @@ static inline u32 am33xx_cm_clear_reg_bi - return am33xx_cm_rmw_reg_bits(bits, 0x0, inst, idx); - } - --static inline u32 am33xx_cm_read_reg_bits(u16 inst, s16 idx, u32 mask) -+static inline u32 am33xx_cm_read_reg_bits(u16 inst, u16 idx, u32 mask) - { - u32 v; - -@@ -102,7 +102,7 @@ static inline u32 am33xx_cm_read_reg_bit - * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to - * bit 0. - */ --static u32 _clkctrl_idlest(u16 inst, s16 cdoffs, u16 clkctrl_offs) -+static u32 _clkctrl_idlest(u16 inst, u16 cdoffs, u16 clkctrl_offs) - { - u32 v = am33xx_cm_read_reg(inst, clkctrl_offs); - v &= AM33XX_IDLEST_MASK; -@@ -119,7 +119,7 @@ static u32 _clkctrl_idlest(u16 inst, s16 - * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either - * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise. - */ --static bool _is_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs) -+static bool _is_module_ready(u16 inst, u16 cdoffs, u16 clkctrl_offs) - { - u32 v; - -@@ -138,7 +138,7 @@ static bool _is_module_ready(u16 inst, s - * @c must be the unshifted value for CLKTRCTRL - i.e., this function - * will handle the shift itself. - */ --static void _clktrctrl_write(u8 c, s16 inst, u16 cdoffs) -+static void _clktrctrl_write(u8 c, u16 inst, u16 cdoffs) - { - u32 v; - -@@ -158,7 +158,7 @@ static void _clktrctrl_write(u8 c, s16 i - * Returns true if the clockdomain referred to by (@inst, @cdoffs) - * is in hardware-supervised idle mode, or 0 otherwise. - */ --bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs) -+bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs) - { - u32 v; - -@@ -177,7 +177,7 @@ bool am33xx_cm_is_clkdm_in_hwsup(s16 ins - * Put a clockdomain referred to by (@inst, @cdoffs) into - * hardware-supervised idle mode. No return value. - */ --void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs) -+void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs) - { - _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs); - } -@@ -191,7 +191,7 @@ void am33xx_cm_clkdm_enable_hwsup(s16 in - * software-supervised idle mode, i.e., controlled manually by the - * Linux OMAP clockdomain code. No return value. - */ --void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs) -+void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs) - { - _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs); - } -@@ -204,7 +204,7 @@ void am33xx_cm_clkdm_disable_hwsup(s16 i - * Put a clockdomain referred to by (@inst, @cdoffs) into idle - * No return value. - */ --void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs) -+void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs) - { - _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs); - } -@@ -217,7 +217,7 @@ void am33xx_cm_clkdm_force_sleep(s16 ins - * Take a clockdomain referred to by (@inst, @cdoffs) out of idle, - * waking it up. No return value. - */ --void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs) -+void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs) - { - _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs); - } -@@ -237,7 +237,7 @@ void am33xx_cm_clkdm_force_wakeup(s16 in - * sysconfig cannot be accessed and will probably lead to an "imprecise - * external abort" - */ --int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs) -+int am33xx_cm_wait_module_ready(u16 inst, u16 cdoffs, u16 clkctrl_offs) - { - int i = 0; - -@@ -258,7 +258,7 @@ int am33xx_cm_wait_module_ready(u16 inst - * like reset assertion or parent clock de-activation must wait the - * module to be fully disabled. - */ --int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, u16 clkctrl_offs) -+int am33xx_cm_wait_module_idle(u16 inst, u16 cdoffs, u16 clkctrl_offs) - { - int i = 0; - -@@ -281,7 +281,7 @@ int am33xx_cm_wait_module_idle(u16 inst, - * - * No return value. - */ --void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, u16 clkctrl_offs) -+void am33xx_cm_module_enable(u8 mode, u16 inst, u16 cdoffs, u16 clkctrl_offs) - { - u32 v; - -@@ -299,7 +299,7 @@ void am33xx_cm_module_enable(u8 mode, u1 - * - * No return value. - */ --void am33xx_cm_module_disable(u16 inst, s16 cdoffs, u16 clkctrl_offs) -+void am33xx_cm_module_disable(u16 inst, u16 cdoffs, u16 clkctrl_offs) - { - u32 v; - ---- a/arch/arm/mach-omap2/cm33xx.h -+++ b/arch/arm/mach-omap2/cm33xx.h -@@ -377,36 +377,36 @@ - - - #ifndef __ASSEMBLER__ --extern bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs); --extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs); --extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs); --extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs); --extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs); -+extern bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs); -+extern void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs); -+extern void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs); -+extern void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs); -+extern void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs); - --#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) --extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, -+#ifdef CONFIG_SOC_AM33XX -+extern int am33xx_cm_wait_module_idle(u16 inst, u16 cdoffs, - u16 clkctrl_offs); --extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, -+extern void am33xx_cm_module_enable(u8 mode, u16 inst, u16 cdoffs, - u16 clkctrl_offs); --extern void am33xx_cm_module_disable(u16 inst, s16 cdoffs, -+extern void am33xx_cm_module_disable(u16 inst, u16 cdoffs, - u16 clkctrl_offs); --extern int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, -+extern int am33xx_cm_wait_module_ready(u16 inst, u16 cdoffs, - u16 clkctrl_offs); - #else --static inline int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, -+static inline int am33xx_cm_wait_module_idle(u16 inst, u16 cdoffs, - u16 clkctrl_offs) - { - return 0; - } --static inline void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, -+static inline void am33xx_cm_module_enable(u8 mode, u16 inst, u16 cdoffs, - u16 clkctrl_offs) - { - } --static inline void am33xx_cm_module_disable(u16 inst, s16 cdoffs, -+static inline void am33xx_cm_module_disable(u16 inst, u16 cdoffs, - u16 clkctrl_offs) - { - } --static inline int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, -+static inline int am33xx_cm_wait_module_ready(u16 inst, u16 cdoffs, - u16 clkctrl_offs) - { - return 0; ---- a/arch/arm/mach-omap2/cminst44xx.c -+++ b/arch/arm/mach-omap2/cminst44xx.c -@@ -80,7 +80,7 @@ void omap_cm_base_init(void) - * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to - * bit 0. - */ --static u32 _clkctrl_idlest(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs) -+static u32 _clkctrl_idlest(u8 part, u16 inst, u16 cdoffs, u16 clkctrl_offs) - { - u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); - v &= OMAP4430_IDLEST_MASK; -@@ -98,7 +98,7 @@ static u32 _clkctrl_idlest(u8 part, u16 - * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either - * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise. - */ --static bool _is_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs) -+static bool _is_module_ready(u8 part, u16 inst, u16 cdoffs, u16 clkctrl_offs) - { - u32 v; - -@@ -111,7 +111,7 @@ static bool _is_module_ready(u8 part, u1 - /* Public functions */ - - /* Read a register in a CM instance */ --u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx) -+u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx) - { - BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || - part == OMAP4430_INVALID_PRCM_PARTITION || -@@ -120,7 +120,7 @@ u32 omap4_cminst_read_inst_reg(u8 part, - } - - /* Write into a register in a CM instance */ --void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx) -+void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx) - { - BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || - part == OMAP4430_INVALID_PRCM_PARTITION || -@@ -152,7 +152,7 @@ u32 omap4_cminst_clear_inst_reg_bits(u32 - return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx); - } - --u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask) -+u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, u16 idx, u32 mask) - { - u32 v; - -@@ -177,7 +177,7 @@ u32 omap4_cminst_read_inst_reg_bits(u8 p - * @c must be the unshifted value for CLKTRCTRL - i.e., this function - * will handle the shift itself. - */ --static void _clktrctrl_write(u8 c, u8 part, s16 inst, u16 cdoffs) -+static void _clktrctrl_write(u8 c, u8 part, u16 inst, u16 cdoffs) - { - u32 v; - -@@ -196,7 +196,7 @@ static void _clktrctrl_write(u8 c, u8 pa - * Returns true if the clockdomain referred to by (@part, @inst, @cdoffs) - * is in hardware-supervised idle mode, or 0 otherwise. - */ --bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs) -+bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs) - { - u32 v; - -@@ -216,7 +216,7 @@ bool omap4_cminst_is_clkdm_in_hwsup(u8 p - * Put a clockdomain referred to by (@part, @inst, @cdoffs) into - * hardware-supervised idle mode. No return value. - */ --void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs) -+void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs) - { - _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs); - } -@@ -231,7 +231,7 @@ void omap4_cminst_clkdm_enable_hwsup(u8 - * software-supervised idle mode, i.e., controlled manually by the - * Linux OMAP clockdomain code. No return value. - */ --void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs) -+void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs) - { - _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs); - } -@@ -245,7 +245,7 @@ void omap4_cminst_clkdm_disable_hwsup(u8 - * Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle, - * waking it up. No return value. - */ --void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs) -+void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs) - { - _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs); - } -@@ -266,7 +266,7 @@ void omap4_cminst_clkdm_force_wakeup(u8 - * sysconfig cannot be accessed and will probably lead to an "imprecise - * external abort" - */ --int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, -+int omap4_cminst_wait_module_ready(u8 part, u16 inst, u16 cdoffs, - u16 clkctrl_offs) - { - int i = 0; -@@ -292,7 +292,8 @@ int omap4_cminst_wait_module_ready(u8 pa - * like reset assertion or parent clock de-activation must wait the - * module to be fully disabled. - */ --int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs) -+int omap4_cminst_wait_module_idle(u8 part, u16 inst, -+ u16 cdoffs, u16 clkctrl_offs) - { - int i = 0; - -@@ -316,7 +317,7 @@ int omap4_cminst_wait_module_idle(u8 par - * - * No return value. - */ --void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs, -+void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, u16 cdoffs, - u16 clkctrl_offs) - { - u32 v; -@@ -336,7 +337,7 @@ void omap4_cminst_module_enable(u8 mode, - * - * No return value. - */ --void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs, -+void omap4_cminst_module_disable(u8 part, u16 inst, u16 cdoffs, - u16 clkctrl_offs) - { - u32 v; -@@ -479,6 +480,15 @@ struct clkdm_ops omap4_clkdm_operations - .clkdm_sleep = omap4_clkdm_sleep, - .clkdm_wakeup = omap4_clkdm_wakeup, - .clkdm_allow_idle = omap4_clkdm_allow_idle, -+ .clkdm_deny_idle = omap4_clkdm_deny_idle, -+ .clkdm_clk_enable = omap4_clkdm_clk_enable, -+ .clkdm_clk_disable = omap4_clkdm_clk_disable, -+}; -+ -+struct clkdm_ops am43xx_clkdm_operations = { -+ .clkdm_sleep = omap4_clkdm_sleep, -+ .clkdm_wakeup = omap4_clkdm_wakeup, -+ .clkdm_allow_idle = omap4_clkdm_allow_idle, - .clkdm_deny_idle = omap4_clkdm_deny_idle, - .clkdm_clk_enable = omap4_clkdm_clk_enable, - .clkdm_clk_disable = omap4_clkdm_clk_disable, ---- a/arch/arm/mach-omap2/cminst44xx.h -+++ b/arch/arm/mach-omap2/cminst44xx.h -@@ -11,31 +11,32 @@ - #ifndef __ARCH_ASM_MACH_OMAP2_CMINST44XX_H - #define __ARCH_ASM_MACH_OMAP2_CMINST44XX_H - --extern bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs); --extern void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs); --extern void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs); --extern void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs); --extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs); --extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs); --extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, -+extern bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs); -+extern void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs); -+extern void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs); -+extern void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs); -+extern void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs); -+extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, -+ u16 cdoffs, u16 clkctrl_offs); -+extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, u16 cdoffs, - u16 clkctrl_offs); --extern void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs, -+extern void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, u16 cdoffs, - u16 clkctrl_offs); --extern void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs, -+extern void omap4_cminst_module_disable(u8 part, u16 inst, u16 cdoffs, - u16 clkctrl_offs); - /* - * In an ideal world, we would not export these low-level functions, - * but this will probably take some time to fix properly - */ --extern u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx); --extern void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx); -+extern u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx); -+extern void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx); - extern u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, - s16 inst, s16 idx); - extern u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, s16 inst, - s16 idx); - extern u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst, - s16 idx); --extern u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, -+extern u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, u16 idx, - u32 mask); - - extern void omap_cm_base_init(void); ---- a/arch/arm/mach-omap2/common.c -+++ b/arch/arm/mach-omap2/common.c -@@ -15,10 +15,14 @@ - #include - #include - #include -+#include -+#include - - #include "common.h" - #include "omap-secure.h" - -+#define AM33XX_DRAM_SYNC_VA 0xfe600000 -+ - /* - * Stub function for OMAP2 so that common files - * continue to build when custom builds are used -@@ -34,3 +38,31 @@ void __init omap_reserve(void) - omap_secure_ram_reserve_memblock(); - omap_barrier_reserve_memblock(); - } -+ -+static phys_addr_t am33xx_paddr; -+static u32 am33xx_size; -+ -+/* Steal one page physical memory for uncached read DeepSleep */ -+void __init am33xx_reserve(void) -+{ -+ am33xx_size = ALIGN(PAGE_SIZE, SZ_1M); -+ am33xx_paddr = arm_memblock_steal(am33xx_size, SZ_1M); -+ -+ omap_reserve(); -+} -+ -+void __iomem *am33xx_dram_sync; -+ -+void __init am33xx_dram_sync_init(void) -+{ -+ struct map_desc dram_io_desc[1]; -+ -+ dram_io_desc[0].virtual = AM33XX_DRAM_SYNC_VA; -+ dram_io_desc[0].pfn = __phys_to_pfn(am33xx_paddr); -+ dram_io_desc[0].length = am33xx_size; -+ dram_io_desc[0].type = MT_MEMORY_SO; -+ -+ iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc)); -+ -+ am33xx_dram_sync = (void __iomem *) dram_io_desc[0].virtual; -+} ---- a/arch/arm/mach-omap2/common.h -+++ b/arch/arm/mach-omap2/common.h -@@ -60,7 +60,7 @@ static inline int omap3_pm_init(void) - } - #endif - --#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP4) -+#if defined(CONFIG_PM) && (defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)) - int omap4_pm_init(void); - #else - static inline int omap4_pm_init(void) -@@ -69,6 +69,15 @@ static inline int omap4_pm_init(void) - } - #endif - -+#if defined(CONFIG_PM) && defined(CONFIG_SOC_AM33XX) -+int am33xx_pm_init(void); -+#else -+static inline int am33xx_pm_init(void) -+{ -+ return 0; -+} -+#endif -+ - #ifdef CONFIG_OMAP_MUX - int omap_mux_late_init(void); - #else -@@ -107,10 +116,14 @@ void omap2430_init_late(void); - void omap3430_init_late(void); - void omap35xx_init_late(void); - void omap3630_init_late(void); -+void am33xx_init_late(void); - void am35xx_init_late(void); - void ti81xx_init_late(void); -+void am33xx_init_late(void); -+void omap5_init_late(void); - int omap2_common_pm_late_init(void); - void dra7xx_init_early(void); -+void dra7xx_init_late(void); - - #ifdef CONFIG_SOC_BUS - void omap_soc_device_init(void); -@@ -136,6 +149,14 @@ static inline void am33xx_restart(enum r - } - #endif - -+#ifdef CONFIG_SOC_AM43XX -+void am43xx_restart(enum reboot_mode mode, const char *cmd); -+#else -+static inline void am43xx_restart(enum reboot_mode mode, const char *cmd) -+{ -+} -+#endif -+ - #ifdef CONFIG_ARCH_OMAP3 - void omap3xxx_restart(enum reboot_mode mode, const char *cmd); - #else -@@ -152,6 +173,14 @@ static inline void omap44xx_restart(enum - } - #endif - -+#if defined(CONFIG_SUSPEND) -+void omap2_common_suspend_init(void); -+#else -+inline void omap2_common_suspend_init(void); -+{ -+} -+#endif -+ - /* This gets called from mach-omap2/io.c, do not call this */ - void __init omap2_set_globals_tap(u32 class, void __iomem *tap); - -@@ -165,7 +194,6 @@ void __init ti81xx_map_io(void); - - /* omap_barriers_init() is OMAP4 only */ - void omap_barriers_init(void); -- - /** - * omap_test_timeout - busy-loop, testing a condition - * @cond: condition to test until it evaluates to true -@@ -259,6 +287,8 @@ extern int omap4_enter_lowpower(unsigned - extern int omap4_finish_suspend(unsigned long cpu_state); - extern void omap4_cpu_resume(void); - extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state); -+extern int omap5_finish_suspend(unsigned long cpu_state); -+extern void omap5_cpu_resume(void); - #else - static inline int omap4_enter_lowpower(unsigned int cpu, - unsigned int power_state) -@@ -286,6 +316,14 @@ static inline int omap4_finish_suspend(u - static inline void omap4_cpu_resume(void) - {} - -+static inline int omap5_finish_suspend(unsigned long cpu_state) -+{ -+ return 0; -+} -+ -+static inline void omap5_cpu_resume(void) -+{} -+ - #endif - - struct omap_sdrc_params; -@@ -295,11 +333,17 @@ struct omap2_hsmmc_info; - extern int omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers); - extern void omap_reserve(void); - -+extern void am33xx_reserve(void); -+extern void am33xx_dram_sync_init(void); -+extern void __iomem *am33xx_dram_sync; -+ - struct omap_hwmod; - extern int omap_dss_reset(struct omap_hwmod *); - - /* SoC specific clock initializer */ - extern int (*omap_clk_init)(void); - -+int __init omapdss_init_of(void); -+ - #endif /* __ASSEMBLER__ */ - #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */ ---- a/arch/arm/mach-omap2/devices.c -+++ b/arch/arm/mach-omap2/devices.c -@@ -37,6 +37,7 @@ - #include "mux.h" - #include "control.h" - #include "devices.h" -+#include "display.h" - - #define L3_MODULES_MAX_LEN 12 - #define L3_MODULES 3 -@@ -466,13 +467,13 @@ static struct platform_device omap_vout_ - .resource = &omap_vout_resource[0], - .id = -1, - }; --static void omap_init_vout(void) -+ -+int __init omap_init_vout(void) - { -- if (platform_device_register(&omap_vout_device) < 0) -- printk(KERN_ERR "Unable to register OMAP-VOUT device\n"); -+ return platform_device_register(&omap_vout_device); - } - #else --static inline void omap_init_vout(void) {} -+int __init omap_init_vout(void) { return 0; } - #endif - - #if IS_ENABLED(CONFIG_WL12XX) -@@ -524,9 +525,9 @@ static int __init omap2_init_devices(voi - omap_init_audio(); - omap_init_camera(); - omap_init_hdmi_audio(); -- omap_init_mbox(); - /* If dtb is there, the devices will be created dynamically */ - if (!of_have_populated_dt()) { -+ omap_init_mbox(); - omap_init_mcspi(); - omap_init_sham(); - omap_init_aes(); -@@ -536,7 +537,6 @@ static int __init omap2_init_devices(voi - omap_init_wl12xx_of(); - } - omap_init_sti(); -- omap_init_vout(); - - return 0; - } ---- a/arch/arm/mach-omap2/display.c -+++ b/arch/arm/mach-omap2/display.c -@@ -23,6 +23,8 @@ - #include - #include - #include -+#include -+#include - - #include