From: York Sun <yorksun@freescale.com>
Date: Fri, 4 Feb 2011 21:57:59 +0000 (-0800)
Subject: powerpc/85xx: Update fixed DDR3 timing table for P4080DS
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=dea8bd627c26bb2d17d7079b374352301af4a028;p=project%2Fbcm63xx%2Fu-boot.git

powerpc/85xx: Update fixed DDR3 timing table for P4080DS

Most of time U-boot doesn't get an exact clock number. For example, clock
900MHz may be detected as 899.99MHz. 800MHz could be 799.99MHz. Update the
table to align the desired clocks in the middle.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---

diff --git a/board/freescale/corenet_ds/p4080ds_ddr.c b/board/freescale/corenet_ds/p4080ds_ddr.c
index ccb9da832c..844e1d736a 100644
--- a/board/freescale/corenet_ds/p4080ds_ddr.c
+++ b/board/freescale/corenet_ds/p4080ds_ddr.c
@@ -334,17 +334,17 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_1200_2nd = {
 };
 
 fixed_ddr_parm_t fixed_ddr_parm_0[] = {
-	{800, 900, &ddr_cfg_regs_800},
-	{900, 1000, &ddr_cfg_regs_900},
-	{1000, 1200, &ddr_cfg_regs_1000},
-	{1200, 1300, &ddr_cfg_regs_1200},
+	{750, 850, &ddr_cfg_regs_800},
+	{850, 950, &ddr_cfg_regs_900},
+	{950, 1050, &ddr_cfg_regs_1000},
+	{1050, 1250, &ddr_cfg_regs_1200},
 	{0, 0, NULL}
 };
 
 fixed_ddr_parm_t fixed_ddr_parm_1[] = {
-	{800, 900, &ddr_cfg_regs_800_2nd},
-	{900, 1000, &ddr_cfg_regs_900_2nd},
-	{1000, 1200, &ddr_cfg_regs_1000_2nd},
-	{1200, 1300, &ddr_cfg_regs_1200_2nd},
+	{750, 850, &ddr_cfg_regs_800_2nd},
+	{850, 950, &ddr_cfg_regs_900_2nd},
+	{950, 1050, &ddr_cfg_regs_1000_2nd},
+	{1050, 1250, &ddr_cfg_regs_1200_2nd},
 	{0, 0, NULL}
 };