From: Álvaro Fernández Rojas Date: Tue, 23 Feb 2021 14:14:41 +0000 (+0100) Subject: bmips: rename upstream patches X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=de3066bef705bd400a05e92305e634939d46f5a1;p=openwrt%2Fstaging%2Fneocturne.git bmips: rename upstream patches These patches were applied in linux v5.11, not v5.12. Signed-off-by: Álvaro Fernández Rojas --- diff --git a/target/linux/bmips/patches-5.10/001-v5.11-mips-bmips-select-ARCH_HAS_RESET_CONTROLLER.patch b/target/linux/bmips/patches-5.10/001-v5.11-mips-bmips-select-ARCH_HAS_RESET_CONTROLLER.patch new file mode 100644 index 0000000000..b8601ec1bf --- /dev/null +++ b/target/linux/bmips/patches-5.10/001-v5.11-mips-bmips-select-ARCH_HAS_RESET_CONTROLLER.patch @@ -0,0 +1,27 @@ +From 29906e1aac11bf9907e26608216dc7970e73a70e Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= +Date: Wed, 17 Jun 2020 12:50:33 +0200 +Subject: [PATCH 1/9] mips: bmips: select ARCH_HAS_RESET_CONTROLLER +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This allows to add reset controllers support. + +Signed-off-by: Álvaro Fernández Rojas +Acked-by: Florian Fainelli +Signed-off-by: Thomas Bogendoerfer +--- + arch/mips/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -249,6 +249,7 @@ config ATH79 + + config BMIPS_GENERIC + bool "Broadcom Generic BMIPS kernel" ++ select ARCH_HAS_RESET_CONTROLLER + select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL + select ARCH_HAS_PHYS_TO_DMA + select BOOT_RAW diff --git a/target/linux/bmips/patches-5.10/001-v5.12-mips-bmips-select-ARCH_HAS_RESET_CONTROLLER.patch b/target/linux/bmips/patches-5.10/001-v5.12-mips-bmips-select-ARCH_HAS_RESET_CONTROLLER.patch deleted file mode 100644 index b8601ec1bf..0000000000 --- a/target/linux/bmips/patches-5.10/001-v5.12-mips-bmips-select-ARCH_HAS_RESET_CONTROLLER.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 29906e1aac11bf9907e26608216dc7970e73a70e Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= -Date: Wed, 17 Jun 2020 12:50:33 +0200 -Subject: [PATCH 1/9] mips: bmips: select ARCH_HAS_RESET_CONTROLLER -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This allows to add reset controllers support. - -Signed-off-by: Álvaro Fernández Rojas -Acked-by: Florian Fainelli -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/Kconfig | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -249,6 +249,7 @@ config ATH79 - - config BMIPS_GENERIC - bool "Broadcom Generic BMIPS kernel" -+ select ARCH_HAS_RESET_CONTROLLER - select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL - select ARCH_HAS_PHYS_TO_DMA - select BOOT_RAW diff --git a/target/linux/bmips/patches-5.10/002-v5.11-dt-bindings-reset-add-BCM6345-reset-controller-bindi.patch b/target/linux/bmips/patches-5.10/002-v5.11-dt-bindings-reset-add-BCM6345-reset-controller-bindi.patch new file mode 100644 index 0000000000..95eb299576 --- /dev/null +++ b/target/linux/bmips/patches-5.10/002-v5.11-dt-bindings-reset-add-BCM6345-reset-controller-bindi.patch @@ -0,0 +1,59 @@ +From 10c1e714a68b45b124157aa02d80abe244a2a61a Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= +Date: Wed, 17 Jun 2020 12:50:34 +0200 +Subject: [PATCH 2/9] dt-bindings: reset: add BCM6345 reset controller bindings +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add device tree binding documentation for BCM6345 reset controller. + +Signed-off-by: Álvaro Fernández Rojas +Reviewed-by: Florian Fainelli +Reviewed-by: Rob Herring +Signed-off-by: Thomas Bogendoerfer +--- + .../bindings/reset/brcm,bcm6345-reset.yaml | 37 +++++++++++++++++++ + 1 file changed, 37 insertions(+) + create mode 100644 Documentation/devicetree/bindings/reset/brcm,bcm6345-reset.yaml + +--- /dev/null ++++ b/Documentation/devicetree/bindings/reset/brcm,bcm6345-reset.yaml +@@ -0,0 +1,37 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: "http://devicetree.org/schemas/reset/brcm,bcm6345-reset.yaml#" ++$schema: "http://devicetree.org/meta-schemas/core.yaml#" ++ ++title: BCM6345 reset controller ++ ++description: This document describes the BCM6345 reset controller. ++ ++maintainers: ++ - Álvaro Fernández Rojas ++ ++properties: ++ compatible: ++ const: brcm,bcm6345-reset ++ ++ reg: ++ maxItems: 1 ++ ++ "#reset-cells": ++ const: 1 ++ ++required: ++ - compatible ++ - reg ++ - "#reset-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ reset-controller@10000010 { ++ compatible = "brcm,bcm6345-reset"; ++ reg = <0x10000010 0x4>; ++ #reset-cells = <1>; ++ }; diff --git a/target/linux/bmips/patches-5.10/002-v5.12-dt-bindings-reset-add-BCM6345-reset-controller-bindi.patch b/target/linux/bmips/patches-5.10/002-v5.12-dt-bindings-reset-add-BCM6345-reset-controller-bindi.patch deleted file mode 100644 index 95eb299576..0000000000 --- a/target/linux/bmips/patches-5.10/002-v5.12-dt-bindings-reset-add-BCM6345-reset-controller-bindi.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 10c1e714a68b45b124157aa02d80abe244a2a61a Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= -Date: Wed, 17 Jun 2020 12:50:34 +0200 -Subject: [PATCH 2/9] dt-bindings: reset: add BCM6345 reset controller bindings -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add device tree binding documentation for BCM6345 reset controller. - -Signed-off-by: Álvaro Fernández Rojas -Reviewed-by: Florian Fainelli -Reviewed-by: Rob Herring -Signed-off-by: Thomas Bogendoerfer ---- - .../bindings/reset/brcm,bcm6345-reset.yaml | 37 +++++++++++++++++++ - 1 file changed, 37 insertions(+) - create mode 100644 Documentation/devicetree/bindings/reset/brcm,bcm6345-reset.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/reset/brcm,bcm6345-reset.yaml -@@ -0,0 +1,37 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: "http://devicetree.org/schemas/reset/brcm,bcm6345-reset.yaml#" -+$schema: "http://devicetree.org/meta-schemas/core.yaml#" -+ -+title: BCM6345 reset controller -+ -+description: This document describes the BCM6345 reset controller. -+ -+maintainers: -+ - Álvaro Fernández Rojas -+ -+properties: -+ compatible: -+ const: brcm,bcm6345-reset -+ -+ reg: -+ maxItems: 1 -+ -+ "#reset-cells": -+ const: 1 -+ -+required: -+ - compatible -+ - reg -+ - "#reset-cells" -+ -+additionalProperties: false -+ -+examples: -+ - | -+ reset-controller@10000010 { -+ compatible = "brcm,bcm6345-reset"; -+ reg = <0x10000010 0x4>; -+ #reset-cells = <1>; -+ }; diff --git a/target/linux/bmips/patches-5.10/003-v5.11-reset-add-BCM6345-reset-controller-driver.patch b/target/linux/bmips/patches-5.10/003-v5.11-reset-add-BCM6345-reset-controller-driver.patch new file mode 100644 index 0000000000..39b607d5bd --- /dev/null +++ b/target/linux/bmips/patches-5.10/003-v5.11-reset-add-BCM6345-reset-controller-driver.patch @@ -0,0 +1,186 @@ +From aac025437f14c1647dc6054b95daeebed34f6971 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= +Date: Wed, 17 Jun 2020 12:50:35 +0200 +Subject: [PATCH 3/9] reset: add BCM6345 reset controller driver +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add support for resetting blocks through the Linux reset controller +subsystem for BCM63xx SoCs. + +Signed-off-by: Álvaro Fernández Rojas +Reviewed-by: Florian Fainelli +Reviewed-by: Philipp Zabel +Signed-off-by: Thomas Bogendoerfer +--- + drivers/reset/Kconfig | 7 ++ + drivers/reset/Makefile | 1 + + drivers/reset/reset-bcm6345.c | 135 ++++++++++++++++++++++++++++++++++ + 3 files changed, 143 insertions(+) + create mode 100644 drivers/reset/reset-bcm6345.c + +--- a/drivers/reset/Kconfig ++++ b/drivers/reset/Kconfig +@@ -35,6 +35,13 @@ config RESET_AXS10X + help + This enables the reset controller driver for AXS10x. + ++config RESET_BCM6345 ++ bool "BCM6345 Reset Controller" ++ depends on BMIPS_GENERIC || COMPILE_TEST ++ default BMIPS_GENERIC ++ help ++ This enables the reset controller driver for BCM6345 SoCs. ++ + config RESET_BERLIN + bool "Berlin Reset Driver" if COMPILE_TEST + default ARCH_BERLIN +--- a/drivers/reset/Makefile ++++ b/drivers/reset/Makefile +@@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_TEGRA) += tegra/ + obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o + obj-$(CONFIG_RESET_ATH79) += reset-ath79.o + obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o ++obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o + obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o + obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o + obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o +--- /dev/null ++++ b/drivers/reset/reset-bcm6345.c +@@ -0,0 +1,135 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * BCM6345 Reset Controller Driver ++ * ++ * Copyright (C) 2020 Álvaro Fernández Rojas ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define BCM6345_RESET_NUM 32 ++#define BCM6345_RESET_SLEEP_MIN_US 10000 ++#define BCM6345_RESET_SLEEP_MAX_US 20000 ++ ++struct bcm6345_reset { ++ struct reset_controller_dev rcdev; ++ void __iomem *base; ++ spinlock_t lock; ++}; ++ ++static inline struct bcm6345_reset * ++to_bcm6345_reset(struct reset_controller_dev *rcdev) ++{ ++ return container_of(rcdev, struct bcm6345_reset, rcdev); ++} ++ ++static int bcm6345_reset_update(struct reset_controller_dev *rcdev, ++ unsigned long id, bool assert) ++{ ++ struct bcm6345_reset *bcm6345_reset = to_bcm6345_reset(rcdev); ++ unsigned long flags; ++ uint32_t val; ++ ++ spin_lock_irqsave(&bcm6345_reset->lock, flags); ++ val = __raw_readl(bcm6345_reset->base); ++ if (assert) ++ val &= ~BIT(id); ++ else ++ val |= BIT(id); ++ __raw_writel(val, bcm6345_reset->base); ++ spin_unlock_irqrestore(&bcm6345_reset->lock, flags); ++ ++ return 0; ++} ++ ++static int bcm6345_reset_assert(struct reset_controller_dev *rcdev, ++ unsigned long id) ++{ ++ return bcm6345_reset_update(rcdev, id, true); ++} ++ ++static int bcm6345_reset_deassert(struct reset_controller_dev *rcdev, ++ unsigned long id) ++{ ++ return bcm6345_reset_update(rcdev, id, false); ++} ++ ++static int bcm6345_reset_reset(struct reset_controller_dev *rcdev, ++ unsigned long id) ++{ ++ bcm6345_reset_update(rcdev, id, true); ++ usleep_range(BCM6345_RESET_SLEEP_MIN_US, ++ BCM6345_RESET_SLEEP_MAX_US); ++ ++ bcm6345_reset_update(rcdev, id, false); ++ /* ++ * Ensure component is taken out reset state by sleeping also after ++ * deasserting the reset. Otherwise, the component may not be ready ++ * for operation. ++ */ ++ usleep_range(BCM6345_RESET_SLEEP_MIN_US, ++ BCM6345_RESET_SLEEP_MAX_US); ++ ++ return 0; ++} ++ ++static int bcm6345_reset_status(struct reset_controller_dev *rcdev, ++ unsigned long id) ++{ ++ struct bcm6345_reset *bcm6345_reset = to_bcm6345_reset(rcdev); ++ ++ return !(__raw_readl(bcm6345_reset->base) & BIT(id)); ++} ++ ++static struct reset_control_ops bcm6345_reset_ops = { ++ .assert = bcm6345_reset_assert, ++ .deassert = bcm6345_reset_deassert, ++ .reset = bcm6345_reset_reset, ++ .status = bcm6345_reset_status, ++}; ++ ++static int bcm6345_reset_probe(struct platform_device *pdev) ++{ ++ struct bcm6345_reset *bcm6345_reset; ++ ++ bcm6345_reset = devm_kzalloc(&pdev->dev, ++ sizeof(*bcm6345_reset), GFP_KERNEL); ++ if (!bcm6345_reset) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, bcm6345_reset); ++ ++ bcm6345_reset->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(bcm6345_reset->base)) ++ return PTR_ERR(bcm6345_reset->base); ++ ++ spin_lock_init(&bcm6345_reset->lock); ++ bcm6345_reset->rcdev.ops = &bcm6345_reset_ops; ++ bcm6345_reset->rcdev.owner = THIS_MODULE; ++ bcm6345_reset->rcdev.of_node = pdev->dev.of_node; ++ bcm6345_reset->rcdev.of_reset_n_cells = 1; ++ bcm6345_reset->rcdev.nr_resets = BCM6345_RESET_NUM; ++ ++ return devm_reset_controller_register(&pdev->dev, ++ &bcm6345_reset->rcdev); ++} ++ ++static const struct of_device_id bcm6345_reset_of_match[] = { ++ { .compatible = "brcm,bcm6345-reset" }, ++ { /* sentinel */ }, ++}; ++ ++static struct platform_driver bcm6345_reset_driver = { ++ .probe = bcm6345_reset_probe, ++ .driver = { ++ .name = "bcm6345-reset", ++ .of_match_table = bcm6345_reset_of_match, ++ .suppress_bind_attrs = true, ++ }, ++}; ++builtin_platform_driver(bcm6345_reset_driver); diff --git a/target/linux/bmips/patches-5.10/003-v5.12-reset-add-BCM6345-reset-controller-driver.patch b/target/linux/bmips/patches-5.10/003-v5.12-reset-add-BCM6345-reset-controller-driver.patch deleted file mode 100644 index 39b607d5bd..0000000000 --- a/target/linux/bmips/patches-5.10/003-v5.12-reset-add-BCM6345-reset-controller-driver.patch +++ /dev/null @@ -1,186 +0,0 @@ -From aac025437f14c1647dc6054b95daeebed34f6971 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= -Date: Wed, 17 Jun 2020 12:50:35 +0200 -Subject: [PATCH 3/9] reset: add BCM6345 reset controller driver -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add support for resetting blocks through the Linux reset controller -subsystem for BCM63xx SoCs. - -Signed-off-by: Álvaro Fernández Rojas -Reviewed-by: Florian Fainelli -Reviewed-by: Philipp Zabel -Signed-off-by: Thomas Bogendoerfer ---- - drivers/reset/Kconfig | 7 ++ - drivers/reset/Makefile | 1 + - drivers/reset/reset-bcm6345.c | 135 ++++++++++++++++++++++++++++++++++ - 3 files changed, 143 insertions(+) - create mode 100644 drivers/reset/reset-bcm6345.c - ---- a/drivers/reset/Kconfig -+++ b/drivers/reset/Kconfig -@@ -35,6 +35,13 @@ config RESET_AXS10X - help - This enables the reset controller driver for AXS10x. - -+config RESET_BCM6345 -+ bool "BCM6345 Reset Controller" -+ depends on BMIPS_GENERIC || COMPILE_TEST -+ default BMIPS_GENERIC -+ help -+ This enables the reset controller driver for BCM6345 SoCs. -+ - config RESET_BERLIN - bool "Berlin Reset Driver" if COMPILE_TEST - default ARCH_BERLIN ---- a/drivers/reset/Makefile -+++ b/drivers/reset/Makefile -@@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_TEGRA) += tegra/ - obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o - obj-$(CONFIG_RESET_ATH79) += reset-ath79.o - obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o -+obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o - obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o - obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o - obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o ---- /dev/null -+++ b/drivers/reset/reset-bcm6345.c -@@ -0,0 +1,135 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+/* -+ * BCM6345 Reset Controller Driver -+ * -+ * Copyright (C) 2020 Álvaro Fernández Rojas -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define BCM6345_RESET_NUM 32 -+#define BCM6345_RESET_SLEEP_MIN_US 10000 -+#define BCM6345_RESET_SLEEP_MAX_US 20000 -+ -+struct bcm6345_reset { -+ struct reset_controller_dev rcdev; -+ void __iomem *base; -+ spinlock_t lock; -+}; -+ -+static inline struct bcm6345_reset * -+to_bcm6345_reset(struct reset_controller_dev *rcdev) -+{ -+ return container_of(rcdev, struct bcm6345_reset, rcdev); -+} -+ -+static int bcm6345_reset_update(struct reset_controller_dev *rcdev, -+ unsigned long id, bool assert) -+{ -+ struct bcm6345_reset *bcm6345_reset = to_bcm6345_reset(rcdev); -+ unsigned long flags; -+ uint32_t val; -+ -+ spin_lock_irqsave(&bcm6345_reset->lock, flags); -+ val = __raw_readl(bcm6345_reset->base); -+ if (assert) -+ val &= ~BIT(id); -+ else -+ val |= BIT(id); -+ __raw_writel(val, bcm6345_reset->base); -+ spin_unlock_irqrestore(&bcm6345_reset->lock, flags); -+ -+ return 0; -+} -+ -+static int bcm6345_reset_assert(struct reset_controller_dev *rcdev, -+ unsigned long id) -+{ -+ return bcm6345_reset_update(rcdev, id, true); -+} -+ -+static int bcm6345_reset_deassert(struct reset_controller_dev *rcdev, -+ unsigned long id) -+{ -+ return bcm6345_reset_update(rcdev, id, false); -+} -+ -+static int bcm6345_reset_reset(struct reset_controller_dev *rcdev, -+ unsigned long id) -+{ -+ bcm6345_reset_update(rcdev, id, true); -+ usleep_range(BCM6345_RESET_SLEEP_MIN_US, -+ BCM6345_RESET_SLEEP_MAX_US); -+ -+ bcm6345_reset_update(rcdev, id, false); -+ /* -+ * Ensure component is taken out reset state by sleeping also after -+ * deasserting the reset. Otherwise, the component may not be ready -+ * for operation. -+ */ -+ usleep_range(BCM6345_RESET_SLEEP_MIN_US, -+ BCM6345_RESET_SLEEP_MAX_US); -+ -+ return 0; -+} -+ -+static int bcm6345_reset_status(struct reset_controller_dev *rcdev, -+ unsigned long id) -+{ -+ struct bcm6345_reset *bcm6345_reset = to_bcm6345_reset(rcdev); -+ -+ return !(__raw_readl(bcm6345_reset->base) & BIT(id)); -+} -+ -+static struct reset_control_ops bcm6345_reset_ops = { -+ .assert = bcm6345_reset_assert, -+ .deassert = bcm6345_reset_deassert, -+ .reset = bcm6345_reset_reset, -+ .status = bcm6345_reset_status, -+}; -+ -+static int bcm6345_reset_probe(struct platform_device *pdev) -+{ -+ struct bcm6345_reset *bcm6345_reset; -+ -+ bcm6345_reset = devm_kzalloc(&pdev->dev, -+ sizeof(*bcm6345_reset), GFP_KERNEL); -+ if (!bcm6345_reset) -+ return -ENOMEM; -+ -+ platform_set_drvdata(pdev, bcm6345_reset); -+ -+ bcm6345_reset->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(bcm6345_reset->base)) -+ return PTR_ERR(bcm6345_reset->base); -+ -+ spin_lock_init(&bcm6345_reset->lock); -+ bcm6345_reset->rcdev.ops = &bcm6345_reset_ops; -+ bcm6345_reset->rcdev.owner = THIS_MODULE; -+ bcm6345_reset->rcdev.of_node = pdev->dev.of_node; -+ bcm6345_reset->rcdev.of_reset_n_cells = 1; -+ bcm6345_reset->rcdev.nr_resets = BCM6345_RESET_NUM; -+ -+ return devm_reset_controller_register(&pdev->dev, -+ &bcm6345_reset->rcdev); -+} -+ -+static const struct of_device_id bcm6345_reset_of_match[] = { -+ { .compatible = "brcm,bcm6345-reset" }, -+ { /* sentinel */ }, -+}; -+ -+static struct platform_driver bcm6345_reset_driver = { -+ .probe = bcm6345_reset_probe, -+ .driver = { -+ .name = "bcm6345-reset", -+ .of_match_table = bcm6345_reset_of_match, -+ .suppress_bind_attrs = true, -+ }, -+}; -+builtin_platform_driver(bcm6345_reset_driver); diff --git a/target/linux/bmips/patches-5.10/004-v5.11-mips-bmips-dts-add-BCM6328-reset-controller-support.patch b/target/linux/bmips/patches-5.10/004-v5.11-mips-bmips-dts-add-BCM6328-reset-controller-support.patch new file mode 100644 index 0000000000..85c63f6bd1 --- /dev/null +++ b/target/linux/bmips/patches-5.10/004-v5.11-mips-bmips-dts-add-BCM6328-reset-controller-support.patch @@ -0,0 +1,56 @@ +From 83f865d7e32e40b4903b1f83537c63fc5cdf1eb8 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= +Date: Wed, 17 Jun 2020 12:50:36 +0200 +Subject: [PATCH 4/9] mips: bmips: dts: add BCM6328 reset controller support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +BCM6328 SoCs have a reset controller for certain components. + +Signed-off-by: Álvaro Fernández Rojas +Acked-by: Florian Fainelli +Reviewed-by: Rob Herring +Signed-off-by: Thomas Bogendoerfer +--- + arch/mips/boot/dts/brcm/bcm6328.dtsi | 6 ++++++ + include/dt-bindings/reset/bcm6328-reset.h | 18 ++++++++++++++++++ + 2 files changed, 24 insertions(+) + create mode 100644 include/dt-bindings/reset/bcm6328-reset.h + +--- a/arch/mips/boot/dts/brcm/bcm6328.dtsi ++++ b/arch/mips/boot/dts/brcm/bcm6328.dtsi +@@ -57,6 +57,12 @@ + #clock-cells = <1>; + }; + ++ periph_rst: reset-controller@10000010 { ++ compatible = "brcm,bcm6345-reset"; ++ reg = <0x10000010 0x4>; ++ #reset-cells = <1>; ++ }; ++ + periph_intc: interrupt-controller@10000020 { + compatible = "brcm,bcm6345-l1-intc"; + reg = <0x10000020 0x10>, +--- /dev/null ++++ b/include/dt-bindings/reset/bcm6328-reset.h +@@ -0,0 +1,18 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++ ++#ifndef __DT_BINDINGS_RESET_BCM6328_H ++#define __DT_BINDINGS_RESET_BCM6328_H ++ ++#define BCM6328_RST_SPI 0 ++#define BCM6328_RST_EPHY 1 ++#define BCM6328_RST_SAR 2 ++#define BCM6328_RST_ENETSW 3 ++#define BCM6328_RST_USBS 4 ++#define BCM6328_RST_USBH 5 ++#define BCM6328_RST_PCM 6 ++#define BCM6328_RST_PCIE_CORE 7 ++#define BCM6328_RST_PCIE 8 ++#define BCM6328_RST_PCIE_EXT 9 ++#define BCM6328_RST_PCIE_HARD 10 ++ ++#endif /* __DT_BINDINGS_RESET_BCM6328_H */ diff --git a/target/linux/bmips/patches-5.10/004-v5.12-mips-bmips-dts-add-BCM6328-reset-controller-support.patch b/target/linux/bmips/patches-5.10/004-v5.12-mips-bmips-dts-add-BCM6328-reset-controller-support.patch deleted file mode 100644 index 85c63f6bd1..0000000000 --- a/target/linux/bmips/patches-5.10/004-v5.12-mips-bmips-dts-add-BCM6328-reset-controller-support.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 83f865d7e32e40b4903b1f83537c63fc5cdf1eb8 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= -Date: Wed, 17 Jun 2020 12:50:36 +0200 -Subject: [PATCH 4/9] mips: bmips: dts: add BCM6328 reset controller support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM6328 SoCs have a reset controller for certain components. - -Signed-off-by: Álvaro Fernández Rojas -Acked-by: Florian Fainelli -Reviewed-by: Rob Herring -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/boot/dts/brcm/bcm6328.dtsi | 6 ++++++ - include/dt-bindings/reset/bcm6328-reset.h | 18 ++++++++++++++++++ - 2 files changed, 24 insertions(+) - create mode 100644 include/dt-bindings/reset/bcm6328-reset.h - ---- a/arch/mips/boot/dts/brcm/bcm6328.dtsi -+++ b/arch/mips/boot/dts/brcm/bcm6328.dtsi -@@ -57,6 +57,12 @@ - #clock-cells = <1>; - }; - -+ periph_rst: reset-controller@10000010 { -+ compatible = "brcm,bcm6345-reset"; -+ reg = <0x10000010 0x4>; -+ #reset-cells = <1>; -+ }; -+ - periph_intc: interrupt-controller@10000020 { - compatible = "brcm,bcm6345-l1-intc"; - reg = <0x10000020 0x10>, ---- /dev/null -+++ b/include/dt-bindings/reset/bcm6328-reset.h -@@ -0,0 +1,18 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+ -+#ifndef __DT_BINDINGS_RESET_BCM6328_H -+#define __DT_BINDINGS_RESET_BCM6328_H -+ -+#define BCM6328_RST_SPI 0 -+#define BCM6328_RST_EPHY 1 -+#define BCM6328_RST_SAR 2 -+#define BCM6328_RST_ENETSW 3 -+#define BCM6328_RST_USBS 4 -+#define BCM6328_RST_USBH 5 -+#define BCM6328_RST_PCM 6 -+#define BCM6328_RST_PCIE_CORE 7 -+#define BCM6328_RST_PCIE 8 -+#define BCM6328_RST_PCIE_EXT 9 -+#define BCM6328_RST_PCIE_HARD 10 -+ -+#endif /* __DT_BINDINGS_RESET_BCM6328_H */ diff --git a/target/linux/bmips/patches-5.10/005-v5.11-mips-bmips-dts-add-BCM6358-reset-controller-support.patch b/target/linux/bmips/patches-5.10/005-v5.11-mips-bmips-dts-add-BCM6358-reset-controller-support.patch new file mode 100644 index 0000000000..d350dbb190 --- /dev/null +++ b/target/linux/bmips/patches-5.10/005-v5.11-mips-bmips-dts-add-BCM6358-reset-controller-support.patch @@ -0,0 +1,53 @@ +From 8079cfba4c7b8cae900c27104b4512fa5ed1f021 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= +Date: Wed, 17 Jun 2020 12:50:37 +0200 +Subject: [PATCH 5/9] mips: bmips: dts: add BCM6358 reset controller support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +BCM6358 SoCs have a reset controller for certain components. + +Signed-off-by: Álvaro Fernández Rojas +Acked-by: Florian Fainelli +Reviewed-by: Rob Herring +Signed-off-by: Thomas Bogendoerfer +--- + arch/mips/boot/dts/brcm/bcm6358.dtsi | 6 ++++++ + include/dt-bindings/reset/bcm6358-reset.h | 15 +++++++++++++++ + 2 files changed, 21 insertions(+) + create mode 100644 include/dt-bindings/reset/bcm6358-reset.h + +--- a/arch/mips/boot/dts/brcm/bcm6358.dtsi ++++ b/arch/mips/boot/dts/brcm/bcm6358.dtsi +@@ -82,6 +82,12 @@ + interrupts = <2>, <3>; + }; + ++ periph_rst: reset-controller@fffe0034 { ++ compatible = "brcm,bcm6345-reset"; ++ reg = <0xfffe0034 0x4>; ++ #reset-cells = <1>; ++ }; ++ + leds0: led-controller@fffe00d0 { + #address-cells = <1>; + #size-cells = <0>; +--- /dev/null ++++ b/include/dt-bindings/reset/bcm6358-reset.h +@@ -0,0 +1,15 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++ ++#ifndef __DT_BINDINGS_RESET_BCM6358_H ++#define __DT_BINDINGS_RESET_BCM6358_H ++ ++#define BCM6358_RST_SPI 0 ++#define BCM6358_RST_ENET 2 ++#define BCM6358_RST_MPI 3 ++#define BCM6358_RST_EPHY 6 ++#define BCM6358_RST_SAR 7 ++#define BCM6358_RST_USBH 12 ++#define BCM6358_RST_PCM 13 ++#define BCM6358_RST_ADSL 14 ++ ++#endif /* __DT_BINDINGS_RESET_BCM6358_H */ diff --git a/target/linux/bmips/patches-5.10/005-v5.12-mips-bmips-dts-add-BCM6358-reset-controller-support.patch b/target/linux/bmips/patches-5.10/005-v5.12-mips-bmips-dts-add-BCM6358-reset-controller-support.patch deleted file mode 100644 index d350dbb190..0000000000 --- a/target/linux/bmips/patches-5.10/005-v5.12-mips-bmips-dts-add-BCM6358-reset-controller-support.patch +++ /dev/null @@ -1,53 +0,0 @@ -From 8079cfba4c7b8cae900c27104b4512fa5ed1f021 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= -Date: Wed, 17 Jun 2020 12:50:37 +0200 -Subject: [PATCH 5/9] mips: bmips: dts: add BCM6358 reset controller support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM6358 SoCs have a reset controller for certain components. - -Signed-off-by: Álvaro Fernández Rojas -Acked-by: Florian Fainelli -Reviewed-by: Rob Herring -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/boot/dts/brcm/bcm6358.dtsi | 6 ++++++ - include/dt-bindings/reset/bcm6358-reset.h | 15 +++++++++++++++ - 2 files changed, 21 insertions(+) - create mode 100644 include/dt-bindings/reset/bcm6358-reset.h - ---- a/arch/mips/boot/dts/brcm/bcm6358.dtsi -+++ b/arch/mips/boot/dts/brcm/bcm6358.dtsi -@@ -82,6 +82,12 @@ - interrupts = <2>, <3>; - }; - -+ periph_rst: reset-controller@fffe0034 { -+ compatible = "brcm,bcm6345-reset"; -+ reg = <0xfffe0034 0x4>; -+ #reset-cells = <1>; -+ }; -+ - leds0: led-controller@fffe00d0 { - #address-cells = <1>; - #size-cells = <0>; ---- /dev/null -+++ b/include/dt-bindings/reset/bcm6358-reset.h -@@ -0,0 +1,15 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+ -+#ifndef __DT_BINDINGS_RESET_BCM6358_H -+#define __DT_BINDINGS_RESET_BCM6358_H -+ -+#define BCM6358_RST_SPI 0 -+#define BCM6358_RST_ENET 2 -+#define BCM6358_RST_MPI 3 -+#define BCM6358_RST_EPHY 6 -+#define BCM6358_RST_SAR 7 -+#define BCM6358_RST_USBH 12 -+#define BCM6358_RST_PCM 13 -+#define BCM6358_RST_ADSL 14 -+ -+#endif /* __DT_BINDINGS_RESET_BCM6358_H */ diff --git a/target/linux/bmips/patches-5.10/006-v5.11-mips-bmips-dts-add-BCM6362-reset-controller-support.patch b/target/linux/bmips/patches-5.10/006-v5.11-mips-bmips-dts-add-BCM6362-reset-controller-support.patch new file mode 100644 index 0000000000..31a8edd87d --- /dev/null +++ b/target/linux/bmips/patches-5.10/006-v5.11-mips-bmips-dts-add-BCM6362-reset-controller-support.patch @@ -0,0 +1,60 @@ +From 226383600be58dcf2e070e4ac8a371640024fe54 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= +Date: Wed, 17 Jun 2020 12:50:38 +0200 +Subject: [PATCH 6/9] mips: bmips: dts: add BCM6362 reset controller support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +BCM6362 SoCs have a reset controller for certain components. + +Signed-off-by: Álvaro Fernández Rojas +Acked-by: Florian Fainelli +Reviewed-by: Rob Herring +Signed-off-by: Thomas Bogendoerfer +--- + arch/mips/boot/dts/brcm/bcm6362.dtsi | 6 ++++++ + include/dt-bindings/reset/bcm6362-reset.h | 22 ++++++++++++++++++++++ + 2 files changed, 28 insertions(+) + create mode 100644 include/dt-bindings/reset/bcm6362-reset.h + +--- a/arch/mips/boot/dts/brcm/bcm6362.dtsi ++++ b/arch/mips/boot/dts/brcm/bcm6362.dtsi +@@ -70,6 +70,12 @@ + mask = <0x1>; + }; + ++ periph_rst: reset-controller@10000010 { ++ compatible = "brcm,bcm6345-reset"; ++ reg = <0x10000010 0x4>; ++ #reset-cells = <1>; ++ }; ++ + periph_intc: interrupt-controller@10000020 { + compatible = "brcm,bcm6345-l1-intc"; + reg = <0x10000020 0x10>, +--- /dev/null ++++ b/include/dt-bindings/reset/bcm6362-reset.h +@@ -0,0 +1,22 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++ ++#ifndef __DT_BINDINGS_RESET_BCM6362_H ++#define __DT_BINDINGS_RESET_BCM6362_H ++ ++#define BCM6362_RST_SPI 0 ++#define BCM6362_RST_IPSEC 1 ++#define BCM6362_RST_EPHY 2 ++#define BCM6362_RST_SAR 3 ++#define BCM6362_RST_ENETSW 4 ++#define BCM6362_RST_USBD 5 ++#define BCM6362_RST_USBH 6 ++#define BCM6362_RST_PCM 7 ++#define BCM6362_RST_PCIE_CORE 8 ++#define BCM6362_RST_PCIE 9 ++#define BCM6362_RST_PCIE_EXT 10 ++#define BCM6362_RST_WLAN_SHIM 11 ++#define BCM6362_RST_DDR_PHY 12 ++#define BCM6362_RST_FAP 13 ++#define BCM6362_RST_WLAN_UBUS 14 ++ ++#endif /* __DT_BINDINGS_RESET_BCM6362_H */ diff --git a/target/linux/bmips/patches-5.10/006-v5.12-mips-bmips-dts-add-BCM6362-reset-controller-support.patch b/target/linux/bmips/patches-5.10/006-v5.12-mips-bmips-dts-add-BCM6362-reset-controller-support.patch deleted file mode 100644 index 31a8edd87d..0000000000 --- a/target/linux/bmips/patches-5.10/006-v5.12-mips-bmips-dts-add-BCM6362-reset-controller-support.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 226383600be58dcf2e070e4ac8a371640024fe54 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= -Date: Wed, 17 Jun 2020 12:50:38 +0200 -Subject: [PATCH 6/9] mips: bmips: dts: add BCM6362 reset controller support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM6362 SoCs have a reset controller for certain components. - -Signed-off-by: Álvaro Fernández Rojas -Acked-by: Florian Fainelli -Reviewed-by: Rob Herring -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/boot/dts/brcm/bcm6362.dtsi | 6 ++++++ - include/dt-bindings/reset/bcm6362-reset.h | 22 ++++++++++++++++++++++ - 2 files changed, 28 insertions(+) - create mode 100644 include/dt-bindings/reset/bcm6362-reset.h - ---- a/arch/mips/boot/dts/brcm/bcm6362.dtsi -+++ b/arch/mips/boot/dts/brcm/bcm6362.dtsi -@@ -70,6 +70,12 @@ - mask = <0x1>; - }; - -+ periph_rst: reset-controller@10000010 { -+ compatible = "brcm,bcm6345-reset"; -+ reg = <0x10000010 0x4>; -+ #reset-cells = <1>; -+ }; -+ - periph_intc: interrupt-controller@10000020 { - compatible = "brcm,bcm6345-l1-intc"; - reg = <0x10000020 0x10>, ---- /dev/null -+++ b/include/dt-bindings/reset/bcm6362-reset.h -@@ -0,0 +1,22 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+ -+#ifndef __DT_BINDINGS_RESET_BCM6362_H -+#define __DT_BINDINGS_RESET_BCM6362_H -+ -+#define BCM6362_RST_SPI 0 -+#define BCM6362_RST_IPSEC 1 -+#define BCM6362_RST_EPHY 2 -+#define BCM6362_RST_SAR 3 -+#define BCM6362_RST_ENETSW 4 -+#define BCM6362_RST_USBD 5 -+#define BCM6362_RST_USBH 6 -+#define BCM6362_RST_PCM 7 -+#define BCM6362_RST_PCIE_CORE 8 -+#define BCM6362_RST_PCIE 9 -+#define BCM6362_RST_PCIE_EXT 10 -+#define BCM6362_RST_WLAN_SHIM 11 -+#define BCM6362_RST_DDR_PHY 12 -+#define BCM6362_RST_FAP 13 -+#define BCM6362_RST_WLAN_UBUS 14 -+ -+#endif /* __DT_BINDINGS_RESET_BCM6362_H */ diff --git a/target/linux/bmips/patches-5.10/007-v5.11-mips-bmips-dts-add-BCM6368-reset-controller-support.patch b/target/linux/bmips/patches-5.10/007-v5.11-mips-bmips-dts-add-BCM6368-reset-controller-support.patch new file mode 100644 index 0000000000..9d03665d19 --- /dev/null +++ b/target/linux/bmips/patches-5.10/007-v5.11-mips-bmips-dts-add-BCM6368-reset-controller-support.patch @@ -0,0 +1,54 @@ +From 7acf84e87857721d66a1ba800c2c50669089f43d Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= +Date: Wed, 17 Jun 2020 12:50:39 +0200 +Subject: [PATCH 7/9] mips: bmips: dts: add BCM6368 reset controller support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +BCM6368 SoCs have a reset controller for certain components. + +Signed-off-by: Álvaro Fernández Rojas +Acked-by: Florian Fainelli +Reviewed-by: Rob Herring +Signed-off-by: Thomas Bogendoerfer +--- + arch/mips/boot/dts/brcm/bcm6368.dtsi | 6 ++++++ + include/dt-bindings/reset/bcm6368-reset.h | 16 ++++++++++++++++ + 2 files changed, 22 insertions(+) + create mode 100644 include/dt-bindings/reset/bcm6368-reset.h + +--- a/arch/mips/boot/dts/brcm/bcm6368.dtsi ++++ b/arch/mips/boot/dts/brcm/bcm6368.dtsi +@@ -70,6 +70,12 @@ + mask = <0x1>; + }; + ++ periph_rst: reset-controller@10000010 { ++ compatible = "brcm,bcm6345-reset"; ++ reg = <0x10000010 0x4>; ++ #reset-cells = <1>; ++ }; ++ + periph_intc: interrupt-controller@10000020 { + compatible = "brcm,bcm6345-l1-intc"; + reg = <0x10000020 0x10>, +--- /dev/null ++++ b/include/dt-bindings/reset/bcm6368-reset.h +@@ -0,0 +1,16 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++ ++#ifndef __DT_BINDINGS_RESET_BCM6368_H ++#define __DT_BINDINGS_RESET_BCM6368_H ++ ++#define BCM6368_RST_SPI 0 ++#define BCM6368_RST_MPI 3 ++#define BCM6368_RST_IPSEC 4 ++#define BCM6368_RST_EPHY 6 ++#define BCM6368_RST_SAR 7 ++#define BCM6368_RST_SWITCH 10 ++#define BCM6368_RST_USBD 11 ++#define BCM6368_RST_USBH 12 ++#define BCM6368_RST_PCM 13 ++ ++#endif /* __DT_BINDINGS_RESET_BCM6368_H */ diff --git a/target/linux/bmips/patches-5.10/007-v5.12-mips-bmips-dts-add-BCM6368-reset-controller-support.patch b/target/linux/bmips/patches-5.10/007-v5.12-mips-bmips-dts-add-BCM6368-reset-controller-support.patch deleted file mode 100644 index 9d03665d19..0000000000 --- a/target/linux/bmips/patches-5.10/007-v5.12-mips-bmips-dts-add-BCM6368-reset-controller-support.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 7acf84e87857721d66a1ba800c2c50669089f43d Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= -Date: Wed, 17 Jun 2020 12:50:39 +0200 -Subject: [PATCH 7/9] mips: bmips: dts: add BCM6368 reset controller support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM6368 SoCs have a reset controller for certain components. - -Signed-off-by: Álvaro Fernández Rojas -Acked-by: Florian Fainelli -Reviewed-by: Rob Herring -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/boot/dts/brcm/bcm6368.dtsi | 6 ++++++ - include/dt-bindings/reset/bcm6368-reset.h | 16 ++++++++++++++++ - 2 files changed, 22 insertions(+) - create mode 100644 include/dt-bindings/reset/bcm6368-reset.h - ---- a/arch/mips/boot/dts/brcm/bcm6368.dtsi -+++ b/arch/mips/boot/dts/brcm/bcm6368.dtsi -@@ -70,6 +70,12 @@ - mask = <0x1>; - }; - -+ periph_rst: reset-controller@10000010 { -+ compatible = "brcm,bcm6345-reset"; -+ reg = <0x10000010 0x4>; -+ #reset-cells = <1>; -+ }; -+ - periph_intc: interrupt-controller@10000020 { - compatible = "brcm,bcm6345-l1-intc"; - reg = <0x10000020 0x10>, ---- /dev/null -+++ b/include/dt-bindings/reset/bcm6368-reset.h -@@ -0,0 +1,16 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+ -+#ifndef __DT_BINDINGS_RESET_BCM6368_H -+#define __DT_BINDINGS_RESET_BCM6368_H -+ -+#define BCM6368_RST_SPI 0 -+#define BCM6368_RST_MPI 3 -+#define BCM6368_RST_IPSEC 4 -+#define BCM6368_RST_EPHY 6 -+#define BCM6368_RST_SAR 7 -+#define BCM6368_RST_SWITCH 10 -+#define BCM6368_RST_USBD 11 -+#define BCM6368_RST_USBH 12 -+#define BCM6368_RST_PCM 13 -+ -+#endif /* __DT_BINDINGS_RESET_BCM6368_H */ diff --git a/target/linux/bmips/patches-5.10/008-v5.11-mips-bmips-dts-add-BCM63268-reset-controller-support.patch b/target/linux/bmips/patches-5.10/008-v5.11-mips-bmips-dts-add-BCM63268-reset-controller-support.patch new file mode 100644 index 0000000000..b508190b91 --- /dev/null +++ b/target/linux/bmips/patches-5.10/008-v5.11-mips-bmips-dts-add-BCM63268-reset-controller-support.patch @@ -0,0 +1,64 @@ +From b7aa228813bdf014d6ad173ca3abfced30f1ed37 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= +Date: Wed, 17 Jun 2020 12:50:40 +0200 +Subject: [PATCH 8/9] mips: bmips: dts: add BCM63268 reset controller support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +BCM63268 SoCs have a reset controller for certain components. + +Signed-off-by: Álvaro Fernández Rojas +Acked-by: Florian Fainelli +Reviewed-by: Rob Herring +Signed-off-by: Thomas Bogendoerfer +--- + arch/mips/boot/dts/brcm/bcm63268.dtsi | 6 +++++ + include/dt-bindings/reset/bcm63268-reset.h | 26 ++++++++++++++++++++++ + 2 files changed, 32 insertions(+) + create mode 100644 include/dt-bindings/reset/bcm63268-reset.h + +--- a/arch/mips/boot/dts/brcm/bcm63268.dtsi ++++ b/arch/mips/boot/dts/brcm/bcm63268.dtsi +@@ -70,6 +70,12 @@ + mask = <0x1>; + }; + ++ periph_rst: reset-controller@10000010 { ++ compatible = "brcm,bcm6345-reset"; ++ reg = <0x10000010 0x4>; ++ #reset-cells = <1>; ++ }; ++ + periph_intc: interrupt-controller@10000020 { + compatible = "brcm,bcm6345-l1-intc"; + reg = <0x10000020 0x20>, +--- /dev/null ++++ b/include/dt-bindings/reset/bcm63268-reset.h +@@ -0,0 +1,26 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++ ++#ifndef __DT_BINDINGS_RESET_BCM63268_H ++#define __DT_BINDINGS_RESET_BCM63268_H ++ ++#define BCM63268_RST_SPI 0 ++#define BCM63268_RST_IPSEC 1 ++#define BCM63268_RST_EPHY 2 ++#define BCM63268_RST_SAR 3 ++#define BCM63268_RST_ENETSW 4 ++#define BCM63268_RST_USBS 5 ++#define BCM63268_RST_USBH 6 ++#define BCM63268_RST_PCM 7 ++#define BCM63268_RST_PCIE_CORE 8 ++#define BCM63268_RST_PCIE 9 ++#define BCM63268_RST_PCIE_EXT 10 ++#define BCM63268_RST_WLAN_SHIM 11 ++#define BCM63268_RST_DDR_PHY 12 ++#define BCM63268_RST_FAP0 13 ++#define BCM63268_RST_WLAN_UBUS 14 ++#define BCM63268_RST_DECT 15 ++#define BCM63268_RST_FAP1 16 ++#define BCM63268_RST_PCIE_HARD 17 ++#define BCM63268_RST_GPHY 18 ++ ++#endif /* __DT_BINDINGS_RESET_BCM63268_H */ diff --git a/target/linux/bmips/patches-5.10/008-v5.12-mips-bmips-dts-add-BCM63268-reset-controller-support.patch b/target/linux/bmips/patches-5.10/008-v5.12-mips-bmips-dts-add-BCM63268-reset-controller-support.patch deleted file mode 100644 index b508190b91..0000000000 --- a/target/linux/bmips/patches-5.10/008-v5.12-mips-bmips-dts-add-BCM63268-reset-controller-support.patch +++ /dev/null @@ -1,64 +0,0 @@ -From b7aa228813bdf014d6ad173ca3abfced30f1ed37 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= -Date: Wed, 17 Jun 2020 12:50:40 +0200 -Subject: [PATCH 8/9] mips: bmips: dts: add BCM63268 reset controller support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM63268 SoCs have a reset controller for certain components. - -Signed-off-by: Álvaro Fernández Rojas -Acked-by: Florian Fainelli -Reviewed-by: Rob Herring -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/boot/dts/brcm/bcm63268.dtsi | 6 +++++ - include/dt-bindings/reset/bcm63268-reset.h | 26 ++++++++++++++++++++++ - 2 files changed, 32 insertions(+) - create mode 100644 include/dt-bindings/reset/bcm63268-reset.h - ---- a/arch/mips/boot/dts/brcm/bcm63268.dtsi -+++ b/arch/mips/boot/dts/brcm/bcm63268.dtsi -@@ -70,6 +70,12 @@ - mask = <0x1>; - }; - -+ periph_rst: reset-controller@10000010 { -+ compatible = "brcm,bcm6345-reset"; -+ reg = <0x10000010 0x4>; -+ #reset-cells = <1>; -+ }; -+ - periph_intc: interrupt-controller@10000020 { - compatible = "brcm,bcm6345-l1-intc"; - reg = <0x10000020 0x20>, ---- /dev/null -+++ b/include/dt-bindings/reset/bcm63268-reset.h -@@ -0,0 +1,26 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+ -+#ifndef __DT_BINDINGS_RESET_BCM63268_H -+#define __DT_BINDINGS_RESET_BCM63268_H -+ -+#define BCM63268_RST_SPI 0 -+#define BCM63268_RST_IPSEC 1 -+#define BCM63268_RST_EPHY 2 -+#define BCM63268_RST_SAR 3 -+#define BCM63268_RST_ENETSW 4 -+#define BCM63268_RST_USBS 5 -+#define BCM63268_RST_USBH 6 -+#define BCM63268_RST_PCM 7 -+#define BCM63268_RST_PCIE_CORE 8 -+#define BCM63268_RST_PCIE 9 -+#define BCM63268_RST_PCIE_EXT 10 -+#define BCM63268_RST_WLAN_SHIM 11 -+#define BCM63268_RST_DDR_PHY 12 -+#define BCM63268_RST_FAP0 13 -+#define BCM63268_RST_WLAN_UBUS 14 -+#define BCM63268_RST_DECT 15 -+#define BCM63268_RST_FAP1 16 -+#define BCM63268_RST_PCIE_HARD 17 -+#define BCM63268_RST_GPHY 18 -+ -+#endif /* __DT_BINDINGS_RESET_BCM63268_H */ diff --git a/target/linux/bmips/patches-5.10/009-v5.11-mips-bmips-add-BCM6318-reset-controller-definitions.patch b/target/linux/bmips/patches-5.10/009-v5.11-mips-bmips-add-BCM6318-reset-controller-definitions.patch new file mode 100644 index 0000000000..4cbaa569cd --- /dev/null +++ b/target/linux/bmips/patches-5.10/009-v5.11-mips-bmips-add-BCM6318-reset-controller-definitions.patch @@ -0,0 +1,42 @@ +From 8c9e8b0a28225c46f2cca0a09a3a111bb043e874 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= +Date: Wed, 17 Jun 2020 12:50:41 +0200 +Subject: [PATCH 9/9] mips: bmips: add BCM6318 reset controller definitions +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +BCM6318 SoCs have a reset controller for certain components. + +Signed-off-by: Álvaro Fernández Rojas +Acked-by: Florian Fainelli +Reviewed-by: Rob Herring +Signed-off-by: Thomas Bogendoerfer +--- + include/dt-bindings/reset/bcm6318-reset.h | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + create mode 100644 include/dt-bindings/reset/bcm6318-reset.h + +--- /dev/null ++++ b/include/dt-bindings/reset/bcm6318-reset.h +@@ -0,0 +1,20 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++ ++#ifndef __DT_BINDINGS_RESET_BCM6318_H ++#define __DT_BINDINGS_RESET_BCM6318_H ++ ++#define BCM6318_RST_SPI 0 ++#define BCM6318_RST_EPHY 1 ++#define BCM6318_RST_SAR 2 ++#define BCM6318_RST_ENETSW 3 ++#define BCM6318_RST_USBD 4 ++#define BCM6318_RST_USBH 5 ++#define BCM6318_RST_PCIE_CORE 6 ++#define BCM6318_RST_PCIE 7 ++#define BCM6318_RST_PCIE_EXT 8 ++#define BCM6318_RST_PCIE_HARD 9 ++#define BCM6318_RST_ADSL 10 ++#define BCM6318_RST_PHYMIPS 11 ++#define BCM6318_RST_HOSTMIPS 12 ++ ++#endif /* __DT_BINDINGS_RESET_BCM6318_H */ diff --git a/target/linux/bmips/patches-5.10/009-v5.12-mips-bmips-add-BCM6318-reset-controller-definitions.patch b/target/linux/bmips/patches-5.10/009-v5.12-mips-bmips-add-BCM6318-reset-controller-definitions.patch deleted file mode 100644 index 4cbaa569cd..0000000000 --- a/target/linux/bmips/patches-5.10/009-v5.12-mips-bmips-add-BCM6318-reset-controller-definitions.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 8c9e8b0a28225c46f2cca0a09a3a111bb043e874 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= -Date: Wed, 17 Jun 2020 12:50:41 +0200 -Subject: [PATCH 9/9] mips: bmips: add BCM6318 reset controller definitions -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM6318 SoCs have a reset controller for certain components. - -Signed-off-by: Álvaro Fernández Rojas -Acked-by: Florian Fainelli -Reviewed-by: Rob Herring -Signed-off-by: Thomas Bogendoerfer ---- - include/dt-bindings/reset/bcm6318-reset.h | 20 ++++++++++++++++++++ - 1 file changed, 20 insertions(+) - create mode 100644 include/dt-bindings/reset/bcm6318-reset.h - ---- /dev/null -+++ b/include/dt-bindings/reset/bcm6318-reset.h -@@ -0,0 +1,20 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+ -+#ifndef __DT_BINDINGS_RESET_BCM6318_H -+#define __DT_BINDINGS_RESET_BCM6318_H -+ -+#define BCM6318_RST_SPI 0 -+#define BCM6318_RST_EPHY 1 -+#define BCM6318_RST_SAR 2 -+#define BCM6318_RST_ENETSW 3 -+#define BCM6318_RST_USBD 4 -+#define BCM6318_RST_USBH 5 -+#define BCM6318_RST_PCIE_CORE 6 -+#define BCM6318_RST_PCIE 7 -+#define BCM6318_RST_PCIE_EXT 8 -+#define BCM6318_RST_PCIE_HARD 9 -+#define BCM6318_RST_ADSL 10 -+#define BCM6318_RST_PHYMIPS 11 -+#define BCM6318_RST_HOSTMIPS 12 -+ -+#endif /* __DT_BINDINGS_RESET_BCM6318_H */