From: Masahiro Yamada Date: Fri, 20 Feb 2015 08:04:18 +0000 (+0900) Subject: ARM: keystone: move SoC headers to mach-keystone/include/mach X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=dc7de222aa82cc962f15b5d04e1e4c6b0ab62398;p=project%2Fbcm63xx%2Fu-boot.git ARM: keystone: move SoC headers to mach-keystone/include/mach Move arch/arm/include/asm/arch-keystone/* -> arch/arm/mach-keystone/include/mach/* Signed-off-by: Masahiro Yamada Cc: Tom Rini --- diff --git a/arch/arm/include/asm/arch-keystone/clock-k2e.h b/arch/arm/include/asm/arch-keystone/clock-k2e.h deleted file mode 100644 index d013b830ed..0000000000 --- a/arch/arm/include/asm/arch-keystone/clock-k2e.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * K2E: Clock management APIs - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_CLOCK_K2E_H -#define __ASM_ARCH_CLOCK_K2E_H - -enum ext_clk_e { - sys_clk, - alt_core_clk, - pa_clk, - ddr3_clk, - mcm_clk, - pcie_clk, - sgmii_clk, - xgmii_clk, - usb_clk, - ext_clk_count /* number of external clocks */ -}; - -extern unsigned int external_clk[ext_clk_count]; - -#define CLK_LIST(CLK)\ - CLK(0, core_pll_clk)\ - CLK(1, pass_pll_clk)\ - CLK(2, ddr3_pll_clk)\ - CLK(3, sys_clk0_clk)\ - CLK(4, sys_clk0_1_clk)\ - CLK(5, sys_clk0_2_clk)\ - CLK(6, sys_clk0_3_clk)\ - CLK(7, sys_clk0_4_clk)\ - CLK(8, sys_clk0_6_clk)\ - CLK(9, sys_clk0_8_clk)\ - CLK(10, sys_clk0_12_clk)\ - CLK(11, sys_clk0_24_clk)\ - CLK(12, sys_clk1_clk)\ - CLK(13, sys_clk1_3_clk)\ - CLK(14, sys_clk1_4_clk)\ - CLK(15, sys_clk1_6_clk)\ - CLK(16, sys_clk1_12_clk)\ - CLK(17, sys_clk2_clk)\ - CLK(18, sys_clk3_clk) - -#define PLLSET_CMD_LIST "" - -#define KS2_CLK1_6 sys_clk0_6_clk - -/* PLL identifiers */ -enum pll_type_e { - CORE_PLL, - PASS_PLL, - DDR3_PLL, -}; - -enum { - SPD800, - SPD850, - SPD1000, - SPD1250, - SPD1350, - SPD1400, - SPD1500, - SPD_RSV -}; - -#define CORE_PLL_800 {CORE_PLL, 16, 1, 2} -#define CORE_PLL_850 {CORE_PLL, 17, 1, 2} -#define CORE_PLL_1000 {CORE_PLL, 20, 1, 2} -#define CORE_PLL_1200 {CORE_PLL, 24, 1, 2} -#define PASS_PLL_1000 {PASS_PLL, 20, 1, 2} -#define CORE_PLL_1250 {CORE_PLL, 25, 1, 2} -#define CORE_PLL_1350 {CORE_PLL, 27, 1, 2} -#define CORE_PLL_1400 {CORE_PLL, 28, 1, 2} -#define CORE_PLL_1500 {CORE_PLL, 30, 1, 2} -#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2} -#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4} -#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2} -#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6} - -#endif diff --git a/arch/arm/include/asm/arch-keystone/clock-k2hk.h b/arch/arm/include/asm/arch-keystone/clock-k2hk.h deleted file mode 100644 index f28d5f0c4e..0000000000 --- a/arch/arm/include/asm/arch-keystone/clock-k2hk.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - * K2HK: Clock management APIs - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_CLOCK_K2HK_H -#define __ASM_ARCH_CLOCK_K2HK_H - -enum ext_clk_e { - sys_clk, - alt_core_clk, - pa_clk, - tetris_clk, - ddr3a_clk, - ddr3b_clk, - mcm_clk, - pcie_clk, - sgmii_srio_clk, - xgmii_clk, - usb_clk, - rp1_clk, - ext_clk_count /* number of external clocks */ -}; - -extern unsigned int external_clk[ext_clk_count]; - -#define CLK_LIST(CLK)\ - CLK(0, core_pll_clk)\ - CLK(1, pass_pll_clk)\ - CLK(2, tetris_pll_clk)\ - CLK(3, ddr3a_pll_clk)\ - CLK(4, ddr3b_pll_clk)\ - CLK(5, sys_clk0_clk)\ - CLK(6, sys_clk0_1_clk)\ - CLK(7, sys_clk0_2_clk)\ - CLK(8, sys_clk0_3_clk)\ - CLK(9, sys_clk0_4_clk)\ - CLK(10, sys_clk0_6_clk)\ - CLK(11, sys_clk0_8_clk)\ - CLK(12, sys_clk0_12_clk)\ - CLK(13, sys_clk0_24_clk)\ - CLK(14, sys_clk1_clk)\ - CLK(15, sys_clk1_3_clk)\ - CLK(16, sys_clk1_4_clk)\ - CLK(17, sys_clk1_6_clk)\ - CLK(18, sys_clk1_12_clk)\ - CLK(19, sys_clk2_clk)\ - CLK(20, sys_clk3_clk) - -#define PLLSET_CMD_LIST "" - -#define KS2_CLK1_6 sys_clk0_6_clk - -/* PLL identifiers */ -enum pll_type_e { - CORE_PLL, - PASS_PLL, - TETRIS_PLL, - DDR3A_PLL, - DDR3B_PLL, -}; - -enum { - SPD800, - SPD1000, - SPD1200, - SPD1350, - SPD1400, - SPD_RSV -}; - -#define CORE_PLL_799 {CORE_PLL, 13, 1, 2} -#define CORE_PLL_983 {CORE_PLL, 16, 1, 2} -#define CORE_PLL_999 {CORE_PLL, 122, 15, 1} -#define CORE_PLL_1167 {CORE_PLL, 19, 1, 2} -#define CORE_PLL_1228 {CORE_PLL, 20, 1, 2} -#define CORE_PLL_1200 {CORE_PLL, 625, 32, 2} -#define PASS_PLL_1228 {PASS_PLL, 20, 1, 2} -#define PASS_PLL_983 {PASS_PLL, 16, 1, 2} -#define PASS_PLL_1050 {PASS_PLL, 205, 12, 2} -#define TETRIS_PLL_500 {TETRIS_PLL, 8, 1, 2} -#define TETRIS_PLL_750 {TETRIS_PLL, 12, 1, 2} -#define TETRIS_PLL_800 {TETRIS_PLL, 32, 5, 1} -#define TETRIS_PLL_687 {TETRIS_PLL, 11, 1, 2} -#define TETRIS_PLL_625 {TETRIS_PLL, 10, 1, 2} -#define TETRIS_PLL_812 {TETRIS_PLL, 13, 1, 2} -#define TETRIS_PLL_875 {TETRIS_PLL, 14, 1, 2} -#define TETRIS_PLL_1000 {TETRIS_PLL, 40, 5, 1} -#define TETRIS_PLL_1188 {TETRIS_PLL, 19, 2, 1} -#define TETRIS_PLL_1200 {TETRIS_PLL, 48, 5, 1} -#define TETRIS_PLL_1350 {TETRIS_PLL, 54, 5, 1} -#define TETRIS_PLL_1375 {TETRIS_PLL, 22, 2, 1} -#define TETRIS_PLL_1400 {TETRIS_PLL, 56, 5, 1} -#define DDR3_PLL_200(x) {DDR3##x##_PLL, 4, 1, 2} -#define DDR3_PLL_400(x) {DDR3##x##_PLL, 16, 1, 4} -#define DDR3_PLL_800(x) {DDR3##x##_PLL, 16, 1, 2} -#define DDR3_PLL_333(x) {DDR3##x##_PLL, 20, 1, 6} - -#endif diff --git a/arch/arm/include/asm/arch-keystone/clock-k2l.h b/arch/arm/include/asm/arch-keystone/clock-k2l.h deleted file mode 100644 index bb9a5c4dcf..0000000000 --- a/arch/arm/include/asm/arch-keystone/clock-k2l.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * K2L: Clock management APIs - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_CLOCK_K2L_H -#define __ASM_ARCH_CLOCK_K2L_H - -enum ext_clk_e { - sys_clk, - alt_core_clk, - pa_clk, - tetris_clk, - ddr3_clk, - pcie_clk, - sgmii_clk, - usb_clk, - rp1_clk, - ext_clk_count /* number of external clocks */ -}; - -extern unsigned int external_clk[ext_clk_count]; - -#define CLK_LIST(CLK)\ - CLK(0, core_pll_clk)\ - CLK(1, pass_pll_clk)\ - CLK(2, tetris_pll_clk)\ - CLK(3, ddr3_pll_clk)\ - CLK(4, sys_clk0_clk)\ - CLK(5, sys_clk0_1_clk)\ - CLK(6, sys_clk0_2_clk)\ - CLK(7, sys_clk0_3_clk)\ - CLK(8, sys_clk0_4_clk)\ - CLK(9, sys_clk0_6_clk)\ - CLK(10, sys_clk0_8_clk)\ - CLK(11, sys_clk0_12_clk)\ - CLK(12, sys_clk0_24_clk)\ - CLK(13, sys_clk1_clk)\ - CLK(14, sys_clk1_3_clk)\ - CLK(15, sys_clk1_4_clk)\ - CLK(16, sys_clk1_6_clk)\ - CLK(17, sys_clk1_12_clk)\ - CLK(18, sys_clk2_clk)\ - CLK(19, sys_clk3_clk)\ - -#define PLLSET_CMD_LIST "" - -#define KS2_CLK1_6 sys_clk0_6_clk - -/* PLL identifiers */ -enum pll_type_e { - CORE_PLL, - PASS_PLL, - TETRIS_PLL, - DDR3_PLL, -}; - -enum { - SPD800, - SPD1000, - SPD1200, - SPD1350, - SPD1400, - SPD_RSV -}; - -#define CORE_PLL_799 {CORE_PLL, 13, 1, 2} -#define CORE_PLL_983 {CORE_PLL, 16, 1, 2} -#define CORE_PLL_1000 {CORE_PLL, 114, 7, 2} -#define CORE_PLL_1167 {CORE_PLL, 19, 1, 2} -#define CORE_PLL_1198 {CORE_PLL, 39, 2, 2} -#define CORE_PLL_1228 {CORE_PLL, 20, 1, 2} -#define PASS_PLL_1228 {PASS_PLL, 20, 1, 2} -#define PASS_PLL_983 {PASS_PLL, 16, 1, 2} -#define PASS_PLL_1050 {PASS_PLL, 205, 12, 2} -#define TETRIS_PLL_491 {TETRIS_PLL, 8, 1, 2} -#define TETRIS_PLL_737 {TETRIS_PLL, 12, 1, 2} -#define TETRIS_PLL_799 {TETRIS_PLL, 13, 1, 2} -#define TETRIS_PLL_983 {TETRIS_PLL, 16, 1, 2} -#define TETRIS_PLL_1000 {TETRIS_PLL, 114, 7, 2} -#define TETRIS_PLL_1167 {TETRIS_PLL, 19, 1, 2} -#define TETRIS_PLL_1198 {TETRIS_PLL, 39, 2, 2} -#define TETRIS_PLL_1228 {TETRIS_PLL, 20, 1, 2} -#define TETRIS_PLL_1352 {TETRIS_PLL, 22, 1, 2} -#define TETRIS_PLL_1401 {TETRIS_PLL, 114, 5, 2} -#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2} -#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4} -#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2} -#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6} - -#endif diff --git a/arch/arm/include/asm/arch-keystone/clock.h b/arch/arm/include/asm/arch-keystone/clock.h deleted file mode 100644 index 9f6cfb265f..0000000000 --- a/arch/arm/include/asm/arch-keystone/clock.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * keystone2: common clock header file - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -#ifndef __ASSEMBLY__ - -#ifdef CONFIG_SOC_K2HK -#include -#endif - -#ifdef CONFIG_SOC_K2E -#include -#endif - -#ifdef CONFIG_SOC_K2L -#include -#endif - -#define MAIN_PLL CORE_PLL - -#include - -#define GENERATE_ENUM(NUM, ENUM) ENUM = NUM, -#define GENERATE_INDX_STR(NUM, STRING) #NUM"\t- "#STRING"\n" -#define CLOCK_INDEXES_LIST CLK_LIST(GENERATE_INDX_STR) - -enum clk_e { - CLK_LIST(GENERATE_ENUM) -}; - -struct keystone_pll_regs { - u32 reg0; - u32 reg1; -}; - -/* PLL configuration data */ -struct pll_init_data { - int pll; - int pll_m; /* PLL Multiplier */ - int pll_d; /* PLL divider */ - int pll_od; /* PLL output divider */ -}; - -extern const struct keystone_pll_regs keystone_pll_regs[]; -extern int dev_speeds[]; -extern int arm_speeds[]; - -void init_plls(int num_pll, struct pll_init_data *config); -void init_pll(const struct pll_init_data *data); -unsigned long clk_get_rate(unsigned int clk); -unsigned long clk_round_rate(unsigned int clk, unsigned long hz); -int clk_set_rate(unsigned int clk, unsigned long hz); -void pass_pll_pa_clk_enable(void); -int get_max_dev_speed(void); -int get_max_arm_speed(void); - -#endif -#endif diff --git a/arch/arm/include/asm/arch-keystone/clock_defs.h b/arch/arm/include/asm/arch-keystone/clock_defs.h deleted file mode 100644 index 85a046b89a..0000000000 --- a/arch/arm/include/asm/arch-keystone/clock_defs.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * keystone2: common pll clock definitions - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _CLOCK_DEFS_H_ -#define _CLOCK_DEFS_H_ - -#include - -#define BIT(x) (1 << (x)) - -/* PLL Control Registers */ -struct pllctl_regs { - u32 ctl; /* 00 */ - u32 ocsel; /* 04 */ - u32 secctl; /* 08 */ - u32 resv0; - u32 mult; /* 10 */ - u32 prediv; /* 14 */ - u32 div1; /* 18 */ - u32 div2; /* 1c */ - u32 div3; /* 20 */ - u32 oscdiv1; /* 24 */ - u32 resv1; /* 28 */ - u32 bpdiv; /* 2c */ - u32 wakeup; /* 30 */ - u32 resv2; - u32 cmd; /* 38 */ - u32 stat; /* 3c */ - u32 alnctl; /* 40 */ - u32 dchange; /* 44 */ - u32 cken; /* 48 */ - u32 ckstat; /* 4c */ - u32 systat; /* 50 */ - u32 ckctl; /* 54 */ - u32 resv3[2]; - u32 div4; /* 60 */ - u32 div5; /* 64 */ - u32 div6; /* 68 */ - u32 div7; /* 6c */ - u32 div8; /* 70 */ - u32 div9; /* 74 */ - u32 div10; /* 78 */ - u32 div11; /* 7c */ - u32 div12; /* 80 */ -}; - -static struct pllctl_regs *pllctl_regs[] = { - (struct pllctl_regs *)(KS2_CLOCK_BASE + 0x100) -}; - -#define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg)) -#define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg)) -#define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg)) - -#define pllctl_reg_rmw(pll, reg, mask, val) \ - pllctl_reg_write(pll, reg, \ - (pllctl_reg_read(pll, reg) & ~(mask)) | val) - -#define pllctl_reg_setbits(pll, reg, mask) \ - pllctl_reg_rmw(pll, reg, 0, mask) - -#define pllctl_reg_clrbits(pll, reg, mask) \ - pllctl_reg_rmw(pll, reg, mask, 0) - -#define pll0div_read(N) ((pllctl_reg_read(CORE_PLL, div##N) & 0xff) + 1) - -/* PLLCTL Bits */ -#define PLLCTL_BYPASS BIT(23) -#define PLL_PLLRST BIT(14) -#define PLLCTL_PAPLL BIT(13) -#define PLLCTL_CLKMODE BIT(8) -#define PLLCTL_PLLSELB BIT(7) -#define PLLCTL_ENSAT BIT(6) -#define PLLCTL_PLLENSRC BIT(5) -#define PLLCTL_PLLDIS BIT(4) -#define PLLCTL_PLLRST BIT(3) -#define PLLCTL_PLLPWRDN BIT(1) -#define PLLCTL_PLLEN BIT(0) -#define PLLSTAT_GO BIT(0) - -#define MAIN_ENSAT_OFFSET 6 - -#define PLLDIV_ENABLE BIT(15) - -#define PLL_DIV_MASK 0x3f -#define PLL_MULT_MASK 0x1fff -#define PLL_MULT_SHIFT 6 -#define PLLM_MULT_HI_MASK 0x7f -#define PLLM_MULT_HI_SHIFT 12 -#define PLLM_MULT_HI_SMASK (PLLM_MULT_HI_MASK << PLLM_MULT_HI_SHIFT) -#define PLLM_MULT_LO_MASK 0x3f -#define PLL_CLKOD_MASK 0xf -#define PLL_CLKOD_SHIFT 19 -#define PLL_CLKOD_SMASK (PLL_CLKOD_MASK << PLL_CLKOD_SHIFT) -#define PLL_BWADJ_LO_MASK 0xff -#define PLL_BWADJ_LO_SHIFT 24 -#define PLL_BWADJ_LO_SMASK (PLL_BWADJ_LO_MASK << PLL_BWADJ_LO_SHIFT) -#define PLL_BWADJ_HI_MASK 0xf - -#define PLLM_RATIO_DIV1 (PLLDIV_ENABLE | 0x0) -#define PLLM_RATIO_DIV2 (PLLDIV_ENABLE | 0x0) -#define PLLM_RATIO_DIV3 (PLLDIV_ENABLE | 0x1) -#define PLLM_RATIO_DIV4 (PLLDIV_ENABLE | 0x4) -#define PLLM_RATIO_DIV5 (PLLDIV_ENABLE | 0x17) - -#endif /* _CLOCK_DEFS_H_ */ diff --git a/arch/arm/include/asm/arch-keystone/ddr3.h b/arch/arm/include/asm/arch-keystone/ddr3.h deleted file mode 100644 index a22c237c80..0000000000 --- a/arch/arm/include/asm/arch-keystone/ddr3.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * DDR3 - * - * (C) Copyright 2014 - * Texas Instruments Incorporated, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _DDR3_H_ -#define _DDR3_H_ - -#include - -struct ddr3_phy_config { - unsigned int pllcr; - unsigned int pgcr1_mask; - unsigned int pgcr1_val; - unsigned int ptr0; - unsigned int ptr1; - unsigned int ptr2; - unsigned int ptr3; - unsigned int ptr4; - unsigned int dcr_mask; - unsigned int dcr_val; - unsigned int dtpr0; - unsigned int dtpr1; - unsigned int dtpr2; - unsigned int mr0; - unsigned int mr1; - unsigned int mr2; - unsigned int dtcr; - unsigned int pgcr2; - unsigned int zq0cr1; - unsigned int zq1cr1; - unsigned int zq2cr1; - unsigned int pir_v1; - unsigned int pir_v2; -}; - -struct ddr3_emif_config { - unsigned int sdcfg; - unsigned int sdtim1; - unsigned int sdtim2; - unsigned int sdtim3; - unsigned int sdtim4; - unsigned int zqcfg; - unsigned int sdrfc; -}; - -u32 ddr3_init(void); -void ddr3_reset_ddrphy(void); -void ddr3_init_ecc(u32 base, u32 ddr3_size); -void ddr3_disable_ecc(u32 base); -void ddr3_check_ecc_int(u32 base); -int ddr3_ecc_support_rmw(u32 base); -void ddr3_err_reset_workaround(void); -void ddr3_enable_ecc(u32 base, int test); -void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg); -void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg); - -#endif diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2e.h b/arch/arm/include/asm/arch-keystone/hardware-k2e.h deleted file mode 100644 index df499957e5..0000000000 --- a/arch/arm/include/asm/arch-keystone/hardware-k2e.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * K2E: SoC definitions - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_HARDWARE_K2E_H -#define __ASM_ARCH_HARDWARE_K2E_H - -/* PA SS Registers */ -#define KS2_PASS_BASE 0x24000000 - -/* Power and Sleep Controller (PSC) Domains */ -#define KS2_LPSC_MOD_RST 0 -#define KS2_LPSC_USB_1 1 -#define KS2_LPSC_USB 2 -#define KS2_LPSC_EMIF25_SPI 3 -#define KS2_LPSC_TSIP 4 -#define KS2_LPSC_DEBUGSS_TRC 5 -#define KS2_LPSC_TETB_TRC 6 -#define KS2_LPSC_PKTPROC 7 -#define KS2_LPSC_PA KS2_LPSC_PKTPROC -#define KS2_LPSC_SGMII 8 -#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII -#define KS2_LPSC_CRYPTO 9 -#define KS2_LPSC_PCIE 10 -#define KS2_LPSC_VUSR0 12 -#define KS2_LPSC_CHIP_SRSS 13 -#define KS2_LPSC_MSMC 14 -#define KS2_LPSC_EMIF4F_DDR3 23 -#define KS2_LPSC_PCIE_1 27 -#define KS2_LPSC_XGE 50 - -/* MSMC */ -#define KS2_MSMC_SEGMENT_PCIE1 13 - -/* Chip Interrupt Controller */ -#define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */ -#define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */ - -/* SGMII SerDes */ -#define KS2_SGMII_SERDES2_BASE 0x02324000 -#define KS2_LANES_PER_SGMII_SERDES 4 - -/* Number of DSP cores */ -#define KS2_NUM_DSPS 1 - -/* NETCP pktdma */ -#define KS2_NETCP_PDMA_CTRL_BASE 0x24186000 -#define KS2_NETCP_PDMA_TX_BASE 0x24187000 -#define KS2_NETCP_PDMA_TX_CH_NUM 21 -#define KS2_NETCP_PDMA_RX_BASE 0x24188000 -#define KS2_NETCP_PDMA_RX_CH_NUM 91 -#define KS2_NETCP_PDMA_SCHED_BASE 0x24186100 -#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x24189000 -#define KS2_NETCP_PDMA_RX_FLOW_NUM 96 -#define KS2_NETCP_PDMA_TX_SND_QUEUE 896 - -/* NETCP */ -#define KS2_NETCP_BASE 0x24000000 - -#endif diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h deleted file mode 100644 index 195c0d3003..0000000000 --- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * K2HK: SoC definitions - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_HARDWARE_K2HK_H -#define __ASM_ARCH_HARDWARE_K2HK_H - -#define KS2_ARM_PLL_EN BIT(13) - -/* PA SS Registers */ -#define KS2_PASS_BASE 0x02000000 - -/* PLL control registers */ -#define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368) -#define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C) - -/* Power and Sleep Controller (PSC) Domains */ -#define KS2_LPSC_MOD 0 -#define KS2_LPSC_DUMMY1 1 -#define KS2_LPSC_USB 2 -#define KS2_LPSC_EMIF25_SPI 3 -#define KS2_LPSC_TSIP 4 -#define KS2_LPSC_DEBUGSS_TRC 5 -#define KS2_LPSC_TETB_TRC 6 -#define KS2_LPSC_PKTPROC 7 -#define KS2_LPSC_PA KS2_LPSC_PKTPROC -#define KS2_LPSC_SGMII 8 -#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII -#define KS2_LPSC_CRYPTO 9 -#define KS2_LPSC_PCIE 10 -#define KS2_LPSC_SRIO 11 -#define KS2_LPSC_VUSR0 12 -#define KS2_LPSC_CHIP_SRSS 13 -#define KS2_LPSC_MSMC 14 -#define KS2_LPSC_GEM_1 16 -#define KS2_LPSC_GEM_2 17 -#define KS2_LPSC_GEM_3 18 -#define KS2_LPSC_GEM_4 19 -#define KS2_LPSC_GEM_5 20 -#define KS2_LPSC_GEM_6 21 -#define KS2_LPSC_GEM_7 22 -#define KS2_LPSC_EMIF4F_DDR3A 23 -#define KS2_LPSC_EMIF4F_DDR3B 24 -#define KS2_LPSC_TAC 25 -#define KS2_LPSC_RAC 26 -#define KS2_LPSC_RAC_1 27 -#define KS2_LPSC_FFTC_A 28 -#define KS2_LPSC_FFTC_B 29 -#define KS2_LPSC_FFTC_C 30 -#define KS2_LPSC_FFTC_D 31 -#define KS2_LPSC_FFTC_E 32 -#define KS2_LPSC_FFTC_F 33 -#define KS2_LPSC_AI2 34 -#define KS2_LPSC_TCP3D_0 35 -#define KS2_LPSC_TCP3D_1 36 -#define KS2_LPSC_TCP3D_2 37 -#define KS2_LPSC_TCP3D_3 38 -#define KS2_LPSC_VCP2X4_A 39 -#define KS2_LPSC_CP2X4_B 40 -#define KS2_LPSC_VCP2X4_C 41 -#define KS2_LPSC_VCP2X4_D 42 -#define KS2_LPSC_VCP2X4_E 43 -#define KS2_LPSC_VCP2X4_F 44 -#define KS2_LPSC_VCP2X4_G 45 -#define KS2_LPSC_VCP2X4_H 46 -#define KS2_LPSC_BCP 47 -#define KS2_LPSC_DXB 48 -#define KS2_LPSC_VUSR1 49 -#define KS2_LPSC_XGE 50 -#define KS2_LPSC_ARM_SREFLEX 51 - -/* DDR3B definitions */ -#define KS2_DDR3B_EMIF_CTRL_BASE 0x21020000 -#define KS2_DDR3B_EMIF_DATA_BASE 0x60000000 -#define KS2_DDR3B_DDRPHYC 0x02328000 - -#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3 /* DDR3 ECC system irq number */ -#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D /* DDR3 ECC int mapped to CIC2 - channel 29 */ - -/* SGMII SerDes */ -#define KS2_LANES_PER_SGMII_SERDES 4 - -/* Number of DSP cores */ -#define KS2_NUM_DSPS 8 - -/* NETCP pktdma */ -#define KS2_NETCP_PDMA_CTRL_BASE 0x02004000 -#define KS2_NETCP_PDMA_TX_BASE 0x02004400 -#define KS2_NETCP_PDMA_TX_CH_NUM 9 -#define KS2_NETCP_PDMA_RX_BASE 0x02004800 -#define KS2_NETCP_PDMA_RX_CH_NUM 26 -#define KS2_NETCP_PDMA_SCHED_BASE 0x02004c00 -#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x02005000 -#define KS2_NETCP_PDMA_RX_FLOW_NUM 32 -#define KS2_NETCP_PDMA_TX_SND_QUEUE 648 - -/* NETCP */ -#define KS2_NETCP_BASE 0x02000000 - -#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2l.h b/arch/arm/include/asm/arch-keystone/hardware-k2l.h deleted file mode 100644 index 4f1197ea92..0000000000 --- a/arch/arm/include/asm/arch-keystone/hardware-k2l.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * K2L: SoC definitions - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_HARDWARE_K2L_H -#define __ASM_ARCH_HARDWARE_K2L_H - -#define KS2_ARM_PLL_EN BIT(13) - -/* PA SS Registers */ -#define KS2_PASS_BASE 0x26000000 - -/* Power and Sleep Controller (PSC) Domains */ -#define KS2_LPSC_MOD 0 -#define KS2_LPSC_DFE_IQN_SYS 1 -#define KS2_LPSC_USB 2 -#define KS2_LPSC_EMIF25_SPI 3 -#define KS2_LPSC_TSIP 4 -#define KS2_LPSC_DEBUGSS_TRC 5 -#define KS2_LPSC_TETB_TRC 6 -#define KS2_LPSC_PKTPROC 7 -#define KS2_LPSC_PA KS2_LPSC_PKTPROC -#define KS2_LPSC_SGMII 8 -#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII -#define KS2_LPSC_CRYPTO 9 -#define KS2_LPSC_PCIE0 10 -#define KS2_LPSC_PCIE1 11 -#define KS2_LPSC_JESD_MISC 12 -#define KS2_LPSC_CHIP_SRSS 13 -#define KS2_LPSC_MSMC 14 -#define KS2_LPSC_GEM_1 16 -#define KS2_LPSC_GEM_2 17 -#define KS2_LPSC_GEM_3 18 -#define KS2_LPSC_EMIF4F_DDR3 23 -#define KS2_LPSC_TAC 25 -#define KS2_LPSC_RAC 26 -#define KS2_LPSC_DDUC4X_CFR2X_BB 27 -#define KS2_LPSC_FFTC_A 28 -#define KS2_LPSC_OSR 34 -#define KS2_LPSC_TCP3D_0 35 -#define KS2_LPSC_TCP3D_1 37 -#define KS2_LPSC_VCP2X4_A 39 -#define KS2_LPSC_VCP2X4_B 40 -#define KS2_LPSC_VCP2X4_C 41 -#define KS2_LPSC_VCP2X4_D 42 -#define KS2_LPSC_BCP 47 -#define KS2_LPSC_DPD4X 48 -#define KS2_LPSC_FFTC_B 49 -#define KS2_LPSC_IQN_AIL 50 - -/* MSMC */ -#define KS2_MSMC_SEGMENT_PCIE1 14 - -/* Chip Interrupt Controller */ -#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3 -#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D - -/* OSR */ -#define KS2_OSR_DATA_BASE 0x70000000 /* OSR data base */ -#define KS2_OSR_CFG_BASE 0x02348c00 /* OSR config base */ -#define KS2_OSR_ECC_VEC 0x08 /* ECC Vector reg */ -#define KS2_OSR_ECC_CTRL 0x14 /* ECC control reg */ - -/* OSR ECC Vector register */ -#define KS2_OSR_ECC_VEC_TRIG_RD BIT(15) /* trigger a read op */ -#define KS2_OSR_ECC_VEC_RD_DONE BIT(24) /* read complete */ - -#define KS2_OSR_ECC_VEC_RAM_ID_SH 0 /* RAM ID shift */ -#define KS2_OSR_ECC_VEC_RD_ADDR_SH 16 /* read address shift */ - -/* OSR ECC control register */ -#define KS2_OSR_ECC_CTRL_EN BIT(0) /* ECC enable bit */ -#define KS2_OSR_ECC_CTRL_CHK BIT(1) /* ECC check bit */ -#define KS2_OSR_ECC_CTRL_RMW BIT(2) /* ECC check bit */ - -/* Number of OSR RAM banks */ -#define KS2_OSR_NUM_RAM_BANKS 4 - -/* OSR memory size */ -#define KS2_OSR_SIZE 0x100000 - -/* SGMII SerDes */ -#define KS2_SGMII_SERDES2_BASE 0x02320000 -#define KS2_LANES_PER_SGMII_SERDES 2 - -/* Number of DSP cores */ -#define KS2_NUM_DSPS 4 - -/* NETCP pktdma */ -#define KS2_NETCP_PDMA_CTRL_BASE 0x26186000 -#define KS2_NETCP_PDMA_TX_BASE 0x26187000 -#define KS2_NETCP_PDMA_TX_CH_NUM 21 -#define KS2_NETCP_PDMA_RX_BASE 0x26188000 -#define KS2_NETCP_PDMA_RX_CH_NUM 91 -#define KS2_NETCP_PDMA_SCHED_BASE 0x26186100 -#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x26189000 -#define KS2_NETCP_PDMA_RX_FLOW_NUM 96 -#define KS2_NETCP_PDMA_TX_SND_QUEUE 896 - -/* NETCP */ -#define KS2_NETCP_BASE 0x26000000 - -#endif /* __ASM_ARCH_HARDWARE_K2L_H */ diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h deleted file mode 100644 index 16cbcee12b..0000000000 --- a/arch/arm/include/asm/arch-keystone/hardware.h +++ /dev/null @@ -1,290 +0,0 @@ -/* - * Keystone2: Common SoC definitions, structures etc. - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include - -#ifndef __ASSEMBLY__ - -#include -#include - -#define REG(addr) (*(volatile unsigned int *)(addr)) -#define REG_P(addr) ((volatile unsigned int *)(addr)) - -typedef volatile unsigned int dv_reg; -typedef volatile unsigned int *dv_reg_p; - -#endif - -#define BIT(x) (1 << (x)) - -#define KS2_DDRPHY_PIR_OFFSET 0x04 -#define KS2_DDRPHY_PGCR0_OFFSET 0x08 -#define KS2_DDRPHY_PGCR1_OFFSET 0x0C -#define KS2_DDRPHY_PGSR0_OFFSET 0x10 -#define KS2_DDRPHY_PGSR1_OFFSET 0x14 -#define KS2_DDRPHY_PLLCR_OFFSET 0x18 -#define KS2_DDRPHY_PTR0_OFFSET 0x1C -#define KS2_DDRPHY_PTR1_OFFSET 0x20 -#define KS2_DDRPHY_PTR2_OFFSET 0x24 -#define KS2_DDRPHY_PTR3_OFFSET 0x28 -#define KS2_DDRPHY_PTR4_OFFSET 0x2C -#define KS2_DDRPHY_DCR_OFFSET 0x44 - -#define KS2_DDRPHY_DTPR0_OFFSET 0x48 -#define KS2_DDRPHY_DTPR1_OFFSET 0x4C -#define KS2_DDRPHY_DTPR2_OFFSET 0x50 - -#define KS2_DDRPHY_MR0_OFFSET 0x54 -#define KS2_DDRPHY_MR1_OFFSET 0x58 -#define KS2_DDRPHY_MR2_OFFSET 0x5C -#define KS2_DDRPHY_DTCR_OFFSET 0x68 -#define KS2_DDRPHY_PGCR2_OFFSET 0x8C - -#define KS2_DDRPHY_ZQ0CR1_OFFSET 0x184 -#define KS2_DDRPHY_ZQ1CR1_OFFSET 0x194 -#define KS2_DDRPHY_ZQ2CR1_OFFSET 0x1A4 -#define KS2_DDRPHY_ZQ3CR1_OFFSET 0x1B4 - -#define KS2_DDRPHY_DATX8_8_OFFSET 0x3C0 - -#define IODDRM_MASK 0x00000180 -#define ZCKSEL_MASK 0x01800000 -#define CL_MASK 0x00000072 -#define WR_MASK 0x00000E00 -#define BL_MASK 0x00000003 -#define RRMODE_MASK 0x00040000 -#define UDIMM_MASK 0x20000000 -#define BYTEMASK_MASK 0x0003FC00 -#define MPRDQ_MASK 0x00000080 -#define PDQ_MASK 0x00000070 -#define NOSRA_MASK 0x08000000 -#define ECC_MASK 0x00000001 - -/* DDR3 definitions */ -#define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000 -#define KS2_DDR3A_EMIF_DATA_BASE 0x80000000 -#define KS2_DDR3A_DDRPHYC 0x02329000 - -#define KS2_DDR3_MIDR_OFFSET 0x00 -#define KS2_DDR3_STATUS_OFFSET 0x04 -#define KS2_DDR3_SDCFG_OFFSET 0x08 -#define KS2_DDR3_SDRFC_OFFSET 0x10 -#define KS2_DDR3_SDTIM1_OFFSET 0x18 -#define KS2_DDR3_SDTIM2_OFFSET 0x1C -#define KS2_DDR3_SDTIM3_OFFSET 0x20 -#define KS2_DDR3_SDTIM4_OFFSET 0x28 -#define KS2_DDR3_PMCTL_OFFSET 0x38 -#define KS2_DDR3_ZQCFG_OFFSET 0xC8 - -#define KS2_DDR3_PLLCTRL_PHY_RESET 0x80000000 - -/* DDR3 ECC */ -#define KS2_DDR3_ECC_INT_STATUS_OFFSET 0x0AC -#define KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET 0x0B4 -#define KS2_DDR3_ECC_CTRL_OFFSET 0x110 -#define KS2_DDR3_ECC_ADDR_RANGE1_OFFSET 0x114 -#define KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET 0x130 -#define KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET 0x13C - -/* DDR3 ECC Interrupt Status register */ -#define KS2_DDR3_1B_ECC_ERR_SYS BIT(5) -#define KS2_DDR3_2B_ECC_ERR_SYS BIT(4) -#define KS2_DDR3_WR_ECC_ERR_SYS BIT(3) - -/* DDR3 ECC Control register */ -#define KS2_DDR3_ECC_EN BIT(31) -#define KS2_DDR3_ECC_ADDR_RNG_PROT BIT(30) -#define KS2_DDR3_ECC_VERIFY_EN BIT(29) -#define KS2_DDR3_ECC_RMW_EN BIT(28) -#define KS2_DDR3_ECC_ADDR_RNG_1_EN BIT(0) - -#define KS2_DDR3_ECC_ENABLE (KS2_DDR3_ECC_EN | \ - KS2_DDR3_ECC_ADDR_RNG_PROT | \ - KS2_DDR3_ECC_VERIFY_EN) - -/* EDMA */ -#define KS2_EDMA0_BASE 0x02700000 - -/* EDMA3 register offsets */ -#define KS2_EDMA_QCHMAP0 0x0200 -#define KS2_EDMA_IPR 0x1068 -#define KS2_EDMA_ICR 0x1070 -#define KS2_EDMA_QEECR 0x1088 -#define KS2_EDMA_QEESR 0x108c -#define KS2_EDMA_PARAM_1(x) (0x4020 + (4 * x)) - -/* NETCP pktdma */ -#define KS2_NETCP_PDMA_RX_FREE_QUEUE 4001 -#define KS2_NETCP_PDMA_RX_RCV_QUEUE 4002 - -/* Chip Interrupt Controller */ -#define KS2_CIC2_BASE 0x02608000 - -/* Chip Interrupt Controller register offsets */ -#define KS2_CIC_CTRL 0x04 -#define KS2_CIC_HOST_CTRL 0x0C -#define KS2_CIC_GLOBAL_ENABLE 0x10 -#define KS2_CIC_SYS_ENABLE_IDX_SET 0x28 -#define KS2_CIC_HOST_ENABLE_IDX_SET 0x34 -#define KS2_CIC_CHAN_MAP(n) (0x0400 + (n << 2)) - -#define KS2_UART0_BASE 0x02530c00 -#define KS2_UART1_BASE 0x02531000 - -/* Boot Config */ -#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000 -#define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18) -#define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20) -#define KS2_DEVCFG (KS2_DEVICE_STATE_CTRL_BASE + 0x14c) - -/* PSC */ -#define KS2_PSC_BASE 0x02350000 -#define KS2_LPSC_GEM_0 15 -#define KS2_LPSC_TETRIS 52 -#define KS2_TETRIS_PWR_DOMAIN 31 - -/* Chip configuration unlock codes and registers */ -#define KS2_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38) -#define KS2_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c) -#define KS2_KICK0_MAGIC 0x83e70b13 -#define KS2_KICK1_MAGIC 0x95a4f1e0 - -/* PLL control registers */ -#define KS2_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350) -#define KS2_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354) -#define KS2_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358) -#define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C) -#define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360) -#define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364) -#define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370) -#define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374) - -#define KS2_PLL_CNTRL_BASE 0x02310000 -#define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE -#define KS2_RSTCTRL_RSTYPE (KS2_PLL_CNTRL_BASE + 0xe4) -#define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8) -#define KS2_RSTCTRL_RSCFG (KS2_PLL_CNTRL_BASE + 0xec) -#define KS2_RSTCTRL_KEY 0x5a69 -#define KS2_RSTCTRL_MASK 0xffff0000 -#define KS2_RSTCTRL_SWRST 0xfffe0000 -#define KS2_RSTYPE_PLL_SOFT BIT(13) - -/* SPI */ -#define KS2_SPI0_BASE 0x21000400 -#define KS2_SPI1_BASE 0x21000600 -#define KS2_SPI2_BASE 0x21000800 -#define KS2_SPI_BASE KS2_SPI0_BASE - -/* AEMIF */ -#define KS2_AEMIF_CNTRL_BASE 0x21000a00 -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE - -/* Flag from ks2_debug options to check if DSPs need to stay ON */ -#define DBG_LEAVE_DSPS_ON 0x1 - -/* MSMC control */ -#define KS2_MSMC_CTRL_BASE 0x0bc00000 -#define KS2_MSMC_DATA_BASE 0x0c000000 -#define KS2_MSMC_SEGMENT_TETRIS 8 -#define KS2_MSMC_SEGMENT_NETCP 9 -#define KS2_MSMC_SEGMENT_QM_PDSP 10 -#define KS2_MSMC_SEGMENT_PCIE0 11 - -/* MSMC segment size shift bits */ -#define KS2_MSMC_SEG_SIZE_SHIFT 12 -#define KS2_MSMC_MAP_SEG_NUM (2 << (30 - KS2_MSMC_SEG_SIZE_SHIFT)) -#define KS2_MSMC_DST_SEG_BASE (CONFIG_SYS_LPAE_SDRAM_BASE >> \ - KS2_MSMC_SEG_SIZE_SHIFT) - -/* Device speed */ -#define KS2_REV1_DEVSPEED (KS2_DEVICE_STATE_CTRL_BASE + 0xc98) -#define KS2_EFUSE_BOOTROM (KS2_DEVICE_STATE_CTRL_BASE + 0xc90) -#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c) - -/* Queue manager */ -#define KS2_QM_BASE_ADDRESS 0x23a80000 -#define KS2_QM_CONF_BASE 0x02a02000 -#define KS2_QM_DESC_SETUP_BASE 0x02a03000 -#define KS2_QM_STATUS_RAM_BASE 0x02a06000 -#define KS2_QM_INTD_CONF_BASE 0x02a0c000 -#define KS2_QM_PDSP1_CMD_BASE 0x02a20000 -#define KS2_QM_PDSP1_CTRL_BASE 0x02a0f000 -#define KS2_QM_PDSP1_IRAM_BASE 0x02a10000 -#define KS2_QM_MANAGER_QUEUES_BASE 0x02a80000 -#define KS2_QM_MANAGER_Q_PROXY_BASE 0x02ac0000 -#define KS2_QM_QUEUE_STATUS_BASE 0x02a40000 -#define KS2_QM_LINK_RAM_BASE 0x00100000 -#define KS2_QM_REGION_NUM 64 -#define KS2_QM_QPOOL_NUM 4000 - -/* USB */ -#define KS2_USB_SS_BASE 0x02680000 -#define KS2_USB_HOST_XHCI_BASE (KS2_USB_SS_BASE + 0x10000) -#define KS2_DEV_USB_PHY_BASE 0x02620738 -#define KS2_USB_PHY_CFG_BASE 0x02630000 - -#define KS2_MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110) - -/* SGMII SerDes */ -#define KS2_SGMII_SERDES_BASE 0x0232a000 - -#ifdef CONFIG_SOC_K2HK -#include -#endif - -#ifdef CONFIG_SOC_K2E -#include -#endif - -#ifdef CONFIG_SOC_K2L -#include -#endif - -#ifndef __ASSEMBLY__ -static inline int cpu_is_k2hk(void) -{ - unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG); - unsigned int part_no = (jtag_id >> 12) & 0xffff; - - return (part_no == 0xb981) ? 1 : 0; -} - -static inline int cpu_is_k2e(void) -{ - unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG); - unsigned int part_no = (jtag_id >> 12) & 0xffff; - - return (part_no == 0xb9a6) ? 1 : 0; -} - -static inline int cpu_is_k2l(void) -{ - unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG); - unsigned int part_no = (jtag_id >> 12) & 0xffff; - - return (part_no == 0xb9a7) ? 1 : 0; -} - -static inline int cpu_revision(void) -{ - unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG); - unsigned int rev = (jtag_id >> 28) & 0xf; - - return rev; -} - -int cpu_to_bus(u32 *ptr, u32 length); -void sdelay(unsigned long); - -#endif - -#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-keystone/i2c_defs.h b/arch/arm/include/asm/arch-keystone/i2c_defs.h deleted file mode 100644 index d4256526cc..0000000000 --- a/arch/arm/include/asm/arch-keystone/i2c_defs.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * keystone: i2c driver definitions - * - * (C) Copyright 2014 - * Texas Instruments Incorporated, - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _I2C_DEFS_H_ -#define _I2C_DEFS_H_ - -#define I2C0_BASE 0x02530000 -#define I2C1_BASE 0x02530400 -#define I2C2_BASE 0x02530800 -#define I2C_BASE I2C0_BASE - -#endif diff --git a/arch/arm/include/asm/arch-keystone/mon.h b/arch/arm/include/asm/arch-keystone/mon.h deleted file mode 100644 index 33a28764bc..0000000000 --- a/arch/arm/include/asm/arch-keystone/mon.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * K2HK: secure kernel command header file - * - * (C) Copyright 2014 - * Texas Instruments Incorporated, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _MON_H_ -#define _MON_H_ - -int mon_power_off(int core_id); - -#endif diff --git a/arch/arm/include/asm/arch-keystone/msmc.h b/arch/arm/include/asm/arch-keystone/msmc.h deleted file mode 100644 index 083f5ba052..0000000000 --- a/arch/arm/include/asm/arch-keystone/msmc.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * MSMC controller - * - * (C) Copyright 2014 - * Texas Instruments Incorporated, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _MSMC_H_ -#define _MSMC_H_ - -#include - -enum mpax_seg_size { - MPAX_SEG_4K = 0x0b, - MPAX_SEG_8K, - MPAX_SEG_16K, - MPAX_SEG_32K, - MPAX_SEG_64K, - MPAX_SEG_128K, - MPAX_SEG_256K, - MPAX_SEG_512K, - MPAX_SEG_1M, - MPAX_SEG_2M, - MPAX_SEG_4M, - MPAX_SEG_8M, - MPAX_SEG_16M, - MPAX_SEG_32M, - MPAX_SEG_64M, - MPAX_SEG_128M, - MPAX_SEG_256M, - MPAX_SEG_512M, - MPAX_SEG_1G, - MPAX_SEG_2G, - MPAX_SEG_4G -}; - -void msmc_share_all_segments(int priv_id); -void msmc_get_ses_mpax(int priv_id, int ses_pair, u32 *mpax); -void msmc_set_ses_mpax(int priv_id, int ses_pair, u32 *mpax); -void msmc_map_ses_segment(int priv_id, int ses_pair, - u32 src_pfn, u32 dst_pfn, enum mpax_seg_size size); - -#endif diff --git a/arch/arm/include/asm/arch-keystone/psc_defs.h b/arch/arm/include/asm/arch-keystone/psc_defs.h deleted file mode 100644 index 70d22cf217..0000000000 --- a/arch/arm/include/asm/arch-keystone/psc_defs.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _PSC_DEFS_H_ -#define _PSC_DEFS_H_ - -#include - -/* - * FILE PURPOSE: Local Power Sleep Controller definitions - * - * FILE NAME: psc_defs.h - * - * DESCRIPTION: Provides local definitions for the power saver controller - * - */ - -/* Register offsets */ -#define PSC_REG_PTCMD 0x120 -#define PSC_REG_PSTAT 0x128 -#define PSC_REG_PDSTAT(x) (0x200 + (4 * (x))) -#define PSC_REG_PDCTL(x) (0x300 + (4 * (x))) -#define PSC_REG_MDCFG(x) (0x600 + (4 * (x))) -#define PSC_REG_MDSTAT(x) (0x800 + (4 * (x))) -#define PSC_REG_MDCTL(x) (0xa00 + (4 * (x))) - -#define BOOTBITMASK(x, y) ((((((u32)1 << (((u32)x) - ((u32)y) + (u32)1)) - \ - (u32)1)) << ((u32)y))) - -#define BOOT_READ_BITFIELD(z, x, y) (((u32)z) & BOOTBITMASK(x, y)) >> (y) -#define BOOT_SET_BITFIELD(z, f, x, y) (((u32)z) & ~BOOTBITMASK(x, y)) | \ - ((((u32)f) << (y)) & BOOTBITMASK(x, y)) - -/* PDCTL */ -#define PSC_REG_PDCTL_SET_NEXT(x, y) BOOT_SET_BITFIELD((x), (y), 0, 0) -#define PSC_REG_PDCTL_SET_PDMODE(x, y) BOOT_SET_BITFIELD((x), (y), 15, 12) - -/* PDSTAT */ -#define PSC_REG_PDSTAT_GET_STATE(x) BOOT_READ_BITFIELD((x), 4, 0) - -/* MDCFG */ -#define PSC_REG_MDCFG_GET_PD(x) BOOT_READ_BITFIELD((x), 20, 16) -#define PSC_REG_MDCFG_GET_RESET_ISO(x) BOOT_READ_BITFIELD((x), 14, 14) - -/* MDCTL */ -#define PSC_REG_MDCTL_SET_NEXT(x, y) BOOT_SET_BITFIELD((x), (y), 4, 0) -#define PSC_REG_MDCTL_SET_LRSTZ(x, y) BOOT_SET_BITFIELD((x), (y), 8, 8) -#define PSC_REG_MDCTL_GET_LRSTZ(x) BOOT_READ_BITFIELD((x), 8, 8) -#define PSC_REG_MDCTL_SET_RESET_ISO(x, y) BOOT_SET_BITFIELD((x), (y), \ - 12, 12) - -/* MDSTAT */ -#define PSC_REG_MDSTAT_GET_STATUS(x) BOOT_READ_BITFIELD((x), 5, 0) -#define PSC_REG_MDSTAT_GET_LRSTZ(x) BOOT_READ_BITFIELD((x), 8, 8) -#define PSC_REG_MDSTAT_GET_LRSTDONE(x) BOOT_READ_BITFIELD((x), 9, 9) - -/* PDCTL states */ -#define PSC_REG_VAL_PDCTL_NEXT_ON 1 -#define PSC_REG_VAL_PDCTL_NEXT_OFF 0 - -#define PSC_REG_VAL_PDCTL_PDMODE_SLEEP 0 - -/* MDCTL states */ -#define PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE 0 -#define PSC_REG_VAL_MDCTL_NEXT_OFF 2 -#define PSC_REG_VAL_MDCTL_NEXT_ON 3 - -/* MDSTAT states */ -#define PSC_REG_VAL_MDSTAT_STATE_ON 3 -#define PSC_REG_VAL_MDSTAT_STATE_ENABLE_IN_PROG 0x24 -#define PSC_REG_VAL_MDSTAT_STATE_OFF 2 -#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG1 0x20 -#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG2 0x21 -#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG3 0x22 - -/* - * Timeout limit on checking PTSTAT. This is the number of times the - * wait function will be called before giving up. - */ -#define PSC_PTSTAT_TIMEOUT_LIMIT 100 - -u32 psc_get_domain_num(u32 mod_num); -int psc_enable_module(u32 mod_num); -int psc_disable_module(u32 mod_num); -int psc_disable_domain(u32 domain_num); - -#endif /* _PSC_DEFS_H_ */ diff --git a/arch/arm/include/asm/arch-keystone/xhci-keystone.h b/arch/arm/include/asm/arch-keystone/xhci-keystone.h deleted file mode 100644 index 3aab4e045f..0000000000 --- a/arch/arm/include/asm/arch-keystone/xhci-keystone.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * USB 3.0 DRD Controller - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define USB3_PHY_REF_SSP_EN BIT(29) -#define USB3_PHY_OTG_VBUSVLDECTSEL BIT(16) - -/* KEYSTONE2 XHCI PHY register structure */ -struct keystone_xhci_phy { - unsigned int phy_utmi; /* ctl0 */ - unsigned int phy_pipe; /* ctl1 */ - unsigned int phy_param_ctrl_1; /* ctl2 */ - unsigned int phy_param_ctrl_2; /* ctl3 */ - unsigned int phy_clock; /* ctl4 */ - unsigned int phy_pll; /* ctl5 */ -}; diff --git a/arch/arm/mach-keystone/include/mach/clock-k2e.h b/arch/arm/mach-keystone/include/mach/clock-k2e.h new file mode 100644 index 0000000000..d013b830ed --- /dev/null +++ b/arch/arm/mach-keystone/include/mach/clock-k2e.h @@ -0,0 +1,85 @@ +/* + * K2E: Clock management APIs + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_CLOCK_K2E_H +#define __ASM_ARCH_CLOCK_K2E_H + +enum ext_clk_e { + sys_clk, + alt_core_clk, + pa_clk, + ddr3_clk, + mcm_clk, + pcie_clk, + sgmii_clk, + xgmii_clk, + usb_clk, + ext_clk_count /* number of external clocks */ +}; + +extern unsigned int external_clk[ext_clk_count]; + +#define CLK_LIST(CLK)\ + CLK(0, core_pll_clk)\ + CLK(1, pass_pll_clk)\ + CLK(2, ddr3_pll_clk)\ + CLK(3, sys_clk0_clk)\ + CLK(4, sys_clk0_1_clk)\ + CLK(5, sys_clk0_2_clk)\ + CLK(6, sys_clk0_3_clk)\ + CLK(7, sys_clk0_4_clk)\ + CLK(8, sys_clk0_6_clk)\ + CLK(9, sys_clk0_8_clk)\ + CLK(10, sys_clk0_12_clk)\ + CLK(11, sys_clk0_24_clk)\ + CLK(12, sys_clk1_clk)\ + CLK(13, sys_clk1_3_clk)\ + CLK(14, sys_clk1_4_clk)\ + CLK(15, sys_clk1_6_clk)\ + CLK(16, sys_clk1_12_clk)\ + CLK(17, sys_clk2_clk)\ + CLK(18, sys_clk3_clk) + +#define PLLSET_CMD_LIST "" + +#define KS2_CLK1_6 sys_clk0_6_clk + +/* PLL identifiers */ +enum pll_type_e { + CORE_PLL, + PASS_PLL, + DDR3_PLL, +}; + +enum { + SPD800, + SPD850, + SPD1000, + SPD1250, + SPD1350, + SPD1400, + SPD1500, + SPD_RSV +}; + +#define CORE_PLL_800 {CORE_PLL, 16, 1, 2} +#define CORE_PLL_850 {CORE_PLL, 17, 1, 2} +#define CORE_PLL_1000 {CORE_PLL, 20, 1, 2} +#define CORE_PLL_1200 {CORE_PLL, 24, 1, 2} +#define PASS_PLL_1000 {PASS_PLL, 20, 1, 2} +#define CORE_PLL_1250 {CORE_PLL, 25, 1, 2} +#define CORE_PLL_1350 {CORE_PLL, 27, 1, 2} +#define CORE_PLL_1400 {CORE_PLL, 28, 1, 2} +#define CORE_PLL_1500 {CORE_PLL, 30, 1, 2} +#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2} +#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4} +#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2} +#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6} + +#endif diff --git a/arch/arm/mach-keystone/include/mach/clock-k2hk.h b/arch/arm/mach-keystone/include/mach/clock-k2hk.h new file mode 100644 index 0000000000..f28d5f0c4e --- /dev/null +++ b/arch/arm/mach-keystone/include/mach/clock-k2hk.h @@ -0,0 +1,103 @@ +/* + * K2HK: Clock management APIs + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_CLOCK_K2HK_H +#define __ASM_ARCH_CLOCK_K2HK_H + +enum ext_clk_e { + sys_clk, + alt_core_clk, + pa_clk, + tetris_clk, + ddr3a_clk, + ddr3b_clk, + mcm_clk, + pcie_clk, + sgmii_srio_clk, + xgmii_clk, + usb_clk, + rp1_clk, + ext_clk_count /* number of external clocks */ +}; + +extern unsigned int external_clk[ext_clk_count]; + +#define CLK_LIST(CLK)\ + CLK(0, core_pll_clk)\ + CLK(1, pass_pll_clk)\ + CLK(2, tetris_pll_clk)\ + CLK(3, ddr3a_pll_clk)\ + CLK(4, ddr3b_pll_clk)\ + CLK(5, sys_clk0_clk)\ + CLK(6, sys_clk0_1_clk)\ + CLK(7, sys_clk0_2_clk)\ + CLK(8, sys_clk0_3_clk)\ + CLK(9, sys_clk0_4_clk)\ + CLK(10, sys_clk0_6_clk)\ + CLK(11, sys_clk0_8_clk)\ + CLK(12, sys_clk0_12_clk)\ + CLK(13, sys_clk0_24_clk)\ + CLK(14, sys_clk1_clk)\ + CLK(15, sys_clk1_3_clk)\ + CLK(16, sys_clk1_4_clk)\ + CLK(17, sys_clk1_6_clk)\ + CLK(18, sys_clk1_12_clk)\ + CLK(19, sys_clk2_clk)\ + CLK(20, sys_clk3_clk) + +#define PLLSET_CMD_LIST "" + +#define KS2_CLK1_6 sys_clk0_6_clk + +/* PLL identifiers */ +enum pll_type_e { + CORE_PLL, + PASS_PLL, + TETRIS_PLL, + DDR3A_PLL, + DDR3B_PLL, +}; + +enum { + SPD800, + SPD1000, + SPD1200, + SPD1350, + SPD1400, + SPD_RSV +}; + +#define CORE_PLL_799 {CORE_PLL, 13, 1, 2} +#define CORE_PLL_983 {CORE_PLL, 16, 1, 2} +#define CORE_PLL_999 {CORE_PLL, 122, 15, 1} +#define CORE_PLL_1167 {CORE_PLL, 19, 1, 2} +#define CORE_PLL_1228 {CORE_PLL, 20, 1, 2} +#define CORE_PLL_1200 {CORE_PLL, 625, 32, 2} +#define PASS_PLL_1228 {PASS_PLL, 20, 1, 2} +#define PASS_PLL_983 {PASS_PLL, 16, 1, 2} +#define PASS_PLL_1050 {PASS_PLL, 205, 12, 2} +#define TETRIS_PLL_500 {TETRIS_PLL, 8, 1, 2} +#define TETRIS_PLL_750 {TETRIS_PLL, 12, 1, 2} +#define TETRIS_PLL_800 {TETRIS_PLL, 32, 5, 1} +#define TETRIS_PLL_687 {TETRIS_PLL, 11, 1, 2} +#define TETRIS_PLL_625 {TETRIS_PLL, 10, 1, 2} +#define TETRIS_PLL_812 {TETRIS_PLL, 13, 1, 2} +#define TETRIS_PLL_875 {TETRIS_PLL, 14, 1, 2} +#define TETRIS_PLL_1000 {TETRIS_PLL, 40, 5, 1} +#define TETRIS_PLL_1188 {TETRIS_PLL, 19, 2, 1} +#define TETRIS_PLL_1200 {TETRIS_PLL, 48, 5, 1} +#define TETRIS_PLL_1350 {TETRIS_PLL, 54, 5, 1} +#define TETRIS_PLL_1375 {TETRIS_PLL, 22, 2, 1} +#define TETRIS_PLL_1400 {TETRIS_PLL, 56, 5, 1} +#define DDR3_PLL_200(x) {DDR3##x##_PLL, 4, 1, 2} +#define DDR3_PLL_400(x) {DDR3##x##_PLL, 16, 1, 4} +#define DDR3_PLL_800(x) {DDR3##x##_PLL, 16, 1, 2} +#define DDR3_PLL_333(x) {DDR3##x##_PLL, 20, 1, 6} + +#endif diff --git a/arch/arm/mach-keystone/include/mach/clock-k2l.h b/arch/arm/mach-keystone/include/mach/clock-k2l.h new file mode 100644 index 0000000000..bb9a5c4dcf --- /dev/null +++ b/arch/arm/mach-keystone/include/mach/clock-k2l.h @@ -0,0 +1,95 @@ +/* + * K2L: Clock management APIs + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_CLOCK_K2L_H +#define __ASM_ARCH_CLOCK_K2L_H + +enum ext_clk_e { + sys_clk, + alt_core_clk, + pa_clk, + tetris_clk, + ddr3_clk, + pcie_clk, + sgmii_clk, + usb_clk, + rp1_clk, + ext_clk_count /* number of external clocks */ +}; + +extern unsigned int external_clk[ext_clk_count]; + +#define CLK_LIST(CLK)\ + CLK(0, core_pll_clk)\ + CLK(1, pass_pll_clk)\ + CLK(2, tetris_pll_clk)\ + CLK(3, ddr3_pll_clk)\ + CLK(4, sys_clk0_clk)\ + CLK(5, sys_clk0_1_clk)\ + CLK(6, sys_clk0_2_clk)\ + CLK(7, sys_clk0_3_clk)\ + CLK(8, sys_clk0_4_clk)\ + CLK(9, sys_clk0_6_clk)\ + CLK(10, sys_clk0_8_clk)\ + CLK(11, sys_clk0_12_clk)\ + CLK(12, sys_clk0_24_clk)\ + CLK(13, sys_clk1_clk)\ + CLK(14, sys_clk1_3_clk)\ + CLK(15, sys_clk1_4_clk)\ + CLK(16, sys_clk1_6_clk)\ + CLK(17, sys_clk1_12_clk)\ + CLK(18, sys_clk2_clk)\ + CLK(19, sys_clk3_clk)\ + +#define PLLSET_CMD_LIST "" + +#define KS2_CLK1_6 sys_clk0_6_clk + +/* PLL identifiers */ +enum pll_type_e { + CORE_PLL, + PASS_PLL, + TETRIS_PLL, + DDR3_PLL, +}; + +enum { + SPD800, + SPD1000, + SPD1200, + SPD1350, + SPD1400, + SPD_RSV +}; + +#define CORE_PLL_799 {CORE_PLL, 13, 1, 2} +#define CORE_PLL_983 {CORE_PLL, 16, 1, 2} +#define CORE_PLL_1000 {CORE_PLL, 114, 7, 2} +#define CORE_PLL_1167 {CORE_PLL, 19, 1, 2} +#define CORE_PLL_1198 {CORE_PLL, 39, 2, 2} +#define CORE_PLL_1228 {CORE_PLL, 20, 1, 2} +#define PASS_PLL_1228 {PASS_PLL, 20, 1, 2} +#define PASS_PLL_983 {PASS_PLL, 16, 1, 2} +#define PASS_PLL_1050 {PASS_PLL, 205, 12, 2} +#define TETRIS_PLL_491 {TETRIS_PLL, 8, 1, 2} +#define TETRIS_PLL_737 {TETRIS_PLL, 12, 1, 2} +#define TETRIS_PLL_799 {TETRIS_PLL, 13, 1, 2} +#define TETRIS_PLL_983 {TETRIS_PLL, 16, 1, 2} +#define TETRIS_PLL_1000 {TETRIS_PLL, 114, 7, 2} +#define TETRIS_PLL_1167 {TETRIS_PLL, 19, 1, 2} +#define TETRIS_PLL_1198 {TETRIS_PLL, 39, 2, 2} +#define TETRIS_PLL_1228 {TETRIS_PLL, 20, 1, 2} +#define TETRIS_PLL_1352 {TETRIS_PLL, 22, 1, 2} +#define TETRIS_PLL_1401 {TETRIS_PLL, 114, 5, 2} +#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2} +#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4} +#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2} +#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6} + +#endif diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h new file mode 100644 index 0000000000..9f6cfb265f --- /dev/null +++ b/arch/arm/mach-keystone/include/mach/clock.h @@ -0,0 +1,66 @@ +/* + * keystone2: common clock header file + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_CLOCK_H +#define __ASM_ARCH_CLOCK_H + +#ifndef __ASSEMBLY__ + +#ifdef CONFIG_SOC_K2HK +#include +#endif + +#ifdef CONFIG_SOC_K2E +#include +#endif + +#ifdef CONFIG_SOC_K2L +#include +#endif + +#define MAIN_PLL CORE_PLL + +#include + +#define GENERATE_ENUM(NUM, ENUM) ENUM = NUM, +#define GENERATE_INDX_STR(NUM, STRING) #NUM"\t- "#STRING"\n" +#define CLOCK_INDEXES_LIST CLK_LIST(GENERATE_INDX_STR) + +enum clk_e { + CLK_LIST(GENERATE_ENUM) +}; + +struct keystone_pll_regs { + u32 reg0; + u32 reg1; +}; + +/* PLL configuration data */ +struct pll_init_data { + int pll; + int pll_m; /* PLL Multiplier */ + int pll_d; /* PLL divider */ + int pll_od; /* PLL output divider */ +}; + +extern const struct keystone_pll_regs keystone_pll_regs[]; +extern int dev_speeds[]; +extern int arm_speeds[]; + +void init_plls(int num_pll, struct pll_init_data *config); +void init_pll(const struct pll_init_data *data); +unsigned long clk_get_rate(unsigned int clk); +unsigned long clk_round_rate(unsigned int clk, unsigned long hz); +int clk_set_rate(unsigned int clk, unsigned long hz); +void pass_pll_pa_clk_enable(void); +int get_max_dev_speed(void); +int get_max_arm_speed(void); + +#endif +#endif diff --git a/arch/arm/mach-keystone/include/mach/clock_defs.h b/arch/arm/mach-keystone/include/mach/clock_defs.h new file mode 100644 index 0000000000..85a046b89a --- /dev/null +++ b/arch/arm/mach-keystone/include/mach/clock_defs.h @@ -0,0 +1,111 @@ +/* + * keystone2: common pll clock definitions + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CLOCK_DEFS_H_ +#define _CLOCK_DEFS_H_ + +#include + +#define BIT(x) (1 << (x)) + +/* PLL Control Registers */ +struct pllctl_regs { + u32 ctl; /* 00 */ + u32 ocsel; /* 04 */ + u32 secctl; /* 08 */ + u32 resv0; + u32 mult; /* 10 */ + u32 prediv; /* 14 */ + u32 div1; /* 18 */ + u32 div2; /* 1c */ + u32 div3; /* 20 */ + u32 oscdiv1; /* 24 */ + u32 resv1; /* 28 */ + u32 bpdiv; /* 2c */ + u32 wakeup; /* 30 */ + u32 resv2; + u32 cmd; /* 38 */ + u32 stat; /* 3c */ + u32 alnctl; /* 40 */ + u32 dchange; /* 44 */ + u32 cken; /* 48 */ + u32 ckstat; /* 4c */ + u32 systat; /* 50 */ + u32 ckctl; /* 54 */ + u32 resv3[2]; + u32 div4; /* 60 */ + u32 div5; /* 64 */ + u32 div6; /* 68 */ + u32 div7; /* 6c */ + u32 div8; /* 70 */ + u32 div9; /* 74 */ + u32 div10; /* 78 */ + u32 div11; /* 7c */ + u32 div12; /* 80 */ +}; + +static struct pllctl_regs *pllctl_regs[] = { + (struct pllctl_regs *)(KS2_CLOCK_BASE + 0x100) +}; + +#define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg)) +#define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg)) +#define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg)) + +#define pllctl_reg_rmw(pll, reg, mask, val) \ + pllctl_reg_write(pll, reg, \ + (pllctl_reg_read(pll, reg) & ~(mask)) | val) + +#define pllctl_reg_setbits(pll, reg, mask) \ + pllctl_reg_rmw(pll, reg, 0, mask) + +#define pllctl_reg_clrbits(pll, reg, mask) \ + pllctl_reg_rmw(pll, reg, mask, 0) + +#define pll0div_read(N) ((pllctl_reg_read(CORE_PLL, div##N) & 0xff) + 1) + +/* PLLCTL Bits */ +#define PLLCTL_BYPASS BIT(23) +#define PLL_PLLRST BIT(14) +#define PLLCTL_PAPLL BIT(13) +#define PLLCTL_CLKMODE BIT(8) +#define PLLCTL_PLLSELB BIT(7) +#define PLLCTL_ENSAT BIT(6) +#define PLLCTL_PLLENSRC BIT(5) +#define PLLCTL_PLLDIS BIT(4) +#define PLLCTL_PLLRST BIT(3) +#define PLLCTL_PLLPWRDN BIT(1) +#define PLLCTL_PLLEN BIT(0) +#define PLLSTAT_GO BIT(0) + +#define MAIN_ENSAT_OFFSET 6 + +#define PLLDIV_ENABLE BIT(15) + +#define PLL_DIV_MASK 0x3f +#define PLL_MULT_MASK 0x1fff +#define PLL_MULT_SHIFT 6 +#define PLLM_MULT_HI_MASK 0x7f +#define PLLM_MULT_HI_SHIFT 12 +#define PLLM_MULT_HI_SMASK (PLLM_MULT_HI_MASK << PLLM_MULT_HI_SHIFT) +#define PLLM_MULT_LO_MASK 0x3f +#define PLL_CLKOD_MASK 0xf +#define PLL_CLKOD_SHIFT 19 +#define PLL_CLKOD_SMASK (PLL_CLKOD_MASK << PLL_CLKOD_SHIFT) +#define PLL_BWADJ_LO_MASK 0xff +#define PLL_BWADJ_LO_SHIFT 24 +#define PLL_BWADJ_LO_SMASK (PLL_BWADJ_LO_MASK << PLL_BWADJ_LO_SHIFT) +#define PLL_BWADJ_HI_MASK 0xf + +#define PLLM_RATIO_DIV1 (PLLDIV_ENABLE | 0x0) +#define PLLM_RATIO_DIV2 (PLLDIV_ENABLE | 0x0) +#define PLLM_RATIO_DIV3 (PLLDIV_ENABLE | 0x1) +#define PLLM_RATIO_DIV4 (PLLDIV_ENABLE | 0x4) +#define PLLM_RATIO_DIV5 (PLLDIV_ENABLE | 0x17) + +#endif /* _CLOCK_DEFS_H_ */ diff --git a/arch/arm/mach-keystone/include/mach/ddr3.h b/arch/arm/mach-keystone/include/mach/ddr3.h new file mode 100644 index 0000000000..a22c237c80 --- /dev/null +++ b/arch/arm/mach-keystone/include/mach/ddr3.h @@ -0,0 +1,62 @@ +/* + * DDR3 + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DDR3_H_ +#define _DDR3_H_ + +#include + +struct ddr3_phy_config { + unsigned int pllcr; + unsigned int pgcr1_mask; + unsigned int pgcr1_val; + unsigned int ptr0; + unsigned int ptr1; + unsigned int ptr2; + unsigned int ptr3; + unsigned int ptr4; + unsigned int dcr_mask; + unsigned int dcr_val; + unsigned int dtpr0; + unsigned int dtpr1; + unsigned int dtpr2; + unsigned int mr0; + unsigned int mr1; + unsigned int mr2; + unsigned int dtcr; + unsigned int pgcr2; + unsigned int zq0cr1; + unsigned int zq1cr1; + unsigned int zq2cr1; + unsigned int pir_v1; + unsigned int pir_v2; +}; + +struct ddr3_emif_config { + unsigned int sdcfg; + unsigned int sdtim1; + unsigned int sdtim2; + unsigned int sdtim3; + unsigned int sdtim4; + unsigned int zqcfg; + unsigned int sdrfc; +}; + +u32 ddr3_init(void); +void ddr3_reset_ddrphy(void); +void ddr3_init_ecc(u32 base, u32 ddr3_size); +void ddr3_disable_ecc(u32 base); +void ddr3_check_ecc_int(u32 base); +int ddr3_ecc_support_rmw(u32 base); +void ddr3_err_reset_workaround(void); +void ddr3_enable_ecc(u32 base, int test); +void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg); +void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg); + +#endif diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2e.h b/arch/arm/mach-keystone/include/mach/hardware-k2e.h new file mode 100644 index 0000000000..df499957e5 --- /dev/null +++ b/arch/arm/mach-keystone/include/mach/hardware-k2e.h @@ -0,0 +1,65 @@ +/* + * K2E: SoC definitions + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_HARDWARE_K2E_H +#define __ASM_ARCH_HARDWARE_K2E_H + +/* PA SS Registers */ +#define KS2_PASS_BASE 0x24000000 + +/* Power and Sleep Controller (PSC) Domains */ +#define KS2_LPSC_MOD_RST 0 +#define KS2_LPSC_USB_1 1 +#define KS2_LPSC_USB 2 +#define KS2_LPSC_EMIF25_SPI 3 +#define KS2_LPSC_TSIP 4 +#define KS2_LPSC_DEBUGSS_TRC 5 +#define KS2_LPSC_TETB_TRC 6 +#define KS2_LPSC_PKTPROC 7 +#define KS2_LPSC_PA KS2_LPSC_PKTPROC +#define KS2_LPSC_SGMII 8 +#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII +#define KS2_LPSC_CRYPTO 9 +#define KS2_LPSC_PCIE 10 +#define KS2_LPSC_VUSR0 12 +#define KS2_LPSC_CHIP_SRSS 13 +#define KS2_LPSC_MSMC 14 +#define KS2_LPSC_EMIF4F_DDR3 23 +#define KS2_LPSC_PCIE_1 27 +#define KS2_LPSC_XGE 50 + +/* MSMC */ +#define KS2_MSMC_SEGMENT_PCIE1 13 + +/* Chip Interrupt Controller */ +#define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */ +#define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */ + +/* SGMII SerDes */ +#define KS2_SGMII_SERDES2_BASE 0x02324000 +#define KS2_LANES_PER_SGMII_SERDES 4 + +/* Number of DSP cores */ +#define KS2_NUM_DSPS 1 + +/* NETCP pktdma */ +#define KS2_NETCP_PDMA_CTRL_BASE 0x24186000 +#define KS2_NETCP_PDMA_TX_BASE 0x24187000 +#define KS2_NETCP_PDMA_TX_CH_NUM 21 +#define KS2_NETCP_PDMA_RX_BASE 0x24188000 +#define KS2_NETCP_PDMA_RX_CH_NUM 91 +#define KS2_NETCP_PDMA_SCHED_BASE 0x24186100 +#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x24189000 +#define KS2_NETCP_PDMA_RX_FLOW_NUM 96 +#define KS2_NETCP_PDMA_TX_SND_QUEUE 896 + +/* NETCP */ +#define KS2_NETCP_BASE 0x24000000 + +#endif diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2hk.h b/arch/arm/mach-keystone/include/mach/hardware-k2hk.h new file mode 100644 index 0000000000..195c0d3003 --- /dev/null +++ b/arch/arm/mach-keystone/include/mach/hardware-k2hk.h @@ -0,0 +1,106 @@ +/* + * K2HK: SoC definitions + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_HARDWARE_K2HK_H +#define __ASM_ARCH_HARDWARE_K2HK_H + +#define KS2_ARM_PLL_EN BIT(13) + +/* PA SS Registers */ +#define KS2_PASS_BASE 0x02000000 + +/* PLL control registers */ +#define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368) +#define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C) + +/* Power and Sleep Controller (PSC) Domains */ +#define KS2_LPSC_MOD 0 +#define KS2_LPSC_DUMMY1 1 +#define KS2_LPSC_USB 2 +#define KS2_LPSC_EMIF25_SPI 3 +#define KS2_LPSC_TSIP 4 +#define KS2_LPSC_DEBUGSS_TRC 5 +#define KS2_LPSC_TETB_TRC 6 +#define KS2_LPSC_PKTPROC 7 +#define KS2_LPSC_PA KS2_LPSC_PKTPROC +#define KS2_LPSC_SGMII 8 +#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII +#define KS2_LPSC_CRYPTO 9 +#define KS2_LPSC_PCIE 10 +#define KS2_LPSC_SRIO 11 +#define KS2_LPSC_VUSR0 12 +#define KS2_LPSC_CHIP_SRSS 13 +#define KS2_LPSC_MSMC 14 +#define KS2_LPSC_GEM_1 16 +#define KS2_LPSC_GEM_2 17 +#define KS2_LPSC_GEM_3 18 +#define KS2_LPSC_GEM_4 19 +#define KS2_LPSC_GEM_5 20 +#define KS2_LPSC_GEM_6 21 +#define KS2_LPSC_GEM_7 22 +#define KS2_LPSC_EMIF4F_DDR3A 23 +#define KS2_LPSC_EMIF4F_DDR3B 24 +#define KS2_LPSC_TAC 25 +#define KS2_LPSC_RAC 26 +#define KS2_LPSC_RAC_1 27 +#define KS2_LPSC_FFTC_A 28 +#define KS2_LPSC_FFTC_B 29 +#define KS2_LPSC_FFTC_C 30 +#define KS2_LPSC_FFTC_D 31 +#define KS2_LPSC_FFTC_E 32 +#define KS2_LPSC_FFTC_F 33 +#define KS2_LPSC_AI2 34 +#define KS2_LPSC_TCP3D_0 35 +#define KS2_LPSC_TCP3D_1 36 +#define KS2_LPSC_TCP3D_2 37 +#define KS2_LPSC_TCP3D_3 38 +#define KS2_LPSC_VCP2X4_A 39 +#define KS2_LPSC_CP2X4_B 40 +#define KS2_LPSC_VCP2X4_C 41 +#define KS2_LPSC_VCP2X4_D 42 +#define KS2_LPSC_VCP2X4_E 43 +#define KS2_LPSC_VCP2X4_F 44 +#define KS2_LPSC_VCP2X4_G 45 +#define KS2_LPSC_VCP2X4_H 46 +#define KS2_LPSC_BCP 47 +#define KS2_LPSC_DXB 48 +#define KS2_LPSC_VUSR1 49 +#define KS2_LPSC_XGE 50 +#define KS2_LPSC_ARM_SREFLEX 51 + +/* DDR3B definitions */ +#define KS2_DDR3B_EMIF_CTRL_BASE 0x21020000 +#define KS2_DDR3B_EMIF_DATA_BASE 0x60000000 +#define KS2_DDR3B_DDRPHYC 0x02328000 + +#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3 /* DDR3 ECC system irq number */ +#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D /* DDR3 ECC int mapped to CIC2 + channel 29 */ + +/* SGMII SerDes */ +#define KS2_LANES_PER_SGMII_SERDES 4 + +/* Number of DSP cores */ +#define KS2_NUM_DSPS 8 + +/* NETCP pktdma */ +#define KS2_NETCP_PDMA_CTRL_BASE 0x02004000 +#define KS2_NETCP_PDMA_TX_BASE 0x02004400 +#define KS2_NETCP_PDMA_TX_CH_NUM 9 +#define KS2_NETCP_PDMA_RX_BASE 0x02004800 +#define KS2_NETCP_PDMA_RX_CH_NUM 26 +#define KS2_NETCP_PDMA_SCHED_BASE 0x02004c00 +#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x02005000 +#define KS2_NETCP_PDMA_RX_FLOW_NUM 32 +#define KS2_NETCP_PDMA_TX_SND_QUEUE 648 + +/* NETCP */ +#define KS2_NETCP_BASE 0x02000000 + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2l.h b/arch/arm/mach-keystone/include/mach/hardware-k2l.h new file mode 100644 index 0000000000..4f1197ea92 --- /dev/null +++ b/arch/arm/mach-keystone/include/mach/hardware-k2l.h @@ -0,0 +1,108 @@ +/* + * K2L: SoC definitions + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_HARDWARE_K2L_H +#define __ASM_ARCH_HARDWARE_K2L_H + +#define KS2_ARM_PLL_EN BIT(13) + +/* PA SS Registers */ +#define KS2_PASS_BASE 0x26000000 + +/* Power and Sleep Controller (PSC) Domains */ +#define KS2_LPSC_MOD 0 +#define KS2_LPSC_DFE_IQN_SYS 1 +#define KS2_LPSC_USB 2 +#define KS2_LPSC_EMIF25_SPI 3 +#define KS2_LPSC_TSIP 4 +#define KS2_LPSC_DEBUGSS_TRC 5 +#define KS2_LPSC_TETB_TRC 6 +#define KS2_LPSC_PKTPROC 7 +#define KS2_LPSC_PA KS2_LPSC_PKTPROC +#define KS2_LPSC_SGMII 8 +#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII +#define KS2_LPSC_CRYPTO 9 +#define KS2_LPSC_PCIE0 10 +#define KS2_LPSC_PCIE1 11 +#define KS2_LPSC_JESD_MISC 12 +#define KS2_LPSC_CHIP_SRSS 13 +#define KS2_LPSC_MSMC 14 +#define KS2_LPSC_GEM_1 16 +#define KS2_LPSC_GEM_2 17 +#define KS2_LPSC_GEM_3 18 +#define KS2_LPSC_EMIF4F_DDR3 23 +#define KS2_LPSC_TAC 25 +#define KS2_LPSC_RAC 26 +#define KS2_LPSC_DDUC4X_CFR2X_BB 27 +#define KS2_LPSC_FFTC_A 28 +#define KS2_LPSC_OSR 34 +#define KS2_LPSC_TCP3D_0 35 +#define KS2_LPSC_TCP3D_1 37 +#define KS2_LPSC_VCP2X4_A 39 +#define KS2_LPSC_VCP2X4_B 40 +#define KS2_LPSC_VCP2X4_C 41 +#define KS2_LPSC_VCP2X4_D 42 +#define KS2_LPSC_BCP 47 +#define KS2_LPSC_DPD4X 48 +#define KS2_LPSC_FFTC_B 49 +#define KS2_LPSC_IQN_AIL 50 + +/* MSMC */ +#define KS2_MSMC_SEGMENT_PCIE1 14 + +/* Chip Interrupt Controller */ +#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3 +#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D + +/* OSR */ +#define KS2_OSR_DATA_BASE 0x70000000 /* OSR data base */ +#define KS2_OSR_CFG_BASE 0x02348c00 /* OSR config base */ +#define KS2_OSR_ECC_VEC 0x08 /* ECC Vector reg */ +#define KS2_OSR_ECC_CTRL 0x14 /* ECC control reg */ + +/* OSR ECC Vector register */ +#define KS2_OSR_ECC_VEC_TRIG_RD BIT(15) /* trigger a read op */ +#define KS2_OSR_ECC_VEC_RD_DONE BIT(24) /* read complete */ + +#define KS2_OSR_ECC_VEC_RAM_ID_SH 0 /* RAM ID shift */ +#define KS2_OSR_ECC_VEC_RD_ADDR_SH 16 /* read address shift */ + +/* OSR ECC control register */ +#define KS2_OSR_ECC_CTRL_EN BIT(0) /* ECC enable bit */ +#define KS2_OSR_ECC_CTRL_CHK BIT(1) /* ECC check bit */ +#define KS2_OSR_ECC_CTRL_RMW BIT(2) /* ECC check bit */ + +/* Number of OSR RAM banks */ +#define KS2_OSR_NUM_RAM_BANKS 4 + +/* OSR memory size */ +#define KS2_OSR_SIZE 0x100000 + +/* SGMII SerDes */ +#define KS2_SGMII_SERDES2_BASE 0x02320000 +#define KS2_LANES_PER_SGMII_SERDES 2 + +/* Number of DSP cores */ +#define KS2_NUM_DSPS 4 + +/* NETCP pktdma */ +#define KS2_NETCP_PDMA_CTRL_BASE 0x26186000 +#define KS2_NETCP_PDMA_TX_BASE 0x26187000 +#define KS2_NETCP_PDMA_TX_CH_NUM 21 +#define KS2_NETCP_PDMA_RX_BASE 0x26188000 +#define KS2_NETCP_PDMA_RX_CH_NUM 91 +#define KS2_NETCP_PDMA_SCHED_BASE 0x26186100 +#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x26189000 +#define KS2_NETCP_PDMA_RX_FLOW_NUM 96 +#define KS2_NETCP_PDMA_TX_SND_QUEUE 896 + +/* NETCP */ +#define KS2_NETCP_BASE 0x26000000 + +#endif /* __ASM_ARCH_HARDWARE_K2L_H */ diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h new file mode 100644 index 0000000000..16cbcee12b --- /dev/null +++ b/arch/arm/mach-keystone/include/mach/hardware.h @@ -0,0 +1,290 @@ +/* + * Keystone2: Common SoC definitions, structures etc. + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include + +#ifndef __ASSEMBLY__ + +#include +#include + +#define REG(addr) (*(volatile unsigned int *)(addr)) +#define REG_P(addr) ((volatile unsigned int *)(addr)) + +typedef volatile unsigned int dv_reg; +typedef volatile unsigned int *dv_reg_p; + +#endif + +#define BIT(x) (1 << (x)) + +#define KS2_DDRPHY_PIR_OFFSET 0x04 +#define KS2_DDRPHY_PGCR0_OFFSET 0x08 +#define KS2_DDRPHY_PGCR1_OFFSET 0x0C +#define KS2_DDRPHY_PGSR0_OFFSET 0x10 +#define KS2_DDRPHY_PGSR1_OFFSET 0x14 +#define KS2_DDRPHY_PLLCR_OFFSET 0x18 +#define KS2_DDRPHY_PTR0_OFFSET 0x1C +#define KS2_DDRPHY_PTR1_OFFSET 0x20 +#define KS2_DDRPHY_PTR2_OFFSET 0x24 +#define KS2_DDRPHY_PTR3_OFFSET 0x28 +#define KS2_DDRPHY_PTR4_OFFSET 0x2C +#define KS2_DDRPHY_DCR_OFFSET 0x44 + +#define KS2_DDRPHY_DTPR0_OFFSET 0x48 +#define KS2_DDRPHY_DTPR1_OFFSET 0x4C +#define KS2_DDRPHY_DTPR2_OFFSET 0x50 + +#define KS2_DDRPHY_MR0_OFFSET 0x54 +#define KS2_DDRPHY_MR1_OFFSET 0x58 +#define KS2_DDRPHY_MR2_OFFSET 0x5C +#define KS2_DDRPHY_DTCR_OFFSET 0x68 +#define KS2_DDRPHY_PGCR2_OFFSET 0x8C + +#define KS2_DDRPHY_ZQ0CR1_OFFSET 0x184 +#define KS2_DDRPHY_ZQ1CR1_OFFSET 0x194 +#define KS2_DDRPHY_ZQ2CR1_OFFSET 0x1A4 +#define KS2_DDRPHY_ZQ3CR1_OFFSET 0x1B4 + +#define KS2_DDRPHY_DATX8_8_OFFSET 0x3C0 + +#define IODDRM_MASK 0x00000180 +#define ZCKSEL_MASK 0x01800000 +#define CL_MASK 0x00000072 +#define WR_MASK 0x00000E00 +#define BL_MASK 0x00000003 +#define RRMODE_MASK 0x00040000 +#define UDIMM_MASK 0x20000000 +#define BYTEMASK_MASK 0x0003FC00 +#define MPRDQ_MASK 0x00000080 +#define PDQ_MASK 0x00000070 +#define NOSRA_MASK 0x08000000 +#define ECC_MASK 0x00000001 + +/* DDR3 definitions */ +#define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000 +#define KS2_DDR3A_EMIF_DATA_BASE 0x80000000 +#define KS2_DDR3A_DDRPHYC 0x02329000 + +#define KS2_DDR3_MIDR_OFFSET 0x00 +#define KS2_DDR3_STATUS_OFFSET 0x04 +#define KS2_DDR3_SDCFG_OFFSET 0x08 +#define KS2_DDR3_SDRFC_OFFSET 0x10 +#define KS2_DDR3_SDTIM1_OFFSET 0x18 +#define KS2_DDR3_SDTIM2_OFFSET 0x1C +#define KS2_DDR3_SDTIM3_OFFSET 0x20 +#define KS2_DDR3_SDTIM4_OFFSET 0x28 +#define KS2_DDR3_PMCTL_OFFSET 0x38 +#define KS2_DDR3_ZQCFG_OFFSET 0xC8 + +#define KS2_DDR3_PLLCTRL_PHY_RESET 0x80000000 + +/* DDR3 ECC */ +#define KS2_DDR3_ECC_INT_STATUS_OFFSET 0x0AC +#define KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET 0x0B4 +#define KS2_DDR3_ECC_CTRL_OFFSET 0x110 +#define KS2_DDR3_ECC_ADDR_RANGE1_OFFSET 0x114 +#define KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET 0x130 +#define KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET 0x13C + +/* DDR3 ECC Interrupt Status register */ +#define KS2_DDR3_1B_ECC_ERR_SYS BIT(5) +#define KS2_DDR3_2B_ECC_ERR_SYS BIT(4) +#define KS2_DDR3_WR_ECC_ERR_SYS BIT(3) + +/* DDR3 ECC Control register */ +#define KS2_DDR3_ECC_EN BIT(31) +#define KS2_DDR3_ECC_ADDR_RNG_PROT BIT(30) +#define KS2_DDR3_ECC_VERIFY_EN BIT(29) +#define KS2_DDR3_ECC_RMW_EN BIT(28) +#define KS2_DDR3_ECC_ADDR_RNG_1_EN BIT(0) + +#define KS2_DDR3_ECC_ENABLE (KS2_DDR3_ECC_EN | \ + KS2_DDR3_ECC_ADDR_RNG_PROT | \ + KS2_DDR3_ECC_VERIFY_EN) + +/* EDMA */ +#define KS2_EDMA0_BASE 0x02700000 + +/* EDMA3 register offsets */ +#define KS2_EDMA_QCHMAP0 0x0200 +#define KS2_EDMA_IPR 0x1068 +#define KS2_EDMA_ICR 0x1070 +#define KS2_EDMA_QEECR 0x1088 +#define KS2_EDMA_QEESR 0x108c +#define KS2_EDMA_PARAM_1(x) (0x4020 + (4 * x)) + +/* NETCP pktdma */ +#define KS2_NETCP_PDMA_RX_FREE_QUEUE 4001 +#define KS2_NETCP_PDMA_RX_RCV_QUEUE 4002 + +/* Chip Interrupt Controller */ +#define KS2_CIC2_BASE 0x02608000 + +/* Chip Interrupt Controller register offsets */ +#define KS2_CIC_CTRL 0x04 +#define KS2_CIC_HOST_CTRL 0x0C +#define KS2_CIC_GLOBAL_ENABLE 0x10 +#define KS2_CIC_SYS_ENABLE_IDX_SET 0x28 +#define KS2_CIC_HOST_ENABLE_IDX_SET 0x34 +#define KS2_CIC_CHAN_MAP(n) (0x0400 + (n << 2)) + +#define KS2_UART0_BASE 0x02530c00 +#define KS2_UART1_BASE 0x02531000 + +/* Boot Config */ +#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000 +#define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18) +#define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20) +#define KS2_DEVCFG (KS2_DEVICE_STATE_CTRL_BASE + 0x14c) + +/* PSC */ +#define KS2_PSC_BASE 0x02350000 +#define KS2_LPSC_GEM_0 15 +#define KS2_LPSC_TETRIS 52 +#define KS2_TETRIS_PWR_DOMAIN 31 + +/* Chip configuration unlock codes and registers */ +#define KS2_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38) +#define KS2_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c) +#define KS2_KICK0_MAGIC 0x83e70b13 +#define KS2_KICK1_MAGIC 0x95a4f1e0 + +/* PLL control registers */ +#define KS2_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350) +#define KS2_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354) +#define KS2_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358) +#define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C) +#define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360) +#define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364) +#define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370) +#define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374) + +#define KS2_PLL_CNTRL_BASE 0x02310000 +#define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE +#define KS2_RSTCTRL_RSTYPE (KS2_PLL_CNTRL_BASE + 0xe4) +#define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8) +#define KS2_RSTCTRL_RSCFG (KS2_PLL_CNTRL_BASE + 0xec) +#define KS2_RSTCTRL_KEY 0x5a69 +#define KS2_RSTCTRL_MASK 0xffff0000 +#define KS2_RSTCTRL_SWRST 0xfffe0000 +#define KS2_RSTYPE_PLL_SOFT BIT(13) + +/* SPI */ +#define KS2_SPI0_BASE 0x21000400 +#define KS2_SPI1_BASE 0x21000600 +#define KS2_SPI2_BASE 0x21000800 +#define KS2_SPI_BASE KS2_SPI0_BASE + +/* AEMIF */ +#define KS2_AEMIF_CNTRL_BASE 0x21000a00 +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE + +/* Flag from ks2_debug options to check if DSPs need to stay ON */ +#define DBG_LEAVE_DSPS_ON 0x1 + +/* MSMC control */ +#define KS2_MSMC_CTRL_BASE 0x0bc00000 +#define KS2_MSMC_DATA_BASE 0x0c000000 +#define KS2_MSMC_SEGMENT_TETRIS 8 +#define KS2_MSMC_SEGMENT_NETCP 9 +#define KS2_MSMC_SEGMENT_QM_PDSP 10 +#define KS2_MSMC_SEGMENT_PCIE0 11 + +/* MSMC segment size shift bits */ +#define KS2_MSMC_SEG_SIZE_SHIFT 12 +#define KS2_MSMC_MAP_SEG_NUM (2 << (30 - KS2_MSMC_SEG_SIZE_SHIFT)) +#define KS2_MSMC_DST_SEG_BASE (CONFIG_SYS_LPAE_SDRAM_BASE >> \ + KS2_MSMC_SEG_SIZE_SHIFT) + +/* Device speed */ +#define KS2_REV1_DEVSPEED (KS2_DEVICE_STATE_CTRL_BASE + 0xc98) +#define KS2_EFUSE_BOOTROM (KS2_DEVICE_STATE_CTRL_BASE + 0xc90) +#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c) + +/* Queue manager */ +#define KS2_QM_BASE_ADDRESS 0x23a80000 +#define KS2_QM_CONF_BASE 0x02a02000 +#define KS2_QM_DESC_SETUP_BASE 0x02a03000 +#define KS2_QM_STATUS_RAM_BASE 0x02a06000 +#define KS2_QM_INTD_CONF_BASE 0x02a0c000 +#define KS2_QM_PDSP1_CMD_BASE 0x02a20000 +#define KS2_QM_PDSP1_CTRL_BASE 0x02a0f000 +#define KS2_QM_PDSP1_IRAM_BASE 0x02a10000 +#define KS2_QM_MANAGER_QUEUES_BASE 0x02a80000 +#define KS2_QM_MANAGER_Q_PROXY_BASE 0x02ac0000 +#define KS2_QM_QUEUE_STATUS_BASE 0x02a40000 +#define KS2_QM_LINK_RAM_BASE 0x00100000 +#define KS2_QM_REGION_NUM 64 +#define KS2_QM_QPOOL_NUM 4000 + +/* USB */ +#define KS2_USB_SS_BASE 0x02680000 +#define KS2_USB_HOST_XHCI_BASE (KS2_USB_SS_BASE + 0x10000) +#define KS2_DEV_USB_PHY_BASE 0x02620738 +#define KS2_USB_PHY_CFG_BASE 0x02630000 + +#define KS2_MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110) + +/* SGMII SerDes */ +#define KS2_SGMII_SERDES_BASE 0x0232a000 + +#ifdef CONFIG_SOC_K2HK +#include +#endif + +#ifdef CONFIG_SOC_K2E +#include +#endif + +#ifdef CONFIG_SOC_K2L +#include +#endif + +#ifndef __ASSEMBLY__ +static inline int cpu_is_k2hk(void) +{ + unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG); + unsigned int part_no = (jtag_id >> 12) & 0xffff; + + return (part_no == 0xb981) ? 1 : 0; +} + +static inline int cpu_is_k2e(void) +{ + unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG); + unsigned int part_no = (jtag_id >> 12) & 0xffff; + + return (part_no == 0xb9a6) ? 1 : 0; +} + +static inline int cpu_is_k2l(void) +{ + unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG); + unsigned int part_no = (jtag_id >> 12) & 0xffff; + + return (part_no == 0xb9a7) ? 1 : 0; +} + +static inline int cpu_revision(void) +{ + unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG); + unsigned int rev = (jtag_id >> 28) & 0xf; + + return rev; +} + +int cpu_to_bus(u32 *ptr, u32 length); +void sdelay(unsigned long); + +#endif + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-keystone/include/mach/i2c_defs.h b/arch/arm/mach-keystone/include/mach/i2c_defs.h new file mode 100644 index 0000000000..d4256526cc --- /dev/null +++ b/arch/arm/mach-keystone/include/mach/i2c_defs.h @@ -0,0 +1,17 @@ +/* + * keystone: i2c driver definitions + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _I2C_DEFS_H_ +#define _I2C_DEFS_H_ + +#define I2C0_BASE 0x02530000 +#define I2C1_BASE 0x02530400 +#define I2C2_BASE 0x02530800 +#define I2C_BASE I2C0_BASE + +#endif diff --git a/arch/arm/mach-keystone/include/mach/mon.h b/arch/arm/mach-keystone/include/mach/mon.h new file mode 100644 index 0000000000..33a28764bc --- /dev/null +++ b/arch/arm/mach-keystone/include/mach/mon.h @@ -0,0 +1,15 @@ +/* + * K2HK: secure kernel command header file + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MON_H_ +#define _MON_H_ + +int mon_power_off(int core_id); + +#endif diff --git a/arch/arm/mach-keystone/include/mach/msmc.h b/arch/arm/mach-keystone/include/mach/msmc.h new file mode 100644 index 0000000000..083f5ba052 --- /dev/null +++ b/arch/arm/mach-keystone/include/mach/msmc.h @@ -0,0 +1,45 @@ +/* + * MSMC controller + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MSMC_H_ +#define _MSMC_H_ + +#include + +enum mpax_seg_size { + MPAX_SEG_4K = 0x0b, + MPAX_SEG_8K, + MPAX_SEG_16K, + MPAX_SEG_32K, + MPAX_SEG_64K, + MPAX_SEG_128K, + MPAX_SEG_256K, + MPAX_SEG_512K, + MPAX_SEG_1M, + MPAX_SEG_2M, + MPAX_SEG_4M, + MPAX_SEG_8M, + MPAX_SEG_16M, + MPAX_SEG_32M, + MPAX_SEG_64M, + MPAX_SEG_128M, + MPAX_SEG_256M, + MPAX_SEG_512M, + MPAX_SEG_1G, + MPAX_SEG_2G, + MPAX_SEG_4G +}; + +void msmc_share_all_segments(int priv_id); +void msmc_get_ses_mpax(int priv_id, int ses_pair, u32 *mpax); +void msmc_set_ses_mpax(int priv_id, int ses_pair, u32 *mpax); +void msmc_map_ses_segment(int priv_id, int ses_pair, + u32 src_pfn, u32 dst_pfn, enum mpax_seg_size size); + +#endif diff --git a/arch/arm/mach-keystone/include/mach/psc_defs.h b/arch/arm/mach-keystone/include/mach/psc_defs.h new file mode 100644 index 0000000000..70d22cf217 --- /dev/null +++ b/arch/arm/mach-keystone/include/mach/psc_defs.h @@ -0,0 +1,90 @@ +/* + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _PSC_DEFS_H_ +#define _PSC_DEFS_H_ + +#include + +/* + * FILE PURPOSE: Local Power Sleep Controller definitions + * + * FILE NAME: psc_defs.h + * + * DESCRIPTION: Provides local definitions for the power saver controller + * + */ + +/* Register offsets */ +#define PSC_REG_PTCMD 0x120 +#define PSC_REG_PSTAT 0x128 +#define PSC_REG_PDSTAT(x) (0x200 + (4 * (x))) +#define PSC_REG_PDCTL(x) (0x300 + (4 * (x))) +#define PSC_REG_MDCFG(x) (0x600 + (4 * (x))) +#define PSC_REG_MDSTAT(x) (0x800 + (4 * (x))) +#define PSC_REG_MDCTL(x) (0xa00 + (4 * (x))) + +#define BOOTBITMASK(x, y) ((((((u32)1 << (((u32)x) - ((u32)y) + (u32)1)) - \ + (u32)1)) << ((u32)y))) + +#define BOOT_READ_BITFIELD(z, x, y) (((u32)z) & BOOTBITMASK(x, y)) >> (y) +#define BOOT_SET_BITFIELD(z, f, x, y) (((u32)z) & ~BOOTBITMASK(x, y)) | \ + ((((u32)f) << (y)) & BOOTBITMASK(x, y)) + +/* PDCTL */ +#define PSC_REG_PDCTL_SET_NEXT(x, y) BOOT_SET_BITFIELD((x), (y), 0, 0) +#define PSC_REG_PDCTL_SET_PDMODE(x, y) BOOT_SET_BITFIELD((x), (y), 15, 12) + +/* PDSTAT */ +#define PSC_REG_PDSTAT_GET_STATE(x) BOOT_READ_BITFIELD((x), 4, 0) + +/* MDCFG */ +#define PSC_REG_MDCFG_GET_PD(x) BOOT_READ_BITFIELD((x), 20, 16) +#define PSC_REG_MDCFG_GET_RESET_ISO(x) BOOT_READ_BITFIELD((x), 14, 14) + +/* MDCTL */ +#define PSC_REG_MDCTL_SET_NEXT(x, y) BOOT_SET_BITFIELD((x), (y), 4, 0) +#define PSC_REG_MDCTL_SET_LRSTZ(x, y) BOOT_SET_BITFIELD((x), (y), 8, 8) +#define PSC_REG_MDCTL_GET_LRSTZ(x) BOOT_READ_BITFIELD((x), 8, 8) +#define PSC_REG_MDCTL_SET_RESET_ISO(x, y) BOOT_SET_BITFIELD((x), (y), \ + 12, 12) + +/* MDSTAT */ +#define PSC_REG_MDSTAT_GET_STATUS(x) BOOT_READ_BITFIELD((x), 5, 0) +#define PSC_REG_MDSTAT_GET_LRSTZ(x) BOOT_READ_BITFIELD((x), 8, 8) +#define PSC_REG_MDSTAT_GET_LRSTDONE(x) BOOT_READ_BITFIELD((x), 9, 9) + +/* PDCTL states */ +#define PSC_REG_VAL_PDCTL_NEXT_ON 1 +#define PSC_REG_VAL_PDCTL_NEXT_OFF 0 + +#define PSC_REG_VAL_PDCTL_PDMODE_SLEEP 0 + +/* MDCTL states */ +#define PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE 0 +#define PSC_REG_VAL_MDCTL_NEXT_OFF 2 +#define PSC_REG_VAL_MDCTL_NEXT_ON 3 + +/* MDSTAT states */ +#define PSC_REG_VAL_MDSTAT_STATE_ON 3 +#define PSC_REG_VAL_MDSTAT_STATE_ENABLE_IN_PROG 0x24 +#define PSC_REG_VAL_MDSTAT_STATE_OFF 2 +#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG1 0x20 +#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG2 0x21 +#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG3 0x22 + +/* + * Timeout limit on checking PTSTAT. This is the number of times the + * wait function will be called before giving up. + */ +#define PSC_PTSTAT_TIMEOUT_LIMIT 100 + +u32 psc_get_domain_num(u32 mod_num); +int psc_enable_module(u32 mod_num); +int psc_disable_module(u32 mod_num); +int psc_disable_domain(u32 domain_num); + +#endif /* _PSC_DEFS_H_ */ diff --git a/arch/arm/mach-keystone/include/mach/xhci-keystone.h b/arch/arm/mach-keystone/include/mach/xhci-keystone.h new file mode 100644 index 0000000000..3aab4e045f --- /dev/null +++ b/arch/arm/mach-keystone/include/mach/xhci-keystone.h @@ -0,0 +1,21 @@ +/* + * USB 3.0 DRD Controller + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define USB3_PHY_REF_SSP_EN BIT(29) +#define USB3_PHY_OTG_VBUSVLDECTSEL BIT(16) + +/* KEYSTONE2 XHCI PHY register structure */ +struct keystone_xhci_phy { + unsigned int phy_utmi; /* ctl0 */ + unsigned int phy_pipe; /* ctl1 */ + unsigned int phy_param_ctrl_1; /* ctl2 */ + unsigned int phy_param_ctrl_2; /* ctl3 */ + unsigned int phy_clock; /* ctl4 */ + unsigned int phy_pll; /* ctl5 */ +};