From: Boris Brezillon Date: Thu, 1 Dec 2016 21:00:20 +0000 (+0100) Subject: clk: bcm: Allow rate change propagation to PLLH_AUX on VEC clock X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=d86d46af84855403c00018be1c3e7bc190f2a6cd;p=openwrt%2Fstaging%2Fblogic.git clk: bcm: Allow rate change propagation to PLLH_AUX on VEC clock The VEC clock requires needs to be set at exactly 108MHz. Allow rate change propagation on PLLH_AUX to match this requirement wihtout impacting other IPs (PLLH is currently only used by the HDMI encoder, which cannot be enabled when the VEC encoder is enabled). Signed-off-by: Boris Brezillon Reviewed-by: Eric Anholt Signed-off-by: Stephen Boyd --- diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index df96fe6dadab..eaf82f49dede 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -1861,7 +1861,12 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .ctl_reg = CM_VECCTL, .div_reg = CM_VECDIV, .int_bits = 4, - .frac_bits = 0), + .frac_bits = 0, + /* + * Allow rate change propagation only on PLLH_AUX which is + * assigned index 7 in the parent array. + */ + .set_rate_parent = BIT(7)), /* dsi clocks */ [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK(