From: Stanislav Fomichev Date: Sun, 10 Apr 2011 18:34:19 +0000 (+0400) Subject: brcm80211: use native PCI capability defines X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=d83942856615c17724201a9aecda5b4c582a2476;p=openwrt%2Fstaging%2Fblogic.git brcm80211: use native PCI capability defines Signed-off-by: Stanislav Fomichev Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/staging/brcm80211/include/pcicfg.h b/drivers/staging/brcm80211/include/pcicfg.h index 860121ffa8f5..4a519f2852d5 100644 --- a/drivers/staging/brcm80211/include/pcicfg.h +++ b/drivers/staging/brcm80211/include/pcicfg.h @@ -25,10 +25,6 @@ #define PCR_RSVDA_MAX 2 -/* pci config status reg has a bit to indicate that capability ptr is present */ - -#define PCI_CAPPTR_PRESENT 0x0010 - typedef struct _pci_config_regs { u16 vendor; u16 device; @@ -112,15 +108,6 @@ typedef struct _ppb_config_regs { u8 dev_dep[192]; } ppb_config_regs; -/* PCI CAPABILITY DEFINES */ -#define PCI_CAP_POWERMGMTCAP_ID 0x01 -#define PCI_CAP_PCIECAP_ID 0x10 - -#define PME_CAP_PM_STATES (0x1f << 27) /* Bits 31:27 states that can generate PME */ -#define PME_CSR_OFFSET 0x4 /* 4-bytes offset */ -#define PME_CSR_PME_EN (1 << 8) /* Bit 8 Enable generating of PME */ -#define PME_CSR_PME_STAT (1 << 15) /* Bit 15 PME got asserted */ - /* Everything below is BRCM HND proprietary */ /* Brcm PCI configuration registers */ diff --git a/drivers/staging/brcm80211/util/nicpci.c b/drivers/staging/brcm80211/util/nicpci.c index d603452ffb5f..7d441c359631 100644 --- a/drivers/staging/brcm80211/util/nicpci.c +++ b/drivers/staging/brcm80211/util/nicpci.c @@ -98,9 +98,8 @@ void *pcicore_init(si_t *sih, void *pdev, void *regs) if (sih->buscoretype == PCIE_CORE_ID) { u8 cap_ptr; pi->regs.pcieregs = (sbpcieregs_t *) regs; - cap_ptr = - pcicore_find_pci_capability(pi->dev, PCI_CAP_PCIECAP_ID, - NULL, NULL); + cap_ptr = pcicore_find_pci_capability(pi->dev, PCI_CAP_ID_EXP, + NULL, NULL); ASSERT(cap_ptr); pi->pciecap_lcreg_offset = cap_ptr + PCIE_CAP_LINKCTRL_OFFSET; } else @@ -136,7 +135,7 @@ pcicore_find_pci_capability(void *dev, u8 req_cap_id, /* check if the capability pointer field exists */ pci_read_config_byte(dev, PCI_STATUS, &byte_val); - if (!(byte_val & PCI_CAPPTR_PRESENT)) + if (!(byte_val & PCI_STATUS_CAP_LIST)) goto end; pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &cap_ptr); @@ -693,16 +692,15 @@ bool pcicore_pmecap_fast(void *pch) u8 cap_ptr; u32 pmecap; - cap_ptr = - pcicore_find_pci_capability(pi->dev, PCI_CAP_POWERMGMTCAP_ID, NULL, - NULL); + cap_ptr = pcicore_find_pci_capability(pi->dev, PCI_CAP_ID_PM, NULL, + NULL); if (!cap_ptr) return false; pci_read_config_dword(pi->dev, cap_ptr, &pmecap); - return (pmecap & PME_CAP_PM_STATES) != 0; + return (pmecap & (PCI_PM_CAP_PME_MASK << 16)) != 0; } /* return true if PM capability exists in the pci config space @@ -714,10 +712,9 @@ static bool pcicore_pmecap(pcicore_info_t *pi) u32 pmecap; if (!pi->pmecap_offset) { - cap_ptr = - pcicore_find_pci_capability(pi->dev, - PCI_CAP_POWERMGMTCAP_ID, NULL, - NULL); + cap_ptr = pcicore_find_pci_capability(pi->dev, + PCI_CAP_ID_PM, + NULL, NULL); if (!cap_ptr) return false; @@ -727,7 +724,7 @@ static bool pcicore_pmecap(pcicore_info_t *pi) &pmecap); /* At least one state can generate PME */ - pi->pmecap = (pmecap & PME_CAP_PM_STATES) != 0; + pi->pmecap = (pmecap & (PCI_PM_CAP_PME_MASK << 16)) != 0; } return pi->pmecap; @@ -743,11 +740,11 @@ void pcicore_pmeen(void *pch) if (!pcicore_pmecap(pi)) return; - pci_read_config_dword(pi->dev, pi->pmecap_offset + PME_CSR_OFFSET, + pci_read_config_dword(pi->dev, pi->pmecap_offset + PCI_PM_CTRL, &w); - w |= (PME_CSR_PME_EN); + w |= (PCI_PM_CTRL_PME_ENABLE); pci_write_config_dword(pi->dev, - pi->pmecap_offset + PME_CSR_OFFSET, w); + pi->pmecap_offset + PCI_PM_CTRL, w); } /* @@ -761,10 +758,10 @@ bool pcicore_pmestat(void *pch) if (!pcicore_pmecap(pi)) return false; - pci_read_config_dword(pi->dev, pi->pmecap_offset + PME_CSR_OFFSET, + pci_read_config_dword(pi->dev, pi->pmecap_offset + PCI_PM_CTRL, &w); - return (w & PME_CSR_PME_STAT) == PME_CSR_PME_STAT; + return (w & PCI_PM_CTRL_PME_STATUS) == PCI_PM_CTRL_PME_STATUS; } /* Disable PME generation, clear the PME status bit if set @@ -777,16 +774,16 @@ void pcicore_pmeclr(void *pch) if (!pcicore_pmecap(pi)) return; - pci_read_config_dword(pi->dev, pi->pmecap_offset + PME_CSR_OFFSET, + pci_read_config_dword(pi->dev, pi->pmecap_offset + PCI_PM_CTRL, &w); PCI_ERROR(("pcicore_pci_pmeclr PMECSR : 0x%x\n", w)); /* PMESTAT is cleared by writing 1 to it */ - w &= ~(PME_CSR_PME_EN); + w &= ~(PCI_PM_CTRL_PME_ENABLE); pci_write_config_dword(pi->dev, - pi->pmecap_offset + PME_CSR_OFFSET, w); + pi->pmecap_offset + PCI_PM_CTRL, w); } u32 pcie_lcreg(void *pch, u32 mask, u32 val) diff --git a/drivers/staging/brcm80211/util/siutils.c b/drivers/staging/brcm80211/util/siutils.c index 29b6fa70f37f..9e181d60c201 100644 --- a/drivers/staging/brcm80211/util/siutils.c +++ b/drivers/staging/brcm80211/util/siutils.c @@ -1486,9 +1486,8 @@ static __used bool si_ispcie(si_info_t *sii) if (sii->pub.bustype != PCI_BUS) return false; - cap_ptr = - pcicore_find_pci_capability(sii->pbus, PCI_CAP_PCIECAP_ID, NULL, - NULL); + cap_ptr = pcicore_find_pci_capability(sii->pbus, PCI_CAP_ID_EXP, NULL, + NULL); if (!cap_ptr) return false;