From: John Crispin Date: Wed, 3 Apr 2013 09:58:44 +0000 (+0000) Subject: move files to files-3.7 X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=d4db00205d726f9faca3147cb345518ec5406aab;p=openwrt%2Fstaging%2Fblocktrron.git move files to files-3.7 Signed-off-by: John Crispin SVN-Revision: 36161 --- diff --git a/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/common.h b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/common.h new file mode 100644 index 0000000000..bb6e12bf86 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/common.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2009-2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_RALINK_COMMON_H +#define __ASM_MACH_RALINK_COMMON_H + +#define RAMIPS_SYS_TYPE_LEN 64 +extern unsigned char ramips_sys_type[RAMIPS_SYS_TYPE_LEN]; +extern unsigned long ramips_mem_base; +extern unsigned long ramips_mem_size_min; +extern unsigned long ramips_mem_size_max; +extern unsigned long (*ramips_get_mem_size)(void); + +void ramips_intc_irq_init(unsigned intc_base, unsigned irq, unsigned irq_base); +u32 ramips_intc_get_status(void); + +void ramips_soc_prom_init(void); +void ramips_soc_setup(void); +void ramips_early_serial_setup(int line, unsigned base, unsigned freq, + unsigned irq); + +#endif /* __ASM_MACH_RALINK_COMMON_H */ diff --git a/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/dev-gpio-buttons.h b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/dev-gpio-buttons.h new file mode 100644 index 0000000000..8eb5e16906 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/dev-gpio-buttons.h @@ -0,0 +1,29 @@ +/* + * Ralink SoC GPIO button support + * + * Copyright (C) 2010-2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_RALINK_DEV_GPIO_BUTTONS_H +#define __ASM_MACH_RALINK_DEV_GPIO_BUTTONS_H + +#include +#include + +#ifdef CONFIG_RALINK_DEV_GPIO_BUTTONS +void +ramips_register_gpio_buttons(int id, unsigned poll_interval, unsigned nbuttons, + struct gpio_keys_button *buttons); +#else +static inline void +ramips_register_gpio_buttons(int id, unsigned poll_interval, unsigned nbuttons, + struct gpio_keys_button *buttons) +{ +} +#endif + +#endif /* __ASM_MACH_RALINK_DEV_GPIO_BUTTONS_H */ diff --git a/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/dev-gpio-leds.h b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/dev-gpio-leds.h new file mode 100644 index 0000000000..24233abde6 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/dev-gpio-leds.h @@ -0,0 +1,26 @@ +/* + * Ralink SoC GPIO LED device support + * + * Copyright (C) 2009-2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_RALINK_DEV_GPIO_LEDS_H +#define __ASM_MACH_RALINK_DEV_GPIO_LEDS_H + +#include + +#ifdef CONFIG_RALINK_DEV_GPIO_LEDS +void ramips_register_gpio_leds(int id, unsigned num_leds, + struct gpio_led *leds); +#else +static inline void ramips_register_gpio_leds(int id, unsigned num_leds, + struct gpio_led *leds) +{ +} +#endif + +#endif /* __ASM_MACH_RALINK_DEV_GPIO_LEDS_H */ diff --git a/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/gpio.h b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/gpio.h new file mode 100644 index 0000000000..f68ee16856 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/gpio.h @@ -0,0 +1,24 @@ +/* + * Ralink SoC GPIO API support + * + * Copyright (C) 2008-2009 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef __ASM_MACH_RALINK_GPIO_H +#define __ASM_MACH_RALINK_GPIO_H + +#define ARCH_NR_GPIOS 128 +#include + +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep +#define gpio_to_irq __gpio_to_irq + +#endif /* __ASM_MACH_RALINK_GPIO_H */ diff --git a/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/machine.h b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/machine.h new file mode 100644 index 0000000000..200f737f71 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/machine.h @@ -0,0 +1,88 @@ +/* + * Ralink machine types + * + * Copyright (C) 2010 Joonas Lahtinen + * Copyright (C) 2009 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +enum ramips_mach_type { + RAMIPS_MACH_GENERIC, + /* RT2880 based machines */ + RAMIPS_MACH_F5D8235_V1, /* Belkin F5D8235 v1 */ + RAMIPS_MACH_BR6524N, /* Edimax BR6524N */ + RAMIPS_MACH_RT_N15, /* Asus RT-N15 */ + RAMIPS_MACH_V11ST_FE, /* Ralink V11ST-FE */ + RAMIPS_MACH_WLI_TX4_AG300N, /* Buffalo WLI-TX4-AG300N */ + RAMIPS_MACH_WZR_AGL300NH, /* Buffalo WZR-AGL300NH */ + + /* RT3050 based machines */ + RAMIPS_MACH_3G_6200N, /* Edimax 3G-6200N */ + RAMIPS_MACH_ALL0256N, /* Allnet ALL0256N */ + RAMIPS_MACH_CARAMBOLA, /* 8devices Carambola */ + RAMIPS_MACH_DIR_300_B1, /* D-Link DIR-300 B1 */ + RAMIPS_MACH_DIR_600_B1, /* D-Link DIR-600 B1 */ + RAMIPS_MACH_DIR_600_B2, /* D-Link DIR-600 B2 */ + RAMIPS_MACH_DIR_615_D, /* D-Link DIR-615 D */ + RAMIPS_MACH_DIR_620_A1, /* D-Link DIR-620 A1 */ + RAMIPS_MACH_RT_G32_B1, /* Asus RT-G32 B1 */ + RAMIPS_MACH_RT_N10_PLUS, /* Asus RT-N10+ */ + RAMIPS_MACH_NW718, /* Netcore NW718 */ + RAMIPS_MACH_WL_330N, /* Asus WL-330N */ + RAMIPS_MACH_WL_330N3G, /* Asus WL-330N3G */ + + /* RT3052 based machines */ + RAMIPS_MACH_3G300M, /* Tenda 3G300M */ + RAMIPS_MACH_ALL0239_3G, /* ALL0239-3G */ + RAMIPS_MACH_ARGUS_ATP52B, /* Argus ATP-52B */ + RAMIPS_MACH_BC2, /* NexAira BC2 */ + RAMIPS_MACH_BR6425, /* Edimax BR-6425 */ + RAMIPS_MACH_BROADWAY, /* Hauppauge Broadway */ + RAMIPS_MACH_DAP_1350, /* D-Link DAP-1350 */ + RAMIPS_MACH_ESR_9753, /* Senao / EnGenius ESR-9753*/ + RAMIPS_MACH_F5D8235_V2, /* Belkin F5D8235 v2 */ + RAMIPS_MACH_FONERA20N, /* La Fonera 2.0N */ + RAMIPS_MACH_RT_N13U, /* ASUS RT-N13U */ + RAMIPS_MACH_FREESTATION5, /* ARC Freestation5 */ + RAMIPS_MACH_HW550_3G, /* Aztech HW550-3G */ + RAMIPS_MACH_MOFI3500_3GN, /* MoFi Network MOFI3500-3GN */ + RAMIPS_MACH_NBG_419N, /* ZyXEL NBG-419N */ + RAMIPS_MACH_OMNI_EMB, /* Omnima MiniEMBWiFi */ + RAMIPS_MACH_PSR_680W, /* Petatel PSR-680W Wireless 3G Router*/ + RAMIPS_MACH_PWH2004, /* Prolink 2004H / Abocom 5205 */ + RAMIPS_MACH_SL_R7205, /* Skylink SL-R7205 Wireless 3G Router*/ + RAMIPS_MACH_V22RW_2X2, /* Ralink AP-RT3052-V22RW-2X2 */ + RAMIPS_MACH_W306R_V20, /* Tenda W306R_V20 */ + RAMIPS_MACH_W502U, /* ALFA Networks W502U */ + RAMIPS_MACH_WCR150GN, /* Sparklan WCR-150GN */ + RAMIPS_MACH_WHR_G300N, /* Buffalo WHR-G300N */ + RAMIPS_MACH_WL341V3, /* Sitecom WL-341 v3 */ + RAMIPS_MACH_WL351, /* Sitecom WL-351 v1 002 */ + RAMIPS_MACH_WR512_3GN, /* SH-WR512NU/WS-WR512N1-like 3GN*/ + RAMIPS_MACH_WR6202, /* Accton WR6202 */ + RAMIPS_MACH_MZKW300NH2, /* Planex MZK-W300NH2 Router */ + RAMIPS_MACH_XDXRN502J, /* unknown XDX-RN502J */ + RAMIPS_MACH_UR_326N4G, /* UPVEL ROUTER */ + RAMIPS_MACH_UR_336UN, /* UPVEL ROUTER */ + + /* RT3352 based machines */ + RAMIPS_MACH_ALL5002, /* Allnet ALL5002 */ + RAMIPS_MACH_DIR_615_H1, + + /* RT3662 based machines */ + RAMIPS_MACH_DIR_645, /* D-Link DIR-645 */ + RAMIPS_MACH_OMNI_EMB_HPM, /* Omnima EMB HPM */ + RAMIPS_MACH_RT_N56U, /* Asus RT-N56U */ + + /* RT3883 based machines */ + RAMIPS_MACH_TEW_691GR, /* TRENDnet TEW-691GR */ + RAMIPS_MACH_TEW_692GR, /* TRENDnet TEW-692GR */ + + /* RT5350 based machines */ + RAMIPS_MACH_AIR3GII, /* AirLive Air3GII */ +}; diff --git a/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/ramips_eth_platform.h b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/ramips_eth_platform.h new file mode 100644 index 0000000000..57c0556b93 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/ramips_eth_platform.h @@ -0,0 +1,41 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + * + * based on Ralink SDK3.3 + * Copyright (C) 2009 John Crispin + */ + +#ifndef _RAMIPS_ETH_PLATFORM_H +#define _RAMIPS_ETH_PLATFORM_H + +#include + +struct ramips_eth_platform_data +{ + unsigned char mac[6]; + void (*reset_fe)(void); + int min_pkt_len; + unsigned long sys_freq; + + int speed; + int duplex; + int tx_fc; + int rx_fc; + + u32 phy_mask; + phy_interface_t phy_if_mode; +}; + +#endif /* _RAMIPS_ETH_PLATFORM_H */ + diff --git a/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/ramips_gpio.h b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/ramips_gpio.h new file mode 100644 index 0000000000..32fc7a7402 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/ramips_gpio.h @@ -0,0 +1,48 @@ +/* + * Ralink SoC specific GPIO support + * + * Copyright (C) 2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _RAMIPS_GPIO_H +#define _RAMIPS_GPIO_H + +#include +#include + +enum ramips_gpio_reg { + RAMIPS_GPIO_REG_INT = 0, /* Interrupt status */ + RAMIPS_GPIO_REG_EDGE, + RAMIPS_GPIO_REG_RENA, + RAMIPS_GPIO_REG_FENA, + RAMIPS_GPIO_REG_DATA, + RAMIPS_GPIO_REG_DIR, /* Direction, 0:in, 1: out */ + RAMIPS_GPIO_REG_POL, /* Polarity, 0: normal, 1: invert */ + RAMIPS_GPIO_REG_SET, + RAMIPS_GPIO_REG_RESET, + RAMIPS_GPIO_REG_TOGGLE, + RAMIPS_GPIO_REG_MAX +}; + +struct ramips_gpio_chip { + struct gpio_chip chip; + unsigned long map_base; + unsigned long map_size; + u8 regs[RAMIPS_GPIO_REG_MAX]; + + spinlock_t lock; + void __iomem *regs_base; +}; + +struct ramips_gpio_data { + unsigned int num_chips; + struct ramips_gpio_chip *chips; +}; + +int ramips_gpio_init(struct ramips_gpio_data *data); + +#endif /* _RAMIPS_GPIO_H */ diff --git a/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/ramips_nand_platform.h b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/ramips_nand_platform.h new file mode 100644 index 0000000000..54203db8ea --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/ramips_nand_platform.h @@ -0,0 +1,23 @@ +/* + * Platform data definition for the built-in NAND controller of the + * Ralink RT305X/RT3662/RT3883 SoCs + * + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _RAMIPS_NAND_PLATFORM_H +#define _RAMIPS_NAND_PLATFORM_H + +#define RAMIPS_NAND_DRIVER_NAME "ramips-nand" + +struct ramips_nand_platform_data { + const char *name; + struct mtd_partition *parts; + int nr_parts; +}; + +#endif /* _RAMIPS_NAND_PLATFORM_H */ diff --git a/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt288x.h b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt288x.h new file mode 100644 index 0000000000..10d7263324 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt288x.h @@ -0,0 +1,76 @@ +/* + * Ralink RT288x SoC specific definitions + * + * Copyright (C) 2008-2011 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Ralink's 2.6.21 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _RT288X_H_ +#define _RT288X_H_ + +#include +#include + +#define RT288X_MEM_SIZE_MIN (2 * 1024 * 1024) +#define RT288X_MEM_SIZE_MAX (128 * 1024 * 1024) + +#define RT288X_CPU_IRQ_BASE 0 +#define RT288X_INTC_IRQ_BASE 8 +#define RT288X_INTC_IRQ_COUNT 32 +#define RT288X_GPIO_IRQ_BASE 40 + +#define RT288X_CPU_IRQ_INTC (RT288X_CPU_IRQ_BASE + 2) +#define RT288X_CPU_IRQ_PCI (RT288X_CPU_IRQ_BASE + 4) +#define RT288X_CPU_IRQ_FE (RT288X_CPU_IRQ_BASE + 5) +#define RT288X_CPU_IRQ_WNIC (RT288X_CPU_IRQ_BASE + 6) +#define RT288X_CPU_IRQ_COUNTER (RT288X_CPU_IRQ_BASE + 7) + +#define RT2880_INTC_IRQ_TIMER0 (RT288X_INTC_IRQ_BASE + 0) +#define RT2880_INTC_IRQ_TIMER1 (RT288X_INTC_IRQ_BASE + 1) +#define RT2880_INTC_IRQ_UART0 (RT288X_INTC_IRQ_BASE + 2) +#define RT2880_INTC_IRQ_PIO (RT288X_INTC_IRQ_BASE + 3) +#define RT2880_INTC_IRQ_PCM (RT288X_INTC_IRQ_BASE + 4) +#define RT2880_INTC_IRQ_UART1 (RT288X_INTC_IRQ_BASE + 8) +#define RT2880_INTC_IRQ_IA (RT288X_INTC_IRQ_BASE + 23) + +#define RT288X_GPIO_IRQ(x) (RT288X_GPIO_IRQ_BASE + (x)) +#define RT288X_GPIO_COUNT 32 + +extern void __iomem *rt288x_sysc_base; +extern void __iomem *rt288x_memc_base; + +static inline void rt288x_sysc_wr(u32 val, unsigned reg) +{ + __raw_writel(val, rt288x_sysc_base + reg); +} + +static inline u32 rt288x_sysc_rr(unsigned reg) +{ + return __raw_readl(rt288x_sysc_base + reg); +} + +static inline void rt288x_memc_wr(u32 val, unsigned reg) +{ + __raw_writel(val, rt288x_memc_base + reg); +} + +static inline u32 rt288x_memc_rr(unsigned reg) +{ + return __raw_readl(rt288x_memc_base + reg); +} + +void rt288x_gpio_init(u32 mode); + +#ifdef CONFIG_PCI +int rt288x_register_pci(void); +#else +static inline int rt288x_register_pci(void) { return 0; } +#endif /* CONFIG_PCI */ + +#endif /* _RT228X_H_ */ diff --git a/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h new file mode 100644 index 0000000000..5e27363324 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h @@ -0,0 +1,56 @@ +/* + * Ralink RT288x specific CPU feature overrides + * + * Copyright (C) 2008-2009 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This file was derived from: include/asm-mips/cpu-features.h + * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ +#ifndef __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_sb1_cache 0 +#define cpu_has_fpu 0 +#define cpu_has_32fpr 0 +#define cpu_has_counter 1 +#define cpu_has_watch 1 +#define cpu_has_divec 1 + +#define cpu_has_prefetch 1 +#define cpu_has_ejtag 1 +#define cpu_has_llsc 1 + +#define cpu_has_mips16 1 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 + +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 1 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + +#define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 + +#define cpu_has_64bits 0 +#define cpu_has_64bit_zero_reg 0 +#define cpu_has_64bit_gp_regs 0 +#define cpu_has_64bit_addresses 0 + +#define cpu_dcache_line_size() 16 +#define cpu_icache_line_size() 16 + +#endif /* __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H */ diff --git a/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt288x/irq.h b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt288x/irq.h new file mode 100644 index 0000000000..61264f3c6a --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt288x/irq.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2008 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ +#ifndef __ASM_MACH_RALINK_RT288X_IRQ_H +#define __ASM_MACH_RALINK_RT288X_IRQ_H + +#define MIPS_CPU_IRQ_BASE 0 +#define NR_IRQS 48 + +#include_next + +#endif /* __ASM_MACH_RALINK_RT288X_IRQ_H */ diff --git a/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt288x_regs.h b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt288x_regs.h new file mode 100644 index 0000000000..b5f4812b5c --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt288x_regs.h @@ -0,0 +1,127 @@ +/* + * Ralink RT288x SoC register definitions + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _RT288X_REGS_H_ +#define _RT288X_REGS_H_ + +#include + +#define RT2880_SYSC_BASE 0x00300000 +#define RT2880_TIMER_BASE 0x00300100 +#define RT2880_INTC_BASE 0x00300200 +#define RT2880_MEMC_BASE 0x00300300 +#define RT2880_UART0_BASE 0x00300500 +#define RT2880_PIO_BASE 0x00300600 +#define RT2880_I2C_BASE 0x00300900 +#define RT2880_SPI_BASE 0x00300b00 +#define RT2880_UART1_BASE 0x00300c00 +#define RT2880_FE_BASE 0x00400000 +#define RT2880_ROM_BASE 0x00410000 +#define RT2880_PCM_BASE 0x00420000 +#define RT2880_PCI_BASE 0x00440000 +#define RT2880_WMAC_BASE 0x00480000 +#define RT2880_FLASH1_BASE 0x01000000 +#define RT2880_FLASH0_BASE 0x1dc00000 +#define RT2880_SDRAM_BASE 0x08000000 + +#define RT2880_SYSC_SIZE 0x100 +#define RT2880_TIMER_SIZE 0x100 +#define RT2880_INTC_SIZE 0x100 +#define RT2880_MEMC_SIZE 0x100 +#define RT2880_UART0_SIZE 0x100 +#define RT2880_PIO_SIZE 0x100 +#define RT2880_UART1_SIZE 0x100 +#define RT2880_FLASH1_SIZE (16 * 1024 * 1024) +#define RT2880_FLASH0_SIZE (32 * 1024 * 1024) + +/* SYSC registers */ +#define SYSC_REG_CHIP_NAME0 0x000 /* Chip Name 0 */ +#define SYSC_REG_CHIP_NAME1 0x004 /* Chip Name 1 */ +#define SYSC_REG_CHIP_ID 0x00c /* Chip Identification */ +#define SYSC_REG_SYSTEM_CONFIG 0x010 /* System Configuration */ +#define SYSC_REG_CLKCFG 0x030 +#define SYSC_REG_RESET_CTRL 0x034 /* Reset Control*/ +#define SYSC_REG_RESET_STATUS 0x038 /* Reset Status*/ +#define SYSC_REG_GPIO_MODE 0x060 /* GPIO Purpose Select */ +#define SYSC_REG_IA_ADDRESS 0x310 /* Illegal Access Address */ +#define SYSC_REG_IA_TYPE 0x314 /* Illegal Access Type */ + +#define CHIP_ID_ID_MASK 0xff +#define CHIP_ID_ID_SHIFT 8 +#define CHIP_ID_REV_MASK 0xff + +#define SYSTEM_CONFIG_CPUCLK_SHIFT 20 +#define SYSTEM_CONFIG_CPUCLK_MASK 0x3 +#define SYSTEM_CONFIG_CPUCLK_250 0x0 +#define SYSTEM_CONFIG_CPUCLK_266 0x1 +#define SYSTEM_CONFIG_CPUCLK_280 0x2 +#define SYSTEM_CONFIG_CPUCLK_300 0x3 + +#define CLKCFG_SRAM_CS_N_WDT BIT(9) + +#define RT2880_RESET_SYSTEM BIT(0) +#define RT2880_RESET_TIMER BIT(1) +#define RT2880_RESET_INTC BIT(2) +#define RT2880_RESET_MEMC BIT(3) +#define RT2880_RESET_CPU BIT(4) +#define RT2880_RESET_UART0 BIT(5) +#define RT2880_RESET_PIO BIT(6) +#define RT2880_RESET_I2C BIT(9) +#define RT2880_RESET_SPI BIT(11) +#define RT2880_RESET_UART1 BIT(12) +#define RT2880_RESET_PCI BIT(16) +#define RT2880_RESET_WMAC BIT(17) +#define RT2880_RESET_FE BIT(18) +#define RT2880_RESET_PCM BIT(19) + +#define RT2880_GPIO_MODE_I2C BIT(0) +#define RT2880_GPIO_MODE_UART0 BIT(1) +#define RT2880_GPIO_MODE_SPI BIT(2) +#define RT2880_GPIO_MODE_UART1 BIT(3) +#define RT2880_GPIO_MODE_JTAG BIT(4) +#define RT2880_GPIO_MODE_MDIO BIT(5) +#define RT2880_GPIO_MODE_SDRAM BIT(6) +#define RT2880_GPIO_MODE_PCI BIT(7) + +#define RT2880_INTC_INT_TIMER0 BIT(0) +#define RT2880_INTC_INT_TIMER1 BIT(1) +#define RT2880_INTC_INT_UART0 BIT(2) +#define RT2880_INTC_INT_PIO BIT(3) +#define RT2880_INTC_INT_PCM BIT(4) +#define RT2880_INTC_INT_UART1 BIT(8) +#define RT2880_INTC_INT_IA BIT(23) +#define RT2880_INTC_INT_GLOBAL BIT(31) + +/* MEMC registers */ +#define MEMC_REG_SDRAM_CFG0 0x00 +#define MEMC_REG_SDRAM_CFG1 0x04 +#define MEMC_REG_FLASH_CFG0 0x08 +#define MEMC_REG_FLASH_CFG1 0x0c +#define MEMC_REG_IA_ADDR 0x10 +#define MEMC_REG_IA_TYPE 0x14 + +#define FLASH_CFG_WIDTH_SHIFT 26 +#define FLASH_CFG_WIDTH_MASK 0x3 +#define FLASH_CFG_WIDTH_8BIT 0x0 +#define FLASH_CFG_WIDTH_16BIT 0x1 +#define FLASH_CFG_WIDTH_32BIT 0x2 + +/* UART registers */ +#define UART_REG_RX 0 +#define UART_REG_TX 1 +#define UART_REG_IER 2 +#define UART_REG_IIR 3 +#define UART_REG_FCR 4 +#define UART_REG_LCR 5 +#define UART_REG_MCR 6 +#define UART_REG_LSR 7 + +#endif /* _RT288X_REGS_H_ */ diff --git a/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt305x.h b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt305x.h new file mode 100644 index 0000000000..c59135c1ab --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt305x.h @@ -0,0 +1,169 @@ +/* + * Ralink RT305x SoC specific definitions + * + * Copyright (C) 2009-2011 Gabor Juhos + * + * Parts of this file are based on Ralink's 2.6.21 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _RT305X_H_ +#define _RT305X_H_ + +#include +#include + +enum rt305x_soc_type { + RT305X_SOC_UNKNOWN = 0, + RT305X_SOC_RT3050, + RT305X_SOC_RT3052, + RT305X_SOC_RT3350, + RT305X_SOC_RT3352, + RT305X_SOC_RT5350, +}; + +extern enum rt305x_soc_type rt305x_soc; + +static inline int soc_is_rt3050(void) +{ + return rt305x_soc == RT305X_SOC_RT3050; +} + +static inline int soc_is_rt3052(void) +{ + return rt305x_soc == RT305X_SOC_RT3052; +} + +static inline int soc_is_rt305x(void) +{ + return soc_is_rt3050() || soc_is_rt3052(); +} + +static inline int soc_is_rt3350(void) +{ + return rt305x_soc == RT305X_SOC_RT3350; +} + +static inline int soc_is_rt3352(void) +{ + return rt305x_soc == RT305X_SOC_RT3352; +} + +static inline int soc_is_rt5350(void) +{ + return rt305x_soc == RT305X_SOC_RT5350; +} + +#define RT305X_MEM_SIZE_MIN (2 * 1024 * 1024) +#define RT305X_MEM_SIZE_MAX (64 * 1024 * 1024) + +#define RT3352_MEM_SIZE_MIN (2 * 1024 * 1024) +#define RT3352_MEM_SIZE_MAX (256 * 1024 * 1024) + +#define RT305X_CPU_IRQ_BASE 0 +#define RT305X_INTC_IRQ_BASE 8 +#define RT305X_INTC_IRQ_COUNT 32 +#define RT305X_GPIO_IRQ_BASE 40 + +#define RT305X_CPU_IRQ_INTC (RT305X_CPU_IRQ_BASE + 2) +#define RT305X_CPU_IRQ_FE (RT305X_CPU_IRQ_BASE + 5) +#define RT305X_CPU_IRQ_WNIC (RT305X_CPU_IRQ_BASE + 6) +#define RT305X_CPU_IRQ_COUNTER (RT305X_CPU_IRQ_BASE + 7) + +#define RT305X_INTC_IRQ_SYSCTL (RT305X_INTC_IRQ_BASE + 0) +#define RT305X_INTC_IRQ_TIMER0 (RT305X_INTC_IRQ_BASE + 1) +#define RT305X_INTC_IRQ_TIMER1 (RT305X_INTC_IRQ_BASE + 2) +#define RT305X_INTC_IRQ_IA (RT305X_INTC_IRQ_BASE + 3) +#define RT305X_INTC_IRQ_PCM (RT305X_INTC_IRQ_BASE + 4) +#define RT305X_INTC_IRQ_UART0 (RT305X_INTC_IRQ_BASE + 5) +#define RT305X_INTC_IRQ_PIO (RT305X_INTC_IRQ_BASE + 6) +#define RT305X_INTC_IRQ_DMA (RT305X_INTC_IRQ_BASE + 7) +#define RT305X_INTC_IRQ_NAND (RT305X_INTC_IRQ_BASE + 8) +#define RT305X_INTC_IRQ_PERFC (RT305X_INTC_IRQ_BASE + 9) +#define RT305X_INTC_IRQ_I2S (RT305X_INTC_IRQ_BASE + 10) +#define RT305X_INTC_IRQ_UART1 (RT305X_INTC_IRQ_BASE + 12) +#define RT305X_INTC_IRQ_ESW (RT305X_INTC_IRQ_BASE + 17) +#define RT305X_INTC_IRQ_OTG (RT305X_INTC_IRQ_BASE + 18) + +extern void __iomem *rt305x_sysc_base; +extern void __iomem *rt305x_memc_base; + +static inline void rt305x_sysc_wr(u32 val, unsigned reg) +{ + __raw_writel(val, rt305x_sysc_base + reg); +} + +static inline u32 rt305x_sysc_rr(unsigned reg) +{ + return __raw_readl(rt305x_sysc_base + reg); +} + +static inline void rt305x_memc_wr(u32 val, unsigned reg) +{ + __raw_writel(val, rt305x_memc_base + reg); +} + +static inline u32 rt305x_memc_rr(unsigned reg) +{ + return __raw_readl(rt305x_memc_base + reg); +} + +#define RT305X_GPIO_I2C_SD 1 +#define RT305X_GPIO_I2C_SCLK 2 +#define RT305X_GPIO_SPI_EN 3 +#define RT305X_GPIO_SPI_CLK 4 +#define RT305X_GPIO_SPI_DOUT 5 +#define RT305X_GPIO_SPI_DIN 6 +/* GPIO 7-14 is shared between UART0, PCM and I2S interfaces */ +#define RT305X_GPIO_7 7 +#define RT305X_GPIO_8 8 +#define RT305X_GPIO_9 9 +#define RT305X_GPIO_10 10 +#define RT305X_GPIO_11 11 +#define RT305X_GPIO_12 12 +#define RT305X_GPIO_13 13 +#define RT305X_GPIO_14 14 +#define RT305X_GPIO_UART1_TXD 15 +#define RT305X_GPIO_UART1_RXD 16 +#define RT305X_GPIO_JTAG_TDO 17 +#define RT305X_GPIO_JTAG_TDI 18 +#define RT305X_GPIO_JTAG_TMS 19 +#define RT305X_GPIO_JTAG_TCLK 20 +#define RT305X_GPIO_JTAG_TRST_N 21 +#define RT305X_GPIO_MDIO_MDC 22 +#define RT305X_GPIO_MDIO_MDIO 23 +#define RT305X_GPIO_SDRAM_MD16 24 +#define RT305X_GPIO_SDRAM_MD17 25 +#define RT305X_GPIO_SDRAM_MD18 26 +#define RT305X_GPIO_SDRAM_MD19 27 +#define RT305X_GPIO_SDRAM_MD20 28 +#define RT305X_GPIO_SDRAM_MD21 29 +#define RT305X_GPIO_SDRAM_MD22 30 +#define RT305X_GPIO_SDRAM_MD23 31 +#define RT305X_GPIO_SDRAM_MD24 32 +#define RT305X_GPIO_SDRAM_MD25 33 +#define RT305X_GPIO_SDRAM_MD26 34 +#define RT305X_GPIO_SDRAM_MD27 35 +#define RT305X_GPIO_SDRAM_MD28 36 +#define RT305X_GPIO_SDRAM_MD29 37 +#define RT305X_GPIO_SDRAM_MD30 38 +#define RT305X_GPIO_SDRAM_MD31 39 +#define RT305X_GPIO_GE0_TXD0 40 +#define RT305X_GPIO_GE0_TXD1 41 +#define RT305X_GPIO_GE0_TXD2 42 +#define RT305X_GPIO_GE0_TXD3 43 +#define RT305X_GPIO_GE0_TXEN 44 +#define RT305X_GPIO_GE0_TXCLK 45 +#define RT305X_GPIO_GE0_RXD0 46 +#define RT305X_GPIO_GE0_RXD1 47 +#define RT305X_GPIO_GE0_RXD2 48 +#define RT305X_GPIO_GE0_RXD3 49 +#define RT305X_GPIO_GE0_RXDV 50 +#define RT305X_GPIO_GE0_RXCLK 51 + +void rt305x_gpio_init(u32 mode); + +#endif /* _RT305X_H_ */ diff --git a/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h new file mode 100644 index 0000000000..8c1261106c --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h @@ -0,0 +1,56 @@ +/* + * Ralink RT305x specific CPU feature overrides + * + * Copyright (C) 2008-2009 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This file was derived from: include/asm-mips/cpu-features.h + * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ +#ifndef __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_sb1_cache 0 +#define cpu_has_fpu 0 +#define cpu_has_32fpr 0 +#define cpu_has_counter 1 +#define cpu_has_watch 1 +#define cpu_has_divec 1 + +#define cpu_has_prefetch 1 +#define cpu_has_ejtag 1 +#define cpu_has_llsc 1 + +#define cpu_has_mips16 1 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 + +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 1 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + +#define cpu_has_dsp 1 +#define cpu_has_mipsmt 0 + +#define cpu_has_64bits 0 +#define cpu_has_64bit_zero_reg 0 +#define cpu_has_64bit_gp_regs 0 +#define cpu_has_64bit_addresses 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 + +#endif /* __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H */ diff --git a/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt305x/irq.h b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt305x/irq.h new file mode 100644 index 0000000000..a72d677142 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt305x/irq.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2008 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ +#ifndef __ASM_MACH_RALINK_RT305X_IRQ_H +#define __ASM_MACH_RALINK_RT305X_IRQ_H + +#define MIPS_CPU_IRQ_BASE 0 +#define NR_IRQS 48 + +#include_next + +#endif /* __ASM_MACH_RALINK_RT305X_IRQ_H */ diff --git a/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h new file mode 100644 index 0000000000..2098c5cc1f --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h @@ -0,0 +1,27 @@ +/* + * Ralink RT305x SoC platform device registration + * + * Copyright (C) 2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _RT305X_ESW_PLATFORM_H +#define _RT305X_ESW_PLATFORM_H + +enum { + RT305X_ESW_VLAN_CONFIG_NONE = 0, + RT305X_ESW_VLAN_CONFIG_LLLLW, + RT305X_ESW_VLAN_CONFIG_WLLLL, +}; + +struct rt305x_esw_platform_data +{ + u8 vlan_config; + u32 reg_initval_fct2; + u32 reg_initval_fpa2; +}; + +#endif /* _RT305X_ESW_PLATFORM_H */ diff --git a/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt305x_regs.h b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt305x_regs.h new file mode 100644 index 0000000000..943facb6de --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt305x_regs.h @@ -0,0 +1,216 @@ +/* + * Ralink RT305 SoC register definitions + * + * Copyright (C) 2009 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _RT305X_REGS_H_ +#define _RT305X_REGS_H_ + +#include + +#define RT305X_SDRAM_BASE 0x00000000 +#define RT305X_SYSC_BASE 0x10000000 +#define RT305X_TIMER_BASE 0x10000100 +#define RT305X_INTC_BASE 0x10000200 +#define RT305X_MEMC_BASE 0x10000300 +#define RT305X_PCM_BASE 0x10000400 +#define RT305X_UART0_BASE 0x10000500 +#define RT305X_PIO_BASE 0x10000600 +#define RT305X_GDMA_BASE 0x10000700 +#define RT305X_NANDC_BASE 0x10000800 +#define RT305X_I2C_BASE 0x10000900 +#define RT305X_I2S_BASE 0x10000a00 +#define RT305X_SPI_BASE 0x10000b00 +#define RT305X_UART1_BASE 0x10000c00 +#define RT305X_FE_BASE 0x10100000 +#define RT305X_SWITCH_BASE 0x10110000 +#define RT305X_WMAC_BASE 0x10180000 +#define RT305X_OTG_BASE 0x101c0000 +#define RT305X_ROM_BASE 0x00400000 +#define RT305X_FLASH1_BASE 0x1b000000 +#define RT305X_FLASH0_BASE 0x1f000000 + +#define RT305X_SYSC_SIZE 0x100 +#define RT305X_TIMER_SIZE 0x100 +#define RT305X_INTC_SIZE 0x100 +#define RT305X_MEMC_SIZE 0x100 +#define RT305X_UART0_SIZE 0x100 +#define RT305X_PIO_SIZE 0x100 +#define RT305X_UART1_SIZE 0x100 +#define RT305X_SPI_SIZE 0x100 +#define RT305X_FLASH1_SIZE (16 * 1024 * 1024) +#define RT305X_FLASH0_SIZE (8 * 1024 * 1024) + +#define RT3352_EHCI_BASE 0x101c0000 +#define RT3352_EHCI_SIZE 0x1000 +#define RT3352_OHCI_BASE 0x101c1000 +#define RT3352_OHCI_SIZE 0x1000 + +/* SYSC registers */ +#define SYSC_REG_CHIP_NAME0 0x000 /* Chip Name 0 */ +#define SYSC_REG_CHIP_NAME1 0x004 /* Chip Name 1 */ +#define SYSC_REG_CHIP_ID 0x00c /* Chip Identification */ +#define SYSC_REG_SYSTEM_CONFIG 0x010 /* System Configuration */ +#define SYSC_REG_RESET_CTRL 0x034 /* Reset Control*/ +#define SYSC_REG_RESET_STATUS 0x038 /* Reset Status*/ +#define SYSC_REG_GPIO_MODE 0x060 /* GPIO Purpose Select */ +#define SYSC_REG_IA_ADDRESS 0x310 /* Illegal Access Address */ +#define SYSC_REG_IA_TYPE 0x314 /* Illegal Access Type */ + +#define RT3352_SYSC_REG_SYSCFG1 0x014 +#define RT3352_SYSC_REG_CLKCFG1 0x030 +#define RT3352_SYSC_REG_RSTCTRL 0x034 +#define RT3352_SYSC_REG_USB_PS 0x05c + +#define RT3052_CHIP_NAME0 0x30335452 +#define RT3052_CHIP_NAME1 0x20203235 + +#define RT3350_CHIP_NAME0 0x33335452 +#define RT3350_CHIP_NAME1 0x20203035 + +#define RT3352_CHIP_NAME0 0x33335452 +#define RT3352_CHIP_NAME1 0x20203235 + +#define RT5350_CHIP_NAME0 0x33355452 +#define RT5350_CHIP_NAME1 0x20203035 + +#define CHIP_ID_ID_MASK 0xff +#define CHIP_ID_ID_SHIFT 8 +#define CHIP_ID_REV_MASK 0xff + +#define RT305X_SYSCFG_CPUCLK_SHIFT 18 +#define RT305X_SYSCFG_CPUCLK_MASK 0x1 +#define RT305X_SYSCFG_CPUCLK_LOW 0x0 +#define RT305X_SYSCFG_CPUCLK_HIGH 0x1 +#define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT 2 +#define RT305X_SYSCFG_SRAM_CS0_MODE_MASK 0x3 +#define RT305X_SYSCFG_SRAM_CS0_MODE_NORMAL 0 +#define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 1 +#define RT305X_SYSCFG_SRAM_CS0_MODE_BTCOEX 2 + +#define RT3352_SYSCFG0_CPUCLK_SHIFT 8 +#define RT3352_SYSCFG0_CPUCLK_MASK 0x1 +#define RT3352_SYSCFG0_CPUCLK_LOW 0x0 +#define RT3352_SYSCFG0_CPUCLK_HIGH 0x1 + +#define RT5350_SYSCFG0_CPUCLK_SHIFT 8 +#define RT5350_SYSCFG0_CPUCLK_MASK 0x3 +#define RT5350_SYSCFG0_CPUCLK_360 0x0 +#define RT5350_SYSCFG0_CPUCLK_320 0x2 +#define RT5350_SYSCFG0_CPUCLK_300 0x3 +#define RT5350_SYSCFG0_DRAM_SIZE_SHIFT 12 +#define RT5350_SYSCFG0_DRAM_SIZE_MASK 7 +#define RT5350_SYSCFG0_DRAM_SIZE_2M 0 +#define RT5350_SYSCFG0_DRAM_SIZE_8M 1 +#define RT5350_SYSCFG0_DRAM_SIZE_16M 2 +#define RT5350_SYSCFG0_DRAM_SIZE_32M 3 +#define RT5350_SYSCFG0_DRAM_SIZE_64M 4 + +#define RT3352_SYSCFG0_XTAL_SEL BIT(20) + +#define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10) + +#define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18) +#define RT3352_CLKCFG1_UPHY1_CLK_EN BIT(20) + +#define RT305X_GPIO_MODE_I2C BIT(0) +#define RT305X_GPIO_MODE_SPI BIT(1) +#define RT305X_GPIO_MODE_UART0_SHIFT 2 +#define RT305X_GPIO_MODE_UART0_MASK 0x7 +#define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT) +#define RT305X_GPIO_MODE_UARTF 0x0 +#define RT305X_GPIO_MODE_PCM_UARTF 0x1 +#define RT305X_GPIO_MODE_PCM_I2S 0x2 +#define RT305X_GPIO_MODE_I2S_UARTF 0x3 +#define RT305X_GPIO_MODE_PCM_GPIO 0x4 +#define RT305X_GPIO_MODE_GPIO_UARTF 0x5 +#define RT305X_GPIO_MODE_GPIO_I2S 0x6 +#define RT305X_GPIO_MODE_GPIO 0x7 +#define RT305X_GPIO_MODE_UART1 BIT(5) +#define RT305X_GPIO_MODE_JTAG BIT(6) +#define RT305X_GPIO_MODE_MDIO BIT(7) +#define RT305X_GPIO_MODE_SDRAM BIT(8) +#define RT305X_GPIO_MODE_RGMII BIT(9) + +#define RT305X_RESET_SYSTEM BIT(0) +#define RT305X_RESET_TIMER BIT(8) +#define RT305X_RESET_INTC BIT(9) +#define RT305X_RESET_MEMC BIT(10) +#define RT305X_RESET_PCM BIT(11) +#define RT305X_RESET_UART0 BIT(12) +#define RT305X_RESET_PIO BIT(13) +#define RT305X_RESET_DMA BIT(14) +#define RT305X_RESET_I2C BIT(16) +#define RT305X_RESET_I2S BIT(17) +#define RT305X_RESET_SPI BIT(18) +#define RT305X_RESET_UART1 BIT(19) +#define RT305X_RESET_WNIC BIT(20) +#define RT305X_RESET_FE BIT(21) +#define RT305X_RESET_OTG BIT(22) +#define RT305X_RESET_ESW BIT(23) + +#define RT3352_RSTCTRL_SYS BIT(0) +#define RT3352_RSTCTRL_TIMER BIT(8) +#define RT3352_RSTCTRL_INTC BIT(9) +#define RT3352_RSTCTRL_MEMC BIT(10) +#define RT3352_RSTCTRL_PCM BIT(11) +#define RT3352_RSTCTRL_UART0 BIT(12) +#define RT3352_RSTCTRL_PIO BIT(13) +#define RT3352_RSTCTRL_DMA BIT(14) +#define RT3352_RSTCTRL_I2C BIT(16) +#define RT3352_RSTCTRL_I2S BIT(17) +#define RT3352_RSTCTRL_SPI BIT(18) +#define RT3352_RSTCTRL_UART1 BIT(19) +#define RT3352_RSTCTRL_WNIC BIT(20) +#define RT3352_RSTCTRL_FE BIT(21) +#define RT3352_RSTCTRL_UHST BIT(22) +#define RT3352_RSTCTRL_ESW BIT(23) +#define RT3352_RSTCTRL_EPHY BIT(24) +#define RT3352_RSTCTRL_UDEV BIT(25) + +#define RT305X_INTC_INT_SYSCTL BIT(0) +#define RT305X_INTC_INT_TIMER0 BIT(1) +#define RT305X_INTC_INT_TIMER1 BIT(2) +#define RT305X_INTC_INT_IA BIT(3) +#define RT305X_INTC_INT_PCM BIT(4) +#define RT305X_INTC_INT_UART0 BIT(5) +#define RT305X_INTC_INT_PIO BIT(6) +#define RT305X_INTC_INT_DMA BIT(7) +#define RT305X_INTC_INT_NAND BIT(8) +#define RT305X_INTC_INT_PERFC BIT(9) +#define RT305X_INTC_INT_I2S BIT(10) +#define RT305X_INTC_INT_UART1 BIT(12) +#define RT305X_INTC_INT_ESW BIT(17) +#define RT305X_INTC_INT_OTG BIT(18) +#define RT305X_INTC_INT_GLOBAL BIT(31) + +/* MEMC registers */ +#define MEMC_REG_SDRAM_CFG0 0x00 +#define MEMC_REG_SDRAM_CFG1 0x04 +#define MEMC_REG_FLASH_CFG0 0x08 +#define MEMC_REG_FLASH_CFG1 0x0c +#define MEMC_REG_IA_ADDR 0x10 +#define MEMC_REG_IA_TYPE 0x14 + +#define FLASH_CFG_WIDTH_SHIFT 26 +#define FLASH_CFG_WIDTH_MASK 0x3 +#define FLASH_CFG_WIDTH_8BIT 0x0 +#define FLASH_CFG_WIDTH_16BIT 0x1 +#define FLASH_CFG_WIDTH_32BIT 0x2 + +/* UART registers */ +#define UART_REG_RX 0 +#define UART_REG_TX 1 +#define UART_REG_IER 2 +#define UART_REG_IIR 3 +#define UART_REG_FCR 4 +#define UART_REG_LCR 5 +#define UART_REG_MCR 6 +#define UART_REG_LSR 7 + +#endif /* _RT305X_REGS_H_ */ diff --git a/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt3883.h b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt3883.h new file mode 100644 index 0000000000..cf8fb6fd10 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt3883.h @@ -0,0 +1,152 @@ +/* + * Ralink RT3662/RT3883 SoC specific definitions + * + * Copyright (C) 2011-2012 Gabor Juhos + * + * Parts of this file are based on Ralink's 2.6.21 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _RT3883_H_ +#define _RT3883_H_ + +#include +#include + +#define RT3883_MEM_SIZE_MIN (2 * 1024 * 1024) +#define RT3883_MEM_SIZE_MAX (256 * 1024 * 1024) + +#define RT3883_CPU_IRQ_BASE 0 +#define RT3883_CPU_IRQ_COUNT 8 +#define RT3883_INTC_IRQ_BASE (RT3883_CPU_IRQ_BASE + RT3883_CPU_IRQ_COUNT) +#define RT3883_INTC_IRQ_COUNT 32 +#define RT3883_GPIO_IRQ_BASE (RT3883_INTC_IRQ_BASE + RT3883_INTC_IRQ_COUNT) +#define RT3883_GPIO_IRQ_COUNT 96 +#define RT3883_PCI_IRQ_BASE (RT3883_GPIO_IRQ_BASE + RT3883_GPIO_IRQ_COUNT) +#define RT3883_PCI_IRQ_COUNT 3 + +#define RT3883_CPU_IRQ_INTC (RT3883_CPU_IRQ_BASE + 2) +#define RT3883_CPU_IRQ_PCI (RT3883_CPU_IRQ_BASE + 4) +#define RT3883_CPU_IRQ_FE (RT3883_CPU_IRQ_BASE + 5) +#define RT3883_CPU_IRQ_WLAN (RT3883_CPU_IRQ_BASE + 6) +#define RT3883_CPU_IRQ_COUNTER (RT3883_CPU_IRQ_BASE + 7) + +#define RT3883_INTC_IRQ_SYSCTL (RT3883_INTC_IRQ_BASE + 0) +#define RT3883_INTC_IRQ_TIMER0 (RT3883_INTC_IRQ_BASE + 1) +#define RT3883_INTC_IRQ_TIMER1 (RT3883_INTC_IRQ_BASE + 2) +#define RT3883_INTC_IRQ_IA (RT3883_INTC_IRQ_BASE + 3) +#define RT3883_INTC_IRQ_PCM (RT3883_INTC_IRQ_BASE + 4) +#define RT3883_INTC_IRQ_UART0 (RT3883_INTC_IRQ_BASE + 5) +#define RT3883_INTC_IRQ_PIO (RT3883_INTC_IRQ_BASE + 6) +#define RT3883_INTC_IRQ_DMA (RT3883_INTC_IRQ_BASE + 7) +#define RT3883_INTC_IRQ_NAND (RT3883_INTC_IRQ_BASE + 8) +#define RT3883_INTC_IRQ_PERFC (RT3883_INTC_IRQ_BASE + 9) +#define RT3883_INTC_IRQ_I2S (RT3883_INTC_IRQ_BASE + 10) +#define RT3883_INTC_IRQ_UART1 (RT3883_INTC_IRQ_BASE + 12) +#define RT3883_INTC_IRQ_UHST (RT3883_INTC_IRQ_BASE + 18) +#define RT3883_INTC_IRQ_UDEV (RT3883_INTC_IRQ_BASE + 19) + +#define RT3883_PCI_IRQ_PCI0 (RT3883_PCI_IRQ_BASE + 0) +#define RT3883_PCI_IRQ_PCI1 (RT3883_PCI_IRQ_BASE + 1) +#define RT3883_PCI_IRQ_PCIE (RT3883_PCI_IRQ_BASE + 2) + +extern void __iomem *rt3883_sysc_base; +extern void __iomem *rt3883_memc_base; + +static inline void rt3883_sysc_wr(u32 val, unsigned reg) +{ + __raw_writel(val, rt3883_sysc_base + reg); +} + +static inline u32 rt3883_sysc_rr(unsigned reg) +{ + return __raw_readl(rt3883_sysc_base + reg); +} + +static inline void rt3883_memc_wr(u32 val, unsigned reg) +{ + __raw_writel(val, rt3883_memc_base + reg); +} + +static inline u32 rt3883_memc_rr(unsigned reg) +{ + return __raw_readl(rt3883_memc_base + reg); +} + +#define RT3883_GPIO_I2C_SD 1 +#define RT3883_GPIO_I2C_SCLK 2 +#define RT3883_GPIO_SPI_CS0 3 +#define RT3883_GPIO_SPI_CLK 4 +#define RT3883_GPIO_SPI_MOSI 5 +#define RT3883_GPIO_SPI_MISO 6 +/* GPIO 7-14 is shared between UART0, PCM and I2S interfaces */ +#define RT3883_GPIO_7 7 +#define RT3883_GPIO_8 8 +#define RT3883_GPIO_9 9 +#define RT3883_GPIO_10 10 +#define RT3883_GPIO_11 11 +#define RT3883_GPIO_12 12 +#define RT3883_GPIO_13 13 +#define RT3883_GPIO_14 14 +#define RT3883_GPIO_UART1_TXD 15 +#define RT3883_GPIO_UART1_RXD 16 +#define RT3883_GPIO_JTAG_TDO 17 +#define RT3883_GPIO_JTAG_TDI 18 +#define RT3883_GPIO_JTAG_TMS 19 +#define RT3883_GPIO_JTAG_TCLK 20 +#define RT3883_GPIO_JTAG_TRST_N 21 +#define RT3883_GPIO_MDIO_MDC 22 +#define RT3883_GPIO_MDIO_MDIO 23 +#define RT3883_GPIO_LNA_PE_A0 32 +#define RT3883_GPIO_LNA_PE_A1 33 +#define RT3883_GPIO_LNA_PE_A2 34 +#define RT3883_GPIO_LNA_PE_G0 35 +#define RT3883_GPIO_LNA_PE_G1 36 +#define RT3883_GPIO_LNA_PE_G2 37 +#define RT3883_GPIO_PCI_AD0 40 +#define RT3883_GPIO_PCI_AD31 71 +#define RT3883_GPIO_GE2_TXD0 72 +#define RT3883_GPIO_GE2_TXD1 73 +#define RT3883_GPIO_GE2_TXD2 74 +#define RT3883_GPIO_GE2_TXD3 75 +#define RT3883_GPIO_GE2_TXEN 76 +#define RT3883_GPIO_GE2_TXCLK 77 +#define RT3883_GPIO_GE2_RXD0 78 +#define RT3883_GPIO_GE2_RXD1 79 +#define RT3883_GPIO_GE2_RXD2 80 +#define RT3883_GPIO_GE2_RXD3 81 +#define RT3883_GPIO_GE2_RXDV 82 +#define RT3883_GPIO_GE2_RXCLK 83 +#define RT3883_GPIO_GE1_TXD0 84 +#define RT3883_GPIO_GE1_TXD1 85 +#define RT3883_GPIO_GE1_TXD2 86 +#define RT3883_GPIO_GE1_TXD3 87 +#define RT3883_GPIO_GE1_TXEN 88 +#define RT3883_GPIO_GE1_TXCLK 89 +#define RT3883_GPIO_GE1_RXD0 90 +#define RT3883_GPIO_GE1_RXD1 91 +#define RT3883_GPIO_GE1_RXD2 92 +#define RT3883_GPIO_GE1_RXD3 93 +#define RT3883_GPIO_GE1_RXDV 94 +#define RT3883_GPIO_GE1_RXCLK 95 + +void rt3883_gpio_init(u32 mode); + +#define RT3883_PCI_MODE_PCI 0x01 +#define RT3883_PCI_MODE_PCIE 0x02 +#define RT3883_PCI_MODE_BOTH (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE) + +struct pci_dev; + +#ifdef CONFIG_PCI +void rt3883_pci_init(unsigned mode); +void rt3883_pci_set_plat_dev_init(int (*f)(struct pci_dev *)); +#else +static inline void rt3883_pci_init(unsigned mode) {} +static inline void rt3883_pci_set_plat_dev_init(int (*f)(struct pci_dev *)) {} +#endif /* CONFIG_PCI */ + +#endif /* _RT3883_H_ */ diff --git a/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h new file mode 100644 index 0000000000..ac435dd330 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h @@ -0,0 +1,55 @@ +/* + * Ralink RT3662/RT3883 specific CPU feature overrides + * + * Copyright (C) 2011-2012 Gabor Juhos + * + * This file was derived from: include/asm-mips/cpu-features.h + * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ +#ifndef __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_sb1_cache 0 +#define cpu_has_fpu 0 +#define cpu_has_32fpr 0 +#define cpu_has_counter 1 +#define cpu_has_watch 1 +#define cpu_has_divec 1 + +#define cpu_has_prefetch 1 +#define cpu_has_ejtag 1 +#define cpu_has_llsc 1 + +#define cpu_has_mips16 1 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 + +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 1 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + +#define cpu_has_dsp 1 +#define cpu_has_mipsmt 0 + +#define cpu_has_64bits 0 +#define cpu_has_64bit_zero_reg 0 +#define cpu_has_64bit_gp_regs 0 +#define cpu_has_64bit_addresses 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 + +#endif /* __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H */ diff --git a/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt3883/irq.h b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt3883/irq.h new file mode 100644 index 0000000000..635d68c101 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt3883/irq.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ +#ifndef __ASM_MACH_RALINK_RT3883_IRQ_H +#define __ASM_MACH_RALINK_RT3883_IRQ_H + +#define MIPS_CPU_IRQ_BASE 0 +#define NR_IRQS 140 + +#include_next + +#endif /* __ASM_MACH_RALINK_RT3883_IRQ_H */ diff --git a/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt3883_regs.h b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt3883_regs.h new file mode 100644 index 0000000000..b36cabe858 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/rt3883_regs.h @@ -0,0 +1,207 @@ +/* + * Ralink RT3662/RT3883 SoC register definitions + * + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _RT3883_REGS_H_ +#define _RT3883_REGS_H_ + +#include + +#define RT3883_SDRAM_BASE 0x00000000 +#define RT3883_SYSC_BASE 0x10000000 +#define RT3883_TIMER_BASE 0x10000100 +#define RT3883_INTC_BASE 0x10000200 +#define RT3883_MEMC_BASE 0x10000300 +#define RT3883_UART0_BASE 0x10000500 +#define RT3883_PIO_BASE 0x10000600 +#define RT3883_FSCC_BASE 0x10000700 +#define RT3883_NANDC_BASE 0x10000810 +#define RT3883_I2C_BASE 0x10000900 +#define RT3883_I2S_BASE 0x10000a00 +#define RT3883_SPI_BASE 0x10000b00 +#define RT3883_UART1_BASE 0x10000c00 +#define RT3883_PCM_BASE 0x10002000 +#define RT3883_GDMA_BASE 0x10002800 +#define RT3883_CODEC1_BASE 0x10003000 +#define RT3883_CODEC2_BASE 0x10003800 +#define RT3883_FE_BASE 0x10100000 +#define RT3883_ROM_BASE 0x10118000 +#define RT3883_USBDEV_BASE 0x10112000 +#define RT3883_PCI_BASE 0x10140000 +#define RT3883_WLAN_BASE 0x10180000 +#define RT3883_USBHOST_BASE 0x101c0000 +#define RT3883_BOOT_BASE 0x1c000000 +#define RT3883_SRAM_BASE 0x1e000000 +#define RT3883_PCIMEM_BASE 0x20000000 + +#define RT3883_EHCI_BASE (RT3883_USBHOST_BASE) +#define RT3883_OHCI_BASE (RT3883_USBHOST_BASE + 0x1000) + +#define RT3883_SYSC_SIZE 0x100 +#define RT3883_TIMER_SIZE 0x100 +#define RT3883_INTC_SIZE 0x100 +#define RT3883_MEMC_SIZE 0x100 +#define RT3883_UART0_SIZE 0x100 +#define RT3883_UART1_SIZE 0x100 +#define RT3883_PIO_SIZE 0x100 +#define RT3883_FSCC_SIZE 0x100 +#define RT3883_NANDC_SIZE 0x0f0 +#define RT3883_I2C_SIZE 0x100 +#define RT3883_I2S_SIZE 0x100 +#define RT3883_SPI_SIZE 0x100 +#define RT3883_PCM_SIZE 0x800 +#define RT3883_GDMA_SIZE 0x800 +#define RT3883_CODEC1_SIZE 0x800 +#define RT3883_CODEC2_SIZE 0x800 +#define RT3883_FE_SIZE 0x10000 +#define RT3883_ROM_SIZE 0x4000 +#define RT3883_USBDEV_SIZE 0x4000 +#define RT3883_PCI_SIZE 0x40000 +#define RT3883_WLAN_SIZE 0x40000 +#define RT3883_USBHOST_SIZE 0x40000 +#define RT3883_BOOT_SIZE (32 * 1024 * 1024) +#define RT3883_SRAM_SIZE (32 * 1024 * 1024) + +/* SYSC registers */ +#define RT3883_SYSC_REG_CHIPID0_3 0x00 /* Chip ID 0 */ +#define RT3883_SYSC_REG_CHIPID4_7 0x04 /* Chip ID 1 */ +#define RT3883_SYSC_REG_REVID 0x0c /* Chip Revision Identification */ +#define RT3883_SYSC_REG_SYSCFG0 0x10 /* System Configuration 0 */ +#define RT3883_SYSC_REG_SYSCFG1 0x14 /* System Configuration 1 */ +#define RT3883_SYSC_REG_CLKCFG0 0x2c /* Clock Configuration 0 */ +#define RT3883_SYSC_REG_CLKCFG1 0x30 /* Clock Configuration 1 */ +#define RT3883_SYSC_REG_RSTCTRL 0x34 /* Reset Control*/ +#define RT3883_SYSC_REG_RSTSTAT 0x38 /* Reset Status*/ +#define RT3883_SYSC_REG_USB_PS 0x5c /* USB Power saving control */ +#define RT3883_SYSC_REG_GPIO_MODE 0x60 /* GPIO Purpose Select */ +#define RT3883_SYSC_REG_PCIE_CLK_GEN0 0x7c +#define RT3883_SYSC_REG_PCIE_CLK_GEN1 0x80 +#define RT3883_SYSC_REG_PCIE_CLK_GEN2 0x84 +#define RT3883_SYSC_REG_PMU 0x88 +#define RT3883_SYSC_REG_PMU1 0x8c + +#define RT3883_REVID_VER_ID_MASK 0x0f +#define RT3883_REVID_VER_ID_SHIFT 8 +#define RT3883_REVID_ECO_ID_MASK 0x0f + +#define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17) +#define RT3883_SYSCFG0_CPUCLK_SHIFT 8 +#define RT3883_SYSCFG0_CPUCLK_MASK 0x3 +#define RT3883_SYSCFG0_CPUCLK_250 0x0 +#define RT3883_SYSCFG0_CPUCLK_384 0x1 +#define RT3883_SYSCFG0_CPUCLK_480 0x2 +#define RT3883_SYSCFG0_CPUCLK_500 0x3 + +#define RT3883_SYSCFG1_USB0_HOST_MODE BIT(10) +#define RT3883_SYSCFG1_PCIE_RC_MODE BIT(8) +#define RT3883_SYSCFG1_PCI_HOST_MODE BIT(7) +#define RT3883_SYSCFG1_PCI_66M_MODE BIT(6) +#define RT3883_SYSCFG1_GPIO2_AS_WDT_OUT BIT(2) + +#define RT3883_CLKCFG1_PCIE_CLK_EN BIT(21) +#define RT3883_CLKCFG1_UPHY1_CLK_EN BIT(20) +#define RT3883_CLKCFG1_PCI_CLK_EN BIT(19) +#define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18) + +#define RT3883_GPIO_MODE_I2C BIT(0) +#define RT3883_GPIO_MODE_SPI BIT(1) +#define RT3883_GPIO_MODE_UART0_SHIFT 2 +#define RT3883_GPIO_MODE_UART0_MASK 0x7 +#define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT) +#define RT3883_GPIO_MODE_UARTF 0x0 +#define RT3883_GPIO_MODE_PCM_UARTF 0x1 +#define RT3883_GPIO_MODE_PCM_I2S 0x2 +#define RT3883_GPIO_MODE_I2S_UARTF 0x3 +#define RT3883_GPIO_MODE_PCM_GPIO 0x4 +#define RT3883_GPIO_MODE_GPIO_UARTF 0x5 +#define RT3883_GPIO_MODE_GPIO_I2S 0x6 +#define RT3883_GPIO_MODE_GPIO 0x7 +#define RT3883_GPIO_MODE_UART1 BIT(5) +#define RT3883_GPIO_MODE_JTAG BIT(6) +#define RT3883_GPIO_MODE_MDIO BIT(7) +#define RT3883_GPIO_MODE_GE1 BIT(9) +#define RT3883_GPIO_MODE_GE2 BIT(10) +#define RT3883_GPIO_MODE_PCI_SHIFT 11 +#define RT3883_GPIO_MODE_PCI_MASK 0x7 +#define RT3883_GPIO_MODE_PCI(_x) ((_x) << RT3883_GPIO_MODE_PCI_SHIFT) +#define RT3883_GPIO_MODE_PCI_DEV 0 +#define RT3883_GPIO_MODE_PCI_HOST2 1 +#define RT3883_GPIO_MODE_PCI_HOST1 2 +#define RT3883_GPIO_MODE_PCI_FNC 3 +#define RT3883_GPIO_MODE_PCI_GPIO 7 +#define RT3883_GPIO_MODE_LNA_A_SHIFT 16 +#define RT3883_GPIO_MODE_LNA_A_MASK 0x3 +#define RT3883_GPIO_MODE_LNA_A(_x) ((_x) << RT3883_GPIO_MODE_LNA_A_SHIFT) +#define RT3883_GPIO_MODE_LNA_A_GPIO 0x3 +#define RT3883_GPIO_MODE_LNA_G_SHIFT 18 +#define RT3883_GPIO_MODE_LNA_G_MASK 0x3 +#define RT3883_GPIO_MODE_LNA_G(_x) ((_x) << RT3883_GPIO_MODE_LNA_G_SHIFT) +#define RT3883_GPIO_MODE_LNA_G_GPIO 0x3 + +#define RT3883_RSTCTRL_PCIE_PCI_PDM BIT(27) +#define RT3883_RSTCTRL_FLASH BIT(26) +#define RT3883_RSTCTRL_UDEV BIT(25) +#define RT3883_RSTCTRL_PCI BIT(24) +#define RT3883_RSTCTRL_PCIE BIT(23) +#define RT3883_RSTCTRL_UHST BIT(22) +#define RT3883_RSTCTRL_FE BIT(21) +#define RT3883_RSTCTRL_WLAN BIT(20) +#define RT3883_RSTCTRL_UART1 BIT(29) +#define RT3883_RSTCTRL_SPI BIT(18) +#define RT3883_RSTCTRL_I2S BIT(17) +#define RT3883_RSTCTRL_I2C BIT(16) +#define RT3883_RSTCTRL_NAND BIT(15) +#define RT3883_RSTCTRL_DMA BIT(14) +#define RT3883_RSTCTRL_PIO BIT(13) +#define RT3883_RSTCTRL_UART BIT(12) +#define RT3883_RSTCTRL_PCM BIT(11) +#define RT3883_RSTCTRL_MC BIT(10) +#define RT3883_RSTCTRL_INTC BIT(9) +#define RT3883_RSTCTRL_TIMER BIT(8) +#define RT3883_RSTCTRL_SYS BIT(0) + +#define RT3883_INTC_INT_SYSCTL BIT(0) +#define RT3883_INTC_INT_TIMER0 BIT(1) +#define RT3883_INTC_INT_TIMER1 BIT(2) +#define RT3883_INTC_INT_IA BIT(3) +#define RT3883_INTC_INT_PCM BIT(4) +#define RT3883_INTC_INT_UART0 BIT(5) +#define RT3883_INTC_INT_PIO BIT(6) +#define RT3883_INTC_INT_DMA BIT(7) +#define RT3883_INTC_INT_NAND BIT(8) +#define RT3883_INTC_INT_PERFC BIT(9) +#define RT3883_INTC_INT_I2S BIT(10) +#define RT3883_INTC_INT_UART1 BIT(12) +#define RT3883_INTC_INT_UHST BIT(18) +#define RT3883_INTC_INT_UDEV BIT(19) + +/* FLASH/SRAM/Codec Controller registers */ +#define RT3883_FSCC_REG_FLASH_CFG0 0x00 +#define RT3883_FSCC_REG_FLASH_CFG1 0x04 +#define RT3883_FSCC_REG_CODEC_CFG0 0x40 +#define RT3883_FSCC_REG_CODEC_CFG1 0x44 + +#define RT3883_FLASH_CFG_WIDTH_SHIFT 26 +#define RT3883_FLASH_CFG_WIDTH_MASK 0x3 +#define RT3883_FLASH_CFG_WIDTH_8BIT 0x0 +#define RT3883_FLASH_CFG_WIDTH_16BIT 0x1 +#define RT3883_FLASH_CFG_WIDTH_32BIT 0x2 + + +/* UART registers */ +#define RT3883_UART_REG_RX 0 +#define RT3883_UART_REG_TX 1 +#define RT3883_UART_REG_IER 2 +#define RT3883_UART_REG_IIR 3 +#define RT3883_UART_REG_FCR 4 +#define RT3883_UART_REG_LCR 5 +#define RT3883_UART_REG_MCR 6 +#define RT3883_UART_REG_LSR 7 + +#endif /* _RT3883_REGS_H_ */ diff --git a/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/war.h b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/war.h new file mode 100644 index 0000000000..a7b712cf2d --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/include/asm/mach-ralink/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MACH_RALINK_WAR_H +#define __ASM_MACH_RALINK_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MACH_RALINK_WAR_H */ diff --git a/target/linux/ramips/files-3.7/arch/mips/pci/pci-rt288x.c b/target/linux/ramips/files-3.7/arch/mips/pci/pci-rt288x.c new file mode 100644 index 0000000000..f67902272c --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/pci/pci-rt288x.c @@ -0,0 +1,250 @@ +/* + * Ralink RT288x SoC PCI register definitions + * + * Copyright (C) 2009 John Crispin + * Copyright (C) 2009 Gabor Juhos + * + * Parts of this file are based on Ralink's 2.6.21 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include + +#define RT2880_PCI_MEM_BASE 0x20000000 +#define RT2880_PCI_MEM_SIZE 0x10000000 +#define RT2880_PCI_IO_BASE 0x00460000 +#define RT2880_PCI_IO_SIZE 0x00010000 + +#define RT2880_PCI_REG_PCICFG_ADDR 0x00 +#define RT2880_PCI_REG_PCIMSK_ADDR 0x0c +#define RT2880_PCI_REG_BAR0SETUP_ADDR 0x10 +#define RT2880_PCI_REG_IMBASEBAR0_ADDR 0x18 +#define RT2880_PCI_REG_CONFIG_ADDR 0x20 +#define RT2880_PCI_REG_CONFIG_DATA 0x24 +#define RT2880_PCI_REG_MEMBASE 0x28 +#define RT2880_PCI_REG_IOBASE 0x2c +#define RT2880_PCI_REG_ID 0x30 +#define RT2880_PCI_REG_CLASS 0x34 +#define RT2880_PCI_REG_SUBID 0x38 +#define RT2880_PCI_REG_ARBCTL 0x80 + +static void __iomem *rt2880_pci_base; +static DEFINE_SPINLOCK(rt2880_pci_lock); + +static u32 rt2880_pci_reg_read(u32 reg) +{ + return readl(rt2880_pci_base + reg); +} + +static void rt2880_pci_reg_write(u32 val, u32 reg) +{ + writel(val, rt2880_pci_base + reg); +} + +static inline u32 rt2880_pci_get_cfgaddr(unsigned int bus, unsigned int slot, + unsigned int func, unsigned int where) +{ + return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | + 0x80000000); +} + +static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + unsigned long flags; + u32 address; + u32 data; + + address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), + PCI_FUNC(devfn), where); + + spin_lock_irqsave(&rt2880_pci_lock, flags); + rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR); + data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA); + spin_unlock_irqrestore(&rt2880_pci_lock, flags); + + switch (size) { + case 1: + *val = (data >> ((where & 3) << 3)) & 0xff; + break; + case 2: + *val = (data >> ((where & 3) << 3)) & 0xffff; + break; + case 4: + *val = data; + break; + } + + return PCIBIOS_SUCCESSFUL; +} + +static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + unsigned long flags; + u32 address; + u32 data; + + address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), + PCI_FUNC(devfn), where); + + spin_lock_irqsave(&rt2880_pci_lock, flags); + rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR); + data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA); + + switch (size) { + case 1: + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + break; + case 2: + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + break; + case 4: + data = val; + break; + } + + rt2880_pci_reg_write(data, RT2880_PCI_REG_CONFIG_DATA); + spin_unlock_irqrestore(&rt2880_pci_lock, flags); + + return PCIBIOS_SUCCESSFUL; +} + +static struct pci_ops rt2880_pci_ops = { + .read = rt2880_pci_config_read, + .write = rt2880_pci_config_write, +}; + +static struct resource rt2880_pci_mem_resource = { + .name = "PCI MEM space", + .start = RT2880_PCI_MEM_BASE, + .end = RT2880_PCI_MEM_BASE + RT2880_PCI_MEM_SIZE - 1, + .flags = IORESOURCE_MEM, +}; + +static struct resource rt2880_pci_io_resource = { + .name = "PCI IO space", + .start = RT2880_PCI_IO_BASE, + .end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1, + .flags = IORESOURCE_IO, +}; + +static struct pci_controller rt2880_pci_controller = { + .pci_ops = &rt2880_pci_ops, + .mem_resource = &rt2880_pci_mem_resource, + .io_resource = &rt2880_pci_io_resource, +}; + +static inline u32 rt2880_pci_read_u32(unsigned long reg) +{ + unsigned long flags; + u32 address; + u32 ret; + + address = rt2880_pci_get_cfgaddr(0, 0, 0, reg); + + spin_lock_irqsave(&rt2880_pci_lock, flags); + rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR); + ret = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA); + spin_unlock_irqrestore(&rt2880_pci_lock, flags); + + return ret; +} + +static inline void rt2880_pci_write_u32(unsigned long reg, u32 val) +{ + unsigned long flags; + u32 address; + + address = rt2880_pci_get_cfgaddr(0, 0, 0, reg); + + spin_lock_irqsave(&rt2880_pci_lock, flags); + rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR); + rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA); + spin_unlock_irqrestore(&rt2880_pci_lock, flags); +} + +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + u16 cmd; + int irq = -1; + + if (dev->bus->number != 0) + return irq; + + switch (PCI_SLOT(dev->devfn)) { + case 0x00: + rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000); + (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0); + break; + case 0x11: + irq = RT288X_CPU_IRQ_PCI; + break; + default: + printk("%s:%s[%d] trying to alloc unknown pci irq\n", + __FILE__, __func__, __LINE__); + BUG(); + break; + } + + pci_write_config_byte((struct pci_dev*)dev, PCI_CACHE_LINE_SIZE, 0x14); + pci_write_config_byte((struct pci_dev*)dev, PCI_LATENCY_TIMER, 0xFF); + pci_read_config_word((struct pci_dev*)dev, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK | + PCI_COMMAND_SERR | PCI_COMMAND_WAIT | PCI_COMMAND_PARITY; + pci_write_config_word((struct pci_dev*)dev, PCI_COMMAND, cmd); + pci_write_config_byte((struct pci_dev*)dev, PCI_INTERRUPT_LINE, + dev->irq); + return irq; +} + +int __init rt288x_register_pci(void) +{ + void __iomem *io_map_base; + int i; + + rt2880_pci_base = ioremap_nocache(RT2880_PCI_BASE, PAGE_SIZE); + + io_map_base = ioremap(RT2880_PCI_IO_BASE, RT2880_PCI_IO_SIZE); + rt2880_pci_controller.io_map_base = (unsigned long) io_map_base; + set_io_port_base((unsigned long) io_map_base); + + ioport_resource.start = RT2880_PCI_IO_BASE; + ioport_resource.end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1; + + rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR); + for(i = 0; i < 0xfffff; i++) {} + + rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL); + rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR); + rt2880_pci_reg_write(RT2880_PCI_MEM_BASE, RT2880_PCI_REG_MEMBASE); + rt2880_pci_reg_write(RT2880_PCI_IO_BASE, RT2880_PCI_REG_IOBASE); + rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR); + rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID); + rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS); + rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID); + rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR); + + rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000); + (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0); + + register_pci_controller(&rt2880_pci_controller); + return 0; +} + +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} diff --git a/target/linux/ramips/files-3.7/arch/mips/pci/pci-rt3883.c b/target/linux/ramips/files-3.7/arch/mips/pci/pci-rt3883.c new file mode 100644 index 0000000000..8a4c8ce61a --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/pci/pci-rt3883.c @@ -0,0 +1,487 @@ +/* + * Ralink RT3883 SoC PCI support + * + * Copyright (C) 2011-2012 Gabor Juhos + * + * Parts of this file are based on Ralink's 2.6.21 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#define RT3883_MEMORY_BASE 0x00000000 +#define RT3883_MEMORY_SIZE 0x02000000 + +#define RT3883_PCI_MEM_BASE 0x20000000 +#define RT3883_PCI_MEM_SIZE 0x10000000 +#define RT3883_PCI_IO_BASE 0x10160000 +#define RT3883_PCI_IO_SIZE 0x00010000 + +#define RT3883_PCI_REG_PCICFG_ADDR 0x00 +#define RT3883_PCI_REG_PCIRAW_ADDR 0x04 +#define RT3883_PCI_REG_PCIINT_ADDR 0x08 +#define RT3883_PCI_REG_PCIMSK_ADDR 0x0c +#define RT3833_PCI_PCIINT_PCIE BIT(20) +#define RT3833_PCI_PCIINT_PCI1 BIT(19) +#define RT3833_PCI_PCIINT_PCI0 BIT(18) + +#define RT3883_PCI_REG_CONFIG_ADDR 0x20 +#define RT3883_PCI_REG_CONFIG_DATA 0x24 +#define RT3883_PCI_REG_MEMBASE 0x28 +#define RT3883_PCI_REG_IOBASE 0x2c +#define RT3883_PCI_REG_ARBCTL 0x80 + +#define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000) +#define RT3883_PCI_REG_BAR0SETUP_ADDR(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10) +#define RT3883_PCI_REG_IMBASEBAR0_ADDR(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18) +#define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30) +#define RT3883_PCI_REG_CLASS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x34) +#define RT3883_PCI_REG_SUBID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x38) +#define RT3883_PCI_REG_STATUS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x50) + +static int (*rt3883_pci_plat_dev_init)(struct pci_dev *dev); +static void __iomem *rt3883_pci_base; +static DEFINE_SPINLOCK(rt3883_pci_lock); + +static inline u32 rt3883_pci_rr(unsigned reg) +{ + return readl(rt3883_pci_base + reg); +} + +static inline void rt3883_pci_wr(u32 val, unsigned reg) +{ + writel(val, rt3883_pci_base + reg); +} + +static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot, + unsigned int func, unsigned int where) +{ + return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | + 0x80000000); +} + +static u32 rt3883_pci_read_u32(unsigned bus, unsigned slot, + unsigned func, unsigned reg) +{ + unsigned long flags; + u32 address; + u32 ret; + + address = rt3883_pci_get_cfgaddr(bus, slot, func, reg); + + spin_lock_irqsave(&rt3883_pci_lock, flags); + rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR); + ret = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA); + spin_unlock_irqrestore(&rt3883_pci_lock, flags); + + return ret; +} + +static void rt3883_pci_write_u32(unsigned bus, unsigned slot, + unsigned func, unsigned reg, u32 val) +{ + unsigned long flags; + u32 address; + + address = rt3883_pci_get_cfgaddr(bus, slot, func, reg); + + spin_lock_irqsave(&rt3883_pci_lock, flags); + rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR); + rt3883_pci_wr(val, RT3883_PCI_REG_CONFIG_DATA); + spin_unlock_irqrestore(&rt3883_pci_lock, flags); +} + +static void rt3883_pci_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + u32 pending; + + pending = rt3883_pci_rr(RT3883_PCI_REG_PCIINT_ADDR) & + rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR); + + if (!pending) { + spurious_interrupt(); + return; + } + + if (pending & RT3833_PCI_PCIINT_PCI0) + generic_handle_irq(RT3883_PCI_IRQ_PCI0); + + if (pending & RT3833_PCI_PCIINT_PCI1) + generic_handle_irq(RT3883_PCI_IRQ_PCI1); + + if (pending & RT3833_PCI_PCIINT_PCIE) + generic_handle_irq(RT3883_PCI_IRQ_PCIE); +} + +static void rt3883_pci_irq_unmask(struct irq_data *d) +{ + int irq = d->irq; + u32 mask; + u32 t; + + switch (irq) { + case RT3883_PCI_IRQ_PCI0: + mask = RT3833_PCI_PCIINT_PCI0; + break; + case RT3883_PCI_IRQ_PCI1: + mask = RT3833_PCI_PCIINT_PCI1; + break; + case RT3883_PCI_IRQ_PCIE: + mask = RT3833_PCI_PCIINT_PCIE; + break; + default: + BUG(); + } + + t = rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR); + rt3883_pci_wr(t | mask, RT3883_PCI_REG_PCIMSK_ADDR); + /* flush write */ + rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR); +} + +static void rt3883_pci_irq_mask(struct irq_data *d) +{ + int irq = d->irq; + u32 mask; + u32 t; + + switch (irq) { + case RT3883_PCI_IRQ_PCI0: + mask = RT3833_PCI_PCIINT_PCI0; + break; + case RT3883_PCI_IRQ_PCI1: + mask = RT3833_PCI_PCIINT_PCI1; + break; + case RT3883_PCI_IRQ_PCIE: + mask = RT3833_PCI_PCIINT_PCIE; + break; + default: + BUG(); + } + + t = rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR); + rt3883_pci_wr(t & ~mask, RT3883_PCI_REG_PCIMSK_ADDR); + /* flush write */ + rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR); +} + +static struct irq_chip rt3883_pci_irq_chip = { + .name = "RT3883 PCI", + .irq_mask = rt3883_pci_irq_mask, + .irq_unmask = rt3883_pci_irq_unmask, + .irq_mask_ack = rt3883_pci_irq_mask, +}; + +static void __init rt3883_pci_irq_init(void) +{ + int i; + + /* disable all interrupts */ + rt3883_pci_wr(0, RT3883_PCI_REG_PCIMSK_ADDR); + + for (i = RT3883_PCI_IRQ_BASE; + i < RT3883_PCI_IRQ_BASE + RT3883_PCI_IRQ_COUNT; i++) { + irq_set_chip_and_handler(i, &rt3883_pci_irq_chip, + handle_level_irq); + } + + irq_set_chained_handler(RT3883_CPU_IRQ_PCI, rt3883_pci_irq_handler); +} + +static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + unsigned long flags; + u32 address; + u32 data; + + address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), + PCI_FUNC(devfn), where); + + spin_lock_irqsave(&rt3883_pci_lock, flags); + rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR); + data = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA); + spin_unlock_irqrestore(&rt3883_pci_lock, flags); + + switch (size) { + case 1: + *val = (data >> ((where & 3) << 3)) & 0xff; + break; + case 2: + *val = (data >> ((where & 3) << 3)) & 0xffff; + break; + case 4: + *val = data; + break; + } + + return PCIBIOS_SUCCESSFUL; +} + +static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + unsigned long flags; + u32 address; + u32 data; + + address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), + PCI_FUNC(devfn), where); + + spin_lock_irqsave(&rt3883_pci_lock, flags); + rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR); + data = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA); + + switch (size) { + case 1: + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + break; + case 2: + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + break; + case 4: + data = val; + break; + } + + rt3883_pci_wr(data, RT3883_PCI_REG_CONFIG_DATA); + spin_unlock_irqrestore(&rt3883_pci_lock, flags); + + return PCIBIOS_SUCCESSFUL; +} + +static struct pci_ops rt3883_pci_ops = { + .read = rt3883_pci_config_read, + .write = rt3883_pci_config_write, +}; + +static struct resource rt3883_pci_mem_resource = { + .name = "PCI MEM space", + .start = RT3883_PCI_MEM_BASE, + .end = RT3883_PCI_MEM_BASE + RT3883_PCI_MEM_SIZE - 1, + .flags = IORESOURCE_MEM, +}; + +static struct resource rt3883_pci_io_resource = { + .name = "PCI IO space", + .start = RT3883_PCI_IO_BASE, + .end = RT3883_PCI_IO_BASE + RT3883_PCI_IO_SIZE - 1, + .flags = IORESOURCE_IO, +}; + +static struct pci_controller rt3883_pci_controller = { + .pci_ops = &rt3883_pci_ops, + .mem_resource = &rt3883_pci_mem_resource, + .io_resource = &rt3883_pci_io_resource, +}; + +static void rt3883_pci_preinit(unsigned mode) +{ + u32 syscfg1; + u32 rstctrl; + u32 clkcfg1; + + if (mode & RT3883_PCI_MODE_PCIE) { + u32 val; + + val = rt3883_sysc_rr(RT3883_SYSC_REG_SYSCFG1); + val &= ~(0x30); + val |= (2 << 4); + rt3883_sysc_wr(val, RT3883_SYSC_REG_SYSCFG1); + + val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN0); + val &= ~BIT(31); + rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN0); + + val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN1); + val &= 0x80ffffff; + rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN1); + + val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN1); + val |= 0xa << 24; + rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN1); + + val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN0); + val |= BIT(31); + rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN0); + + msleep(50); + } + + syscfg1 = rt3883_sysc_rr(RT3883_SYSC_REG_SYSCFG1); + syscfg1 &= ~(RT3883_SYSCFG1_PCIE_RC_MODE | + RT3883_SYSCFG1_PCI_HOST_MODE); + + rstctrl = rt3883_sysc_rr(RT3883_SYSC_REG_RSTCTRL); + rstctrl |= (RT3883_RSTCTRL_PCI | RT3883_RSTCTRL_PCIE); + + clkcfg1 = rt3883_sysc_rr(RT3883_SYSC_REG_CLKCFG1); + clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN | + RT3883_CLKCFG1_PCIE_CLK_EN); + + if (mode & RT3883_PCI_MODE_PCI) { + syscfg1 |= RT3883_SYSCFG1_PCI_HOST_MODE; + clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN; + rstctrl &= ~RT3883_RSTCTRL_PCI; + } + if (mode & RT3883_PCI_MODE_PCIE) { + syscfg1 |= RT3883_SYSCFG1_PCI_HOST_MODE | + RT3883_SYSCFG1_PCIE_RC_MODE; + clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN; + rstctrl &= ~RT3883_RSTCTRL_PCIE; + } + + rt3883_sysc_wr(syscfg1, RT3883_SYSC_REG_SYSCFG1); + rt3883_sysc_wr(rstctrl, RT3883_SYSC_REG_RSTCTRL); + rt3883_sysc_wr(clkcfg1, RT3883_SYSC_REG_CLKCFG1); + + msleep(500); +} + +static int rt3883_pcie_ready(void) +{ + u32 status; + + msleep(500); + + status = rt3883_pci_rr(RT3883_PCI_REG_STATUS(1)); + if (status & BIT(0)) + return 0; + + /* TODO: reset PCIe and turn off PCIe clock */ + + return -ENODEV; +} + +void __init rt3883_pci_init(unsigned mode) +{ + u32 val; + int err; + + rt3883_pci_preinit(mode); + + rt3883_pci_base = ioremap(RT3883_PCI_BASE, PAGE_SIZE); + if (rt3883_pci_base == NULL) { + pr_err("failed to ioremap PCI registers\n"); + return; + } + + rt3883_pci_wr(0, RT3883_PCI_REG_PCICFG_ADDR); + if (mode & RT3883_PCI_MODE_PCI) + rt3883_pci_wr(BIT(16), RT3883_PCI_REG_PCICFG_ADDR); + + msleep(500); + + if (mode & RT3883_PCI_MODE_PCIE) { + err = rt3883_pcie_ready(); + if (err) + return; + } + + if (mode & RT3883_PCI_MODE_PCI) + rt3883_pci_wr(0x79, RT3883_PCI_REG_ARBCTL); + + rt3883_pci_wr(RT3883_PCI_MEM_BASE, RT3883_PCI_REG_MEMBASE); + rt3883_pci_wr(RT3883_PCI_IO_BASE, RT3883_PCI_REG_IOBASE); + + /* PCI */ + rt3883_pci_wr(0x03ff0000, RT3883_PCI_REG_BAR0SETUP_ADDR(0)); + rt3883_pci_wr(RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0_ADDR(0)); + rt3883_pci_wr(0x08021814, RT3883_PCI_REG_ID(0)); + rt3883_pci_wr(0x00800001, RT3883_PCI_REG_CLASS(0)); + rt3883_pci_wr(0x28801814, RT3883_PCI_REG_SUBID(0)); + + /* PCIe */ + rt3883_pci_wr(0x01ff0000, RT3883_PCI_REG_BAR0SETUP_ADDR(1)); + rt3883_pci_wr(RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0_ADDR(1)); + rt3883_pci_wr(0x08021814, RT3883_PCI_REG_ID(1)); + rt3883_pci_wr(0x06040001, RT3883_PCI_REG_CLASS(1)); + rt3883_pci_wr(0x28801814, RT3883_PCI_REG_SUBID(1)); + + rt3883_pci_irq_init(); + + /* PCIe */ + val = rt3883_pci_read_u32(0, 0x01, 0, PCI_COMMAND); + val |= 0x7; + rt3883_pci_write_u32(0, 0x01, 0, PCI_COMMAND, val); + + /* PCI */ + val = rt3883_pci_read_u32(0, 0x00, 0, PCI_COMMAND); + val |= 0x7; + rt3883_pci_write_u32(0, 0x00, 0, PCI_COMMAND, val); + + ioport_resource.start = rt3883_pci_io_resource.start; + ioport_resource.end = rt3883_pci_io_resource.end; + + register_pci_controller(&rt3883_pci_controller); +} + +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + int irq = -1; + + switch (dev->bus->number) { + case 0: + switch (PCI_SLOT(dev->devfn)) { + case 0x00: + rt3883_pci_wr(0x03ff0001, + RT3883_PCI_REG_BAR0SETUP_ADDR(0)); + rt3883_pci_wr(0x03ff0001, + RT3883_PCI_REG_BAR0SETUP_ADDR(1)); + + rt3883_pci_write_u32(0, 0x00, 0, PCI_BASE_ADDRESS_0, + RT3883_MEMORY_BASE); + rt3883_pci_read_u32(0, 0x00, 0, PCI_BASE_ADDRESS_0); + + irq = RT3883_CPU_IRQ_PCI; + break; + case 0x01: + rt3883_pci_write_u32(0, 0x01, 0, PCI_IO_BASE, + 0x00000101); + break; + case 0x11: + irq = RT3883_PCI_IRQ_PCI0; + break; + case 0x12: + irq = RT3883_PCI_IRQ_PCI1; + break; + } + break; + + case 1: + irq = RT3883_PCI_IRQ_PCIE; + break; + + default: + dev_err(&dev->dev, "no IRQ specified\n"); + return irq; + } + + return irq; +} + +void __init rt3883_pci_set_plat_dev_init(int (*f)(struct pci_dev *dev)) +{ + rt3883_pci_plat_dev_init = f; +} + +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + if (rt3883_pci_plat_dev_init) + return rt3883_pci_plat_dev_init(dev); + + return 0; +} diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/Kconfig b/target/linux/ramips/files-3.7/arch/mips/ralink/Kconfig new file mode 100644 index 0000000000..74bca6d0e9 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/Kconfig @@ -0,0 +1,83 @@ +if MIPS_RALINK + +choice + prompt "Ralink SoC selection" + default SOC_RT288X + help + Select Ralink MIPS SoC type. + + config RALINK_RT288X + bool "RT288x" + select SOC_RT288X + + config RALINK_RT305X + bool "RT305x" + select SOC_RT305X + + config RALINK_RT3883 + bool "RT3883" + select SOC_RT3883 + +endchoice + +source "arch/mips/ralink/rt288x/Kconfig" +source "arch/mips/ralink/rt305x/Kconfig" +source "arch/mips/ralink/rt3883/Kconfig" + +config SOC_RT288X + bool + select CEVT_R4K + select CSRC_R4K + select DMA_NONCOHERENT + select IRQ_CPU + select ARCH_REQUIRE_GPIOLIB + select SYS_HAS_CPU_MIPS32_R1 + select SYS_HAS_CPU_MIPS32_R2 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_HAS_EARLY_PRINTK + select MIPS_MACHINE + select HAVE_CLK + +config SOC_RT305X + bool + select CEVT_R4K + select CSRC_R4K + select DMA_NONCOHERENT + select IRQ_CPU + select ARCH_REQUIRE_GPIOLIB + select SYS_HAS_CPU_MIPS32_R1 + select SYS_HAS_CPU_MIPS32_R2 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_HAS_EARLY_PRINTK + select MIPS_MACHINE + select USB_ARCH_HAS_HCD + select USB_ARCH_HAS_OHCI + select USB_ARCH_HAS_EHCI + select HAVE_CLK + +config SOC_RT3883 + bool + select CEVT_R4K + select CSRC_R4K + select DMA_NONCOHERENT + select IRQ_CPU + select ARCH_REQUIRE_GPIOLIB + select SYS_HAS_CPU_MIPS32_R1 + select SYS_HAS_CPU_MIPS32_R2 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_HAS_EARLY_PRINTK + select MIPS_MACHINE + select USB_ARCH_HAS_OHCI + select USB_ARCH_HAS_EHCI + select HAVE_CLK + +config RALINK_DEV_GPIO_BUTTONS + def_bool n + +config RALINK_DEV_GPIO_LEDS + def_bool n + +endif diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/Platform b/target/linux/ramips/files-3.7/arch/mips/ralink/Platform new file mode 100644 index 0000000000..1b540492c2 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/Platform @@ -0,0 +1,26 @@ +# +# Ralink SoC common stuff +# +core-$(CONFIG_MIPS_RALINK) += arch/mips/ralink/common/ +cflags-$(CONFIG_MIPS_RALINK) += -I$(srctree)/arch/mips/include/asm/mach-ralink + +# +# Ralink RT288x +# +core-$(CONFIG_RALINK_RT288X) += arch/mips/ralink/rt288x/ +cflags-$(CONFIG_RALINK_RT288X) += -I$(srctree)//arch/mips/include/asm/mach-ralink/rt288x +load-$(CONFIG_RALINK_RT288X) += 0xffffffff88000000 + +# +# Ralink RT305x +# +core-$(CONFIG_RALINK_RT305X) += arch/mips/ralink/rt305x/ +cflags-$(CONFIG_RALINK_RT305X) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt305x +load-$(CONFIG_RALINK_RT305X) += 0xffffffff80000000 + +# +# Ralink RT3883 +# +core-$(CONFIG_RALINK_RT3883) += arch/mips/ralink/rt3883/ +cflags-$(CONFIG_RALINK_RT3883) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt3883 +load-$(CONFIG_RALINK_RT3883) += 0xffffffff80000000 diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/common/Makefile b/target/linux/ramips/files-3.7/arch/mips/ralink/common/Makefile new file mode 100644 index 0000000000..adab85f689 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/common/Makefile @@ -0,0 +1,13 @@ +# +# Makefile for the Ralink common stuff +# +# Copyright (C) 2009-2010 Gabor Juhos +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License version 2 as published +# by the Free Software Foundation. + +obj-y := prom.o setup.o intc.o gpio.o + +obj-$(CONFIG_RALINK_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o +obj-$(CONFIG_RALINK_DEV_GPIO_LEDS) += dev-gpio-leds.o diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/common/dev-gpio-buttons.c b/target/linux/ramips/files-3.7/arch/mips/ralink/common/dev-gpio-buttons.c new file mode 100644 index 0000000000..75a2a17143 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/common/dev-gpio-buttons.c @@ -0,0 +1,57 @@ +/* + * Ralink SoC GPIO button support + * + * Copyright (C) 2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "linux/init.h" +#include +#include + +#include + +void __init ramips_register_gpio_buttons(int id, + unsigned poll_interval, + unsigned nbuttons, + struct gpio_keys_button *buttons) +{ + struct platform_device *pdev; + struct gpio_keys_platform_data pdata; + struct gpio_keys_button *p; + int err; + + p = kmalloc(nbuttons * sizeof(*p), GFP_KERNEL); + if (!p) + return; + + memcpy(p, buttons, nbuttons * sizeof(*p)); + + pdev = platform_device_alloc("gpio-keys-polled", id); + if (!pdev) + goto err_free_buttons; + + memset(&pdata, 0, sizeof(pdata)); + pdata.poll_interval = poll_interval; + pdata.nbuttons = nbuttons; + pdata.buttons = p; + + err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); + if (err) + goto err_put_pdev; + + err = platform_device_add(pdev); + if (err) + goto err_put_pdev; + + return; + +err_put_pdev: + platform_device_put(pdev); + +err_free_buttons: + kfree(p); +} diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/common/dev-gpio-leds.c b/target/linux/ramips/files-3.7/arch/mips/ralink/common/dev-gpio-leds.c new file mode 100644 index 0000000000..a45a7cb779 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/common/dev-gpio-leds.c @@ -0,0 +1,54 @@ +/* + * Ralink SoC GPIO LED device support + * + * Copyright (C) 2009 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include + +void __init ramips_register_gpio_leds(int id, unsigned num_leds, + struct gpio_led *leds) +{ + struct platform_device *pdev; + struct gpio_led_platform_data pdata; + struct gpio_led *p; + int err; + + p = kmalloc(num_leds * sizeof(*p), GFP_KERNEL); + if (!p) + return; + + memcpy(p, leds, num_leds * sizeof(*p)); + + pdev = platform_device_alloc("leds-gpio", id); + if (!pdev) + goto err_free_leds; + + memset(&pdata, 0, sizeof(pdata)); + pdata.num_leds = num_leds; + pdata.leds = p; + + err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); + if (err) + goto err_put_pdev; + + err = platform_device_add(pdev); + if (err) + goto err_put_pdev; + + return; + +err_put_pdev: + platform_device_put(pdev); + +err_free_leds: + kfree(p); +} diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/common/gpio.c b/target/linux/ramips/files-3.7/arch/mips/ralink/common/gpio.c new file mode 100644 index 0000000000..f03d145b6d --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/common/gpio.c @@ -0,0 +1,113 @@ +/* + * Ralink SoC specific GPIO support + * + * Copyright (C) 2009-2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include + +static inline struct ramips_gpio_chip *to_ramips_gpio(struct gpio_chip *chip) +{ + struct ramips_gpio_chip *rg; + + rg = container_of(chip, struct ramips_gpio_chip, chip); + return rg; +} + +static inline void ramips_gpio_wr(struct ramips_gpio_chip *rg, u8 reg, u32 val) +{ + __raw_writel(val, rg->regs_base + rg->regs[reg]); +} + +static inline u32 ramips_gpio_rr(struct ramips_gpio_chip *rg, u8 reg) +{ + return __raw_readl(rg->regs_base + rg->regs[reg]); +} + +static int ramips_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + struct ramips_gpio_chip *rg = to_ramips_gpio(chip); + unsigned long flags; + u32 t; + + spin_lock_irqsave(&rg->lock, flags); + t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DIR); + t &= ~(1 << offset); + ramips_gpio_wr(rg, RAMIPS_GPIO_REG_DIR, t); + spin_unlock_irqrestore(&rg->lock, flags); + + return 0; +} + +static int ramips_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct ramips_gpio_chip *rg = to_ramips_gpio(chip); + unsigned long flags; + u32 reg; + u32 t; + + reg = (value) ? RAMIPS_GPIO_REG_SET : RAMIPS_GPIO_REG_RESET; + + spin_lock_irqsave(&rg->lock, flags); + ramips_gpio_wr(rg, reg, 1 << offset); + + t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DIR); + t |= 1 << offset; + ramips_gpio_wr(rg, RAMIPS_GPIO_REG_DIR, t); + spin_unlock_irqrestore(&rg->lock, flags); + + return 0; +} + +static void ramips_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct ramips_gpio_chip *rg = to_ramips_gpio(chip); + u32 reg; + + reg = (value) ? RAMIPS_GPIO_REG_SET : RAMIPS_GPIO_REG_RESET; + ramips_gpio_wr(rg, reg, 1 << offset); +} + +static int ramips_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct ramips_gpio_chip *rg = to_ramips_gpio(chip); + u32 t; + + t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DATA); + return !!(t & (1 << offset)); +} + +static __init void ramips_gpio_chip_add(struct ramips_gpio_chip *rg) +{ + spin_lock_init(&rg->lock); + + rg->regs_base = ioremap(rg->map_base, rg->map_size); + + rg->chip.direction_input = ramips_gpio_direction_input; + rg->chip.direction_output = ramips_gpio_direction_output; + rg->chip.get = ramips_gpio_get; + rg->chip.set = ramips_gpio_set; + + /* set polarity to low for all lines */ + ramips_gpio_wr(rg, RAMIPS_GPIO_REG_POL, 0); + + gpiochip_add(&rg->chip); +} + +__init int ramips_gpio_init(struct ramips_gpio_data *data) +{ + int i; + + for (i = 0; i < data->num_chips; i++) + ramips_gpio_chip_add(&data->chips[i]); + + return 0; +} diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/common/intc.c b/target/linux/ramips/files-3.7/arch/mips/ralink/common/intc.c new file mode 100644 index 0000000000..65e42b423b --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/common/intc.c @@ -0,0 +1,99 @@ +/* + * Ralink SoC Interrupt controller routines + * + * Copyright (C) 2009 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +/* INTC register offsets */ +#define INTC_REG_STATUS0 0x00 +#define INTC_REG_STATUS1 0x04 +#define INTC_REG_TYPE 0x20 +#define INTC_REG_RAW_STATUS 0x30 +#define INTC_REG_ENABLE 0x34 +#define INTC_REG_DISABLE 0x38 + +#define INTC_INT_GLOBAL BIT(31) +#define INTC_IRQ_COUNT 32 + +static unsigned int ramips_intc_irq_base; +static void __iomem *ramips_intc_base; + +static inline void ramips_intc_wr(u32 val, unsigned reg) +{ + __raw_writel(val, ramips_intc_base + reg); +} + +static inline u32 ramips_intc_rr(unsigned reg) +{ + return __raw_readl(ramips_intc_base + reg); +} + +static void ramips_intc_irq_unmask(struct irq_data *d) +{ + unsigned int irq = d->irq - ramips_intc_irq_base; + + ramips_intc_wr((1 << irq), INTC_REG_ENABLE); +} + +static void ramips_intc_irq_mask(struct irq_data *d) +{ + unsigned int irq = d->irq - ramips_intc_irq_base; + + ramips_intc_wr((1 << irq), INTC_REG_DISABLE); +} + +static struct irq_chip ramips_intc_irq_chip = { + .name = "INTC", + .irq_unmask = ramips_intc_irq_unmask, + .irq_mask = ramips_intc_irq_mask, + .irq_mask_ack = ramips_intc_irq_mask, +}; + +static struct irqaction ramips_intc_irqaction = { + .handler = no_action, + .name = "cascade [INTC]", +}; + +void __init ramips_intc_irq_init(unsigned intc_base, unsigned irq, + unsigned irq_base) +{ + int i; + + ramips_intc_base = ioremap_nocache(intc_base, PAGE_SIZE); + ramips_intc_irq_base = irq_base; + + /* disable all interrupts */ + ramips_intc_wr(~0, INTC_REG_DISABLE); + + /* route all INTC interrupts to MIPS HW0 interrupt */ + ramips_intc_wr(0, INTC_REG_TYPE); + + for (i = ramips_intc_irq_base; + i < ramips_intc_irq_base + INTC_IRQ_COUNT; i++) + irq_set_chip_and_handler(i, &ramips_intc_irq_chip, + handle_level_irq); + + setup_irq(irq, &ramips_intc_irqaction); + ramips_intc_wr(INTC_INT_GLOBAL, INTC_REG_ENABLE); +} + +u32 ramips_intc_get_status(void) +{ + return ramips_intc_rr(INTC_REG_STATUS0); +} diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/common/prom.c b/target/linux/ramips/files-3.7/arch/mips/ralink/common/prom.c new file mode 100644 index 0000000000..26169d366d --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/common/prom.c @@ -0,0 +1,168 @@ +/* + * Ralink SoC specific prom routines + * + * Copyright (C) 2010 Joonas Lahtinen + * Copyright (C) 2009 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include + +#include +#include + +unsigned long ramips_mem_base; +unsigned long ramips_mem_size_min; +unsigned long ramips_mem_size_max; + +static inline void *to_ram_addr(void *addr) +{ + u32 base; + + base = KSEG0ADDR(ramips_mem_base); + if (((u32) addr > base) && + ((u32) addr < (base + ramips_mem_size_max))) + return addr; + + base = KSEG1ADDR(ramips_mem_base); + if (((u32) addr > base) && + ((u32) addr < (base + ramips_mem_size_max))) + return addr; + + /* some U-Boot variants uses physical addresses */ + base = ramips_mem_base; + if (((u32) addr > base) && + ((u32) addr < (base + ramips_mem_size_max))) + return (void *)KSEG0ADDR(addr); + + return NULL; +} + +static char ramips_cmdline_buf[COMMAND_LINE_SIZE] __initdata; +static void __init prom_append_cmdline(const char *name, + const char *value) +{ + snprintf(ramips_cmdline_buf, sizeof(ramips_cmdline_buf), + " %s=%s", name, value); + strlcat(arcs_cmdline, ramips_cmdline_buf, sizeof(arcs_cmdline)); +} + +#ifdef CONFIG_IMAGE_CMDLINE_HACK +extern char __image_cmdline[]; + +static int __init use_image_cmdline(void) +{ + char *p = __image_cmdline; + int replace = 0; + + if (*p == '-') { + replace = 1; + p++; + } + + if (*p == '\0') + return 0; + + if (replace) { + strlcpy(arcs_cmdline, p, sizeof(arcs_cmdline)); + } else { + strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); + strlcat(arcs_cmdline, p, sizeof(arcs_cmdline)); + } + + return 1; +} +#else +static int inline use_image_cmdline(void) { return 0; } +#endif + +static __init void prom_init_cmdline(int argc, char **argv) +{ + int i; + + if (use_image_cmdline()) + return; + + if (!argv) { + printk(KERN_DEBUG "argv=%p is invalid, skipping\n", + argv); + return; + } + + for (i = 0; i < argc; i++) { + char *p = to_ram_addr(argv[i]); + + if (!p) { + printk(KERN_DEBUG + "argv[%d]=%p is invalid, skipping\n", + i, argv[i]); + continue; + } + + printk(KERN_DEBUG "argv[%d]: %s\n", i, p); + strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); + strlcat(arcs_cmdline, p, sizeof(arcs_cmdline)); + } +} + +static __init char *prom_append_env(char **env, const char *envname) +{ +#define PROM_MAX_ENVS 256 + int len = strlen(envname); + int i; + + if (!env) { + printk(KERN_DEBUG "env=%p is not in RAM, skipping\n", + env); + return NULL; + } + + for (i = 0; i < PROM_MAX_ENVS; i++) { + char *p = to_ram_addr(env[i]); + + if (!p) + break; + + printk(KERN_DEBUG "env[%d]: %s\n", i, p); + if (strncmp(envname, p, len) == 0 && p[len] == '=') + prom_append_cmdline(envname, p + len + 1); + } + + return NULL; +#undef PROM_MAX_ENVS +} + +void __init prom_init(void) +{ + int argc; + char **envp; + char **argv; + + ramips_soc_prom_init(); + + printk(KERN_DEBUG + "prom: fw_arg0=%08x, fw_arg1=%08x, fw_arg2=%08x, fw_arg3=%08x\n", + (unsigned int)fw_arg0, (unsigned int)fw_arg1, + (unsigned int)fw_arg2, (unsigned int)fw_arg3); + + argc = fw_arg0; + argv = to_ram_addr((void *)fw_arg1); + prom_init_cmdline(argc, argv); + + envp = to_ram_addr((void *)fw_arg2); + prom_append_env(envp, "board"); + prom_append_env(envp, "ethaddr"); +} + +void __init prom_free_prom_memory(void) +{ + /* We do not have to prom memory to free */ +} diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/common/setup.c b/target/linux/ramips/files-3.7/arch/mips/ralink/common/setup.c new file mode 100644 index 0000000000..1af855e649 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/common/setup.c @@ -0,0 +1,98 @@ +/* + * Ralink SoC common setup + * + * Copyright (C) 2008-2009 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include + +#include +#include + +unsigned char ramips_sys_type[RAMIPS_SYS_TYPE_LEN]; +unsigned long (*ramips_get_mem_size)(void); + +const char *get_system_type(void) +{ + return ramips_sys_type; +} + +static void __init detect_mem_size(void) +{ + unsigned long size; + + if (ramips_get_mem_size) { + size = ramips_get_mem_size(); + } else { + void *base; + + base = (void *) KSEG1ADDR(detect_mem_size); + for (size = ramips_mem_size_min; size < ramips_mem_size_max; + size <<= 1 ) { + if (!memcmp(base, base + size, 1024)) + break; + } + } + + add_memory_region(ramips_mem_base, size, BOOT_MEM_RAM); +} + +void __init ramips_early_serial_setup(int line, unsigned base, unsigned freq, + unsigned irq) +{ + struct uart_port p; + int err; + + memset(&p, 0, sizeof(p)); + p.flags = UPF_SKIP_TEST | UPF_FIXED_TYPE; + p.iotype = UPIO_AU; + p.uartclk = freq; + p.regshift = 2; + p.type = PORT_16550A; + + p.mapbase = base; + p.membase = ioremap_nocache(p.mapbase, PAGE_SIZE); + p.line = line; + p.irq = irq; + + err = early_serial_setup(&p); + if (err) + printk(KERN_ERR "early serial%d registration failed %d\n", + line, err); +} + +void __init plat_mem_setup(void) +{ + set_io_port_base(KSEG1); + + detect_mem_size(); + ramips_soc_setup(); +} + +__setup("board=", mips_machtype_setup); + +static int __init ramips_machine_setup(void) +{ + mips_machine_setup(); + return 0; +} + +arch_initcall(ramips_machine_setup); + +static void __init ramips_generic_init(void) +{ +} + +MIPS_MACHINE(RAMIPS_MACH_GENERIC, "Generic", "Generic Ralink board", + ramips_generic_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/Kconfig b/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/Kconfig new file mode 100644 index 0000000000..739561c640 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/Kconfig @@ -0,0 +1,36 @@ +if RALINK_RT288X + +menu "Ralink RT288x machine selection" + +config RT288X_MACH_F5D8235_V1 + bool "Belkin F5D8235 V1 board support" + select RALINK_DEV_GPIO_LEDS + +config RT288X_MACH_BR6524N + bool "Edimax BR6524N support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT288X_MACH_RT_N15 + bool "Asus RT-N15 board support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT288X_MACH_V11ST_FE + bool "Ralink V11ST-FE board support" + select HW_HAS_PCI + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT288X_MACH_WLI_TX4_AG300N + bool "Buffalo WLI-TX4-AG300N board support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT288X_MACH_WZR_AGL300NH + bool "Buffalo WZR-AGL300NH board support" + select RALINK_DEV_GPIO_LEDS + +endmenu + +endif diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/Makefile b/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/Makefile new file mode 100644 index 0000000000..eb60c5d10d --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/Makefile @@ -0,0 +1,21 @@ +# +# Makefile for the Ralink RT288x SoC specific parts of the kernel +# +# Copyright (C) 2010 Joonas Lahtinen +# Copyright (C) 2008-2009 Gabor Juhos +# Copyright (C) 2008 Imre Kaloz +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License version 2 as published +# by the Free Software Foundation. + +obj-y := irq.o setup.o rt288x.o devices.o clock.o + +obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + +obj-$(CONFIG_RT288X_MACH_F5D8235_V1) += mach-f5d8235-v1.o +obj-$(CONFIG_RT288X_MACH_BR6524N) += mach-br6524n.o +obj-$(CONFIG_RT288X_MACH_RT_N15) += mach-rt-n15.o +obj-$(CONFIG_RT288X_MACH_V11ST_FE) += mach-v11st-fe.o +obj-$(CONFIG_RT288X_MACH_WLI_TX4_AG300N) += mach-wli-tx4-ag300n.o +obj-$(CONFIG_RT288X_MACH_WZR_AGL300NH) += mach-wzr-agl300nh.o diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/clock.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/clock.c new file mode 100644 index 0000000000..36d754dbf6 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/clock.c @@ -0,0 +1,99 @@ +/* + * Ralink RT288X clock API + * + * Copyright (C) 2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include "common.h" + +struct clk { + unsigned long rate; +}; + +static struct clk rt288x_cpu_clk; +static struct clk rt288x_sys_clk; +static struct clk rt288x_wdt_clk; +static struct clk rt288x_uart_clk; + +void __init rt288x_clocks_init(void) +{ + u32 t; + + t = rt288x_sysc_rr(SYSC_REG_SYSTEM_CONFIG); + t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK); + + switch (t) { + case SYSTEM_CONFIG_CPUCLK_250: + rt288x_cpu_clk.rate = 250000000; + break; + case SYSTEM_CONFIG_CPUCLK_266: + rt288x_cpu_clk.rate = 266666667; + break; + case SYSTEM_CONFIG_CPUCLK_280: + rt288x_cpu_clk.rate = 280000000; + break; + case SYSTEM_CONFIG_CPUCLK_300: + rt288x_cpu_clk.rate = 300000000; + break; + } + + rt288x_sys_clk.rate = rt288x_cpu_clk.rate / 2; + rt288x_uart_clk.rate = rt288x_sys_clk.rate; + rt288x_wdt_clk.rate = rt288x_sys_clk.rate; +} + +/* + * Linux clock API + */ +struct clk *clk_get(struct device *dev, const char *id) +{ + if (!strcmp(id, "sys")) + return &rt288x_sys_clk; + + if (!strcmp(id, "cpu")) + return &rt288x_cpu_clk; + + if (!strcmp(id, "wdt")) + return &rt288x_wdt_clk; + + if (!strcmp(id, "uart")) + return &rt288x_uart_clk; + + return ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL(clk_get); + +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + return clk->rate; +} +EXPORT_SYMBOL(clk_get_rate); + +void clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_put); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/common.h b/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/common.h new file mode 100644 index 0000000000..f2415c58ba --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/common.h @@ -0,0 +1,16 @@ +/* + * Ralink RT288X SoC common defines + * + * Copyright (C) 2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _RT288X_COMMON_H +#define _RT288X_COMMON_H + +void rt288x_clocks_init(void); + +#endif /* _RT288X_COMMON_H */ \ No newline at end of file diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/devices.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/devices.c new file mode 100644 index 0000000000..196810a30f --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/devices.c @@ -0,0 +1,211 @@ +/* + * Ralink RT288x SoC platform device registration + * + * Copyright (C) 2008-2011 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +#include "devices.h" + +static struct resource rt288x_flash0_resources[] = { + { + .flags = IORESOURCE_MEM, + .start = KSEG1ADDR(RT2880_FLASH0_BASE), + .end = KSEG1ADDR(RT2880_FLASH0_BASE) + + RT2880_FLASH0_SIZE - 1, + }, +}; + +struct physmap_flash_data rt288x_flash0_data; +static struct platform_device rt288x_flash0_device = { + .name = "physmap-flash", + .resource = rt288x_flash0_resources, + .num_resources = ARRAY_SIZE(rt288x_flash0_resources), + .dev = { + .platform_data = &rt288x_flash0_data, + }, +}; + +static struct resource rt288x_flash1_resources[] = { + { + .flags = IORESOURCE_MEM, + .start = KSEG1ADDR(RT2880_FLASH1_BASE), + .end = KSEG1ADDR(RT2880_FLASH1_BASE) + + RT2880_FLASH1_SIZE - 1, + }, +}; + +struct physmap_flash_data rt288x_flash1_data; +static struct platform_device rt288x_flash1_device = { + .name = "physmap-flash", + .resource = rt288x_flash1_resources, + .num_resources = ARRAY_SIZE(rt288x_flash1_resources), + .dev = { + .platform_data = &rt288x_flash1_data, + }, +}; + +static int rt288x_flash_instance __initdata; +void __init rt288x_register_flash(unsigned int id) +{ + struct platform_device *pdev; + struct physmap_flash_data *pdata; + u32 t; + int reg; + + switch (id) { + case 0: + pdev = &rt288x_flash0_device; + reg = MEMC_REG_FLASH_CFG0; + break; + case 1: + pdev = &rt288x_flash1_device; + reg = MEMC_REG_FLASH_CFG1; + break; + default: + return; + } + + t = rt288x_memc_rr(reg); + t = (t >> FLASH_CFG_WIDTH_SHIFT) & FLASH_CFG_WIDTH_MASK; + + pdata = pdev->dev.platform_data; + switch (t) { + case FLASH_CFG_WIDTH_8BIT: + pdata->width = 1; + break; + case FLASH_CFG_WIDTH_16BIT: + pdata->width = 2; + break; + case FLASH_CFG_WIDTH_32BIT: + pdata->width = 4; + break; + default: + printk(KERN_ERR "RT288x: flash bank%u witdh is invalid\n", id); + return; + } + + pdev->id = rt288x_flash_instance; + + platform_device_register(pdev); + rt288x_flash_instance++; +} + +static struct resource rt288x_wifi_resources[] = { + { + .start = RT2880_WMAC_BASE, + .end = RT2880_WMAC_BASE + 0x3FFFF, + .flags = IORESOURCE_MEM, + }, { + .start = RT288X_CPU_IRQ_WNIC, + .end = RT288X_CPU_IRQ_WNIC, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct rt2x00_platform_data rt288x_wifi_data; +static struct platform_device rt288x_wifi_device = { + .name = "rt2800_wmac", + .resource = rt288x_wifi_resources, + .num_resources = ARRAY_SIZE(rt288x_wifi_resources), + .dev = { + .platform_data = &rt288x_wifi_data, + } +}; + +void __init rt288x_register_wifi(void) +{ + rt288x_wifi_data.eeprom_file_name = "soc_wmac.eeprom"; + platform_device_register(&rt288x_wifi_device); +} + +static void rt288x_fe_reset(void) +{ + rt288x_sysc_wr(RT2880_RESET_FE, SYSC_REG_RESET_CTRL); +} + +static struct resource rt288x_eth_resources[] = { + { + .start = RT2880_FE_BASE, + .end = RT2880_FE_BASE + PAGE_SIZE - 1, + .flags = IORESOURCE_MEM, + }, { + .start = RT288X_CPU_IRQ_FE, + .end = RT288X_CPU_IRQ_FE, + .flags = IORESOURCE_IRQ, + }, +}; + +struct ramips_eth_platform_data rt288x_eth_data; +static struct platform_device rt288x_eth_device = { + .name = "ramips_eth", + .resource = rt288x_eth_resources, + .num_resources = ARRAY_SIZE(rt288x_eth_resources), + .dev = { + .platform_data = &rt288x_eth_data, + } +}; + +void __init rt288x_register_ethernet(void) +{ + struct clk *clk; + + clk = clk_get(NULL, "sys"); + if (IS_ERR(clk)) + panic("unable to get SYS clock, err=%ld", PTR_ERR(clk)); + + rt288x_eth_data.sys_freq = clk_get_rate(clk); + rt288x_eth_data.reset_fe = rt288x_fe_reset; + rt288x_eth_data.min_pkt_len = 64; + + if (!is_valid_ether_addr(rt288x_eth_data.mac)) + random_ether_addr(rt288x_eth_data.mac); + + platform_device_register(&rt288x_eth_device); +} + +static struct resource rt288x_wdt_resources[] = { + { + .start = RT2880_TIMER_BASE, + .end = RT2880_TIMER_BASE + RT2880_TIMER_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device rt288x_wdt_device = { + .name = "ramips-wdt", + .id = -1, + .resource = rt288x_wdt_resources, + .num_resources = ARRAY_SIZE(rt288x_wdt_resources), +}; + +void __init rt288x_register_wdt(void) +{ + u32 t; + + /* enable WDT reset output on pin SRAM_CS_N */ + t = rt288x_sysc_rr(SYSC_REG_CLKCFG); + t |= CLKCFG_SRAM_CS_N_WDT; + rt288x_sysc_wr(t, SYSC_REG_CLKCFG); + + platform_device_register(&rt288x_wdt_device); +} diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/devices.h b/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/devices.h new file mode 100644 index 0000000000..d097e5d90e --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/devices.h @@ -0,0 +1,28 @@ +/* + * Ralink RT288x SoC specific platform definitions + * + * Copyright (C) 2008-2011 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_RT288X_PLATFORM_H +#define __ASM_MACH_RT288X_PLATFORM_H + +struct physmap_flash_data; + +extern struct physmap_flash_data rt288x_flash0_data; +extern struct physmap_flash_data rt288x_flash1_data; +void rt288x_register_flash(unsigned int id); + +void rt288x_register_wifi(void); + +extern struct ramips_eth_platform_data rt288x_eth_data; +void rt288x_register_ethernet(void); + +void rt288x_register_wdt(void); + +#endif /* __ASM_MACH_RT288X_PLATFORM_H */ diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/early_printk.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/early_printk.c new file mode 100644 index 0000000000..9fd7adb543 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/early_printk.c @@ -0,0 +1,30 @@ +/* + * Ralink RT288x SoC early printk support + * + * Copyright (C) 2009 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include + +#include + +#define UART_READ(r) \ + __raw_readl((void __iomem *)(KSEG1ADDR(RT2880_UART1_BASE) + 4 * (r))) + +#define UART_WRITE(r, v) \ + __raw_writel((v), (void __iomem *)(KSEG1ADDR(RT2880_UART1_BASE) + 4 * (r))) + +void prom_putchar(unsigned char ch) +{ + while (((UART_READ(UART_REG_LSR)) & UART_LSR_THRE) == 0); + UART_WRITE(UART_REG_TX, ch); + while (((UART_READ(UART_REG_LSR)) & UART_LSR_THRE) == 0); +} diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/irq.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/irq.c new file mode 100644 index 0000000000..5465a4560d --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/irq.c @@ -0,0 +1,81 @@ +/* + * Ralink RT288x SoC specific interrupt handling + * + * Copyright (C) 2008-2009 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +static void rt288x_intc_irq_dispatch(void) +{ + u32 pending; + + pending = ramips_intc_get_status(); + + if (pending & RT2880_INTC_INT_TIMER0) + do_IRQ(RT2880_INTC_IRQ_TIMER0); + + else if (pending & RT2880_INTC_INT_TIMER1) + do_IRQ(RT2880_INTC_IRQ_TIMER1); + + else if (pending & RT2880_INTC_INT_UART0) + do_IRQ(RT2880_INTC_IRQ_UART0); + + else if (pending & RT2880_INTC_INT_PCM) + do_IRQ(RT2880_INTC_IRQ_PCM); + + else if (pending & RT2880_INTC_INT_UART1) + do_IRQ(RT2880_INTC_IRQ_UART1); + + /* TODO: handle PIO interrupts as well */ + + else + spurious_interrupt(); +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned long pending; + + pending = read_c0_status() & read_c0_cause() & ST0_IM; + + if (pending & STATUSF_IP7) + do_IRQ(RT288X_CPU_IRQ_COUNTER); + + else if (pending & STATUSF_IP4) + do_IRQ(RT288X_CPU_IRQ_PCI); + + else if (pending & STATUSF_IP5) + do_IRQ(RT288X_CPU_IRQ_FE); + + else if (pending & STATUSF_IP6) + do_IRQ(RT288X_CPU_IRQ_WNIC); + + else if (pending & STATUSF_IP2) + rt288x_intc_irq_dispatch(); + + else + spurious_interrupt(); +} + +void __init arch_init_irq(void) +{ + mips_cpu_irq_init(); + ramips_intc_irq_init(RT2880_INTC_BASE, RT288X_CPU_IRQ_INTC, + RT288X_INTC_IRQ_BASE); +} diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/mach-br6524n.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/mach-br6524n.c new file mode 100644 index 0000000000..ff4746cda5 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/mach-br6524n.c @@ -0,0 +1,74 @@ +/* + * Edimax BR6524N board support + * + * Copyright (C) 2012 Florian Fainelli + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "devices.h" + +#define BR6524N_GPIO_STATUS_LED 12 +#define BR6524N_GPIO_BUTTON_WPS 0 + +#define BR6524N_KEYS_POLL_INTERVAL 20 +#define BR6524N_KEYS_DEBOUNCE_INTERVAL (3 * BR6524N_KEYS_POLL_INTERVAL) + +static struct gpio_led br6524n_leds_gpio[] __initdata = { + { + .name = "br6524n:green:status", + .gpio = BR6524N_GPIO_STATUS_LED, + .active_low = 1, + } +}; + +static struct gpio_keys_button br6524n_gpio_buttons[] __initdata = { + { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = BR6524N_KEYS_DEBOUNCE_INTERVAL, + .gpio = BR6524N_GPIO_BUTTON_WPS, + } +}; + +static void __init br6524n_fe_init(void) +{ + rt288x_gpio_init(RT2880_GPIO_MODE_UART0); + + rt288x_register_flash(0); + + ramips_register_gpio_leds(-1, ARRAY_SIZE(br6524n_leds_gpio), + br6524n_leds_gpio); + + ramips_register_gpio_buttons(-1, BR6524N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(br6524n_gpio_buttons), + br6524n_gpio_buttons); + + rt288x_register_wifi(); + + /* Board is connected to an IC+ IP175C Fast Ethernet switch */ + rt288x_eth_data.speed = SPEED_100; + rt288x_eth_data.duplex = DUPLEX_FULL; + rt288x_eth_data.tx_fc = 1; + rt288x_eth_data.rx_fc = 1; + rt288x_eth_data.phy_mask = BIT(0); + rt288x_register_ethernet(); + + rt288x_register_wdt(); +} + +MIPS_MACHINE(RAMIPS_MACH_BR6524N, "BR6524N", "Edimax BR6524N", br6524n_fe_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/mach-f5d8235-v1.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/mach-f5d8235-v1.c new file mode 100644 index 0000000000..7679572bb5 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/mach-f5d8235-v1.c @@ -0,0 +1,106 @@ +/* + * Belkin F5D825 V1 board support + * + * Copyright (C) 2011 Cezary Jackiewicz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#include +#include + +#include + +#define F5D8235_GPIO_RTL8366_SCK 2 +#define F5D8235_GPIO_RTL8366_SDA 1 + +#define F5D8235_GPIO_LED_USB_BLUE 7 +#define F5D8235_GPIO_LED_USB_ORANGE 8 +#define F5D8235_GPIO_BUTTON_WPS 0 +#define F5D8235_GPIO_BUTTON_RESET 9 + +#define F5D8235_KEYS_POLL_INTERVAL 20 +#define F5D8235_KEYS_DEBOUNCE_INTERVAL (3 * F5D8235_KEYS_POLL_INTERVAL) + +static struct rtl8366_platform_data f5d8235_rtl8366s_data = { + .gpio_sda = F5D8235_GPIO_RTL8366_SDA, + .gpio_sck = F5D8235_GPIO_RTL8366_SCK, +}; + +static struct platform_device f5d8235_rtl8366s_device = { + .name = RTL8366S_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &f5d8235_rtl8366s_data, + } +}; + +static struct gpio_led f5d8235_leds_gpio[] __initdata = { + { + .name = "f5d8235-v1:blue:storage", + .gpio = F5D8235_GPIO_LED_USB_BLUE, + .active_low = 1, + },{ + .name = "f5d8235-v1:orange:storage", + .gpio = F5D8235_GPIO_LED_USB_ORANGE, + .active_low = 1, + } +}; + +static struct gpio_keys_button f5d8235_gpio_buttons[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = F5D8235_KEYS_DEBOUNCE_INTERVAL, + .gpio = F5D8235_GPIO_BUTTON_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = F5D8235_KEYS_DEBOUNCE_INTERVAL, + .gpio = F5D8235_GPIO_BUTTON_WPS, + .active_low = 1, + } +}; + +static void __init f5d8235_init(void) +{ + rt288x_gpio_init(RT2880_GPIO_MODE_UART0 | RT2880_GPIO_MODE_I2C); + + rt288x_register_flash(0); + rt288x_register_wifi(); + rt288x_register_wdt(); + + ramips_register_gpio_leds(-1, ARRAY_SIZE(f5d8235_leds_gpio), + f5d8235_leds_gpio); + + ramips_register_gpio_buttons(-1, F5D8235_KEYS_POLL_INTERVAL, + ARRAY_SIZE(f5d8235_gpio_buttons), + f5d8235_gpio_buttons); + + platform_device_register(&f5d8235_rtl8366s_device); + + rt288x_eth_data.speed = SPEED_1000; + rt288x_eth_data.duplex = DUPLEX_FULL; + rt288x_eth_data.tx_fc = 1; + rt288x_eth_data.rx_fc = 1; + rt288x_register_ethernet(); +} + +MIPS_MACHINE(RAMIPS_MACH_F5D8235_V1, "F5D8235_V1", + "Belkin F5D8235 v1", f5d8235_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/mach-rt-n15.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/mach-rt-n15.c new file mode 100644 index 0000000000..1085b82f91 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/mach-rt-n15.c @@ -0,0 +1,99 @@ +/* + * Asus RT-N15 board support + * + * Copyright (C) 2009-2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "devices.h" + +#define RT_N15_GPIO_LED_POWER 11 +#define RT_N15_GPIO_BUTTON_WPS 0 +#define RT_N15_GPIO_BUTTON_RESET 12 + +#define RT_N15_GPIO_RTL8366_SCK 2 +#define RT_N15_GPIO_RTL8366_SDA 1 + +#define RT_N15_KEYS_POLL_INTERVAL 20 +#define RT_N15_KEYS_DEBOUNCE_INTERVAL (3 * RT_N15_KEYS_POLL_INTERVAL) + +static struct gpio_led rt_n15_leds_gpio[] __initdata = { + { + .name = "rt-n15:blue:power", + .gpio = RT_N15_GPIO_LED_POWER, + .active_low = 1, + } +}; + +static struct gpio_keys_button rt_n15_gpio_buttons[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = RT_N15_KEYS_DEBOUNCE_INTERVAL, + .gpio = RT_N15_GPIO_BUTTON_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = RT_N15_KEYS_DEBOUNCE_INTERVAL, + .gpio = RT_N15_GPIO_BUTTON_WPS, + .active_low = 1, + } +}; + +static struct rtl8366_platform_data rt_n15_rtl8366s_data = { + .gpio_sda = RT_N15_GPIO_RTL8366_SDA, + .gpio_sck = RT_N15_GPIO_RTL8366_SCK, +}; + +static struct platform_device rt_n15_rtl8366s_device = { + .name = RTL8366S_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &rt_n15_rtl8366s_data, + } +}; + +static void __init rt_n15_init(void) +{ + rt288x_gpio_init(RT2880_GPIO_MODE_UART0 | RT2880_GPIO_MODE_I2C); + + rt288x_register_flash(0); + + ramips_register_gpio_leds(-1, ARRAY_SIZE(rt_n15_leds_gpio), + rt_n15_leds_gpio); + + ramips_register_gpio_buttons(-1, RT_N15_KEYS_POLL_INTERVAL, + ARRAY_SIZE(rt_n15_gpio_buttons), + rt_n15_gpio_buttons); + + platform_device_register(&rt_n15_rtl8366s_device); + + rt288x_register_wifi(); + + rt288x_eth_data.speed = SPEED_1000; + rt288x_eth_data.duplex = DUPLEX_FULL; + rt288x_eth_data.tx_fc = 1; + rt288x_eth_data.rx_fc = 1; + rt288x_register_ethernet(); + rt288x_register_wdt(); +} + +MIPS_MACHINE(RAMIPS_MACH_RT_N15, "RT-N15", "Asus RT-N15", rt_n15_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/mach-v11st-fe.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/mach-v11st-fe.c new file mode 100644 index 0000000000..667fe92dc0 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/mach-v11st-fe.c @@ -0,0 +1,75 @@ +/* + * Ralink V11ST-FE board support + * + * Copyright (C) 2012 Florian Fainelli + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "devices.h" + +#define V11ST_FE_GPIO_STATUS_LED 12 +#define V11ST_FE_GPIO_BUTTON_WPS 0 + +#define V11ST_FE_KEYS_POLL_INTERVAL 20 +#define V11ST_FE_KEYS_DEBOUNCE_INTERVAL (3 * V11ST_FE_KEYS_POLL_INTERVAL) + +static struct gpio_led v11st_fe_leds_gpio[] __initdata = { + { + .name = "v11st-fe:green:status", + .gpio = V11ST_FE_GPIO_STATUS_LED, + .active_low = 1, + } +}; + +static struct gpio_keys_button v11st_fe_gpio_buttons[] __initdata = { + { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = V11ST_FE_KEYS_DEBOUNCE_INTERVAL, + .gpio = V11ST_FE_GPIO_BUTTON_WPS, + } +}; + +static void __init rt_v11st_fe_init(void) +{ + rt288x_gpio_init(RT2880_GPIO_MODE_UART0); + + rt288x_register_flash(0); + + ramips_register_gpio_leds(-1, ARRAY_SIZE(v11st_fe_leds_gpio), + v11st_fe_leds_gpio); + + ramips_register_gpio_buttons(-1, V11ST_FE_KEYS_POLL_INTERVAL, + ARRAY_SIZE(v11st_fe_gpio_buttons), + v11st_fe_gpio_buttons); + + rt288x_register_wifi(); + + /* Board is connected to an IC+ IP175C Fast Ethernet switch */ + rt288x_eth_data.speed = SPEED_100; + rt288x_eth_data.duplex = DUPLEX_FULL; + rt288x_eth_data.tx_fc = 1; + rt288x_eth_data.rx_fc = 1; + rt288x_eth_data.phy_mask = BIT(0); + rt288x_register_ethernet(); + + rt288x_register_wdt(); + rt288x_register_pci(); +} + +MIPS_MACHINE(RAMIPS_MACH_V11ST_FE, "V11ST-FE", "Ralink V11ST-FE", rt_v11st_fe_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/mach-wli-tx4-ag300n.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/mach-wli-tx4-ag300n.c new file mode 100644 index 0000000000..02fac0b3c5 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/mach-wli-tx4-ag300n.c @@ -0,0 +1,102 @@ +/* + * Buffalo WLI-TX4-AG300N board support + * + * Copyright (C) 2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "devices.h" + +#define WLI_TX4_AG300N_GPIO_LED_DIAG 10 +#define WLI_TX4_AG300N_GPIO_LED_POWER 12 +#define WLI_TX4_AG300N_GPIO_LED_SECURITY 13 + +#define WLI_TX4_AG300N_GPIO_BUTTON_AOSS 0 +#define WLI_TX4_AG300N_GPIO_BUTTON_BW_SWITCH 8 +#define WLI_TX4_AG300N_GPIO_BUTTON_RESET 9 + +#define WLI_TX4_AG300N_KEYS_POLL_INTERVAL 20 +#define WLI_TX4_AG300N_KEYS_DEBOUNCE_INTERVAL (3 * WLI_TX4_AG300N_KEYS_POLL_INTERVAL) + +static struct gpio_led wli_tx4_ag300n_leds_gpio[] __initdata = { + { + .name = "buffalo:blue:power", + .gpio = WLI_TX4_AG300N_GPIO_LED_POWER, + .active_low = 1, + }, + { + .name = "buffalo:red:diag", + .gpio = WLI_TX4_AG300N_GPIO_LED_DIAG, + .active_low = 1, + }, + { + .name = "buffalo:blue:security", + .gpio = WLI_TX4_AG300N_GPIO_LED_SECURITY, + .active_low = 0, + }, +}; + +static struct gpio_keys_button wli_tx4_ag300n_gpio_buttons[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WLI_TX4_AG300N_KEYS_DEBOUNCE_INTERVAL, + .gpio = WLI_TX4_AG300N_GPIO_BUTTON_RESET, + .active_low = 1, + }, + { + .desc = "AOSS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WLI_TX4_AG300N_KEYS_DEBOUNCE_INTERVAL, + .gpio = WLI_TX4_AG300N_GPIO_BUTTON_AOSS, + .active_low = 1, + }, + { + .desc = "Bandwidth switch", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = WLI_TX4_AG300N_KEYS_DEBOUNCE_INTERVAL, + .gpio = WLI_TX4_AG300N_GPIO_BUTTON_BW_SWITCH, + .active_low = 0, + }, +}; + +static void __init wli_tx4_ag300n_init(void) +{ + rt288x_gpio_init(RT2880_GPIO_MODE_UART0); + + ramips_register_gpio_leds(-1, ARRAY_SIZE(wli_tx4_ag300n_leds_gpio), + wli_tx4_ag300n_leds_gpio); + ramips_register_gpio_buttons(-1, WLI_TX4_AG300N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wli_tx4_ag300n_gpio_buttons), + wli_tx4_ag300n_gpio_buttons); + + rt288x_register_flash(0); + rt288x_register_wifi(); + rt288x_register_wdt(); + + rt288x_eth_data.speed = SPEED_100; + rt288x_eth_data.duplex = DUPLEX_FULL; + rt288x_eth_data.tx_fc = 1; + rt288x_eth_data.rx_fc = 1; + rt288x_register_ethernet(); +} + +MIPS_MACHINE(RAMIPS_MACH_WLI_TX4_AG300N, "WLI-TX4-AG300N", + "Buffalo WLI-TX4-AG300N", wli_tx4_ag300n_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/mach-wzr-agl300nh.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/mach-wzr-agl300nh.c new file mode 100644 index 0000000000..6bd7a45423 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/mach-wzr-agl300nh.c @@ -0,0 +1,77 @@ +/* + * Buffalo WZR-AGL300NH board support + * + * Copyright (C) 2010 Joonas Lahtinen + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "devices.h" + +/* + * MTD layout from stock firmware: + * mtd0: 00030000 00010000 "uboot" + * mtd1: 00010000 00010000 "uboot_environ" + * mtd2: 00010000 00010000 "factory_default" + * mtd3: 000b0000 00010000 "linux" + * mtd4: 002f0000 00010000 "rootfs" + * mtd5: 00010000 00010000 "user_property" + */ + +static struct mtd_partition wzr_agl300nh_partitions[] = { + { + .name = "uboot", + .offset = 0, + .size = 0x030000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "uboot_environ", + .offset = 0x030000, + .size = 0x010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "factory_default", + .offset = 0x040000, + .size = 0x010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "linux", + .offset = 0x050000, + .size = 0x0b0000, + }, { + .name = "rootfs", + .offset = 0x100000, + .size = 0x2f0000, + }, { + .name = "user_property", + .offset = 0x3f0000, + .size = 0x010000, + } +}; + +static void __init wzr_agl300nh_init(void) +{ + rt288x_gpio_init(RT2880_GPIO_MODE_UART0); + + rt288x_flash0_data.nr_parts = ARRAY_SIZE(wzr_agl300nh_partitions); + rt288x_flash0_data.parts = wzr_agl300nh_partitions; + rt288x_register_flash(0); + + rt288x_register_wifi(); + rt288x_register_wdt(); +} + +MIPS_MACHINE(RAMIPS_MACH_WZR_AGL300NH, "WZR-AGL300NH", + "Buffalo WZR-AGL300NH", wzr_agl300nh_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/rt288x.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/rt288x.c new file mode 100644 index 0000000000..c51ad98b3a --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/rt288x.c @@ -0,0 +1,153 @@ +/* + * Ralink RT288x SoC specific setup + * + * Copyright (C) 2008-2011 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Ralink's 2.6.21 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include +#include +#include + +void __iomem * rt288x_sysc_base; +void __iomem * rt288x_memc_base; + +void __init ramips_soc_prom_init(void) +{ + void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE); + u32 n0; + u32 n1; + u32 id; + + n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); + n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); + id = __raw_readl(sysc + SYSC_REG_CHIP_ID); + + snprintf(ramips_sys_type, RAMIPS_SYS_TYPE_LEN, + "Ralink %c%c%c%c%c%c%c%c id:%u rev:%u", + (char) (n0 & 0xff), (char) ((n0 >> 8) & 0xff), + (char) ((n0 >> 16) & 0xff), (char) ((n0 >> 24) & 0xff), + (char) (n1 & 0xff), (char) ((n1 >> 8) & 0xff), + (char) ((n1 >> 16) & 0xff), (char) ((n1 >> 24) & 0xff), + (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK, + (id & CHIP_ID_REV_MASK)); + + ramips_mem_base = RT2880_SDRAM_BASE; + ramips_mem_size_min = RT288X_MEM_SIZE_MIN; + ramips_mem_size_max = RT288X_MEM_SIZE_MAX; +} + +static struct ramips_gpio_chip rt288x_gpio_chips[] = { + { + .chip = { + .label = "RT288X-GPIO0", + .base = 0, + .ngpio = 24, + }, + .regs = { + [RAMIPS_GPIO_REG_INT] = 0x00, + [RAMIPS_GPIO_REG_EDGE] = 0x04, + [RAMIPS_GPIO_REG_RENA] = 0x08, + [RAMIPS_GPIO_REG_FENA] = 0x0c, + [RAMIPS_GPIO_REG_DATA] = 0x20, + [RAMIPS_GPIO_REG_DIR] = 0x24, + [RAMIPS_GPIO_REG_POL] = 0x28, + [RAMIPS_GPIO_REG_SET] = 0x2c, + [RAMIPS_GPIO_REG_RESET] = 0x30, + [RAMIPS_GPIO_REG_TOGGLE] = 0x34, + }, + .map_base = RT2880_PIO_BASE, + .map_size = RT2880_PIO_SIZE, + }, + { + .chip = { + .label = "RT288X-GPIO1", + .base = 24, + .ngpio = 16, + }, + .regs = { + [RAMIPS_GPIO_REG_INT] = 0x38, + [RAMIPS_GPIO_REG_EDGE] = 0x3c, + [RAMIPS_GPIO_REG_RENA] = 0x40, + [RAMIPS_GPIO_REG_FENA] = 0x44, + [RAMIPS_GPIO_REG_DATA] = 0x48, + [RAMIPS_GPIO_REG_DIR] = 0x4c, + [RAMIPS_GPIO_REG_POL] = 0x50, + [RAMIPS_GPIO_REG_SET] = 0x54, + [RAMIPS_GPIO_REG_RESET] = 0x58, + [RAMIPS_GPIO_REG_TOGGLE] = 0x5c, + }, + .map_base = RT2880_PIO_BASE, + .map_size = RT2880_PIO_SIZE, + }, + { + .chip = { + .label = "RT288X-GPIO2", + .base = 40, + .ngpio = 32, + }, + .regs = { + [RAMIPS_GPIO_REG_INT] = 0x60, + [RAMIPS_GPIO_REG_EDGE] = 0x64, + [RAMIPS_GPIO_REG_RENA] = 0x68, + [RAMIPS_GPIO_REG_FENA] = 0x6c, + [RAMIPS_GPIO_REG_DATA] = 0x70, + [RAMIPS_GPIO_REG_DIR] = 0x74, + [RAMIPS_GPIO_REG_POL] = 0x78, + [RAMIPS_GPIO_REG_SET] = 0x7c, + [RAMIPS_GPIO_REG_RESET] = 0x80, + [RAMIPS_GPIO_REG_TOGGLE] = 0x84, + }, + .map_base = RT2880_PIO_BASE, + .map_size = RT2880_PIO_SIZE, + }, +}; + +static struct ramips_gpio_data rt288x_gpio_data = { + .chips = rt288x_gpio_chips, + .num_chips = ARRAY_SIZE(rt288x_gpio_chips), +}; + +static void rt288x_gpio_reserve(int first, int last) +{ + for (; first <= last; first++) + gpio_request(first, "reserved"); +} + +void __init rt288x_gpio_init(u32 mode) +{ + rt288x_sysc_wr(mode, SYSC_REG_GPIO_MODE); + + ramips_gpio_init(&rt288x_gpio_data); + if ((mode & RT2880_GPIO_MODE_I2C) == 0) + rt288x_gpio_reserve(1, 2); + + if ((mode & RT2880_GPIO_MODE_SPI) == 0) + rt288x_gpio_reserve(3, 6); + + if ((mode & RT2880_GPIO_MODE_UART0) == 0) + rt288x_gpio_reserve(7, 14); + + if ((mode & RT2880_GPIO_MODE_JTAG) == 0) + rt288x_gpio_reserve(17, 21); + + if ((mode & RT2880_GPIO_MODE_MDIO) == 0) + rt288x_gpio_reserve(22, 23); + + if ((mode & RT2880_GPIO_MODE_SDRAM) == 0) + rt288x_gpio_reserve(24, 39); + + if ((mode & RT2880_GPIO_MODE_PCI) == 0) + rt288x_gpio_reserve(40, 71); +} diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/setup.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/setup.c new file mode 100644 index 0000000000..be474b5292 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt288x/setup.c @@ -0,0 +1,88 @@ +/* + * Ralink RT288x SoC specific setup + * + * Copyright (C) 2008 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Ralink's 2.6.21 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include "common.h" + +static void rt288x_restart(char *command) +{ + rt288x_sysc_wr(RT2880_RESET_SYSTEM, SYSC_REG_RESET_CTRL); + while (1) + if (cpu_wait) + cpu_wait(); +} + +static void rt288x_halt(void) +{ + while (1) + cpu_wait(); +} + +unsigned int __cpuinit get_c0_compare_irq(void) +{ + return CP0_LEGACY_COMPARE_IRQ; +} + +void __init ramips_soc_setup(void) +{ + struct clk *clk; + + rt288x_sysc_base = ioremap_nocache(RT2880_SYSC_BASE, RT2880_SYSC_SIZE); + rt288x_memc_base = ioremap_nocache(RT2880_MEMC_BASE, RT2880_MEMC_SIZE); + + rt288x_clocks_init(); + + clk = clk_get(NULL, "cpu"); + if (IS_ERR(clk)) + panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); + + printk(KERN_INFO "%s running at %lu.%02lu MHz\n", ramips_sys_type, + clk_get_rate(clk) / 1000000, + (clk_get_rate(clk) % 1000000) * 100 / 1000000); + + _machine_restart = rt288x_restart; + _machine_halt = rt288x_halt; + pm_power_off = rt288x_halt; + + clk = clk_get(NULL, "uart"); + if (IS_ERR(clk)) + panic("unable to get UART clock, err=%ld", PTR_ERR(clk)); + + ramips_early_serial_setup(0, RT2880_UART0_BASE, clk_get_rate(clk), + RT2880_INTC_IRQ_UART0); + ramips_early_serial_setup(1, RT2880_UART1_BASE, clk_get_rate(clk), + RT2880_INTC_IRQ_UART1); +} + +void __init plat_time_init(void) +{ + struct clk *clk; + + clk = clk_get(NULL, "cpu"); + if (IS_ERR(clk)) + panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); + + mips_hpt_frequency = clk_get_rate(clk) / 2; +} diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/Kconfig b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/Kconfig new file mode 100644 index 0000000000..700a983388 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/Kconfig @@ -0,0 +1,219 @@ +if RALINK_RT305X + +menu "Ralink RT350x machine selection" + +config RT305X_MACH_CARAMBOLA + bool "8devices Carambola dev board support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_3G_6200N + bool "Edimax 3G-6200N board support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_3G300M + bool "Tenda 3G300M board support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_BR6425 + bool "Edimax BR-6425 board support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_WR6202 + bool "Accton WR6202" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_AIR3GII + bool "AirLive Air3GII board support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_ALL0256N + bool "Allnet ALL0256N support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_ALL5002 + bool "Allnet ALL5002 support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_W502U + bool "ALFA Networks W502U board support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_ARGUS_ATP52B + bool "Argus ATP-52B support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_RT_G32_REVB + bool "Asus RT-G32 revB board support" + select RALINK_DEV_GPIO_BUTTONS + +config RT305X_MACH_RT_N10_PLUS + bool "Asus RT-N10+ board support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_WL_330N + bool "Asus WL-330N board support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_WL_330N3G + bool "Asus WL-330N3G board support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_HW550_3G + bool "Aztech HW550-3G support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_F5D8235_V2 + bool "Belkin F5D8235 v2 support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_WHR_G300N + bool "Buffalo WHR-G300N support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_DIR_300_REVB + bool "D-Link DIR-300 revB board support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_DIR_615_H1 + bool "D-Link DIR-615 H1 board support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_DAP_1350 + bool "D-Link DAP-1350 board support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_ESR_9753 + bool "EnGenius ESR-9753 support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_BROADWAY + bool "Hauppauge Broadway support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_FONERA20N + bool "La Fonera20N board support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_RT_N13U + bool "ASUS RT-N13U board support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_FREESTATION5 + bool "ARC FreeStation5" + +config RT305X_MACH_MOFI3500_3GN + bool "MoFi Network MOFI3500-3GN support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_WR512_3GN + bool "SH-WR512NU/WS-WR512N1-like 3GN router" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_UR_326N4G + bool "UR-326N4G Wireless N router" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_UR_336UN + bool "UR-336UN Wireless N router" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_NW718 + bool "Netcore NW718" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_BC2 + bool "NexAira BC2" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_OMNI_EMB + bool "Omnima MiniEMBWiFi" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_PSR_680W + bool "Petatel PSR-680W Wireless 3G Router support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_PWH2004 + bool "Prolink PWH2004 / Abocom WR5205 support (32M RAM, 8M flash)" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_V22RW_2X2 + bool "Ralink AP-RT3052-V22RW-2X2 board support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_W306R_V20 + bool "Tenda W306R V2.0 board support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_WL341V3 + bool "Sitecom WL-341 v3 board support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_WL351 + bool "Sitecom WL-351 support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_SL_R7205 + bool "Skyline SL-R7205 Wireless 3G Router support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_WCR150GN + bool "Sparklan WCR-150GN support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_NBG_419N + bool "ZyXEL NBG-419N support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_MZKW300NH2 + bool "Planex MZK-W300NH2 Router support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT305X_MACH_XDX_RN502J + bool "Unknown board XDX-RN502J" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +endmenu + +endif diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/Makefile b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/Makefile new file mode 100644 index 0000000000..47e9ce52ba --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/Makefile @@ -0,0 +1,56 @@ +# +# Makefile for the Ralink RT305x SoC specific parts of the kernel +# +# Copyright (C) 2009-2011 Gabor Juhos +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License version 2 as published +# by the Free Software Foundation. + +obj-y := irq.o setup.o devices.o rt305x.o clock.o + +obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + +obj-$(CONFIG_RT305X_MACH_3G_6200N) += mach-3g-6200n.o +obj-$(CONFIG_RT305X_MACH_3G300M) += mach-3g300m.o +obj-$(CONFIG_RT305X_MACH_ARGUS_ATP52B) += mach-argus-atp52b.o +obj-$(CONFIG_RT305X_MACH_BC2) += mach-bc2.o +obj-$(CONFIG_RT305X_MACH_AIR3GII) += mach-air3gii.o +obj-$(CONFIG_RT305X_MACH_ALL0256N) += mach-all0256n.o +obj-$(CONFIG_RT305X_MACH_ALL5002) += mach-all5002.o +obj-$(CONFIG_RT305X_MACH_BR6425) += mach-br6425.o +obj-$(CONFIG_RT305X_MACH_BROADWAY) += mach-broadway.o +obj-$(CONFIG_RT305X_MACH_CARAMBOLA) += mach-carambola.o +obj-$(CONFIG_RT305X_MACH_DIR_300_REVB) += mach-dir-300-revb.o +obj-$(CONFIG_RT305X_MACH_DIR_615_H1) += mach-dir-615-h1.o +obj-$(CONFIG_RT305X_MACH_DAP_1350) += mach-dap-1350.o +obj-$(CONFIG_RT305X_MACH_ESR_9753) += mach-esr-9753.o +obj-$(CONFIG_RT305X_MACH_F5D8235_V2) += mach-f5d8235-v2.o +obj-$(CONFIG_RT305X_MACH_FONERA20N) += mach-fonera20n.o +obj-$(CONFIG_RT305X_MACH_RT_N13U) += mach-rt-n13u.o +obj-$(CONFIG_RT305X_MACH_FREESTATION5) += mach-freestation5.o +obj-$(CONFIG_RT305X_MACH_HW550_3G) += mach-hw550-3g.o +obj-$(CONFIG_RT305X_MACH_MOFI3500_3GN) += mach-mofi3500-3gn.o +obj-$(CONFIG_RT305X_MACH_NBG_419N) += mach-nbg-419n.o +obj-$(CONFIG_RT305X_MACH_NW718) += mach-nw718.o +obj-$(CONFIG_RT305X_MACH_OMNI_EMB) += mach-omni-emb.o +obj-$(CONFIG_RT305X_MACH_PSR_680W) += mach-psr-680w.o +obj-$(CONFIG_RT305X_MACH_PWH2004) += mach-pwh2004.o +obj-$(CONFIG_RT305X_MACH_RT_G32_REVB) += mach-rt-g32-revb.o +obj-$(CONFIG_RT305X_MACH_RT_N10_PLUS) += mach-rt-n10-plus.o +obj-$(CONFIG_RT305X_MACH_SL_R7205) += mach-sl-r7205.o +obj-$(CONFIG_RT305X_MACH_V22RW_2X2) += mach-v22rw-2x2.o +obj-$(CONFIG_RT305X_MACH_W306R_V20) += mach-w306r-v20.o +obj-$(CONFIG_RT305X_MACH_W502U) += mach-w502u.o +obj-$(CONFIG_RT305X_MACH_WCR150GN) += mach-wcr150gn.o +obj-$(CONFIG_RT305X_MACH_WHR_G300N) += mach-whr-g300n.o +obj-$(CONFIG_RT305X_MACH_WR512_3GN) += mach-wr512-3gn.o +obj-$(CONFIG_RT305X_MACH_UR_326N4G) += mach-ur-326n4g.o +obj-$(CONFIG_RT305X_MACH_UR_336UN) += mach-ur-336un.o +obj-$(CONFIG_RT305X_MACH_WL_330N) += mach-wl-330n.o +obj-$(CONFIG_RT305X_MACH_WL_330N3G) += mach-wl-330n3g.o +obj-$(CONFIG_RT305X_MACH_WL341V3) += mach-wl341v3.o +obj-$(CONFIG_RT305X_MACH_WL351) += mach-wl351.o +obj-$(CONFIG_RT305X_MACH_WR6202) += mach-wr6202.o +obj-$(CONFIG_RT305X_MACH_MZKW300NH2) += mach-mzk-w300nh2.o +obj-$(CONFIG_RT305X_MACH_XDX_RN502J) += mach-xdx-rn502j.o diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/clock.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/clock.c new file mode 100644 index 0000000000..c46a1747b5 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/clock.c @@ -0,0 +1,133 @@ +/* + * Ralink RT305X clock API + * + * Copyright (C) 2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include "common.h" + +struct clk { + unsigned long rate; +}; + +static struct clk rt305x_cpu_clk; +static struct clk rt305x_sys_clk; +static struct clk rt305x_wdt_clk; +static struct clk rt305x_uart_clk; + +void __init rt305x_clocks_init(void) +{ + u32 t; + + t = rt305x_sysc_rr(SYSC_REG_SYSTEM_CONFIG); + + if (soc_is_rt305x() || soc_is_rt3350()) { + t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) & + RT305X_SYSCFG_CPUCLK_MASK; + switch (t) { + case RT305X_SYSCFG_CPUCLK_LOW: + rt305x_cpu_clk.rate = 320000000; + break; + case RT305X_SYSCFG_CPUCLK_HIGH: + rt305x_cpu_clk.rate = 384000000; + break; + } + rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3; + rt305x_uart_clk.rate = rt305x_sys_clk.rate; + rt305x_wdt_clk.rate = rt305x_sys_clk.rate; + } else if (soc_is_rt3352()) { + t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) & + RT3352_SYSCFG0_CPUCLK_MASK; + switch (t) { + case RT3352_SYSCFG0_CPUCLK_LOW: + rt305x_cpu_clk.rate = 384000000; + break; + case RT3352_SYSCFG0_CPUCLK_HIGH: + rt305x_cpu_clk.rate = 400000000; + break; + } + rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3; + rt305x_uart_clk.rate = 40000000; + rt305x_wdt_clk.rate = rt305x_sys_clk.rate; + } else if (soc_is_rt5350()) { + t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) & + RT5350_SYSCFG0_CPUCLK_MASK; + switch (t) { + case RT5350_SYSCFG0_CPUCLK_360: + rt305x_cpu_clk.rate = 360000000; + rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3; + break; + case RT5350_SYSCFG0_CPUCLK_320: + rt305x_cpu_clk.rate = 320000000; + rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 4; + break; + case RT5350_SYSCFG0_CPUCLK_300: + rt305x_cpu_clk.rate = 300000000; + rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3; + break; + default: + BUG(); + } + rt305x_uart_clk.rate = 40000000; + rt305x_wdt_clk.rate = rt305x_sys_clk.rate; + } else { + BUG(); + } + +} + +/* + * Linux clock API + */ +struct clk *clk_get(struct device *dev, const char *id) +{ + if (!strcmp(id, "sys")) + return &rt305x_sys_clk; + + if (!strcmp(id, "cpu")) + return &rt305x_cpu_clk; + + if (!strcmp(id, "wdt")) + return &rt305x_wdt_clk; + + if (!strcmp(id, "uart")) + return &rt305x_uart_clk; + + return ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL(clk_get); + +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + return clk->rate; +} +EXPORT_SYMBOL(clk_get_rate); + +void clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_put); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/common.h b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/common.h new file mode 100644 index 0000000000..48ac43e81b --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/common.h @@ -0,0 +1,16 @@ +/* + * Ralink RT305x SoC common defines + * + * Copyright (C) 2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _RT305X_COMMON_H +#define _RT305X_COMMON_H + +void rt305x_clocks_init(void); + +#endif /* _RT305X_COMMON_H */ \ No newline at end of file diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/devices.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/devices.c new file mode 100644 index 0000000000..f16ba6d5f1 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/devices.c @@ -0,0 +1,428 @@ +/* + * Ralink RT305x SoC platform device registration + * + * Copyright (C) 2009-2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include "devices.h" + +#include +#include + +static struct resource rt305x_flash0_resources[] = { + { + .flags = IORESOURCE_MEM, + .start = KSEG1ADDR(RT305X_FLASH0_BASE), + .end = KSEG1ADDR(RT305X_FLASH0_BASE) + + RT305X_FLASH0_SIZE - 1, + }, +}; + +struct physmap_flash_data rt305x_flash0_data; +static struct platform_device rt305x_flash0_device = { + .name = "physmap-flash", + .resource = rt305x_flash0_resources, + .num_resources = ARRAY_SIZE(rt305x_flash0_resources), + .dev = { + .platform_data = &rt305x_flash0_data, + }, +}; + +static struct resource rt305x_flash1_resources[] = { + { + .flags = IORESOURCE_MEM, + .start = KSEG1ADDR(RT305X_FLASH1_BASE), + .end = KSEG1ADDR(RT305X_FLASH1_BASE) + + RT305X_FLASH1_SIZE - 1, + }, +}; + +struct physmap_flash_data rt305x_flash1_data; +static struct platform_device rt305x_flash1_device = { + .name = "physmap-flash", + .resource = rt305x_flash1_resources, + .num_resources = ARRAY_SIZE(rt305x_flash1_resources), + .dev = { + .platform_data = &rt305x_flash1_data, + }, +}; + +static int rt305x_flash_instance __initdata; +void __init rt305x_register_flash(unsigned int id) +{ + struct platform_device *pdev; + struct physmap_flash_data *pdata; + u32 t; + int reg; + + switch (id) { + case 0: + pdev = &rt305x_flash0_device; + reg = MEMC_REG_FLASH_CFG0; + break; + case 1: + pdev = &rt305x_flash1_device; + reg = MEMC_REG_FLASH_CFG1; + break; + default: + return; + } + + t = rt305x_memc_rr(reg); + t = (t >> FLASH_CFG_WIDTH_SHIFT) & FLASH_CFG_WIDTH_MASK; + + pdata = pdev->dev.platform_data; + switch (t) { + case FLASH_CFG_WIDTH_8BIT: + pdata->width = 1; + break; + case FLASH_CFG_WIDTH_16BIT: + pdata->width = 2; + break; + case FLASH_CFG_WIDTH_32BIT: + pdata->width = 4; + break; + default: + printk(KERN_ERR "RT305x: flash bank%u witdh is invalid\n", id); + return; + } + + pdev->id = rt305x_flash_instance; + + platform_device_register(pdev); + rt305x_flash_instance++; +} + +static void rt305x_fe_reset(void) +{ + u32 reset_bits = RT305X_RESET_FE; + + if (soc_is_rt5350()) + reset_bits |= RT305X_RESET_ESW; + rt305x_sysc_wr(reset_bits, SYSC_REG_RESET_CTRL); + rt305x_sysc_wr(0, SYSC_REG_RESET_CTRL); +} + +static struct resource rt305x_eth_resources[] = { + { + .start = RT305X_FE_BASE, + .end = RT305X_FE_BASE + PAGE_SIZE - 1, + .flags = IORESOURCE_MEM, + }, { + .start = RT305X_CPU_IRQ_FE, + .end = RT305X_CPU_IRQ_FE, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct ramips_eth_platform_data ramips_eth_data = { + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 }, + .reset_fe = rt305x_fe_reset, + .min_pkt_len = 64, +}; + +static struct platform_device rt305x_eth_device = { + .name = "ramips_eth", + .resource = rt305x_eth_resources, + .num_resources = ARRAY_SIZE(rt305x_eth_resources), + .dev = { + .platform_data = &ramips_eth_data, + } +}; + +static struct resource rt305x_esw_resources[] = { + { + .start = RT305X_SWITCH_BASE, + .end = RT305X_SWITCH_BASE + PAGE_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct rt305x_esw_platform_data rt305x_esw_data = { + /* All ports are LAN ports. */ + .vlan_config = RT305X_ESW_VLAN_CONFIG_NONE, + .reg_initval_fct2 = 0x00d6500c, + /* + * ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1, + * turbo mii off, rgmi 3.3v off + * port5: disabled + * port6: enabled, gige, full-duplex, rx/tx-flow-control + */ + .reg_initval_fpa2 = 0x3f502b28, +}; + +static struct platform_device rt305x_esw_device = { + .name = "rt305x-esw", + .resource = rt305x_esw_resources, + .num_resources = ARRAY_SIZE(rt305x_esw_resources), + .dev = { + .platform_data = &rt305x_esw_data, + } +}; + +void __init rt305x_register_ethernet(void) +{ + struct clk *clk; + + clk = clk_get(NULL, "sys"); + if (IS_ERR(clk)) + panic("unable to get SYS clock, err=%ld", PTR_ERR(clk)); + + ramips_eth_data.sys_freq = clk_get_rate(clk); + + platform_device_register(&rt305x_esw_device); + platform_device_register(&rt305x_eth_device); +} + +static struct resource rt305x_wifi_resources[] = { + { + .start = RT305X_WMAC_BASE, + .end = RT305X_WMAC_BASE + 0x3FFFF, + .flags = IORESOURCE_MEM, + }, { + .start = RT305X_CPU_IRQ_WNIC, + .end = RT305X_CPU_IRQ_WNIC, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct rt2x00_platform_data rt305x_wifi_data; +static struct platform_device rt305x_wifi_device = { + .name = "rt2800_wmac", + .resource = rt305x_wifi_resources, + .num_resources = ARRAY_SIZE(rt305x_wifi_resources), + .dev = { + .platform_data = &rt305x_wifi_data, + } +}; + +void __init rt305x_register_wifi(void) +{ + u32 t; + + rt305x_wifi_data.eeprom_file_name = "soc_wmac.eeprom"; + + if (soc_is_rt3352() || soc_is_rt5350()) { + t = rt305x_sysc_rr(SYSC_REG_SYSTEM_CONFIG); + t &= RT3352_SYSCFG0_XTAL_SEL; + if (!t) + rt305x_wifi_data.clk_is_20mhz = 1; + } + platform_device_register(&rt305x_wifi_device); +} + +static struct resource rt305x_wdt_resources[] = { + { + .start = RT305X_TIMER_BASE, + .end = RT305X_TIMER_BASE + RT305X_TIMER_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device rt305x_wdt_device = { + .name = "ramips-wdt", + .id = -1, + .resource = rt305x_wdt_resources, + .num_resources = ARRAY_SIZE(rt305x_wdt_resources), +}; + +void __init rt305x_register_wdt(void) +{ + u32 t; + + /* enable WDT reset output on pin SRAM_CS_N */ + t = rt305x_sysc_rr(SYSC_REG_SYSTEM_CONFIG); + t |= RT305X_SYSCFG_SRAM_CS0_MODE_WDT << + RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT; + rt305x_sysc_wr(t, SYSC_REG_SYSTEM_CONFIG); + + platform_device_register(&rt305x_wdt_device); +} + +static struct resource rt305x_spi_resources[] = { + { + .flags = IORESOURCE_MEM, + .start = RT305X_SPI_BASE, + .end = RT305X_SPI_BASE + RT305X_SPI_SIZE - 1, + }, +}; + +static struct platform_device rt305x_spi_device = { + .name = "ramips-spi", + .id = 0, + .resource = rt305x_spi_resources, + .num_resources = ARRAY_SIZE(rt305x_spi_resources), +}; + +void __init rt305x_register_spi(struct spi_board_info *info, int n) +{ + spi_register_board_info(info, n); + platform_device_register(&rt305x_spi_device); +} + +static struct resource rt305x_dwc_otg_resources[] = { + { + .start = RT305X_OTG_BASE, + .end = RT305X_OTG_BASE + 0x3FFFF, + .flags = IORESOURCE_MEM, + }, { + .start = RT305X_INTC_IRQ_OTG, + .end = RT305X_INTC_IRQ_OTG, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device rt305x_dwc_otg_device = { + .name = "dwc_otg", + .resource = rt305x_dwc_otg_resources, + .num_resources = ARRAY_SIZE(rt305x_dwc_otg_resources), + .dev = { + .platform_data = NULL, + } +}; + +static atomic_t rt3352_usb_pwr_ref = ATOMIC_INIT(0); + +static int rt3352_usb_power_on(struct platform_device *pdev) +{ + + if (atomic_inc_return(&rt3352_usb_pwr_ref) == 1) { + u32 t; + + t = rt305x_sysc_rr(RT3352_SYSC_REG_USB_PS); + + /* enable clock for port0's and port1's phys */ + t = rt305x_sysc_rr(RT3352_SYSC_REG_CLKCFG1); + t |= RT3352_CLKCFG1_UPHY0_CLK_EN | RT3352_CLKCFG1_UPHY1_CLK_EN; + rt305x_sysc_wr(t, RT3352_SYSC_REG_CLKCFG1); + mdelay(500); + + /* pull USBHOST and USBDEV out from reset */ + t = rt305x_sysc_rr(RT3352_SYSC_REG_RSTCTRL); + t &= ~(RT3352_RSTCTRL_UHST | RT3352_RSTCTRL_UDEV); + rt305x_sysc_wr(t, RT3352_SYSC_REG_RSTCTRL); + mdelay(500); + + /* enable host mode */ + t = rt305x_sysc_rr(RT3352_SYSC_REG_SYSCFG1); + t |= RT3352_SYSCFG1_USB0_HOST_MODE; + rt305x_sysc_wr(t, RT3352_SYSC_REG_SYSCFG1); + + t = rt305x_sysc_rr(RT3352_SYSC_REG_USB_PS); + } + + return 0; +} + +static void rt3352_usb_power_off(struct platform_device *pdev) +{ + + if (atomic_dec_return(&rt3352_usb_pwr_ref) == 0) { + u32 t; + + /* put USBHOST and USBDEV into reset */ + t = rt305x_sysc_rr(RT3352_SYSC_REG_RSTCTRL); + t |= RT3352_RSTCTRL_UHST | RT3352_RSTCTRL_UDEV; + rt305x_sysc_wr(t, RT3352_SYSC_REG_RSTCTRL); + udelay(10000); + + /* disable clock for port0's and port1's phys*/ + t = rt305x_sysc_rr(RT3352_SYSC_REG_CLKCFG1); + t &= ~(RT3352_CLKCFG1_UPHY0_CLK_EN | RT3352_CLKCFG1_UPHY1_CLK_EN); + rt305x_sysc_wr(t, RT3352_SYSC_REG_CLKCFG1); + udelay(10000); + } +} + +static struct usb_ehci_pdata rt3352_ehci_data = { + .power_on = rt3352_usb_power_on, + .power_off = rt3352_usb_power_off, +}; + +static struct resource rt3352_ehci_resources[] = { + { + .start = RT3352_EHCI_BASE, + .end = RT3352_EHCI_BASE + RT3352_EHCI_SIZE - 1, + .flags = IORESOURCE_MEM, + }, { + .start = RT305X_INTC_IRQ_OTG, + .end = RT305X_INTC_IRQ_OTG, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 rt3352_ehci_dmamask = DMA_BIT_MASK(32); +static struct platform_device rt3352_ehci_device = { + .name = "ehci-platform", + .id = -1, + .resource = rt3352_ehci_resources, + .num_resources = ARRAY_SIZE(rt3352_ehci_resources), + .dev = { + .dma_mask = &rt3352_ehci_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &rt3352_ehci_data, + }, +}; + +static struct resource rt3352_ohci_resources[] = { + { + .start = RT3352_OHCI_BASE, + .end = RT3352_OHCI_BASE + RT3352_OHCI_SIZE - 1, + .flags = IORESOURCE_MEM, + }, { + .start = RT305X_INTC_IRQ_OTG, + .end = RT305X_INTC_IRQ_OTG, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct usb_ohci_pdata rt3352_ohci_data = { + .power_on = rt3352_usb_power_on, + .power_off = rt3352_usb_power_off, +}; + +static u64 rt3352_ohci_dmamask = DMA_BIT_MASK(32); +static struct platform_device rt3352_ohci_device = { + .name = "ohci-platform", + .id = -1, + .resource = rt3352_ohci_resources, + .num_resources = ARRAY_SIZE(rt3352_ohci_resources), + .dev = { + .dma_mask = &rt3352_ohci_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &rt3352_ohci_data, + }, +}; + +void __init rt305x_register_usb(void) +{ + if (soc_is_rt305x() || soc_is_rt3350()) { + platform_device_register(&rt305x_dwc_otg_device); + } else if (soc_is_rt3352() || soc_is_rt5350()) { + platform_device_register(&rt3352_ehci_device); + platform_device_register(&rt3352_ohci_device); + } else { + BUG(); + } +} diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/devices.h b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/devices.h new file mode 100644 index 0000000000..22c9ce4232 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/devices.h @@ -0,0 +1,32 @@ +/* + * Ralink RT305x SoC specific platform device definitions + * + * Copyright (C) 2009-2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __RT305X_DEVICES_H +#define __RT305X_DEVICES_H + +#include + +struct physmap_flash_data; +struct spi_board_info; + +extern struct physmap_flash_data rt305x_flash0_data; +extern struct physmap_flash_data rt305x_flash1_data; + +extern struct rt305x_esw_platform_data rt305x_esw_data; + +void rt305x_register_flash(unsigned int id); +void rt305x_register_ethernet(void); +void rt305x_register_wifi(void); +void rt305x_register_wdt(void); +void rt305x_register_spi(struct spi_board_info *info, int n); +void rt305x_register_usb(void); + +#endif /* __RT305X_DEVICES_H */ + diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/early_printk.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/early_printk.c new file mode 100644 index 0000000000..602df863ef --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/early_printk.c @@ -0,0 +1,29 @@ +/* + * Ralink RT305x SoC early printk support + * + * Copyright (C) 2009 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include + +#include + +#define UART_READ(r) \ + __raw_readl((void __iomem *)(KSEG1ADDR(RT305X_UART1_BASE) + 4 * (r))) + +#define UART_WRITE(r, v) \ + __raw_writel((v), (void __iomem *)(KSEG1ADDR(RT305X_UART1_BASE) + 4 * (r))) + +void prom_putchar(unsigned char ch) +{ + while (((UART_READ(UART_REG_LSR)) & UART_LSR_THRE) == 0); + UART_WRITE(UART_REG_TX, ch); + while (((UART_READ(UART_REG_LSR)) & UART_LSR_THRE) == 0); +} diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/irq.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/irq.c new file mode 100644 index 0000000000..fcac2dd860 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/irq.c @@ -0,0 +1,82 @@ +/* + * Ralink RT305x SoC specific interrupt handling + * + * Copyright (C) 2009 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +static void rt305x_intc_irq_dispatch(void) +{ + u32 pending; + + pending = ramips_intc_get_status(); + + if (pending & RT305X_INTC_INT_TIMER0) + do_IRQ(RT305X_INTC_IRQ_TIMER0); + + else if (pending & RT305X_INTC_INT_TIMER1) + do_IRQ(RT305X_INTC_IRQ_TIMER1); + + else if (pending & RT305X_INTC_INT_UART0) + do_IRQ(RT305X_INTC_IRQ_UART0); + + else if (pending & RT305X_INTC_INT_UART1) + do_IRQ(RT305X_INTC_IRQ_UART1); + + else if (pending & RT305X_INTC_INT_PERFC) + do_IRQ(RT305X_INTC_IRQ_PERFC); + + else if (pending & RT305X_INTC_INT_OTG) + do_IRQ(RT305X_INTC_IRQ_OTG); + + /* TODO: handle PIO interrupts as well */ + + else + spurious_interrupt(); +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned long pending; + + pending = read_c0_status() & read_c0_cause() & ST0_IM; + + if (pending & STATUSF_IP7) + do_IRQ(RT305X_CPU_IRQ_COUNTER); + + else if (pending & STATUSF_IP5) + do_IRQ(RT305X_CPU_IRQ_FE); + + else if (pending & STATUSF_IP6) + do_IRQ(RT305X_CPU_IRQ_WNIC); + + else if (pending & STATUSF_IP2) + rt305x_intc_irq_dispatch(); + + else + spurious_interrupt(); +} + +void __init arch_init_irq(void) +{ + mips_cpu_irq_init(); + ramips_intc_irq_init(RT305X_INTC_BASE, RT305X_CPU_IRQ_INTC, + RT305X_INTC_IRQ_BASE); + + cp0_perfcount_irq = RT305X_INTC_IRQ_PERFC; +} diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-3g-6200n.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-3g-6200n.c new file mode 100644 index 0000000000..ade4fe9008 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-3g-6200n.c @@ -0,0 +1,86 @@ +/* + * Edimax 3g-6200n board support + * + * Copyright (C) 2011 Andrzej Hajda + * Copyright (C) 2012 Lukasz Golebiowski + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + + +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define EDIMAX_GPIO_BUTTON_WPS 12 +#define EDIMAX_GPIO_BTN_0 13 /* Wifi on/off switch button */ + +#define EDIMAX_GPIO_LED_POWER 9 +#define EDIMAX_GPIO_LED_WLAN 14 +#define EDIMAX_GPIO_LED_3G 7 + +#define EDIMAX_KEYS_POLL_INTERVAL 20 +#define EDIMAX_KEYS_DEBOUNCE_INTERVAL (3 * EDIMAX_KEYS_POLL_INTERVAL) + +static struct gpio_led edimax_leds_gpio[] __initdata = { + { + .name = "edimax:green:power", + .gpio = EDIMAX_GPIO_LED_POWER, + .active_low = 1, + }, { + .name = "edimax:amber:wlan", + .gpio = EDIMAX_GPIO_LED_WLAN, + .active_low = 1, + }, { + .name = "edimax:blue:3g", + .gpio = EDIMAX_GPIO_LED_3G, + .active_low = 1, + } +}; + +static struct gpio_keys_button edimax_gpio_buttons[] __initdata = { + { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = EDIMAX_KEYS_DEBOUNCE_INTERVAL, + .gpio = EDIMAX_GPIO_BUTTON_WPS, + .active_low = 1, + }, { + .desc = "wlanswitch", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = EDIMAX_KEYS_DEBOUNCE_INTERVAL, + .gpio = EDIMAX_GPIO_BTN_0, + .active_low = 1, + } +}; + +static void __init edimax_init(void) +{ + rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); + + rt305x_register_flash(0); + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; + rt305x_register_ethernet(); + ramips_register_gpio_leds(-1, ARRAY_SIZE(edimax_leds_gpio), + edimax_leds_gpio); + ramips_register_gpio_buttons(-1, EDIMAX_KEYS_POLL_INTERVAL, + ARRAY_SIZE(edimax_gpio_buttons), + edimax_gpio_buttons); + rt305x_register_wifi(); + rt305x_register_wdt(); + rt305x_register_usb(); +} + +MIPS_MACHINE(RAMIPS_MACH_3G_6200N, "3G-6200N", "Edimax 3g-6200n", + edimax_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-3g300m.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-3g300m.c new file mode 100644 index 0000000000..e4993b303e --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-3g300m.c @@ -0,0 +1,126 @@ +/* + * Tenda 3G300M board support + * + * Copyright (C) 2013 Cezary Jackiewicz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define TENDA_3G300M_GPIO_BUTTON_RESET 0 +#define TENDA_3G300M_GPIO_BUTTON_MODE 10 + +#define TENDA_3G300M_GPIO_LED_3GROUTER 11 +#define TENDA_3G300M_GPIO_LED_AP 12 +#define TENDA_3G300M_GPIO_LED_WISPROUTER 9 +#define TENDA_3G300M_GPIO_LED_WIRELESSROUTER 13 +#define TENDA_3G300M_GPIO_LED_3G 7 +#define TENDA_3G300M_GPIO_LED_WPSRESET 14 + +#define TENDA_3G300M_KEYS_POLL_INTERVAL 20 +#define TENDA_3G300M_KEYS_DEBOUNCE_INTERVAL (3 * TENDA_3G300M_KEYS_POLL_INTERVAL) + +const struct flash_platform_data tenda_3g300m_flash = { + .type = "mx25l3205d", +}; + +struct spi_board_info tenda_3g300m_spi_slave_info[] __initdata = { + { + .modalias = "m25p80", + .platform_data = &tenda_3g300m_flash, + .irq = -1, + .max_speed_hz = 10000000, + .bus_num = 0, + .chip_select = 0, + } +}; + +static struct gpio_led tenda_3g300m_leds_gpio[] __initdata = { + { + .name = "tenda:blue:3grouter", + .gpio = TENDA_3G300M_GPIO_LED_3GROUTER, + .active_low = 1, + },{ + .name = "tenda:blue:ap", + .gpio = TENDA_3G300M_GPIO_LED_AP, + .active_low = 1, + },{ + .name = "tenda:blue:wisprouter", + .gpio = TENDA_3G300M_GPIO_LED_WISPROUTER, + .active_low = 1, + },{ + .name = "tenda:blue:wirelessrouter", + .gpio = TENDA_3G300M_GPIO_LED_WIRELESSROUTER, + .active_low = 1, + },{ + .name = "tenda:blue:3g", + .gpio = TENDA_3G300M_GPIO_LED_3G, + .active_low = 1, + },{ + .name = "tenda:blue:wpsreset", + .gpio = TENDA_3G300M_GPIO_LED_WPSRESET, + .active_low = 1, + } +}; + +static struct gpio_keys_button tenda_3g300m_gpio_buttons[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TENDA_3G300M_KEYS_DEBOUNCE_INTERVAL, + .gpio = TENDA_3G300M_GPIO_BUTTON_RESET, + .active_low = 1, + },{ + .desc = "mode", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = TENDA_3G300M_KEYS_DEBOUNCE_INTERVAL, + .gpio = TENDA_3G300M_GPIO_BUTTON_MODE, + .active_low = 1, + } +}; + +static void __init tenda_3g300m_init(void) +{ + rt305x_gpio_init((RT305X_GPIO_MODE_GPIO << + RT305X_GPIO_MODE_UART0_SHIFT) | + RT305X_GPIO_MODE_JTAG); + + rt305x_register_spi(tenda_3g300m_spi_slave_info, + ARRAY_SIZE(tenda_3g300m_spi_slave_info)); + + ramips_register_gpio_leds(-1, ARRAY_SIZE(tenda_3g300m_leds_gpio), + tenda_3g300m_leds_gpio); + + ramips_register_gpio_buttons(-1, TENDA_3G300M_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tenda_3g300m_gpio_buttons), + tenda_3g300m_gpio_buttons); + + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; + rt305x_register_ethernet(); + + rt305x_register_wifi(); + + rt305x_register_wdt(); + + rt305x_register_usb(); +} + +MIPS_MACHINE(RAMIPS_MACH_3G300M, "3G300M", "Tenda 3G300M", + tenda_3g300m_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-air3gii.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-air3gii.c new file mode 100644 index 0000000000..aca238abe1 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-air3gii.c @@ -0,0 +1,94 @@ +/* + * AirLive Air3GII board support + * + * Copyright (C) 2012 Cezary Jackiewicz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define AIR3GII_GPIO_BUTTON_WPS 7 + +#define AIR3GII_GPIO_LED_WLAN 8 +#define AIR3GII_GPIO_LED_MOBILE 9 + +#define AIR3GII_KEYS_POLL_INTERVAL 20 +#define AIR3GII_KEYS_DEBOUNCE_INTERVAL (3 * AIR3GII_KEYS_POLL_INTERVAL) + +const struct flash_platform_data air3gii_flash = { + .type = "en25q32b", +}; + +struct spi_board_info air3gii_spi_slave_info[] __initdata = { + { + .modalias = "m25p80", + .platform_data = &air3gii_flash, + .irq = -1, + .max_speed_hz = 10000000, + .bus_num = 0, + .chip_select = 0, + }, +}; + +static struct gpio_led air3gii_leds_gpio[] __initdata = { + { + .name = "airlive:green:wlan", + .gpio = AIR3GII_GPIO_LED_WLAN, + .active_low = 0, + }, { + .name = "airlive:green:mobile", + .gpio = AIR3GII_GPIO_LED_MOBILE, + .active_low = 1, + } +}; + +static struct gpio_keys_button air3gii_gpio_buttons[] __initdata = { + { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = AIR3GII_KEYS_DEBOUNCE_INTERVAL, + .gpio = AIR3GII_GPIO_BUTTON_WPS, + .active_low = 1, + } +}; + +static void __init air3gii_init(void) +{ + rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); + + rt305x_register_spi(air3gii_spi_slave_info, + ARRAY_SIZE(air3gii_spi_slave_info)); + + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; + rt305x_register_ethernet(); + + ramips_register_gpio_leds(-1, ARRAY_SIZE(air3gii_leds_gpio), + air3gii_leds_gpio); + + ramips_register_gpio_buttons(-1, AIR3GII_KEYS_POLL_INTERVAL, + ARRAY_SIZE(air3gii_gpio_buttons), + air3gii_gpio_buttons); + + rt305x_register_wifi(); + rt305x_register_wdt(); + rt305x_register_usb(); +} + +MIPS_MACHINE(RAMIPS_MACH_AIR3GII, "AIR3GII", "AirLive Air3GII", + air3gii_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-all0256n.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-all0256n.c new file mode 100644 index 0000000000..7f5e00b418 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-all0256n.c @@ -0,0 +1,90 @@ +/* + * Allnet ALL0256N board support + * + * Copyright (C) 2012 Daniel Golle + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define ALL0256N_GPIO_BUTTON_RESET 0 +#define ALL0256N_GPIO_LED_RSSI_LOW 14 +#define ALL0256N_GPIO_LED_RSSI_MED 12 +#define ALL0256N_GPIO_LED_RSSI_HIGH 13 +#define ALL0256N_KEYS_POLL_INTERVAL 20 +#define ALL0256N_KEYS_DEBOUNCE_INTERVAL (3 * ALL0256N_KEYS_POLL_INTERVAL) + +const struct flash_platform_data all0256n_flash = { + .type = "mx25l3205d", +}; + +struct spi_board_info all0256n_spi_slave_info[] __initdata = { + { + .modalias = "m25p80", + .platform_data = &all0256n_flash, + .irq = -1, + .max_speed_hz = 10000000, + .bus_num = 0, + .chip_select = 0, + }, +}; + +static struct gpio_keys_button all0256n_gpio_buttons[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = ALL0256N_KEYS_DEBOUNCE_INTERVAL, + .gpio = ALL0256N_GPIO_BUTTON_RESET, + .active_low = 1, + } +}; + +static struct gpio_led all0256n_leds_gpio[] __initdata = { + { + .name = "all0256n:green:rssilow", + .gpio = ALL0256N_GPIO_LED_RSSI_LOW, + .active_low = 1, + }, { + .name = "all0256n:green:rssimed", + .gpio = ALL0256N_GPIO_LED_RSSI_MED, + .active_low = 1, + }, { + .name = "all0256n:green:rssihigh", + .gpio = ALL0256N_GPIO_LED_RSSI_HIGH, + .active_low = 1, + } +}; + +static void __init all0256n_init(void) +{ + rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); + rt305x_register_spi(all0256n_spi_slave_info, + ARRAY_SIZE(all0256n_spi_slave_info)); + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_NONE; + rt305x_register_ethernet(); + ramips_register_gpio_leds(-1, ARRAY_SIZE(all0256n_leds_gpio), + all0256n_leds_gpio); + ramips_register_gpio_buttons(-1, ALL0256N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(all0256n_gpio_buttons), + all0256n_gpio_buttons); + rt305x_register_wifi(); + rt305x_register_wdt(); +} + +MIPS_MACHINE(RAMIPS_MACH_ALL0256N, "ALL0256N", "Allnet ALL0256N", + all0256n_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-all5002.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-all5002.c new file mode 100644 index 0000000000..71938f028c --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-all5002.c @@ -0,0 +1,61 @@ +/* + * Allnet ALL5002 + * + * Copyright (C) 2012 Daniel Golle + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +// #define ALL5002_GPIO_BUTTON_RESET 0 +// #define ALL5002_GPIO_LED_RSSI_LOW 14 +// #define ALL5002_GPIO_LED_RSSI_MED 12 +// #define ALL5002_GPIO_LED_RSSI_HIGH 13 +// #define ALL5002_BUTTONS_POLL_INTERVAL 20 + +const struct flash_platform_data all5002_flash = { + .type = "mx25l25635e", +}; + +struct spi_board_info all5002_spi_slave_info[] __initdata = { + { + .modalias = "m25p80", + .platform_data = &all5002_flash, + .irq = -1, + .max_speed_hz = 10000000, + .bus_num = 0, + .chip_select = 0, + }, +}; + +static void __init all5002_init(void) +{ + rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); + rt305x_register_spi(all5002_spi_slave_info, + ARRAY_SIZE(all5002_spi_slave_info)); + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_NONE; + rt305x_register_ethernet(); + rt305x_register_wifi(); + rt305x_register_wdt(); + rt305x_register_usb(); +} + +MIPS_MACHINE(RAMIPS_MACH_ALL5002, "ALL5002", "Allnet ALL5002/ALL5003", + all5002_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-argus-atp52b.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-argus-atp52b.c new file mode 100644 index 0000000000..b683485d71 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-argus-atp52b.c @@ -0,0 +1,81 @@ +/* + * Argus ATP-52B router support + * http://www.argus-co.com/english/productsview.php?id=70&cid=81 + * + * Copyright (C) 2011 Roman Yeryomin + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define ARGUS_ATP52B_GPIO_LED_RUN 9 +#define ARGUS_ATP52B_GPIO_LED_NET 13 +#define ARGUS_ATP52B_GPIO_BUTTON_WPS 0 +#define ARGUS_ATP52B_GPIO_BUTTON_RESET 10 +#define ARGUS_ATP52B_KEYS_POLL_INTERVAL 20 +#define ARGUS_ATP52B_KEYS_DEBOUNCE_INTERVAL (3 * ARGUS_ATP52B_KEYS_POLL_INTERVAL) + +static struct gpio_led argus_atp52b_leds_gpio[] __initdata = { + { + .name = "argus-atp52b:green:run", + .gpio = ARGUS_ATP52B_GPIO_LED_RUN, + .active_low = 1, + }, + { + .name = "argus-atp52b:amber:net", + .gpio = ARGUS_ATP52B_GPIO_LED_NET, + .active_low = 1, + } +}; + +static struct gpio_keys_button argus_atp52b_gpio_buttons[] __initdata = { + { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = ARGUS_ATP52B_KEYS_DEBOUNCE_INTERVAL, + .gpio = ARGUS_ATP52B_GPIO_BUTTON_WPS, + .active_low = 1, + }, + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = ARGUS_ATP52B_KEYS_DEBOUNCE_INTERVAL, + .gpio = ARGUS_ATP52B_GPIO_BUTTON_RESET, + .active_low = 1, + } +}; + +static void __init argus_atp52b_init(void) +{ + rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); + + rt305x_register_flash(0); + + ramips_register_gpio_leds(-1, ARRAY_SIZE(argus_atp52b_leds_gpio), + argus_atp52b_leds_gpio); + ramips_register_gpio_buttons(-1, ARGUS_ATP52B_KEYS_POLL_INTERVAL, + ARRAY_SIZE(argus_atp52b_gpio_buttons), + argus_atp52b_gpio_buttons); + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL; + rt305x_register_ethernet(); + rt305x_register_wifi(); + rt305x_register_wdt(); + rt305x_register_usb(); +} + +MIPS_MACHINE(RAMIPS_MACH_ARGUS_ATP52B, "ARGUS_ATP52B", "Argus ATP-52B", + argus_atp52b_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-bc2.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-bc2.c new file mode 100644 index 0000000000..7a21488511 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-bc2.c @@ -0,0 +1,70 @@ +/* + * NexAira BC2 board support + * + * Copyright (C) 2011 Adam J. Porter + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define BC2_GPIO_BUTTON_RESET 17 +#define BC2_GPIO_LED_USB 20 + +#define BC2_KEYS_POLL_INTERVAL 20 +#define BC2_KEYS_DEBOUNCE_INTERVAL (3 * BC2_KEYS_POLL_INTERVAL) + +static struct gpio_led bc2_leds_gpio[] __initdata = { + { + .name = "bc2:blue:usb", + .gpio = BC2_GPIO_LED_USB, + .active_low = 1, + } +}; + +static struct gpio_keys_button bc2_gpio_buttons[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = BC2_KEYS_DEBOUNCE_INTERVAL, + .gpio = BC2_GPIO_BUTTON_RESET, + .active_low = 1, + } +}; + +static void __init bc2_init(void) +{ + rt305x_gpio_init((RT305X_GPIO_MODE_GPIO << + RT305X_GPIO_MODE_UART0_SHIFT) | + RT305X_GPIO_MODE_JTAG); + + rt305x_register_flash(0); + + ramips_register_gpio_leds(-1, ARRAY_SIZE(bc2_leds_gpio), + bc2_leds_gpio); + + ramips_register_gpio_buttons(-1, BC2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(bc2_gpio_buttons), + bc2_gpio_buttons); + + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; + rt305x_register_ethernet(); + rt305x_register_wifi(); + rt305x_register_wdt(); + rt305x_register_usb(); +} + +MIPS_MACHINE(RAMIPS_MACH_BC2, "BC2", "NexAira BC2", + bc2_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-br6425.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-br6425.c new file mode 100644 index 0000000000..3a24516496 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-br6425.c @@ -0,0 +1,78 @@ +/* + * Edimax BR-6425 board support + * + * Copyright (C) 2012 OpenWrt.org + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define BR6425_GPIO_LED_POWER 9 +#define BR6425_GPIO_BUTTON_RESET 12 +#define BR6425_GPIO_SWITCH_RFKILL 13 +#define BR6425_GPIO_LED_WLAN 14 +#define BR6425_KEYS_POLL_INTERVAL 20 +#define BR6425_KEYS_DEBOUNCE_INTERVAL (3 * BR6425_KEYS_POLL_INTERVAL) + +static struct gpio_keys_button br6425_gpio_buttons[] __initdata = { + { + .desc = "reset_wps", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = BR6425_KEYS_DEBOUNCE_INTERVAL, + .gpio = BR6425_GPIO_BUTTON_RESET, + .active_low = 1, + }, + { + .desc = "RFKILL switch", + .type = EV_SW, + .code = KEY_RFKILL, + .debounce_interval = BR6425_KEYS_DEBOUNCE_INTERVAL, + .gpio = BR6425_GPIO_SWITCH_RFKILL, + .active_low = 1, + }, +}; + +static struct gpio_led br6425_leds_gpio[] __initdata = { + { + .name = "edimax:green:power", + .gpio = BR6425_GPIO_LED_POWER, + .active_low = 1, + }, { + .name = "edimax:orange:wlan", + .gpio = BR6425_GPIO_LED_WLAN, + .active_low = 1, + }, +}; + +static void __init br6425_init(void) +{ + rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); + rt305x_register_flash(0); + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; + rt305x_register_ethernet(); + ramips_register_gpio_leds(-1, ARRAY_SIZE(br6425_leds_gpio), + br6425_leds_gpio); + ramips_register_gpio_buttons(-1, BR6425_KEYS_POLL_INTERVAL, + ARRAY_SIZE(br6425_gpio_buttons), + br6425_gpio_buttons); + rt305x_register_wifi(); + rt305x_register_wdt(); +} + +MIPS_MACHINE(RAMIPS_MACH_BR6425, "BR-6425", "Edimax BR-6425", + br6425_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-broadway.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-broadway.c new file mode 100644 index 0000000000..74dfaa30b0 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-broadway.c @@ -0,0 +1,87 @@ +/* + * Hauppauge/PCTV Broadway Support + * + * Copyright (C) 2012 Devin Heitmueller + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define BROADWAY_GPIO_LED_DISKMOUNT 9 +#define BROADWAY_GPIO_LED_WPS 14 + +#define BROADWAY_GPIO_BUTTON_WPS 0 +#define BROADWAY_GPIO_BUTTON_FACTORYRESET 13 + +#define BROADWAY_KEYS_POLL_INTERVAL 20 +#define BROADWAY_KEYS_DEBOUNCE_INTERVAL (3 * BROADWAY_KEYS_POLL_INTERVAL) + +static struct gpio_led broadway_leds_gpio[] __initdata = { + { + .name = "red:diskmounted", + .gpio = BROADWAY_GPIO_LED_DISKMOUNT, + .active_low = 1, + }, + { + .name = "red:wps_active", + .gpio = BROADWAY_GPIO_LED_WPS, + .active_low = 1, + }, +}; + +static struct gpio_keys_button broadway_gpio_buttons[] __initdata = { + { + .desc = "Factory Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = BROADWAY_KEYS_DEBOUNCE_INTERVAL, + .gpio = BROADWAY_GPIO_BUTTON_FACTORYRESET, + .active_low = 1, + }, +#ifdef DJH_WPS_BUTTON_NOT_WIRED_TO_GPIO + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = BROADWAY_KEYS_DEBOUNCE_INTERVAL, + .gpio = BROADWAY_GPIO_BUTTON_WPS, + .active_low = 1, + }, +#endif +}; + +static void __init broadway_init(void) +{ + rt305x_gpio_init((RT305X_GPIO_MODE_GPIO << + RT305X_GPIO_MODE_UART0_SHIFT)); + + rt305x_register_flash(0); + + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL; + rt305x_register_ethernet(); + + ramips_register_gpio_leds(-1, ARRAY_SIZE(broadway_leds_gpio), + broadway_leds_gpio); + ramips_register_gpio_buttons(-1, BROADWAY_KEYS_POLL_INTERVAL, + ARRAY_SIZE(broadway_gpio_buttons), + broadway_gpio_buttons); + + rt305x_register_wifi(); + rt305x_register_wdt(); + rt305x_register_usb(); +} + +MIPS_MACHINE(RAMIPS_MACH_BROADWAY, "BROADWAY", "Hauppauge Broadway", + broadway_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-carambola.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-carambola.c new file mode 100644 index 0000000000..c24527a7ba --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-carambola.c @@ -0,0 +1,42 @@ +/* + * 8devices Carambola dev board support + * + * Copyright (C) 2012 Tobias Diedrich + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +static void __init carambola_init(void) +{ + /* Ugh, inverted logic... + * This actually puts the pins into GPIO mode rather I2C, SPI, ... */ + rt305x_gpio_init(RT305X_GPIO_MODE_UART0(RT305X_GPIO_MODE_GPIO) | + RT305X_GPIO_MODE_I2C | + RT305X_GPIO_MODE_SPI | + RT305X_GPIO_MODE_JTAG | + RT305X_GPIO_MODE_MDIO); + + rt305x_register_flash(0); + + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_NONE; + rt305x_register_ethernet(); + rt305x_register_wifi(); + rt305x_register_wdt(); + rt305x_register_usb(); +} + +MIPS_MACHINE(RAMIPS_MACH_CARAMBOLA, "CARAMBOLA", "8devices Carambola", + carambola_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-dap-1350.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-dap-1350.c new file mode 100644 index 0000000000..17a49aac5a --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-dap-1350.c @@ -0,0 +1,95 @@ +/* + * D-Link DAP-1350 board support + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define DAP_1350_GPIO_LED_POWER_BLUE 8 +#define DAP_1350_GPIO_LED_POWER_RED 9 +#define DAP_1350_GPIO_LED_WPS 14 + +#define DAP_1350_GPIO_BUTTON_WPS 0 /* active low */ +#define DAP_1350_GPIO_BUTTON_RESET 10 /* active low */ +#define DAP_1350_GPIO_SWITCH_MODE_AP 7 /* active low */ +#define DAP_1350_GPIO_SWITCH_MODE_RT 11 /* active low */ + +#define DAP_1350_KEYS_POLL_INTERVAL 20 +#define DAP_1350_KEYS_DEBOUNCE_INTERVAL (3 * DAP_1350_KEYS_POLL_INTERVAL) + +static struct gpio_led dap_1350_leds_gpio[] __initdata = { + { + .name = "d-link:blue:power", + .gpio = DAP_1350_GPIO_LED_POWER_BLUE, + .active_low = 1, + }, { + .name = "d-link:red:power", + .gpio = DAP_1350_GPIO_LED_POWER_RED, + .active_low = 1, + }, { + .name = "d-link:blue:wps", + .gpio = DAP_1350_GPIO_LED_WPS, + .active_low = 1, + } +}; + +static struct gpio_keys_button dap_1350_gpio_buttons[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DAP_1350_KEYS_DEBOUNCE_INTERVAL, + .gpio = DAP_1350_GPIO_BUTTON_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DAP_1350_KEYS_DEBOUNCE_INTERVAL, + .gpio = DAP_1350_GPIO_BUTTON_WPS, + .active_low = 1, + }, { + .desc = "rt", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = DAP_1350_KEYS_DEBOUNCE_INTERVAL, + .gpio = DAP_1350_GPIO_SWITCH_MODE_RT, + .active_low = 1, + }, { + .desc = "ap", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = DAP_1350_KEYS_DEBOUNCE_INTERVAL, + .gpio = DAP_1350_GPIO_SWITCH_MODE_AP, + .active_low = 1, + } +}; + +static void __init dap_1350_init(void) +{ + rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); + + rt305x_register_flash(0); + + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; + rt305x_register_ethernet(); + ramips_register_gpio_leds(-1, ARRAY_SIZE(dap_1350_leds_gpio), + dap_1350_leds_gpio); + ramips_register_gpio_buttons(-1, DAP_1350_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dap_1350_gpio_buttons), + dap_1350_gpio_buttons); + rt305x_register_wifi(); + rt305x_register_wdt(); + rt305x_register_usb(); +} + +MIPS_MACHINE(RAMIPS_MACH_DAP_1350, "DAP-1350", "D-Link DAP-1350", + dap_1350_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-dir-300-revb.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-dir-300-revb.c new file mode 100644 index 0000000000..3ae1b7852c --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-dir-300-revb.c @@ -0,0 +1,155 @@ +/* + * D-Link DIR-300 rev B board support + * + * Copyright (C) 2009-2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define DIR_300B_GPIO_LED_STATUS_AMBER 8 +#define DIR_300B_GPIO_LED_STATUS_GREEN 9 +#define DIR_300B_GPIO_LED_WPS 13 +/* + * NOTE: The wan led is also connected to the switch, both + * switch and gpio must be active to make it light up + */ +#define DIR_300B_GPIO_LED_WAN_GREEN 12 +#define DIR_300B_GPIO_LED_WAN_AMBER 14 + +/* + * NOTE: the WPS led in DIR-620 consists of two antiparallel leds, + * so they can't be lit simultaneously + */ +#define DIR_620_GPIO_LED_WPS_AMBER 11 + +#define DIR_300B_GPIO_BUTTON_WPS 0 /* active low */ +#define DIR_300B_GPIO_BUTTON_RESET 10 /* active low */ + +#define DIR_300B_KEYS_POLL_INTERVAL 20 +#define DIR_300B_KEYS_DEBOUNCE_INTERVAL (3 * DIR_300B_KEYS_POLL_INTERVAL) + +static struct gpio_led dir_300b_leds_gpio[] __initdata = { + { + .name = "d-link:amber:status", + .gpio = DIR_300B_GPIO_LED_STATUS_AMBER, + .active_low = 1, + }, { + .name = "d-link:green:status", + .gpio = DIR_300B_GPIO_LED_STATUS_GREEN, + .active_low = 1, + }, { + .name = "d-link:amber:wan", + .gpio = DIR_300B_GPIO_LED_WAN_AMBER, + .active_low = 1, + }, { + .name = "d-link:green:wan", + .gpio = DIR_300B_GPIO_LED_WAN_GREEN, + .active_low = 1, + }, { + .name = "d-link:blue:wps", + .gpio = DIR_300B_GPIO_LED_WPS, + .active_low = 1, + } +}; + +static struct gpio_keys_button dir_300b_gpio_buttons[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DIR_300B_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR_300B_GPIO_BUTTON_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DIR_300B_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR_300B_GPIO_BUTTON_WPS, + .active_low = 1, + } +}; + +static struct gpio_led dir_620_leds_gpio[] __initdata = { + { + .name = "d-link:amber:status", + .gpio = DIR_300B_GPIO_LED_STATUS_AMBER, + .active_low = 1, + }, { + .name = "d-link:green:status", + .gpio = DIR_300B_GPIO_LED_STATUS_GREEN, + .active_low = 1, + }, { + .name = "d-link:amber:wan", + .gpio = DIR_300B_GPIO_LED_WAN_AMBER, + .active_low = 1, + }, { + .name = "d-link:green:wan", + .gpio = DIR_300B_GPIO_LED_WAN_GREEN, + .active_low = 1, + }, { + .name = "d-link:blue:wps", + .gpio = DIR_300B_GPIO_LED_WPS, + }, { + .name = "d-link:amber:wps", + .gpio = DIR_620_GPIO_LED_WPS_AMBER, + } +}; + +static void __init dir_common_init(void) +{ + rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); + + rt305x_register_flash(0); + + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; + rt305x_register_ethernet(); + ramips_register_gpio_buttons(-1, DIR_300B_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dir_300b_gpio_buttons), + dir_300b_gpio_buttons); + rt305x_register_wifi(); + rt305x_register_wdt(); +} + +static void __init dir_300b_init(void) +{ + dir_common_init(); + ramips_register_gpio_leds(-1, ARRAY_SIZE(dir_300b_leds_gpio), + dir_300b_leds_gpio); +} + +static void __init dir_620a1_init(void) +{ + dir_common_init(); + ramips_register_gpio_leds(-1, ARRAY_SIZE(dir_620_leds_gpio), + dir_620_leds_gpio); + rt305x_register_usb(); +} + +MIPS_MACHINE(RAMIPS_MACH_DIR_300_B1, "DIR-300-B1", "D-Link DIR-300 B1", + dir_300b_init); + +MIPS_MACHINE(RAMIPS_MACH_DIR_600_B1, "DIR-600-B1", "D-Link DIR-600 B1", + dir_300b_init); + +MIPS_MACHINE(RAMIPS_MACH_DIR_600_B2, "DIR-600-B2", "D-Link DIR-600 B2", + dir_300b_init); + +MIPS_MACHINE(RAMIPS_MACH_DIR_615_D, "DIR-615-D", "D-Link DIR-615 D", + dir_300b_init); + +MIPS_MACHINE(RAMIPS_MACH_DIR_620_A1, "DIR-620-A1", "D-Link DIR-620 A1", + dir_620a1_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-dir-615-h1.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-dir-615-h1.c new file mode 100644 index 0000000000..dbfe4aa92f --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-dir-615-h1.c @@ -0,0 +1,112 @@ +/* + * D-Link DIR-615 H1 + * + * Copyright (C) 2012 Mikko Hissa + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define DIR_615_H1_GPIO_LED_WAN_AMBER 12 /* active low */ +#define DIR_615_H1_GPIO_LED_WAN_GREEN 13 /* active low */ +#define DIR_615_H1_GPIO_LED_WPS_BLUE 14 /* active low */ + +#define DIR_615_H1_GPIO_LED_STATUS_AMBER 7 +#define DIR_615_H1_GPIO_LED_STATUS_GREEN 9 + +#define DIR_615_H1_GPIO_BUTTON_RESET 10 /* active low */ +#define DIR_615_H1_GPIO_BUTTON_WPS 0 /* active low */ + +#define DIR_615_H1_KEYS_POLL_INTERVAL 20 +#define DIR_615_H1_KEYS_DEBOUNCE_INTERVAL (3 * DIR_615_H1_KEYS_POLL_INTERVAL) + +static struct gpio_led dir_615_h1_leds_gpio[] __initdata = { + { + .name = "d-link:amber:status", + .gpio = DIR_615_H1_GPIO_LED_STATUS_AMBER, + }, { + .name = "d-link:green:status", + .gpio = DIR_615_H1_GPIO_LED_STATUS_GREEN, + }, { + .name = "d-link:amber:wan", + .gpio = DIR_615_H1_GPIO_LED_WAN_AMBER, + .active_low = 1, + }, { + .name = "d-link:green:wan", + .gpio = DIR_615_H1_GPIO_LED_WAN_GREEN, + .active_low = 1, + }, { + .name = "d-link:blue:wps", + .gpio = DIR_615_H1_GPIO_LED_WPS_BLUE, + .active_low = 1, + } +}; + +static struct gpio_keys_button dir_615_h1_gpio_buttons[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DIR_615_H1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR_615_H1_GPIO_BUTTON_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DIR_615_H1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR_615_H1_GPIO_BUTTON_WPS, + .active_low = 1, + } +}; + +const struct flash_platform_data dir615h1_flash = { + .type = "mx25l3205d", +}; + +struct spi_board_info dir615h1_spi_slave_info[] __initdata = { + { + .modalias = "m25p80", + .platform_data = &dir615h1_flash, + .irq = -1, + .max_speed_hz = 10000000, + .bus_num = 0, + .chip_select = 0, + }, +}; + +static void __init dir615h1_init(void) +{ + rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); + rt305x_register_spi(dir615h1_spi_slave_info, + ARRAY_SIZE(dir615h1_spi_slave_info)); + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; + rt305x_register_ethernet(); + ramips_register_gpio_leds(-1, ARRAY_SIZE(dir_615_h1_leds_gpio), + dir_615_h1_leds_gpio); + ramips_register_gpio_buttons(-1, DIR_615_H1_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dir_615_h1_gpio_buttons), + dir_615_h1_gpio_buttons); + rt305x_register_wifi(); + rt305x_register_wdt(); +} + +MIPS_MACHINE(RAMIPS_MACH_DIR_615_H1, "DIR-615-H1", "D-Link DIR-615 H1", + dir615h1_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-esr-9753.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-esr-9753.c new file mode 100644 index 0000000000..d5f65df5ec --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-esr-9753.c @@ -0,0 +1,81 @@ +/* + * Senao / EnGenius ESR-9753 board support + * + * Copyright (C) 2011 Artur Wronowski + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define ESR_9753_GPIO_LED_POWER 8 +#define ESR_9753_GPIO_LED_WPS 14 + +#define ESR_9753_GPIO_BUTTON_WPS 0 /* active low */ +#define ESR_9753_GPIO_BUTTON_RESET 10 /* active low */ + +#define ESR_9753_KEYS_POLL_INTERVAL 20 +#define ESR_9753_KEYS_DEBOUNCE_INTERVAL (3 * ESR_9753_KEYS_POLL_INTERVAL) + +static struct gpio_led esr_9753_leds_gpio[] __initdata = { + { + .name = "esr-9753:orange:power", + .gpio = ESR_9753_GPIO_LED_POWER, + .active_low = 1, + }, { + .name = "esr-9753:orange:wps", + .gpio = ESR_9753_GPIO_LED_WPS, + .active_low = 1, + } +}; + +static struct gpio_keys_button esr_9753_gpio_buttons[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = ESR_9753_KEYS_DEBOUNCE_INTERVAL, + .gpio = ESR_9753_GPIO_BUTTON_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = ESR_9753_KEYS_DEBOUNCE_INTERVAL, + .gpio = ESR_9753_GPIO_BUTTON_WPS, + .active_low = 1, + } +}; + +static void __init esr_9753_init(void) +{ + rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); + + rt305x_register_flash(0); + + ramips_register_gpio_leds(-1, ARRAY_SIZE(esr_9753_leds_gpio), + esr_9753_leds_gpio); + + ramips_register_gpio_buttons(-1, ESR_9753_KEYS_POLL_INTERVAL, + ARRAY_SIZE(esr_9753_gpio_buttons), + esr_9753_gpio_buttons); + + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL; + rt305x_register_ethernet(); + rt305x_register_wifi(); + rt305x_register_wdt(); +} + +MIPS_MACHINE(RAMIPS_MACH_ESR_9753, "ESR-9753", "Senao / EnGenius ESR-9753", + esr_9753_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-f5d8235-v2.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-f5d8235-v2.c new file mode 100644 index 0000000000..073fc75a6e --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-f5d8235-v2.c @@ -0,0 +1,108 @@ +/* + * Belkin F5D8235 v2 board support + * + * Copyright (C) 2010 Roman Yeryomin + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define F5D8235_V2_GPIO_LED_INTERNET_BLUE 5 +#define F5D8235_V2_GPIO_LED_INTERNET_AMBER 6 +#define F5D8235_V2_GPIO_LED_MODEM_BLUE 11 +#define F5D8235_V2_GPIO_LED_MODEM_AMBER 8 +#define F5D8235_V2_GPIO_LED_ROUTER 9 +#define F5D8235_V2_GPIO_LED_STORAGE_BLUE 23 +#define F5D8235_V2_GPIO_LED_STORAGE_AMBER 22 +#define F5D8235_V2_GPIO_LED_SECURITY_BLUE 13 +#define F5D8235_V2_GPIO_LED_SECURITY_AMBER 12 + +static struct gpio_led f5d8235v2_leds_gpio[] __initdata = { + { + .name = "f5d8235v2:blue:internet", + .gpio = F5D8235_V2_GPIO_LED_INTERNET_BLUE, + .active_low = 1, + }, { + .name = "f5d8235v2:amber:internet", + .gpio = F5D8235_V2_GPIO_LED_INTERNET_AMBER, + .active_low = 1, + }, { + .name = "f5d8235v2:blue:modem", + .gpio = F5D8235_V2_GPIO_LED_MODEM_BLUE, + .active_low = 1, + }, { + .name = "f5d8235v2:amber:modem", + .gpio = F5D8235_V2_GPIO_LED_MODEM_AMBER, + .active_low = 1, + }, { + .name = "f5d8235v2:blue:router", + .gpio = F5D8235_V2_GPIO_LED_ROUTER, + .active_low = 1, + }, { + .name = "f5d8235v2:blue:storage", + .gpio = F5D8235_V2_GPIO_LED_STORAGE_BLUE, + .active_low = 1, + }, { + .name = "f5d8235v2:amber:storage", + .gpio = F5D8235_V2_GPIO_LED_STORAGE_AMBER, + .active_low = 1, + }, { + .name = "f5d8235v2:blue:security", + .gpio = F5D8235_V2_GPIO_LED_SECURITY_BLUE, + .active_low = 1, + }, { + .name = "f5d8235v2:amber:security", + .gpio = F5D8235_V2_GPIO_LED_SECURITY_AMBER, + .active_low = 1, + } +}; + +static struct rtl8366_platform_data f5d8235v2_switch_data = { + .gpio_sda = RT305X_GPIO_I2C_SD, + .gpio_sck = RT305X_GPIO_I2C_SCLK, +}; + +static struct platform_device f5d8235v2_switch = { + .name = RTL8366RB_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &f5d8235v2_switch_data, + } +}; + +static void __init f5d8235v2_init(void) +{ + rt305x_gpio_init((RT305X_GPIO_MODE_GPIO << + RT305X_GPIO_MODE_UART0_SHIFT) | + RT305X_GPIO_MODE_I2C | + RT305X_GPIO_MODE_SPI | + RT305X_GPIO_MODE_MDIO); + + rt305x_register_flash(0); + + ramips_register_gpio_leds(-1, ARRAY_SIZE(f5d8235v2_leds_gpio), + f5d8235v2_leds_gpio); + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_NONE; + rt305x_register_ethernet(); + platform_device_register(&f5d8235v2_switch); + rt305x_register_wifi(); + rt305x_register_wdt(); + rt305x_register_usb(); +} + +MIPS_MACHINE(RAMIPS_MACH_F5D8235_V2, "F5D8235_V2", "Belkin F5D8235 v2", + f5d8235v2_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-fonera20n.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-fonera20n.c new file mode 100644 index 0000000000..a433e40e91 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-fonera20n.c @@ -0,0 +1,87 @@ +/* + * La Fonera20N board support + * + * Copyright (C) 2009 John Crispin + * Copyright (C) 2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define FONERA20N_GPIO_BUTTON_RESET 12 +#define FONERA20N_GPIO_SWITCH 13 +#define FONERA20N_GPIO_LED_WIFI 7 +#define FONERA20N_GPIO_LED_POWER 9 +#define FONERA20N_GPIO_LED_USB 14 + +#define FONERA20N_KEYS_POLL_INTERVAL 20 +#define FONERA20N_KEYS_DEBOUNCE_INTERVAL (3 * FONERA20N_KEYS_POLL_INTERVAL) + +static struct gpio_led fonera20n_leds_gpio[] __initdata = { + { + .name = "fonera20n:orange:wifi", + .gpio = FONERA20N_GPIO_LED_WIFI, + .active_low = 1, + }, { + .name = "fonera20n:green:power", + .gpio = FONERA20N_GPIO_LED_POWER, + .active_low = 1, + }, { + .name = "fonera20n:orange:usb", + .gpio = FONERA20N_GPIO_LED_USB, + .active_low = 1, + } +}; + +static struct gpio_keys_button fonera20n_gpio_buttons[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = FONERA20N_KEYS_DEBOUNCE_INTERVAL, + .gpio = FONERA20N_GPIO_BUTTON_RESET, + .active_low = 1, + }, { + .desc = "switch", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = FONERA20N_KEYS_DEBOUNCE_INTERVAL, + .gpio = FONERA20N_GPIO_SWITCH, + .active_low = 1, + } +}; + +static void __init fonera20n_init(void) +{ + rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); + + rt305x_register_flash(0); + + ramips_register_gpio_leds(-1, ARRAY_SIZE(fonera20n_leds_gpio), + fonera20n_leds_gpio); + + ramips_register_gpio_buttons(-1, FONERA20N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(fonera20n_gpio_buttons), + fonera20n_gpio_buttons); + + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; + rt305x_register_ethernet(); + rt305x_register_wifi(); + rt305x_register_wdt(); + rt305x_register_usb(); +} + +MIPS_MACHINE(RAMIPS_MACH_FONERA20N, "FONERA20N", "La Fonera 2.0N", + fonera20n_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-freestation5.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-freestation5.c new file mode 100644 index 0000000000..b868244cca --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-freestation5.c @@ -0,0 +1,34 @@ +/* + * ARC FreeStation2/5 board support + * + * Copyright (C) 2009 John Crispin + * Copyright (C) 2010 Gabor Juhos + * Copyright (C) 2012 Pau Escrich + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include +#include + +#include "devices.h" + +static void __init freestation5_init(void) +{ + rt305x_register_flash(0); + + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL; + rt305x_register_ethernet(); + rt305x_register_wifi(); + rt305x_register_wdt(); + rt305x_register_usb(); +} + +MIPS_MACHINE(RAMIPS_MACH_FREESTATION5, "FREESTATION5", "ARC FreeStation5", + freestation5_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-hw550-3g.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-hw550-3g.c new file mode 100644 index 0000000000..b274b917da --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-hw550-3g.c @@ -0,0 +1,105 @@ +/* + * Aztech HW550-3G board support + * + * Copyright (C) 2011 Layne Edwards + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define HW550_3G_GPIO_LED_USB 8 +#define HW550_3G_GPIO_LED_3G 11 +#define HW550_3G_GPIO_LED_STATUS 12 +#define HW550_3G_GPIO_LED_WPS 14 + +#define HW550_3G_GPIO_BUTTON_RESET 10 +#define HW550_3G_GPIO_BUTTON_CONNECT 7 +#define HW550_3G_GPIO_BUTTON_WPS 0 + +#define HW550_3G_KEYS_POLL_INTERVAL 20 +#define HW550_3G_KEYS_DEBOUNCE_INTERVAL (3 * HW550_3G_KEYS_POLL_INTERVAL) + +static struct gpio_led hw550_3g_leds_gpio[] __initdata = { + { + .name = "hw550-3g:green:usb", + .gpio = HW550_3G_GPIO_LED_USB, + .active_low = 1, + }, { + .name = "hw550-3g:green:3g", + .gpio = HW550_3G_GPIO_LED_3G, + .active_low = 1, + }, { + .name = "hw550-3g:green:status", + .gpio = HW550_3G_GPIO_LED_STATUS, + .active_low = 1, + }, { + .name = "hw550-3g:green:wps", + .gpio = HW550_3G_GPIO_LED_WPS, + .active_low = 1, + } +}; + +static struct gpio_keys_button hw550_3g_gpio_buttons[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = HW550_3G_KEYS_DEBOUNCE_INTERVAL, + .gpio = HW550_3G_GPIO_BUTTON_RESET, + .active_low = 1, + }, { + .desc = "connect", + .type = EV_KEY, + .code = KEY_CONNECT, + .debounce_interval = HW550_3G_KEYS_DEBOUNCE_INTERVAL, + .gpio = HW550_3G_GPIO_BUTTON_CONNECT, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = HW550_3G_KEYS_DEBOUNCE_INTERVAL, + .gpio = HW550_3G_GPIO_BUTTON_WPS, + .active_low = 1, + } +}; + +#define HW550_3G_GPIO_MODE \ + ((RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT) | \ + RT305X_GPIO_MODE_MDIO) + +static void __init hw550_3g_init(void) +{ + rt305x_gpio_init(HW550_3G_GPIO_MODE); + + rt305x_register_flash(0); + + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL; + rt305x_register_ethernet(); + ramips_register_gpio_leds(-1, ARRAY_SIZE(hw550_3g_leds_gpio), + hw550_3g_leds_gpio); + ramips_register_gpio_buttons(-1, HW550_3G_KEYS_POLL_INTERVAL, + ARRAY_SIZE(hw550_3g_gpio_buttons), + hw550_3g_gpio_buttons); + rt305x_register_wifi(); + rt305x_register_wdt(); + rt305x_register_usb(); +} + +MIPS_MACHINE(RAMIPS_MACH_HW550_3G, "HW550-3G", "Aztech HW550-3G", + hw550_3g_init); + +MIPS_MACHINE(RAMIPS_MACH_ALL0239_3G, "ALL0239-3G", "Allnet ALL0239-3G", + hw550_3g_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-mofi3500-3gn.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-mofi3500-3gn.c new file mode 100644 index 0000000000..38d217a4ff --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-mofi3500-3gn.c @@ -0,0 +1,102 @@ +/* + * MoFi Network MOFI3500-3GN board support + * + * Copyright (C) 2011 Layne Edwards + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define MOFI3500_3GN_GPIO_LED_USB 8 +#define MOFI3500_3GN_GPIO_LED_3G 11 +#define MOFI3500_3GN_GPIO_LED_STATUS 12 +#define MOFI3500_3GN_GPIO_LED_WPS 14 + +#define MOFI3500_3GN_GPIO_BUTTON_RESET 10 +#define MOFI3500_3GN_GPIO_BUTTON_CONNECT 7 +#define MOFI3500_3GN_GPIO_BUTTON_WPS 0 + +#define MOFI3500_3GN_KEYS_POLL_INTERVAL 20 +#define MOFI3500_3GN_KEYS_DEBOUNCE_INTERVAL (3 * MOFI3500_3GN_KEYS_POLL_INTERVAL) + +static struct gpio_led mofi3500_3gn_leds_gpio[] __initdata = { + { + .name = "mofi3500-3gn:green:usb", + .gpio = MOFI3500_3GN_GPIO_LED_USB, + .active_low = 1, + }, { + .name = "mofi3500-3gn:green:3g", + .gpio = MOFI3500_3GN_GPIO_LED_3G, + .active_low = 1, + }, { + .name = "mofi3500-3gn:green:status", + .gpio = MOFI3500_3GN_GPIO_LED_STATUS, + .active_low = 1, + }, { + .name = "mofi3500-3gn:green:wps", + .gpio = MOFI3500_3GN_GPIO_LED_WPS, + .active_low = 1, + } +}; + +static struct gpio_keys_button mofi3500_3gn_gpio_buttons[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = MOFI3500_3GN_KEYS_DEBOUNCE_INTERVAL, + .gpio = MOFI3500_3GN_GPIO_BUTTON_RESET, + .active_low = 1, + }, { + .desc = "connect", + .type = EV_KEY, + .code = KEY_CONNECT, + .debounce_interval = MOFI3500_3GN_KEYS_DEBOUNCE_INTERVAL, + .gpio = MOFI3500_3GN_GPIO_BUTTON_CONNECT, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = MOFI3500_3GN_KEYS_DEBOUNCE_INTERVAL, + .gpio = MOFI3500_3GN_GPIO_BUTTON_WPS, + .active_low = 1, + } +}; + +#define MOFI3500_3GN_GPIO_MODE \ + ((RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT) | \ + RT305X_GPIO_MODE_MDIO) + +static void __init mofi3500_3gn_init(void) +{ + rt305x_gpio_init(MOFI3500_3GN_GPIO_MODE); + + rt305x_register_flash(0); + + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; + rt305x_register_ethernet(); + ramips_register_gpio_leds(-1, ARRAY_SIZE(mofi3500_3gn_leds_gpio), + mofi3500_3gn_leds_gpio); + ramips_register_gpio_buttons(-1, MOFI3500_3GN_KEYS_POLL_INTERVAL, + ARRAY_SIZE(mofi3500_3gn_gpio_buttons), + mofi3500_3gn_gpio_buttons); + rt305x_register_wifi(); + rt305x_register_wdt(); + rt305x_register_usb(); +} + +MIPS_MACHINE(RAMIPS_MACH_MOFI3500_3GN, "MOFI3500-3GN", "MoFi Network MOFI3500-3GN", + mofi3500_3gn_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-mzk-w300nh2.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-mzk-w300nh2.c new file mode 100644 index 0000000000..01cabbc0bf --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-mzk-w300nh2.c @@ -0,0 +1,94 @@ +/* + * Planex MZK-W300NH2 board support + * + * Copyright (C) 2012 Samir Ibradžić + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define MZKW300NH2_GPIO_BUTTON_RESET 0 /* active low */ +#define MZKW300NH2_GPIO_BUTTON_WPS 12 /* active low */ +#define MZKW300NH2_GPIO_SWITCH_MODE_RT 13 /* active low */ + +#define MZKW300NH2_GPIO_LED_POWER 9 +#define MZKW300NH2_GPIO_LED_WLAN 14 +#define MZKW300NH2_GPIO_LED_WPS 11 + +#define MZKW300NH2_KEYS_POLL_INTERVAL 20 +#define MZKW300NH2_KEYS_DEBOUNCE_INTERVAL (3 * MZKW300NH2_KEYS_POLL_INTERVAL) + +static struct gpio_led mzkw300nh2_leds_gpio[] __initdata = { + { + .name = "mzkw300nh2:green:power", + .gpio = MZKW300NH2_GPIO_LED_POWER, + .active_low = 1, + }, { + .name = "mzkw300nh2:amber:wlan", + .gpio = MZKW300NH2_GPIO_LED_WLAN, + .active_low = 1, + }, { + .name = "mzkw300nh2:amber:wps", + .gpio = MZKW300NH2_GPIO_LED_WPS, + .active_low = 1, + } +}; + +static struct gpio_keys_button mzkw300nh2_gpio_buttons[] __initdata = { + { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = MZKW300NH2_KEYS_DEBOUNCE_INTERVAL, + .gpio = MZKW300NH2_GPIO_BUTTON_WPS, + .active_low = 1, + }, { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = MZKW300NH2_KEYS_DEBOUNCE_INTERVAL, + .gpio = MZKW300NH2_GPIO_BUTTON_RESET, + .active_low = 1, + }, { + .desc = "rt", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = MZKW300NH2_KEYS_DEBOUNCE_INTERVAL, + .gpio = MZKW300NH2_GPIO_SWITCH_MODE_RT, + .active_low = 1, + } +}; + +static void __init mzkw300nh2_init(void) +{ + rt305x_gpio_init(RT305X_GPIO_MODE_UART0(RT305X_GPIO_MODE_GPIO) | + RT305X_GPIO_MODE_I2C | + RT305X_GPIO_MODE_SPI | + RT305X_GPIO_MODE_JTAG); + + rt305x_register_flash(0); + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; + rt305x_register_ethernet(); + ramips_register_gpio_leds(-1, ARRAY_SIZE(mzkw300nh2_leds_gpio), + mzkw300nh2_leds_gpio); + ramips_register_gpio_buttons(-1, MZKW300NH2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(mzkw300nh2_gpio_buttons), + mzkw300nh2_gpio_buttons); + rt305x_register_wifi(); + rt305x_register_wdt(); +} + +MIPS_MACHINE(RAMIPS_MACH_MZKW300NH2, "MZK-W300NH2", "Planex MZK-W300NH2", + mzkw300nh2_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-nbg-419n.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-nbg-419n.c new file mode 100644 index 0000000000..856520368f --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-nbg-419n.c @@ -0,0 +1,78 @@ +/* + * ZyXEL NBG-419N board support + * + * Copyright (C) 2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define NBG_419N_GPIO_LED_POWER 9 +#define NBG_419N_GPIO_LED_WPS 14 + +#define NBG_419N_GPIO_BUTTON_WPS 0 /* active low */ +#define NBG_419N_GPIO_BUTTON_RESET 10 /* active low */ + +#define NBG_419N_KEYS_POLL_INTERVAL 20 +#define NBG_419N_KEYS_DEBOUNCE_INTERVAL (3 * NBG_419N_KEYS_POLL_INTERVAL) + +static struct gpio_led nbg_419n_leds_gpio[] __initdata = { + { + .name = "nbg-419n:green:power", + .gpio = NBG_419N_GPIO_LED_POWER, + .active_low = 1, + }, { + .name = "nbg-419n:green:wps", + .gpio = NBG_419N_GPIO_LED_WPS, + .active_low = 1, + } +}; + +static struct gpio_keys_button nbg_419n_gpio_buttons[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = NBG_419N_KEYS_DEBOUNCE_INTERVAL, + .gpio = NBG_419N_GPIO_BUTTON_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = NBG_419N_KEYS_DEBOUNCE_INTERVAL, + .gpio = NBG_419N_GPIO_BUTTON_WPS, + .active_low = 1, + } +}; + +static void __init nbg_419n_init(void) +{ + rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); + + rt305x_register_flash(0); + + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; + rt305x_register_ethernet(); + ramips_register_gpio_leds(-1, ARRAY_SIZE(nbg_419n_leds_gpio), + nbg_419n_leds_gpio); + ramips_register_gpio_buttons(-1, NBG_419N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(nbg_419n_gpio_buttons), + nbg_419n_gpio_buttons); + rt305x_register_wifi(); + rt305x_register_wdt(); +} + +MIPS_MACHINE(RAMIPS_MACH_NBG_419N, "NBG-419N", "ZyXEL NBG-419N", nbg_419n_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-nw718.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-nw718.c new file mode 100644 index 0000000000..3c9d047908 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-nw718.c @@ -0,0 +1,95 @@ +/* + * Netcore NW718 board support + * + * Copyright (C) 2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define NW718_GPIO_LED_USB 8 +#define NW718_GPIO_LED_CPU 13 +#define NW718_GPIO_LED_WPS 14 + +#define NW718_GPIO_BUTTON_WPS 0 +#define NW718_GPIO_BUTTON_RESET 10 + +#define NW718_GPIO_SPI_CS0 3 + +#define NW718_KEYS_POLL_INTERVAL 20 +#define NW718_KEYS_DEBOUNCE_INTERVAL (3 * NW718_KEYS_POLL_INTERVAL) + +static struct gpio_led nw718_leds_gpio[] __initdata = { + { + .name = "nw718:amber:cpu", + .gpio = NW718_GPIO_LED_CPU, + .active_low = 1, + }, { + .name = "nw718:amber:usb", + .gpio = NW718_GPIO_LED_USB, + .active_low = 1, + }, { + .name = "nw718:amber:wps", + .gpio = NW718_GPIO_LED_WPS, + .active_low = 1, + } +}; + +static struct gpio_keys_button nw718_gpio_buttons[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = NW718_KEYS_DEBOUNCE_INTERVAL, + .gpio = NW718_GPIO_BUTTON_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = NW718_KEYS_DEBOUNCE_INTERVAL, + .gpio = NW718_GPIO_BUTTON_WPS, + .active_low = 1, + } +}; + +static struct spi_board_info nw718_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "m25p80", + } +}; + +static void __init nw718_init(void) +{ + rt305x_gpio_init(RT305X_GPIO_MODE_I2C | + RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); + + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; + rt305x_register_ethernet(); + ramips_register_gpio_leds(-1, ARRAY_SIZE(nw718_leds_gpio), + nw718_leds_gpio); + ramips_register_gpio_buttons(-1, NW718_KEYS_POLL_INTERVAL, + ARRAY_SIZE(nw718_gpio_buttons), + nw718_gpio_buttons); + rt305x_register_wifi(); + rt305x_register_wdt(); + rt305x_register_spi(nw718_spi_info, ARRAY_SIZE(nw718_spi_info)); + rt305x_register_usb(); +} + +MIPS_MACHINE(RAMIPS_MACH_WHR_G300N, "NW718", "Netcore NW718", nw718_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-omni-emb.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-omni-emb.c new file mode 100644 index 0000000000..930ac3028f --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-omni-emb.c @@ -0,0 +1,74 @@ +/* + * Omnima MiniEMBWiFi board support + * + * Copyright (C) 2011 Johnathan Boyce + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define OMNI_EMB_GPIO_BUTTON_RESET 12 /* active low */ + +#define OMNI_EMB_KEYS_POLL_INTERVAL 20 +#define OMNI_EMB_KEYS_DEBOUNCE_INTERVAL (3 * OMNI_EMB_KEYS_POLL_INTERVAL) + +#define OMNI_EMB_GPIO_LED_STATUS 9 +#define OMNI_EMB_GPIO_LED_WLAN 14 + +static struct gpio_led omni_emb_leds_gpio[] __initdata = { + { + .name = "emb:green:status", + .gpio = OMNI_EMB_GPIO_LED_STATUS, + .active_low = 1, + }, { + .name = "emb:green:wlan", + .gpio = OMNI_EMB_GPIO_LED_WLAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button omni_emb_gpio_buttons[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = OMNI_EMB_KEYS_DEBOUNCE_INTERVAL, + .gpio = OMNI_EMB_GPIO_BUTTON_RESET, + .active_low = 1, + } +}; + +static void __init omni_emb_init(void) +{ + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; + + rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); + + ramips_register_gpio_leds(-1, ARRAY_SIZE(omni_emb_leds_gpio), + omni_emb_leds_gpio); + ramips_register_gpio_buttons(-1, OMNI_EMB_KEYS_POLL_INTERVAL, + ARRAY_SIZE(omni_emb_gpio_buttons), + omni_emb_gpio_buttons); + + rt305x_register_flash(0); + rt305x_register_ethernet(); + rt305x_register_wifi(); + rt305x_register_wdt(); + rt305x_register_usb(); +} + +MIPS_MACHINE(RAMIPS_MACH_OMNI_EMB, "OMNI-EMB", "Omnima MiniEMBWiFi", + omni_emb_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-psr-680w.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-psr-680w.c new file mode 100644 index 0000000000..a6d10f7cbe --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-psr-680w.c @@ -0,0 +1,73 @@ +/* + * Petatel PSR-680W Wireless 3G Router support + * + * Copyright (C) 2012 Dmitry Shmygov + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define PSR_680W_GPIO_BUTTON_RESET 0 /* active low */ + +#define PSR_680W_GPIO_LED_STATUS 19 + +#define PSR_680W_KEYS_POLL_INTERVAL 20 +#define PSR_680W_KEYS_DEBOUNCE_INTERVAL (3 * PSR_680W_KEYS_POLL_INTERVAL) + + +static struct gpio_led psr_680w_leds_gpio[] __initdata = { + { + .name = "psr-680w:red:wan", + .gpio = PSR_680W_GPIO_LED_STATUS, + .active_low = 1, + } +}; + +static struct gpio_keys_button psr_680w_gpio_buttons[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = PSR_680W_KEYS_DEBOUNCE_INTERVAL, + .gpio = PSR_680W_GPIO_BUTTON_RESET, + .active_low = 1, + } +}; + +static void __init psr_680w_init(void) +{ + rt305x_gpio_init((RT305X_GPIO_MODE_I2S_UARTF << RT305X_GPIO_MODE_UART0_SHIFT) | + RT305X_GPIO_MODE_SPI | + RT305X_GPIO_MODE_JTAG | + RT305X_GPIO_MODE_MDIO | + RT305X_GPIO_MODE_RGMII); + + rt305x_register_flash(0); + + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL; + rt305x_register_ethernet(); + ramips_register_gpio_leds(-1, ARRAY_SIZE(psr_680w_leds_gpio), + psr_680w_leds_gpio); + ramips_register_gpio_buttons(-1, PSR_680W_KEYS_POLL_INTERVAL, + ARRAY_SIZE(psr_680w_gpio_buttons), + psr_680w_gpio_buttons); + rt305x_register_wifi(); + rt305x_register_wdt(); + rt305x_register_usb(); +} + +MIPS_MACHINE(RAMIPS_MACH_PSR_680W, "PSR-680W", + "Petatel PSR-680W Wireless 3G Router", + psr_680w_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-pwh2004.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-pwh2004.c new file mode 100644 index 0000000000..5baf32a49a --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-pwh2004.c @@ -0,0 +1,69 @@ +/* + * Prolink PWH2004 support (or Abocom WR5205) + * + * Copyright (C) 2010 Esa Hyytia + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define PWH2004_GPIO_BUTTON_WPS 12 +#define PWH2004_GPIO_LED_POWER 9 +#define PWH2004_GPIO_LED_WIFI 14 +#define PWH2004_KEYS_POLL_INTERVAL 20 +#define PWH2004_KEYS_DEBOUNCE_INTERVAL (3 * PWH2004_KEYS_POLL_INTERVAL) + +static struct gpio_led pwh2004_leds_gpio[] __initdata = { + { + .name = "pwh2004:red:wifi", + .gpio = PWH2004_GPIO_LED_WIFI, + .active_low = 1, + }, { + .name = "pwh2004:green:power", + .gpio = PWH2004_GPIO_LED_POWER, + .active_low = 1, + } +}; + +static struct gpio_keys_button pwh2004_gpio_buttons[] __initdata = { + { + .desc = "wps", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = PWH2004_KEYS_DEBOUNCE_INTERVAL, + .gpio = PWH2004_GPIO_BUTTON_WPS, + .active_low = 1, + } +}; + +static void __init pwh2004_init(void) +{ + rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); + + rt305x_register_flash(0); + + ramips_register_gpio_leds(-1, ARRAY_SIZE(pwh2004_leds_gpio), + pwh2004_leds_gpio); + ramips_register_gpio_buttons(-1, PWH2004_KEYS_POLL_INTERVAL, + ARRAY_SIZE(pwh2004_gpio_buttons), + pwh2004_gpio_buttons); + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; + rt305x_register_ethernet(); + rt305x_register_wifi(); + rt305x_register_wdt(); +} + +MIPS_MACHINE(RAMIPS_MACH_PWH2004, "PWH2004", "Prolink PWH2004", + pwh2004_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-rt-g32-revb.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-rt-g32-revb.c new file mode 100644 index 0000000000..2f0f710874 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-rt-g32-revb.c @@ -0,0 +1,78 @@ +/* + * Asus RT-G32 rev B board support + * + * Copyright (C) 2011 Sergiy + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "devices.h" + +#define RT_G32B_GPIO_BUTTON_WPS 0 /* active low */ +#define RT_G32B_GPIO_BUTTON_RESET 10 /* active low */ + +#define RT_G32B_KEYS_POLL_INTERVAL 20 +#define RT_G32B_KEYS_DEBOUNCE_INTERVAL (3 * RT_G32B_KEYS_POLL_INTERVAL) + +const struct flash_platform_data rt_g32b_flash = { + .type = "mx25l3205d", +}; + +struct spi_board_info __initdata rt_g32b_spi_slave_info[] = { + { + .modalias = "m25p80", + .platform_data = &rt_g32b_flash, + .irq = -1, + .max_speed_hz = 10000000, + .bus_num = 0, + .chip_select = 0, + }, +}; + +static struct gpio_keys_button rt_g32b_gpio_buttons[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = RT_G32B_KEYS_DEBOUNCE_INTERVAL, + .gpio = RT_G32B_GPIO_BUTTON_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = RT_G32B_KEYS_DEBOUNCE_INTERVAL, + .gpio = RT_G32B_GPIO_BUTTON_WPS, + .active_low = 1, + } +}; + +static void __init rt_g32b_init(void) +{ + rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); + rt305x_register_spi(rt_g32b_spi_slave_info, + ARRAY_SIZE(rt_g32b_spi_slave_info)); + + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; + rt305x_register_ethernet(); + ramips_register_gpio_buttons(-1, RT_G32B_KEYS_POLL_INTERVAL, + ARRAY_SIZE(rt_g32b_gpio_buttons), + rt_g32b_gpio_buttons); + rt305x_register_wifi(); + rt305x_register_wdt(); +} + +MIPS_MACHINE(RAMIPS_MACH_RT_G32_B1, "RT-G32-B1", "Asus RT-G32 B1", + rt_g32b_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-rt-n10-plus.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-rt-n10-plus.c new file mode 100644 index 0000000000..5b496d4eac --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-rt-n10-plus.c @@ -0,0 +1,74 @@ +/* + * ASUS RT-N10+ board support + * + * Copyright (C) 2009-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define RT_N10_PLUS_GPIO_LED_WPS 14 + +#define RT_N10_PLUS_GPIO_BUTTON_WPS 0 /* active low */ +#define RT_N10_PLUS_GPIO_BUTTON_RESET 10 /* active low */ + +#define RT_N10_PLUS_KEYS_POLL_INTERVAL 20 +#define RT_N10_PLUS_KEYS_DEBOUNCE_INTERVAL (3 * RT_N10_PLUS_KEYS_POLL_INTERVAL) + +static struct gpio_led rt_n10_plus_leds_gpio[] __initdata = { + { + .name = "asus:green:wps", + .gpio = RT_N10_PLUS_GPIO_LED_WPS, + .active_low = 1, + } +}; + +static struct gpio_keys_button rt_n10_plus_gpio_buttons[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = RT_N10_PLUS_KEYS_DEBOUNCE_INTERVAL, + .gpio = RT_N10_PLUS_GPIO_BUTTON_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = RT_N10_PLUS_KEYS_DEBOUNCE_INTERVAL, + .gpio = RT_N10_PLUS_GPIO_BUTTON_WPS, + .active_low = 1, + } +}; + +static void __init rt_n10_plus_init(void) +{ + rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); + + rt305x_register_flash(0); + + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL; + rt305x_register_ethernet(); + ramips_register_gpio_leds(-1, ARRAY_SIZE(rt_n10_plus_leds_gpio), + rt_n10_plus_leds_gpio); + ramips_register_gpio_buttons(-1, RT_N10_PLUS_KEYS_POLL_INTERVAL, + ARRAY_SIZE(rt_n10_plus_gpio_buttons), + rt_n10_plus_gpio_buttons); + rt305x_register_wifi(); + rt305x_register_wdt(); +} + +MIPS_MACHINE(RAMIPS_MACH_RT_N10_PLUS, "RT-N10-PLUS", "Asus RT-N10+", + rt_n10_plus_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-rt-n13u.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-rt-n13u.c new file mode 100644 index 0000000000..cae857abd4 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-rt-n13u.c @@ -0,0 +1,83 @@ +/* + * ASUS RT-N13U board support + * + * Copyright (C) 2012 lintel + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define RT_N13U_GPIO_BUTTON_RESET 10 +#define RT_N13U_GPIO_BUTTON_WPS 0 + +#define RT_N13U_GPIO_LED_POWER 7 +#define RT_N13U_GPIO_LED_WIFI 8 + + +#define RT_N13U_BUTTONS_POLL_INTERVAL 10 +#define RT_N13U_BUTTONS_DEBOUNCE_INTERVAL (3 * RT_N13U_BUTTONS_POLL_INTERVAL) + +static struct gpio_led rt_n13u_leds_gpio[] __initdata = { + { + .name = "rt-n13u:power", + .gpio = RT_N13U_GPIO_LED_POWER, + .active_low = 1, + }, { + .name = "rt-n13u:wifi", + .gpio = RT_N13U_GPIO_LED_WIFI, + .active_low = 1, + } +}; + +static struct gpio_keys_button rt_n13u_gpio_buttons[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = RT_N13U_BUTTONS_DEBOUNCE_INTERVAL, + .gpio = RT_N13U_GPIO_BUTTON_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = RT_N13U_BUTTONS_DEBOUNCE_INTERVAL, + .gpio = RT_N13U_GPIO_BUTTON_WPS, + .active_low = 1, + }, +}; + +static void __init rt_n13u_init(void) +{ + rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); + + rt305x_register_flash(0); + + ramips_register_gpio_leds(-1, ARRAY_SIZE(rt_n13u_leds_gpio), + rt_n13u_leds_gpio); + + ramips_register_gpio_buttons(-1, RT_N13U_BUTTONS_POLL_INTERVAL, + ARRAY_SIZE(rt_n13u_gpio_buttons), + rt_n13u_gpio_buttons); + + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; + rt305x_register_ethernet(); + rt305x_register_wifi(); + rt305x_register_wdt(); + rt305x_register_usb(); +} + +MIPS_MACHINE(RAMIPS_MACH_RT_N13U, "RT-N13U", "Asus RT-N13U", + rt_n13u_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-sl-r7205.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-sl-r7205.c new file mode 100644 index 0000000000..31f002c9aa --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-sl-r7205.c @@ -0,0 +1,76 @@ +/* + * Skyline SL-R7205 Wireless 3G Router support + * + * Copyright (C) 2012 Haipoh Teoh + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define SL_R7205_GPIO_BUTTON_WPS 0 +#define SL_R7205_GPIO_BUTTON_RESET 10 /* active low */ + +#define SL_R7205_GPIO_LED_WIFI 7 + +#define SL_R7205_KEYS_POLL_INTERVAL 20 +#define SL_R7205_KEYS_DEBOUNCE_INTERVAL (3 * SL_R7205_KEYS_POLL_INTERVAL) + +static struct gpio_led sl_r7205_leds_gpio[] __initdata = { + { + .name = "sl-r7205:green:wifi", + .gpio = SL_R7205_GPIO_LED_WIFI, + .active_low = 1, + } +}; + +static struct gpio_keys_button sl_r7205_gpio_buttons[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = SL_R7205_KEYS_DEBOUNCE_INTERVAL, + .gpio = SL_R7205_GPIO_BUTTON_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = SL_R7205_KEYS_DEBOUNCE_INTERVAL, + .gpio = SL_R7205_GPIO_BUTTON_WPS, + .active_low = 1, + } +}; + +static void __init sl_r7205_init(void) +{ + rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); + + rt305x_register_flash(0); + + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL; + rt305x_register_ethernet(); + ramips_register_gpio_leds(-1, ARRAY_SIZE(sl_r7205_leds_gpio), + sl_r7205_leds_gpio); + ramips_register_gpio_buttons(-1, SL_R7205_KEYS_POLL_INTERVAL, + ARRAY_SIZE(sl_r7205_gpio_buttons), + sl_r7205_gpio_buttons); + rt305x_register_wifi(); + rt305x_register_wdt(); + rt305x_register_usb(); +} + +MIPS_MACHINE(RAMIPS_MACH_SL_R7205, "SL-R7205", + "Skyline SL-R7205 Wireless 3G Router", + sl_r7205_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-ur-326n4g.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-ur-326n4g.c new file mode 100644 index 0000000000..a5296941a1 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-ur-326n4g.c @@ -0,0 +1,102 @@ +/* + * UR-326N4G board support + * + * Copyright (C) 2013 Dmitry Lebedev + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + + +#define UR_326N4G_GPIO_LED_3G 9 +#define UR_326N4G_GPIO_LED_GATEWAY 11 +#define UR_326N4G_GPIO_LED_AP 12 +#define UR_326N4G_GPIO_LED_STATION 13 +#define UR_326N4G_GPIO_LED_WPS 14 + +#define UR_326N4G_GPIO_BUTTON_RESET 10 +#define UR_326N4G_GPIO_BUTTON_CONNECT 7 +#define UR_326N4G_GPIO_BUTTON_WPS 0 +#define UR_326N4G_GPIO_BUTTON_WPS2 8 + +#define UR_326N4G_KEYS_POLL_INTERVAL 20 +#define UR_326N4G_KEYS_DEBOUNCE_INTERVAL (3 * UR_326N4G_KEYS_POLL_INTERVAL) + +static struct gpio_led UR_326N4G_leds_gpio[] __initdata = { + { + .name = "ur326:green:3g", + .gpio = UR_326N4G_GPIO_LED_3G, + .active_low = 1, + }, { + .name = "ur326:green:gateway", + .gpio = UR_326N4G_GPIO_LED_GATEWAY, + .active_low = 1, + }, { + .name = "ur326:green:ap", + .gpio = UR_326N4G_GPIO_LED_AP, + .active_low = 1, + }, { + .name = "ur326:green:wps", + .gpio = UR_326N4G_GPIO_LED_WPS, + .active_low = 1, + }, { + .name = "ur326:green:station", + .gpio = UR_326N4G_GPIO_LED_STATION, + .active_low = 1, + } +}; + +static struct gpio_keys_button UR_326N4G_gpio_buttons[] __initdata = { + { + .desc = "reset_wps", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = UR_326N4G_KEYS_DEBOUNCE_INTERVAL, + .gpio = UR_326N4G_GPIO_BUTTON_RESET, + .active_low = 1, + }, { + .desc = "mode", + .type = EV_KEY, + .code = KEY_M, + .debounce_interval = UR_326N4G_KEYS_DEBOUNCE_INTERVAL, + .gpio = UR_326N4G_GPIO_BUTTON_CONNECT, + .active_low = 1, + } +}; + +#define UR_326N4G_GPIO_MODE \ + ((RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT) | \ + RT305X_GPIO_MODE_MDIO) + +static void __init UR_326N4G_init(void) +{ + rt305x_gpio_init(UR_326N4G_GPIO_MODE); + + rt305x_register_flash(0); + + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; + rt305x_register_ethernet(); + ramips_register_gpio_leds(-1, ARRAY_SIZE(UR_326N4G_leds_gpio), + UR_326N4G_leds_gpio); + ramips_register_gpio_buttons(-1, UR_326N4G_KEYS_POLL_INTERVAL, + ARRAY_SIZE(UR_326N4G_gpio_buttons), + UR_326N4G_gpio_buttons); + rt305x_register_wifi(); + rt305x_register_wdt(); + rt305x_register_usb(); +} + +MIPS_MACHINE(RAMIPS_MACH_UR_326N4G, "UR-326N4G", "UR-326N4G Wireless N router", + UR_326N4G_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-ur-336un.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-ur-336un.c new file mode 100644 index 0000000000..0ff264957a --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-ur-336un.c @@ -0,0 +1,92 @@ +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + + +#define UR_336UN_GPIO_LED_3G 9 +#define UR_336UN_GPIO_LED_GATEWAY 11 +#define UR_336UN_GPIO_LED_AP 12 +#define UR_336UN_GPIO_LED_STATION 13 +#define UR_336UN_GPIO_LED_WPS 14 + +#define UR_336UN_GPIO_BUTTON_RESET 10 +#define UR_336UN_GPIO_BUTTON_CONNECT 7 +#define UR_336UN_GPIO_BUTTON_WPS 0 +#define UR_336UN_GPIO_BUTTON_WPS2 8 + +#define UR_336UN_KEYS_POLL_INTERVAL 20 +#define UR_336UN_KEYS_DEBOUNCE_INTERVAL (3 * UR_336UN_KEYS_POLL_INTERVAL) + +static struct gpio_led UR_336UN_leds_gpio[] __initdata = { + { + .name = "ur336:green:3g", + .gpio = UR_336UN_GPIO_LED_3G, + .active_low = 1, + }, { + .name = "ur336:green:gateway", + .gpio = UR_336UN_GPIO_LED_GATEWAY, + .active_low = 1, + }, { + .name = "ur336:green:ap", + .gpio = UR_336UN_GPIO_LED_AP, + .active_low = 1, + }, { + .name = "ur336:green:wps", + .gpio = UR_336UN_GPIO_LED_WPS, + .active_low = 1, + }, { + .name = "ur336:green:station", + .gpio = UR_336UN_GPIO_LED_STATION, + .active_low = 1, + } +}; + +static struct gpio_keys_button UR_336UN_gpio_buttons[] __initdata = { + { + .desc = "reset_wps", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = UR_336UN_KEYS_DEBOUNCE_INTERVAL, + .gpio = UR_336UN_GPIO_BUTTON_RESET, + .active_low = 1, + }, { + .desc = "mode", + .type = EV_KEY, + .code = KEY_M, + .debounce_interval = UR_336UN_KEYS_DEBOUNCE_INTERVAL, + .gpio = UR_336UN_GPIO_BUTTON_CONNECT, + .active_low = 1, + } +}; + +#define UR_336UN_GPIO_MODE \ + ((RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT) | \ + RT305X_GPIO_MODE_MDIO) + +static void __init UR_336UN_init(void) +{ + rt305x_gpio_init(UR_336UN_GPIO_MODE); + + rt305x_register_flash(0); + + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; + rt305x_register_ethernet(); + ramips_register_gpio_leds(-1, ARRAY_SIZE(UR_336UN_leds_gpio), + UR_336UN_leds_gpio); + ramips_register_gpio_buttons(-1, UR_336UN_KEYS_POLL_INTERVAL, + ARRAY_SIZE(UR_336UN_gpio_buttons), + UR_336UN_gpio_buttons); + rt305x_register_wifi(); + rt305x_register_wdt(); + rt305x_register_usb(); +} + +MIPS_MACHINE(RAMIPS_MACH_UR_336UN, "UR-336UN", "UR-336UN Wireless N router", + UR_336UN_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-v22rw-2x2.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-v22rw-2x2.c new file mode 100644 index 0000000000..7f43dabdc4 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-v22rw-2x2.c @@ -0,0 +1,79 @@ +/* + * Ralink AP-RT3052-V22RW-2X2 board support + * + * Copyright (C) 2009-2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define V22RW_2X2_GPIO_BUTTON_WPS 0 +#define V22RW_2X2_GPIO_BUTTON_SWRST 10 +#define V22RW_2X2_GPIO_LED_SECURITY 13 +#define V22RW_2X2_GPIO_LED_WPS 14 + +#define V22RW_2X2_KEYS_POLL_INTERVAL 20 +#define V22RW_2X2_KEYS_DEBOUNCE_INTERVAL (3 * V22RW_2X2_KEYS_POLL_INTERVAL) + +static struct gpio_led v22rw_2x2_leds_gpio[] __initdata = { + { + .name = "v22rw-2x2:green:security", + .gpio = V22RW_2X2_GPIO_LED_SECURITY, + .active_low = 1, + }, { + .name = "v22rw-2x2:red:wps", + .gpio = V22RW_2X2_GPIO_LED_WPS, + .active_low = 1, + } +}; + +static struct gpio_keys_button v22rw_2x2_gpio_buttons[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = V22RW_2X2_KEYS_DEBOUNCE_INTERVAL, + .gpio = V22RW_2X2_GPIO_BUTTON_SWRST, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = V22RW_2X2_KEYS_DEBOUNCE_INTERVAL, + .gpio = V22RW_2X2_GPIO_BUTTON_WPS, + .active_low = 1, + } +}; + +static void __init v22rw_2x2_init(void) +{ + rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); + + rt305x_register_flash(0); + + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; + rt305x_register_ethernet(); + ramips_register_gpio_leds(-1, ARRAY_SIZE(v22rw_2x2_leds_gpio), + v22rw_2x2_leds_gpio); + ramips_register_gpio_buttons(-1, V22RW_2X2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(v22rw_2x2_gpio_buttons), + v22rw_2x2_gpio_buttons); + rt305x_register_wifi(); + rt305x_register_wdt(); + rt305x_register_usb(); +} + +MIPS_MACHINE(RAMIPS_MACH_V22RW_2X2, "V22RW-2X2", "Ralink AP-RT3052-V22RW-2X2", + v22rw_2x2_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-w306r-v20.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-w306r-v20.c new file mode 100644 index 0000000000..7c8eb867cd --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-w306r-v20.c @@ -0,0 +1,72 @@ +/* + * Tenda W306R V2.0 board support + * + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "devices.h" + +#define W306R_V20_GPIO_LED_SYS 9 +#define W306R_V20_GPIO_LED_WPS 13 + +#define W306R_V20_GPIO_BUTTON_RESET 10 + +#define W306R_V20_KEYS_POLL_INTERVAL 20 +#define W306R_V20_KEYS_DEBOUNCE_INTERVAL (3 * W306R_V20_KEYS_POLL_INTERVAL) + +static struct gpio_led w306r_v20_leds_gpio[] __initdata = { + { + .name = "w306r-v20:green:sys", + .gpio = W306R_V20_GPIO_LED_SYS, + .active_low = 1, + }, { + .name = "w306r-v20:green:wps", + .gpio = W306R_V20_GPIO_LED_WPS, + .active_low = 1, + } +}; + +static struct gpio_keys_button w306r_v20_gpio_buttons[] __initdata = { + { + .desc = "RESET/WPS", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = W306R_V20_KEYS_DEBOUNCE_INTERVAL, + .gpio = W306R_V20_GPIO_BUTTON_RESET, + .active_low = 1, + } +}; + +static void __init w306r_v20_init(void) +{ + rt305x_register_flash(0); + + rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); + + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL; + rt305x_register_ethernet(); + ramips_register_gpio_leds(-1, ARRAY_SIZE(w306r_v20_leds_gpio), + w306r_v20_leds_gpio); + ramips_register_gpio_buttons(-1, W306R_V20_KEYS_POLL_INTERVAL, + ARRAY_SIZE(w306r_v20_gpio_buttons), + w306r_v20_gpio_buttons); + rt305x_register_wifi(); + rt305x_register_wdt(); +} + +MIPS_MACHINE(RAMIPS_MACH_W306R_V20, "W306R_V20", "Tenda W306R V2.0", + w306r_v20_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-w502u.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-w502u.c new file mode 100644 index 0000000000..6633ca0288 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-w502u.c @@ -0,0 +1,83 @@ +/* + * ALFA Networks W502U board support + * + * Copyright (C) 2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define W502U_GPIO_LED_USB 13 +#define W502U_GPIO_LED_WPS 14 + +#define W502U_GPIO_BUTTON_WPS 0 +#define W502U_GPIO_BUTTON_RESET 10 + +#define W502U_KEYS_POLL_INTERVAL 20 +#define W502U_KEYS_DEBOUNCE_INTERVAL (3 * W502U_KEYS_POLL_INTERVAL) + +static struct gpio_led w502u_leds_gpio[] __initdata = { + { + .name = "alfa:blue:usb", + .gpio = W502U_GPIO_LED_USB, + .active_low = 1, + }, + { + .name = "alfa:blue:wps", + .gpio = W502U_GPIO_LED_WPS, + .active_low = 1, + }, +}; + +static struct gpio_keys_button w502u_gpio_buttons[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = W502U_KEYS_DEBOUNCE_INTERVAL, + .gpio = W502U_GPIO_BUTTON_RESET, + .active_low = 1, + }, + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = W502U_KEYS_DEBOUNCE_INTERVAL, + .gpio = W502U_GPIO_BUTTON_WPS, + .active_low = 1, + }, +}; + +static void __init w502u_init(void) +{ + rt305x_gpio_init((RT305X_GPIO_MODE_GPIO << + RT305X_GPIO_MODE_UART0_SHIFT)); + + rt305x_register_flash(0); + + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL; + rt305x_register_ethernet(); + ramips_register_gpio_leds(-1, ARRAY_SIZE(w502u_leds_gpio), + w502u_leds_gpio); + ramips_register_gpio_buttons(-1, W502U_KEYS_POLL_INTERVAL, + ARRAY_SIZE(w502u_gpio_buttons), + w502u_gpio_buttons); + rt305x_register_wifi(); + rt305x_register_wdt(); + rt305x_register_usb(); +} + +MIPS_MACHINE(RAMIPS_MACH_W502U, "W502U", "ALFA Networks W502U", + w502u_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-wcr150gn.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-wcr150gn.c new file mode 100644 index 0000000000..dec1a7bb5b --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-wcr150gn.c @@ -0,0 +1,80 @@ +/* + * Sparklan WCR-150GN board support + * + * Copyright (C) 2010 Roman Yeryomin + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define WCR150GN_GPIO_LED_USER 12 +#define WCR150GN_GPIO_LED_POWER 8 +#define WCR150GN_GPIO_BUTTON_WPS 10 +#define WCR150GN_GPIO_BUTTON_RESET 0 +#define WCR150GN_KEYS_POLL_INTERVAL 20 +#define WCR150GN_KEYS_DEBOUNCE_INTERVAL (3 * WCR150GN_KEYS_POLL_INTERVAL) + +static struct gpio_led wcr150gn_leds_gpio[] __initdata = { + { + .name = "wcr150gn:amber:user", + .gpio = WCR150GN_GPIO_LED_USER, + .active_low = 1, + }, + { + .name = "wcr150gn:amber:power", + .gpio = WCR150GN_GPIO_LED_POWER, + .active_low = 1, + } +}; + +static struct gpio_keys_button wcr150gn_gpio_buttons[] __initdata = { + { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WCR150GN_KEYS_DEBOUNCE_INTERVAL, + .gpio = WCR150GN_GPIO_BUTTON_WPS, + .active_low = 1, + }, + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WCR150GN_KEYS_DEBOUNCE_INTERVAL, + .gpio = WCR150GN_GPIO_BUTTON_RESET, + .active_low = 1, + } +}; + +static void __init wcr150gn_init(void) +{ + rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); + + rt305x_register_flash(0); + + ramips_register_gpio_leds(-1, ARRAY_SIZE(wcr150gn_leds_gpio), + wcr150gn_leds_gpio); + ramips_register_gpio_buttons(-1, WCR150GN_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wcr150gn_gpio_buttons), + wcr150gn_gpio_buttons); + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; + rt305x_register_ethernet(); + rt305x_register_wifi(); + rt305x_register_wdt(); + rt305x_register_usb(); +} + +MIPS_MACHINE(RAMIPS_MACH_WCR150GN, "WCR150GN", "Sparklan WCR-150GN", + wcr150gn_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-whr-g300n.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-whr-g300n.c new file mode 100644 index 0000000000..e5adb1909f --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-whr-g300n.c @@ -0,0 +1,100 @@ +/* + * Buffalo WHR-G300N board support + * + * Copyright (C) 2009-2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define WHR_G300N_GPIO_LED_DIAG 7 +#define WHR_G300N_GPIO_LED_ROUTER 9 +#define WHR_G300N_GPIO_LED_SECURITY 14 + +#define WHR_G300N_GPIO_BUTTON_AOSS 0 /* active low */ +#define WHR_G300N_GPIO_BUTTON_RESET 10 /* active low */ +#define WHR_G300N_GPIO_BUTTON_ROUTER_ON 8 /* active low */ +#define WHR_G300N_GPIO_BUTTON_ROUTER_OFF 11 /* active low */ + +#define WHR_G300N_KEYS_POLL_INTERVAL 20 +#define WHR_G300N_KEYS_DEBOUNCE_INTERVAL (3 * WHR_G300N_KEYS_POLL_INTERVAL) + +static struct gpio_led whr_g300n_leds_gpio[] __initdata = { + { + .name = "whr-g300n:red:diag", + .gpio = WHR_G300N_GPIO_LED_DIAG, + .active_low = 1, + }, { + .name = "whr-g300n:green:router", + .gpio = WHR_G300N_GPIO_LED_ROUTER, + .active_low = 1, + }, { + .name = "whr-g300n:amber:security", + .gpio = WHR_G300N_GPIO_LED_SECURITY, + .active_low = 1, + } +}; + +static struct gpio_keys_button whr_g300n_gpio_buttons[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WHR_G300N_KEYS_DEBOUNCE_INTERVAL, + .gpio = WHR_G300N_GPIO_BUTTON_RESET, + .active_low = 1, + }, { + .desc = "aoss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WHR_G300N_KEYS_DEBOUNCE_INTERVAL, + .gpio = WHR_G300N_GPIO_BUTTON_AOSS, + .active_low = 1, + }, { + .desc = "router-off", + .type = EV_KEY, + .code = BTN_2, + .debounce_interval = WHR_G300N_KEYS_DEBOUNCE_INTERVAL, + .gpio = WHR_G300N_GPIO_BUTTON_ROUTER_OFF, + .active_low = 1, + }, { + .desc = "router-on", + .type = EV_KEY, + .code = BTN_3, + .debounce_interval = WHR_G300N_KEYS_DEBOUNCE_INTERVAL, + .gpio = WHR_G300N_GPIO_BUTTON_ROUTER_ON, + .active_low = 1, + } +}; + +static void __init whr_g300n_init(void) +{ + rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); + + rt305x_register_flash(0); + + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; + rt305x_register_ethernet(); + ramips_register_gpio_leds(-1, ARRAY_SIZE(whr_g300n_leds_gpio), + whr_g300n_leds_gpio); + ramips_register_gpio_buttons(-1, WHR_G300N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(whr_g300n_gpio_buttons), + whr_g300n_gpio_buttons); + rt305x_register_wifi(); + rt305x_register_wdt(); +} + +MIPS_MACHINE(RAMIPS_MACH_WHR_G300N, "WHR-G300N", "Buffalo WHR-G300N", + whr_g300n_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-wl-330n.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-wl-330n.c new file mode 100644 index 0000000000..b548dfee1d --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-wl-330n.c @@ -0,0 +1,94 @@ +/* + * Asus WL_330N board support + * + * Copyright (C) 2012 Frederic Leroy + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define WL_330N_GPIO_BUTTON_RESET 10 +#define WL_330N_GPIO_BUTTON_WPS 0 +#define WL_330N_GPIO_LED_LINK 9 +#define WL_330N_GPIO_LED_POWER 11 +#define WL_330N_KEYS_POLL_INTERVAL 20 +#define WL_330N_KEYS_DEBOUNCE_INTERVAL (3 * WL_330N_KEYS_POLL_INTERVAL) + +const struct flash_platform_data wl_330n_flash = { + .type = "mx25l3205d", +}; + +struct spi_board_info wl_330n_spi_slave_info[] __initdata = { + { + .modalias = "m25p80", + .platform_data = &wl_330n_flash, + .irq = -1, + .max_speed_hz = 10000000, + .bus_num = 0, + .chip_select = 0, + }, +}; + +static struct gpio_keys_button wl_330n_gpio_buttons[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WL_330N_KEYS_DEBOUNCE_INTERVAL, + .gpio = WL_330N_GPIO_BUTTON_RESET, + .active_low = 1, + }, + { + .desc = "wps", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WL_330N_KEYS_DEBOUNCE_INTERVAL, + .gpio = WL_330N_GPIO_BUTTON_WPS, + .active_low = 1, + } +}; + +static struct gpio_led wl_330n_leds_gpio[] __initdata = { + { + .name = "asus:blue:link", + .gpio = WL_330N_GPIO_LED_LINK, + .active_low = 1, + }, { + .name = "asus:blue:power", + .gpio = WL_330N_GPIO_LED_POWER, + .active_low = 1, + } +}; + +static void __init wl_330n_init(void) +{ + rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); + rt305x_register_spi(wl_330n_spi_slave_info, + ARRAY_SIZE(wl_330n_spi_slave_info)); + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL; + rt305x_register_ethernet(); + ramips_register_gpio_leds(-1, ARRAY_SIZE(wl_330n_leds_gpio), + wl_330n_leds_gpio); + ramips_register_gpio_buttons(-1, WL_330N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wl_330n_gpio_buttons), + wl_330n_gpio_buttons); + rt305x_register_wifi(); + rt305x_register_wdt(); +} + +MIPS_MACHINE(RAMIPS_MACH_WL_330N, "WL_330N", "Asus WL-330N", + wl_330n_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-wl-330n3g.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-wl-330n3g.c new file mode 100644 index 0000000000..599b9a9adb --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-wl-330n3g.c @@ -0,0 +1,100 @@ +/* + * Asus WL_330N3G board support + * + * Copyright (C) 2012 Frederic Leroy + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define WL_330N3G_GPIO_BUTTON_RESET 10 +#define WL_330N3G_GPIO_BUTTON_WPS 0 +#define WL_330N3G_GPIO_LED_3G_BLUE 9 +#define WL_330N3G_GPIO_LED_3G_RED 13 +#define WL_330N3G_GPIO_LED_POWER 11 +#define WL_330N3G_KEYS_POLL_INTERVAL 20 +#define WL_330N3G_KEYS_DEBOUNCE_INTERVAL (3 * WL_330N3G_KEYS_POLL_INTERVAL) + +const struct flash_platform_data wl_330n3g_flash = { + .type = "mx25l3205d", +}; + +struct spi_board_info wl_330n3g_spi_slave_info[] __initdata = { + { + .modalias = "m25p80", + .platform_data = &wl_330n3g_flash, + .irq = -1, + .max_speed_hz = 10000000, + .bus_num = 0, + .chip_select = 0, + }, +}; + +static struct gpio_keys_button wl_330n3g_gpio_buttons[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WL_330N3G_KEYS_DEBOUNCE_INTERVAL, + .gpio = WL_330N3G_GPIO_BUTTON_RESET, + .active_low = 1, + }, + { + .desc = "wps", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WL_330N3G_KEYS_DEBOUNCE_INTERVAL, + .gpio = WL_330N3G_GPIO_BUTTON_WPS, + .active_low = 1, + } +}; + +static struct gpio_led wl_330n3g_leds_gpio[] __initdata = { + { + .name = "asus:blue:3g", + .gpio = WL_330N3G_GPIO_LED_3G_BLUE, + .active_low = 1, + }, { + .name = "asus:red:3g", + .gpio = WL_330N3G_GPIO_LED_3G_RED, + .active_low = 1, + }, { + .name = "asus:blue:power", + .gpio = WL_330N3G_GPIO_LED_POWER, + .active_low = 1, + } +}; + +static void __init wl_330n3g_init(void) +{ + rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); + rt305x_register_spi(wl_330n3g_spi_slave_info, + ARRAY_SIZE(wl_330n3g_spi_slave_info)); + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL; + rt305x_register_ethernet(); + ramips_register_gpio_leds(-1, ARRAY_SIZE(wl_330n3g_leds_gpio), + wl_330n3g_leds_gpio); + ramips_register_gpio_buttons(-1, WL_330N3G_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wl_330n3g_gpio_buttons), + wl_330n3g_gpio_buttons); + rt305x_register_wifi(); + rt305x_register_usb(); + rt305x_register_wdt(); +} + +MIPS_MACHINE(RAMIPS_MACH_WL_330N3G, "WL_330N3G", "Asus WL-330N3G", + wl_330n3g_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-wl341v3.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-wl341v3.c new file mode 100644 index 0000000000..2cd1d5e47a --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-wl341v3.c @@ -0,0 +1,105 @@ +/* + * Sitecom WL341v3 board support + * + * Copyright (C) 2012 Marco Antonio Mauro + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define WL341V3_GPIO_LED_FIRST_AMBER 9 +#define WL341V3_GPIO_LED_FIRST_BLUE 13 +#define WL341V3_GPIO_LED_THIRD_AMBER 11 +#define WL341V3_GPIO_LED_THIRD_BLUE 14 +#define WL341V3_GPIO_LED_FOURTH_BLUE 10 +#define WL341V3_GPIO_LED_FIFTH_AMBER 12 +#define WL341V3_GPIO_LED_FIFTH_BLUE 8 + +#define WL341V3_GPIO_BUTTON_WPS 5 /* active low */ +#define WL341V3_GPIO_BUTTON_RESET 7 /* active low */ + +#define WL341V3_KEYS_POLL_INTERVAL 20 +#define WL341V3_KEYS_DEBOUNCE_INTERVAL (3 * WL341V3_KEYS_POLL_INTERVAL) + +static struct gpio_led wl341v3_leds_gpio[] __initdata = { + { + .name = "wl341v3:amber:first", + .gpio = WL341V3_GPIO_LED_FIRST_AMBER, + .active_low = 1, + }, { + .name = "wl341v3:blue:first", + .gpio = WL341V3_GPIO_LED_FIRST_BLUE, + .active_low = 1, + }, { + .name = "wl341v3:amber:third", + .gpio = WL341V3_GPIO_LED_THIRD_AMBER, + .active_low = 1, + }, { + .name = "wl341v3:blue:third", + .gpio = WL341V3_GPIO_LED_THIRD_BLUE, + .active_low = 1, + }, { + .name = "wl341v3:blue:fourth", + .gpio = WL341V3_GPIO_LED_FOURTH_BLUE, + .active_low = 1, + }, { + .name = "wl341v3:amber:fifth", + .gpio = WL341V3_GPIO_LED_FIFTH_AMBER, + .active_low = 1, + }, { + .name = "wl341v3:blue:fifth", + .gpio = WL341V3_GPIO_LED_FIFTH_BLUE, + .active_low = 1, + } +}; + +static struct gpio_keys_button wl341v3_gpio_buttons[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WL341V3_KEYS_DEBOUNCE_INTERVAL, + .gpio = WL341V3_GPIO_BUTTON_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WL341V3_KEYS_DEBOUNCE_INTERVAL, + .gpio = WL341V3_GPIO_BUTTON_WPS, + .active_low = 1, + } +}; + +static void __init wl341v3_init(void) +{ + rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); + + rt305x_register_flash(0); + + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL; + rt305x_register_ethernet(); + ramips_register_gpio_leds(-1, ARRAY_SIZE(wl341v3_leds_gpio), + wl341v3_leds_gpio); + ramips_register_gpio_buttons(-1, WL341V3_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wl341v3_gpio_buttons), + wl341v3_gpio_buttons); + rt305x_register_wifi(); + rt305x_register_wdt(); + rt305x_register_usb(); +} + +MIPS_MACHINE(RAMIPS_MACH_WL341V3, "WL341V3", "Sitecom WL-341 v3", + wl341v3_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-wl351.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-wl351.c new file mode 100644 index 0000000000..8c0caadb1a --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-wl351.c @@ -0,0 +1,118 @@ +/* + * Sitecom WL-351 v1 002 board support + * + * Copyright (C) 2011 Tobias Diedrich + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define WL351_GPIO_LED_POWER_AMBER 8 +#define WL351_GPIO_LED_UNPOPULATED_AMBER 12 +#define WL351_GPIO_LED_UNPOPULATED_BLUE 13 + +#define WL351_GPIO_BUTTON_RESET 10 +#define WL351_GPIO_BUTTON_WPS 0 + +#define WL351_KEYS_POLL_INTERVAL 20 +#define WL351_KEYS_DEBOUNCE_INTERVAL (3 * WL351_KEYS_POLL_INTERVAL) + +static struct gpio_led wl351_leds_gpio[] __initdata = { + { + .name = "wl-351:amber:power", + .gpio = WL351_GPIO_LED_POWER_AMBER, + .active_low = 1, + }, { + .name = "wl-351:amber:unpopulated", + .gpio = WL351_GPIO_LED_UNPOPULATED_AMBER, + .active_low = 1, + }, { + .name = "wl-351:blue:unpopulated", + .gpio = WL351_GPIO_LED_UNPOPULATED_BLUE, + .active_low = 1, + } +}; + + +static struct gpio_keys_button wl351_gpio_buttons[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WL351_KEYS_DEBOUNCE_INTERVAL, + .gpio = WL351_GPIO_BUTTON_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WL351_KEYS_DEBOUNCE_INTERVAL, + .gpio = WL351_GPIO_BUTTON_WPS, + .active_low = 1, + } +}; + +static struct rtl8366_platform_data wl351_switch_data = { + .gpio_sda = RT305X_GPIO_I2C_SD, + .gpio_sck = RT305X_GPIO_I2C_SCLK, +}; + +static struct platform_device wl351_switch = { + .name = RTL8366RB_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &wl351_switch_data, + } +}; + +static void __init wl351_init(void) +{ + rt305x_gpio_init((RT305X_GPIO_MODE_GPIO << + RT305X_GPIO_MODE_UART0_SHIFT) | + RT305X_GPIO_MODE_I2C | + RT305X_GPIO_MODE_SPI | + RT305X_GPIO_MODE_MDIO); + + rt305x_register_flash(0); + + ramips_register_gpio_leds(-1, ARRAY_SIZE(wl351_leds_gpio), + wl351_leds_gpio); + ramips_register_gpio_buttons(-1, WL351_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wl351_gpio_buttons), + wl351_gpio_buttons); + /* External RTL8366RB. */ + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_NONE; + rt305x_esw_data.reg_initval_fct2 = 0x0002500c; + /* + * ext phy base addr 31, rx/tx clock skew 0, + * turbo mii off, rgmi 3.3v off, port 5 polling off + * port5: enabled, gige, full-duplex, rx/tx-flow-control + * port6: enabled, gige, full-duplex, rx/tx-flow-control + */ + rt305x_esw_data.reg_initval_fpa2 = 0x1f003fff; + rt305x_register_ethernet(); + platform_device_register(&wl351_switch); + rt305x_register_wifi(); + rt305x_register_wdt(); + rt305x_register_usb(); +} + +MIPS_MACHINE(RAMIPS_MACH_WL351, "WL-351", "Sitecom WL-351 v1 002", + wl351_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-wr512-3gn.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-wr512-3gn.c new file mode 100644 index 0000000000..eed752353d --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-wr512-3gn.c @@ -0,0 +1,110 @@ +/* + * Unbranded router from DX board support + * Also known as *WR512*-3GN by local vendors + * e.g. WS-WR512N1, Sin Hon SH-WR512NU, and etc + * (http://www.dealextreme.com/p/portable-wireless-n-3g-router-cdma2000-evdo-td-scdma-hspa-wcdma-45639) + * This router is also known to be rebranded and sold by a number of local + * vendors in several countries. + * + * Copyright (C) 2011 Andrew Andrianov + * Based on MOFI3500-3N code by + * Copyright (C) 2011 Layne Edwards + * + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + + +#define WR512_3GN_GPIO_LED_3G 9 +#define WR512_3GN_GPIO_LED_GATEWAY 11 +#define WR512_3GN_GPIO_LED_AP 12 +#define WR512_3GN_GPIO_LED_STATION 13 +#define WR512_3GN_GPIO_LED_WPS 14 + +#define WR512_3GN_GPIO_BUTTON_RESET 10 +#define WR512_3GN_GPIO_BUTTON_CONNECT 7 +#define WR512_3GN_GPIO_BUTTON_WPS 0 +#define WR512_3GN_GPIO_BUTTON_WPS2 8 + +#define WR512_3GN_KEYS_POLL_INTERVAL 20 +#define WR512_3GN_KEYS_DEBOUNCE_INTERVAL (3 * WR512_3GN_KEYS_POLL_INTERVAL) + +static struct gpio_led wr512_3gn_leds_gpio[] __initdata = { + { + .name = "wr512:green:3g", + .gpio = WR512_3GN_GPIO_LED_3G, + .active_low = 1, + }, { + .name = "wr512:green:gateway", + .gpio = WR512_3GN_GPIO_LED_GATEWAY, + .active_low = 1, + }, { + .name = "wr512:green:ap", + .gpio = WR512_3GN_GPIO_LED_AP, + .active_low = 1, + }, { + .name = "wr512:green:wps", + .gpio = WR512_3GN_GPIO_LED_WPS, + .active_low = 1, + }, { + .name = "wr512:green:station", + .gpio = WR512_3GN_GPIO_LED_STATION, + .active_low = 1, + } +}; + +static struct gpio_keys_button wr512_3gn_gpio_buttons[] __initdata = { + { + .desc = "reset_wps", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WR512_3GN_KEYS_DEBOUNCE_INTERVAL, + .gpio = WR512_3GN_GPIO_BUTTON_RESET, + .active_low = 1, + }, { + .desc = "mode", + .type = EV_KEY, + .code = KEY_M, + .debounce_interval = WR512_3GN_KEYS_DEBOUNCE_INTERVAL, + .gpio = WR512_3GN_GPIO_BUTTON_CONNECT, + .active_low = 1, + } +}; + +#define WR512_3GN_GPIO_MODE \ + ((RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT) | \ + RT305X_GPIO_MODE_MDIO) + +static void __init wr512_3gn_init(void) +{ + rt305x_gpio_init(WR512_3GN_GPIO_MODE); + + rt305x_register_flash(0); + + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; + rt305x_register_ethernet(); + ramips_register_gpio_leds(-1, ARRAY_SIZE(wr512_3gn_leds_gpio), + wr512_3gn_leds_gpio); + ramips_register_gpio_buttons(-1, WR512_3GN_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wr512_3gn_gpio_buttons), + wr512_3gn_gpio_buttons); + rt305x_register_wifi(); + rt305x_register_wdt(); + rt305x_register_usb(); +} + +MIPS_MACHINE(RAMIPS_MACH_WR512_3GN, "WR512-3GN", "WR512-3GN-like router", + wr512_3gn_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-wr6202.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-wr6202.c new file mode 100644 index 0000000000..591d9ceb59 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-wr6202.c @@ -0,0 +1,90 @@ +/* + * AWB WR6202 board support + * + * Copyright (C) 2012 Johnathan Boyce + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define WR6202_GPIO_BUTTON_RESET 10 /* active low */ +#define WR6202_GPIO_BUTTON_WPS 0 /* active low */ + +#define WR6202_KEYS_POLL_INTERVAL 20 +#define WR6202_KEYS_DEBOUNCE_INTERVAL (3 * WR6202_KEYS_POLL_INTERVAL) + +#define WR6202_GPIO_USB_POWER 11 + +#define WR6202_GPIO_LED_3G 13 +#define WR6202_GPIO_LED_WPS 14 + +static struct gpio_led wr6202_leds_gpio[] __initdata = { + { + .name = "wr6202:blue:wps", + .gpio = WR6202_GPIO_LED_WPS, + .active_low = 1, + }, { + .name = "wr6202:blue:3g", + .gpio = WR6202_GPIO_LED_3G, + .active_low = 1, + } +}; + +static struct gpio_keys_button wr6202_gpio_buttons[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WR6202_KEYS_DEBOUNCE_INTERVAL, + .gpio = WR6202_GPIO_BUTTON_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WR6202_KEYS_DEBOUNCE_INTERVAL, + .gpio = WR6202_GPIO_BUTTON_WPS, + .active_low = 1, + } +}; + +static void __init wr6202_init(void) +{ + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL; + + rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); + + ramips_register_gpio_leds(-1, ARRAY_SIZE(wr6202_leds_gpio), + wr6202_leds_gpio); + ramips_register_gpio_buttons(-1, WR6202_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wr6202_gpio_buttons), + wr6202_gpio_buttons); + + /* Power to the USB port is controlled by GPIO line */ + gpio_request(WR6202_GPIO_USB_POWER, "WR6202_GPIO_USB_POWER"); + gpio_direction_output(WR6202_GPIO_USB_POWER, 0); + gpio_free(WR6202_GPIO_USB_POWER); + + rt305x_register_flash(0); + + rt305x_register_ethernet(); + rt305x_register_wifi(); + rt305x_register_wdt(); + rt305x_register_usb(); +} + +MIPS_MACHINE(RAMIPS_MACH_WR6202, "WR6202", "AWB WR6202", + wr6202_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-xdx-rn502j.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-xdx-rn502j.c new file mode 100644 index 0000000000..f7ef353262 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/mach-xdx-rn502j.c @@ -0,0 +1,79 @@ +/* + * Unknown router name/model, PCB marked with XDX-RN502J + * + * Copyright (C) 2011 Bruno Schwander bruno@tinkerbox.org + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +#define XDXRN502J_GPIO_BUTTON_RESET 12 +#define XDXRN502J_GPIO_LED_WIFI 7 +#define XDXRN502J_GPIO_LED_POWER 9 + +#define XDXRN502J_BUTTONS_POLL_INTERVAL 20 +#define XDXRN502J_BUTTONS_DEBOUNCE_INTERVAL (3 * XDXRN502J_BUTTONS_POLL_INTERVAL) + + +static struct gpio_led xdxrn502j_leds_gpio[] __initdata = { + { + .name = "xdxrn502j:green:wifi", + .gpio = XDXRN502J_GPIO_LED_WIFI, + .active_low = 1, + }, { + .name = "xdxrn502j:green:power", + .gpio = XDXRN502J_GPIO_LED_POWER, + .active_low = 1, + } +}; + +static struct gpio_keys_button xdxrn502j_gpio_buttons[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = XDXRN502J_BUTTONS_DEBOUNCE_INTERVAL, + .gpio = XDXRN502J_GPIO_BUTTON_RESET, + .active_low = 1, + } +}; + +#define XDXRN502J_GPIO_MODE \ + ((RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT) | \ + RT305X_GPIO_MODE_MDIO) + +static void __init xdxrn502j_init(void) +{ + rt305x_gpio_init(XDXRN502J_GPIO_MODE); + + rt305x_register_flash(0); + + rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL; + rt305x_register_ethernet(); + + ramips_register_gpio_leds(-1, ARRAY_SIZE(xdxrn502j_leds_gpio), + xdxrn502j_leds_gpio); + + ramips_register_gpio_buttons(-1, XDXRN502J_BUTTONS_POLL_INTERVAL, + ARRAY_SIZE(xdxrn502j_gpio_buttons), + xdxrn502j_gpio_buttons); + + rt305x_register_wifi(); + rt305x_register_wdt(); + rt305x_register_usb(); +} + +MIPS_MACHINE(RAMIPS_MACH_XDXRN502J, "XDXRN502J", "XDX RN502J", + xdxrn502j_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/rt305x.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/rt305x.c new file mode 100644 index 0000000000..8a7a58b7d5 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/rt305x.c @@ -0,0 +1,247 @@ +/* + * Ralink RT305x SoC specific setup + * + * Copyright (C) 2008-2011 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Ralink's 2.6.21 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include + +#include +#include +#include +#include + +void __iomem * rt305x_sysc_base; +void __iomem * rt305x_memc_base; +enum rt305x_soc_type rt305x_soc; + +static unsigned long rt5350_get_mem_size(void) +{ + void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE); + unsigned long ret; + u32 t; + + t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG); + t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) & + RT5350_SYSCFG0_DRAM_SIZE_MASK; + + switch (t) { + case RT5350_SYSCFG0_DRAM_SIZE_2M: + ret = 2 * 1024 * 1024; + break; + case RT5350_SYSCFG0_DRAM_SIZE_8M: + ret = 8 * 1024 * 1024; + break; + case RT5350_SYSCFG0_DRAM_SIZE_16M: + ret = 16 * 1024 * 1024; + break; + case RT5350_SYSCFG0_DRAM_SIZE_32M: + ret = 32 * 1024 * 1024; + break; + case RT5350_SYSCFG0_DRAM_SIZE_64M: + ret = 64 * 1024 * 1024; + break; + default: + panic("rt5350: invalid DRAM size: %u", t); + break; + } + + return ret; +} + +void __init ramips_soc_prom_init(void) +{ + void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE); + const char *name = "unknown"; + u32 n0; + u32 n1; + u32 id; + + n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); + n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); + + if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) { + unsigned long icache_sets; + + icache_sets = (read_c0_config1() >> 22) & 7; + if (icache_sets == 1) { + rt305x_soc = RT305X_SOC_RT3050; + name = "RT3050"; + } else { + rt305x_soc = RT305X_SOC_RT3052; + name = "RT3052"; + } + } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) { + rt305x_soc = RT305X_SOC_RT3350; + name = "RT3350"; + } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) { + rt305x_soc = RT305X_SOC_RT3352; + name = "RT3352"; + } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) { + rt305x_soc = RT305X_SOC_RT5350; + name = "RT5350"; + } else { + panic("rt305x: unknown SoC, n0:%08x n1:%08x\n", n0, n1); + } + + id = __raw_readl(sysc + SYSC_REG_CHIP_ID); + + snprintf(ramips_sys_type, RAMIPS_SYS_TYPE_LEN, + "Ralink %s id:%u rev:%u", + name, + (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK, + (id & CHIP_ID_REV_MASK)); + + ramips_mem_base = RT305X_SDRAM_BASE; + + if (soc_is_rt5350()) { + ramips_get_mem_size = rt5350_get_mem_size; + } else if (soc_is_rt305x() || soc_is_rt3350() ) { + ramips_mem_size_min = RT305X_MEM_SIZE_MIN; + ramips_mem_size_max = RT305X_MEM_SIZE_MAX; + } else if (soc_is_rt3352()) { + ramips_mem_size_min = RT3352_MEM_SIZE_MIN; + ramips_mem_size_max = RT3352_MEM_SIZE_MAX; + } else { + BUG(); + } +} + +static struct ramips_gpio_chip rt305x_gpio_chips[] = { + { + .chip = { + .label = "RT305X-GPIO0", + .base = 0, + .ngpio = 24, + }, + .regs = { + [RAMIPS_GPIO_REG_INT] = 0x00, + [RAMIPS_GPIO_REG_EDGE] = 0x04, + [RAMIPS_GPIO_REG_RENA] = 0x08, + [RAMIPS_GPIO_REG_FENA] = 0x0c, + [RAMIPS_GPIO_REG_DATA] = 0x20, + [RAMIPS_GPIO_REG_DIR] = 0x24, + [RAMIPS_GPIO_REG_POL] = 0x28, + [RAMIPS_GPIO_REG_SET] = 0x2c, + [RAMIPS_GPIO_REG_RESET] = 0x30, + [RAMIPS_GPIO_REG_TOGGLE] = 0x34, + }, + .map_base = RT305X_PIO_BASE, + .map_size = RT305X_PIO_SIZE, + }, + { + .chip = { + .label = "RT305X-GPIO1", + .base = 24, + .ngpio = 16, + }, + .regs = { + [RAMIPS_GPIO_REG_INT] = 0x38, + [RAMIPS_GPIO_REG_EDGE] = 0x3c, + [RAMIPS_GPIO_REG_RENA] = 0x40, + [RAMIPS_GPIO_REG_FENA] = 0x44, + [RAMIPS_GPIO_REG_DATA] = 0x48, + [RAMIPS_GPIO_REG_DIR] = 0x4c, + [RAMIPS_GPIO_REG_POL] = 0x50, + [RAMIPS_GPIO_REG_SET] = 0x54, + [RAMIPS_GPIO_REG_RESET] = 0x58, + [RAMIPS_GPIO_REG_TOGGLE] = 0x5c, + }, + .map_base = RT305X_PIO_BASE, + .map_size = RT305X_PIO_SIZE, + }, + { + .chip = { + .label = "RT305X-GPIO2", + .base = 40, + .ngpio = 12, + }, + .regs = { + [RAMIPS_GPIO_REG_INT] = 0x60, + [RAMIPS_GPIO_REG_EDGE] = 0x64, + [RAMIPS_GPIO_REG_RENA] = 0x68, + [RAMIPS_GPIO_REG_FENA] = 0x6c, + [RAMIPS_GPIO_REG_DATA] = 0x70, + [RAMIPS_GPIO_REG_DIR] = 0x74, + [RAMIPS_GPIO_REG_POL] = 0x78, + [RAMIPS_GPIO_REG_SET] = 0x7c, + [RAMIPS_GPIO_REG_RESET] = 0x80, + [RAMIPS_GPIO_REG_TOGGLE] = 0x84, + }, + .map_base = RT305X_PIO_BASE, + .map_size = RT305X_PIO_SIZE, + }, +}; + +static struct ramips_gpio_data rt305x_gpio_data = { + .chips = rt305x_gpio_chips, + .num_chips = ARRAY_SIZE(rt305x_gpio_chips), +}; + +static void rt305x_gpio_reserve(int first, int last) +{ + for (; first <= last; first++) + gpio_request(first, "reserved"); +} + +void __init rt305x_gpio_init(u32 mode) +{ + u32 t; + + rt305x_sysc_wr(mode, SYSC_REG_GPIO_MODE); + + ramips_gpio_init(&rt305x_gpio_data); + if ((mode & RT305X_GPIO_MODE_I2C) == 0) + rt305x_gpio_reserve(RT305X_GPIO_I2C_SD, RT305X_GPIO_I2C_SCLK); + + if ((mode & RT305X_GPIO_MODE_SPI) == 0) + rt305x_gpio_reserve(RT305X_GPIO_SPI_EN, RT305X_GPIO_SPI_CLK); + + t = mode >> RT305X_GPIO_MODE_UART0_SHIFT; + t &= RT305X_GPIO_MODE_UART0_MASK; + switch (t) { + case RT305X_GPIO_MODE_UARTF: + case RT305X_GPIO_MODE_PCM_UARTF: + case RT305X_GPIO_MODE_PCM_I2S: + case RT305X_GPIO_MODE_I2S_UARTF: + rt305x_gpio_reserve(RT305X_GPIO_7, RT305X_GPIO_14); + break; + case RT305X_GPIO_MODE_PCM_GPIO: + rt305x_gpio_reserve(RT305X_GPIO_10, RT305X_GPIO_14); + break; + case RT305X_GPIO_MODE_GPIO_UARTF: + case RT305X_GPIO_MODE_GPIO_I2S: + rt305x_gpio_reserve(RT305X_GPIO_7, RT305X_GPIO_10); + break; + } + + if ((mode & RT305X_GPIO_MODE_UART1) == 0) + rt305x_gpio_reserve(RT305X_GPIO_UART1_TXD, + RT305X_GPIO_UART1_RXD); + + if ((mode & RT305X_GPIO_MODE_JTAG) == 0) + rt305x_gpio_reserve(RT305X_GPIO_JTAG_TDO, RT305X_GPIO_JTAG_TDI); + + if ((mode & RT305X_GPIO_MODE_MDIO) == 0) + rt305x_gpio_reserve(RT305X_GPIO_MDIO_MDC, + RT305X_GPIO_MDIO_MDIO); + + if ((mode & RT305X_GPIO_MODE_SDRAM) == 0) + rt305x_gpio_reserve(RT305X_GPIO_SDRAM_MD16, + RT305X_GPIO_SDRAM_MD31); + + if ((mode & RT305X_GPIO_MODE_RGMII) == 0) + rt305x_gpio_reserve(RT305X_GPIO_GE0_TXD0, + RT305X_GPIO_GE0_RXCLK); +} diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/setup.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/setup.c new file mode 100644 index 0000000000..5a069db454 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/setup.c @@ -0,0 +1,88 @@ +/* + * Ralink RT305x SoC specific setup + * + * Copyright (C) 2008-2011 Gabor Juhos + * + * Parts of this file are based on Ralink's 2.6.21 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include "common.h" + +static void rt305x_restart(char *command) +{ + rt305x_sysc_wr(RT305X_RESET_SYSTEM, SYSC_REG_RESET_CTRL); + while (1) + if (cpu_wait) + cpu_wait(); +} + +static void rt305x_halt(void) +{ + while (1) + if (cpu_wait) + cpu_wait(); +} + +unsigned int __cpuinit get_c0_compare_irq(void) +{ + return CP0_LEGACY_COMPARE_IRQ; +} + +void __init ramips_soc_setup(void) +{ + struct clk *clk; + + rt305x_sysc_base = ioremap_nocache(RT305X_SYSC_BASE, PAGE_SIZE); + rt305x_memc_base = ioremap_nocache(RT305X_MEMC_BASE, PAGE_SIZE); + + rt305x_clocks_init(); + + clk = clk_get(NULL, "cpu"); + if (IS_ERR(clk)) + panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); + + printk(KERN_INFO "%s running at %lu.%02lu MHz\n", ramips_sys_type, + clk_get_rate(clk) / 1000000, + (clk_get_rate(clk) % 1000000) * 100 / 1000000); + + _machine_restart = rt305x_restart; + _machine_halt = rt305x_halt; + pm_power_off = rt305x_halt; + + clk = clk_get(NULL, "uart"); + if (IS_ERR(clk)) + panic("unable to get UART clock, err=%ld", PTR_ERR(clk)); + + ramips_early_serial_setup(0, RT305X_UART0_BASE, clk_get_rate(clk), + RT305X_INTC_IRQ_UART0); + ramips_early_serial_setup(1, RT305X_UART1_BASE, clk_get_rate(clk), + RT305X_INTC_IRQ_UART1); +} + +void __init plat_time_init(void) +{ + struct clk *clk; + + clk = clk_get(NULL, "cpu"); + if (IS_ERR(clk)) + panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); + + mips_hpt_frequency = clk_get_rate(clk) / 2; +} diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/Kconfig b/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/Kconfig new file mode 100644 index 0000000000..57823f0c67 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/Kconfig @@ -0,0 +1,34 @@ +if RALINK_RT3883 + +menu "Ralink RT3662/RT3883 machine selection" + +config RT3883_MACH_RT_N56U + bool "Asus RT-N56U support" + select HW_HAS_PCI + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT3883_MACH_DIR_645 + bool "D-Link DIR-645 support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT3883_MACH_OMNI_EMB_HPM + bool "Omnima EMB HPM board support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT3883_MACH_TEW_691GR + bool "TRENDnet TEW-691GR support" + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +config RT3883_MACH_TEW_692GR + bool "TRENDnet TEW-692GR support" + select HW_HAS_PCI + select RALINK_DEV_GPIO_BUTTONS + select RALINK_DEV_GPIO_LEDS + +endmenu + +endif diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/Makefile b/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/Makefile new file mode 100644 index 0000000000..e1ab61e814 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/Makefile @@ -0,0 +1,18 @@ +# +# Makefile for the Ralink RT3662/RT3883 SoC specific parts of the kernel +# +# Copyright (C) 2011-2012 Gabor Juhos +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License version 2 as published +# by the Free Software Foundation. + +obj-y := irq.o setup.o devices.o rt3883.o clock.o + +obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + +obj-$(CONFIG_RT3883_MACH_DIR_645) += mach-dir-645.o +obj-$(CONFIG_RT3883_MACH_OMNI_EMB_HPM) += mach-omni-emb-hpm.o +obj-$(CONFIG_RT3883_MACH_RT_N56U) += mach-rt-n56u.o +obj-$(CONFIG_RT3883_MACH_TEW_691GR) += mach-tew-691gr.o +obj-$(CONFIG_RT3883_MACH_TEW_692GR) += mach-tew-692gr.o diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/clock.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/clock.c new file mode 100644 index 0000000000..bf70259cae --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/clock.c @@ -0,0 +1,103 @@ +/* + * Ralink RT3662/RT3883 clock API + * + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include "common.h" + +struct clk { + unsigned long rate; +}; + +static struct clk rt3883_cpu_clk; +static struct clk rt3883_sys_clk; +static struct clk rt3883_wdt_clk; +static struct clk rt3883_uart_clk; + +void __init rt3883_clocks_init(void) +{ + u32 syscfg0; + u32 clksel; + u32 ddr2; + + syscfg0 = rt3883_sysc_rr(RT3883_SYSC_REG_SYSCFG0); + clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) & + RT3883_SYSCFG0_CPUCLK_MASK); + ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2; + + switch (clksel) { + case RT3883_SYSCFG0_CPUCLK_250: + rt3883_cpu_clk.rate = 250000000; + rt3883_sys_clk.rate = (ddr2) ? 125000000 : 83000000; + break; + case RT3883_SYSCFG0_CPUCLK_384: + rt3883_cpu_clk.rate = 384000000; + rt3883_sys_clk.rate = (ddr2) ? 128000000 : 96000000; + break; + case RT3883_SYSCFG0_CPUCLK_480: + rt3883_cpu_clk.rate = 480000000; + rt3883_sys_clk.rate = (ddr2) ? 160000000 : 120000000; + break; + case RT3883_SYSCFG0_CPUCLK_500: + rt3883_cpu_clk.rate = 500000000; + rt3883_sys_clk.rate = (ddr2) ? 166000000 : 125000000; + break; + } + + rt3883_wdt_clk.rate = rt3883_sys_clk.rate; + rt3883_uart_clk.rate = 40000000; +} + +struct clk *clk_get(struct device *dev, const char *id) +{ + if (!strcmp(id, "sys")) + return &rt3883_sys_clk; + + if (!strcmp(id, "cpu")) + return &rt3883_cpu_clk; + + if (!strcmp(id, "wdt")) + return &rt3883_wdt_clk; + + if (!strcmp(id, "uart")) + return &rt3883_uart_clk; + + return ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL(clk_get); + +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + return clk->rate; +} +EXPORT_SYMBOL(clk_get_rate); + +void clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_put); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/common.h b/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/common.h new file mode 100644 index 0000000000..a389dccce0 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/common.h @@ -0,0 +1,16 @@ +/* + * Ralink RT3662/RT3883 SoC common defines + * + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _RT3883_COMMON_H +#define _RT3883_COMMON_H + +void rt3883_clocks_init(void); + +#endif /* _RT3883_COMMON_H */ \ No newline at end of file diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/devices.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/devices.c new file mode 100644 index 0000000000..6077e97dda --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/devices.c @@ -0,0 +1,398 @@ +/* + * Ralink RT3662/RT3883 SoC platform device registration + * + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include "devices.h" + +#include + +static struct resource rt3883_flash0_resources[] = { + { + .flags = IORESOURCE_MEM, + .start = RT3883_BOOT_BASE, + .end = RT3883_BOOT_BASE + RT3883_BOOT_SIZE - 1, + }, +}; + +struct physmap_flash_data rt3883_flash0_data; +static struct platform_device rt3883_flash0_device = { + .name = "physmap-flash", + .resource = rt3883_flash0_resources, + .num_resources = ARRAY_SIZE(rt3883_flash0_resources), + .dev = { + .platform_data = &rt3883_flash0_data, + }, +}; + +static struct resource rt3883_flash1_resources[] = { + { + .flags = IORESOURCE_MEM, + .start = RT3883_SRAM_BASE, + .end = RT3883_SRAM_BASE + RT3883_SRAM_SIZE - 1, + }, +}; + +struct physmap_flash_data rt3883_flash1_data; +static struct platform_device rt3883_flash1_device = { + .name = "physmap-flash", + .resource = rt3883_flash1_resources, + .num_resources = ARRAY_SIZE(rt3883_flash1_resources), + .dev = { + .platform_data = &rt3883_flash1_data, + }, +}; + +static int rt3883_flash_instance __initdata; +void __init rt3883_register_pflash(unsigned int id) +{ + struct platform_device *pdev; + struct physmap_flash_data *pdata; + void __iomem *fscc_base; + u32 t; + int reg; + + switch (id) { + case 0: + pdev = &rt3883_flash0_device; + reg = RT3883_FSCC_REG_FLASH_CFG0; + break; + case 1: + pdev = &rt3883_flash1_device; + reg = RT3883_FSCC_REG_FLASH_CFG1; + break; + default: + return; + } + + pdata = pdev->dev.platform_data; + + fscc_base = ioremap(RT3883_FSCC_BASE, RT3883_FSCC_SIZE); + if (!fscc_base) + panic("RT3883: ioremap failed for FSCC"); + + t = __raw_readl(fscc_base + reg); + iounmap(fscc_base); + + t = (t >> RT3883_FLASH_CFG_WIDTH_SHIFT) & RT3883_FLASH_CFG_WIDTH_MASK; + switch (t) { + case RT3883_FLASH_CFG_WIDTH_8BIT: + pdata->width = 1; + break; + case RT3883_FLASH_CFG_WIDTH_16BIT: + pdata->width = 2; + break; + case RT3883_FLASH_CFG_WIDTH_32BIT: + if (id == 1) { + pdata->width = 4; + break; + } + /* fallthrough */ + default: + pr_warn("RT3883: flash bank%d: invalid width detected\n", id); + return; + } + + pdev->id = rt3883_flash_instance; + + platform_device_register(pdev); + rt3883_flash_instance++; +} + +static atomic_t rt3883_usb_pwr_ref = ATOMIC_INIT(0); + +static int rt3883_usb_power_on(struct platform_device *pdev) +{ + + if (atomic_inc_return(&rt3883_usb_pwr_ref) == 1) { + u32 t; + + t = rt3883_sysc_rr(RT3883_SYSC_REG_USB_PS); + + /* enable clock for port0's and port1's phys */ + t = rt3883_sysc_rr(RT3883_SYSC_REG_CLKCFG1); + t |= RT3883_CLKCFG1_UPHY0_CLK_EN | RT3883_CLKCFG1_UPHY1_CLK_EN; + rt3883_sysc_wr(t, RT3883_SYSC_REG_CLKCFG1); + mdelay(500); + + /* pull USBHOST and USBDEV out from reset */ + t = rt3883_sysc_rr(RT3883_SYSC_REG_RSTCTRL); + t &= ~(RT3883_RSTCTRL_UHST | RT3883_RSTCTRL_UDEV); + rt3883_sysc_wr(t, RT3883_SYSC_REG_RSTCTRL); + mdelay(500); + + /* enable host mode */ + t = rt3883_sysc_rr(RT3883_SYSC_REG_SYSCFG1); + t |= RT3883_SYSCFG1_USB0_HOST_MODE; + rt3883_sysc_wr(t, RT3883_SYSC_REG_SYSCFG1); + + t = rt3883_sysc_rr(RT3883_SYSC_REG_USB_PS); + } + + return 0; +} + +static void rt3883_usb_power_off(struct platform_device *pdev) +{ + if (atomic_dec_return(&rt3883_usb_pwr_ref) == 0) { + u32 t; + + /* put USBHOST and USBDEV into reset */ + t = rt3883_sysc_rr(RT3883_SYSC_REG_RSTCTRL); + t |= RT3883_RSTCTRL_UHST | RT3883_RSTCTRL_UDEV; + rt3883_sysc_wr(t, RT3883_SYSC_REG_RSTCTRL); + udelay(10000); + + /* disable clock for port0's and port1's phys*/ + t = rt3883_sysc_rr(RT3883_SYSC_REG_CLKCFG1); + t &= ~(RT3883_CLKCFG1_UPHY0_CLK_EN | + RT3883_CLKCFG1_UPHY1_CLK_EN); + rt3883_sysc_wr(t, RT3883_SYSC_REG_CLKCFG1); + udelay(10000); + } +} + +static struct usb_ehci_pdata rt3883_ehci_data = { + .power_on = rt3883_usb_power_on, + .power_off = rt3883_usb_power_off, +}; + +static struct resource rt3883_ehci_resources[] = { + { + .start = RT3883_EHCI_BASE, + .end = RT3883_EHCI_BASE + PAGE_SIZE - 1, + .flags = IORESOURCE_MEM, + }, { + .start = RT3883_INTC_IRQ_UHST, + .end = RT3883_INTC_IRQ_UHST, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 rt3883_ehci_dmamask = DMA_BIT_MASK(32); +static struct platform_device rt3883_ehci_device = { + .name = "ehci-platform", + .id = -1, + .resource = rt3883_ehci_resources, + .num_resources = ARRAY_SIZE(rt3883_ehci_resources), + .dev = { + .dma_mask = &rt3883_ehci_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &rt3883_ehci_data, + }, +}; + +static struct resource rt3883_ohci_resources[] = { + { + .start = RT3883_OHCI_BASE, + .end = RT3883_OHCI_BASE + PAGE_SIZE - 1, + .flags = IORESOURCE_MEM, + }, { + .start = RT3883_INTC_IRQ_UHST, + .end = RT3883_INTC_IRQ_UHST, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct usb_ohci_pdata rt3883_ohci_data = { + .power_on = rt3883_usb_power_on, + .power_off = rt3883_usb_power_off, +}; + +static u64 rt3883_ohci_dmamask = DMA_BIT_MASK(32); +static struct platform_device rt3883_ohci_device = { + .name = "ohci-platform", + .id = -1, + .resource = rt3883_ohci_resources, + .num_resources = ARRAY_SIZE(rt3883_ohci_resources), + .dev = { + .dma_mask = &rt3883_ohci_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &rt3883_ohci_data, + }, +}; + +void __init rt3883_register_usbhost(void) +{ + platform_device_register(&rt3883_ehci_device); + platform_device_register(&rt3883_ohci_device); +} + +static void rt3883_fe_reset(void) +{ + u32 t; + + t = rt3883_sysc_rr(RT3883_SYSC_REG_RSTCTRL); + t |= RT3883_RSTCTRL_FE; + rt3883_sysc_wr(t , RT3883_SYSC_REG_RSTCTRL); + + t &= ~RT3883_RSTCTRL_FE; + rt3883_sysc_wr(t, RT3883_SYSC_REG_RSTCTRL); +} + +static struct resource rt3883_eth_resources[] = { + { + .start = RT3883_FE_BASE, + .end = RT3883_FE_BASE + PAGE_SIZE - 1, + .flags = IORESOURCE_MEM, + }, { + .start = RT3883_CPU_IRQ_FE, + .end = RT3883_CPU_IRQ_FE, + .flags = IORESOURCE_IRQ, + }, +}; + +struct ramips_eth_platform_data rt3883_eth_data = { + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 }, + .reset_fe = rt3883_fe_reset, + .min_pkt_len = 64, +}; + +static struct platform_device rt3883_eth_device = { + .name = "ramips_eth", + .resource = rt3883_eth_resources, + .num_resources = ARRAY_SIZE(rt3883_eth_resources), + .dev = { + .platform_data = &rt3883_eth_data, + } +}; + +void __init rt3883_register_ethernet(void) +{ + struct clk *clk; + + clk = clk_get(NULL, "sys"); + if (IS_ERR(clk)) + panic("unable to get SYS clock, err=%ld", PTR_ERR(clk)); + + rt3883_eth_data.sys_freq = clk_get_rate(clk); + + platform_device_register(&rt3883_eth_device); +} + +static struct resource rt3883_wlan_resources[] = { + { + .start = RT3883_WLAN_BASE, + .end = RT3883_WLAN_BASE + 0x3FFFF, + .flags = IORESOURCE_MEM, + }, { + .start = RT3883_CPU_IRQ_WLAN, + .end = RT3883_CPU_IRQ_WLAN, + .flags = IORESOURCE_IRQ, + }, +}; + +struct rt2x00_platform_data rt3883_wlan_data; +static struct platform_device rt3883_wlan_device = { + .name = "rt2800_wmac", + .resource = rt3883_wlan_resources, + .num_resources = ARRAY_SIZE(rt3883_wlan_resources), + .dev = { + .platform_data = &rt3883_wlan_data, + } +}; + +void __init rt3883_register_wlan(void) +{ + rt3883_wlan_data.eeprom_file_name = "soc_wmac.eeprom", + platform_device_register(&rt3883_wlan_device); +} + +static struct resource rt3883_wdt_resources[] = { + { + .start = RT3883_TIMER_BASE, + .end = RT3883_TIMER_BASE + RT3883_TIMER_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device rt3883_wdt_device = { + .name = "ramips-wdt", + .id = -1, + .resource = rt3883_wdt_resources, + .num_resources = ARRAY_SIZE(rt3883_wdt_resources), +}; + +void __init rt3883_register_wdt(bool enable_reset) +{ + if (enable_reset) { + u32 t; + + /* enable WDT reset output on GPIO 2 */ + t = rt3883_sysc_rr(RT3883_SYSC_REG_SYSCFG1); + t |= RT3883_SYSCFG1_GPIO2_AS_WDT_OUT; + rt3883_sysc_wr(t, RT3883_SYSC_REG_SYSCFG1); + } + + platform_device_register(&rt3883_wdt_device); +} + +static struct resource rt3883_nand_resources[] = { + { + .flags = IORESOURCE_MEM, + .start = RT3883_NANDC_BASE, + .end = RT3883_NANDC_BASE + RT3883_NANDC_SIZE - 1, + }, +}; + +struct ramips_nand_platform_data rt3883_nand_data; +static struct platform_device rt3883_nand_device = { + .name = RAMIPS_NAND_DRIVER_NAME, + .id = -1, + .resource = rt3883_nand_resources, + .num_resources = ARRAY_SIZE(rt3883_nand_resources), + .dev = { + .platform_data = &rt3883_nand_data, + }, +}; + +void __init rt3883_register_nand(void) +{ + platform_device_register(&rt3883_nand_device); +} + +static struct resource rt3883_spi_resources[] = { + { + .flags = IORESOURCE_MEM, + .start = RT3883_SPI_BASE, + .end = RT3883_SPI_BASE + RT3883_SPI_SIZE - 1, + }, +}; + +static struct platform_device rt3883_spi_device = { + .name = "ramips-spi", + .id = 0, + .resource = rt3883_spi_resources, + .num_resources = ARRAY_SIZE(rt3883_spi_resources), +}; + +void __init rt3883_register_spi(struct spi_board_info *info, int n) +{ + spi_register_board_info(info, n); + platform_device_register(&rt3883_spi_device); +} + diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/devices.h b/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/devices.h new file mode 100644 index 0000000000..808bcb2d36 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/devices.h @@ -0,0 +1,34 @@ +/* + * Ralink RT3662/3883 SoC specific platform device definitions + * + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _RT3883_DEVICES_H +#define _RT3883_DEVICES_H + +struct physmap_flash_data; +struct spi_board_info; + +extern struct physmap_flash_data rt3883_flash0_data; +extern struct physmap_flash_data rt3883_flash1_data; +void rt3883_register_pflash(unsigned int id); + +extern struct ramips_nand_platform_data rt3883_nand_data; +void rt3883_register_nand(void); + +extern struct ramips_eth_platform_data rt3883_eth_data; +void rt3883_register_ethernet(void); +void rt3883_register_usbhost(void); + +extern struct rt2x00_platform_data rt3883_wlan_data; +void rt3883_register_wlan(void); +void rt3883_register_wdt(bool enable_reset); + +void rt3883_register_spi(struct spi_board_info *info, int n); + +#endif /* _RT3883_DEVICES_H */ diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/early_printk.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/early_printk.c new file mode 100644 index 0000000000..e3bf7ba339 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/early_printk.c @@ -0,0 +1,29 @@ +/* + * Ralink RT3662/RT3883 SoC early printk support + * + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include + +#include + +#define UART_READ(r) \ + __raw_readl((void __iomem *)(KSEG1ADDR(RT3883_UART1_BASE) + 4 * (r))) + +#define UART_WRITE(r, v) \ + __raw_writel((v), (void __iomem *)(KSEG1ADDR(RT3883_UART1_BASE) + 4 * (r))) + +void prom_putchar(unsigned char ch) +{ + while (((UART_READ(RT3883_UART_REG_LSR)) & UART_LSR_THRE) == 0); + UART_WRITE(RT3883_UART_REG_TX, ch); + while (((UART_READ(RT3883_UART_REG_LSR)) & UART_LSR_THRE) == 0); +} diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/irq.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/irq.c new file mode 100644 index 0000000000..b561fd38cd --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/irq.c @@ -0,0 +1,84 @@ +/* + * Ralink RT3662/RT3883 SoC specific interrupt handling + * + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +static void rt3883_intc_irq_dispatch(void) +{ + u32 pending; + + pending = ramips_intc_get_status(); + + if (pending & RT3883_INTC_INT_TIMER0) + do_IRQ(RT3883_INTC_IRQ_TIMER0); + + else if (pending & RT3883_INTC_INT_TIMER1) + do_IRQ(RT3883_INTC_IRQ_TIMER1); + + else if (pending & RT3883_INTC_INT_UART0) + do_IRQ(RT3883_INTC_IRQ_UART0); + + else if (pending & RT3883_INTC_INT_UART1) + do_IRQ(RT3883_INTC_IRQ_UART1); + + else if (pending & RT3883_INTC_INT_PERFC) + do_IRQ(RT3883_INTC_IRQ_PERFC); + + else if (pending & RT3883_INTC_INT_UHST) + do_IRQ(RT3883_INTC_IRQ_UHST); + + /* TODO: handle PIO interrupts as well */ + + else + spurious_interrupt(); +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned long pending; + + pending = read_c0_status() & read_c0_cause() & ST0_IM; + + if (pending & STATUSF_IP7) + do_IRQ(RT3883_CPU_IRQ_COUNTER); + + else if (pending & STATUSF_IP5) + do_IRQ(RT3883_CPU_IRQ_FE); + + else if (pending & STATUSF_IP6) + do_IRQ(RT3883_CPU_IRQ_WLAN); + + else if (pending & STATUSF_IP4) + do_IRQ(RT3883_CPU_IRQ_PCI); + + else if (pending & STATUSF_IP2) + rt3883_intc_irq_dispatch(); + + else + spurious_interrupt(); +} + +void __init arch_init_irq(void) +{ + mips_cpu_irq_init(); + ramips_intc_irq_init(RT3883_INTC_BASE, RT3883_CPU_IRQ_INTC, + RT3883_INTC_IRQ_BASE); + cp0_perfcount_irq = RT3883_INTC_IRQ_PERFC; +} diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/mach-dir-645.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/mach-dir-645.c new file mode 100644 index 0000000000..825da27f77 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/mach-dir-645.c @@ -0,0 +1,152 @@ +/* + * D-Link DIR-645 board support + * + * Copyright (C) 2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "devices.h" + +#define DIR_645_GPIO_LED_INET 0 +#define DIR_645_GPIO_LED_WPS 26 + +#define DIR_645_GPIO_BUTTON_RESET 9 +#define DIR_645_GPIO_BUTTON_WPS 14 + +#define DIR_645_GPIO_USB_POWER 30 + +#define DIR_645_GPIO_RTL8367_SCK 2 +#define DIR_645_GPIO_RTL8367_SDA 1 + +#define DIR_645_KEYS_POLL_INTERVAL 20 +#define DIR_645_KEYS_DEBOUNCE_INTERVAL (3 * DIR_645_KEYS_POLL_INTERVAL) + +static struct gpio_led dir_645_leds_gpio[] __initdata = { + { + .name = "d-link:green:inet", + .gpio = DIR_645_GPIO_LED_INET, + .active_low = 1, + }, + { + .name = "d-link:green:wps", + .gpio = DIR_645_GPIO_LED_WPS, + .active_low = 1, + }, +}; + +static struct gpio_keys_button dir_645_gpio_buttons[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DIR_645_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR_645_GPIO_BUTTON_RESET, + .active_low = 1, + }, + { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DIR_645_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR_645_GPIO_BUTTON_WPS, + .active_low = 1, + } +}; + +static struct rtl8367_extif_config dir_645_rtl8367_extif1_cfg = { + .txdelay = 1, + .rxdelay = 0, + .mode = RTL8367_EXTIF_MODE_RGMII, + .ability = { + .force_mode = 1, + .txpause = 1, + .rxpause = 1, + .link = 1, + .duplex = 1, + .speed = RTL8367_PORT_SPEED_1000, + } +}; + +static struct rtl8367_platform_data dir_645_rtl8367_data = { + .gpio_sda = DIR_645_GPIO_RTL8367_SDA, + .gpio_sck = DIR_645_GPIO_RTL8367_SCK, + .extif1_cfg = &dir_645_rtl8367_extif1_cfg, +}; + +static struct platform_device dir_645_rtl8367_device = { + .name = RTL8367B_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &dir_645_rtl8367_data, + } +}; + +static struct spi_board_info dir_645_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "m25p80", + } +}; + +static void __init dir_645_gpio_init(void) +{ + rt3883_gpio_init(RT3883_GPIO_MODE_I2C | + RT3883_GPIO_MODE_UART0(RT3883_GPIO_MODE_GPIO) | + RT3883_GPIO_MODE_JTAG | + RT3883_GPIO_MODE_PCI(RT3883_GPIO_MODE_PCI_FNC)); + + gpio_request_one(DIR_645_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); +} + +static void __init dir_645_init(void) +{ + dir_645_gpio_init(); + + rt3883_register_spi(dir_645_spi_info, + ARRAY_SIZE(dir_645_spi_info)); + + ramips_register_gpio_leds(-1, ARRAY_SIZE(dir_645_leds_gpio), + dir_645_leds_gpio); + + ramips_register_gpio_buttons(-1, DIR_645_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dir_645_gpio_buttons), + dir_645_gpio_buttons); + + platform_device_register(&dir_645_rtl8367_device); + + rt3883_wlan_data.disable_5ghz = 1; + rt3883_register_wlan(); + + rt3883_eth_data.speed = SPEED_1000; + rt3883_eth_data.duplex = DUPLEX_FULL; + rt3883_eth_data.tx_fc = 1; + rt3883_eth_data.rx_fc = 1; + rt3883_register_ethernet(); + + rt3883_register_wdt(false); + rt3883_register_usbhost(); +} + +MIPS_MACHINE(RAMIPS_MACH_DIR_645, "DIR-645", "D-Link DIR-645", dir_645_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/mach-omni-emb-hpm.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/mach-omni-emb-hpm.c new file mode 100644 index 0000000000..77ccff624f --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/mach-omni-emb-hpm.c @@ -0,0 +1,157 @@ +/* + * Omnima EMB HPM board support + * + * Copyright (C) 2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "devices.h" + +#define OMNI_EMB_HPM_GPIO_LED_POWER 7 +#define OMNI_EMB_HPM_GPIO_LED_ETH_GREEN 20 +#define OMNI_EMB_HPM_GPIO_LED_ETH_RED 18 +#define OMNI_EMB_HPM_GPIO_LED_STATUS 21 +#define OMNI_EMB_HPM_GPIO_LED_WIFI_GREEN 17 +#define OMNI_EMB_HPM_GPIO_LED_WIFI_RED 19 + +#define OMNI_EMB_HPM_GPIO_BUTTON_RESET 14 + +#define OMNI_EMB_HPM_GPIO_USB0_ENABLE 2 +#define OMNI_EMB_HPM_GPIO_USB1_ENABLE 1 +#define OMNI_EMB_HPM_GPIO_USB0_OC 12 +#define OMNI_EMB_HPM_GPIO_USB1_OC 13 + +#define OMNI_EMB_HPM_KEYS_POLL_INTERVAL 20 +#define OMNI_EMB_HPM_KEYS_DEBOUNCE_INTERVAL (3 * OMNI_EMB_HPM_KEYS_POLL_INTERVAL) + +static struct gpio_led omni_emb_hpm_leds_gpio[] __initdata = { + { + .name = "emb:orange:power", + .gpio = OMNI_EMB_HPM_GPIO_LED_POWER, + .active_low = 1, + }, + { + .name = "emb:green:status", + .gpio = OMNI_EMB_HPM_GPIO_LED_STATUS, + }, + { + .name = "emb:green:eth", + .gpio = OMNI_EMB_HPM_GPIO_LED_ETH_GREEN, + .active_low = 1, + }, + { + .name = "emb:red:eth", + .gpio = OMNI_EMB_HPM_GPIO_LED_ETH_RED, + .active_low = 1, + }, + { + .name = "emb:green:wifi", + .gpio = OMNI_EMB_HPM_GPIO_LED_WIFI_GREEN, + .active_low = 1, + }, + { + .name = "emb:red:wifi", + .gpio = OMNI_EMB_HPM_GPIO_LED_WIFI_RED, + .active_low = 1, + }, +}; + +static struct gpio_keys_button omni_emb_hpm_gpio_buttons[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = OMNI_EMB_HPM_KEYS_DEBOUNCE_INTERVAL, + .gpio = OMNI_EMB_HPM_GPIO_BUTTON_RESET, + .active_low = 1, + }, +}; + +static struct spi_board_info omni_emb_hpm_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "m25p80", + } +}; + + +static void __init omni_emb_hpm_gpio_request(unsigned int gpio, + unsigned long flags, + const char *label, + bool free) +{ + int err; + + err = gpio_request_one(gpio, flags, label); + if (err) { + pr_err("EMB_HPM: can't setup GPIO%u (%s), err=%d\n", + gpio, label, err); + return; + } + + if (free) + gpio_free(gpio); +} + +static void __init omni_emb_hpm_gpio_init(void) +{ + rt3883_gpio_init(RT3883_GPIO_MODE_I2C | + RT3883_GPIO_MODE_UART0(RT3883_GPIO_MODE_GPIO) | + RT3883_GPIO_MODE_JTAG); + + omni_emb_hpm_gpio_request(OMNI_EMB_HPM_GPIO_USB0_ENABLE, + GPIOF_OUT_INIT_HIGH, + "USB0 power", true); + omni_emb_hpm_gpio_request(OMNI_EMB_HPM_GPIO_USB1_ENABLE, + GPIOF_OUT_INIT_HIGH, + "USB1 power", true); + omni_emb_hpm_gpio_request(OMNI_EMB_HPM_GPIO_USB0_OC, + GPIOF_IN, "USB0 OC", false); + omni_emb_hpm_gpio_request(OMNI_EMB_HPM_GPIO_USB1_OC, + GPIOF_IN, "USB1 OC", false); +} + +static void __init omni_emb_hpm_init(void) +{ + omni_emb_hpm_gpio_init(); + + ramips_register_gpio_leds(-1, ARRAY_SIZE(omni_emb_hpm_leds_gpio), + omni_emb_hpm_leds_gpio); + + ramips_register_gpio_buttons(-1, OMNI_EMB_HPM_KEYS_POLL_INTERVAL, + ARRAY_SIZE(omni_emb_hpm_gpio_buttons), + omni_emb_hpm_gpio_buttons); + + rt3883_register_spi(omni_emb_hpm_spi_info, + ARRAY_SIZE(omni_emb_hpm_spi_info)); + + rt3883_register_wlan(); + + rt3883_eth_data.phy_mask = BIT(4); + rt3883_register_ethernet(); + + rt3883_register_wdt(false); + rt3883_register_usbhost(); +} + +MIPS_MACHINE(RAMIPS_MACH_OMNI_EMB_HPM, "OMNI-EMB-HPM", "Omnima EMB HPM", + omni_emb_hpm_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/mach-rt-n56u.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/mach-rt-n56u.c new file mode 100644 index 0000000000..99aa03fe9e --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/mach-rt-n56u.c @@ -0,0 +1,155 @@ +/* + * Asus RT-N56U board support + * + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "devices.h" + +#define RT_N56U_GPIO_LED_POWER 0 +#define RT_N56U_GPIO_LED_LAN 19 +#define RT_N56U_GPIO_LED_USB 24 +#define RT_N56U_GPIO_LED_WAN 27 +#define RT_N56U_GPIO_BUTTON_RESET 13 +#define RT_N56U_GPIO_BUTTON_WPS 26 + +#define RT_N56U_GPIO_RTL8367_SCK 2 +#define RT_N56U_GPIO_RTL8367_SDA 1 + +#define RT_N56U_KEYS_POLL_INTERVAL 20 +#define RT_N56U_KEYS_DEBOUNCE_INTERVAL (3 * RT_N56U_KEYS_POLL_INTERVAL) + +static struct gpio_led rt_n56u_leds_gpio[] __initdata = { + { + .name = "asus:blue:power", + .gpio = RT_N56U_GPIO_LED_POWER, + .active_low = 1, + }, + { + .name = "asus:blue:lan", + .gpio = RT_N56U_GPIO_LED_LAN, + .active_low = 1, + }, + { + .name = "asus:blue:wan", + .gpio = RT_N56U_GPIO_LED_WAN, + .active_low = 1, + }, + { + .name = "asus:blue:usb", + .gpio = RT_N56U_GPIO_LED_USB, + .active_low = 1, + }, +}; + +static struct gpio_keys_button rt_n56u_gpio_buttons[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = RT_N56U_KEYS_DEBOUNCE_INTERVAL, + .gpio = RT_N56U_GPIO_BUTTON_RESET, + .active_low = 1, + }, + { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = RT_N56U_KEYS_DEBOUNCE_INTERVAL, + .gpio = RT_N56U_GPIO_BUTTON_WPS, + .active_low = 1, + } +}; + +static struct rtl8367_extif_config rt_n56u_rtl8367_extif1_cfg = { + .txdelay = 1, + .rxdelay = 0, + .mode = RTL8367_EXTIF_MODE_RGMII, + .ability = { + .force_mode = 1, + .txpause = 1, + .rxpause = 1, + .link = 1, + .duplex = 1, + .speed = RTL8367_PORT_SPEED_1000, + } +}; + +static struct rtl8367_platform_data rt_n56u_rtl8367_data = { + .gpio_sda = RT_N56U_GPIO_RTL8367_SDA, + .gpio_sck = RT_N56U_GPIO_RTL8367_SCK, + .extif1_cfg = &rt_n56u_rtl8367_extif1_cfg, +}; + +static struct platform_device rt_n56u_rtl8367_device = { + .name = RTL8367_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &rt_n56u_rtl8367_data, + } +}; + +static struct rt2x00_platform_data rt_n56u_pci_wlan_data = { + .eeprom_file_name = "rt2x00pci_1_0.eeprom", +}; + +static int rt_n56u_pci_plat_dev_init(struct pci_dev *dev) +{ + if (dev->bus->number == 1 && PCI_SLOT(dev->devfn) == 0) + dev->dev.platform_data = &rt_n56u_pci_wlan_data; + + return 0; +} + +static void __init rt_n56u_init(void) +{ + rt3883_gpio_init(RT3883_GPIO_MODE_I2C | + RT3883_GPIO_MODE_UART0(RT3883_GPIO_MODE_GPIO) | + RT3883_GPIO_MODE_JTAG | + RT3883_GPIO_MODE_PCI(RT3883_GPIO_MODE_PCI_FNC)); + + rt3883_register_pflash(0); + + ramips_register_gpio_leds(-1, ARRAY_SIZE(rt_n56u_leds_gpio), + rt_n56u_leds_gpio); + + ramips_register_gpio_buttons(-1, RT_N56U_KEYS_POLL_INTERVAL, + ARRAY_SIZE(rt_n56u_gpio_buttons), + rt_n56u_gpio_buttons); + + platform_device_register(&rt_n56u_rtl8367_device); + + rt3883_wlan_data.disable_2ghz = 1; + rt3883_register_wlan(); + + rt3883_eth_data.speed = SPEED_1000; + rt3883_eth_data.duplex = DUPLEX_FULL; + rt3883_eth_data.tx_fc = 1; + rt3883_eth_data.rx_fc = 1; + rt3883_register_ethernet(); + + rt3883_register_wdt(false); + rt3883_register_usbhost(); + rt3883_pci_set_plat_dev_init(rt_n56u_pci_plat_dev_init); + rt3883_pci_init(RT3883_PCI_MODE_PCIE); +} + +MIPS_MACHINE(RAMIPS_MACH_RT_N56U, "RT-N56U", "Asus RT-N56U", rt_n56u_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/mach-tew-691gr.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/mach-tew-691gr.c new file mode 100644 index 0000000000..7b553ab6b2 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/mach-tew-691gr.c @@ -0,0 +1,103 @@ +/* + * TRENDnet TEW-691GR board support + * + * Copyright (C) 2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "devices.h" + +#define TEW_691GR_GPIO_LED_WPS_GREEN 9 + +#define TEW_691GR_GPIO_BUTTON_RESET 10 +#define TEW_691GR_GPIO_BUTTON_WPS 26 + +#define TEW_691GR_GPIO_SWITCH_RFKILL 0 + +#define TEW_691GR_KEYS_POLL_INTERVAL 20 +#define TEW_691GR_KEYS_DEBOUNCE_INTERVAL (3 * TEW_691GR_KEYS_POLL_INTERVAL) + +static struct gpio_led tew_691gr_leds_gpio[] __initdata = { + { + .name = "trendnet:green:wps", + .gpio = TEW_691GR_GPIO_LED_WPS_GREEN, + .active_low = 1, + }, +}; + +static struct gpio_keys_button tew_691gr_gpio_buttons[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TEW_691GR_KEYS_DEBOUNCE_INTERVAL, + .gpio = TEW_691GR_GPIO_BUTTON_RESET, + .active_low = 1, + }, + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TEW_691GR_KEYS_DEBOUNCE_INTERVAL, + .gpio = TEW_691GR_GPIO_BUTTON_WPS, + .active_low = 1, + }, + { + .desc = "RFKILL switch", + .type = EV_SW, + .code = KEY_RFKILL, + .debounce_interval = TEW_691GR_KEYS_DEBOUNCE_INTERVAL, + .gpio = TEW_691GR_GPIO_SWITCH_RFKILL, + .active_low = 1, + }, +}; + +static void __init tew_691gr_init(void) +{ + rt3883_gpio_init(RT3883_GPIO_MODE_I2C | + RT3883_GPIO_MODE_SPI | + RT3883_GPIO_MODE_UART0(RT3883_GPIO_MODE_GPIO) | + RT3883_GPIO_MODE_JTAG | + RT3883_GPIO_MODE_PCI(RT3883_GPIO_MODE_PCI_FNC)); + + rt3883_register_pflash(0); + + ramips_register_gpio_leds(-1, ARRAY_SIZE(tew_691gr_leds_gpio), + tew_691gr_leds_gpio); + + ramips_register_gpio_buttons(-1, TEW_691GR_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tew_691gr_gpio_buttons), + tew_691gr_gpio_buttons); + + rt3883_wlan_data.disable_5ghz = 1; + rt3883_register_wlan(); + + rt3883_eth_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + rt3883_eth_data.phy_mask = BIT(0); + rt3883_eth_data.tx_fc = 1; + rt3883_eth_data.rx_fc = 1; + rt3883_register_ethernet(); + + rt3883_register_wdt(false); +} + +MIPS_MACHINE(RAMIPS_MACH_TEW_691GR, "TEW-691GR", "TRENDnet TEW-691GR", + tew_691gr_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/mach-tew-692gr.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/mach-tew-692gr.c new file mode 100644 index 0000000000..59b520a371 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/mach-tew-692gr.c @@ -0,0 +1,147 @@ +/* + * TRENDnet TEW-692GR board support + * + * Copyright (C) 2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "devices.h" + +#define TEW_692GR_GPIO_LED_WPS_ORANGE 9 +#define TEW_692GR_GPIO_LED_WPS_GREEN 28 + +#define TEW_692GR_GPIO_BUTTON_RESET 10 +#define TEW_692GR_GPIO_BUTTON_WPS 26 + +#define TEW_692GR_KEYS_POLL_INTERVAL 20 +#define TEW_692GR_KEYS_DEBOUNCE_INTERVAL (3 * TEW_692GR_KEYS_POLL_INTERVAL) + +static struct gpio_led tew_692gr_leds_gpio[] __initdata = { + { + .name = "trendnet:orange:wps", + .gpio = TEW_692GR_GPIO_LED_WPS_ORANGE, + .active_low = 1, + }, + { + .name = "trendnet:green:wps", + .gpio = TEW_692GR_GPIO_LED_WPS_GREEN, + .active_low = 1, + }, +}; + +static struct gpio_keys_button tew_692gr_gpio_buttons[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TEW_692GR_KEYS_DEBOUNCE_INTERVAL, + .gpio = TEW_692GR_GPIO_BUTTON_RESET, + .active_low = 1, + }, + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TEW_692GR_KEYS_DEBOUNCE_INTERVAL, + .gpio = TEW_692GR_GPIO_BUTTON_WPS, + .active_low = 1, + }, +}; + +static struct ar8327_pad_cfg tew_692gr_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_pad_cfg tew_692gr_ar8327_pad6_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .rxclk_delay_en = true, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL0, +}; + +static struct ar8327_led_cfg tew_692gr_ar8327_led_cfg = { + .led_ctrl0 = 0xc437c437, + .led_ctrl1 = 0xc337c337, + .led_ctrl2 = 0x00000000, + .led_ctrl3 = 0x03ffff00, + .open_drain = false, +}; + +static struct ar8327_platform_data tew_692gr_ar8327_data = { + .pad0_cfg = &tew_692gr_ar8327_pad0_cfg, + .pad6_cfg = &tew_692gr_ar8327_pad6_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .led_cfg = &tew_692gr_ar8327_led_cfg, +}; + +static struct mdio_board_info tew_692gr_mdio0_info[] = { + { + .bus_id = "ramips_mdio", + .phy_addr = 0, + .platform_data = &tew_692gr_ar8327_data, + }, +}; + +static void __init tew_692gr_init(void) +{ + rt3883_gpio_init(RT3883_GPIO_MODE_I2C | + RT3883_GPIO_MODE_SPI | + RT3883_GPIO_MODE_UART0(RT3883_GPIO_MODE_GPIO) | + RT3883_GPIO_MODE_JTAG | + RT3883_GPIO_MODE_PCI(RT3883_GPIO_MODE_PCI_FNC)); + + rt3883_register_pflash(0); + + ramips_register_gpio_leds(-1, ARRAY_SIZE(tew_692gr_leds_gpio), + tew_692gr_leds_gpio); + + ramips_register_gpio_buttons(-1, TEW_692GR_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tew_692gr_gpio_buttons), + tew_692gr_gpio_buttons); + + rt3883_wlan_data.disable_5ghz = 1; + rt3883_register_wlan(); + + mdiobus_register_board_info(tew_692gr_mdio0_info, + ARRAY_SIZE(tew_692gr_mdio0_info)); + + rt3883_eth_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + rt3883_eth_data.phy_mask = BIT(0); + rt3883_eth_data.tx_fc = 1; + rt3883_eth_data.rx_fc = 1; + rt3883_register_ethernet(); + + rt3883_register_wdt(false); + + rt3883_pci_init(RT3883_PCI_MODE_PCIE); +} + +MIPS_MACHINE(RAMIPS_MACH_TEW_692GR, "TEW-692GR", "TRENDnet TEW-692GR", + tew_692gr_init); diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/rt3883.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/rt3883.c new file mode 100644 index 0000000000..e397b854ea --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/rt3883.c @@ -0,0 +1,216 @@ +/* + * Ralink RT3662/RT3883 SoC specific setup + * + * Copyright (C) 2011-2012 Gabor Juhos + * + * Parts of this file are based on Ralink's 2.6.21 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include +#include +#include + +void __iomem * rt3883_sysc_base; +void __iomem * rt3883_memc_base; + +void __init ramips_soc_prom_init(void) +{ + void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE); + u32 n0; + u32 n1; + u32 id; + + n0 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID0_3); + n1 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID4_7); + id = __raw_readl(sysc + RT3883_SYSC_REG_REVID); + + snprintf(ramips_sys_type, RAMIPS_SYS_TYPE_LEN, + "Ralink %c%c%c%c%c%c%c%c ver:%u eco:%u", + (char) (n0 & 0xff), (char) ((n0 >> 8) & 0xff), + (char) ((n0 >> 16) & 0xff), (char) ((n0 >> 24) & 0xff), + (char) (n1 & 0xff), (char) ((n1 >> 8) & 0xff), + (char) ((n1 >> 16) & 0xff), (char) ((n1 >> 24) & 0xff), + (id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK, + (id & RT3883_REVID_ECO_ID_MASK)); + + ramips_mem_base = RT3883_SDRAM_BASE; + ramips_mem_size_min = RT3883_MEM_SIZE_MIN; + ramips_mem_size_max = RT3883_MEM_SIZE_MAX; +} + +static struct ramips_gpio_chip rt3883_gpio_chips[] = { + { + .chip = { + .label = "RT3883-GPIO0", + .base = 0, + .ngpio = 24, + }, + .regs = { + [RAMIPS_GPIO_REG_INT] = 0x00, + [RAMIPS_GPIO_REG_EDGE] = 0x04, + [RAMIPS_GPIO_REG_RENA] = 0x08, + [RAMIPS_GPIO_REG_FENA] = 0x0c, + [RAMIPS_GPIO_REG_DATA] = 0x20, + [RAMIPS_GPIO_REG_DIR] = 0x24, + [RAMIPS_GPIO_REG_POL] = 0x28, + [RAMIPS_GPIO_REG_SET] = 0x2c, + [RAMIPS_GPIO_REG_RESET] = 0x30, + [RAMIPS_GPIO_REG_TOGGLE] = 0x34, + }, + .map_base = RT3883_PIO_BASE, + .map_size = RT3883_PIO_SIZE, + }, + { + .chip = { + .label = "RT3883-GPIO1", + .base = 24, + .ngpio = 16, + }, + .regs = { + [RAMIPS_GPIO_REG_INT] = 0x38, + [RAMIPS_GPIO_REG_EDGE] = 0x3c, + [RAMIPS_GPIO_REG_RENA] = 0x40, + [RAMIPS_GPIO_REG_FENA] = 0x44, + [RAMIPS_GPIO_REG_DATA] = 0x48, + [RAMIPS_GPIO_REG_DIR] = 0x4c, + [RAMIPS_GPIO_REG_POL] = 0x50, + [RAMIPS_GPIO_REG_SET] = 0x54, + [RAMIPS_GPIO_REG_RESET] = 0x58, + [RAMIPS_GPIO_REG_TOGGLE] = 0x5c, + }, + .map_base = RT3883_PIO_BASE, + .map_size = RT3883_PIO_SIZE, + }, + { + .chip = { + .label = "RT3883-GPIO2", + .base = 40, + .ngpio = 32, + }, + .regs = { + [RAMIPS_GPIO_REG_INT] = 0x60, + [RAMIPS_GPIO_REG_EDGE] = 0x64, + [RAMIPS_GPIO_REG_RENA] = 0x68, + [RAMIPS_GPIO_REG_FENA] = 0x6c, + [RAMIPS_GPIO_REG_DATA] = 0x70, + [RAMIPS_GPIO_REG_DIR] = 0x74, + [RAMIPS_GPIO_REG_POL] = 0x78, + [RAMIPS_GPIO_REG_SET] = 0x7c, + [RAMIPS_GPIO_REG_RESET] = 0x80, + [RAMIPS_GPIO_REG_TOGGLE] = 0x84, + }, + .map_base = RT3883_PIO_BASE, + .map_size = RT3883_PIO_SIZE, + }, + { + .chip = { + .label = "RT3883-GPIO3", + .base = 72, + .ngpio = 24, + }, + .regs = { + [RAMIPS_GPIO_REG_INT] = 0x88, + [RAMIPS_GPIO_REG_EDGE] = 0x8c, + [RAMIPS_GPIO_REG_RENA] = 0x90, + [RAMIPS_GPIO_REG_FENA] = 0x94, + [RAMIPS_GPIO_REG_DATA] = 0x98, + [RAMIPS_GPIO_REG_DIR] = 0x9c, + [RAMIPS_GPIO_REG_POL] = 0xa0, + [RAMIPS_GPIO_REG_SET] = 0xa4, + [RAMIPS_GPIO_REG_RESET] = 0xa8, + [RAMIPS_GPIO_REG_TOGGLE] = 0xac, + }, + .map_base = RT3883_PIO_BASE, + .map_size = RT3883_PIO_SIZE, + }, +}; + +static struct ramips_gpio_data rt3883_gpio_data = { + .chips = rt3883_gpio_chips, + .num_chips = ARRAY_SIZE(rt3883_gpio_chips), +}; + +static void rt3883_gpio_reserve(int first, int last) +{ + for (; first <= last; first++) + gpio_request(first, "reserved"); +} + +void __init rt3883_gpio_init(u32 mode) +{ + u32 t; + + rt3883_sysc_wr(mode, RT3883_SYSC_REG_GPIO_MODE); + + ramips_gpio_init(&rt3883_gpio_data); + if ((mode & RT3883_GPIO_MODE_I2C) == 0) + rt3883_gpio_reserve(RT3883_GPIO_I2C_SD, RT3883_GPIO_I2C_SCLK); + + if ((mode & RT3883_GPIO_MODE_SPI) == 0) + rt3883_gpio_reserve(RT3883_GPIO_SPI_CS0, RT3883_GPIO_SPI_MISO); + + t = mode >> RT3883_GPIO_MODE_UART0_SHIFT; + t &= RT3883_GPIO_MODE_UART0_MASK; + switch (t) { + case RT3883_GPIO_MODE_UARTF: + case RT3883_GPIO_MODE_PCM_UARTF: + case RT3883_GPIO_MODE_PCM_I2S: + case RT3883_GPIO_MODE_I2S_UARTF: + rt3883_gpio_reserve(RT3883_GPIO_7, RT3883_GPIO_14); + break; + case RT3883_GPIO_MODE_PCM_GPIO: + rt3883_gpio_reserve(RT3883_GPIO_11, RT3883_GPIO_14); + break; + case RT3883_GPIO_MODE_GPIO_UARTF: + case RT3883_GPIO_MODE_GPIO_I2S: + rt3883_gpio_reserve(RT3883_GPIO_7, RT3883_GPIO_10); + break; + } + + if ((mode & RT3883_GPIO_MODE_UART1) == 0) + rt3883_gpio_reserve(RT3883_GPIO_UART1_TXD, + RT3883_GPIO_UART1_RXD); + + if ((mode & RT3883_GPIO_MODE_JTAG) == 0) + rt3883_gpio_reserve(RT3883_GPIO_JTAG_TDO, + RT3883_GPIO_JTAG_TCLK); + + if ((mode & RT3883_GPIO_MODE_MDIO) == 0) + rt3883_gpio_reserve(RT3883_GPIO_MDIO_MDC, + RT3883_GPIO_MDIO_MDIO); + + if ((mode & RT3883_GPIO_MODE_GE1) == 0) + rt3883_gpio_reserve(RT3883_GPIO_GE1_TXD0, + RT3883_GPIO_GE1_RXCLK); + + if ((mode & RT3883_GPIO_MODE_GE2) == 0) + rt3883_gpio_reserve(RT3883_GPIO_GE2_TXD0, + RT3883_GPIO_GE2_RXCLK); + + t = mode >> RT3883_GPIO_MODE_PCI_SHIFT; + t &= RT3883_GPIO_MODE_PCI_MASK; + if (t != RT3883_GPIO_MODE_PCI_GPIO) + rt3883_gpio_reserve(RT3883_GPIO_PCI_AD0, + RT3883_GPIO_PCI_AD31); + + t = mode >> RT3883_GPIO_MODE_LNA_A_SHIFT; + t &= RT3883_GPIO_MODE_LNA_A_MASK; + if (t != RT3883_GPIO_MODE_LNA_A_GPIO) + rt3883_gpio_reserve(RT3883_GPIO_LNA_PE_A0, + RT3883_GPIO_LNA_PE_A2); + + t = mode >> RT3883_GPIO_MODE_LNA_G_SHIFT; + t &= RT3883_GPIO_MODE_LNA_G_MASK; + if (t != RT3883_GPIO_MODE_LNA_G_GPIO) + rt3883_gpio_reserve(RT3883_GPIO_LNA_PE_G0, + RT3883_GPIO_LNA_PE_G2); +} diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/setup.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/setup.c new file mode 100644 index 0000000000..6e037a7291 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt3883/setup.c @@ -0,0 +1,88 @@ +/* + * Ralink RT3662/RT3883 SoC specific setup + * + * Copyright (C) 2011-2012 Gabor Juhos + * + * Parts of this file are based on Ralink's 2.6.21 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include "common.h" + +static void rt3883_restart(char *command) +{ + rt3883_sysc_wr(RT3883_RSTCTRL_SYS, RT3883_SYSC_REG_RSTCTRL); + while (1) + if (cpu_wait) + cpu_wait(); +} + +static void rt3883_halt(void) +{ + while (1) + if (cpu_wait) + cpu_wait(); +} + +unsigned int __cpuinit get_c0_compare_irq(void) +{ + return CP0_LEGACY_COMPARE_IRQ; +} + +void __init ramips_soc_setup(void) +{ + struct clk *clk; + + rt3883_sysc_base = ioremap_nocache(RT3883_SYSC_BASE, PAGE_SIZE); + rt3883_memc_base = ioremap_nocache(RT3883_MEMC_BASE, PAGE_SIZE); + + rt3883_clocks_init(); + + clk = clk_get(NULL, "cpu"); + if (IS_ERR(clk)) + panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); + + printk(KERN_INFO "%s running at %lu.%02lu MHz\n", ramips_sys_type, + clk_get_rate(clk) / 1000000, + (clk_get_rate(clk) % 1000000) * 100 / 1000000); + + _machine_restart = rt3883_restart; + _machine_halt = rt3883_halt; + pm_power_off = rt3883_halt; + + clk = clk_get(NULL, "uart"); + if (IS_ERR(clk)) + panic("unable to get UART clock, err=%ld", PTR_ERR(clk)); + + ramips_early_serial_setup(0, RT3883_UART0_BASE, clk_get_rate(clk), + RT3883_INTC_IRQ_UART0); + ramips_early_serial_setup(1, RT3883_UART1_BASE, clk_get_rate(clk), + RT3883_INTC_IRQ_UART1); +} + +void __init plat_time_init(void) +{ + struct clk *clk; + + clk = clk_get(NULL, "cpu"); + if (IS_ERR(clk)) + panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); + + mips_hpt_frequency = clk_get_rate(clk) / 2; +} diff --git a/target/linux/ramips/files-3.7/drivers/net/ethernet/ramips/Kconfig b/target/linux/ramips/files-3.7/drivers/net/ethernet/ramips/Kconfig new file mode 100644 index 0000000000..1bc4c2bb08 --- /dev/null +++ b/target/linux/ramips/files-3.7/drivers/net/ethernet/ramips/Kconfig @@ -0,0 +1,18 @@ +config NET_RAMIPS + tristate "Ralink RT288X/RT3X5X/RT3662/RT3883 ethernet driver" + depends on MIPS_RALINK + select PHYLIB if (SOC_RT288X || SOC_RT3883) + select SWCONFIG if SOC_RT305X + help + This driver supports the etehrnet mac inside the ralink wisocs + +if NET_RAMIPS + +config NET_RAMIPS_DEBUG + bool "Enable debug messages in the Ralink ethernet driver" + +config NET_RAMIPS_DEBUG_FS + bool "Enable debugfs support for the Ralink ethernet driver" + depends on DEBUG_FS + +endif diff --git a/target/linux/ramips/files-3.7/drivers/net/ethernet/ramips/Makefile b/target/linux/ramips/files-3.7/drivers/net/ethernet/ramips/Makefile new file mode 100644 index 0000000000..22c460d4df --- /dev/null +++ b/target/linux/ramips/files-3.7/drivers/net/ethernet/ramips/Makefile @@ -0,0 +1,9 @@ +# +# Makefile for the Ramips SoCs built-in ethernet macs +# + +ramips-y += ramips_main.o + +ramips-$(CONFIG_NET_RAMIPS_DEBUG_FS) += ramips_debugfs.o + +obj-$(CONFIG_NET_RAMIPS) += ramips.o diff --git a/target/linux/ramips/files-3.7/drivers/net/ethernet/ramips/ramips_debugfs.c b/target/linux/ramips/files-3.7/drivers/net/ethernet/ramips/ramips_debugfs.c new file mode 100644 index 0000000000..20afcf5028 --- /dev/null +++ b/target/linux/ramips/files-3.7/drivers/net/ethernet/ramips/ramips_debugfs.c @@ -0,0 +1,127 @@ +/* + * Ralink SoC ethernet driver debugfs code + * + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include "ramips_eth.h" + +static struct dentry *raeth_debugfs_root; + +static int raeth_debugfs_generic_open(struct inode *inode, struct file *file) +{ + file->private_data = inode->i_private; + return 0; +} + +void raeth_debugfs_update_int_stats(struct raeth_priv *re, u32 status) +{ + re->debug.int_stats.total += !!status; + + re->debug.int_stats.rx_delayed += !!(status & RAMIPS_RX_DLY_INT); + re->debug.int_stats.rx_done0 += !!(status & RAMIPS_RX_DONE_INT0); + re->debug.int_stats.rx_coherent += !!(status & RAMIPS_RX_COHERENT); + + re->debug.int_stats.tx_delayed += !!(status & RAMIPS_TX_DLY_INT); + re->debug.int_stats.tx_done0 += !!(status & RAMIPS_TX_DONE_INT0); + re->debug.int_stats.tx_done1 += !!(status & RAMIPS_TX_DONE_INT1); + re->debug.int_stats.tx_done2 += !!(status & RAMIPS_TX_DONE_INT2); + re->debug.int_stats.tx_done3 += !!(status & RAMIPS_TX_DONE_INT3); + re->debug.int_stats.tx_coherent += !!(status & RAMIPS_TX_COHERENT); + + re->debug.int_stats.pse_fq_empty += !!(status & RAMIPS_PSE_FQ_EMPTY); + re->debug.int_stats.pse_p0_fc += !!(status & RAMIPS_PSE_P0_FC); + re->debug.int_stats.pse_p1_fc += !!(status & RAMIPS_PSE_P1_FC); + re->debug.int_stats.pse_p2_fc += !!(status & RAMIPS_PSE_P2_FC); + re->debug.int_stats.pse_buf_drop += !!(status & RAMIPS_PSE_BUF_DROP); +} + +static ssize_t read_file_int_stats(struct file *file, char __user *user_buf, + size_t count, loff_t *ppos) +{ +#define PR_INT_STAT(_label, _field) \ + len += snprintf(buf + len, sizeof(buf) - len, \ + "%-18s: %10lu\n", _label, re->debug.int_stats._field); + + struct raeth_priv *re = file->private_data; + char buf[512]; + unsigned int len = 0; + unsigned long flags; + + spin_lock_irqsave(&re->page_lock, flags); + + PR_INT_STAT("RX Delayed", rx_delayed); + PR_INT_STAT("RX Done 0", rx_done0); + PR_INT_STAT("RX Coherent", rx_coherent); + + PR_INT_STAT("TX Delayed", tx_delayed); + PR_INT_STAT("TX Done 0", tx_done0); + PR_INT_STAT("TX Done 1", tx_done1); + PR_INT_STAT("TX Done 2", tx_done2); + PR_INT_STAT("TX Done 3", tx_done3); + PR_INT_STAT("TX Coherent", tx_coherent); + + PR_INT_STAT("PSE FQ empty", pse_fq_empty); + PR_INT_STAT("CDMA Flow control", pse_p0_fc); + PR_INT_STAT("GDMA1 Flow control", pse_p1_fc); + PR_INT_STAT("GDMA2 Flow control", pse_p2_fc); + PR_INT_STAT("PSE discard", pse_buf_drop); + + len += snprintf(buf + len, sizeof(buf) - len, "\n"); + PR_INT_STAT("Total", total); + + spin_unlock_irqrestore(&re->page_lock, flags); + + return simple_read_from_buffer(user_buf, count, ppos, buf, len); +#undef PR_INT_STAT +} + +static const struct file_operations raeth_fops_int_stats = { + .open = raeth_debugfs_generic_open, + .read = read_file_int_stats, + .owner = THIS_MODULE +}; + +void raeth_debugfs_exit(struct raeth_priv *re) +{ + debugfs_remove_recursive(re->debug.debugfs_dir); +} + +int raeth_debugfs_init(struct raeth_priv *re) +{ + re->debug.debugfs_dir = debugfs_create_dir(re->netdev->name, + raeth_debugfs_root); + if (!re->debug.debugfs_dir) + return -ENOMEM; + + debugfs_create_file("int_stats", S_IRUGO, re->debug.debugfs_dir, + re, &raeth_fops_int_stats); + + return 0; +} + +int raeth_debugfs_root_init(void) +{ + if (raeth_debugfs_root) + return -EBUSY; + + raeth_debugfs_root = debugfs_create_dir("raeth", NULL); + if (!raeth_debugfs_root) + return -ENOENT; + + return 0; +} + +void raeth_debugfs_root_exit(void) +{ + debugfs_remove(raeth_debugfs_root); + raeth_debugfs_root = NULL; +} diff --git a/target/linux/ramips/files-3.7/drivers/net/ethernet/ramips/ramips_esw.c b/target/linux/ramips/files-3.7/drivers/net/ethernet/ramips/ramips_esw.c new file mode 100644 index 0000000000..d3150d7a6f --- /dev/null +++ b/target/linux/ramips/files-3.7/drivers/net/ethernet/ramips/ramips_esw.c @@ -0,0 +1,1132 @@ +#include +#include +#include + +#include +#include + +/* + * HW limitations for this switch: + * - No large frame support (PKT_MAX_LEN at most 1536) + * - Can't have untagged vlan and tagged vlan on one port at the same time, + * though this might be possible using the undocumented PPE. + */ + +#define RT305X_ESW_REG_FCT0 0x08 +#define RT305X_ESW_REG_PFC1 0x14 +#define RT305X_ESW_REG_ATS 0x24 +#define RT305X_ESW_REG_ATS0 0x28 +#define RT305X_ESW_REG_ATS1 0x2c +#define RT305X_ESW_REG_ATS2 0x30 +#define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n)) +#define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n)) +#define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n)) +#define RT305X_ESW_REG_POA 0x80 +#define RT305X_ESW_REG_FPA 0x84 +#define RT305X_ESW_REG_SOCPC 0x8c +#define RT305X_ESW_REG_POC0 0x90 +#define RT305X_ESW_REG_POC1 0x94 +#define RT305X_ESW_REG_POC2 0x98 +#define RT305X_ESW_REG_SGC 0x9c +#define RT305X_ESW_REG_STRT 0xa0 +#define RT305X_ESW_REG_PCR0 0xc0 +#define RT305X_ESW_REG_PCR1 0xc4 +#define RT305X_ESW_REG_FPA2 0xc8 +#define RT305X_ESW_REG_FCT2 0xcc +#define RT305X_ESW_REG_SGC2 0xe4 +#define RT305X_ESW_REG_P0LED 0xa4 +#define RT305X_ESW_REG_P1LED 0xa8 +#define RT305X_ESW_REG_P2LED 0xac +#define RT305X_ESW_REG_P3LED 0xb0 +#define RT305X_ESW_REG_P4LED 0xb4 +#define RT305X_ESW_REG_P0PC 0xe8 +#define RT305X_ESW_REG_P1PC 0xec +#define RT305X_ESW_REG_P2PC 0xf0 +#define RT305X_ESW_REG_P3PC 0xf4 +#define RT305X_ESW_REG_P4PC 0xf8 +#define RT305X_ESW_REG_P5PC 0xfc + +#define RT305X_ESW_LED_LINK 0 +#define RT305X_ESW_LED_100M 1 +#define RT305X_ESW_LED_DUPLEX 2 +#define RT305X_ESW_LED_ACTIVITY 3 +#define RT305X_ESW_LED_COLLISION 4 +#define RT305X_ESW_LED_LINKACT 5 +#define RT305X_ESW_LED_DUPLCOLL 6 +#define RT305X_ESW_LED_10MACT 7 +#define RT305X_ESW_LED_100MACT 8 +/* Additional led states not in datasheet: */ +#define RT305X_ESW_LED_BLINK 10 +#define RT305X_ESW_LED_ON 12 + +#define RT305X_ESW_LINK_S 25 +#define RT305X_ESW_DUPLEX_S 9 +#define RT305X_ESW_SPD_S 0 + +#define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16 +#define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13) +#define RT305X_ESW_PCR0_CPU_PHY_REG_S 8 + +#define RT305X_ESW_PCR1_WT_DONE BIT(0) + +#define RT305X_ESW_ATS_TIMEOUT (5 * HZ) +#define RT305X_ESW_PHY_TIMEOUT (5 * HZ) + +#define RT305X_ESW_PVIDC_PVID_M 0xfff +#define RT305X_ESW_PVIDC_PVID_S 12 + +#define RT305X_ESW_VLANI_VID_M 0xfff +#define RT305X_ESW_VLANI_VID_S 12 + +#define RT305X_ESW_VMSC_MSC_M 0xff +#define RT305X_ESW_VMSC_MSC_S 8 + +#define RT305X_ESW_SOCPC_DISUN2CPU_S 0 +#define RT305X_ESW_SOCPC_DISMC2CPU_S 8 +#define RT305X_ESW_SOCPC_DISBC2CPU_S 16 +#define RT305X_ESW_SOCPC_CRC_PADDING BIT(25) + +#define RT305X_ESW_POC0_EN_BP_S 0 +#define RT305X_ESW_POC0_EN_FC_S 8 +#define RT305X_ESW_POC0_DIS_RMC2CPU_S 16 +#define RT305X_ESW_POC0_DIS_PORT_M 0x7f +#define RT305X_ESW_POC0_DIS_PORT_S 23 + +#define RT305X_ESW_POC2_UNTAG_EN_M 0xff +#define RT305X_ESW_POC2_UNTAG_EN_S 0 +#define RT305X_ESW_POC2_ENAGING_S 8 +#define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16 + +#define RT305X_ESW_SGC2_DOUBLE_TAG_M 0x7f +#define RT305X_ESW_SGC2_DOUBLE_TAG_S 0 +#define RT305X_ESW_SGC2_LAN_PMAP_M 0x3f +#define RT305X_ESW_SGC2_LAN_PMAP_S 24 + +#define RT305X_ESW_PFC1_EN_VLAN_M 0xff +#define RT305X_ESW_PFC1_EN_VLAN_S 16 +#define RT305X_ESW_PFC1_EN_TOS_S 24 + +#define RT305X_ESW_VLAN_NONE 0xfff + +#define RT305X_ESW_PORT0 0 +#define RT305X_ESW_PORT1 1 +#define RT305X_ESW_PORT2 2 +#define RT305X_ESW_PORT3 3 +#define RT305X_ESW_PORT4 4 +#define RT305X_ESW_PORT5 5 +#define RT305X_ESW_PORT6 6 + +#define RT305X_ESW_PORTS_NONE 0 + +#define RT305X_ESW_PMAP_LLLLLL 0x3f +#define RT305X_ESW_PMAP_LLLLWL 0x2f +#define RT305X_ESW_PMAP_WLLLLL 0x3e + +#define RT305X_ESW_PORTS_INTERNAL \ + (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \ + BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \ + BIT(RT305X_ESW_PORT4)) + +#define RT305X_ESW_PORTS_NOCPU \ + (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5)) + +#define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6) + +#define RT305X_ESW_PORTS_ALL \ + (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU) + +#define RT305X_ESW_NUM_VLANS 16 +#define RT305X_ESW_NUM_VIDS 4096 +#define RT305X_ESW_NUM_PORTS 7 +#define RT305X_ESW_NUM_LANWAN 6 +#define RT305X_ESW_NUM_LEDS 5 + +enum { + /* Global attributes. */ + RT305X_ESW_ATTR_ENABLE_VLAN, + RT305X_ESW_ATTR_ALT_VLAN_DISABLE, + /* Port attributes. */ + RT305X_ESW_ATTR_PORT_DISABLE, + RT305X_ESW_ATTR_PORT_DOUBLETAG, + RT305X_ESW_ATTR_PORT_UNTAG, + RT305X_ESW_ATTR_PORT_LED, + RT305X_ESW_ATTR_PORT_LAN, + RT305X_ESW_ATTR_PORT_RECV_BAD, + RT305X_ESW_ATTR_PORT_RECV_GOOD, +}; + +struct rt305x_esw_port { + bool disable; + bool doubletag; + bool untag; + u8 led; + u16 pvid; +}; + +struct rt305x_esw_vlan { + u8 ports; + u16 vid; +}; + +struct rt305x_esw { + void __iomem *base; + struct rt305x_esw_platform_data *pdata; + /* Protects against concurrent register rmw operations. */ + spinlock_t reg_rw_lock; + + struct switch_dev swdev; + bool global_vlan_enable; + bool alt_vlan_disable; + struct rt305x_esw_vlan vlans[RT305X_ESW_NUM_VLANS]; + struct rt305x_esw_port ports[RT305X_ESW_NUM_PORTS]; + +}; + +static inline void +rt305x_esw_wr(struct rt305x_esw *esw, u32 val, unsigned reg) +{ + __raw_writel(val, esw->base + reg); +} + +static inline u32 +rt305x_esw_rr(struct rt305x_esw *esw, unsigned reg) +{ + return __raw_readl(esw->base + reg); +} + +static inline void +rt305x_esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask, + unsigned long val) +{ + unsigned long t; + + t = __raw_readl(esw->base + reg) & ~mask; + __raw_writel(t | val, esw->base + reg); +} + +static void +rt305x_esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask, + unsigned long val) +{ + unsigned long flags; + + spin_lock_irqsave(&esw->reg_rw_lock, flags); + rt305x_esw_rmw_raw(esw, reg, mask, val); + spin_unlock_irqrestore(&esw->reg_rw_lock, flags); +} + +static u32 +rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register, + u32 write_data) +{ + unsigned long t_start = jiffies; + int ret = 0; + + while (1) { + if (!(rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) & + RT305X_ESW_PCR1_WT_DONE)) + break; + if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) { + ret = 1; + goto out; + } + } + + write_data &= 0xffff; + rt305x_esw_wr(esw, + (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) | + (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) | + (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD, + RT305X_ESW_REG_PCR0); + + t_start = jiffies; + while (1) { + if (rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) & + RT305X_ESW_PCR1_WT_DONE) + break; + + if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) { + ret = 1; + break; + } + } +out: + if (ret) + printk(KERN_ERR "ramips_eth: MDIO timeout\n"); + return ret; +} + +static unsigned +rt305x_esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan) +{ + unsigned s; + unsigned val; + + s = RT305X_ESW_VLANI_VID_S * (vlan % 2); + val = rt305x_esw_rr(esw, RT305X_ESW_REG_VLANI(vlan / 2)); + val = (val >> s) & RT305X_ESW_VLANI_VID_M; + + return val; +} + +static void +rt305x_esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid) +{ + unsigned s; + + s = RT305X_ESW_VLANI_VID_S * (vlan % 2); + rt305x_esw_rmw(esw, + RT305X_ESW_REG_VLANI(vlan / 2), + RT305X_ESW_VLANI_VID_M << s, + (vid & RT305X_ESW_VLANI_VID_M) << s); +} + +static unsigned +rt305x_esw_get_pvid(struct rt305x_esw *esw, unsigned port) +{ + unsigned s, val; + + s = RT305X_ESW_PVIDC_PVID_S * (port % 2); + val = rt305x_esw_rr(esw, RT305X_ESW_REG_PVIDC(port / 2)); + return (val >> s) & RT305X_ESW_PVIDC_PVID_M; +} + +static void +rt305x_esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid) +{ + unsigned s; + + s = RT305X_ESW_PVIDC_PVID_S * (port % 2); + rt305x_esw_rmw(esw, + RT305X_ESW_REG_PVIDC(port / 2), + RT305X_ESW_PVIDC_PVID_M << s, + (pvid & RT305X_ESW_PVIDC_PVID_M) << s); +} + +static unsigned +rt305x_esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan) +{ + unsigned s, val; + + s = RT305X_ESW_VMSC_MSC_S * (vlan % 4); + val = rt305x_esw_rr(esw, RT305X_ESW_REG_VMSC(vlan / 4)); + val = (val >> s) & RT305X_ESW_VMSC_MSC_M; + + return val; +} + +static void +rt305x_esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc) +{ + unsigned s; + + s = RT305X_ESW_VMSC_MSC_S * (vlan % 4); + rt305x_esw_rmw(esw, + RT305X_ESW_REG_VMSC(vlan / 4), + RT305X_ESW_VMSC_MSC_M << s, + (msc & RT305X_ESW_VMSC_MSC_M) << s); +} + +static unsigned +rt305x_esw_get_port_disable(struct rt305x_esw *esw) +{ + unsigned reg; + reg = rt305x_esw_rr(esw, RT305X_ESW_REG_POC0); + return (reg >> RT305X_ESW_POC0_DIS_PORT_S) & + RT305X_ESW_POC0_DIS_PORT_M; +} + +static void +rt305x_esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask) +{ + unsigned old_mask; + unsigned enable_mask; + unsigned changed; + int i; + + old_mask = rt305x_esw_get_port_disable(esw); + changed = old_mask ^ disable_mask; + enable_mask = old_mask & disable_mask; + + /* enable before writing to MII */ + rt305x_esw_rmw(esw, RT305X_ESW_REG_POC0, + (RT305X_ESW_POC0_DIS_PORT_M << + RT305X_ESW_POC0_DIS_PORT_S), + enable_mask << RT305X_ESW_POC0_DIS_PORT_S); + + for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) { + if (!(changed & (1 << i))) + continue; + if (disable_mask & (1 << i)) { + /* disable */ + rt305x_mii_write(esw, i, MII_BMCR, + BMCR_PDOWN); + } else { + /* enable */ + rt305x_mii_write(esw, i, MII_BMCR, + BMCR_FULLDPLX | + BMCR_ANENABLE | + BMCR_ANRESTART | + BMCR_SPEED100); + } + } + + /* disable after writing to MII */ + rt305x_esw_rmw(esw, RT305X_ESW_REG_POC0, + (RT305X_ESW_POC0_DIS_PORT_M << + RT305X_ESW_POC0_DIS_PORT_S), + disable_mask << RT305X_ESW_POC0_DIS_PORT_S); +} + +static int +rt305x_esw_apply_config(struct switch_dev *dev); + +static void +rt305x_esw_hw_init(struct rt305x_esw *esw) +{ + int i; + u8 port_disable = 0; + u8 port_map = RT305X_ESW_PMAP_LLLLLL; + + /* vodoo from original driver */ + rt305x_esw_wr(esw, 0xC8A07850, RT305X_ESW_REG_FCT0); + rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_SGC2); + /* Port priority 1 for all ports, vlan enabled. */ + rt305x_esw_wr(esw, 0x00005555 | + (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S), + RT305X_ESW_REG_PFC1); + + /* Enable Back Pressure, and Flow Control */ + rt305x_esw_wr(esw, + ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) | + (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)), + RT305X_ESW_REG_POC0); + + /* Enable Aging, and VLAN TAG removal */ + rt305x_esw_wr(esw, + ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) | + (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)), + RT305X_ESW_REG_POC2); + + rt305x_esw_wr(esw, esw->pdata->reg_initval_fct2, RT305X_ESW_REG_FCT2); + + /* + * 300s aging timer, max packet len 1536, broadcast storm prevention + * disabled, disable collision abort, mac xor48 hash, 10 packet back + * pressure jam, GMII disable was_transmit, back pressure disabled, + * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all + * ports. + */ + rt305x_esw_wr(esw, 0x0008a301, RT305X_ESW_REG_SGC); + + /* Setup SoC Port control register */ + rt305x_esw_wr(esw, + (RT305X_ESW_SOCPC_CRC_PADDING | + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) | + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) | + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)), + RT305X_ESW_REG_SOCPC); + + rt305x_esw_wr(esw, esw->pdata->reg_initval_fpa2, RT305X_ESW_REG_FPA2); + rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_FPA); + + /* Force Link/Activity on ports */ + rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P0LED); + rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P1LED); + rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P2LED); + rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P3LED); + rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P4LED); + + /* Copy disabled port configuration from bootloader setup */ + port_disable = rt305x_esw_get_port_disable(esw); + for (i = 0; i < 6; i++) + esw->ports[i].disable = (port_disable & (1 << i)) != 0; + + rt305x_mii_write(esw, 0, 31, 0x8000); + for (i = 0; i < 5; i++) { + if (esw->ports[i].disable) { + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN); + } else { + rt305x_mii_write(esw, i, MII_BMCR, + BMCR_FULLDPLX | + BMCR_ANENABLE | + BMCR_SPEED100); + } + /* TX10 waveform coefficient */ + rt305x_mii_write(esw, i, 26, 0x1601); + /* TX100/TX10 AD/DA current bias */ + rt305x_mii_write(esw, i, 29, 0x7058); + /* TX100 slew rate control */ + rt305x_mii_write(esw, i, 30, 0x0018); + } + + /* PHY IOT */ + /* select global register */ + rt305x_mii_write(esw, 0, 31, 0x0); + /* tune TP_IDL tail and head waveform */ + rt305x_mii_write(esw, 0, 22, 0x052f); + /* set TX10 signal amplitude threshold to minimum */ + rt305x_mii_write(esw, 0, 17, 0x0fe0); + /* set squelch amplitude to higher threshold */ + rt305x_mii_write(esw, 0, 18, 0x40ba); + /* longer TP_IDL tail length */ + rt305x_mii_write(esw, 0, 14, 0x65); + /* select local register */ + rt305x_mii_write(esw, 0, 31, 0x8000); + + switch (esw->pdata->vlan_config) { + case RT305X_ESW_VLAN_CONFIG_NONE: + port_map = RT305X_ESW_PMAP_LLLLLL; + break; + case RT305X_ESW_VLAN_CONFIG_LLLLW: + port_map = RT305X_ESW_PMAP_LLLLWL; + break; + case RT305X_ESW_VLAN_CONFIG_WLLLL: + port_map = RT305X_ESW_PMAP_WLLLLL; + break; + default: + BUG(); + } + + /* + * Unused HW feature, but still nice to be consistent here... + * This is also exported to userspace ('lan' attribute) so it's + * conveniently usable to decide which ports go into the wan vlan by + * default. + */ + rt305x_esw_rmw(esw, RT305X_ESW_REG_SGC2, + RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S, + port_map << RT305X_ESW_SGC2_LAN_PMAP_S); + + /* make the switch leds blink */ + for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) + esw->ports[i].led = 0x05; + + /* Apply the empty config. */ + rt305x_esw_apply_config(&esw->swdev); +} + +static int +rt305x_esw_apply_config(struct switch_dev *dev) +{ + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); + int i; + u8 disable = 0; + u8 doubletag = 0; + u8 en_vlan = 0; + u8 untag = 0; + + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) { + u32 vid, vmsc; + if (esw->global_vlan_enable) { + vid = esw->vlans[i].vid; + vmsc = esw->vlans[i].ports; + } else { + vid = RT305X_ESW_VLAN_NONE; + vmsc = RT305X_ESW_PORTS_NONE; + } + rt305x_esw_set_vlan_id(esw, i, vid); + rt305x_esw_set_vmsc(esw, i, vmsc); + } + + for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) { + u32 pvid; + disable |= esw->ports[i].disable << i; + if (esw->global_vlan_enable) { + doubletag |= esw->ports[i].doubletag << i; + en_vlan |= 1 << i; + untag |= esw->ports[i].untag << i; + pvid = esw->ports[i].pvid; + } else { + int x = esw->alt_vlan_disable ? 0 : 1; + doubletag |= x << i; + en_vlan |= x << i; + untag |= x << i; + pvid = 0; + } + rt305x_esw_set_pvid(esw, i, pvid); + if (i < RT305X_ESW_NUM_LEDS) + rt305x_esw_wr(esw, esw->ports[i].led, + RT305X_ESW_REG_P0LED + 4*i); + } + + rt305x_esw_set_port_disable(esw, disable); + rt305x_esw_rmw(esw, RT305X_ESW_REG_SGC2, + (RT305X_ESW_SGC2_DOUBLE_TAG_M << + RT305X_ESW_SGC2_DOUBLE_TAG_S), + doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S); + rt305x_esw_rmw(esw, RT305X_ESW_REG_PFC1, + RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S, + en_vlan << RT305X_ESW_PFC1_EN_VLAN_S); + rt305x_esw_rmw(esw, RT305X_ESW_REG_POC2, + RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S, + untag << RT305X_ESW_POC2_UNTAG_EN_S); + + if (!esw->global_vlan_enable) { + /* + * Still need to put all ports into vlan 0 or they'll be + * isolated. + * NOTE: vlan 0 is special, no vlan tag is prepended + */ + rt305x_esw_set_vlan_id(esw, 0, 0); + rt305x_esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL); + } + + return 0; +} + +static int +rt305x_esw_reset_switch(struct switch_dev *dev) +{ + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); + esw->global_vlan_enable = 0; + memset(esw->ports, 0, sizeof(esw->ports)); + memset(esw->vlans, 0, sizeof(esw->vlans)); + rt305x_esw_hw_init(esw); + + return 0; +} + +static int +rt305x_esw_get_vlan_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); + + val->value.i = esw->global_vlan_enable; + + return 0; +} + +static int +rt305x_esw_set_vlan_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); + + esw->global_vlan_enable = val->value.i != 0; + + return 0; +} + +static int +rt305x_esw_get_alt_vlan_disable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); + + val->value.i = esw->alt_vlan_disable; + + return 0; +} + +static int +rt305x_esw_set_alt_vlan_disable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); + + esw->alt_vlan_disable = val->value.i != 0; + + return 0; +} + +static int +rt305x_esw_get_port_link(struct switch_dev *dev, + int port, + struct switch_port_link *link) +{ + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); + u32 speed, poa; + + if (port < 0 || port >= RT305X_ESW_NUM_PORTS) + return -EINVAL; + + poa = rt305x_esw_rr(esw, RT305X_ESW_REG_POA) >> port; + + link->link = (poa >> RT305X_ESW_LINK_S) & 1; + link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1; + if (port < RT305X_ESW_NUM_LEDS) { + speed = (poa >> RT305X_ESW_SPD_S) & 1; + } else { + if (port == RT305X_ESW_NUM_PORTS - 1) + poa >>= 1; + speed = (poa >> RT305X_ESW_SPD_S) & 3; + } + switch (speed) { + case 0: + link->speed = SWITCH_PORT_SPEED_10; + break; + case 1: + link->speed = SWITCH_PORT_SPEED_100; + break; + case 2: + case 3: /* forced gige speed can be 2 or 3 */ + link->speed = SWITCH_PORT_SPEED_1000; + break; + default: + link->speed = SWITCH_PORT_SPEED_UNKNOWN; + break; + } + + return 0; +} + +static int +rt305x_esw_get_port_bool(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); + int idx = val->port_vlan; + u32 x, reg, shift; + + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS) + return -EINVAL; + + switch (attr->id) { + case RT305X_ESW_ATTR_PORT_DISABLE: + reg = RT305X_ESW_REG_POC0; + shift = RT305X_ESW_POC0_DIS_PORT_S; + break; + case RT305X_ESW_ATTR_PORT_DOUBLETAG: + reg = RT305X_ESW_REG_SGC2; + shift = RT305X_ESW_SGC2_DOUBLE_TAG_S; + break; + case RT305X_ESW_ATTR_PORT_UNTAG: + reg = RT305X_ESW_REG_POC2; + shift = RT305X_ESW_POC2_UNTAG_EN_S; + break; + case RT305X_ESW_ATTR_PORT_LAN: + reg = RT305X_ESW_REG_SGC2; + shift = RT305X_ESW_SGC2_LAN_PMAP_S; + if (idx >= RT305X_ESW_NUM_LANWAN) + return -EINVAL; + break; + default: + return -EINVAL; + } + + x = rt305x_esw_rr(esw, reg); + val->value.i = (x >> (idx + shift)) & 1; + + return 0; +} + +static int +rt305x_esw_set_port_bool(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); + int idx = val->port_vlan; + + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS || + val->value.i < 0 || val->value.i > 1) + return -EINVAL; + + switch (attr->id) { + case RT305X_ESW_ATTR_PORT_DISABLE: + esw->ports[idx].disable = val->value.i; + break; + case RT305X_ESW_ATTR_PORT_DOUBLETAG: + esw->ports[idx].doubletag = val->value.i; + break; + case RT305X_ESW_ATTR_PORT_UNTAG: + esw->ports[idx].untag = val->value.i; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int +rt305x_esw_get_port_recv_badgood(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); + int idx = val->port_vlan; + int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16; + u32 reg; + + if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN) + return -EINVAL; + + reg = rt305x_esw_rr(esw, RT305X_ESW_REG_P0PC + 4*idx); + val->value.i = (reg >> shift) & 0xffff; + + return 0; +} + +static int +rt305x_esw_get_port_led(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); + int idx = val->port_vlan; + + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS || + idx >= RT305X_ESW_NUM_LEDS) + return -EINVAL; + + val->value.i = rt305x_esw_rr(esw, RT305X_ESW_REG_P0LED + 4*idx); + + return 0; +} + +static int +rt305x_esw_set_port_led(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); + int idx = val->port_vlan; + + if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS) + return -EINVAL; + + esw->ports[idx].led = val->value.i; + + return 0; +} + +static int +rt305x_esw_get_port_pvid(struct switch_dev *dev, int port, int *val) +{ + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); + + if (port >= RT305X_ESW_NUM_PORTS) + return -EINVAL; + + *val = rt305x_esw_get_pvid(esw, port); + + return 0; +} + +static int +rt305x_esw_set_port_pvid(struct switch_dev *dev, int port, int val) +{ + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); + + if (port >= RT305X_ESW_NUM_PORTS) + return -EINVAL; + + esw->ports[port].pvid = val; + + return 0; +} + +static int +rt305x_esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val) +{ + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); + u32 vmsc, poc2; + int vlan_idx = -1; + int i; + + val->len = 0; + + if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS) + return -EINVAL; + + /* valid vlan? */ + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) { + if (rt305x_esw_get_vlan_id(esw, i) == val->port_vlan && + rt305x_esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) { + vlan_idx = i; + break; + } + } + + if (vlan_idx == -1) + return -EINVAL; + + vmsc = rt305x_esw_get_vmsc(esw, vlan_idx); + poc2 = rt305x_esw_rr(esw, RT305X_ESW_REG_POC2); + + for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) { + struct switch_port *p; + int port_mask = 1 << i; + + if (!(vmsc & port_mask)) + continue; + + p = &val->value.ports[val->len++]; + p->id = i; + if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S)) + p->flags = 0; + else + p->flags = 1 << SWITCH_PORT_FLAG_TAGGED; + } + + return 0; +} + +static int +rt305x_esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val) +{ + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); + int ports; + int vlan_idx = -1; + int i; + + if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS || + val->len > RT305X_ESW_NUM_PORTS) + return -EINVAL; + + /* one of the already defined vlans? */ + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) { + if (esw->vlans[i].vid == val->port_vlan && + esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) { + vlan_idx = i; + break; + } + } + + /* select a free slot */ + for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) { + if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE) + vlan_idx = i; + } + + /* bail if all slots are in use */ + if (vlan_idx == -1) + return -EINVAL; + + ports = RT305X_ESW_PORTS_NONE; + for (i = 0; i < val->len; i++) { + struct switch_port *p = &val->value.ports[i]; + int port_mask = 1 << p->id; + bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)); + + if (p->id >= RT305X_ESW_NUM_PORTS) + return -EINVAL; + + ports |= port_mask; + esw->ports[p->id].untag = untagged; + } + esw->vlans[vlan_idx].ports = ports; + if (ports == RT305X_ESW_PORTS_NONE) + esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE; + else + esw->vlans[vlan_idx].vid = val->port_vlan; + + return 0; +} + +static const struct switch_attr rt305x_esw_global[] = { + { + .type = SWITCH_TYPE_INT, + .name = "enable_vlan", + .description = "VLAN mode (1:enabled)", + .max = 1, + .id = RT305X_ESW_ATTR_ENABLE_VLAN, + .get = rt305x_esw_get_vlan_enable, + .set = rt305x_esw_set_vlan_enable, + }, + { + .type = SWITCH_TYPE_INT, + .name = "alternate_vlan_disable", + .description = "Use en_vlan instead of doubletag to disable" + " VLAN mode", + .max = 1, + .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE, + .get = rt305x_esw_get_alt_vlan_disable, + .set = rt305x_esw_set_alt_vlan_disable, + }, +}; + +static const struct switch_attr rt305x_esw_port[] = { + { + .type = SWITCH_TYPE_INT, + .name = "disable", + .description = "Port state (1:disabled)", + .max = 1, + .id = RT305X_ESW_ATTR_PORT_DISABLE, + .get = rt305x_esw_get_port_bool, + .set = rt305x_esw_set_port_bool, + }, + { + .type = SWITCH_TYPE_INT, + .name = "doubletag", + .description = "Double tagging for incoming vlan packets " + "(1:enabled)", + .max = 1, + .id = RT305X_ESW_ATTR_PORT_DOUBLETAG, + .get = rt305x_esw_get_port_bool, + .set = rt305x_esw_set_port_bool, + }, + { + .type = SWITCH_TYPE_INT, + .name = "untag", + .description = "Untag (1:strip outgoing vlan tag)", + .max = 1, + .id = RT305X_ESW_ATTR_PORT_UNTAG, + .get = rt305x_esw_get_port_bool, + .set = rt305x_esw_set_port_bool, + }, + { + .type = SWITCH_TYPE_INT, + .name = "led", + .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity," + " 4:collision, 5:linkact, 6:duplcoll, 7:10mact," + " 8:100mact, 10:blink, 12:on)", + .max = 15, + .id = RT305X_ESW_ATTR_PORT_LED, + .get = rt305x_esw_get_port_led, + .set = rt305x_esw_set_port_led, + }, + { + .type = SWITCH_TYPE_INT, + .name = "lan", + .description = "HW port group (0:wan, 1:lan)", + .max = 1, + .id = RT305X_ESW_ATTR_PORT_LAN, + .get = rt305x_esw_get_port_bool, + }, + { + .type = SWITCH_TYPE_INT, + .name = "recv_bad", + .description = "Receive bad packet counter", + .id = RT305X_ESW_ATTR_PORT_RECV_BAD, + .get = rt305x_esw_get_port_recv_badgood, + }, + { + .type = SWITCH_TYPE_INT, + .name = "recv_good", + .description = "Receive good packet counter", + .id = RT305X_ESW_ATTR_PORT_RECV_GOOD, + .get = rt305x_esw_get_port_recv_badgood, + }, +}; + +static const struct switch_attr rt305x_esw_vlan[] = { +}; + +static const struct switch_dev_ops rt305x_esw_ops = { + .attr_global = { + .attr = rt305x_esw_global, + .n_attr = ARRAY_SIZE(rt305x_esw_global), + }, + .attr_port = { + .attr = rt305x_esw_port, + .n_attr = ARRAY_SIZE(rt305x_esw_port), + }, + .attr_vlan = { + .attr = rt305x_esw_vlan, + .n_attr = ARRAY_SIZE(rt305x_esw_vlan), + }, + .get_vlan_ports = rt305x_esw_get_vlan_ports, + .set_vlan_ports = rt305x_esw_set_vlan_ports, + .get_port_pvid = rt305x_esw_get_port_pvid, + .set_port_pvid = rt305x_esw_set_port_pvid, + .get_port_link = rt305x_esw_get_port_link, + .apply_config = rt305x_esw_apply_config, + .reset_switch = rt305x_esw_reset_switch, +}; + +static int +rt305x_esw_probe(struct platform_device *pdev) +{ + struct rt305x_esw_platform_data *pdata; + struct rt305x_esw *esw; + struct switch_dev *swdev; + struct resource *res; + int err; + + pdata = pdev->dev.platform_data; + if (!pdata) + return -EINVAL; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "no memory resource found\n"); + return -ENOMEM; + } + + esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL); + if (!esw) { + dev_err(&pdev->dev, "no memory for private data\n"); + return -ENOMEM; + } + + esw->base = ioremap(res->start, resource_size(res)); + if (!esw->base) { + dev_err(&pdev->dev, "ioremap failed\n"); + err = -ENOMEM; + goto free_esw; + } + + swdev = &esw->swdev; + swdev->name = "rt305x-esw"; + swdev->alias = "rt305x"; + swdev->cpu_port = RT305X_ESW_PORT6; + swdev->ports = RT305X_ESW_NUM_PORTS; + swdev->vlans = RT305X_ESW_NUM_VIDS; + swdev->ops = &rt305x_esw_ops; + + err = register_switch(swdev, NULL); + if (err < 0) { + dev_err(&pdev->dev, "register_switch failed\n"); + goto unmap_base; + } + + platform_set_drvdata(pdev, esw); + + esw->pdata = pdata; + spin_lock_init(&esw->reg_rw_lock); + rt305x_esw_hw_init(esw); + + return 0; + +unmap_base: + iounmap(esw->base); +free_esw: + kfree(esw); + return err; +} + +static int +rt305x_esw_remove(struct platform_device *pdev) +{ + struct rt305x_esw *esw; + + esw = platform_get_drvdata(pdev); + if (esw) { + unregister_switch(&esw->swdev); + platform_set_drvdata(pdev, NULL); + iounmap(esw->base); + kfree(esw); + } + + return 0; +} + +static struct platform_driver rt305x_esw_driver = { + .probe = rt305x_esw_probe, + .remove = rt305x_esw_remove, + .driver = { + .name = "rt305x-esw", + .owner = THIS_MODULE, + }, +}; + +static int __init +rt305x_esw_init(void) +{ + return platform_driver_register(&rt305x_esw_driver); +} + +static void +rt305x_esw_exit(void) +{ + platform_driver_unregister(&rt305x_esw_driver); +} diff --git a/target/linux/ramips/files-3.7/drivers/net/ethernet/ramips/ramips_eth.h b/target/linux/ramips/files-3.7/drivers/net/ethernet/ramips/ramips_eth.h new file mode 100644 index 0000000000..66187030b9 --- /dev/null +++ b/target/linux/ramips/files-3.7/drivers/net/ethernet/ramips/ramips_eth.h @@ -0,0 +1,358 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + * + * based on Ralink SDK3.3 + * Copyright (C) 2009 John Crispin + */ + +#ifndef RAMIPS_ETH_H +#define RAMIPS_ETH_H + +#include +#include +#include +#include + +#define NUM_RX_DESC 256 +#define NUM_TX_DESC 256 + +#define RAMIPS_DELAY_EN_INT 0x80 +#define RAMIPS_DELAY_MAX_INT 0x04 +#define RAMIPS_DELAY_MAX_TOUT 0x04 +#define RAMIPS_DELAY_CHAN (((RAMIPS_DELAY_EN_INT | RAMIPS_DELAY_MAX_INT) << 8) | RAMIPS_DELAY_MAX_TOUT) +#define RAMIPS_DELAY_INIT ((RAMIPS_DELAY_CHAN << 16) | RAMIPS_DELAY_CHAN) +#define RAMIPS_PSE_FQFC_CFG_INIT 0x80504000 + +/* interrupt bits */ +#define RAMIPS_CNT_PPE_AF BIT(31) +#define RAMIPS_CNT_GDM_AF BIT(29) +#define RAMIPS_PSE_P2_FC BIT(26) +#define RAMIPS_PSE_BUF_DROP BIT(24) +#define RAMIPS_GDM_OTHER_DROP BIT(23) +#define RAMIPS_PSE_P1_FC BIT(22) +#define RAMIPS_PSE_P0_FC BIT(21) +#define RAMIPS_PSE_FQ_EMPTY BIT(20) +#define RAMIPS_GE1_STA_CHG BIT(18) +#define RAMIPS_TX_COHERENT BIT(17) +#define RAMIPS_RX_COHERENT BIT(16) +#define RAMIPS_TX_DONE_INT3 BIT(11) +#define RAMIPS_TX_DONE_INT2 BIT(10) +#define RAMIPS_TX_DONE_INT1 BIT(9) +#define RAMIPS_TX_DONE_INT0 BIT(8) +#define RAMIPS_RX_DONE_INT0 BIT(2) +#define RAMIPS_TX_DLY_INT BIT(1) +#define RAMIPS_RX_DLY_INT BIT(0) + +#define RT5350_RX_DLY_INT BIT(30) +#define RT5350_TX_DLY_INT BIT(28) + +/* registers */ +#define RAMIPS_FE_OFFSET 0x0000 +#define RAMIPS_GDMA_OFFSET 0x0020 +#define RAMIPS_PSE_OFFSET 0x0040 +#define RAMIPS_GDMA2_OFFSET 0x0060 +#define RAMIPS_CDMA_OFFSET 0x0080 +#define RAMIPS_PDMA_OFFSET 0x0100 +#define RAMIPS_PPE_OFFSET 0x0200 +#define RAMIPS_CMTABLE_OFFSET 0x0400 +#define RAMIPS_POLICYTABLE_OFFSET 0x1000 + +#define RT5350_PDMA_OFFSET 0x0800 +#define RT5350_SDM_OFFSET 0x0c00 + +#define RAMIPS_MDIO_ACCESS (RAMIPS_FE_OFFSET + 0x00) +#define RAMIPS_MDIO_CFG (RAMIPS_FE_OFFSET + 0x04) +#define RAMIPS_FE_GLO_CFG (RAMIPS_FE_OFFSET + 0x08) +#define RAMIPS_FE_RST_GL (RAMIPS_FE_OFFSET + 0x0C) +#define RAMIPS_FE_INT_STATUS (RAMIPS_FE_OFFSET + 0x10) +#define RAMIPS_FE_INT_ENABLE (RAMIPS_FE_OFFSET + 0x14) +#define RAMIPS_MDIO_CFG2 (RAMIPS_FE_OFFSET + 0x18) +#define RAMIPS_FOC_TS_T (RAMIPS_FE_OFFSET + 0x1C) + +#define RAMIPS_GDMA1_FWD_CFG (RAMIPS_GDMA_OFFSET + 0x00) +#define RAMIPS_GDMA1_SCH_CFG (RAMIPS_GDMA_OFFSET + 0x04) +#define RAMIPS_GDMA1_SHPR_CFG (RAMIPS_GDMA_OFFSET + 0x08) +#define RAMIPS_GDMA1_MAC_ADRL (RAMIPS_GDMA_OFFSET + 0x0C) +#define RAMIPS_GDMA1_MAC_ADRH (RAMIPS_GDMA_OFFSET + 0x10) + +#define RAMIPS_GDMA2_FWD_CFG (RAMIPS_GDMA2_OFFSET + 0x00) +#define RAMIPS_GDMA2_SCH_CFG (RAMIPS_GDMA2_OFFSET + 0x04) +#define RAMIPS_GDMA2_SHPR_CFG (RAMIPS_GDMA2_OFFSET + 0x08) +#define RAMIPS_GDMA2_MAC_ADRL (RAMIPS_GDMA2_OFFSET + 0x0C) +#define RAMIPS_GDMA2_MAC_ADRH (RAMIPS_GDMA2_OFFSET + 0x10) + +#define RAMIPS_PSE_FQ_CFG (RAMIPS_PSE_OFFSET + 0x00) +#define RAMIPS_CDMA_FC_CFG (RAMIPS_PSE_OFFSET + 0x04) +#define RAMIPS_GDMA1_FC_CFG (RAMIPS_PSE_OFFSET + 0x08) +#define RAMIPS_GDMA2_FC_CFG (RAMIPS_PSE_OFFSET + 0x0C) + +#define RAMIPS_CDMA_CSG_CFG (RAMIPS_CDMA_OFFSET + 0x00) +#define RAMIPS_CDMA_SCH_CFG (RAMIPS_CDMA_OFFSET + 0x04) + +#define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00) +#define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04) +#define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08) +#define RT5350_TX_DTX_IDX0 (RT5350_PDMA_OFFSET + 0x0C) +#define RT5350_TX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x10) +#define RT5350_TX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x14) +#define RT5350_TX_CTX_IDX1 (RT5350_PDMA_OFFSET + 0x18) +#define RT5350_TX_DTX_IDX1 (RT5350_PDMA_OFFSET + 0x1C) +#define RT5350_TX_BASE_PTR2 (RT5350_PDMA_OFFSET + 0x20) +#define RT5350_TX_MAX_CNT2 (RT5350_PDMA_OFFSET + 0x24) +#define RT5350_TX_CTX_IDX2 (RT5350_PDMA_OFFSET + 0x28) +#define RT5350_TX_DTX_IDX2 (RT5350_PDMA_OFFSET + 0x2C) +#define RT5350_TX_BASE_PTR3 (RT5350_PDMA_OFFSET + 0x30) +#define RT5350_TX_MAX_CNT3 (RT5350_PDMA_OFFSET + 0x34) +#define RT5350_TX_CTX_IDX3 (RT5350_PDMA_OFFSET + 0x38) +#define RT5350_TX_DTX_IDX3 (RT5350_PDMA_OFFSET + 0x3C) +#define RT5350_RX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x100) +#define RT5350_RX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x104) +#define RT5350_RX_CALC_IDX0 (RT5350_PDMA_OFFSET + 0x108) +#define RT5350_RX_DRX_IDX0 (RT5350_PDMA_OFFSET + 0x10C) +#define RT5350_RX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x110) +#define RT5350_RX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x114) +#define RT5350_RX_CALC_IDX1 (RT5350_PDMA_OFFSET + 0x118) +#define RT5350_RX_DRX_IDX1 (RT5350_PDMA_OFFSET + 0x11C) +#define RT5350_PDMA_GLO_CFG (RT5350_PDMA_OFFSET + 0x204) +#define RT5350_PDMA_RST_CFG (RT5350_PDMA_OFFSET + 0x208) +#define RT5350_DLY_INT_CFG (RT5350_PDMA_OFFSET + 0x20c) +#define RT5350_FE_INT_STATUS (RT5350_PDMA_OFFSET + 0x220) +#define RT5350_FE_INT_ENABLE (RT5350_PDMA_OFFSET + 0x228) +#define RT5350_PDMA_SCH_CFG (RT5350_PDMA_OFFSET + 0x280) + + +#define RAMIPS_PDMA_GLO_CFG (RAMIPS_PDMA_OFFSET + 0x00) +#define RAMIPS_PDMA_RST_CFG (RAMIPS_PDMA_OFFSET + 0x04) +#define RAMIPS_PDMA_SCH_CFG (RAMIPS_PDMA_OFFSET + 0x08) +#define RAMIPS_DLY_INT_CFG (RAMIPS_PDMA_OFFSET + 0x0C) +#define RAMIPS_TX_BASE_PTR0 (RAMIPS_PDMA_OFFSET + 0x10) +#define RAMIPS_TX_MAX_CNT0 (RAMIPS_PDMA_OFFSET + 0x14) +#define RAMIPS_TX_CTX_IDX0 (RAMIPS_PDMA_OFFSET + 0x18) +#define RAMIPS_TX_DTX_IDX0 (RAMIPS_PDMA_OFFSET + 0x1C) +#define RAMIPS_TX_BASE_PTR1 (RAMIPS_PDMA_OFFSET + 0x20) +#define RAMIPS_TX_MAX_CNT1 (RAMIPS_PDMA_OFFSET + 0x24) +#define RAMIPS_TX_CTX_IDX1 (RAMIPS_PDMA_OFFSET + 0x28) +#define RAMIPS_TX_DTX_IDX1 (RAMIPS_PDMA_OFFSET + 0x2C) +#define RAMIPS_RX_BASE_PTR0 (RAMIPS_PDMA_OFFSET + 0x30) +#define RAMIPS_RX_MAX_CNT0 (RAMIPS_PDMA_OFFSET + 0x34) +#define RAMIPS_RX_CALC_IDX0 (RAMIPS_PDMA_OFFSET + 0x38) +#define RAMIPS_RX_DRX_IDX0 (RAMIPS_PDMA_OFFSET + 0x3C) +#define RAMIPS_TX_BASE_PTR2 (RAMIPS_PDMA_OFFSET + 0x40) +#define RAMIPS_TX_MAX_CNT2 (RAMIPS_PDMA_OFFSET + 0x44) +#define RAMIPS_TX_CTX_IDX2 (RAMIPS_PDMA_OFFSET + 0x48) +#define RAMIPS_TX_DTX_IDX2 (RAMIPS_PDMA_OFFSET + 0x4C) +#define RAMIPS_TX_BASE_PTR3 (RAMIPS_PDMA_OFFSET + 0x50) +#define RAMIPS_TX_MAX_CNT3 (RAMIPS_PDMA_OFFSET + 0x54) +#define RAMIPS_TX_CTX_IDX3 (RAMIPS_PDMA_OFFSET + 0x58) +#define RAMIPS_TX_DTX_IDX3 (RAMIPS_PDMA_OFFSET + 0x5C) +#define RAMIPS_RX_BASE_PTR1 (RAMIPS_PDMA_OFFSET + 0x60) +#define RAMIPS_RX_MAX_CNT1 (RAMIPS_PDMA_OFFSET + 0x64) +#define RAMIPS_RX_CALC_IDX1 (RAMIPS_PDMA_OFFSET + 0x68) +#define RAMIPS_RX_DRX_IDX1 (RAMIPS_PDMA_OFFSET + 0x6C) + +#define RT5350_SDM_CFG (RT5350_SDM_OFFSET + 0x00) //Switch DMA configuration +#define RT5350_SDM_RRING (RT5350_SDM_OFFSET + 0x04) //Switch DMA Rx Ring +#define RT5350_SDM_TRING (RT5350_SDM_OFFSET + 0x08) //Switch DMA Tx Ring +#define RT5350_SDM_MAC_ADRL (RT5350_SDM_OFFSET + 0x0C) //Switch MAC address LSB +#define RT5350_SDM_MAC_ADRH (RT5350_SDM_OFFSET + 0x10) //Switch MAC Address MSB +#define RT5350_SDM_TPCNT (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count +#define RT5350_SDM_TBCNT (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count +#define RT5350_SDM_RPCNT (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count +#define RT5350_SDM_RBCNT (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count +#define RT5350_SDM_CS_ERR (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count + +#define RT5350_SDM_ICS_EN BIT(16) +#define RT5350_SDM_TCS_EN BIT(17) +#define RT5350_SDM_UCS_EN BIT(18) + + +/* MDIO_CFG register bits */ +#define RAMIPS_MDIO_CFG_AUTO_POLL_EN BIT(29) +#define RAMIPS_MDIO_CFG_GP1_BP_EN BIT(16) +#define RAMIPS_MDIO_CFG_GP1_FRC_EN BIT(15) +#define RAMIPS_MDIO_CFG_GP1_SPEED_10 (0 << 13) +#define RAMIPS_MDIO_CFG_GP1_SPEED_100 (1 << 13) +#define RAMIPS_MDIO_CFG_GP1_SPEED_1000 (2 << 13) +#define RAMIPS_MDIO_CFG_GP1_DUPLEX BIT(12) +#define RAMIPS_MDIO_CFG_GP1_FC_TX BIT(11) +#define RAMIPS_MDIO_CFG_GP1_FC_RX BIT(10) +#define RAMIPS_MDIO_CFG_GP1_LNK_DWN BIT(9) +#define RAMIPS_MDIO_CFG_GP1_AN_FAIL BIT(8) +#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6) +#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6) +#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6) +#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6) +#define RAMIPS_MDIO_CFG_TURBO_MII_FREQ BIT(5) +#define RAMIPS_MDIO_CFG_TURBO_MII_MODE BIT(4) +#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2) +#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2) +#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2) +#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2) +#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_0 0 +#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_200 1 +#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_400 2 +#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_INV 3 + +/* uni-cast port */ +#define RAMIPS_GDM1_ICS_EN BIT(22) +#define RAMIPS_GDM1_TCS_EN BIT(21) +#define RAMIPS_GDM1_UCS_EN BIT(20) +#define RAMIPS_GDM1_JMB_EN BIT(19) +#define RAMIPS_GDM1_STRPCRC BIT(16) +#define RAMIPS_GDM1_UFRC_P_CPU (0 << 12) +#define RAMIPS_GDM1_UFRC_P_GDMA1 (1 << 12) +#define RAMIPS_GDM1_UFRC_P_PPE (6 << 12) + +/* checksums */ +#define RAMIPS_ICS_GEN_EN BIT(2) +#define RAMIPS_UCS_GEN_EN BIT(1) +#define RAMIPS_TCS_GEN_EN BIT(0) + +/* dma ring */ +#define RAMIPS_PST_DRX_IDX0 BIT(16) +#define RAMIPS_PST_DTX_IDX3 BIT(3) +#define RAMIPS_PST_DTX_IDX2 BIT(2) +#define RAMIPS_PST_DTX_IDX1 BIT(1) +#define RAMIPS_PST_DTX_IDX0 BIT(0) + +#define RAMIPS_TX_WB_DDONE BIT(6) +#define RAMIPS_RX_DMA_BUSY BIT(3) +#define RAMIPS_TX_DMA_BUSY BIT(1) +#define RAMIPS_RX_DMA_EN BIT(2) +#define RAMIPS_TX_DMA_EN BIT(0) + +#define RAMIPS_PDMA_SIZE_4DWORDS (0 << 4) +#define RAMIPS_PDMA_SIZE_8DWORDS (1 << 4) +#define RAMIPS_PDMA_SIZE_16DWORDS (2 << 4) + +#define RAMIPS_US_CYC_CNT_MASK 0xff +#define RAMIPS_US_CYC_CNT_SHIFT 0x8 +#define RAMIPS_US_CYC_CNT_DIVISOR 1000000 + +#define RX_DMA_PLEN0(_x) (((_x) >> 16) & 0x3fff) +#define RX_DMA_LSO BIT(30) +#define RX_DMA_DONE BIT(31) + +struct ramips_rx_dma { + unsigned int rxd1; + unsigned int rxd2; + unsigned int rxd3; + unsigned int rxd4; +} __packed __aligned(4); + +#define TX_DMA_PLEN0_MASK ((0x3fff) << 16) +#define TX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) +#define TX_DMA_LSO BIT(30) +#define TX_DMA_DONE BIT(31) +#define TX_DMA_QN(_x) ((_x) << 16) +#define TX_DMA_PN(_x) ((_x) << 24) +#define TX_DMA_QN_MASK TX_DMA_QN(0x7) +#define TX_DMA_PN_MASK TX_DMA_PN(0x7) + +struct ramips_tx_dma { + unsigned int txd1; + unsigned int txd2; + unsigned int txd3; + unsigned int txd4; +} __packed __aligned(4); + +struct raeth_tx_info { + struct ramips_tx_dma *tx_desc; + struct sk_buff *tx_skb; +}; + +struct raeth_rx_info { + struct ramips_rx_dma *rx_desc; + struct sk_buff *rx_skb; + dma_addr_t rx_dma; + unsigned int pad; +}; + +struct raeth_int_stats { + unsigned long rx_delayed; + unsigned long tx_delayed; + unsigned long rx_done0; + unsigned long tx_done0; + unsigned long tx_done1; + unsigned long tx_done2; + unsigned long tx_done3; + unsigned long rx_coherent; + unsigned long tx_coherent; + + unsigned long pse_fq_empty; + unsigned long pse_p0_fc; + unsigned long pse_p1_fc; + unsigned long pse_p2_fc; + unsigned long pse_buf_drop; + + unsigned long total; +}; + +struct raeth_debug { + struct dentry *debugfs_dir; + + struct raeth_int_stats int_stats; +}; + +struct raeth_priv +{ + struct raeth_rx_info *rx_info; + dma_addr_t rx_desc_dma; + struct tasklet_struct rx_tasklet; + struct ramips_rx_dma *rx; + + struct raeth_tx_info *tx_info; + dma_addr_t tx_desc_dma; + struct tasklet_struct tx_housekeeping_tasklet; + struct ramips_tx_dma *tx; + + unsigned int skb_free_idx; + + spinlock_t page_lock; + struct net_device *netdev; + struct device *parent; + struct ramips_eth_platform_data *plat; + + int link; + int speed; + int duplex; + int tx_fc; + int rx_fc; + + struct mii_bus *mii_bus; + int mii_irq[PHY_MAX_ADDR]; + struct phy_device *phy_dev; + spinlock_t phy_lock; + +#ifdef CONFIG_NET_RAMIPS_DEBUG_FS + struct raeth_debug debug; +#endif +}; + +#ifdef CONFIG_NET_RAMIPS_DEBUG_FS +int raeth_debugfs_root_init(void); +void raeth_debugfs_root_exit(void); +int raeth_debugfs_init(struct raeth_priv *re); +void raeth_debugfs_exit(struct raeth_priv *re); +void raeth_debugfs_update_int_stats(struct raeth_priv *re, u32 status); +#else +static inline int raeth_debugfs_root_init(void) { return 0; } +static inline void raeth_debugfs_root_exit(void) {} +static inline int raeth_debugfs_init(struct raeth_priv *re) { return 0; } +static inline void raeth_debugfs_exit(struct raeth_priv *re) {} +static inline void raeth_debugfs_update_int_stats(struct raeth_priv *re, + u32 status) {} +#endif /* CONFIG_NET_RAMIPS_DEBUG_FS */ + +#endif /* RAMIPS_ETH_H */ diff --git a/target/linux/ramips/files-3.7/drivers/net/ethernet/ramips/ramips_main.c b/target/linux/ramips/files-3.7/drivers/net/ethernet/ramips/ramips_main.c new file mode 100644 index 0000000000..267860ff0f --- /dev/null +++ b/target/linux/ramips/files-3.7/drivers/net/ethernet/ramips/ramips_main.c @@ -0,0 +1,1212 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) 2009 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "ramips_eth.h" + +#define TX_TIMEOUT (20 * HZ / 100) +#define MAX_RX_LENGTH 1600 + +#ifdef CONFIG_RALINK_RT305X +#include +#include "ramips_esw.c" +#else +static inline int rt305x_esw_init(void) { return 0; } +static inline void rt305x_esw_exit(void) { } +static inline int soc_is_rt5350(void) { return 0; } +#endif + +#define phys_to_bus(a) (a & 0x1FFFFFFF) + +#ifdef CONFIG_NET_RAMIPS_DEBUG +#define RADEBUG(fmt, args...) printk(KERN_DEBUG fmt, ## args) +#else +#define RADEBUG(fmt, args...) do {} while (0) +#endif + +#define RX_DLY_INT ((soc_is_rt5350())?(RT5350_RX_DLY_INT):(RAMIPS_RX_DLY_INT)) +#define TX_DLY_INT ((soc_is_rt5350())?(RT5350_TX_DLY_INT):(RAMIPS_TX_DLY_INT)) + +enum raeth_reg { + RAETH_REG_PDMA_GLO_CFG = 0, + RAETH_REG_PDMA_RST_CFG, + RAETH_REG_DLY_INT_CFG, + RAETH_REG_TX_BASE_PTR0, + RAETH_REG_TX_MAX_CNT0, + RAETH_REG_TX_CTX_IDX0, + RAETH_REG_RX_BASE_PTR0, + RAETH_REG_RX_MAX_CNT0, + RAETH_REG_RX_CALC_IDX0, + RAETH_REG_FE_INT_ENABLE, + RAETH_REG_FE_INT_STATUS, + RAETH_REG_COUNT +}; + +static const u32 ramips_reg_table[RAETH_REG_COUNT] = { + [RAETH_REG_PDMA_GLO_CFG] = RAMIPS_PDMA_GLO_CFG, + [RAETH_REG_PDMA_RST_CFG] = RAMIPS_PDMA_RST_CFG, + [RAETH_REG_DLY_INT_CFG] = RAMIPS_DLY_INT_CFG, + [RAETH_REG_TX_BASE_PTR0] = RAMIPS_TX_BASE_PTR0, + [RAETH_REG_TX_MAX_CNT0] = RAMIPS_TX_MAX_CNT0, + [RAETH_REG_TX_CTX_IDX0] = RAMIPS_TX_CTX_IDX0, + [RAETH_REG_RX_BASE_PTR0] = RAMIPS_RX_BASE_PTR0, + [RAETH_REG_RX_MAX_CNT0] = RAMIPS_RX_MAX_CNT0, + [RAETH_REG_RX_CALC_IDX0] = RAMIPS_RX_CALC_IDX0, + [RAETH_REG_FE_INT_ENABLE] = RAMIPS_FE_INT_ENABLE, + [RAETH_REG_FE_INT_STATUS] = RAMIPS_FE_INT_STATUS, +}; + +static const u32 rt5350_reg_table[RAETH_REG_COUNT] = { + [RAETH_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG, + [RAETH_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG, + [RAETH_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG, + [RAETH_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0, + [RAETH_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0, + [RAETH_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0, + [RAETH_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0, + [RAETH_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0, + [RAETH_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0, + [RAETH_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE, + [RAETH_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS, +}; + +static struct net_device * ramips_dev; +static void __iomem *ramips_fe_base = 0; + +static inline u32 get_reg_offset(enum raeth_reg reg) +{ + const u32 *table; + + if (soc_is_rt5350()) + table = rt5350_reg_table; + else + table = ramips_reg_table; + + return table[reg]; +} + +static inline void +ramips_fe_wr(u32 val, unsigned reg) +{ + __raw_writel(val, ramips_fe_base + reg); +} + +static inline u32 +ramips_fe_rr(unsigned reg) +{ + return __raw_readl(ramips_fe_base + reg); +} + +static inline void +ramips_fe_twr(u32 val, enum raeth_reg reg) +{ + ramips_fe_wr(val, get_reg_offset(reg)); +} + +static inline u32 +ramips_fe_trr(enum raeth_reg reg) +{ + return ramips_fe_rr(get_reg_offset(reg)); +} + +static inline void +ramips_fe_int_disable(u32 mask) +{ + ramips_fe_twr(ramips_fe_trr(RAETH_REG_FE_INT_ENABLE) & ~mask, + RAETH_REG_FE_INT_ENABLE); + /* flush write */ + ramips_fe_trr(RAETH_REG_FE_INT_ENABLE); +} + +static inline void +ramips_fe_int_enable(u32 mask) +{ + ramips_fe_twr(ramips_fe_trr(RAETH_REG_FE_INT_ENABLE) | mask, + RAETH_REG_FE_INT_ENABLE); + /* flush write */ + ramips_fe_trr(RAETH_REG_FE_INT_ENABLE); +} + +static inline void +ramips_hw_set_macaddr(unsigned char *mac) +{ + if (soc_is_rt5350()) { + ramips_fe_wr((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH); + ramips_fe_wr((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], + RT5350_SDM_MAC_ADRL); + } else { + ramips_fe_wr((mac[0] << 8) | mac[1], RAMIPS_GDMA1_MAC_ADRH); + ramips_fe_wr((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], + RAMIPS_GDMA1_MAC_ADRL); + } +} + +static struct sk_buff * +ramips_alloc_skb(struct raeth_priv *re) +{ + struct sk_buff *skb; + + skb = netdev_alloc_skb(re->netdev, MAX_RX_LENGTH + NET_IP_ALIGN); + if (!skb) + return NULL; + + skb_reserve(skb, NET_IP_ALIGN); + + return skb; +} + +static void +ramips_ring_setup(struct raeth_priv *re) +{ + int len; + int i; + + memset(re->tx_info, 0, NUM_TX_DESC * sizeof(struct raeth_tx_info)); + + len = NUM_TX_DESC * sizeof(struct ramips_tx_dma); + memset(re->tx, 0, len); + + for (i = 0; i < NUM_TX_DESC; i++) { + struct raeth_tx_info *txi; + struct ramips_tx_dma *txd; + + txd = &re->tx[i]; + txd->txd4 = TX_DMA_QN(3) | TX_DMA_PN(1); + txd->txd2 = TX_DMA_LSO | TX_DMA_DONE; + + txi = &re->tx_info[i]; + txi->tx_desc = txd; + if (txi->tx_skb != NULL) { + netdev_warn(re->netdev, + "dirty skb for TX desc %d\n", i); + txi->tx_skb = NULL; + } + } + + len = NUM_RX_DESC * sizeof(struct ramips_rx_dma); + memset(re->rx, 0, len); + + for (i = 0; i < NUM_RX_DESC; i++) { + struct raeth_rx_info *rxi; + struct ramips_rx_dma *rxd; + dma_addr_t dma_addr; + + rxd = &re->rx[i]; + rxi = &re->rx_info[i]; + BUG_ON(rxi->rx_skb == NULL); + dma_addr = dma_map_single(&re->netdev->dev, rxi->rx_skb->data, + MAX_RX_LENGTH, DMA_FROM_DEVICE); + rxi->rx_dma = dma_addr; + rxi->rx_desc = rxd; + + rxd->rxd1 = (unsigned int) dma_addr; + rxd->rxd2 = RX_DMA_LSO; + } + + /* flush descriptors */ + wmb(); +} + +static void +ramips_ring_cleanup(struct raeth_priv *re) +{ + int i; + + for (i = 0; i < NUM_RX_DESC; i++) { + struct raeth_rx_info *rxi; + + rxi = &re->rx_info[i]; + if (rxi->rx_skb) + dma_unmap_single(&re->netdev->dev, rxi->rx_dma, + MAX_RX_LENGTH, DMA_FROM_DEVICE); + } + + for (i = 0; i < NUM_TX_DESC; i++) { + struct raeth_tx_info *txi; + + txi = &re->tx_info[i]; + if (txi->tx_skb) { + dev_kfree_skb_any(txi->tx_skb); + txi->tx_skb = NULL; + } + } + + netdev_reset_queue(re->netdev); +} + +#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT3883) + +#define RAMIPS_MDIO_RETRY 1000 + +static unsigned char *ramips_speed_str(struct raeth_priv *re) +{ + switch (re->speed) { + case SPEED_1000: + return "1000"; + case SPEED_100: + return "100"; + case SPEED_10: + return "10"; + } + + return "?"; +} + +static void ramips_link_adjust(struct raeth_priv *re) +{ + struct ramips_eth_platform_data *pdata; + u32 mdio_cfg; + + pdata = re->parent->platform_data; + if (!re->link) { + netif_carrier_off(re->netdev); + netdev_info(re->netdev, "link down\n"); + return; + } + + mdio_cfg = RAMIPS_MDIO_CFG_TX_CLK_SKEW_200 | + RAMIPS_MDIO_CFG_TX_CLK_SKEW_200 | + RAMIPS_MDIO_CFG_GP1_FRC_EN; + + if (re->duplex == DUPLEX_FULL) + mdio_cfg |= RAMIPS_MDIO_CFG_GP1_DUPLEX; + + if (re->tx_fc) + mdio_cfg |= RAMIPS_MDIO_CFG_GP1_FC_TX; + + if (re->rx_fc) + mdio_cfg |= RAMIPS_MDIO_CFG_GP1_FC_RX; + + switch (re->speed) { + case SPEED_10: + mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_10; + break; + case SPEED_100: + mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_100; + break; + case SPEED_1000: + mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_1000; + break; + default: + BUG(); + } + + ramips_fe_wr(mdio_cfg, RAMIPS_MDIO_CFG); + + netif_carrier_on(re->netdev); + netdev_info(re->netdev, "link up (%sMbps/%s duplex)\n", + ramips_speed_str(re), + (DUPLEX_FULL == re->duplex) ? "Full" : "Half"); +} + +static int +ramips_mdio_wait_ready(struct raeth_priv *re) +{ + int retries; + + retries = RAMIPS_MDIO_RETRY; + while (1) { + u32 t; + + t = ramips_fe_rr(RAMIPS_MDIO_ACCESS); + if ((t & (0x1 << 31)) == 0) + return 0; + + if (retries-- == 0) + break; + + udelay(1); + } + + dev_err(re->parent, "MDIO operation timed out\n"); + return -ETIMEDOUT; +} + +static int +ramips_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) +{ + struct raeth_priv *re = bus->priv; + int err; + u32 t; + + err = ramips_mdio_wait_ready(re); + if (err) + return 0xffff; + + t = (phy_addr << 24) | (phy_reg << 16); + ramips_fe_wr(t, RAMIPS_MDIO_ACCESS); + t |= (1 << 31); + ramips_fe_wr(t, RAMIPS_MDIO_ACCESS); + + err = ramips_mdio_wait_ready(re); + if (err) + return 0xffff; + + RADEBUG("%s: addr=%04x, reg=%04x, value=%04x\n", __func__, + phy_addr, phy_reg, ramips_fe_rr(RAMIPS_MDIO_ACCESS) & 0xffff); + + return ramips_fe_rr(RAMIPS_MDIO_ACCESS) & 0xffff; +} + +static int +ramips_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val) +{ + struct raeth_priv *re = bus->priv; + int err; + u32 t; + + RADEBUG("%s: addr=%04x, reg=%04x, value=%04x\n", __func__, + phy_addr, phy_reg, ramips_fe_rr(RAMIPS_MDIO_ACCESS) & 0xffff); + + err = ramips_mdio_wait_ready(re); + if (err) + return err; + + t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val; + ramips_fe_wr(t, RAMIPS_MDIO_ACCESS); + t |= (1 << 31); + ramips_fe_wr(t, RAMIPS_MDIO_ACCESS); + + return ramips_mdio_wait_ready(re); +} + +static int +ramips_mdio_reset(struct mii_bus *bus) +{ + /* TODO */ + return 0; +} + +static int +ramips_mdio_init(struct raeth_priv *re) +{ + int err; + int i; + + re->mii_bus = mdiobus_alloc(); + if (re->mii_bus == NULL) + return -ENOMEM; + + re->mii_bus->name = "ramips_mdio"; + re->mii_bus->read = ramips_mdio_read; + re->mii_bus->write = ramips_mdio_write; + re->mii_bus->reset = ramips_mdio_reset; + re->mii_bus->irq = re->mii_irq; + re->mii_bus->priv = re; + re->mii_bus->parent = re->parent; + + snprintf(re->mii_bus->id, MII_BUS_ID_SIZE, "%s", "ramips_mdio"); + re->mii_bus->phy_mask = 0; + + for (i = 0; i < PHY_MAX_ADDR; i++) + re->mii_irq[i] = PHY_POLL; + + err = mdiobus_register(re->mii_bus); + if (err) + goto err_free_bus; + + return 0; + +err_free_bus: + kfree(re->mii_bus); + return err; +} + +static void +ramips_mdio_cleanup(struct raeth_priv *re) +{ + mdiobus_unregister(re->mii_bus); + kfree(re->mii_bus); +} + +static void +ramips_phy_link_adjust(struct net_device *dev) +{ + struct raeth_priv *re = netdev_priv(dev); + struct phy_device *phydev = re->phy_dev; + unsigned long flags; + int status_change = 0; + + spin_lock_irqsave(&re->phy_lock, flags); + + if (phydev->link) + if (re->duplex != phydev->duplex || + re->speed != phydev->speed) + status_change = 1; + + if (phydev->link != re->link) + status_change = 1; + + re->link = phydev->link; + re->duplex = phydev->duplex; + re->speed = phydev->speed; + + if (status_change) + ramips_link_adjust(re); + + spin_unlock_irqrestore(&re->phy_lock, flags); +} + +static int +ramips_phy_connect_multi(struct raeth_priv *re) +{ + struct net_device *netdev = re->netdev; + struct ramips_eth_platform_data *pdata; + struct phy_device *phydev = NULL; + int phy_addr; + int ret = 0; + + pdata = re->parent->platform_data; + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { + if (!(pdata->phy_mask & (1 << phy_addr))) + continue; + + if (re->mii_bus->phy_map[phy_addr] == NULL) + continue; + + RADEBUG("%s: PHY found at %s, uid=%08x\n", + netdev->name, + dev_name(&re->mii_bus->phy_map[phy_addr]->dev), + re->mii_bus->phy_map[phy_addr]->phy_id); + + if (phydev == NULL) + phydev = re->mii_bus->phy_map[phy_addr]; + } + + if (!phydev) { + netdev_err(netdev, "no PHY found with phy_mask=%08x\n", + pdata->phy_mask); + return -ENODEV; + } + + re->phy_dev = phy_connect(netdev, dev_name(&phydev->dev), + ramips_phy_link_adjust, 0, + pdata->phy_if_mode); + + if (IS_ERR(re->phy_dev)) { + netdev_err(netdev, "could not connect to PHY at %s\n", + dev_name(&phydev->dev)); + return PTR_ERR(re->phy_dev); + } + + phydev->supported &= PHY_GBIT_FEATURES; + phydev->advertising = phydev->supported; + + RADEBUG("%s: connected to PHY at %s [uid=%08x, driver=%s]\n", + netdev->name, dev_name(&phydev->dev), + phydev->phy_id, phydev->drv->name); + + re->link = 0; + re->speed = 0; + re->duplex = -1; + re->rx_fc = 0; + re->tx_fc = 0; + + return ret; +} + +static int +ramips_phy_connect_fixed(struct raeth_priv *re) +{ + struct ramips_eth_platform_data *pdata; + + pdata = re->parent->platform_data; + switch (pdata->speed) { + case SPEED_10: + case SPEED_100: + case SPEED_1000: + break; + default: + netdev_err(re->netdev, "invalid speed specified\n"); + return -EINVAL; + } + + RADEBUG("%s: using fixed link parameters\n", re->netdev->name); + + re->speed = pdata->speed; + re->duplex = pdata->duplex; + re->tx_fc = pdata->tx_fc; + re->rx_fc = pdata->tx_fc; + + return 0; +} + +static int +ramips_phy_connect(struct raeth_priv *re) +{ + struct ramips_eth_platform_data *pdata; + + pdata = re->parent->platform_data; + if (pdata->phy_mask) + return ramips_phy_connect_multi(re); + + return ramips_phy_connect_fixed(re); +} + +static void +ramips_phy_disconnect(struct raeth_priv *re) +{ + if (re->phy_dev) + phy_disconnect(re->phy_dev); +} + +static void +ramips_phy_start(struct raeth_priv *re) +{ + unsigned long flags; + + if (re->phy_dev) { + phy_start(re->phy_dev); + } else { + spin_lock_irqsave(&re->phy_lock, flags); + re->link = 1; + ramips_link_adjust(re); + spin_unlock_irqrestore(&re->phy_lock, flags); + } +} + +static void +ramips_phy_stop(struct raeth_priv *re) +{ + unsigned long flags; + + if (re->phy_dev) + phy_stop(re->phy_dev); + + spin_lock_irqsave(&re->phy_lock, flags); + re->link = 0; + ramips_link_adjust(re); + spin_unlock_irqrestore(&re->phy_lock, flags); +} +#else +static inline int +ramips_mdio_init(struct raeth_priv *re) +{ + return 0; +} + +static inline void +ramips_mdio_cleanup(struct raeth_priv *re) +{ +} + +static inline int +ramips_phy_connect(struct raeth_priv *re) +{ + return 0; +} + +static inline void +ramips_phy_disconnect(struct raeth_priv *re) +{ +} + +static inline void +ramips_phy_start(struct raeth_priv *re) +{ +} + +static inline void +ramips_phy_stop(struct raeth_priv *re) +{ +} +#endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT3883 */ + +static void +ramips_ring_free(struct raeth_priv *re) +{ + int len; + int i; + + if (re->rx_info) { + for (i = 0; i < NUM_RX_DESC; i++) { + struct raeth_rx_info *rxi; + + rxi = &re->rx_info[i]; + if (rxi->rx_skb) + dev_kfree_skb_any(rxi->rx_skb); + } + kfree(re->rx_info); + } + + if (re->rx) { + len = NUM_RX_DESC * sizeof(struct ramips_rx_dma); + dma_free_coherent(&re->netdev->dev, len, re->rx, + re->rx_desc_dma); + } + + if (re->tx) { + len = NUM_TX_DESC * sizeof(struct ramips_tx_dma); + dma_free_coherent(&re->netdev->dev, len, re->tx, + re->tx_desc_dma); + } + + kfree(re->tx_info); +} + +static int +ramips_ring_alloc(struct raeth_priv *re) +{ + int len; + int err = -ENOMEM; + int i; + + re->tx_info = kzalloc(NUM_TX_DESC * sizeof(struct raeth_tx_info), + GFP_ATOMIC); + if (!re->tx_info) + goto err_cleanup; + + re->rx_info = kzalloc(NUM_RX_DESC * sizeof(struct raeth_rx_info), + GFP_ATOMIC); + if (!re->rx_info) + goto err_cleanup; + + /* allocate tx ring */ + len = NUM_TX_DESC * sizeof(struct ramips_tx_dma); + re->tx = dma_alloc_coherent(&re->netdev->dev, len, + &re->tx_desc_dma, GFP_ATOMIC); + if (!re->tx) + goto err_cleanup; + + /* allocate rx ring */ + len = NUM_RX_DESC * sizeof(struct ramips_rx_dma); + re->rx = dma_alloc_coherent(&re->netdev->dev, len, + &re->rx_desc_dma, GFP_ATOMIC); + if (!re->rx) + goto err_cleanup; + + for (i = 0; i < NUM_RX_DESC; i++) { + struct sk_buff *skb; + + skb = ramips_alloc_skb(re); + if (!skb) + goto err_cleanup; + + re->rx_info[i].rx_skb = skb; + } + + return 0; + +err_cleanup: + ramips_ring_free(re); + return err; +} + +static void +ramips_setup_dma(struct raeth_priv *re) +{ + ramips_fe_twr(re->tx_desc_dma, RAETH_REG_TX_BASE_PTR0); + ramips_fe_twr(NUM_TX_DESC, RAETH_REG_TX_MAX_CNT0); + ramips_fe_twr(0, RAETH_REG_TX_CTX_IDX0); + ramips_fe_twr(RAMIPS_PST_DTX_IDX0, RAETH_REG_PDMA_RST_CFG); + + ramips_fe_twr(re->rx_desc_dma, RAETH_REG_RX_BASE_PTR0); + ramips_fe_twr(NUM_RX_DESC, RAETH_REG_RX_MAX_CNT0); + ramips_fe_twr((NUM_RX_DESC - 1), RAETH_REG_RX_CALC_IDX0); + ramips_fe_twr(RAMIPS_PST_DRX_IDX0, RAETH_REG_PDMA_RST_CFG); +} + +static int +ramips_eth_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) +{ + struct raeth_priv *re = netdev_priv(dev); + struct raeth_tx_info *txi, *txi_next; + struct ramips_tx_dma *txd, *txd_next; + unsigned long tx; + unsigned int tx_next; + dma_addr_t mapped_addr; + + if (re->plat->min_pkt_len) { + if (skb->len < re->plat->min_pkt_len) { + if (skb_padto(skb, re->plat->min_pkt_len)) { + printk(KERN_ERR + "ramips_eth: skb_padto failed\n"); + kfree_skb(skb); + return 0; + } + skb_put(skb, re->plat->min_pkt_len - skb->len); + } + } + + dev->trans_start = jiffies; + mapped_addr = dma_map_single(&re->netdev->dev, skb->data, skb->len, + DMA_TO_DEVICE); + + spin_lock(&re->page_lock); + tx = ramips_fe_trr(RAETH_REG_TX_CTX_IDX0); + tx_next = (tx + 1) % NUM_TX_DESC; + + txi = &re->tx_info[tx]; + txd = txi->tx_desc; + txi_next = &re->tx_info[tx_next]; + txd_next = txi_next->tx_desc; + + if ((txi->tx_skb) || (txi_next->tx_skb) || + !(txd->txd2 & TX_DMA_DONE) || + !(txd_next->txd2 & TX_DMA_DONE)) + goto out; + + txi->tx_skb = skb; + + txd->txd1 = (unsigned int) mapped_addr; + wmb(); + txd->txd2 = TX_DMA_LSO | TX_DMA_PLEN0(skb->len); + dev->stats.tx_packets++; + dev->stats.tx_bytes += skb->len; + ramips_fe_twr(tx_next, RAETH_REG_TX_CTX_IDX0); + netdev_sent_queue(dev, skb->len); + spin_unlock(&re->page_lock); + return NETDEV_TX_OK; + + out: + spin_unlock(&re->page_lock); + dev->stats.tx_dropped++; + kfree_skb(skb); + return NETDEV_TX_OK; +} + +static void +ramips_eth_rx_hw(unsigned long ptr) +{ + struct net_device *dev = (struct net_device *) ptr; + struct raeth_priv *re = netdev_priv(dev); + int rx; + int max_rx = 16; + + rx = ramips_fe_trr(RAETH_REG_RX_CALC_IDX0); + + while (max_rx) { + struct raeth_rx_info *rxi; + struct ramips_rx_dma *rxd; + struct sk_buff *rx_skb, *new_skb; + int pktlen; + + rx = (rx + 1) % NUM_RX_DESC; + + rxi = &re->rx_info[rx]; + rxd = rxi->rx_desc; + if (!(rxd->rxd2 & RX_DMA_DONE)) + break; + + rx_skb = rxi->rx_skb; + pktlen = RX_DMA_PLEN0(rxd->rxd2); + + new_skb = ramips_alloc_skb(re); + /* Reuse the buffer on allocation failures */ + if (new_skb) { + dma_addr_t dma_addr; + + dma_unmap_single(&re->netdev->dev, rxi->rx_dma, + MAX_RX_LENGTH, DMA_FROM_DEVICE); + + skb_put(rx_skb, pktlen); + rx_skb->dev = dev; + rx_skb->protocol = eth_type_trans(rx_skb, dev); + rx_skb->ip_summed = CHECKSUM_NONE; + dev->stats.rx_packets++; + dev->stats.rx_bytes += pktlen; + netif_rx(rx_skb); + + rxi->rx_skb = new_skb; + + dma_addr = dma_map_single(&re->netdev->dev, + new_skb->data, + MAX_RX_LENGTH, + DMA_FROM_DEVICE); + rxi->rx_dma = dma_addr; + rxd->rxd1 = (unsigned int) dma_addr; + wmb(); + } else { + dev->stats.rx_dropped++; + } + + rxd->rxd2 = RX_DMA_LSO; + ramips_fe_twr(rx, RAETH_REG_RX_CALC_IDX0); + max_rx--; + } + + if (max_rx == 0) + tasklet_schedule(&re->rx_tasklet); + else + ramips_fe_int_enable(RX_DLY_INT); +} + +static void +ramips_eth_tx_housekeeping(unsigned long ptr) +{ + struct net_device *dev = (struct net_device*)ptr; + struct raeth_priv *re = netdev_priv(dev); + unsigned int bytes_compl = 0, pkts_compl = 0; + + spin_lock(&re->page_lock); + while (1) { + struct raeth_tx_info *txi; + struct ramips_tx_dma *txd; + + txi = &re->tx_info[re->skb_free_idx]; + txd = txi->tx_desc; + + if (!(txd->txd2 & TX_DMA_DONE) || !(txi->tx_skb)) + break; + + pkts_compl++; + bytes_compl += txi->tx_skb->len; + + dev_kfree_skb_irq(txi->tx_skb); + txi->tx_skb = NULL; + re->skb_free_idx++; + if (re->skb_free_idx >= NUM_TX_DESC) + re->skb_free_idx = 0; + } + netdev_completed_queue(dev, pkts_compl, bytes_compl); + spin_unlock(&re->page_lock); + + ramips_fe_int_enable(TX_DLY_INT); +} + +static void +ramips_eth_timeout(struct net_device *dev) +{ + struct raeth_priv *re = netdev_priv(dev); + + tasklet_schedule(&re->tx_housekeeping_tasklet); +} + +static irqreturn_t +ramips_eth_irq(int irq, void *dev) +{ + struct raeth_priv *re = netdev_priv(dev); + unsigned int status; + + status = ramips_fe_trr(RAETH_REG_FE_INT_STATUS); + status &= ramips_fe_trr(RAETH_REG_FE_INT_ENABLE); + + if (!status) + return IRQ_NONE; + + ramips_fe_twr(status, RAETH_REG_FE_INT_STATUS); + + if (status & RX_DLY_INT) { + ramips_fe_int_disable(RX_DLY_INT); + tasklet_schedule(&re->rx_tasklet); + } + + if (status & TX_DLY_INT) { + ramips_fe_int_disable(TX_DLY_INT); + tasklet_schedule(&re->tx_housekeeping_tasklet); + } + + raeth_debugfs_update_int_stats(re, status); + + return IRQ_HANDLED; +} + +static int +ramips_eth_hw_init(struct net_device *dev) +{ + struct raeth_priv *re = netdev_priv(dev); + int err; + + err = request_irq(dev->irq, ramips_eth_irq, IRQF_DISABLED, + dev->name, dev); + if (err) + return err; + + err = ramips_ring_alloc(re); + if (err) + goto err_free_irq; + + ramips_ring_setup(re); + ramips_hw_set_macaddr(dev->dev_addr); + + ramips_setup_dma(re); + ramips_fe_wr((ramips_fe_rr(RAMIPS_FE_GLO_CFG) & + ~(RAMIPS_US_CYC_CNT_MASK << RAMIPS_US_CYC_CNT_SHIFT)) | + ((re->plat->sys_freq / RAMIPS_US_CYC_CNT_DIVISOR) << RAMIPS_US_CYC_CNT_SHIFT), + RAMIPS_FE_GLO_CFG); + + tasklet_init(&re->tx_housekeeping_tasklet, ramips_eth_tx_housekeeping, + (unsigned long)dev); + tasklet_init(&re->rx_tasklet, ramips_eth_rx_hw, (unsigned long)dev); + + + ramips_fe_twr(RAMIPS_DELAY_INIT, RAETH_REG_DLY_INT_CFG); + ramips_fe_twr(TX_DLY_INT | RX_DLY_INT, RAETH_REG_FE_INT_ENABLE); + if (soc_is_rt5350()) { + ramips_fe_wr(ramips_fe_rr(RT5350_SDM_CFG) & + ~(RT5350_SDM_ICS_EN | RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN | 0xffff), + RT5350_SDM_CFG); + } else { + ramips_fe_wr(ramips_fe_rr(RAMIPS_GDMA1_FWD_CFG) & + ~(RAMIPS_GDM1_ICS_EN | RAMIPS_GDM1_TCS_EN | RAMIPS_GDM1_UCS_EN | 0xffff), + RAMIPS_GDMA1_FWD_CFG); + ramips_fe_wr(ramips_fe_rr(RAMIPS_CDMA_CSG_CFG) & + ~(RAMIPS_ICS_GEN_EN | RAMIPS_TCS_GEN_EN | RAMIPS_UCS_GEN_EN), + RAMIPS_CDMA_CSG_CFG); + ramips_fe_wr(RAMIPS_PSE_FQFC_CFG_INIT, RAMIPS_PSE_FQ_CFG); + } + ramips_fe_wr(1, RAMIPS_FE_RST_GL); + ramips_fe_wr(0, RAMIPS_FE_RST_GL); + + return 0; + +err_free_irq: + free_irq(dev->irq, dev); + return err; +} + +static int +ramips_eth_open(struct net_device *dev) +{ + struct raeth_priv *re = netdev_priv(dev); + + ramips_fe_twr((ramips_fe_trr(RAETH_REG_PDMA_GLO_CFG) & 0xff) | + (RAMIPS_TX_WB_DDONE | RAMIPS_RX_DMA_EN | + RAMIPS_TX_DMA_EN | RAMIPS_PDMA_SIZE_4DWORDS), + RAETH_REG_PDMA_GLO_CFG); + ramips_phy_start(re); + netif_start_queue(dev); + return 0; +} + +static int +ramips_eth_stop(struct net_device *dev) +{ + struct raeth_priv *re = netdev_priv(dev); + + ramips_fe_twr(ramips_fe_trr(RAETH_REG_PDMA_GLO_CFG) & + ~(RAMIPS_TX_WB_DDONE | RAMIPS_RX_DMA_EN | RAMIPS_TX_DMA_EN), + RAETH_REG_PDMA_GLO_CFG); + + netif_stop_queue(dev); + ramips_phy_stop(re); + RADEBUG("ramips_eth: stopped\n"); + return 0; +} + +static int __init +ramips_eth_probe(struct net_device *dev) +{ + struct raeth_priv *re = netdev_priv(dev); + int err; + + BUG_ON(!re->plat->reset_fe); + re->plat->reset_fe(); + net_srandom(jiffies); + memcpy(dev->dev_addr, re->plat->mac, ETH_ALEN); + + ether_setup(dev); + dev->mtu = 1500; + dev->watchdog_timeo = TX_TIMEOUT; + spin_lock_init(&re->page_lock); + spin_lock_init(&re->phy_lock); + + err = ramips_mdio_init(re); + if (err) + return err; + + err = ramips_phy_connect(re); + if (err) + goto err_mdio_cleanup; + + err = raeth_debugfs_init(re); + if (err) + goto err_phy_disconnect; + + err = ramips_eth_hw_init(dev); + if (err) + goto err_debugfs; + + return 0; + +err_debugfs: + raeth_debugfs_exit(re); +err_phy_disconnect: + ramips_phy_disconnect(re); +err_mdio_cleanup: + ramips_mdio_cleanup(re); + return err; +} + +static void +ramips_eth_uninit(struct net_device *dev) +{ + struct raeth_priv *re = netdev_priv(dev); + + raeth_debugfs_exit(re); + ramips_phy_disconnect(re); + ramips_mdio_cleanup(re); + ramips_fe_twr(0, RAETH_REG_FE_INT_ENABLE); + free_irq(dev->irq, dev); + tasklet_kill(&re->tx_housekeeping_tasklet); + tasklet_kill(&re->rx_tasklet); + ramips_ring_cleanup(re); + ramips_ring_free(re); +} + +static const struct net_device_ops ramips_eth_netdev_ops = { + .ndo_init = ramips_eth_probe, + .ndo_uninit = ramips_eth_uninit, + .ndo_open = ramips_eth_open, + .ndo_stop = ramips_eth_stop, + .ndo_start_xmit = ramips_eth_hard_start_xmit, + .ndo_tx_timeout = ramips_eth_timeout, + .ndo_change_mtu = eth_change_mtu, + .ndo_set_mac_address = eth_mac_addr, + .ndo_validate_addr = eth_validate_addr, +}; + +static int +ramips_eth_plat_probe(struct platform_device *plat) +{ + struct raeth_priv *re; + struct ramips_eth_platform_data *data = plat->dev.platform_data; + struct resource *res; + int err; + + if (!data) { + dev_err(&plat->dev, "no platform data specified\n"); + return -EINVAL; + } + + res = platform_get_resource(plat, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&plat->dev, "no memory resource found\n"); + return -ENXIO; + } + + ramips_fe_base = ioremap_nocache(res->start, res->end - res->start + 1); + if (!ramips_fe_base) + return -ENOMEM; + + ramips_dev = alloc_etherdev(sizeof(struct raeth_priv)); + if (!ramips_dev) { + dev_err(&plat->dev, "alloc_etherdev failed\n"); + err = -ENOMEM; + goto err_unmap; + } + + strcpy(ramips_dev->name, "eth%d"); + ramips_dev->irq = platform_get_irq(plat, 0); + if (ramips_dev->irq < 0) { + dev_err(&plat->dev, "no IRQ resource found\n"); + err = -ENXIO; + goto err_free_dev; + } + ramips_dev->addr_len = ETH_ALEN; + ramips_dev->base_addr = (unsigned long)ramips_fe_base; + ramips_dev->netdev_ops = &ramips_eth_netdev_ops; + + re = netdev_priv(ramips_dev); + + re->netdev = ramips_dev; + re->parent = &plat->dev; + re->speed = data->speed; + re->duplex = data->duplex; + re->rx_fc = data->rx_fc; + re->tx_fc = data->tx_fc; + re->plat = data; + + err = register_netdev(ramips_dev); + if (err) { + dev_err(&plat->dev, "error bringing up device\n"); + goto err_free_dev; + } + + RADEBUG("ramips_eth: loaded\n"); + return 0; + + err_free_dev: + kfree(ramips_dev); + err_unmap: + iounmap(ramips_fe_base); + return err; +} + +static int +ramips_eth_plat_remove(struct platform_device *plat) +{ + unregister_netdev(ramips_dev); + free_netdev(ramips_dev); + RADEBUG("ramips_eth: unloaded\n"); + return 0; +} + +static struct platform_driver ramips_eth_driver = { + .probe = ramips_eth_plat_probe, + .remove = ramips_eth_plat_remove, + .driver = { + .name = "ramips_eth", + .owner = THIS_MODULE, + }, +}; + +static int __init +ramips_eth_init(void) +{ + int ret; + + ret = raeth_debugfs_root_init(); + if (ret) + goto err_out; + + ret = rt305x_esw_init(); + if (ret) + goto err_debugfs_exit; + + ret = platform_driver_register(&ramips_eth_driver); + if (ret) { + printk(KERN_ERR + "ramips_eth: Error registering platfom driver!\n"); + goto esw_cleanup; + } + + return 0; + +esw_cleanup: + rt305x_esw_exit(); +err_debugfs_exit: + raeth_debugfs_root_exit(); +err_out: + return ret; +} + +static void __exit +ramips_eth_cleanup(void) +{ + platform_driver_unregister(&ramips_eth_driver); + rt305x_esw_exit(); + raeth_debugfs_root_exit(); +} + +module_init(ramips_eth_init); +module_exit(ramips_eth_cleanup); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("John Crispin "); +MODULE_DESCRIPTION("ethernet driver for ramips boards"); diff --git a/target/linux/ramips/files-3.7/drivers/spi/spi-ramips.c b/target/linux/ramips/files-3.7/drivers/spi/spi-ramips.c new file mode 100644 index 0000000000..d2ceaf3b8d --- /dev/null +++ b/target/linux/ramips/files-3.7/drivers/spi/spi-ramips.c @@ -0,0 +1,559 @@ +/* + * ramips_spi.c -- Ralink RT288x/RT305x SPI controller driver + * + * Copyright (C) 2011 Sergiy + * Copyright (C) 2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRIVER_NAME "ramips-spi" +#define RALINK_NUM_CHIPSELECTS 1 /* only one slave is supported*/ +#define RALINK_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */ + +#define RAMIPS_SPI_STAT 0x00 +#define RAMIPS_SPI_CFG 0x10 +#define RAMIPS_SPI_CTL 0x14 +#define RAMIPS_SPI_DATA 0x20 + +/* SPISTAT register bit field */ +#define SPISTAT_BUSY BIT(0) + +/* SPICFG register bit field */ +#define SPICFG_LSBFIRST 0 +#define SPICFG_MSBFIRST BIT(8) +#define SPICFG_SPICLKPOL BIT(6) +#define SPICFG_RXCLKEDGE_FALLING BIT(5) +#define SPICFG_TXCLKEDGE_FALLING BIT(4) +#define SPICFG_SPICLK_PRESCALE_MASK 0x7 +#define SPICFG_SPICLK_DIV2 0 +#define SPICFG_SPICLK_DIV4 1 +#define SPICFG_SPICLK_DIV8 2 +#define SPICFG_SPICLK_DIV16 3 +#define SPICFG_SPICLK_DIV32 4 +#define SPICFG_SPICLK_DIV64 5 +#define SPICFG_SPICLK_DIV128 6 +#define SPICFG_SPICLK_DISABLE 7 + +/* SPICTL register bit field */ +#define SPICTL_HIZSDO BIT(3) +#define SPICTL_STARTWR BIT(2) +#define SPICTL_STARTRD BIT(1) +#define SPICTL_SPIENA BIT(0) + +#ifdef DEBUG +#define spi_debug(args...) printk(args) +#else +#define spi_debug(args...) +#endif + +struct ramips_spi { + struct work_struct work; + + /* Lock access to transfer list.*/ + spinlock_t lock; + + struct list_head msg_queue; + struct spi_master *master; + void __iomem *base; + unsigned int sys_freq; + unsigned int speed; + + struct clk *clk; +}; + +static struct workqueue_struct *ramips_spi_wq; + +static inline struct ramips_spi *ramips_spidev_to_rs(struct spi_device *spi) +{ + return spi_master_get_devdata(spi->master); +} + +static inline u32 ramips_spi_read(struct ramips_spi *rs, u32 reg) +{ + return ioread32(rs->base + reg); +} + +static inline void ramips_spi_write(struct ramips_spi *rs, u32 reg, u32 val) +{ + iowrite32(val, rs->base + reg); +} + +static inline void ramips_spi_setbits(struct ramips_spi *rs, u32 reg, u32 mask) +{ + void __iomem *addr = rs->base + reg; + u32 val; + + val = ioread32(addr); + val |= mask; + iowrite32(val, addr); +} + +static inline void ramips_spi_clrbits(struct ramips_spi *rs, u32 reg, u32 mask) +{ + void __iomem *addr = rs->base + reg; + u32 val; + + val = ioread32(addr); + val &= ~mask; + iowrite32(val, addr); +} + +static int ramips_spi_baudrate_set(struct spi_device *spi, unsigned int speed) +{ + struct ramips_spi *rs = ramips_spidev_to_rs(spi); + u32 rate; + u32 prescale; + u32 reg; + + spi_debug("%s: speed:%u\n", __func__, speed); + + /* + * the supported rates are: 2,4,8...128 + * round up as we look for equal or less speed + */ + rate = DIV_ROUND_UP(rs->sys_freq, speed); + spi_debug("%s: rate-1:%u\n", __func__, rate); + rate = roundup_pow_of_two(rate); + spi_debug("%s: rate-2:%u\n", __func__, rate); + + /* check if requested speed is too small */ + if (rate > 128) + return -EINVAL; + + if (rate < 2) + rate = 2; + + /* Convert the rate to SPI clock divisor value. */ + prescale = ilog2(rate/2); + spi_debug("%s: prescale:%u\n", __func__, prescale); + + reg = ramips_spi_read(rs, RAMIPS_SPI_CFG); + reg = ((reg & ~SPICFG_SPICLK_PRESCALE_MASK) | prescale); + ramips_spi_write(rs, RAMIPS_SPI_CFG, reg); + rs->speed = speed; + return 0; +} + +/* + * called only when no transfer is active on the bus + */ +static int +ramips_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) +{ + struct ramips_spi *rs = ramips_spidev_to_rs(spi); + unsigned int speed = spi->max_speed_hz; + int rc; + unsigned int bits_per_word = 8; + + if ((t != NULL) && t->speed_hz) + speed = t->speed_hz; + + if ((t != NULL) && t->bits_per_word) + bits_per_word = t->bits_per_word; + + if (rs->speed != speed) { + spi_debug("%s: speed_hz:%u\n", __func__, speed); + rc = ramips_spi_baudrate_set(spi, speed); + if (rc) + return rc; + } + + if (bits_per_word != 8) { + spi_debug("%s: bad bits_per_word: %u\n", __func__, + bits_per_word); + return -EINVAL; + } + + return 0; +} + +static void ramips_spi_set_cs(struct ramips_spi *rs, int enable) +{ + if (enable) + ramips_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA); + else + ramips_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA); +} + +static inline int ramips_spi_wait_till_ready(struct ramips_spi *rs) +{ + int i; + + for (i = 0; i < RALINK_SPI_WAIT_RDY_MAX_LOOP; i++) { + u32 status; + + status = ramips_spi_read(rs, RAMIPS_SPI_STAT); + if ((status & SPISTAT_BUSY) == 0) + return 0; + + udelay(1); + } + + return -ETIMEDOUT; +} + +static unsigned int +ramips_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer) +{ + struct ramips_spi *rs = ramips_spidev_to_rs(spi); + unsigned count = 0; + u8 *rx = xfer->rx_buf; + const u8 *tx = xfer->tx_buf; + int err; + + spi_debug("%s(%d): %s %s\n", __func__, xfer->len, + (tx != NULL) ? "tx" : " ", + (rx != NULL) ? "rx" : " "); + + if (tx) { + for (count = 0; count < xfer->len; count++) { + ramips_spi_write(rs, RAMIPS_SPI_DATA, tx[count]); + ramips_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR); + err = ramips_spi_wait_till_ready(rs); + if (err) { + dev_err(&spi->dev, "TX failed, err=%d\n", err); + goto out; + } + } + } + + if (rx) { + for (count = 0; count < xfer->len; count++) { + ramips_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD); + err = ramips_spi_wait_till_ready(rs); + if (err) { + dev_err(&spi->dev, "RX failed, err=%d\n", err); + goto out; + } + rx[count] = (u8) ramips_spi_read(rs, RAMIPS_SPI_DATA); + } + } + +out: + return count; +} + +static void ramips_spi_work(struct work_struct *work) +{ + struct ramips_spi *rs = + container_of(work, struct ramips_spi, work); + + spin_lock_irq(&rs->lock); + while (!list_empty(&rs->msg_queue)) { + struct spi_message *m; + struct spi_device *spi; + struct spi_transfer *t = NULL; + int par_override = 0; + int status = 0; + int cs_active = 0; + + m = container_of(rs->msg_queue.next, struct spi_message, + queue); + + list_del_init(&m->queue); + spin_unlock_irq(&rs->lock); + + spi = m->spi; + + /* Load defaults */ + status = ramips_spi_setup_transfer(spi, NULL); + + if (status < 0) + goto msg_done; + + list_for_each_entry(t, &m->transfers, transfer_list) { + if (par_override || t->speed_hz || t->bits_per_word) { + par_override = 1; + status = ramips_spi_setup_transfer(spi, t); + if (status < 0) + break; + if (!t->speed_hz && !t->bits_per_word) + par_override = 0; + } + + if (!cs_active) { + ramips_spi_set_cs(rs, 1); + cs_active = 1; + } + + if (t->len) + m->actual_length += + ramips_spi_write_read(spi, t); + + if (t->delay_usecs) + udelay(t->delay_usecs); + + if (t->cs_change) { + ramips_spi_set_cs(rs, 0); + cs_active = 0; + } + } + +msg_done: + if (cs_active) + ramips_spi_set_cs(rs, 0); + + m->status = status; + m->complete(m->context); + + spin_lock_irq(&rs->lock); + } + + spin_unlock_irq(&rs->lock); +} + +static int ramips_spi_setup(struct spi_device *spi) +{ + struct ramips_spi *rs = ramips_spidev_to_rs(spi); + + if ((spi->max_speed_hz == 0) || + (spi->max_speed_hz > (rs->sys_freq / 2))) + spi->max_speed_hz = (rs->sys_freq / 2); + + if (spi->max_speed_hz < (rs->sys_freq/128)) { + dev_err(&spi->dev, "setup: requested speed too low %d Hz\n", + spi->max_speed_hz); + return -EINVAL; + } + + if (spi->bits_per_word != 0 && spi->bits_per_word != 8) { + dev_err(&spi->dev, + "setup: requested bits per words - os wrong %d bpw\n", + spi->bits_per_word); + return -EINVAL; + } + + if (spi->bits_per_word == 0) + spi->bits_per_word = 8; + + /* + * baudrate & width will be set ramips_spi_setup_transfer + */ + return 0; +} + +static int ramips_spi_transfer(struct spi_device *spi, struct spi_message *m) +{ + struct ramips_spi *rs; + struct spi_transfer *t = NULL; + unsigned long flags; + + m->actual_length = 0; + m->status = 0; + + /* reject invalid messages and transfers */ + if (list_empty(&m->transfers) || !m->complete) + return -EINVAL; + + rs = ramips_spidev_to_rs(spi); + + list_for_each_entry(t, &m->transfers, transfer_list) { + unsigned int bits_per_word = spi->bits_per_word; + + if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) { + dev_err(&spi->dev, + "message rejected : " + "invalid transfer data buffers\n"); + goto msg_rejected; + } + + if (t->bits_per_word) + bits_per_word = t->bits_per_word; + + if (bits_per_word != 8) { + dev_err(&spi->dev, + "message rejected : " + "invalid transfer bits_per_word (%d bits)\n", + bits_per_word); + goto msg_rejected; + } + + if (t->speed_hz && t->speed_hz < (rs->sys_freq/128)) { + dev_err(&spi->dev, + "message rejected : " + "device min speed (%d Hz) exceeds " + "required transfer speed (%d Hz)\n", + (rs->sys_freq/128), t->speed_hz); + goto msg_rejected; + } + } + + + spin_lock_irqsave(&rs->lock, flags); + list_add_tail(&m->queue, &rs->msg_queue); + queue_work(ramips_spi_wq, &rs->work); + spin_unlock_irqrestore(&rs->lock, flags); + + return 0; +msg_rejected: + /* Message rejected and not queued */ + m->status = -EINVAL; + if (m->complete) + m->complete(m->context); + return -EINVAL; +} + +static void __init ramips_spi_reset(struct ramips_spi *rs) +{ + ramips_spi_write(rs, RAMIPS_SPI_CFG, + SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING | + SPICFG_SPICLK_DIV16 | SPICFG_SPICLKPOL); + ramips_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA); +} + +static int __init ramips_spi_probe(struct platform_device *pdev) +{ + struct spi_master *master; + struct ramips_spi *rs; + struct resource *r; + int status = 0; + + master = spi_alloc_master(&pdev->dev, sizeof(*rs)); + if (master == NULL) { + dev_dbg(&pdev->dev, "master allocation failed\n"); + return -ENOMEM; + } + + if (pdev->id != -1) + master->bus_num = pdev->id; + + /* we support only mode 0, and no options */ + master->mode_bits = 0; + + master->setup = ramips_spi_setup; + master->transfer = ramips_spi_transfer; + master->num_chipselect = RALINK_NUM_CHIPSELECTS; + + dev_set_drvdata(&pdev->dev, master); + + rs = spi_master_get_devdata(master); + rs->master = master; + + rs->clk = clk_get(NULL, "sys"); + if (IS_ERR(rs->clk)) { + status = PTR_ERR(rs->clk); + dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n", + status); + goto out_put_master; + } + + status = clk_enable(rs->clk); + if (status) + goto out_put_clk; + + rs->sys_freq = clk_get_rate(rs->clk); + spi_debug("%s: sys_freq: %ld\n", __func__, rs->sys_freq); + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (r == NULL) { + status = -ENODEV; + goto out_disable_clk; + } + + if (!request_mem_region(r->start, (r->end - r->start) + 1, + dev_name(&pdev->dev))) { + status = -EBUSY; + goto out_disable_clk; + } + + rs->base = ioremap(r->start, resource_size(r)); + if (rs->base == NULL) { + dev_err(&pdev->dev, "ioremap failed\n"); + status = -ENOMEM; + goto out_rel_mem; + } + + INIT_WORK(&rs->work, ramips_spi_work); + + spin_lock_init(&rs->lock); + INIT_LIST_HEAD(&rs->msg_queue); + + ramips_spi_reset(rs); + + status = spi_register_master(master); + if (status) + goto out_unmap_base; + + return 0; + +out_unmap_base: + iounmap(rs->base); +out_rel_mem: + release_mem_region(r->start, (r->end - r->start) + 1); +out_disable_clk: + clk_disable(rs->clk); +out_put_clk: + clk_put(rs->clk); +out_put_master: + spi_master_put(master); + return status; +} + +static int ramips_spi_remove(struct platform_device *pdev) +{ + struct spi_master *master; + struct ramips_spi *rs; + struct resource *r; + + master = dev_get_drvdata(&pdev->dev); + rs = spi_master_get_devdata(master); + + cancel_work_sync(&rs->work); + + iounmap(rs->base); + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(r->start, (r->end - r->start) + 1); + + clk_disable(rs->clk); + clk_put(rs->clk); + spi_unregister_master(master); + + return 0; +} + +MODULE_ALIAS("platform:" DRIVER_NAME); + +static struct platform_driver ramips_spi_driver = { + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + }, + .remove = ramips_spi_remove, +}; + +static int __init ramips_spi_init(void) +{ + ramips_spi_wq = create_singlethread_workqueue( + ramips_spi_driver.driver.name); + if (ramips_spi_wq == NULL) + return -ENOMEM; + + return platform_driver_probe(&ramips_spi_driver, ramips_spi_probe); +} +module_init(ramips_spi_init); + +static void __exit ramips_spi_exit(void) +{ + flush_workqueue(ramips_spi_wq); + platform_driver_unregister(&ramips_spi_driver); + + destroy_workqueue(ramips_spi_wq); +} +module_exit(ramips_spi_exit); + +MODULE_DESCRIPTION("Ralink SPI driver"); +MODULE_AUTHOR("Sergiy "); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_LICENSE("GPL"); diff --git a/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/Kconfig b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/Kconfig new file mode 100644 index 0000000000..6dd75f14a3 --- /dev/null +++ b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/Kconfig @@ -0,0 +1,24 @@ +config DWC_OTG + tristate "Ralink RT305X DWC_OTG support" + depends on SOC_RT305X + ---help--- + This driver supports Ralink DWC_OTG + +choice + prompt "USB Operation Mode" + depends on DWC_OTG + default DWC_OTG_HOST_ONLY + +config DWC_OTG_HOST_ONLY + bool "HOST ONLY MODE" + depends on DWC_OTG + +config DWC_OTG_DEVICE_ONLY + bool "DEVICE ONLY MODE" + depends on DWC_OTG + +endchoice + +config DWC_OTG_DEBUG + bool "Enable debug mode" + depends on DWC_OTG diff --git a/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/Makefile b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/Makefile new file mode 100644 index 0000000000..95c5b66fea --- /dev/null +++ b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/Makefile @@ -0,0 +1,25 @@ +# +# Makefile for DWC_otg Highspeed USB controller driver +# + +ifeq ($(CONFIG_DWC_OTG_DEBUG),y) +EXTRA_CFLAGS += -DDEBUG +endif + +# Use one of the following flags to compile the software in host-only or +# device-only mode. +ifeq ($(CONFIG_DWC_OTG_HOST_ONLY),y) +EXTRA_CFLAGS += -DDWC_HOST_ONLY +EXTRA_CFLAGS += -DDWC_EN_ISOC +endif + +ifeq ($(CONFIG_DWC_OTG_DEVICE_ONLY),y) +EXTRA_CFLAGS += -DDWC_DEVICE_ONLY +endif + +obj-$(CONFIG_DWC_OTG) := dwc_otg.o + +dwc_otg-objs := dwc_otg_driver.o dwc_otg_attr.o +dwc_otg-objs += dwc_otg_cil.o dwc_otg_cil_intr.o +dwc_otg-objs += dwc_otg_pcd.o dwc_otg_pcd_intr.o +dwc_otg-objs += dwc_otg_hcd.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o diff --git a/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dummy_audio.c b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dummy_audio.c new file mode 100644 index 0000000000..225decf765 --- /dev/null +++ b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dummy_audio.c @@ -0,0 +1,1575 @@ +/* + * zero.c -- Gadget Zero, for USB development + * + * Copyright (C) 2003-2004 David Brownell + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The names of the above-listed copyright holders may not be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/* + * Gadget Zero only needs two bulk endpoints, and is an example of how you + * can write a hardware-agnostic gadget driver running inside a USB device. + * + * Hardware details are visible (see CONFIG_USB_ZERO_* below) but don't + * affect most of the driver. + * + * Use it with the Linux host/master side "usbtest" driver to get a basic + * functional test of your device-side usb stack, or with "usb-skeleton". + * + * It supports two similar configurations. One sinks whatever the usb host + * writes, and in return sources zeroes. The other loops whatever the host + * writes back, so the host can read it. Module options include: + * + * buflen=N default N=4096, buffer size used + * qlen=N default N=32, how many buffers in the loopback queue + * loopdefault default false, list loopback config first + * + * Many drivers will only have one configuration, letting them be much + * simpler if they also don't support high speed operation (like this + * driver does). + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21) +# include +#else +# include +#endif + +#include + + +/*-------------------------------------------------------------------------*/ +/*-------------------------------------------------------------------------*/ + + +static int utf8_to_utf16le(const char *s, u16 *cp, unsigned len) +{ + int count = 0; + u8 c; + u16 uchar; + + /* this insists on correct encodings, though not minimal ones. + * BUT it currently rejects legit 4-byte UTF-8 code points, + * which need surrogate pairs. (Unicode 3.1 can use them.) + */ + while (len != 0 && (c = (u8) *s++) != 0) { + if (unlikely(c & 0x80)) { + // 2-byte sequence: + // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx + if ((c & 0xe0) == 0xc0) { + uchar = (c & 0x1f) << 6; + + c = (u8) *s++; + if ((c & 0xc0) != 0xc0) + goto fail; + c &= 0x3f; + uchar |= c; + + // 3-byte sequence (most CJKV characters): + // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx + } else if ((c & 0xf0) == 0xe0) { + uchar = (c & 0x0f) << 12; + + c = (u8) *s++; + if ((c & 0xc0) != 0xc0) + goto fail; + c &= 0x3f; + uchar |= c << 6; + + c = (u8) *s++; + if ((c & 0xc0) != 0xc0) + goto fail; + c &= 0x3f; + uchar |= c; + + /* no bogus surrogates */ + if (0xd800 <= uchar && uchar <= 0xdfff) + goto fail; + + // 4-byte sequence (surrogate pairs, currently rare): + // 11101110wwwwzzzzyy + 110111yyyyxxxxxx + // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx + // (uuuuu = wwww + 1) + // FIXME accept the surrogate code points (only) + + } else + goto fail; + } else + uchar = c; + put_unaligned (cpu_to_le16 (uchar), cp++); + count++; + len--; + } + return count; +fail: + return -1; +} + + +/** + * usb_gadget_get_string - fill out a string descriptor + * @table: of c strings encoded using UTF-8 + * @id: string id, from low byte of wValue in get string descriptor + * @buf: at least 256 bytes + * + * Finds the UTF-8 string matching the ID, and converts it into a + * string descriptor in utf16-le. + * Returns length of descriptor (always even) or negative errno + * + * If your driver needs stings in multiple languages, you'll probably + * "switch (wIndex) { ... }" in your ep0 string descriptor logic, + * using this routine after choosing which set of UTF-8 strings to use. + * Note that US-ASCII is a strict subset of UTF-8; any string bytes with + * the eighth bit set will be multibyte UTF-8 characters, not ISO-8859/1 + * characters (which are also widely used in C strings). + */ +int +usb_gadget_get_string (struct usb_gadget_strings *table, int id, u8 *buf) +{ + struct usb_string *s; + int len; + + /* descriptor 0 has the language id */ + if (id == 0) { + buf [0] = 4; + buf [1] = USB_DT_STRING; + buf [2] = (u8) table->language; + buf [3] = (u8) (table->language >> 8); + return 4; + } + for (s = table->strings; s && s->s; s++) + if (s->id == id) + break; + + /* unrecognized: stall. */ + if (!s || !s->s) + return -EINVAL; + + /* string descriptors have length, tag, then UTF16-LE text */ + len = min ((size_t) 126, strlen (s->s)); + memset (buf + 2, 0, 2 * len); /* zero all the bytes */ + len = utf8_to_utf16le(s->s, (u16 *)&buf[2], len); + if (len < 0) + return -EINVAL; + buf [0] = (len + 1) * 2; + buf [1] = USB_DT_STRING; + return buf [0]; +} + + +/*-------------------------------------------------------------------------*/ +/*-------------------------------------------------------------------------*/ + + +/** + * usb_descriptor_fillbuf - fill buffer with descriptors + * @buf: Buffer to be filled + * @buflen: Size of buf + * @src: Array of descriptor pointers, terminated by null pointer. + * + * Copies descriptors into the buffer, returning the length or a + * negative error code if they can't all be copied. Useful when + * assembling descriptors for an associated set of interfaces used + * as part of configuring a composite device; or in other cases where + * sets of descriptors need to be marshaled. + */ +int +usb_descriptor_fillbuf(void *buf, unsigned buflen, + const struct usb_descriptor_header **src) +{ + u8 *dest = buf; + + if (!src) + return -EINVAL; + + /* fill buffer from src[] until null descriptor ptr */ + for (; 0 != *src; src++) { + unsigned len = (*src)->bLength; + + if (len > buflen) + return -EINVAL; + memcpy(dest, *src, len); + buflen -= len; + dest += len; + } + return dest - (u8 *)buf; +} + + +/** + * usb_gadget_config_buf - builts a complete configuration descriptor + * @config: Header for the descriptor, including characteristics such + * as power requirements and number of interfaces. + * @desc: Null-terminated vector of pointers to the descriptors (interface, + * endpoint, etc) defining all functions in this device configuration. + * @buf: Buffer for the resulting configuration descriptor. + * @length: Length of buffer. If this is not big enough to hold the + * entire configuration descriptor, an error code will be returned. + * + * This copies descriptors into the response buffer, building a descriptor + * for that configuration. It returns the buffer length or a negative + * status code. The config.wTotalLength field is set to match the length + * of the result, but other descriptor fields (including power usage and + * interface count) must be set by the caller. + * + * Gadget drivers could use this when constructing a config descriptor + * in response to USB_REQ_GET_DESCRIPTOR. They will need to patch the + * resulting bDescriptorType value if USB_DT_OTHER_SPEED_CONFIG is needed. + */ +int usb_gadget_config_buf( + const struct usb_config_descriptor *config, + void *buf, + unsigned length, + const struct usb_descriptor_header **desc +) +{ + struct usb_config_descriptor *cp = buf; + int len; + + /* config descriptor first */ + if (length < USB_DT_CONFIG_SIZE || !desc) + return -EINVAL; + *cp = *config; + + /* then interface/endpoint/class/vendor/... */ + len = usb_descriptor_fillbuf(USB_DT_CONFIG_SIZE + (u8*)buf, + length - USB_DT_CONFIG_SIZE, desc); + if (len < 0) + return len; + len += USB_DT_CONFIG_SIZE; + if (len > 0xffff) + return -EINVAL; + + /* patch up the config descriptor */ + cp->bLength = USB_DT_CONFIG_SIZE; + cp->bDescriptorType = USB_DT_CONFIG; + cp->wTotalLength = cpu_to_le16(len); + cp->bmAttributes |= USB_CONFIG_ATT_ONE; + return len; +} + +/*-------------------------------------------------------------------------*/ +/*-------------------------------------------------------------------------*/ + + +#define RBUF_LEN (1024*1024) +static int rbuf_start; +static int rbuf_len; +static __u8 rbuf[RBUF_LEN]; + +/*-------------------------------------------------------------------------*/ + +#define DRIVER_VERSION "St Patrick's Day 2004" + +static const char shortname [] = "zero"; +static const char longname [] = "YAMAHA YST-MS35D USB Speaker "; + +static const char source_sink [] = "source and sink data"; +static const char loopback [] = "loop input to output"; + +/*-------------------------------------------------------------------------*/ + +/* + * driver assumes self-powered hardware, and + * has no way for users to trigger remote wakeup. + * + * this version autoconfigures as much as possible, + * which is reasonable for most "bulk-only" drivers. + */ +static const char *EP_IN_NAME; /* source */ +static const char *EP_OUT_NAME; /* sink */ + +/*-------------------------------------------------------------------------*/ + +/* big enough to hold our biggest descriptor */ +#define USB_BUFSIZ 512 + +struct zero_dev { + spinlock_t lock; + struct usb_gadget *gadget; + struct usb_request *req; /* for control responses */ + + /* when configured, we have one of two configs: + * - source data (in to host) and sink it (out from host) + * - or loop it back (out from host back in to host) + */ + u8 config; + struct usb_ep *in_ep, *out_ep; + + /* autoresume timer */ + struct timer_list resume; +}; + +#define xprintk(d,level,fmt,args...) \ + dev_printk(level , &(d)->gadget->dev , fmt , ## args) + +#ifdef DEBUG +#define DBG(dev,fmt,args...) \ + xprintk(dev , KERN_DEBUG , fmt , ## args) +#else +#define DBG(dev,fmt,args...) \ + do { } while (0) +#endif /* DEBUG */ + +#ifdef VERBOSE +#define VDBG DBG +#else +#define VDBG(dev,fmt,args...) \ + do { } while (0) +#endif /* VERBOSE */ + +#define ERROR(dev,fmt,args...) \ + xprintk(dev , KERN_ERR , fmt , ## args) +#define WARN(dev,fmt,args...) \ + xprintk(dev , KERN_WARNING , fmt , ## args) +#define INFO(dev,fmt,args...) \ + xprintk(dev , KERN_INFO , fmt , ## args) + +/*-------------------------------------------------------------------------*/ + +static unsigned buflen = 4096; +static unsigned qlen = 32; +static unsigned pattern = 0; + +module_param (buflen, uint, S_IRUGO|S_IWUSR); +module_param (qlen, uint, S_IRUGO|S_IWUSR); +module_param (pattern, uint, S_IRUGO|S_IWUSR); + +/* + * if it's nonzero, autoresume says how many seconds to wait + * before trying to wake up the host after suspend. + */ +static unsigned autoresume = 0; +module_param (autoresume, uint, 0); + +/* + * Normally the "loopback" configuration is second (index 1) so + * it's not the default. Here's where to change that order, to + * work better with hosts where config changes are problematic. + * Or controllers (like superh) that only support one config. + */ +static int loopdefault = 0; + +module_param (loopdefault, bool, S_IRUGO|S_IWUSR); + +/*-------------------------------------------------------------------------*/ + +/* Thanks to NetChip Technologies for donating this product ID. + * + * DO NOT REUSE THESE IDs with a protocol-incompatible driver!! Ever!! + * Instead: allocate your own, using normal USB-IF procedures. + */ +#ifndef CONFIG_USB_ZERO_HNPTEST +#define DRIVER_VENDOR_NUM 0x0525 /* NetChip */ +#define DRIVER_PRODUCT_NUM 0xa4a0 /* Linux-USB "Gadget Zero" */ +#else +#define DRIVER_VENDOR_NUM 0x1a0a /* OTG test device IDs */ +#define DRIVER_PRODUCT_NUM 0xbadd +#endif + +/*-------------------------------------------------------------------------*/ + +/* + * DESCRIPTORS ... most are static, but strings and (full) + * configuration descriptors are built on demand. + */ + +/* +#define STRING_MANUFACTURER 25 +#define STRING_PRODUCT 42 +#define STRING_SERIAL 101 +*/ +#define STRING_MANUFACTURER 1 +#define STRING_PRODUCT 2 +#define STRING_SERIAL 3 + +#define STRING_SOURCE_SINK 250 +#define STRING_LOOPBACK 251 + +/* + * This device advertises two configurations; these numbers work + * on a pxa250 as well as more flexible hardware. + */ +#define CONFIG_SOURCE_SINK 3 +#define CONFIG_LOOPBACK 2 + +/* +static struct usb_device_descriptor +device_desc = { + .bLength = sizeof device_desc, + .bDescriptorType = USB_DT_DEVICE, + + .bcdUSB = __constant_cpu_to_le16 (0x0200), + .bDeviceClass = USB_CLASS_VENDOR_SPEC, + + .idVendor = __constant_cpu_to_le16 (DRIVER_VENDOR_NUM), + .idProduct = __constant_cpu_to_le16 (DRIVER_PRODUCT_NUM), + .iManufacturer = STRING_MANUFACTURER, + .iProduct = STRING_PRODUCT, + .iSerialNumber = STRING_SERIAL, + .bNumConfigurations = 2, +}; +*/ +static struct usb_device_descriptor +device_desc = { + .bLength = sizeof device_desc, + .bDescriptorType = USB_DT_DEVICE, + .bcdUSB = __constant_cpu_to_le16 (0x0100), + .bDeviceClass = USB_CLASS_PER_INTERFACE, + .bDeviceSubClass = 0, + .bDeviceProtocol = 0, + .bMaxPacketSize0 = 64, + .bcdDevice = __constant_cpu_to_le16 (0x0100), + .idVendor = __constant_cpu_to_le16 (0x0499), + .idProduct = __constant_cpu_to_le16 (0x3002), + .iManufacturer = STRING_MANUFACTURER, + .iProduct = STRING_PRODUCT, + .iSerialNumber = STRING_SERIAL, + .bNumConfigurations = 1, +}; + +static struct usb_config_descriptor +z_config = { + .bLength = sizeof z_config, + .bDescriptorType = USB_DT_CONFIG, + + /* compute wTotalLength on the fly */ + .bNumInterfaces = 2, + .bConfigurationValue = 1, + .iConfiguration = 0, + .bmAttributes = 0x40, + .bMaxPower = 0, /* self-powered */ +}; + + +static struct usb_otg_descriptor +otg_descriptor = { + .bLength = sizeof otg_descriptor, + .bDescriptorType = USB_DT_OTG, + + .bmAttributes = USB_OTG_SRP, +}; + +/* one interface in each configuration */ +#ifdef CONFIG_USB_GADGET_DUALSPEED + +/* + * usb 2.0 devices need to expose both high speed and full speed + * descriptors, unless they only run at full speed. + * + * that means alternate endpoint descriptors (bigger packets) + * and a "device qualifier" ... plus more construction options + * for the config descriptor. + */ + +static struct usb_qualifier_descriptor +dev_qualifier = { + .bLength = sizeof dev_qualifier, + .bDescriptorType = USB_DT_DEVICE_QUALIFIER, + + .bcdUSB = __constant_cpu_to_le16 (0x0200), + .bDeviceClass = USB_CLASS_VENDOR_SPEC, + + .bNumConfigurations = 2, +}; + + +struct usb_cs_as_general_descriptor { + __u8 bLength; + __u8 bDescriptorType; + + __u8 bDescriptorSubType; + __u8 bTerminalLink; + __u8 bDelay; + __u16 wFormatTag; +} __attribute__ ((packed)); + +struct usb_cs_as_format_descriptor { + __u8 bLength; + __u8 bDescriptorType; + + __u8 bDescriptorSubType; + __u8 bFormatType; + __u8 bNrChannels; + __u8 bSubframeSize; + __u8 bBitResolution; + __u8 bSamfreqType; + __u8 tLowerSamFreq[3]; + __u8 tUpperSamFreq[3]; +} __attribute__ ((packed)); + +static const struct usb_interface_descriptor +z_audio_control_if_desc = { + .bLength = sizeof z_audio_control_if_desc, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = 0, + .bAlternateSetting = 0, + .bNumEndpoints = 0, + .bInterfaceClass = USB_CLASS_AUDIO, + .bInterfaceSubClass = 0x1, + .bInterfaceProtocol = 0, + .iInterface = 0, +}; + +static const struct usb_interface_descriptor +z_audio_if_desc = { + .bLength = sizeof z_audio_if_desc, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = 1, + .bAlternateSetting = 0, + .bNumEndpoints = 0, + .bInterfaceClass = USB_CLASS_AUDIO, + .bInterfaceSubClass = 0x2, + .bInterfaceProtocol = 0, + .iInterface = 0, +}; + +static const struct usb_interface_descriptor +z_audio_if_desc2 = { + .bLength = sizeof z_audio_if_desc, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = 1, + .bAlternateSetting = 1, + .bNumEndpoints = 1, + .bInterfaceClass = USB_CLASS_AUDIO, + .bInterfaceSubClass = 0x2, + .bInterfaceProtocol = 0, + .iInterface = 0, +}; + +static const struct usb_cs_as_general_descriptor +z_audio_cs_as_if_desc = { + .bLength = 7, + .bDescriptorType = 0x24, + + .bDescriptorSubType = 0x01, + .bTerminalLink = 0x01, + .bDelay = 0x0, + .wFormatTag = __constant_cpu_to_le16 (0x0001) +}; + + +static const struct usb_cs_as_format_descriptor +z_audio_cs_as_format_desc = { + .bLength = 0xe, + .bDescriptorType = 0x24, + + .bDescriptorSubType = 2, + .bFormatType = 1, + .bNrChannels = 1, + .bSubframeSize = 1, + .bBitResolution = 8, + .bSamfreqType = 0, + .tLowerSamFreq = {0x7e, 0x13, 0x00}, + .tUpperSamFreq = {0xe2, 0xd6, 0x00}, +}; + +static const struct usb_endpoint_descriptor +z_iso_ep = { + .bLength = 0x09, + .bDescriptorType = 0x05, + .bEndpointAddress = 0x04, + .bmAttributes = 0x09, + .wMaxPacketSize = 0x0038, + .bInterval = 0x01, + .bRefresh = 0x00, + .bSynchAddress = 0x00, +}; + +static char z_iso_ep2[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; + +// 9 bytes +static char z_ac_interface_header_desc[] = +{ 0x09, 0x24, 0x01, 0x00, 0x01, 0x2b, 0x00, 0x01, 0x01 }; + +// 12 bytes +static char z_0[] = {0x0c, 0x24, 0x02, 0x01, 0x01, 0x01, 0x00, 0x02, + 0x03, 0x00, 0x00, 0x00}; +// 13 bytes +static char z_1[] = {0x0d, 0x24, 0x06, 0x02, 0x01, 0x02, 0x15, 0x00, + 0x02, 0x00, 0x02, 0x00, 0x00}; +// 9 bytes +static char z_2[] = {0x09, 0x24, 0x03, 0x03, 0x01, 0x03, 0x00, 0x02, + 0x00}; + +static char za_0[] = {0x09, 0x04, 0x01, 0x02, 0x01, 0x01, 0x02, 0x00, + 0x00}; + +static char za_1[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00}; + +static char za_2[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x01, 0x08, 0x00, + 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00}; + +static char za_3[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00, + 0x00}; + +static char za_4[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; + +static char za_5[] = {0x09, 0x04, 0x01, 0x03, 0x01, 0x01, 0x02, 0x00, + 0x00}; + +static char za_6[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00}; + +static char za_7[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x02, 0x10, 0x00, + 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00}; + +static char za_8[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00, + 0x00}; + +static char za_9[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; + +static char za_10[] = {0x09, 0x04, 0x01, 0x04, 0x01, 0x01, 0x02, 0x00, + 0x00}; + +static char za_11[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00}; + +static char za_12[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x02, 0x10, 0x00, + 0x73, 0x13, 0x00, 0xe2, 0xd6, 0x00}; + +static char za_13[] = {0x09, 0x05, 0x04, 0x09, 0xe0, 0x00, 0x01, 0x00, + 0x00}; + +static char za_14[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; + +static char za_15[] = {0x09, 0x04, 0x01, 0x05, 0x01, 0x01, 0x02, 0x00, + 0x00}; + +static char za_16[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00}; + +static char za_17[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x03, 0x14, 0x00, + 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00}; + +static char za_18[] = {0x09, 0x05, 0x04, 0x09, 0xa8, 0x00, 0x01, 0x00, + 0x00}; + +static char za_19[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; + +static char za_20[] = {0x09, 0x04, 0x01, 0x06, 0x01, 0x01, 0x02, 0x00, + 0x00}; + +static char za_21[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00}; + +static char za_22[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x03, 0x14, 0x00, + 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00}; + +static char za_23[] = {0x09, 0x05, 0x04, 0x09, 0x50, 0x01, 0x01, 0x00, + 0x00}; + +static char za_24[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; + + + +static const struct usb_descriptor_header *z_function [] = { + (struct usb_descriptor_header *) &z_audio_control_if_desc, + (struct usb_descriptor_header *) &z_ac_interface_header_desc, + (struct usb_descriptor_header *) &z_0, + (struct usb_descriptor_header *) &z_1, + (struct usb_descriptor_header *) &z_2, + (struct usb_descriptor_header *) &z_audio_if_desc, + (struct usb_descriptor_header *) &z_audio_if_desc2, + (struct usb_descriptor_header *) &z_audio_cs_as_if_desc, + (struct usb_descriptor_header *) &z_audio_cs_as_format_desc, + (struct usb_descriptor_header *) &z_iso_ep, + (struct usb_descriptor_header *) &z_iso_ep2, + (struct usb_descriptor_header *) &za_0, + (struct usb_descriptor_header *) &za_1, + (struct usb_descriptor_header *) &za_2, + (struct usb_descriptor_header *) &za_3, + (struct usb_descriptor_header *) &za_4, + (struct usb_descriptor_header *) &za_5, + (struct usb_descriptor_header *) &za_6, + (struct usb_descriptor_header *) &za_7, + (struct usb_descriptor_header *) &za_8, + (struct usb_descriptor_header *) &za_9, + (struct usb_descriptor_header *) &za_10, + (struct usb_descriptor_header *) &za_11, + (struct usb_descriptor_header *) &za_12, + (struct usb_descriptor_header *) &za_13, + (struct usb_descriptor_header *) &za_14, + (struct usb_descriptor_header *) &za_15, + (struct usb_descriptor_header *) &za_16, + (struct usb_descriptor_header *) &za_17, + (struct usb_descriptor_header *) &za_18, + (struct usb_descriptor_header *) &za_19, + (struct usb_descriptor_header *) &za_20, + (struct usb_descriptor_header *) &za_21, + (struct usb_descriptor_header *) &za_22, + (struct usb_descriptor_header *) &za_23, + (struct usb_descriptor_header *) &za_24, + NULL, +}; + +/* maxpacket and other transfer characteristics vary by speed. */ +#define ep_desc(g,hs,fs) (((g)->speed==USB_SPEED_HIGH)?(hs):(fs)) + +#else + +/* if there's no high speed support, maxpacket doesn't change. */ +#define ep_desc(g,hs,fs) fs + +#endif /* !CONFIG_USB_GADGET_DUALSPEED */ + +static char manufacturer [40]; +//static char serial [40]; +static char serial [] = "Ser 00 em"; + +/* static strings, in UTF-8 */ +static struct usb_string strings [] = { + { STRING_MANUFACTURER, manufacturer, }, + { STRING_PRODUCT, longname, }, + { STRING_SERIAL, serial, }, + { STRING_LOOPBACK, loopback, }, + { STRING_SOURCE_SINK, source_sink, }, + { } /* end of list */ +}; + +static struct usb_gadget_strings stringtab = { + .language = 0x0409, /* en-us */ + .strings = strings, +}; + +/* + * config descriptors are also handcrafted. these must agree with code + * that sets configurations, and with code managing interfaces and their + * altsettings. other complexity may come from: + * + * - high speed support, including "other speed config" rules + * - multiple configurations + * - interfaces with alternate settings + * - embedded class or vendor-specific descriptors + * + * this handles high speed, and has a second config that could as easily + * have been an alternate interface setting (on most hardware). + * + * NOTE: to demonstrate (and test) more USB capabilities, this driver + * should include an altsetting to test interrupt transfers, including + * high bandwidth modes at high speed. (Maybe work like Intel's test + * device?) + */ +static int +config_buf (struct usb_gadget *gadget, u8 *buf, u8 type, unsigned index) +{ + int len; + const struct usb_descriptor_header **function; + + function = z_function; + len = usb_gadget_config_buf (&z_config, buf, USB_BUFSIZ, function); + if (len < 0) + return len; + ((struct usb_config_descriptor *) buf)->bDescriptorType = type; + return len; +} + +/*-------------------------------------------------------------------------*/ + +static struct usb_request * +alloc_ep_req (struct usb_ep *ep, unsigned length) +{ + struct usb_request *req; + + req = usb_ep_alloc_request (ep, GFP_ATOMIC); + if (req) { + req->length = length; + req->buf = usb_ep_alloc_buffer (ep, length, + &req->dma, GFP_ATOMIC); + if (!req->buf) { + usb_ep_free_request (ep, req); + req = NULL; + } + } + return req; +} + +static void free_ep_req (struct usb_ep *ep, struct usb_request *req) +{ + if (req->buf) + usb_ep_free_buffer (ep, req->buf, req->dma, req->length); + usb_ep_free_request (ep, req); +} + +/*-------------------------------------------------------------------------*/ + +/* optionally require specific source/sink data patterns */ + +static int +check_read_data ( + struct zero_dev *dev, + struct usb_ep *ep, + struct usb_request *req +) +{ + unsigned i; + u8 *buf = req->buf; + + for (i = 0; i < req->actual; i++, buf++) { + switch (pattern) { + /* all-zeroes has no synchronization issues */ + case 0: + if (*buf == 0) + continue; + break; + /* mod63 stays in sync with short-terminated transfers, + * or otherwise when host and gadget agree on how large + * each usb transfer request should be. resync is done + * with set_interface or set_config. + */ + case 1: + if (*buf == (u8)(i % 63)) + continue; + break; + } + ERROR (dev, "bad OUT byte, buf [%d] = %d\n", i, *buf); + usb_ep_set_halt (ep); + return -EINVAL; + } + return 0; +} + +/*-------------------------------------------------------------------------*/ + +static void zero_reset_config (struct zero_dev *dev) +{ + if (dev->config == 0) + return; + + DBG (dev, "reset config\n"); + + /* just disable endpoints, forcing completion of pending i/o. + * all our completion handlers free their requests in this case. + */ + if (dev->in_ep) { + usb_ep_disable (dev->in_ep); + dev->in_ep = NULL; + } + if (dev->out_ep) { + usb_ep_disable (dev->out_ep); + dev->out_ep = NULL; + } + dev->config = 0; + del_timer (&dev->resume); +} + +#define _write(f, buf, sz) (f->f_op->write(f, buf, sz, &f->f_pos)) + +static void +zero_isoc_complete (struct usb_ep *ep, struct usb_request *req) +{ + struct zero_dev *dev = ep->driver_data; + int status = req->status; + int i, j; + + switch (status) { + + case 0: /* normal completion? */ + //printk ("\nzero ---------------> isoc normal completion %d bytes\n", req->actual); + for (i=0, j=rbuf_start; iactual; i++) { + //printk ("%02x ", ((__u8*)req->buf)[i]); + rbuf[j] = ((__u8*)req->buf)[i]; + j++; + if (j >= RBUF_LEN) j=0; + } + rbuf_start = j; + //printk ("\n\n"); + + if (rbuf_len < RBUF_LEN) { + rbuf_len += req->actual; + if (rbuf_len > RBUF_LEN) { + rbuf_len = RBUF_LEN; + } + } + + break; + + /* this endpoint is normally active while we're configured */ + case -ECONNABORTED: /* hardware forced ep reset */ + case -ECONNRESET: /* request dequeued */ + case -ESHUTDOWN: /* disconnect from host */ + VDBG (dev, "%s gone (%d), %d/%d\n", ep->name, status, + req->actual, req->length); + if (ep == dev->out_ep) + check_read_data (dev, ep, req); + free_ep_req (ep, req); + return; + + case -EOVERFLOW: /* buffer overrun on read means that + * we didn't provide a big enough + * buffer. + */ + default: +#if 1 + DBG (dev, "%s complete --> %d, %d/%d\n", ep->name, + status, req->actual, req->length); +#endif + case -EREMOTEIO: /* short read */ + break; + } + + status = usb_ep_queue (ep, req, GFP_ATOMIC); + if (status) { + ERROR (dev, "kill %s: resubmit %d bytes --> %d\n", + ep->name, req->length, status); + usb_ep_set_halt (ep); + /* FIXME recover later ... somehow */ + } +} + +static struct usb_request * +zero_start_isoc_ep (struct usb_ep *ep, int gfp_flags) +{ + struct usb_request *req; + int status; + + req = alloc_ep_req (ep, 512); + if (!req) + return NULL; + + req->complete = zero_isoc_complete; + + status = usb_ep_queue (ep, req, gfp_flags); + if (status) { + struct zero_dev *dev = ep->driver_data; + + ERROR (dev, "start %s --> %d\n", ep->name, status); + free_ep_req (ep, req); + req = NULL; + } + + return req; +} + +/* change our operational config. this code must agree with the code + * that returns config descriptors, and altsetting code. + * + * it's also responsible for power management interactions. some + * configurations might not work with our current power sources. + * + * note that some device controller hardware will constrain what this + * code can do, perhaps by disallowing more than one configuration or + * by limiting configuration choices (like the pxa2xx). + */ +static int +zero_set_config (struct zero_dev *dev, unsigned number, int gfp_flags) +{ + int result = 0; + struct usb_gadget *gadget = dev->gadget; + const struct usb_endpoint_descriptor *d; + struct usb_ep *ep; + + if (number == dev->config) + return 0; + + zero_reset_config (dev); + + gadget_for_each_ep (ep, gadget) { + + if (strcmp (ep->name, "ep4") == 0) { + + d = (struct usb_endpoint_descripter *)&za_23; // isoc ep desc for audio i/f alt setting 6 + result = usb_ep_enable (ep, d); + + if (result == 0) { + ep->driver_data = dev; + dev->in_ep = ep; + + if (zero_start_isoc_ep (ep, gfp_flags) != 0) { + + dev->in_ep = ep; + continue; + } + + usb_ep_disable (ep); + result = -EIO; + } + } + + } + + dev->config = number; + return result; +} + +/*-------------------------------------------------------------------------*/ + +static void zero_setup_complete (struct usb_ep *ep, struct usb_request *req) +{ + if (req->status || req->actual != req->length) + DBG ((struct zero_dev *) ep->driver_data, + "setup complete --> %d, %d/%d\n", + req->status, req->actual, req->length); +} + +/* + * The setup() callback implements all the ep0 functionality that's + * not handled lower down, in hardware or the hardware driver (like + * device and endpoint feature flags, and their status). It's all + * housekeeping for the gadget function we're implementing. Most of + * the work is in config-specific setup. + */ +static int +zero_setup (struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl) +{ + struct zero_dev *dev = get_gadget_data (gadget); + struct usb_request *req = dev->req; + int value = -EOPNOTSUPP; + + /* usually this stores reply data in the pre-allocated ep0 buffer, + * but config change events will reconfigure hardware. + */ + req->zero = 0; + switch (ctrl->bRequest) { + + case USB_REQ_GET_DESCRIPTOR: + + switch (ctrl->wValue >> 8) { + + case USB_DT_DEVICE: + value = min (ctrl->wLength, (u16) sizeof device_desc); + memcpy (req->buf, &device_desc, value); + break; +#ifdef CONFIG_USB_GADGET_DUALSPEED + case USB_DT_DEVICE_QUALIFIER: + if (!gadget->is_dualspeed) + break; + value = min (ctrl->wLength, (u16) sizeof dev_qualifier); + memcpy (req->buf, &dev_qualifier, value); + break; + + case USB_DT_OTHER_SPEED_CONFIG: + if (!gadget->is_dualspeed) + break; + // FALLTHROUGH +#endif /* CONFIG_USB_GADGET_DUALSPEED */ + case USB_DT_CONFIG: + value = config_buf (gadget, req->buf, + ctrl->wValue >> 8, + ctrl->wValue & 0xff); + if (value >= 0) + value = min (ctrl->wLength, (u16) value); + break; + + case USB_DT_STRING: + /* wIndex == language code. + * this driver only handles one language, you can + * add string tables for other languages, using + * any UTF-8 characters + */ + value = usb_gadget_get_string (&stringtab, + ctrl->wValue & 0xff, req->buf); + if (value >= 0) { + value = min (ctrl->wLength, (u16) value); + } + break; + } + break; + + /* currently two configs, two speeds */ + case USB_REQ_SET_CONFIGURATION: + if (ctrl->bRequestType != 0) + goto unknown; + + spin_lock (&dev->lock); + value = zero_set_config (dev, ctrl->wValue, GFP_ATOMIC); + spin_unlock (&dev->lock); + break; + case USB_REQ_GET_CONFIGURATION: + if (ctrl->bRequestType != USB_DIR_IN) + goto unknown; + *(u8 *)req->buf = dev->config; + value = min (ctrl->wLength, (u16) 1); + break; + + /* until we add altsetting support, or other interfaces, + * only 0/0 are possible. pxa2xx only supports 0/0 (poorly) + * and already killed pending endpoint I/O. + */ + case USB_REQ_SET_INTERFACE: + + if (ctrl->bRequestType != USB_RECIP_INTERFACE) + goto unknown; + spin_lock (&dev->lock); + if (dev->config) { + u8 config = dev->config; + + /* resets interface configuration, forgets about + * previous transaction state (queued bufs, etc) + * and re-inits endpoint state (toggle etc) + * no response queued, just zero status == success. + * if we had more than one interface we couldn't + * use this "reset the config" shortcut. + */ + zero_reset_config (dev); + zero_set_config (dev, config, GFP_ATOMIC); + value = 0; + } + spin_unlock (&dev->lock); + break; + case USB_REQ_GET_INTERFACE: + if ((ctrl->bRequestType == 0x21) && (ctrl->wIndex == 0x02)) { + value = ctrl->wLength; + break; + } + else { + if (ctrl->bRequestType != (USB_DIR_IN|USB_RECIP_INTERFACE)) + goto unknown; + if (!dev->config) + break; + if (ctrl->wIndex != 0) { + value = -EDOM; + break; + } + *(u8 *)req->buf = 0; + value = min (ctrl->wLength, (u16) 1); + } + break; + + /* + * These are the same vendor-specific requests supported by + * Intel's USB 2.0 compliance test devices. We exceed that + * device spec by allowing multiple-packet requests. + */ + case 0x5b: /* control WRITE test -- fill the buffer */ + if (ctrl->bRequestType != (USB_DIR_OUT|USB_TYPE_VENDOR)) + goto unknown; + if (ctrl->wValue || ctrl->wIndex) + break; + /* just read that many bytes into the buffer */ + if (ctrl->wLength > USB_BUFSIZ) + break; + value = ctrl->wLength; + break; + case 0x5c: /* control READ test -- return the buffer */ + if (ctrl->bRequestType != (USB_DIR_IN|USB_TYPE_VENDOR)) + goto unknown; + if (ctrl->wValue || ctrl->wIndex) + break; + /* expect those bytes are still in the buffer; send back */ + if (ctrl->wLength > USB_BUFSIZ + || ctrl->wLength != req->length) + break; + value = ctrl->wLength; + break; + + case 0x01: // SET_CUR + case 0x02: + case 0x03: + case 0x04: + case 0x05: + value = ctrl->wLength; + break; + case 0x81: + switch (ctrl->wValue) { + case 0x0201: + case 0x0202: + ((u8*)req->buf)[0] = 0x00; + ((u8*)req->buf)[1] = 0xe3; + break; + case 0x0300: + case 0x0500: + ((u8*)req->buf)[0] = 0x00; + break; + } + //((u8*)req->buf)[0] = 0x81; + //((u8*)req->buf)[1] = 0x81; + value = ctrl->wLength; + break; + case 0x82: + switch (ctrl->wValue) { + case 0x0201: + case 0x0202: + ((u8*)req->buf)[0] = 0x00; + ((u8*)req->buf)[1] = 0xc3; + break; + case 0x0300: + case 0x0500: + ((u8*)req->buf)[0] = 0x00; + break; + } + //((u8*)req->buf)[0] = 0x82; + //((u8*)req->buf)[1] = 0x82; + value = ctrl->wLength; + break; + case 0x83: + switch (ctrl->wValue) { + case 0x0201: + case 0x0202: + ((u8*)req->buf)[0] = 0x00; + ((u8*)req->buf)[1] = 0x00; + break; + case 0x0300: + ((u8*)req->buf)[0] = 0x60; + break; + case 0x0500: + ((u8*)req->buf)[0] = 0x18; + break; + } + //((u8*)req->buf)[0] = 0x83; + //((u8*)req->buf)[1] = 0x83; + value = ctrl->wLength; + break; + case 0x84: + switch (ctrl->wValue) { + case 0x0201: + case 0x0202: + ((u8*)req->buf)[0] = 0x00; + ((u8*)req->buf)[1] = 0x01; + break; + case 0x0300: + case 0x0500: + ((u8*)req->buf)[0] = 0x08; + break; + } + //((u8*)req->buf)[0] = 0x84; + //((u8*)req->buf)[1] = 0x84; + value = ctrl->wLength; + break; + case 0x85: + ((u8*)req->buf)[0] = 0x85; + ((u8*)req->buf)[1] = 0x85; + value = ctrl->wLength; + break; + + + default: +unknown: + printk("unknown control req%02x.%02x v%04x i%04x l%d\n", + ctrl->bRequestType, ctrl->bRequest, + ctrl->wValue, ctrl->wIndex, ctrl->wLength); + } + + /* respond with data transfer before status phase? */ + if (value >= 0) { + req->length = value; + req->zero = value < ctrl->wLength + && (value % gadget->ep0->maxpacket) == 0; + value = usb_ep_queue (gadget->ep0, req, GFP_ATOMIC); + if (value < 0) { + DBG (dev, "ep_queue < 0 --> %d\n", value); + req->status = 0; + zero_setup_complete (gadget->ep0, req); + } + } + + /* device either stalls (value < 0) or reports success */ + return value; +} + +static void +zero_disconnect (struct usb_gadget *gadget) +{ + struct zero_dev *dev = get_gadget_data (gadget); + unsigned long flags; + + spin_lock_irqsave (&dev->lock, flags); + zero_reset_config (dev); + + /* a more significant application might have some non-usb + * activities to quiesce here, saving resources like power + * or pushing the notification up a network stack. + */ + spin_unlock_irqrestore (&dev->lock, flags); + + /* next we may get setup() calls to enumerate new connections; + * or an unbind() during shutdown (including removing module). + */ +} + +static void +zero_autoresume (unsigned long _dev) +{ + struct zero_dev *dev = (struct zero_dev *) _dev; + int status; + + /* normally the host would be woken up for something + * more significant than just a timer firing... + */ + if (dev->gadget->speed != USB_SPEED_UNKNOWN) { + status = usb_gadget_wakeup (dev->gadget); + DBG (dev, "wakeup --> %d\n", status); + } +} + +/*-------------------------------------------------------------------------*/ + +static void +zero_unbind (struct usb_gadget *gadget) +{ + struct zero_dev *dev = get_gadget_data (gadget); + + DBG (dev, "unbind\n"); + + /* we've already been disconnected ... no i/o is active */ + if (dev->req) + free_ep_req (gadget->ep0, dev->req); + del_timer_sync (&dev->resume); + kfree (dev); + set_gadget_data (gadget, NULL); +} + +static int +zero_bind (struct usb_gadget *gadget) +{ + struct zero_dev *dev; + //struct usb_ep *ep; + + printk("binding\n"); + /* + * DRIVER POLICY CHOICE: you may want to do this differently. + * One thing to avoid is reusing a bcdDevice revision code + * with different host-visible configurations or behavior + * restrictions -- using ep1in/ep2out vs ep1out/ep3in, etc + */ + //device_desc.bcdDevice = __constant_cpu_to_le16 (0x0201); + + + /* ok, we made sense of the hardware ... */ + dev = kmalloc (sizeof *dev, SLAB_KERNEL); + if (!dev) + return -ENOMEM; + memset (dev, 0, sizeof *dev); + spin_lock_init (&dev->lock); + dev->gadget = gadget; + set_gadget_data (gadget, dev); + + /* preallocate control response and buffer */ + dev->req = usb_ep_alloc_request (gadget->ep0, GFP_KERNEL); + if (!dev->req) + goto enomem; + dev->req->buf = usb_ep_alloc_buffer (gadget->ep0, USB_BUFSIZ, + &dev->req->dma, GFP_KERNEL); + if (!dev->req->buf) + goto enomem; + + dev->req->complete = zero_setup_complete; + + device_desc.bMaxPacketSize0 = gadget->ep0->maxpacket; + +#ifdef CONFIG_USB_GADGET_DUALSPEED + /* assume ep0 uses the same value for both speeds ... */ + dev_qualifier.bMaxPacketSize0 = device_desc.bMaxPacketSize0; + + /* and that all endpoints are dual-speed */ + //hs_source_desc.bEndpointAddress = fs_source_desc.bEndpointAddress; + //hs_sink_desc.bEndpointAddress = fs_sink_desc.bEndpointAddress; +#endif + + usb_gadget_set_selfpowered (gadget); + + init_timer (&dev->resume); + dev->resume.function = zero_autoresume; + dev->resume.data = (unsigned long) dev; + + gadget->ep0->driver_data = dev; + + INFO (dev, "%s, version: " DRIVER_VERSION "\n", longname); + INFO (dev, "using %s, OUT %s IN %s\n", gadget->name, + EP_OUT_NAME, EP_IN_NAME); + + snprintf (manufacturer, sizeof manufacturer, + UTS_SYSNAME " " UTS_RELEASE " with %s", + gadget->name); + + return 0; + +enomem: + zero_unbind (gadget); + return -ENOMEM; +} + +/*-------------------------------------------------------------------------*/ + +static void +zero_suspend (struct usb_gadget *gadget) +{ + struct zero_dev *dev = get_gadget_data (gadget); + + if (gadget->speed == USB_SPEED_UNKNOWN) + return; + + if (autoresume) { + mod_timer (&dev->resume, jiffies + (HZ * autoresume)); + DBG (dev, "suspend, wakeup in %d seconds\n", autoresume); + } else + DBG (dev, "suspend\n"); +} + +static void +zero_resume (struct usb_gadget *gadget) +{ + struct zero_dev *dev = get_gadget_data (gadget); + + DBG (dev, "resume\n"); + del_timer (&dev->resume); +} + + +/*-------------------------------------------------------------------------*/ + +static struct usb_gadget_driver zero_driver = { +#ifdef CONFIG_USB_GADGET_DUALSPEED + .speed = USB_SPEED_HIGH, +#else + .speed = USB_SPEED_FULL, +#endif + .function = (char *) longname, + .bind = zero_bind, + .unbind = zero_unbind, + + .setup = zero_setup, + .disconnect = zero_disconnect, + + .suspend = zero_suspend, + .resume = zero_resume, + + .driver = { + .name = (char *) shortname, + // .shutdown = ... + // .suspend = ... + // .resume = ... + }, +}; + +MODULE_AUTHOR ("David Brownell"); +MODULE_LICENSE ("Dual BSD/GPL"); + +static struct proc_dir_entry *pdir, *pfile; + +static int isoc_read_data (char *page, char **start, + off_t off, int count, + int *eof, void *data) +{ + int i; + static int c = 0; + static int done = 0; + static int s = 0; + +/* + printk ("\ncount: %d\n", count); + printk ("rbuf_start: %d\n", rbuf_start); + printk ("rbuf_len: %d\n", rbuf_len); + printk ("off: %d\n", off); + printk ("start: %p\n\n", *start); +*/ + if (done) { + c = 0; + done = 0; + *eof = 1; + return 0; + } + + if (c == 0) { + if (rbuf_len == RBUF_LEN) + s = rbuf_start; + else s = 0; + } + + for (i=0; i= rbuf_len) { + *eof = 1; + done = 1; + } + + + return i; +} + +static int __init init (void) +{ + + int retval = 0; + + pdir = proc_mkdir("isoc_test", NULL); + if(pdir == NULL) { + retval = -ENOMEM; + printk("Error creating dir\n"); + goto done; + } + pdir->owner = THIS_MODULE; + + pfile = create_proc_read_entry("isoc_data", + 0444, pdir, + isoc_read_data, + NULL); + if (pfile == NULL) { + retval = -ENOMEM; + printk("Error creating file\n"); + goto no_file; + } + pfile->owner = THIS_MODULE; + + return usb_gadget_register_driver (&zero_driver); + + no_file: + remove_proc_entry("isoc_data", NULL); + done: + return retval; +} +module_init (init); + +static void __exit cleanup (void) +{ + + usb_gadget_unregister_driver (&zero_driver); + + remove_proc_entry("isoc_data", pdir); + remove_proc_entry("isoc_test", NULL); +} +module_exit (cleanup); diff --git a/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_attr.c b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_attr.c new file mode 100644 index 0000000000..85435379d0 --- /dev/null +++ b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_attr.c @@ -0,0 +1,966 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.c $ + * $Revision: 1.2 $ + * $Date: 2008-11-21 05:39:15 $ + * $Change: 1064918 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and + * redistribute this Software in source and binary forms, with or without + * modification, provided that redistributions of source code must retain this + * notice. You may not view, use, disclose, copy or distribute this file or + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * ========================================================================== */ + +/** @file + * + * The diagnostic interface will provide access to the controller for + * bringing up the hardware and testing. The Linux driver attributes + * feature will be used to provide the Linux Diagnostic + * Interface. These attributes are accessed through sysfs. + */ + +/** @page "Linux Module Attributes" + * + * The Linux module attributes feature is used to provide the Linux + * Diagnostic Interface. These attributes are accessed through sysfs. + * The diagnostic interface will provide access to the controller for + * bringing up the hardware and testing. + + + The following table shows the attributes. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Description Access
mode Returns the current mode: 0 for device mode, 1 for host mode Read
hnpcapable Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register. + Read returns the current value. Read/Write
srpcapable Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register. + Read returns the current value. Read/Write
hnp Initiates the Host Negotiation Protocol. Read returns the status. Read/Write
srp Initiates the Session Request Protocol. Read returns the status. Read/Write
buspower Gets or sets the Power State of the bus (0 - Off or 1 - On) Read/Write
bussuspend Suspends the USB bus. Read/Write
busconnected Gets the connection status of the bus Read
gotgctl Gets or sets the Core Control Status Register. Read/Write
gusbcfg Gets or sets the Core USB Configuration Register Read/Write
grxfsiz Gets or sets the Receive FIFO Size Register Read/Write
gnptxfsiz Gets or sets the non-periodic Transmit Size Register Read/Write
gpvndctl Gets or sets the PHY Vendor Control Register Read/Write
ggpio Gets the value in the lower 16-bits of the General Purpose IO Register + or sets the upper 16 bits. Read/Write
guid Gets or sets the value of the User ID Register Read/Write
gsnpsid Gets the value of the Synopsys ID Regester Read
devspeed Gets or sets the device speed setting in the DCFG register Read/Write
enumspeed Gets the device enumeration Speed. Read
hptxfsiz Gets the value of the Host Periodic Transmit FIFO Read
hprt0 Gets or sets the value in the Host Port Control and Status Register Read/Write
regoffset Sets the register offset for the next Register Access Read/Write
regvalue Gets or sets the value of the register at the offset in the regoffset attribute. Read/Write
remote_wakeup On read, shows the status of Remote Wakeup. On write, initiates a remote + wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote + Wakeup signalling bit in the Device Control Register is set for 1 + milli-second. Read/Write
regdump Dumps the contents of core registers. Read
spramdump Dumps the contents of core registers. Read
hcddump Dumps the current HCD state. Read
hcd_frrem Shows the average value of the Frame Remaining + field in the Host Frame Number/Frame Remaining register when an SOF interrupt + occurs. This can be used to determine the average interrupt latency. Also + shows the average Frame Remaining value for start_transfer and the "a" and + "b" sample points. The "a" and "b" sample points may be used during debugging + bto determine how long it takes to execute a section of the HCD code. Read
rd_reg_test Displays the time required to read the GNPTXFSIZ register many times + (the output shows the number of times the register is read). + Read
wr_reg_test Displays the time required to write the GNPTXFSIZ register many times + (the output shows the number of times the register is written). + Read
+ + Example usage: + To get the current mode: + cat /sys/devices/lm0/mode + + To power down the USB: + echo 0 > /sys/devices/lm0/buspower + */ + +#include +#include +#include +#include +#include +#include +#include +#include /* permission constants */ +#include + +#include + +#include "linux/dwc_otg_plat.h" +#include "dwc_otg_attr.h" +#include "dwc_otg_driver.h" +#include "dwc_otg_pcd.h" +#include "dwc_otg_hcd.h" + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) +/* + * MACROs for defining sysfs attribute + */ +#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ +{ \ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \ + uint32_t val; \ + val = dwc_read_reg32 (_addr_); \ + val = (val & (_mask_)) >> _shift_; \ + return sprintf (buf, "%s = 0x%x\n", _string_, val); \ +} +#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \ + const char *buf, size_t count) \ +{ \ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \ + uint32_t set = simple_strtoul(buf, NULL, 16); \ + uint32_t clear = set; \ + clear = ((~clear) << _shift_) & _mask_; \ + set = (set << _shift_) & _mask_; \ + dev_dbg(_dev, "Storing Address=0x%08x Set=0x%08x Clear=0x%08x\n", (uint32_t)_addr_, set, clear); \ + dwc_modify_reg32(_addr_, clear, set); \ + return count; \ +} + +/* + * MACROs for defining sysfs attribute for 32-bit registers + */ +#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \ +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ +{ \ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \ + uint32_t val; \ + val = dwc_read_reg32 (_addr_); \ + return sprintf (buf, "%s = 0x%08x\n", _string_, val); \ +} +#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \ +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \ + const char *buf, size_t count) \ +{ \ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \ + uint32_t val = simple_strtoul(buf, NULL, 16); \ + dev_dbg(_dev, "Storing Address=0x%08x Val=0x%08x\n", (uint32_t)_addr_, val); \ + dwc_write_reg32(_addr_, val); \ + return count; \ +} + +#else + +/* + * MACROs for defining sysfs attribute + */ +#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ +static ssize_t _otg_attr_name_##_show (struct device *_dev, char *buf) \ +{ \ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\ + uint32_t val; \ + val = dwc_read_reg32 (_addr_); \ + val = (val & (_mask_)) >> _shift_; \ + return sprintf (buf, "%s = 0x%x\n", _string_, val); \ +} +#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ +static ssize_t _otg_attr_name_##_store (struct device *_dev, const char *buf, size_t count) \ +{ \ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\ + uint32_t set = simple_strtoul(buf, NULL, 16); \ + uint32_t clear = set; \ + clear = ((~clear) << _shift_) & _mask_; \ + set = (set << _shift_) & _mask_; \ + dev_dbg(_dev, "Storing Address=0x%08x Set=0x%08x Clear=0x%08x\n", (uint32_t)_addr_, set, clear); \ + dwc_modify_reg32(_addr_, clear, set); \ + return count; \ +} + +/* + * MACROs for defining sysfs attribute for 32-bit registers + */ +#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \ +static ssize_t _otg_attr_name_##_show (struct device *_dev, char *buf) \ +{ \ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\ + uint32_t val; \ + val = dwc_read_reg32 (_addr_); \ + return sprintf (buf, "%s = 0x%08x\n", _string_, val); \ +} +#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \ +static ssize_t _otg_attr_name_##_store (struct device *_dev, const char *buf, size_t count) \ +{ \ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\ + uint32_t val = simple_strtoul(buf, NULL, 16); \ + dev_dbg(_dev, "Storing Address=0x%08x Val=0x%08x\n", (uint32_t)_addr_, val); \ + dwc_write_reg32(_addr_, val); \ + return count; \ +} + +#endif + +#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ +DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ +DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ +DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store); + +#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ +DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ +DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL); + +#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \ +DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \ +DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \ +DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store); + +#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \ +DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \ +DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL); + + +/** @name Functions for Show/Store of Attributes */ +/**@{*/ + +/** + * Show the register offset of the Register Access. + */ +static ssize_t regoffset_show( struct device *_dev, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + struct device_attribute *attr, +#endif + char *buf) +{ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + return snprintf(buf, sizeof("0xFFFFFFFF\n")+1,"0x%08x\n", otg_dev->reg_offset); +} + +/** + * Set the register offset for the next Register Access Read/Write + */ +static ssize_t regoffset_store( struct device *_dev, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + struct device_attribute *attr, +#endif + const char *buf, + size_t count ) +{ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + + uint32_t offset = simple_strtoul(buf, NULL, 16); + //dev_dbg(_dev, "Offset=0x%08x\n", offset); + if (offset < 0x00040000 ) { + otg_dev->reg_offset = offset; + } + else { + dev_err( _dev, "invalid offset\n" ); + } + + return count; +} +DEVICE_ATTR(regoffset, S_IRUGO|S_IWUSR, (void *)regoffset_show, regoffset_store); + + +/** + * Show the value of the register at the offset in the reg_offset + * attribute. + */ +static ssize_t regvalue_show( struct device *_dev, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + struct device_attribute *attr, +#endif + char *buf) +{ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + + uint32_t val; + volatile uint32_t *addr; + + if (otg_dev->reg_offset != 0xFFFFFFFF && + 0 != otg_dev->base) { + /* Calculate the address */ + addr = (uint32_t*)(otg_dev->reg_offset + + (uint8_t*)otg_dev->base); + //dev_dbg(_dev, "@0x%08x\n", (unsigned)addr); + val = dwc_read_reg32( addr ); + return snprintf(buf, sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n")+1, + "Reg@0x%06x = 0x%08x\n", + otg_dev->reg_offset, val); + } + else { + dev_err(_dev, "Invalid offset (0x%0x)\n", + otg_dev->reg_offset); + return sprintf(buf, "invalid offset\n" ); + } +} + +/** + * Store the value in the register at the offset in the reg_offset + * attribute. + * + */ +static ssize_t regvalue_store( struct device *_dev, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + struct device_attribute *attr, +#endif + const char *buf, + size_t count ) +{ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + + volatile uint32_t * addr; + uint32_t val = simple_strtoul(buf, NULL, 16); + //dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val); + if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) { + /* Calculate the address */ + addr = (uint32_t*)(otg_dev->reg_offset + + (uint8_t*)otg_dev->base); + //dev_dbg(_dev, "@0x%08x\n", (unsigned)addr); + dwc_write_reg32( addr, val ); + } + else { + dev_err(_dev, "Invalid Register Offset (0x%08x)\n", + otg_dev->reg_offset); + } + return count; +} +DEVICE_ATTR(regvalue, S_IRUGO|S_IWUSR, regvalue_show, regvalue_store); + +/* + * Attributes + */ +DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<20),20,"Mode"); +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<9),9,"Mode"); +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<8),8,"Mode"); + +//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode"); +//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode"); +DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected,otg_dev->core_if->host_if->hprt0,0x01,0,"Bus Connected"); + +DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl,&(otg_dev->core_if->core_global_regs->gotgctl),"GOTGCTL"); +DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,&(otg_dev->core_if->core_global_regs->gusbcfg),"GUSBCFG"); +DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,&(otg_dev->core_if->core_global_regs->grxfsiz),"GRXFSIZ"); +DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,&(otg_dev->core_if->core_global_regs->gnptxfsiz),"GNPTXFSIZ"); +DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,&(otg_dev->core_if->core_global_regs->gpvndctl),"GPVNDCTL"); +DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,&(otg_dev->core_if->core_global_regs->ggpio),"GGPIO"); +DWC_OTG_DEVICE_ATTR_REG32_RW(guid,&(otg_dev->core_if->core_global_regs->guid),"GUID"); +DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,&(otg_dev->core_if->core_global_regs->gsnpsid),"GSNPSID"); +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dcfg),0x3,0,"Device Speed"); +DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dsts),0x6,1,"Device Enumeration Speed"); + +DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,&(otg_dev->core_if->core_global_regs->hptxfsiz),"HPTXFSIZ"); +DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0,otg_dev->core_if->host_if->hprt0,"HPRT0"); + + +/** + * @todo Add code to initiate the HNP. + */ +/** + * Show the HNP status bit + */ +static ssize_t hnp_show( struct device *_dev, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + struct device_attribute *attr, +#endif + char *buf) +{ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + + gotgctl_data_t val; + val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl)); + return sprintf (buf, "HstNegScs = 0x%x\n", val.b.hstnegscs); +} + +/** + * Set the HNP Request bit + */ +static ssize_t hnp_store( struct device *_dev, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + struct device_attribute *attr, +#endif + const char *buf, + size_t count ) +{ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + + uint32_t in = simple_strtoul(buf, NULL, 16); + uint32_t *addr = (uint32_t *)&(otg_dev->core_if->core_global_regs->gotgctl); + gotgctl_data_t mem; + mem.d32 = dwc_read_reg32(addr); + mem.b.hnpreq = in; + dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32); + dwc_write_reg32(addr, mem.d32); + return count; +} +DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store); + +/** + * @todo Add code to initiate the SRP. + */ +/** + * Show the SRP status bit + */ +static ssize_t srp_show( struct device *_dev, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + struct device_attribute *attr, +#endif + char *buf) +{ +#ifndef DWC_HOST_ONLY + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + + gotgctl_data_t val; + val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl)); + return sprintf (buf, "SesReqScs = 0x%x\n", val.b.sesreqscs); +#else + return sprintf(buf, "Host Only Mode!\n"); +#endif +} + + + +/** + * Set the SRP Request bit + */ +static ssize_t srp_store( struct device *_dev, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + struct device_attribute *attr, +#endif + const char *buf, + size_t count ) +{ +#ifndef DWC_HOST_ONLY + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + + dwc_otg_pcd_initiate_srp(otg_dev->pcd); +#endif + return count; +} +DEVICE_ATTR(srp, 0644, srp_show, srp_store); + +/** + * @todo Need to do more for power on/off? + */ +/** + * Show the Bus Power status + */ +static ssize_t buspower_show( struct device *_dev, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + struct device_attribute *attr, +#endif + char *buf) +{ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + + hprt0_data_t val; + val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0); + return sprintf (buf, "Bus Power = 0x%x\n", val.b.prtpwr); +} + + +/** + * Set the Bus Power status + */ +static ssize_t buspower_store( struct device *_dev, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + struct device_attribute *attr, +#endif + const char *buf, + size_t count ) +{ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + + uint32_t on = simple_strtoul(buf, NULL, 16); + uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0; + hprt0_data_t mem; + + mem.d32 = dwc_read_reg32(addr); + mem.b.prtpwr = on; + + //dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32); + dwc_write_reg32(addr, mem.d32); + + return count; +} +DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store); + +/** + * @todo Need to do more for suspend? + */ +/** + * Show the Bus Suspend status + */ +static ssize_t bussuspend_show( struct device *_dev, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + struct device_attribute *attr, +#endif + char *buf) +{ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + + hprt0_data_t val; + val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0); + return sprintf (buf, "Bus Suspend = 0x%x\n", val.b.prtsusp); +} + +/** + * Set the Bus Suspend status + */ +static ssize_t bussuspend_store( struct device *_dev, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + struct device_attribute *attr, +#endif + const char *buf, + size_t count ) +{ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + + uint32_t in = simple_strtoul(buf, NULL, 16); + uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0; + hprt0_data_t mem; + mem.d32 = dwc_read_reg32(addr); + mem.b.prtsusp = in; + dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32); + dwc_write_reg32(addr, mem.d32); + return count; +} +DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store); + +/** + * Show the status of Remote Wakeup. + */ +static ssize_t remote_wakeup_show( struct device *_dev, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + struct device_attribute *attr, +#endif + char *buf) +{ +#ifndef DWC_HOST_ONLY + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + + dctl_data_t val; + val.d32 = + dwc_read_reg32( &otg_dev->core_if->dev_if->dev_global_regs->dctl); + return sprintf( buf, "Remote Wakeup = %d Enabled = %d\n", + val.b.rmtwkupsig, otg_dev->pcd->remote_wakeup_enable); +#else + return sprintf(buf, "Host Only Mode!\n"); +#endif +} +/** + * Initiate a remote wakeup of the host. The Device control register + * Remote Wakeup Signal bit is written if the PCD Remote wakeup enable + * flag is set. + * + */ +static ssize_t remote_wakeup_store( struct device *_dev, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + struct device_attribute *attr, +#endif + const char *buf, + size_t count ) +{ +#ifndef DWC_HOST_ONLY + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + + uint32_t val = simple_strtoul(buf, NULL, 16); + if (val&1) { + dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1); + } + else { + dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0); + } +#endif + return count; +} +DEVICE_ATTR(remote_wakeup, S_IRUGO|S_IWUSR, remote_wakeup_show, + remote_wakeup_store); + +/** + * Dump global registers and either host or device registers (depending on the + * current mode of the core). + */ +static ssize_t regdump_show( struct device *_dev, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + struct device_attribute *attr, +#endif + char *buf) +{ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + + dwc_otg_dump_global_registers( otg_dev->core_if); + if (dwc_otg_is_host_mode(otg_dev->core_if)) { + dwc_otg_dump_host_registers( otg_dev->core_if); + } else { + dwc_otg_dump_dev_registers( otg_dev->core_if); + + } + return sprintf( buf, "Register Dump\n" ); +} + +DEVICE_ATTR(regdump, S_IRUGO|S_IWUSR, regdump_show, 0); + +/** + * Dump global registers and either host or device registers (depending on the + * current mode of the core). + */ +static ssize_t spramdump_show( struct device *_dev, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + struct device_attribute *attr, +#endif + char *buf) +{ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + + dwc_otg_dump_spram( otg_dev->core_if); + + return sprintf( buf, "SPRAM Dump\n" ); +} + +DEVICE_ATTR(spramdump, S_IRUGO|S_IWUSR, spramdump_show, 0); + +/** + * Dump the current hcd state. + */ +static ssize_t hcddump_show( struct device *_dev, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + struct device_attribute *attr, +#endif + char *buf) +{ +#ifndef DWC_DEVICE_ONLY + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + + dwc_otg_hcd_dump_state(otg_dev->hcd); +#endif + return sprintf( buf, "HCD Dump\n" ); +} + +DEVICE_ATTR(hcddump, S_IRUGO|S_IWUSR, hcddump_show, 0); + +/** + * Dump the average frame remaining at SOF. This can be used to + * determine average interrupt latency. Frame remaining is also shown for + * start transfer and two additional sample points. + */ +static ssize_t hcd_frrem_show( struct device *_dev, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + struct device_attribute *attr, +#endif + char *buf) +{ +#ifndef DWC_DEVICE_ONLY + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + + dwc_otg_hcd_dump_frrem(otg_dev->hcd); +#endif + return sprintf( buf, "HCD Dump Frame Remaining\n" ); +} + +DEVICE_ATTR(hcd_frrem, S_IRUGO|S_IWUSR, hcd_frrem_show, 0); + +/** + * Displays the time required to read the GNPTXFSIZ register many times (the + * output shows the number of times the register is read). + */ +#define RW_REG_COUNT 10000000 +#define MSEC_PER_JIFFIE 1000/HZ +static ssize_t rd_reg_test_show( struct device *_dev, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + struct device_attribute *attr, +#endif + char *buf) +{ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + + int i; + int time; + int start_jiffies; + + printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n", + HZ, MSEC_PER_JIFFIE, loops_per_jiffy); + start_jiffies = jiffies; + for (i = 0; i < RW_REG_COUNT; i++) { + dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz); + } + time = jiffies - start_jiffies; + return sprintf( buf, "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n", + RW_REG_COUNT, time * MSEC_PER_JIFFIE, time ); +} + +DEVICE_ATTR(rd_reg_test, S_IRUGO|S_IWUSR, rd_reg_test_show, 0); + +/** + * Displays the time required to write the GNPTXFSIZ register many times (the + * output shows the number of times the register is written). + */ +static ssize_t wr_reg_test_show( struct device *_dev, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + struct device_attribute *attr, +#endif + char *buf) +{ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + + uint32_t reg_val; + int i; + int time; + int start_jiffies; + + printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n", + HZ, MSEC_PER_JIFFIE, loops_per_jiffy); + reg_val = dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz); + start_jiffies = jiffies; + for (i = 0; i < RW_REG_COUNT; i++) { + dwc_write_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz, reg_val); + } + time = jiffies - start_jiffies; + return sprintf( buf, "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n", + RW_REG_COUNT, time * MSEC_PER_JIFFIE, time); +} + +DEVICE_ATTR(wr_reg_test, S_IRUGO|S_IWUSR, wr_reg_test_show, 0); +/**@}*/ + +/** + * Create the device files + */ +void dwc_otg_attr_create (struct device *dev) +{ + int error; + + error = device_create_file(dev, &dev_attr_regoffset); + error = device_create_file(dev, &dev_attr_regvalue); + error = device_create_file(dev, &dev_attr_mode); + error = device_create_file(dev, &dev_attr_hnpcapable); + error = device_create_file(dev, &dev_attr_srpcapable); + error = device_create_file(dev, &dev_attr_hnp); + error = device_create_file(dev, &dev_attr_srp); + error = device_create_file(dev, &dev_attr_buspower); + error = device_create_file(dev, &dev_attr_bussuspend); + error = device_create_file(dev, &dev_attr_busconnected); + error = device_create_file(dev, &dev_attr_gotgctl); + error = device_create_file(dev, &dev_attr_gusbcfg); + error = device_create_file(dev, &dev_attr_grxfsiz); + error = device_create_file(dev, &dev_attr_gnptxfsiz); + error = device_create_file(dev, &dev_attr_gpvndctl); + error = device_create_file(dev, &dev_attr_ggpio); + error = device_create_file(dev, &dev_attr_guid); + error = device_create_file(dev, &dev_attr_gsnpsid); + error = device_create_file(dev, &dev_attr_devspeed); + error = device_create_file(dev, &dev_attr_enumspeed); + error = device_create_file(dev, &dev_attr_hptxfsiz); + error = device_create_file(dev, &dev_attr_hprt0); + error = device_create_file(dev, &dev_attr_remote_wakeup); + error = device_create_file(dev, &dev_attr_regdump); + error = device_create_file(dev, &dev_attr_spramdump); + error = device_create_file(dev, &dev_attr_hcddump); + error = device_create_file(dev, &dev_attr_hcd_frrem); + error = device_create_file(dev, &dev_attr_rd_reg_test); + error = device_create_file(dev, &dev_attr_wr_reg_test); +} + +/** + * Remove the device files + */ +void dwc_otg_attr_remove (struct device *dev) +{ + device_remove_file(dev, &dev_attr_regoffset); + device_remove_file(dev, &dev_attr_regvalue); + device_remove_file(dev, &dev_attr_mode); + device_remove_file(dev, &dev_attr_hnpcapable); + device_remove_file(dev, &dev_attr_srpcapable); + device_remove_file(dev, &dev_attr_hnp); + device_remove_file(dev, &dev_attr_srp); + device_remove_file(dev, &dev_attr_buspower); + device_remove_file(dev, &dev_attr_bussuspend); + device_remove_file(dev, &dev_attr_busconnected); + device_remove_file(dev, &dev_attr_gotgctl); + device_remove_file(dev, &dev_attr_gusbcfg); + device_remove_file(dev, &dev_attr_grxfsiz); + device_remove_file(dev, &dev_attr_gnptxfsiz); + device_remove_file(dev, &dev_attr_gpvndctl); + device_remove_file(dev, &dev_attr_ggpio); + device_remove_file(dev, &dev_attr_guid); + device_remove_file(dev, &dev_attr_gsnpsid); + device_remove_file(dev, &dev_attr_devspeed); + device_remove_file(dev, &dev_attr_enumspeed); + device_remove_file(dev, &dev_attr_hptxfsiz); + device_remove_file(dev, &dev_attr_hprt0); + device_remove_file(dev, &dev_attr_remote_wakeup); + device_remove_file(dev, &dev_attr_regdump); + device_remove_file(dev, &dev_attr_spramdump); + device_remove_file(dev, &dev_attr_hcddump); + device_remove_file(dev, &dev_attr_hcd_frrem); + device_remove_file(dev, &dev_attr_rd_reg_test); + device_remove_file(dev, &dev_attr_wr_reg_test); +} diff --git a/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_attr.h b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_attr.h new file mode 100644 index 0000000000..0862b2711b --- /dev/null +++ b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_attr.h @@ -0,0 +1,67 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.h $ + * $Revision: 1.2 $ + * $Date: 2008-11-21 05:39:15 $ + * $Change: 477051 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and + * redistribute this Software in source and binary forms, with or without + * modification, provided that redistributions of source code must retain this + * notice. You may not view, use, disclose, copy or distribute this file or + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * ========================================================================== */ + +#if !defined(__DWC_OTG_ATTR_H__) +#define __DWC_OTG_ATTR_H__ + +/** @file + * This file contains the interface to the Linux device attributes. + */ +extern struct device_attribute dev_attr_regoffset; +extern struct device_attribute dev_attr_regvalue; + +extern struct device_attribute dev_attr_mode; +extern struct device_attribute dev_attr_hnpcapable; +extern struct device_attribute dev_attr_srpcapable; +extern struct device_attribute dev_attr_hnp; +extern struct device_attribute dev_attr_srp; +extern struct device_attribute dev_attr_buspower; +extern struct device_attribute dev_attr_bussuspend; +extern struct device_attribute dev_attr_busconnected; +extern struct device_attribute dev_attr_gotgctl; +extern struct device_attribute dev_attr_gusbcfg; +extern struct device_attribute dev_attr_grxfsiz; +extern struct device_attribute dev_attr_gnptxfsiz; +extern struct device_attribute dev_attr_gpvndctl; +extern struct device_attribute dev_attr_ggpio; +extern struct device_attribute dev_attr_guid; +extern struct device_attribute dev_attr_gsnpsid; +extern struct device_attribute dev_attr_devspeed; +extern struct device_attribute dev_attr_enumspeed; +extern struct device_attribute dev_attr_hptxfsiz; +extern struct device_attribute dev_attr_hprt0; + +void dwc_otg_attr_create (struct device *dev); +void dwc_otg_attr_remove (struct device *dev); + +#endif diff --git a/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_cil.c b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_cil.c new file mode 100644 index 0000000000..89aa83ec90 --- /dev/null +++ b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_cil.c @@ -0,0 +1,3692 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.c $ + * $Revision: 1.7 $ + * $Date: 2008-12-22 11:43:05 $ + * $Change: 1117667 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and + * redistribute this Software in source and binary forms, with or without + * modification, provided that redistributions of source code must retain this + * notice. You may not view, use, disclose, copy or distribute this file or + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * ========================================================================== */ + +/** @file + * + * The Core Interface Layer provides basic services for accessing and + * managing the DWC_otg hardware. These services are used by both the + * Host Controller Driver and the Peripheral Controller Driver. + * + * The CIL manages the memory map for the core so that the HCD and PCD + * don't have to do this separately. It also handles basic tasks like + * reading/writing the registers and data FIFOs in the controller. + * Some of the data access functions provide encapsulation of several + * operations required to perform a task, such as writing multiple + * registers to start a transfer. Finally, the CIL performs basic + * services that are not specific to either the host or device modes + * of operation. These services include management of the OTG Host + * Negotiation Protocol (HNP) and Session Request Protocol (SRP). A + * Diagnostic API is also provided to allow testing of the controller + * hardware. + * + * The Core Interface Layer has the following requirements: + * - Provides basic controller operations. + * - Minimal use of OS services. + * - The OS services used will be abstracted by using inline functions + * or macros. + * + */ +#include +#include +#ifdef DEBUG +#include +#endif + +#include "linux/dwc_otg_plat.h" +#include "dwc_otg_regs.h" +#include "dwc_otg_cil.h" + +/* Included only to access hc->qh for non-dword buffer handling + * TODO: account it + */ +#include "dwc_otg_hcd.h" + +/** + * This function is called to initialize the DWC_otg CSR data + * structures. The register addresses in the device and host + * structures are initialized from the base address supplied by the + * caller. The calling function must make the OS calls to get the + * base address of the DWC_otg controller registers. The core_params + * argument holds the parameters that specify how the core should be + * configured. + * + * @param[in] reg_base_addr Base address of DWC_otg core registers + * @param[in] core_params Pointer to the core configuration parameters + * + */ +dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *reg_base_addr, + dwc_otg_core_params_t *core_params) +{ + dwc_otg_core_if_t *core_if = 0; + dwc_otg_dev_if_t *dev_if = 0; + dwc_otg_host_if_t *host_if = 0; + uint8_t *reg_base = (uint8_t *)reg_base_addr; + int i = 0; + + DWC_DEBUGPL(DBG_CILV, "%s(%p,%p)\n", __func__, reg_base_addr, core_params); + + core_if = kmalloc(sizeof(dwc_otg_core_if_t), GFP_KERNEL); + + if (core_if == 0) { + DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_core_if_t failed\n"); + return 0; + } + + memset(core_if, 0, sizeof(dwc_otg_core_if_t)); + + core_if->core_params = core_params; + core_if->core_global_regs = (dwc_otg_core_global_regs_t *)reg_base; + + /* + * Allocate the Device Mode structures. + */ + dev_if = kmalloc(sizeof(dwc_otg_dev_if_t), GFP_KERNEL); + + if (dev_if == 0) { + DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n"); + kfree(core_if); + return 0; + } + + dev_if->dev_global_regs = + (dwc_otg_device_global_regs_t *)(reg_base + DWC_DEV_GLOBAL_REG_OFFSET); + + for (i=0; iin_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *) + (reg_base + DWC_DEV_IN_EP_REG_OFFSET + + (i * DWC_EP_REG_OFFSET)); + + dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *) + (reg_base + DWC_DEV_OUT_EP_REG_OFFSET + + (i * DWC_EP_REG_OFFSET)); + DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n", + i, &dev_if->in_ep_regs[i]->diepctl); + DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n", + i, &dev_if->out_ep_regs[i]->doepctl); + } + + dev_if->speed = 0; // unknown + + core_if->dev_if = dev_if; + + /* + * Allocate the Host Mode structures. + */ + host_if = kmalloc(sizeof(dwc_otg_host_if_t), GFP_KERNEL); + + if (host_if == 0) { + DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_host_if_t failed\n"); + kfree(dev_if); + kfree(core_if); + return 0; + } + + host_if->host_global_regs = (dwc_otg_host_global_regs_t *) + (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET); + + host_if->hprt0 = (uint32_t*)(reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET); + + for (i=0; ihc_regs[i] = (dwc_otg_hc_regs_t *) + (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET + + (i * DWC_OTG_CHAN_REGS_OFFSET)); + DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n", + i, &host_if->hc_regs[i]->hcchar); + } + + host_if->num_host_channels = MAX_EPS_CHANNELS; + core_if->host_if = host_if; + + for (i=0; idata_fifo[i] = + (uint32_t *)(reg_base + DWC_OTG_DATA_FIFO_OFFSET + + (i * DWC_OTG_DATA_FIFO_SIZE)); + DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08x\n", + i, (unsigned)core_if->data_fifo[i]); + } + + core_if->pcgcctl = (uint32_t*)(reg_base + DWC_OTG_PCGCCTL_OFFSET); + + /* + * Store the contents of the hardware configuration registers here for + * easy access later. + */ + core_if->hwcfg1.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg1); + core_if->hwcfg2.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg2); + core_if->hwcfg3.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg3); + core_if->hwcfg4.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg4); + + DWC_DEBUGPL(DBG_CILV,"hwcfg1=%08x\n",core_if->hwcfg1.d32); + DWC_DEBUGPL(DBG_CILV,"hwcfg2=%08x\n",core_if->hwcfg2.d32); + DWC_DEBUGPL(DBG_CILV,"hwcfg3=%08x\n",core_if->hwcfg3.d32); + DWC_DEBUGPL(DBG_CILV,"hwcfg4=%08x\n",core_if->hwcfg4.d32); + + core_if->hcfg.d32 = dwc_read_reg32(&core_if->host_if->host_global_regs->hcfg); + core_if->dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg); + + DWC_DEBUGPL(DBG_CILV,"hcfg=%08x\n",core_if->hcfg.d32); + DWC_DEBUGPL(DBG_CILV,"dcfg=%08x\n",core_if->dcfg.d32); + + DWC_DEBUGPL(DBG_CILV,"op_mode=%0x\n",core_if->hwcfg2.b.op_mode); + DWC_DEBUGPL(DBG_CILV,"arch=%0x\n",core_if->hwcfg2.b.architecture); + DWC_DEBUGPL(DBG_CILV,"num_dev_ep=%d\n",core_if->hwcfg2.b.num_dev_ep); + DWC_DEBUGPL(DBG_CILV,"num_host_chan=%d\n",core_if->hwcfg2.b.num_host_chan); + DWC_DEBUGPL(DBG_CILV,"nonperio_tx_q_depth=0x%0x\n",core_if->hwcfg2.b.nonperio_tx_q_depth); + DWC_DEBUGPL(DBG_CILV,"host_perio_tx_q_depth=0x%0x\n",core_if->hwcfg2.b.host_perio_tx_q_depth); + DWC_DEBUGPL(DBG_CILV,"dev_token_q_depth=0x%0x\n",core_if->hwcfg2.b.dev_token_q_depth); + + DWC_DEBUGPL(DBG_CILV,"Total FIFO SZ=%d\n", core_if->hwcfg3.b.dfifo_depth); + DWC_DEBUGPL(DBG_CILV,"xfer_size_cntr_width=%0x\n", core_if->hwcfg3.b.xfer_size_cntr_width); + + /* + * Set the SRP sucess bit for FS-I2c + */ + core_if->srp_success = 0; + core_if->srp_timer_started = 0; + + + /* + * Create new workqueue and init works + */ + core_if->wq_otg = create_singlethread_workqueue("dwc_otg"); + if(core_if->wq_otg == 0) { + DWC_DEBUGPL(DBG_CIL, "Creation of wq_otg failed\n"); + kfree(host_if); + kfree(dev_if); + kfree(core_if); + return 0 * HZ; + } + + + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) + + INIT_WORK(&core_if->w_conn_id, w_conn_id_status_change, core_if); + INIT_WORK(&core_if->w_wkp, w_wakeup_detected, core_if); + +#else + + INIT_WORK(&core_if->w_conn_id, w_conn_id_status_change); + INIT_DELAYED_WORK(&core_if->w_wkp, w_wakeup_detected); + +#endif + return core_if; +} + +/** + * This function frees the structures allocated by dwc_otg_cil_init(). + * + * @param[in] core_if The core interface pointer returned from + * dwc_otg_cil_init(). + * + */ +void dwc_otg_cil_remove(dwc_otg_core_if_t *core_if) +{ + /* Disable all interrupts */ + dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, 1, 0); + dwc_write_reg32(&core_if->core_global_regs->gintmsk, 0); + + if (core_if->wq_otg) { + destroy_workqueue(core_if->wq_otg); + } + if (core_if->dev_if) { + kfree(core_if->dev_if); + } + if (core_if->host_if) { + kfree(core_if->host_if); + } + kfree(core_if); +} + +/** + * This function enables the controller's Global Interrupt in the AHB Config + * register. + * + * @param[in] core_if Programming view of DWC_otg controller. + */ +void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t *core_if) +{ + gahbcfg_data_t ahbcfg = { .d32 = 0}; + ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ + dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32); +} + +/** + * This function disables the controller's Global Interrupt in the AHB Config + * register. + * + * @param[in] core_if Programming view of DWC_otg controller. + */ +void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t *core_if) +{ + gahbcfg_data_t ahbcfg = { .d32 = 0}; + ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ + dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0); +} + +/** + * This function initializes the commmon interrupts, used in both + * device and host modes. + * + * @param[in] core_if Programming view of the DWC_otg controller + * + */ +static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t *core_if) +{ + dwc_otg_core_global_regs_t *global_regs = + core_if->core_global_regs; + gintmsk_data_t intr_mask = { .d32 = 0}; + + /* Clear any pending OTG Interrupts */ + dwc_write_reg32(&global_regs->gotgint, 0xFFFFFFFF); + + /* Clear any pending interrupts */ + dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF); + + /* + * Enable the interrupts in the GINTMSK. + */ + intr_mask.b.modemismatch = 1; + intr_mask.b.otgintr = 1; + + if (!core_if->dma_enable) { + intr_mask.b.rxstsqlvl = 1; + } + + intr_mask.b.conidstschng = 1; + intr_mask.b.wkupintr = 1; + intr_mask.b.disconnect = 1; + intr_mask.b.usbsuspend = 1; + intr_mask.b.sessreqintr = 1; + dwc_write_reg32(&global_regs->gintmsk, intr_mask.d32); +} + +/** + * Initializes the FSLSPClkSel field of the HCFG register depending on the PHY + * type. + */ +static void init_fslspclksel(dwc_otg_core_if_t *core_if) +{ + uint32_t val; + hcfg_data_t hcfg; + + if (((core_if->hwcfg2.b.hs_phy_type == 2) && + (core_if->hwcfg2.b.fs_phy_type == 1) && + (core_if->core_params->ulpi_fs_ls)) || + (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) { + /* Full speed PHY */ + val = DWC_HCFG_48_MHZ; + } + else { + /* High speed PHY running at full speed or high speed */ + val = DWC_HCFG_30_60_MHZ; + } + + DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val); + hcfg.d32 = dwc_read_reg32(&core_if->host_if->host_global_regs->hcfg); + hcfg.b.fslspclksel = val; + dwc_write_reg32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32); +} + +/** + * Initializes the DevSpd field of the DCFG register depending on the PHY type + * and the enumeration speed of the device. + */ +static void init_devspd(dwc_otg_core_if_t *core_if) +{ + uint32_t val; + dcfg_data_t dcfg; + + if (((core_if->hwcfg2.b.hs_phy_type == 2) && + (core_if->hwcfg2.b.fs_phy_type == 1) && + (core_if->core_params->ulpi_fs_ls)) || + (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) { + /* Full speed PHY */ + val = 0x3; + } + else if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) { + /* High speed PHY running at full speed */ + val = 0x1; + } + else { + /* High speed PHY running at high speed */ + val = 0x0; + } + + DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val); + + dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg); + dcfg.b.devspd = val; + dwc_write_reg32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32); +} + +/** + * This function calculates the number of IN EPS + * using GHWCFG1 and GHWCFG2 registers values + * + * @param core_if Programming view of the DWC_otg controller + */ +static uint32_t calc_num_in_eps(dwc_otg_core_if_t *core_if) +{ + uint32_t num_in_eps = 0; + uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep; + uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 3; + uint32_t num_tx_fifos = core_if->hwcfg4.b.num_in_eps; + int i; + + + for(i = 0; i < num_eps; ++i) + { + if(!(hwcfg1 & 0x1)) + num_in_eps++; + + hwcfg1 >>= 2; + } + + if(core_if->hwcfg4.b.ded_fifo_en) { + num_in_eps = (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps; + } + + return num_in_eps; +} + + +/** + * This function calculates the number of OUT EPS + * using GHWCFG1 and GHWCFG2 registers values + * + * @param core_if Programming view of the DWC_otg controller + */ +static uint32_t calc_num_out_eps(dwc_otg_core_if_t *core_if) +{ + uint32_t num_out_eps = 0; + uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep; + uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 2; + int i; + + for(i = 0; i < num_eps; ++i) + { + if(!(hwcfg1 & 0x2)) + num_out_eps++; + + hwcfg1 >>= 2; + } + return num_out_eps; +} +/** + * This function initializes the DWC_otg controller registers and + * prepares the core for device mode or host mode operation. + * + * @param core_if Programming view of the DWC_otg controller + * + */ +void dwc_otg_core_init(dwc_otg_core_if_t *core_if) +{ + int i = 0; + dwc_otg_core_global_regs_t *global_regs = + core_if->core_global_regs; + dwc_otg_dev_if_t *dev_if = core_if->dev_if; + gahbcfg_data_t ahbcfg = { .d32 = 0 }; + gusbcfg_data_t usbcfg = { .d32 = 0 }; + gi2cctl_data_t i2cctl = { .d32 = 0 }; + + DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p)\n", core_if); + + /* Common Initialization */ + + usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); + +// usbcfg.b.tx_end_delay = 1; + /* Program the ULPI External VBUS bit if needed */ + usbcfg.b.ulpi_ext_vbus_drv = + (core_if->core_params->phy_ulpi_ext_vbus == DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0; + + /* Set external TS Dline pulsing */ + usbcfg.b.term_sel_dl_pulse = (core_if->core_params->ts_dline == 1) ? 1 : 0; + dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32); + + + /* Reset the Controller */ + dwc_otg_core_reset(core_if); + + /* Initialize parameters from Hardware configuration registers. */ + dev_if->num_in_eps = calc_num_in_eps(core_if); + dev_if->num_out_eps = calc_num_out_eps(core_if); + + + DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n", core_if->hwcfg4.b.num_dev_perio_in_ep); + + for (i=0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) + { + dev_if->perio_tx_fifo_size[i] = + dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16; + DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n", + i, dev_if->perio_tx_fifo_size[i]); + } + + for (i=0; i < core_if->hwcfg4.b.num_in_eps; i++) + { + dev_if->tx_fifo_size[i] = + dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16; + DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n", + i, dev_if->perio_tx_fifo_size[i]); + } + + core_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth; + core_if->rx_fifo_size = + dwc_read_reg32(&global_regs->grxfsiz); + core_if->nperio_tx_fifo_size = + dwc_read_reg32(&global_regs->gnptxfsiz) >> 16; + + DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", core_if->total_fifo_size); + DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", core_if->rx_fifo_size); + DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n", core_if->nperio_tx_fifo_size); + + /* This programming sequence needs to happen in FS mode before any other + * programming occurs */ + if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) && + (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) { + /* If FS mode with FS PHY */ + + /* core_init() is now called on every switch so only call the + * following for the first time through. */ + if (!core_if->phy_init_done) { + core_if->phy_init_done = 1; + DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n"); + usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); + usbcfg.b.physel = 1; + dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32); + + /* Reset after a PHY select */ + dwc_otg_core_reset(core_if); + } + + /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also + * do this on HNP Dev/Host mode switches (done in dev_init and + * host_init). */ + if (dwc_otg_is_host_mode(core_if)) { + init_fslspclksel(core_if); + } + else { + init_devspd(core_if); + } + + if (core_if->core_params->i2c_enable) { + DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n"); + /* Program GUSBCFG.OtgUtmifsSel to I2C */ + usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); + usbcfg.b.otgutmifssel = 1; + dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32); + + /* Program GI2CCTL.I2CEn */ + i2cctl.d32 = dwc_read_reg32(&global_regs->gi2cctl); + i2cctl.b.i2cdevaddr = 1; + i2cctl.b.i2cen = 0; + dwc_write_reg32 (&global_regs->gi2cctl, i2cctl.d32); + i2cctl.b.i2cen = 1; + dwc_write_reg32 (&global_regs->gi2cctl, i2cctl.d32); + } + + } /* endif speed == DWC_SPEED_PARAM_FULL */ + + else { + /* High speed PHY. */ + if (!core_if->phy_init_done) { + core_if->phy_init_done = 1; + /* HS PHY parameters. These parameters are preserved + * during soft reset so only program the first time. Do + * a soft reset immediately after setting phyif. */ + usbcfg.b.ulpi_utmi_sel = core_if->core_params->phy_type; + if (usbcfg.b.ulpi_utmi_sel == 1) { + /* ULPI interface */ + usbcfg.b.phyif = 0; + usbcfg.b.ddrsel = core_if->core_params->phy_ulpi_ddr; + } + else { + /* UTMI+ interface */ + if (core_if->core_params->phy_utmi_width == 16) { + usbcfg.b.phyif = 1; + } + else { + usbcfg.b.phyif = 0; + } + } + + dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); + + /* Reset after setting the PHY parameters */ + dwc_otg_core_reset(core_if); + } + } + + if ((core_if->hwcfg2.b.hs_phy_type == 2) && + (core_if->hwcfg2.b.fs_phy_type == 1) && + (core_if->core_params->ulpi_fs_ls)) { + DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n"); + usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); + usbcfg.b.ulpi_fsls = 1; + usbcfg.b.ulpi_clk_sus_m = 1; + dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); + } + else { + usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); + usbcfg.b.ulpi_fsls = 0; + usbcfg.b.ulpi_clk_sus_m = 0; + dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); + } + + /* Program the GAHBCFG Register.*/ + switch (core_if->hwcfg2.b.architecture) { + + case DWC_SLAVE_ONLY_ARCH: + DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n"); + ahbcfg.b.nptxfemplvl_txfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY; + ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY; + core_if->dma_enable = 0; + core_if->dma_desc_enable = 0; + break; + + case DWC_EXT_DMA_ARCH: + DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n"); + ahbcfg.b.hburstlen = core_if->core_params->dma_burst_size; + core_if->dma_enable = (core_if->core_params->dma_enable != 0); + core_if->dma_desc_enable = (core_if->core_params->dma_desc_enable != 0); + break; + + case DWC_INT_DMA_ARCH: + DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n"); + ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR; + core_if->dma_enable = (core_if->core_params->dma_enable != 0); + core_if->dma_desc_enable = (core_if->core_params->dma_desc_enable != 0); + break; + + } + ahbcfg.b.dmaenable = core_if->dma_enable; + dwc_write_reg32(&global_regs->gahbcfg, ahbcfg.d32); + + core_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en; + + core_if->pti_enh_enable = core_if->core_params->pti_enable != 0; + core_if->multiproc_int_enable = core_if->core_params->mpi_enable; + DWC_PRINT("Periodic Transfer Interrupt Enhancement - %s\n", ((core_if->pti_enh_enable) ? "enabled": "disabled")); + DWC_PRINT("Multiprocessor Interrupt Enhancement - %s\n", ((core_if->multiproc_int_enable) ? "enabled": "disabled")); + + /* + * Program the GUSBCFG register. + */ + usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); + + switch (core_if->hwcfg2.b.op_mode) { + case DWC_MODE_HNP_SRP_CAPABLE: + usbcfg.b.hnpcap = (core_if->core_params->otg_cap == + DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE); + usbcfg.b.srpcap = (core_if->core_params->otg_cap != + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); + break; + + case DWC_MODE_SRP_ONLY_CAPABLE: + usbcfg.b.hnpcap = 0; + usbcfg.b.srpcap = (core_if->core_params->otg_cap != + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); + break; + + case DWC_MODE_NO_HNP_SRP_CAPABLE: + usbcfg.b.hnpcap = 0; + usbcfg.b.srpcap = 0; + break; + + case DWC_MODE_SRP_CAPABLE_DEVICE: + usbcfg.b.hnpcap = 0; + usbcfg.b.srpcap = (core_if->core_params->otg_cap != + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); + break; + + case DWC_MODE_NO_SRP_CAPABLE_DEVICE: + usbcfg.b.hnpcap = 0; + usbcfg.b.srpcap = 0; + break; + + case DWC_MODE_SRP_CAPABLE_HOST: + usbcfg.b.hnpcap = 0; + usbcfg.b.srpcap = (core_if->core_params->otg_cap != + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); + break; + + case DWC_MODE_NO_SRP_CAPABLE_HOST: + usbcfg.b.hnpcap = 0; + usbcfg.b.srpcap = 0; + break; + } + + dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); + + /* Enable common interrupts */ + dwc_otg_enable_common_interrupts(core_if); + + /* Do device or host intialization based on mode during PCD + * and HCD initialization */ + if (dwc_otg_is_host_mode(core_if)) { + DWC_DEBUGPL(DBG_ANY, "Host Mode\n"); + core_if->op_state = A_HOST; + } + else { + DWC_DEBUGPL(DBG_ANY, "Device Mode\n"); + core_if->op_state = B_PERIPHERAL; +#ifdef DWC_DEVICE_ONLY + dwc_otg_core_dev_init(core_if); +#endif + } +} + + +/** + * This function enables the Device mode interrupts. + * + * @param core_if Programming view of DWC_otg controller + */ +void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *core_if) +{ + gintmsk_data_t intr_mask = { .d32 = 0}; + dwc_otg_core_global_regs_t *global_regs = + core_if->core_global_regs; + + DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__); + + /* Disable all interrupts. */ + dwc_write_reg32(&global_regs->gintmsk, 0); + + /* Clear any pending interrupts */ + dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF); + + /* Enable the common interrupts */ + dwc_otg_enable_common_interrupts(core_if); + + /* Enable interrupts */ + intr_mask.b.usbreset = 1; + intr_mask.b.enumdone = 1; + + if(!core_if->multiproc_int_enable) { + intr_mask.b.inepintr = 1; + intr_mask.b.outepintr = 1; + } + + intr_mask.b.erlysuspend = 1; + + if(core_if->en_multiple_tx_fifo == 0) { + intr_mask.b.epmismatch = 1; + } + + +#ifdef DWC_EN_ISOC + if(core_if->dma_enable) { + if(core_if->dma_desc_enable == 0) { + if(core_if->pti_enh_enable) { + dctl_data_t dctl = { .d32 = 0 }; + dctl.b.ifrmnum = 1; + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32); + } else { + intr_mask.b.incomplisoin = 1; + intr_mask.b.incomplisoout = 1; + } + } + } else { + intr_mask.b.incomplisoin = 1; + intr_mask.b.incomplisoout = 1; + } +#endif // DWC_EN_ISOC + +/** @todo NGS: Should this be a module parameter? */ +#ifdef USE_PERIODIC_EP + intr_mask.b.isooutdrop = 1; + intr_mask.b.eopframe = 1; + intr_mask.b.incomplisoin = 1; + intr_mask.b.incomplisoout = 1; +#endif + + dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32); + + DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__, + dwc_read_reg32(&global_regs->gintmsk)); +} + +/** + * This function initializes the DWC_otg controller registers for + * device mode. + * + * @param core_if Programming view of DWC_otg controller + * + */ +void dwc_otg_core_dev_init(dwc_otg_core_if_t *core_if) +{ + int i; + dwc_otg_core_global_regs_t *global_regs = + core_if->core_global_regs; + dwc_otg_dev_if_t *dev_if = core_if->dev_if; + dwc_otg_core_params_t *params = core_if->core_params; + dcfg_data_t dcfg = { .d32 = 0}; + grstctl_t resetctl = { .d32 = 0 }; + uint32_t rx_fifo_size; + fifosize_data_t nptxfifosize; + fifosize_data_t txfifosize; + dthrctl_data_t dthrctl; + fifosize_data_t ptxfifosize; + + /* Restart the Phy Clock */ + dwc_write_reg32(core_if->pcgcctl, 0); + + /* Device configuration register */ + init_devspd(core_if); + dcfg.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dcfg); + dcfg.b.descdma = (core_if->dma_desc_enable) ? 1 : 0; + dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80; + + dwc_write_reg32(&dev_if->dev_global_regs->dcfg, dcfg.d32); + + /* Configure data FIFO sizes */ + if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) { + DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n", core_if->total_fifo_size); + DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n", params->dev_rx_fifo_size); + DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n", params->dev_nperio_tx_fifo_size); + + /* Rx FIFO */ + DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n", + dwc_read_reg32(&global_regs->grxfsiz)); + + rx_fifo_size = params->dev_rx_fifo_size; + dwc_write_reg32(&global_regs->grxfsiz, rx_fifo_size); + + DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n", + dwc_read_reg32(&global_regs->grxfsiz)); + + /** Set Periodic Tx FIFO Mask all bits 0 */ + core_if->p_tx_msk = 0; + + /** Set Tx FIFO Mask all bits 0 */ + core_if->tx_msk = 0; + + if(core_if->en_multiple_tx_fifo == 0) { + /* Non-periodic Tx FIFO */ + DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n", + dwc_read_reg32(&global_regs->gnptxfsiz)); + + nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size; + nptxfifosize.b.startaddr = params->dev_rx_fifo_size; + + dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32); + + DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n", + dwc_read_reg32(&global_regs->gnptxfsiz)); + + /**@todo NGS: Fix Periodic FIFO Sizing! */ + /* + * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15. + * Indexes of the FIFO size module parameters in the + * dev_perio_tx_fifo_size array and the FIFO size registers in + * the dptxfsiz array run from 0 to 14. + */ + /** @todo Finish debug of this */ + ptxfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth; + for (i=0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) + { + ptxfifosize.b.depth = params->dev_perio_tx_fifo_size[i]; + DWC_DEBUGPL(DBG_CIL, "initial dptxfsiz_dieptxf[%d]=%08x\n", i, + dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i])); + dwc_write_reg32(&global_regs->dptxfsiz_dieptxf[i], + ptxfifosize.d32); + DWC_DEBUGPL(DBG_CIL, "new dptxfsiz_dieptxf[%d]=%08x\n", i, + dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i])); + ptxfifosize.b.startaddr += ptxfifosize.b.depth; + } + } + else { + /* + * Tx FIFOs These FIFOs are numbered from 1 to 15. + * Indexes of the FIFO size module parameters in the + * dev_tx_fifo_size array and the FIFO size registers in + * the dptxfsiz_dieptxf array run from 0 to 14. + */ + + + /* Non-periodic Tx FIFO */ + DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n", + dwc_read_reg32(&global_regs->gnptxfsiz)); + + nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size; + nptxfifosize.b.startaddr = params->dev_rx_fifo_size; + + dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32); + + DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n", + dwc_read_reg32(&global_regs->gnptxfsiz)); + + txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth; + /* + Modify by kaiker ,for RT3052 device mode config + + In RT3052,Since the _core_if->hwcfg4.b.num_dev_perio_in_ep is + configed to 0 so these TX_FIF0 not config.IN EP will can't + more than 1 if not modify it. + + */ +#if 1 + for (i=1 ; i <= dev_if->num_in_eps; i++) +#else + for (i=1; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++) +#endif + { + + txfifosize.b.depth = params->dev_tx_fifo_size[i]; + + DWC_DEBUGPL(DBG_CIL, "initial dptxfsiz_dieptxf[%d]=%08x\n", i, + dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i])); + + dwc_write_reg32(&global_regs->dptxfsiz_dieptxf[i-1], + txfifosize.d32); + + DWC_DEBUGPL(DBG_CIL, "new dptxfsiz_dieptxf[%d]=%08x\n", i, + dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i-1])); + + txfifosize.b.startaddr += txfifosize.b.depth; + } + } + } + /* Flush the FIFOs */ + dwc_otg_flush_tx_fifo(core_if, 0x10); /* all Tx FIFOs */ + dwc_otg_flush_rx_fifo(core_if); + + /* Flush the Learning Queue. */ + resetctl.b.intknqflsh = 1; + dwc_write_reg32(&core_if->core_global_regs->grstctl, resetctl.d32); + + /* Clear all pending Device Interrupts */ + + if(core_if->multiproc_int_enable) { + } + + /** @todo - if the condition needed to be checked + * or in any case all pending interrutps should be cleared? + */ + if(core_if->multiproc_int_enable) { + for(i = 0; i < core_if->dev_if->num_in_eps; ++i) { + dwc_write_reg32(&dev_if->dev_global_regs->diepeachintmsk[i], 0); + } + + for(i = 0; i < core_if->dev_if->num_out_eps; ++i) { + dwc_write_reg32(&dev_if->dev_global_regs->doepeachintmsk[i], 0); + } + + dwc_write_reg32(&dev_if->dev_global_regs->deachint, 0xFFFFFFFF); + dwc_write_reg32(&dev_if->dev_global_regs->deachintmsk, 0); + } else { + dwc_write_reg32(&dev_if->dev_global_regs->diepmsk, 0); + dwc_write_reg32(&dev_if->dev_global_regs->doepmsk, 0); + dwc_write_reg32(&dev_if->dev_global_regs->daint, 0xFFFFFFFF); + dwc_write_reg32(&dev_if->dev_global_regs->daintmsk, 0); + } + + for (i=0; i <= dev_if->num_in_eps; i++) + { + depctl_data_t depctl; + depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl); + if (depctl.b.epena) { + depctl.d32 = 0; + depctl.b.epdis = 1; + depctl.b.snak = 1; + } + else { + depctl.d32 = 0; + } + + dwc_write_reg32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32); + + + dwc_write_reg32(&dev_if->in_ep_regs[i]->dieptsiz, 0); + dwc_write_reg32(&dev_if->in_ep_regs[i]->diepdma, 0); + dwc_write_reg32(&dev_if->in_ep_regs[i]->diepint, 0xFF); + } + + for (i=0; i <= dev_if->num_out_eps; i++) + { + depctl_data_t depctl; + depctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[i]->doepctl); + if (depctl.b.epena) { + depctl.d32 = 0; + depctl.b.epdis = 1; + depctl.b.snak = 1; + } + else { + depctl.d32 = 0; + } + + dwc_write_reg32(&dev_if->out_ep_regs[i]->doepctl, depctl.d32); + + dwc_write_reg32(&dev_if->out_ep_regs[i]->doeptsiz, 0); + dwc_write_reg32(&dev_if->out_ep_regs[i]->doepdma, 0); + dwc_write_reg32(&dev_if->out_ep_regs[i]->doepint, 0xFF); + } + + if(core_if->en_multiple_tx_fifo && core_if->dma_enable) { + dev_if->non_iso_tx_thr_en = params->thr_ctl & 0x1; + dev_if->iso_tx_thr_en = (params->thr_ctl >> 1) & 0x1; + dev_if->rx_thr_en = (params->thr_ctl >> 2) & 0x1; + + dev_if->rx_thr_length = params->rx_thr_length; + dev_if->tx_thr_length = params->tx_thr_length; + + dev_if->setup_desc_index = 0; + + dthrctl.d32 = 0; + dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en; + dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en; + dthrctl.b.tx_thr_len = dev_if->tx_thr_length; + dthrctl.b.rx_thr_en = dev_if->rx_thr_en; + dthrctl.b.rx_thr_len = dev_if->rx_thr_length; + + dwc_write_reg32(&dev_if->dev_global_regs->dtknqr3_dthrctl, dthrctl.d32); + + DWC_DEBUGPL(DBG_CIL, "Non ISO Tx Thr - %d\nISO Tx Thr - %d\nRx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n", + dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en, dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len, dthrctl.b.rx_thr_len); + + } + + dwc_otg_enable_device_interrupts(core_if); + + { + diepmsk_data_t msk = { .d32 = 0 }; + msk.b.txfifoundrn = 1; + if(core_if->multiproc_int_enable) { + dwc_modify_reg32(&dev_if->dev_global_regs->diepeachintmsk[0], msk.d32, msk.d32); + } else { + dwc_modify_reg32(&dev_if->dev_global_regs->diepmsk, msk.d32, msk.d32); + } + } + + + if(core_if->multiproc_int_enable) { + /* Set NAK on Babble */ + dctl_data_t dctl = { .d32 = 0}; + dctl.b.nakonbble = 1; + dwc_modify_reg32(&dev_if->dev_global_regs->dctl, 0, dctl.d32); + } +} + +/** + * This function enables the Host mode interrupts. + * + * @param core_if Programming view of DWC_otg controller + */ +void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *core_if) +{ + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; + gintmsk_data_t intr_mask = { .d32 = 0 }; + + DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__); + + /* Disable all interrupts. */ + dwc_write_reg32(&global_regs->gintmsk, 0); + + /* Clear any pending interrupts. */ + dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF); + + /* Enable the common interrupts */ + dwc_otg_enable_common_interrupts(core_if); + + /* + * Enable host mode interrupts without disturbing common + * interrupts. + */ + intr_mask.b.sofintr = 1; + intr_mask.b.portintr = 1; + intr_mask.b.hcintr = 1; + + dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32); +} + +/** + * This function disables the Host Mode interrupts. + * + * @param core_if Programming view of DWC_otg controller + */ +void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *core_if) +{ + dwc_otg_core_global_regs_t *global_regs = + core_if->core_global_regs; + gintmsk_data_t intr_mask = { .d32 = 0 }; + + DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__); + + /* + * Disable host mode interrupts without disturbing common + * interrupts. + */ + intr_mask.b.sofintr = 1; + intr_mask.b.portintr = 1; + intr_mask.b.hcintr = 1; + intr_mask.b.ptxfempty = 1; + intr_mask.b.nptxfempty = 1; + + dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0); +} + +/** + * This function initializes the DWC_otg controller registers for + * host mode. + * + * This function flushes the Tx and Rx FIFOs and it flushes any entries in the + * request queues. Host channels are reset to ensure that they are ready for + * performing transfers. + * + * @param core_if Programming view of DWC_otg controller + * + */ +void dwc_otg_core_host_init(dwc_otg_core_if_t *core_if) +{ + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; + dwc_otg_host_if_t *host_if = core_if->host_if; + dwc_otg_core_params_t *params = core_if->core_params; + hprt0_data_t hprt0 = { .d32 = 0 }; + fifosize_data_t nptxfifosize; + fifosize_data_t ptxfifosize; + int i; + hcchar_data_t hcchar; + hcfg_data_t hcfg; + dwc_otg_hc_regs_t *hc_regs; + int num_channels; + gotgctl_data_t gotgctl = { .d32 = 0 }; + + DWC_DEBUGPL(DBG_CILV,"%s(%p)\n", __func__, core_if); + + /* Restart the Phy Clock */ + dwc_write_reg32(core_if->pcgcctl, 0); + + /* Initialize Host Configuration Register */ + init_fslspclksel(core_if); + if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) + { + hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg); + hcfg.b.fslssupp = 1; + dwc_write_reg32(&host_if->host_global_regs->hcfg, hcfg.d32); + } + + /* Configure data FIFO sizes */ + if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) { + DWC_DEBUGPL(DBG_CIL,"Total FIFO Size=%d\n", core_if->total_fifo_size); + DWC_DEBUGPL(DBG_CIL,"Rx FIFO Size=%d\n", params->host_rx_fifo_size); + DWC_DEBUGPL(DBG_CIL,"NP Tx FIFO Size=%d\n", params->host_nperio_tx_fifo_size); + DWC_DEBUGPL(DBG_CIL,"P Tx FIFO Size=%d\n", params->host_perio_tx_fifo_size); + + /* Rx FIFO */ + DWC_DEBUGPL(DBG_CIL,"initial grxfsiz=%08x\n", dwc_read_reg32(&global_regs->grxfsiz)); + dwc_write_reg32(&global_regs->grxfsiz, params->host_rx_fifo_size); + DWC_DEBUGPL(DBG_CIL,"new grxfsiz=%08x\n", dwc_read_reg32(&global_regs->grxfsiz)); + + /* Non-periodic Tx FIFO */ + DWC_DEBUGPL(DBG_CIL,"initial gnptxfsiz=%08x\n", dwc_read_reg32(&global_regs->gnptxfsiz)); + nptxfifosize.b.depth = params->host_nperio_tx_fifo_size; + nptxfifosize.b.startaddr = params->host_rx_fifo_size; + dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32); + DWC_DEBUGPL(DBG_CIL,"new gnptxfsiz=%08x\n", dwc_read_reg32(&global_regs->gnptxfsiz)); + + /* Periodic Tx FIFO */ + DWC_DEBUGPL(DBG_CIL,"initial hptxfsiz=%08x\n", dwc_read_reg32(&global_regs->hptxfsiz)); + ptxfifosize.b.depth = params->host_perio_tx_fifo_size; + ptxfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth; + dwc_write_reg32(&global_regs->hptxfsiz, ptxfifosize.d32); + DWC_DEBUGPL(DBG_CIL,"new hptxfsiz=%08x\n", dwc_read_reg32(&global_regs->hptxfsiz)); + } + + /* Clear Host Set HNP Enable in the OTG Control Register */ + gotgctl.b.hstsethnpen = 1; + dwc_modify_reg32(&global_regs->gotgctl, gotgctl.d32, 0); + + /* Make sure the FIFOs are flushed. */ + dwc_otg_flush_tx_fifo(core_if, 0x10 /* all Tx FIFOs */); + dwc_otg_flush_rx_fifo(core_if); + + /* Flush out any leftover queued requests. */ + num_channels = core_if->core_params->host_channels; + for (i = 0; i < num_channels; i++) + { + hc_regs = core_if->host_if->hc_regs[i]; + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + hcchar.b.chen = 0; + hcchar.b.chdis = 1; + hcchar.b.epdir = 0; + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); + } + + /* Halt all channels to put them into a known state. */ + for (i = 0; i < num_channels; i++) + { + int count = 0; + hc_regs = core_if->host_if->hc_regs[i]; + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + hcchar.b.chen = 1; + hcchar.b.chdis = 1; + hcchar.b.epdir = 0; + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); + DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d\n", __func__, i); + do { + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + if (++count > 1000) + { + DWC_ERROR("%s: Unable to clear halt on channel %d\n", + __func__, i); + break; + } + } + while (hcchar.b.chen); + } + + /* Turn on the vbus power. */ + DWC_PRINT("Init: Port Power? op_state=%d\n", core_if->op_state); + if (core_if->op_state == A_HOST) { + hprt0.d32 = dwc_otg_read_hprt0(core_if); + DWC_PRINT("Init: Power Port (%d)\n", hprt0.b.prtpwr); + if (hprt0.b.prtpwr == 0) { + hprt0.b.prtpwr = 1; + dwc_write_reg32(host_if->hprt0, hprt0.d32); + } + } + + dwc_otg_enable_host_interrupts(core_if); +} + +/** + * Prepares a host channel for transferring packets to/from a specific + * endpoint. The HCCHARn register is set up with the characteristics specified + * in _hc. Host channel interrupts that may need to be serviced while this + * transfer is in progress are enabled. + * + * @param core_if Programming view of DWC_otg controller + * @param hc Information needed to initialize the host channel + */ +void dwc_otg_hc_init(dwc_otg_core_if_t *core_if, dwc_hc_t *hc) +{ + uint32_t intr_enable; + hcintmsk_data_t hc_intr_mask; + gintmsk_data_t gintmsk = { .d32 = 0 }; + hcchar_data_t hcchar; + hcsplt_data_t hcsplt; + + uint8_t hc_num = hc->hc_num; + dwc_otg_host_if_t *host_if = core_if->host_if; + dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num]; + + /* Clear old interrupt conditions for this host channel. */ + hc_intr_mask.d32 = 0xFFFFFFFF; + hc_intr_mask.b.reserved = 0; + dwc_write_reg32(&hc_regs->hcint, hc_intr_mask.d32); + + /* Enable channel interrupts required for this transfer. */ + hc_intr_mask.d32 = 0; + hc_intr_mask.b.chhltd = 1; + if (core_if->dma_enable) { + hc_intr_mask.b.ahberr = 1; + if (hc->error_state && !hc->do_split && + hc->ep_type != DWC_OTG_EP_TYPE_ISOC) { + hc_intr_mask.b.ack = 1; + if (hc->ep_is_in) { + hc_intr_mask.b.datatglerr = 1; + if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) { + hc_intr_mask.b.nak = 1; + } + } + } + } + else { + switch (hc->ep_type) { + case DWC_OTG_EP_TYPE_CONTROL: + case DWC_OTG_EP_TYPE_BULK: + hc_intr_mask.b.xfercompl = 1; + hc_intr_mask.b.stall = 1; + hc_intr_mask.b.xacterr = 1; + hc_intr_mask.b.datatglerr = 1; + if (hc->ep_is_in) { + hc_intr_mask.b.bblerr = 1; + } + else { + hc_intr_mask.b.nak = 1; + hc_intr_mask.b.nyet = 1; + if (hc->do_ping) { + hc_intr_mask.b.ack = 1; + } + } + + if (hc->do_split) { + hc_intr_mask.b.nak = 1; + if (hc->complete_split) { + hc_intr_mask.b.nyet = 1; + } + else { + hc_intr_mask.b.ack = 1; + } + } + + if (hc->error_state) { + hc_intr_mask.b.ack = 1; + } + break; + case DWC_OTG_EP_TYPE_INTR: + hc_intr_mask.b.xfercompl = 1; + hc_intr_mask.b.nak = 1; + hc_intr_mask.b.stall = 1; + hc_intr_mask.b.xacterr = 1; + hc_intr_mask.b.datatglerr = 1; + hc_intr_mask.b.frmovrun = 1; + + if (hc->ep_is_in) { + hc_intr_mask.b.bblerr = 1; + } + if (hc->error_state) { + hc_intr_mask.b.ack = 1; + } + if (hc->do_split) { + if (hc->complete_split) { + hc_intr_mask.b.nyet = 1; + } + else { + hc_intr_mask.b.ack = 1; + } + } + break; + case DWC_OTG_EP_TYPE_ISOC: + hc_intr_mask.b.xfercompl = 1; + hc_intr_mask.b.frmovrun = 1; + hc_intr_mask.b.ack = 1; + + if (hc->ep_is_in) { + hc_intr_mask.b.xacterr = 1; + hc_intr_mask.b.bblerr = 1; + } + break; + } + } + dwc_write_reg32(&hc_regs->hcintmsk, hc_intr_mask.d32); + +// if(hc->ep_type == DWC_OTG_EP_TYPE_BULK && !hc->ep_is_in) +// hc->max_packet = 512; + /* Enable the top level host channel interrupt. */ + intr_enable = (1 << hc_num); + dwc_modify_reg32(&host_if->host_global_regs->haintmsk, 0, intr_enable); + + /* Make sure host channel interrupts are enabled. */ + gintmsk.b.hcintr = 1; + dwc_modify_reg32(&core_if->core_global_regs->gintmsk, 0, gintmsk.d32); + + /* + * Program the HCCHARn register with the endpoint characteristics for + * the current transfer. + */ + hcchar.d32 = 0; + hcchar.b.devaddr = hc->dev_addr; + hcchar.b.epnum = hc->ep_num; + hcchar.b.epdir = hc->ep_is_in; + hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW); + hcchar.b.eptype = hc->ep_type; + hcchar.b.mps = hc->max_packet; + + dwc_write_reg32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32); + + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); + DWC_DEBUGPL(DBG_HCDV, " Dev Addr: %d\n", hcchar.b.devaddr); + DWC_DEBUGPL(DBG_HCDV, " Ep Num: %d\n", hcchar.b.epnum); + DWC_DEBUGPL(DBG_HCDV, " Is In: %d\n", hcchar.b.epdir); + DWC_DEBUGPL(DBG_HCDV, " Is Low Speed: %d\n", hcchar.b.lspddev); + DWC_DEBUGPL(DBG_HCDV, " Ep Type: %d\n", hcchar.b.eptype); + DWC_DEBUGPL(DBG_HCDV, " Max Pkt: %d\n", hcchar.b.mps); + DWC_DEBUGPL(DBG_HCDV, " Multi Cnt: %d\n", hcchar.b.multicnt); + + /* + * Program the HCSPLIT register for SPLITs + */ + hcsplt.d32 = 0; + if (hc->do_split) { + DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n", hc->hc_num, + hc->complete_split ? "CSPLIT" : "SSPLIT"); + hcsplt.b.compsplt = hc->complete_split; + hcsplt.b.xactpos = hc->xact_pos; + hcsplt.b.hubaddr = hc->hub_addr; + hcsplt.b.prtaddr = hc->port_addr; + DWC_DEBUGPL(DBG_HCDV, " comp split %d\n", hc->complete_split); + DWC_DEBUGPL(DBG_HCDV, " xact pos %d\n", hc->xact_pos); + DWC_DEBUGPL(DBG_HCDV, " hub addr %d\n", hc->hub_addr); + DWC_DEBUGPL(DBG_HCDV, " port addr %d\n", hc->port_addr); + DWC_DEBUGPL(DBG_HCDV, " is_in %d\n", hc->ep_is_in); + DWC_DEBUGPL(DBG_HCDV, " Max Pkt: %d\n", hcchar.b.mps); + DWC_DEBUGPL(DBG_HCDV, " xferlen: %d\n", hc->xfer_len); + } + dwc_write_reg32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32); + +} + +/** + * Attempts to halt a host channel. This function should only be called in + * Slave mode or to abort a transfer in either Slave mode or DMA mode. Under + * normal circumstances in DMA mode, the controller halts the channel when the + * transfer is complete or a condition occurs that requires application + * intervention. + * + * In slave mode, checks for a free request queue entry, then sets the Channel + * Enable and Channel Disable bits of the Host Channel Characteristics + * register of the specified channel to intiate the halt. If there is no free + * request queue entry, sets only the Channel Disable bit of the HCCHARn + * register to flush requests for this channel. In the latter case, sets a + * flag to indicate that the host channel needs to be halted when a request + * queue slot is open. + * + * In DMA mode, always sets the Channel Enable and Channel Disable bits of the + * HCCHARn register. The controller ensures there is space in the request + * queue before submitting the halt request. + * + * Some time may elapse before the core flushes any posted requests for this + * host channel and halts. The Channel Halted interrupt handler completes the + * deactivation of the host channel. + * + * @param core_if Controller register interface. + * @param hc Host channel to halt. + * @param halt_status Reason for halting the channel. + */ +void dwc_otg_hc_halt(dwc_otg_core_if_t *core_if, + dwc_hc_t *hc, + dwc_otg_halt_status_e halt_status) +{ + gnptxsts_data_t nptxsts; + hptxsts_data_t hptxsts; + hcchar_data_t hcchar; + dwc_otg_hc_regs_t *hc_regs; + dwc_otg_core_global_regs_t *global_regs; + dwc_otg_host_global_regs_t *host_global_regs; + + hc_regs = core_if->host_if->hc_regs[hc->hc_num]; + global_regs = core_if->core_global_regs; + host_global_regs = core_if->host_if->host_global_regs; + + WARN_ON(halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS); + + if (halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE || + halt_status == DWC_OTG_HC_XFER_AHB_ERR) { + /* + * Disable all channel interrupts except Ch Halted. The QTD + * and QH state associated with this transfer has been cleared + * (in the case of URB_DEQUEUE), so the channel needs to be + * shut down carefully to prevent crashes. + */ + hcintmsk_data_t hcintmsk; + hcintmsk.d32 = 0; + hcintmsk.b.chhltd = 1; + dwc_write_reg32(&hc_regs->hcintmsk, hcintmsk.d32); + + /* + * Make sure no other interrupts besides halt are currently + * pending. Handling another interrupt could cause a crash due + * to the QTD and QH state. + */ + dwc_write_reg32(&hc_regs->hcint, ~hcintmsk.d32); + + /* + * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR + * even if the channel was already halted for some other + * reason. + */ + hc->halt_status = halt_status; + + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + if (hcchar.b.chen == 0) { + /* + * The channel is either already halted or it hasn't + * started yet. In DMA mode, the transfer may halt if + * it finishes normally or a condition occurs that + * requires driver intervention. Don't want to halt + * the channel again. In either Slave or DMA mode, + * it's possible that the transfer has been assigned + * to a channel, but not started yet when an URB is + * dequeued. Don't want to halt a channel that hasn't + * started yet. + */ + return; + } + } + + if (hc->halt_pending) { + /* + * A halt has already been issued for this channel. This might + * happen when a transfer is aborted by a higher level in + * the stack. + */ +#ifdef DEBUG + DWC_PRINT("*** %s: Channel %d, _hc->halt_pending already set ***\n", + __func__, hc->hc_num); + +/* dwc_otg_dump_global_registers(core_if); */ +/* dwc_otg_dump_host_registers(core_if); */ +#endif + return; + } + + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + hcchar.b.chen = 1; + hcchar.b.chdis = 1; + + if (!core_if->dma_enable) { + /* Check for space in the request queue to issue the halt. */ + if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL || + hc->ep_type == DWC_OTG_EP_TYPE_BULK) { + nptxsts.d32 = dwc_read_reg32(&global_regs->gnptxsts); + if (nptxsts.b.nptxqspcavail == 0) { + hcchar.b.chen = 0; + } + } + else { + hptxsts.d32 = dwc_read_reg32(&host_global_regs->hptxsts); + if ((hptxsts.b.ptxqspcavail == 0) || (core_if->queuing_high_bandwidth)) { + hcchar.b.chen = 0; + } + } + } + + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); + + hc->halt_status = halt_status; + + if (hcchar.b.chen) { + hc->halt_pending = 1; + hc->halt_on_queue = 0; + } + else { + hc->halt_on_queue = 1; + } + + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); + DWC_DEBUGPL(DBG_HCDV, " hcchar: 0x%08x\n", hcchar.d32); + DWC_DEBUGPL(DBG_HCDV, " halt_pending: %d\n", hc->halt_pending); + DWC_DEBUGPL(DBG_HCDV, " halt_on_queue: %d\n", hc->halt_on_queue); + DWC_DEBUGPL(DBG_HCDV, " halt_status: %d\n", hc->halt_status); + + return; +} + +/** + * Clears the transfer state for a host channel. This function is normally + * called after a transfer is done and the host channel is being released. + * + * @param core_if Programming view of DWC_otg controller. + * @param hc Identifies the host channel to clean up. + */ +void dwc_otg_hc_cleanup(dwc_otg_core_if_t *core_if, dwc_hc_t *hc) +{ + dwc_otg_hc_regs_t *hc_regs; + + hc->xfer_started = 0; + + /* + * Clear channel interrupt enables and any unhandled channel interrupt + * conditions. + */ + hc_regs = core_if->host_if->hc_regs[hc->hc_num]; + dwc_write_reg32(&hc_regs->hcintmsk, 0); + dwc_write_reg32(&hc_regs->hcint, 0xFFFFFFFF); + +#ifdef DEBUG + del_timer(&core_if->hc_xfer_timer[hc->hc_num]); + { + hcchar_data_t hcchar; + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + if (hcchar.b.chdis) { + DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n", + __func__, hc->hc_num, hcchar.d32); + } + } +#endif +} + +/** + * Sets the channel property that indicates in which frame a periodic transfer + * should occur. This is always set to the _next_ frame. This function has no + * effect on non-periodic transfers. + * + * @param core_if Programming view of DWC_otg controller. + * @param hc Identifies the host channel to set up and its properties. + * @param hcchar Current value of the HCCHAR register for the specified host + * channel. + */ +static inline void hc_set_even_odd_frame(dwc_otg_core_if_t *core_if, + dwc_hc_t *hc, + hcchar_data_t *hcchar) +{ + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { + hfnum_data_t hfnum; + hfnum.d32 = dwc_read_reg32(&core_if->host_if->host_global_regs->hfnum); + + /* 1 if _next_ frame is odd, 0 if it's even */ + hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1; +#ifdef DEBUG + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR && hc->do_split && !hc->complete_split) { + switch (hfnum.b.frnum & 0x7) { + case 7: + core_if->hfnum_7_samples++; + core_if->hfnum_7_frrem_accum += hfnum.b.frrem; + break; + case 0: + core_if->hfnum_0_samples++; + core_if->hfnum_0_frrem_accum += hfnum.b.frrem; + break; + default: + core_if->hfnum_other_samples++; + core_if->hfnum_other_frrem_accum += hfnum.b.frrem; + break; + } + } +#endif + } +} + +#ifdef DEBUG +static void hc_xfer_timeout(unsigned long ptr) +{ + hc_xfer_info_t *xfer_info = (hc_xfer_info_t *)ptr; + int hc_num = xfer_info->hc->hc_num; + DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num); + DWC_WARN(" start_hcchar_val 0x%08x\n", xfer_info->core_if->start_hcchar_val[hc_num]); +} +#endif + +/* + * This function does the setup for a data transfer for a host channel and + * starts the transfer. May be called in either Slave mode or DMA mode. In + * Slave mode, the caller must ensure that there is sufficient space in the + * request queue and Tx Data FIFO. + * + * For an OUT transfer in Slave mode, it loads a data packet into the + * appropriate FIFO. If necessary, additional data packets will be loaded in + * the Host ISR. + * + * For an IN transfer in Slave mode, a data packet is requested. The data + * packets are unloaded from the Rx FIFO in the Host ISR. If necessary, + * additional data packets are requested in the Host ISR. + * + * For a PING transfer in Slave mode, the Do Ping bit is set in the egards, + * + * Steven + * + * register along with a packet count of 1 and the channel is enabled. This + * causes a single PING transaction to occur. Other fields in HCTSIZ are + * simply set to 0 since no data transfer occurs in this case. + * + * For a PING transfer in DMA mode, the HCTSIZ register is initialized with + * all the information required to perform the subsequent data transfer. In + * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the + * controller performs the entire PING protocol, then starts the data + * transfer. + * + * @param core_if Programming view of DWC_otg controller. + * @param hc Information needed to initialize the host channel. The xfer_len + * value may be reduced to accommodate the max widths of the XferSize and + * PktCnt fields in the HCTSIZn register. The multi_count value may be changed + * to reflect the final xfer_len value. + */ +void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *core_if, dwc_hc_t *hc) +{ + hcchar_data_t hcchar; + hctsiz_data_t hctsiz; + uint16_t num_packets; + uint32_t max_hc_xfer_size = core_if->core_params->max_transfer_size; + uint16_t max_hc_pkt_count = core_if->core_params->max_packet_count; + dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num]; + + hctsiz.d32 = 0; + + if (hc->do_ping) { + if (!core_if->dma_enable) { + dwc_otg_hc_do_ping(core_if, hc); + hc->xfer_started = 1; + return; + } + else { + hctsiz.b.dopng = 1; + } + } + + if (hc->do_split) { + num_packets = 1; + + if (hc->complete_split && !hc->ep_is_in) { + /* For CSPLIT OUT Transfer, set the size to 0 so the + * core doesn't expect any data written to the FIFO */ + hc->xfer_len = 0; + } + else if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) { + hc->xfer_len = hc->max_packet; + } + else if (!hc->ep_is_in && (hc->xfer_len > 188)) { + hc->xfer_len = 188; + } + + hctsiz.b.xfersize = hc->xfer_len; + } + else { + /* + * Ensure that the transfer length and packet count will fit + * in the widths allocated for them in the HCTSIZn register. + */ + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { + /* + * Make sure the transfer size is no larger than one + * (micro)frame's worth of data. (A check was done + * when the periodic transfer was accepted to ensure + * that a (micro)frame's worth of data can be + * programmed into a channel.) + */ + uint32_t max_periodic_len = hc->multi_count * hc->max_packet; + if (hc->xfer_len > max_periodic_len) { + hc->xfer_len = max_periodic_len; + } + else { + } + + } + else if (hc->xfer_len > max_hc_xfer_size) { + /* Make sure that xfer_len is a multiple of max packet size. */ + hc->xfer_len = max_hc_xfer_size - hc->max_packet + 1; + } + + if (hc->xfer_len > 0) { + num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet; + if (num_packets > max_hc_pkt_count) { + num_packets = max_hc_pkt_count; + hc->xfer_len = num_packets * hc->max_packet; + } + } + else { + /* Need 1 packet for transfer length of 0. */ + num_packets = 1; + } + + if (hc->ep_is_in) { + /* Always program an integral # of max packets for IN transfers. */ + hc->xfer_len = num_packets * hc->max_packet; + } + + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { + /* + * Make sure that the multi_count field matches the + * actual transfer length. + */ + hc->multi_count = num_packets; + } + + if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { + /* Set up the initial PID for the transfer. */ + if (hc->speed == DWC_OTG_EP_SPEED_HIGH) { + if (hc->ep_is_in) { + if (hc->multi_count == 1) { + hc->data_pid_start = DWC_OTG_HC_PID_DATA0; + } + else if (hc->multi_count == 2) { + hc->data_pid_start = DWC_OTG_HC_PID_DATA1; + } + else { + hc->data_pid_start = DWC_OTG_HC_PID_DATA2; + } + } + else { + if (hc->multi_count == 1) { + hc->data_pid_start = DWC_OTG_HC_PID_DATA0; + } + else { + hc->data_pid_start = DWC_OTG_HC_PID_MDATA; + } + } + } + else { + hc->data_pid_start = DWC_OTG_HC_PID_DATA0; + } + } + + hctsiz.b.xfersize = hc->xfer_len; + } + + hc->start_pkt_count = num_packets; + hctsiz.b.pktcnt = num_packets; + hctsiz.b.pid = hc->data_pid_start; + dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); + + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); + DWC_DEBUGPL(DBG_HCDV, " Xfer Size: %d\n", hctsiz.b.xfersize); + DWC_DEBUGPL(DBG_HCDV, " Num Pkts: %d\n", hctsiz.b.pktcnt); + DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid); + + if (core_if->dma_enable) { +#if defined (CONFIG_DWC_OTG_HOST_ONLY) + if ((uint32_t)hc->xfer_buff & 0x3) { + /* non DWORD-aligned buffer case*/ + if(!hc->qh->dw_align_buf) { + hc->qh->dw_align_buf = + dma_alloc_coherent(NULL, + core_if->core_params->max_transfer_size, + &hc->qh->dw_align_buf_dma, + GFP_ATOMIC | GFP_DMA); + if (!hc->qh->dw_align_buf) { + + DWC_ERROR("%s: Failed to allocate memory to handle " + "non-dword aligned buffer case\n", __func__); + return; + } + + } + if (!hc->ep_is_in) { + memcpy(hc->qh->dw_align_buf, phys_to_virt((uint32_t)hc->xfer_buff), hc->xfer_len); + } + + dwc_write_reg32(&hc_regs->hcdma, hc->qh->dw_align_buf_dma); + } + else +#endif + dwc_write_reg32(&hc_regs->hcdma, (uint32_t)hc->xfer_buff); + } + + /* Start the split */ + if (hc->do_split) { + hcsplt_data_t hcsplt; + hcsplt.d32 = dwc_read_reg32 (&hc_regs->hcsplt); + hcsplt.b.spltena = 1; + dwc_write_reg32(&hc_regs->hcsplt, hcsplt.d32); + } + + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + hcchar.b.multicnt = hc->multi_count; + hc_set_even_odd_frame(core_if, hc, &hcchar); +#ifdef DEBUG + core_if->start_hcchar_val[hc->hc_num] = hcchar.d32; + if (hcchar.b.chdis) { + DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n", + __func__, hc->hc_num, hcchar.d32); + } +#endif + + /* Set host channel enable after all other setup is complete. */ + hcchar.b.chen = 1; + hcchar.b.chdis = 0; + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); + + hc->xfer_started = 1; + hc->requests++; + + if (!core_if->dma_enable && + !hc->ep_is_in && hc->xfer_len > 0) { + /* Load OUT packet into the appropriate Tx FIFO. */ + dwc_otg_hc_write_packet(core_if, hc); + } + +#ifdef DEBUG + /* Start a timer for this transfer. */ + core_if->hc_xfer_timer[hc->hc_num].function = hc_xfer_timeout; + core_if->hc_xfer_info[hc->hc_num].core_if = core_if; + core_if->hc_xfer_info[hc->hc_num].hc = hc; + core_if->hc_xfer_timer[hc->hc_num].data = (unsigned long)(&core_if->hc_xfer_info[hc->hc_num]); + core_if->hc_xfer_timer[hc->hc_num].expires = jiffies + (HZ*10); + add_timer(&core_if->hc_xfer_timer[hc->hc_num]); +#endif +} + +/** + * This function continues a data transfer that was started by previous call + * to dwc_otg_hc_start_transfer. The caller must ensure there is + * sufficient space in the request queue and Tx Data FIFO. This function + * should only be called in Slave mode. In DMA mode, the controller acts + * autonomously to complete transfers programmed to a host channel. + * + * For an OUT transfer, a new data packet is loaded into the appropriate FIFO + * if there is any data remaining to be queued. For an IN transfer, another + * data packet is always requested. For the SETUP phase of a control transfer, + * this function does nothing. + * + * @return 1 if a new request is queued, 0 if no more requests are required + * for this transfer. + */ +int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *core_if, dwc_hc_t *hc) +{ + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); + + if (hc->do_split) { + /* SPLITs always queue just once per channel */ + return 0; + } + else if (hc->data_pid_start == DWC_OTG_HC_PID_SETUP) { + /* SETUPs are queued only once since they can't be NAKed. */ + return 0; + } + else if (hc->ep_is_in) { + /* + * Always queue another request for other IN transfers. If + * back-to-back INs are issued and NAKs are received for both, + * the driver may still be processing the first NAK when the + * second NAK is received. When the interrupt handler clears + * the NAK interrupt for the first NAK, the second NAK will + * not be seen. So we can't depend on the NAK interrupt + * handler to requeue a NAKed request. Instead, IN requests + * are issued each time this function is called. When the + * transfer completes, the extra requests for the channel will + * be flushed. + */ + hcchar_data_t hcchar; + dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num]; + + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + hc_set_even_odd_frame(core_if, hc, &hcchar); + hcchar.b.chen = 1; + hcchar.b.chdis = 0; + DWC_DEBUGPL(DBG_HCDV, " IN xfer: hcchar = 0x%08x\n", hcchar.d32); + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); + hc->requests++; + return 1; + } + else { + /* OUT transfers. */ + if (hc->xfer_count < hc->xfer_len) { + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { + hcchar_data_t hcchar; + dwc_otg_hc_regs_t *hc_regs; + hc_regs = core_if->host_if->hc_regs[hc->hc_num]; + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + hc_set_even_odd_frame(core_if, hc, &hcchar); + } + + /* Load OUT packet into the appropriate Tx FIFO. */ + dwc_otg_hc_write_packet(core_if, hc); + hc->requests++; + return 1; + } + else { + return 0; + } + } +} + +/** + * Starts a PING transfer. This function should only be called in Slave mode. + * The Do Ping bit is set in the HCTSIZ register, then the channel is enabled. + */ +void dwc_otg_hc_do_ping(dwc_otg_core_if_t *core_if, dwc_hc_t *hc) +{ + hcchar_data_t hcchar; + hctsiz_data_t hctsiz; + dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num]; + + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); + + hctsiz.d32 = 0; + hctsiz.b.dopng = 1; + hctsiz.b.pktcnt = 1; + dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); + + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + hcchar.b.chen = 1; + hcchar.b.chdis = 0; + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); +} + +/* + * This function writes a packet into the Tx FIFO associated with the Host + * Channel. For a channel associated with a non-periodic EP, the non-periodic + * Tx FIFO is written. For a channel associated with a periodic EP, the + * periodic Tx FIFO is written. This function should only be called in Slave + * mode. + * + * Upon return the xfer_buff and xfer_count fields in _hc are incremented by + * then number of bytes written to the Tx FIFO. + */ +void dwc_otg_hc_write_packet(dwc_otg_core_if_t *core_if, dwc_hc_t *hc) +{ + uint32_t i; + uint32_t remaining_count; + uint32_t byte_count; + uint32_t dword_count; + + uint32_t *data_buff = (uint32_t *)(hc->xfer_buff); + uint32_t *data_fifo = core_if->data_fifo[hc->hc_num]; + + remaining_count = hc->xfer_len - hc->xfer_count; + if (remaining_count > hc->max_packet) { + byte_count = hc->max_packet; + } + else { + byte_count = remaining_count; + } + + dword_count = (byte_count + 3) / 4; + + if ((((unsigned long)data_buff) & 0x3) == 0) { + /* xfer_buff is DWORD aligned. */ + for (i = 0; i < dword_count; i++, data_buff++) + { + dwc_write_reg32(data_fifo, *data_buff); + } + } + else { + /* xfer_buff is not DWORD aligned. */ + for (i = 0; i < dword_count; i++, data_buff++) + { + dwc_write_reg32(data_fifo, get_unaligned(data_buff)); + } + } + + hc->xfer_count += byte_count; + hc->xfer_buff += byte_count; +} + +/** + * Gets the current USB frame number. This is the frame number from the last + * SOF packet. + */ +uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *core_if) +{ + dsts_data_t dsts; + dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); + + /* read current frame/microframe number from DSTS register */ + return dsts.b.soffn; +} + +/** + * This function reads a setup packet from the Rx FIFO into the destination + * buffer. This function is called from the Rx Status Queue Level (RxStsQLvl) + * Interrupt routine when a SETUP packet has been received in Slave mode. + * + * @param core_if Programming view of DWC_otg controller. + * @param dest Destination buffer for packet data. + */ +void dwc_otg_read_setup_packet(dwc_otg_core_if_t *core_if, uint32_t *dest) +{ + /* Get the 8 bytes of a setup transaction data */ + + /* Pop 2 DWORDS off the receive data FIFO into memory */ + dest[0] = dwc_read_reg32(core_if->data_fifo[0]); + dest[1] = dwc_read_reg32(core_if->data_fifo[0]); +} + + +/** + * This function enables EP0 OUT to receive SETUP packets and configures EP0 + * IN for transmitting packets. It is normally called when the + * "Enumeration Done" interrupt occurs. + * + * @param core_if Programming view of DWC_otg controller. + * @param ep The EP0 data. + */ +void dwc_otg_ep0_activate(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) +{ + dwc_otg_dev_if_t *dev_if = core_if->dev_if; + dsts_data_t dsts; + depctl_data_t diepctl; + depctl_data_t doepctl; + dctl_data_t dctl = { .d32 = 0 }; + + /* Read the Device Status and Endpoint 0 Control registers */ + dsts.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dsts); + diepctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl); + doepctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl); + + /* Set the MPS of the IN EP based on the enumeration speed */ + switch (dsts.b.enumspd) { + case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: + case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: + case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ: + diepctl.b.mps = DWC_DEP0CTL_MPS_64; + break; + case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ: + diepctl.b.mps = DWC_DEP0CTL_MPS_8; + break; + } + + dwc_write_reg32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32); + + /* Enable OUT EP for receive */ + doepctl.b.epena = 1; + dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32); + +#ifdef VERBOSE + DWC_DEBUGPL(DBG_PCDV,"doepctl0=%0x\n", + dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl)); + DWC_DEBUGPL(DBG_PCDV,"diepctl0=%0x\n", + dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl)); +#endif + dctl.b.cgnpinnak = 1; + + dwc_modify_reg32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); + DWC_DEBUGPL(DBG_PCDV,"dctl=%0x\n", + dwc_read_reg32(&dev_if->dev_global_regs->dctl)); +} + +/** + * This function activates an EP. The Device EP control register for + * the EP is configured as defined in the ep structure. Note: This + * function is not used for EP0. + * + * @param core_if Programming view of DWC_otg controller. + * @param ep The EP to activate. + */ +void dwc_otg_ep_activate(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) +{ + dwc_otg_dev_if_t *dev_if = core_if->dev_if; + depctl_data_t depctl; + volatile uint32_t *addr; + daint_data_t daintmsk = { .d32 = 0 }; + + DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, ep->num, + (ep->is_in?"IN":"OUT")); + + /* Read DEPCTLn register */ + if (ep->is_in == 1) { + addr = &dev_if->in_ep_regs[ep->num]->diepctl; + daintmsk.ep.in = 1<num; + } + else { + addr = &dev_if->out_ep_regs[ep->num]->doepctl; + daintmsk.ep.out = 1<num; + } + + /* If the EP is already active don't change the EP Control + * register. */ + depctl.d32 = dwc_read_reg32(addr); + if (!depctl.b.usbactep) { + depctl.b.mps = ep->maxpacket; + depctl.b.eptype = ep->type; + depctl.b.txfnum = ep->tx_fifo_num; + + if (ep->type == DWC_OTG_EP_TYPE_ISOC) { + depctl.b.setd0pid = 1; // ??? + } + else { + depctl.b.setd0pid = 1; + } + depctl.b.usbactep = 1; + + dwc_write_reg32(addr, depctl.d32); + DWC_DEBUGPL(DBG_PCDV,"DEPCTL=%08x\n", dwc_read_reg32(addr)); + } + + /* Enable the Interrupt for this EP */ + if(core_if->multiproc_int_enable) { + if (ep->is_in == 1) { + diepmsk_data_t diepmsk = { .d32 = 0}; + diepmsk.b.xfercompl = 1; + diepmsk.b.timeout = 1; + diepmsk.b.epdisabled = 1; + diepmsk.b.ahberr = 1; + diepmsk.b.intknepmis = 1; + diepmsk.b.txfifoundrn = 1; //????? + + + if(core_if->dma_desc_enable) { + diepmsk.b.bna = 1; + } +/* + if(core_if->dma_enable) { + doepmsk.b.nak = 1; + } +*/ + dwc_write_reg32(&dev_if->dev_global_regs->diepeachintmsk[ep->num], diepmsk.d32); + + } else { + doepmsk_data_t doepmsk = { .d32 = 0}; + doepmsk.b.xfercompl = 1; + doepmsk.b.ahberr = 1; + doepmsk.b.epdisabled = 1; + + + if(core_if->dma_desc_enable) { + doepmsk.b.bna = 1; + } +/* + doepmsk.b.babble = 1; + doepmsk.b.nyet = 1; + doepmsk.b.nak = 1; +*/ + dwc_write_reg32(&dev_if->dev_global_regs->doepeachintmsk[ep->num], doepmsk.d32); + } + dwc_modify_reg32(&dev_if->dev_global_regs->deachintmsk, + 0, daintmsk.d32); + } else { + dwc_modify_reg32(&dev_if->dev_global_regs->daintmsk, + 0, daintmsk.d32); + } + + DWC_DEBUGPL(DBG_PCDV,"DAINTMSK=%0x\n", + dwc_read_reg32(&dev_if->dev_global_regs->daintmsk)); + + ep->stall_clear_flag = 0; + return; +} + +/** + * This function deactivates an EP. This is done by clearing the USB Active + * EP bit in the Device EP control register. Note: This function is not used + * for EP0. EP0 cannot be deactivated. + * + * @param core_if Programming view of DWC_otg controller. + * @param ep The EP to deactivate. + */ +void dwc_otg_ep_deactivate(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) +{ + depctl_data_t depctl = { .d32 = 0 }; + volatile uint32_t *addr; + daint_data_t daintmsk = { .d32 = 0}; + + /* Read DEPCTLn register */ + if (ep->is_in == 1) { + addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl; + daintmsk.ep.in = 1<num; + } + else { + addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl; + daintmsk.ep.out = 1<num; + } + + depctl.b.usbactep = 0; + + if(core_if->dma_desc_enable) + depctl.b.epdis = 1; + + dwc_write_reg32(addr, depctl.d32); + + /* Disable the Interrupt for this EP */ + if(core_if->multiproc_int_enable) { + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->deachintmsk, + daintmsk.d32, 0); + + if (ep->is_in == 1) { + dwc_write_reg32(&core_if->dev_if->dev_global_regs->diepeachintmsk[ep->num], 0); + } else { + dwc_write_reg32(&core_if->dev_if->dev_global_regs->doepeachintmsk[ep->num], 0); + } + } else { + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->daintmsk, + daintmsk.d32, 0); + } +} + +/** + * This function does the setup for a data transfer for an EP and + * starts the transfer. For an IN transfer, the packets will be + * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, + * the packets are unloaded from the Rx FIFO in the ISR. the ISR. + * + * @param core_if Programming view of DWC_otg controller. + * @param ep The EP to start the transfer on. + */ +static void init_dma_desc_chain(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) +{ + dwc_otg_dma_desc_t* dma_desc; + uint32_t offset; + uint32_t xfer_est; + int i; + + ep->desc_cnt = ( ep->total_len / ep->maxxfer) + + ((ep->total_len % ep->maxxfer) ? 1 : 0); + if(!ep->desc_cnt) + ep->desc_cnt = 1; + + dma_desc = ep->desc_addr; + xfer_est = ep->total_len; + offset = 0; + for( i = 0; i < ep->desc_cnt; ++i) { + /** DMA Descriptor Setup */ + if(xfer_est > ep->maxxfer) { + dma_desc->status.b.bs = BS_HOST_BUSY; + dma_desc->status.b.l = 0; + dma_desc->status.b.ioc = 0; + dma_desc->status.b.sp = 0; + dma_desc->status.b.bytes = ep->maxxfer; + dma_desc->buf = ep->dma_addr + offset; + dma_desc->status.b.bs = BS_HOST_READY; + + xfer_est -= ep->maxxfer; + offset += ep->maxxfer; + } else { + dma_desc->status.b.bs = BS_HOST_BUSY; + dma_desc->status.b.l = 1; + dma_desc->status.b.ioc = 1; + if(ep->is_in) { + dma_desc->status.b.sp = (xfer_est % ep->maxpacket) ? + 1 : ((ep->sent_zlp) ? 1 : 0); + dma_desc->status.b.bytes = xfer_est; + } else { + dma_desc->status.b.bytes = xfer_est + ((4 - (xfer_est & 0x3)) & 0x3) ; + } + + dma_desc->buf = ep->dma_addr + offset; + dma_desc->status.b.bs = BS_HOST_READY; + } + dma_desc ++; + } +} + +/** + * This function does the setup for a data transfer for an EP and + * starts the transfer. For an IN transfer, the packets will be + * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, + * the packets are unloaded from the Rx FIFO in the ISR. the ISR. + * + * @param core_if Programming view of DWC_otg controller. + * @param ep The EP to start the transfer on. + */ + +void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) +{ + depctl_data_t depctl; + deptsiz_data_t deptsiz; + gintmsk_data_t intr_mask = { .d32 = 0}; + + DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__); + + DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d " + "xfer_buff=%p start_xfer_buff=%p\n", + ep->num, (ep->is_in?"IN":"OUT"), ep->xfer_len, + ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff); + + /* IN endpoint */ + if (ep->is_in == 1) { + dwc_otg_dev_in_ep_regs_t *in_regs = + core_if->dev_if->in_ep_regs[ep->num]; + + gnptxsts_data_t gtxstatus; + + gtxstatus.d32 = + dwc_read_reg32(&core_if->core_global_regs->gnptxsts); + + if(core_if->en_multiple_tx_fifo == 0 && gtxstatus.b.nptxqspcavail == 0) { +#ifdef DEBUG + DWC_PRINT("TX Queue Full (0x%0x)\n", gtxstatus.d32); +#endif + return; + } + + depctl.d32 = dwc_read_reg32(&(in_regs->diepctl)); + deptsiz.d32 = dwc_read_reg32(&(in_regs->dieptsiz)); + + ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ? + ep->maxxfer : (ep->total_len - ep->xfer_len); + + /* Zero Length Packet? */ + if ((ep->xfer_len - ep->xfer_count) == 0) { + deptsiz.b.xfersize = 0; + deptsiz.b.pktcnt = 1; + } + else { + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet + * exist ? 1 : 0) + */ + deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count; + deptsiz.b.pktcnt = + (ep->xfer_len - ep->xfer_count - 1 + ep->maxpacket) / + ep->maxpacket; + } + + + /* Write the DMA register */ + if (core_if->dma_enable) { + if (core_if->dma_desc_enable == 0) { + dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); + dwc_write_reg32 (&(in_regs->diepdma), + (uint32_t)ep->dma_addr); + } + else { + init_dma_desc_chain(core_if, ep); + /** DIEPDMAn Register write */ + dwc_write_reg32(&in_regs->diepdma, ep->dma_desc_addr); + } + } + else { + dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); + if(ep->type != DWC_OTG_EP_TYPE_ISOC) { + /** + * Enable the Non-Periodic Tx FIFO empty interrupt, + * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, + * the data will be written into the fifo by the ISR. + */ + if(core_if->en_multiple_tx_fifo == 0) { + intr_mask.b.nptxfempty = 1; + dwc_modify_reg32(&core_if->core_global_regs->gintmsk, + intr_mask.d32, intr_mask.d32); + } + else { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if(ep->xfer_len > 0) { + uint32_t fifoemptymsk = 0; + fifoemptymsk = 1 << ep->num; + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk, + 0, fifoemptymsk); + + } + } + } + } + + /* EP enable, IN data in FIFO */ + depctl.b.cnak = 1; + depctl.b.epena = 1; + dwc_write_reg32(&in_regs->diepctl, depctl.d32); + + depctl.d32 = dwc_read_reg32 (&core_if->dev_if->in_ep_regs[0]->diepctl); + depctl.b.nextep = ep->num; + dwc_write_reg32 (&core_if->dev_if->in_ep_regs[0]->diepctl, depctl.d32); + + } + else { + /* OUT endpoint */ + dwc_otg_dev_out_ep_regs_t *out_regs = + core_if->dev_if->out_ep_regs[ep->num]; + + depctl.d32 = dwc_read_reg32(&(out_regs->doepctl)); + deptsiz.d32 = dwc_read_reg32(&(out_regs->doeptsiz)); + + ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ? + ep->maxxfer : (ep->total_len - ep->xfer_len); + + /* Program the transfer size and packet count as follows: + * + * pktcnt = N + * xfersize = N * maxpacket + */ + if ((ep->xfer_len - ep->xfer_count) == 0) { + /* Zero Length Packet */ + deptsiz.b.xfersize = ep->maxpacket; + deptsiz.b.pktcnt = 1; + } + else { + deptsiz.b.pktcnt = + (ep->xfer_len - ep->xfer_count + (ep->maxpacket - 1)) / + ep->maxpacket; + ep->xfer_len = deptsiz.b.pktcnt * ep->maxpacket + ep->xfer_count; + deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count; + } + + DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n", + ep->num, + deptsiz.b.xfersize, deptsiz.b.pktcnt); + + if (core_if->dma_enable) { + if (!core_if->dma_desc_enable) { + dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32); + + dwc_write_reg32 (&(out_regs->doepdma), + (uint32_t)ep->dma_addr); + } + else { + init_dma_desc_chain(core_if, ep); + + /** DOEPDMAn Register write */ + dwc_write_reg32(&out_regs->doepdma, ep->dma_desc_addr); + } + } + else { + dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32); + } + + /* EP enable */ + depctl.b.cnak = 1; + depctl.b.epena = 1; + + dwc_write_reg32(&out_regs->doepctl, depctl.d32); + + DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n", + dwc_read_reg32(&out_regs->doepctl), + dwc_read_reg32(&out_regs->doeptsiz)); + DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n", + dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk), + dwc_read_reg32(&core_if->core_global_regs->gintmsk)); + } +} + +/** + * This function setup a zero length transfer in Buffer DMA and + * Slave modes for usb requests with zero field set + * + * @param core_if Programming view of DWC_otg controller. + * @param ep The EP to start the transfer on. + * + */ +void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) +{ + + depctl_data_t depctl; + deptsiz_data_t deptsiz; + gintmsk_data_t intr_mask = { .d32 = 0}; + + DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__); + + /* IN endpoint */ + if (ep->is_in == 1) { + dwc_otg_dev_in_ep_regs_t *in_regs = + core_if->dev_if->in_ep_regs[ep->num]; + + depctl.d32 = dwc_read_reg32(&(in_regs->diepctl)); + deptsiz.d32 = dwc_read_reg32(&(in_regs->dieptsiz)); + + deptsiz.b.xfersize = 0; + deptsiz.b.pktcnt = 1; + + + /* Write the DMA register */ + if (core_if->dma_enable) { + if (core_if->dma_desc_enable == 0) { + dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); + dwc_write_reg32 (&(in_regs->diepdma), + (uint32_t)ep->dma_addr); + } + } + else { + dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); + /** + * Enable the Non-Periodic Tx FIFO empty interrupt, + * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, + * the data will be written into the fifo by the ISR. + */ + if(core_if->en_multiple_tx_fifo == 0) { + intr_mask.b.nptxfempty = 1; + dwc_modify_reg32(&core_if->core_global_regs->gintmsk, + intr_mask.d32, intr_mask.d32); + } + else { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if(ep->xfer_len > 0) { + uint32_t fifoemptymsk = 0; + fifoemptymsk = 1 << ep->num; + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk, + 0, fifoemptymsk); + } + } + } + + /* EP enable, IN data in FIFO */ + depctl.b.cnak = 1; + depctl.b.epena = 1; + dwc_write_reg32(&in_regs->diepctl, depctl.d32); + + depctl.d32 = dwc_read_reg32 (&core_if->dev_if->in_ep_regs[0]->diepctl); + depctl.b.nextep = ep->num; + dwc_write_reg32 (&core_if->dev_if->in_ep_regs[0]->diepctl, depctl.d32); + + } + else { + /* OUT endpoint */ + dwc_otg_dev_out_ep_regs_t *out_regs = + core_if->dev_if->out_ep_regs[ep->num]; + + depctl.d32 = dwc_read_reg32(&(out_regs->doepctl)); + deptsiz.d32 = dwc_read_reg32(&(out_regs->doeptsiz)); + + /* Zero Length Packet */ + deptsiz.b.xfersize = ep->maxpacket; + deptsiz.b.pktcnt = 1; + + if (core_if->dma_enable) { + if (!core_if->dma_desc_enable) { + dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32); + + dwc_write_reg32 (&(out_regs->doepdma), + (uint32_t)ep->dma_addr); + } + } + else { + dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32); + } + + /* EP enable */ + depctl.b.cnak = 1; + depctl.b.epena = 1; + + dwc_write_reg32(&out_regs->doepctl, depctl.d32); + + } +} + +/** + * This function does the setup for a data transfer for EP0 and starts + * the transfer. For an IN transfer, the packets will be loaded into + * the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are + * unloaded from the Rx FIFO in the ISR. + * + * @param core_if Programming view of DWC_otg controller. + * @param ep The EP0 data. + */ +void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) +{ + depctl_data_t depctl; + deptsiz0_data_t deptsiz; + gintmsk_data_t intr_mask = { .d32 = 0}; + dwc_otg_dma_desc_t* dma_desc; + + DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d " + "xfer_buff=%p start_xfer_buff=%p \n", + ep->num, (ep->is_in?"IN":"OUT"), ep->xfer_len, + ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff); + + ep->total_len = ep->xfer_len; + + /* IN endpoint */ + if (ep->is_in == 1) { + dwc_otg_dev_in_ep_regs_t *in_regs = + core_if->dev_if->in_ep_regs[0]; + + gnptxsts_data_t gtxstatus; + + gtxstatus.d32 = + dwc_read_reg32(&core_if->core_global_regs->gnptxsts); + + if(core_if->en_multiple_tx_fifo == 0 && gtxstatus.b.nptxqspcavail == 0) { +#ifdef DEBUG + deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz); + DWC_DEBUGPL(DBG_PCD,"DIEPCTL0=%0x\n", + dwc_read_reg32(&in_regs->diepctl)); + DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n", + deptsiz.d32, + deptsiz.b.xfersize, deptsiz.b.pktcnt); + DWC_PRINT("TX Queue or FIFO Full (0x%0x)\n", + gtxstatus.d32); +#endif + return; + } + + + depctl.d32 = dwc_read_reg32(&in_regs->diepctl); + deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz); + + /* Zero Length Packet? */ + if (ep->xfer_len == 0) { + deptsiz.b.xfersize = 0; + deptsiz.b.pktcnt = 1; + } + else { + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet + * exist ? 1 : 0) + */ + if (ep->xfer_len > ep->maxpacket) { + ep->xfer_len = ep->maxpacket; + deptsiz.b.xfersize = ep->maxpacket; + } + else { + deptsiz.b.xfersize = ep->xfer_len; + } + deptsiz.b.pktcnt = 1; + + } + DWC_DEBUGPL(DBG_PCDV, "IN len=%d xfersize=%d pktcnt=%d [%08x]\n", + ep->xfer_len, + deptsiz.b.xfersize, deptsiz.b.pktcnt, deptsiz.d32); + + /* Write the DMA register */ + if (core_if->dma_enable) { + if(core_if->dma_desc_enable == 0) { + dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); + + dwc_write_reg32 (&(in_regs->diepdma), + (uint32_t)ep->dma_addr); + } + else { + dma_desc = core_if->dev_if->in_desc_addr; + + /** DMA Descriptor Setup */ + dma_desc->status.b.bs = BS_HOST_BUSY; + dma_desc->status.b.l = 1; + dma_desc->status.b.ioc = 1; + dma_desc->status.b.sp = (ep->xfer_len == ep->maxpacket) ? 0 : 1; + dma_desc->status.b.bytes = ep->xfer_len; + dma_desc->buf = ep->dma_addr; + dma_desc->status.b.bs = BS_HOST_READY; + + /** DIEPDMA0 Register write */ + dwc_write_reg32(&in_regs->diepdma, core_if->dev_if->dma_in_desc_addr); + } + } + else { + dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); + } + + /* EP enable, IN data in FIFO */ + depctl.b.cnak = 1; + depctl.b.epena = 1; + dwc_write_reg32(&in_regs->diepctl, depctl.d32); + + /** + * Enable the Non-Periodic Tx FIFO empty interrupt, the + * data will be written into the fifo by the ISR. + */ + if (!core_if->dma_enable) { + if(core_if->en_multiple_tx_fifo == 0) { + intr_mask.b.nptxfempty = 1; + dwc_modify_reg32(&core_if->core_global_regs->gintmsk, + intr_mask.d32, intr_mask.d32); + } + else { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if(ep->xfer_len > 0) { + uint32_t fifoemptymsk = 0; + fifoemptymsk |= 1 << ep->num; + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk, + 0, fifoemptymsk); + } + } + } + } + else { + /* OUT endpoint */ + dwc_otg_dev_out_ep_regs_t *out_regs = + core_if->dev_if->out_ep_regs[0]; + + depctl.d32 = dwc_read_reg32(&out_regs->doepctl); + deptsiz.d32 = dwc_read_reg32(&out_regs->doeptsiz); + + /* Program the transfer size and packet count as follows: + * xfersize = N * (maxpacket + 4 - (maxpacket % 4)) + * pktcnt = N */ + /* Zero Length Packet */ + deptsiz.b.xfersize = ep->maxpacket; + deptsiz.b.pktcnt = 1; + + DWC_DEBUGPL(DBG_PCDV, "len=%d xfersize=%d pktcnt=%d\n", + ep->xfer_len, + deptsiz.b.xfersize, deptsiz.b.pktcnt); + + if (core_if->dma_enable) { + if(!core_if->dma_desc_enable) { + dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32); + + dwc_write_reg32 (&(out_regs->doepdma), + (uint32_t)ep->dma_addr); + } + else { + dma_desc = core_if->dev_if->out_desc_addr; + + /** DMA Descriptor Setup */ + dma_desc->status.b.bs = BS_HOST_BUSY; + dma_desc->status.b.l = 1; + dma_desc->status.b.ioc = 1; + dma_desc->status.b.bytes = ep->maxpacket; + dma_desc->buf = ep->dma_addr; + dma_desc->status.b.bs = BS_HOST_READY; + + /** DOEPDMA0 Register write */ + dwc_write_reg32(&out_regs->doepdma, core_if->dev_if->dma_out_desc_addr); + } + } + else { + dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32); + } + + /* EP enable */ + depctl.b.cnak = 1; + depctl.b.epena = 1; + dwc_write_reg32 (&(out_regs->doepctl), depctl.d32); + } +} + +/** + * This function continues control IN transfers started by + * dwc_otg_ep0_start_transfer, when the transfer does not fit in a + * single packet. NOTE: The DIEPCTL0/DOEPCTL0 registers only have one + * bit for the packet count. + * + * @param core_if Programming view of DWC_otg controller. + * @param ep The EP0 data. + */ +void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) +{ + depctl_data_t depctl; + deptsiz0_data_t deptsiz; + gintmsk_data_t intr_mask = { .d32 = 0}; + dwc_otg_dma_desc_t* dma_desc; + + if (ep->is_in == 1) { + dwc_otg_dev_in_ep_regs_t *in_regs = + core_if->dev_if->in_ep_regs[0]; + gnptxsts_data_t tx_status = { .d32 = 0 }; + + tx_status.d32 = dwc_read_reg32(&core_if->core_global_regs->gnptxsts); + /** @todo Should there be check for room in the Tx + * Status Queue. If not remove the code above this comment. */ + + depctl.d32 = dwc_read_reg32(&in_regs->diepctl); + deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz); + + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet + * exist ? 1 : 0) + */ + + + if(core_if->dma_desc_enable == 0) { + deptsiz.b.xfersize = (ep->total_len - ep->xfer_count) > ep->maxpacket ? ep->maxpacket : + (ep->total_len - ep->xfer_count); + deptsiz.b.pktcnt = 1; + if(core_if->dma_enable == 0) { + ep->xfer_len += deptsiz.b.xfersize; + } else { + ep->xfer_len = deptsiz.b.xfersize; + } + dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); + } + else { + ep->xfer_len = (ep->total_len - ep->xfer_count) > ep->maxpacket ? ep->maxpacket : + (ep->total_len - ep->xfer_count); + + dma_desc = core_if->dev_if->in_desc_addr; + + /** DMA Descriptor Setup */ + dma_desc->status.b.bs = BS_HOST_BUSY; + dma_desc->status.b.l = 1; + dma_desc->status.b.ioc = 1; + dma_desc->status.b.sp = (ep->xfer_len == ep->maxpacket) ? 0 : 1; + dma_desc->status.b.bytes = ep->xfer_len; + dma_desc->buf = ep->dma_addr; + dma_desc->status.b.bs = BS_HOST_READY; + + /** DIEPDMA0 Register write */ + dwc_write_reg32(&in_regs->diepdma, core_if->dev_if->dma_in_desc_addr); + } + + + DWC_DEBUGPL(DBG_PCDV, "IN len=%d xfersize=%d pktcnt=%d [%08x]\n", + ep->xfer_len, + deptsiz.b.xfersize, deptsiz.b.pktcnt, deptsiz.d32); + + /* Write the DMA register */ + if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) { + if(core_if->dma_desc_enable == 0) + dwc_write_reg32 (&(in_regs->diepdma), (uint32_t)ep->dma_addr); + } + + /* EP enable, IN data in FIFO */ + depctl.b.cnak = 1; + depctl.b.epena = 1; + dwc_write_reg32(&in_regs->diepctl, depctl.d32); + + /** + * Enable the Non-Periodic Tx FIFO empty interrupt, the + * data will be written into the fifo by the ISR. + */ + if (!core_if->dma_enable) { + if(core_if->en_multiple_tx_fifo == 0) { + /* First clear it from GINTSTS */ + intr_mask.b.nptxfempty = 1; + dwc_modify_reg32(&core_if->core_global_regs->gintmsk, + intr_mask.d32, intr_mask.d32); + + } + else { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if(ep->xfer_len > 0) { + uint32_t fifoemptymsk = 0; + fifoemptymsk |= 1 << ep->num; + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk, + 0, fifoemptymsk); + } + } + } + } + else { + dwc_otg_dev_out_ep_regs_t *out_regs = + core_if->dev_if->out_ep_regs[0]; + + + depctl.d32 = dwc_read_reg32(&out_regs->doepctl); + deptsiz.d32 = dwc_read_reg32(&out_regs->doeptsiz); + + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet + * exist ? 1 : 0) + */ + deptsiz.b.xfersize = ep->maxpacket; + deptsiz.b.pktcnt = 1; + + + if(core_if->dma_desc_enable == 0) { + dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32); + } + else { + dma_desc = core_if->dev_if->out_desc_addr; + + /** DMA Descriptor Setup */ + dma_desc->status.b.bs = BS_HOST_BUSY; + dma_desc->status.b.l = 1; + dma_desc->status.b.ioc = 1; + dma_desc->status.b.bytes = ep->maxpacket; + dma_desc->buf = ep->dma_addr; + dma_desc->status.b.bs = BS_HOST_READY; + + /** DOEPDMA0 Register write */ + dwc_write_reg32(&out_regs->doepdma, core_if->dev_if->dma_out_desc_addr); + } + + + DWC_DEBUGPL(DBG_PCDV, "IN len=%d xfersize=%d pktcnt=%d [%08x]\n", + ep->xfer_len, + deptsiz.b.xfersize, deptsiz.b.pktcnt, deptsiz.d32); + + /* Write the DMA register */ + if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) { + if(core_if->dma_desc_enable == 0) + dwc_write_reg32 (&(out_regs->doepdma), (uint32_t)ep->dma_addr); + } + + /* EP enable, IN data in FIFO */ + depctl.b.cnak = 1; + depctl.b.epena = 1; + dwc_write_reg32(&out_regs->doepctl, depctl.d32); + + } +} + +#ifdef DEBUG +void dump_msg(const u8 *buf, unsigned int length) +{ + unsigned int start, num, i; + char line[52], *p; + + if (length >= 512) + return; + start = 0; + while (length > 0) { + num = min(length, 16u); + p = line; + for (i = 0; i < num; ++i) + { + if (i == 8) + *p++ = ' '; + sprintf(p, " %02x", buf[i]); + p += 3; + } + *p = 0; + DWC_PRINT("%6x: %s\n", start, line); + buf += num; + start += num; + length -= num; + } +} +#else +static inline void dump_msg(const u8 *buf, unsigned int length) +{ +} +#endif + +/** + * This function writes a packet into the Tx FIFO associated with the + * EP. For non-periodic EPs the non-periodic Tx FIFO is written. For + * periodic EPs the periodic Tx FIFO associated with the EP is written + * with all packets for the next micro-frame. + * + * @param core_if Programming view of DWC_otg controller. + * @param ep The EP to write packet for. + * @param dma Indicates if DMA is being used. + */ +void dwc_otg_ep_write_packet(dwc_otg_core_if_t *core_if, dwc_ep_t *ep, int dma) +{ + /** + * The buffer is padded to DWORD on a per packet basis in + * slave/dma mode if the MPS is not DWORD aligned. The last + * packet, if short, is also padded to a multiple of DWORD. + * + * ep->xfer_buff always starts DWORD aligned in memory and is a + * multiple of DWORD in length + * + * ep->xfer_len can be any number of bytes + * + * ep->xfer_count is a multiple of ep->maxpacket until the last + * packet + * + * FIFO access is DWORD */ + + uint32_t i; + uint32_t byte_count; + uint32_t dword_count; + uint32_t *fifo; + uint32_t *data_buff = (uint32_t *)ep->xfer_buff; + + DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, core_if, ep); + if (ep->xfer_count >= ep->xfer_len) { + DWC_WARN("%s() No data for EP%d!!!\n", __func__, ep->num); + return; + } + + /* Find the byte length of the packet either short packet or MPS */ + if ((ep->xfer_len - ep->xfer_count) < ep->maxpacket) { + byte_count = ep->xfer_len - ep->xfer_count; + } + else { + byte_count = ep->maxpacket; + } + + /* Find the DWORD length, padded by extra bytes as neccessary if MPS + * is not a multiple of DWORD */ + dword_count = (byte_count + 3) / 4; + +#ifdef VERBOSE + dump_msg(ep->xfer_buff, byte_count); +#endif + + /**@todo NGS Where are the Periodic Tx FIFO addresses + * intialized? What should this be? */ + + fifo = core_if->data_fifo[ep->num]; + + + DWC_DEBUGPL((DBG_PCDV|DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n", fifo, data_buff, *data_buff, byte_count); + + if (!dma) { + for (i=0; ixfer_count += byte_count; + ep->xfer_buff += byte_count; + ep->dma_addr += byte_count; +} + +/** + * Set the EP STALL. + * + * @param core_if Programming view of DWC_otg controller. + * @param ep The EP to set the stall on. + */ +void dwc_otg_ep_set_stall(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) +{ + depctl_data_t depctl; + volatile uint32_t *depctl_addr; + + DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num, + (ep->is_in?"IN":"OUT")); + + DWC_PRINT("%s ep%d-%s\n", __func__, ep->num, + (ep->is_in?"in":"out")); + + if (ep->is_in == 1) { + depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl); + depctl.d32 = dwc_read_reg32(depctl_addr); + + /* set the disable and stall bits */ + if (depctl.b.epena) { + depctl.b.epdis = 1; + } + depctl.b.stall = 1; + dwc_write_reg32(depctl_addr, depctl.d32); + } + else { + depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl); + depctl.d32 = dwc_read_reg32(depctl_addr); + + /* set the stall bit */ + depctl.b.stall = 1; + dwc_write_reg32(depctl_addr, depctl.d32); + } + + DWC_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",dwc_read_reg32(depctl_addr)); + + return; +} + +/** + * Clear the EP STALL. + * + * @param core_if Programming view of DWC_otg controller. + * @param ep The EP to clear stall from. + */ +void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) +{ + depctl_data_t depctl; + volatile uint32_t *depctl_addr; + + DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num, + (ep->is_in?"IN":"OUT")); + + if (ep->is_in == 1) { + depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl); + } + else { + depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl); + } + + depctl.d32 = dwc_read_reg32(depctl_addr); + + /* clear the stall bits */ + depctl.b.stall = 0; + + /* + * USB Spec 9.4.5: For endpoints using data toggle, regardless + * of whether an endpoint has the Halt feature set, a + * ClearFeature(ENDPOINT_HALT) request always results in the + * data toggle being reinitialized to DATA0. + */ + if (ep->type == DWC_OTG_EP_TYPE_INTR || + ep->type == DWC_OTG_EP_TYPE_BULK) { + depctl.b.setd0pid = 1; /* DATA0 */ + } + + dwc_write_reg32(depctl_addr, depctl.d32); + DWC_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",dwc_read_reg32(depctl_addr)); + return; +} + +/** + * This function reads a packet from the Rx FIFO into the destination + * buffer. To read SETUP data use dwc_otg_read_setup_packet. + * + * @param core_if Programming view of DWC_otg controller. + * @param dest Destination buffer for the packet. + * @param bytes Number of bytes to copy to the destination. + */ +void dwc_otg_read_packet(dwc_otg_core_if_t *core_if, + uint8_t *dest, + uint16_t bytes) +{ + int i; + int word_count = (bytes + 3) / 4; + + volatile uint32_t *fifo = core_if->data_fifo[0]; + uint32_t *data_buff = (uint32_t *)dest; + + /** + * @todo Account for the case where _dest is not dword aligned. This + * requires reading data from the FIFO into a uint32_t temp buffer, + * then moving it into the data buffer. + */ + + DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__, + core_if, dest, bytes); + + for (i=0; idev_if->dev_global_regs->dcfg; + DWC_PRINT("DCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->dev_if->dev_global_regs->dctl; + DWC_PRINT("DCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->dev_if->dev_global_regs->dsts; + DWC_PRINT("DSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->dev_if->dev_global_regs->diepmsk; + DWC_PRINT("DIEPMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->dev_if->dev_global_regs->doepmsk; + DWC_PRINT("DOEPMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->dev_if->dev_global_regs->daint; + DWC_PRINT("DAINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->dev_if->dev_global_regs->daintmsk; + DWC_PRINT("DAINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->dev_if->dev_global_regs->dtknqr1; + DWC_PRINT("DTKNQR1 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + if (core_if->hwcfg2.b.dev_token_q_depth > 6) { + addr=&core_if->dev_if->dev_global_regs->dtknqr2; + DWC_PRINT("DTKNQR2 @0x%08X : 0x%08X\n", + (uint32_t)addr,dwc_read_reg32(addr)); + } + + addr=&core_if->dev_if->dev_global_regs->dvbusdis; + DWC_PRINT("DVBUSID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + + addr=&core_if->dev_if->dev_global_regs->dvbuspulse; + DWC_PRINT("DVBUSPULSE @0x%08X : 0x%08X\n", + (uint32_t)addr,dwc_read_reg32(addr)); + + if (core_if->hwcfg2.b.dev_token_q_depth > 14) { + addr=&core_if->dev_if->dev_global_regs->dtknqr3_dthrctl; + DWC_PRINT("DTKNQR3_DTHRCTL @0x%08X : 0x%08X\n", + (uint32_t)addr, dwc_read_reg32(addr)); + } +/* + if (core_if->hwcfg2.b.dev_token_q_depth > 22) { + addr=&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk; + DWC_PRINT("DTKNQR4 @0x%08X : 0x%08X\n", + (uint32_t)addr, dwc_read_reg32(addr)); + } +*/ + addr=&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk; + DWC_PRINT("FIFOEMPMSK @0x%08X : 0x%08X\n", (uint32_t)addr, dwc_read_reg32(addr)); + + addr=&core_if->dev_if->dev_global_regs->deachint; + DWC_PRINT("DEACHINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->dev_if->dev_global_regs->deachintmsk; + DWC_PRINT("DEACHINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + + for (i=0; i<= core_if->dev_if->num_in_eps; i++) { + addr=&core_if->dev_if->dev_global_regs->diepeachintmsk[i]; + DWC_PRINT("DIEPEACHINTMSK[%d] @0x%08X : 0x%08X\n", i, (uint32_t)addr, dwc_read_reg32(addr)); + } + + + for (i=0; i<= core_if->dev_if->num_out_eps; i++) { + addr=&core_if->dev_if->dev_global_regs->doepeachintmsk[i]; + DWC_PRINT("DOEPEACHINTMSK[%d] @0x%08X : 0x%08X\n", i, (uint32_t)addr, dwc_read_reg32(addr)); + } + + for (i=0; i<= core_if->dev_if->num_in_eps; i++) { + DWC_PRINT("Device IN EP %d Registers\n", i); + addr=&core_if->dev_if->in_ep_regs[i]->diepctl; + DWC_PRINT("DIEPCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->dev_if->in_ep_regs[i]->diepint; + DWC_PRINT("DIEPINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->dev_if->in_ep_regs[i]->dieptsiz; + DWC_PRINT("DIETSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->dev_if->in_ep_regs[i]->diepdma; + DWC_PRINT("DIEPDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->dev_if->in_ep_regs[i]->dtxfsts; + DWC_PRINT("DTXFSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->dev_if->in_ep_regs[i]->diepdmab; + DWC_PRINT("DIEPDMAB @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + } + + + for (i=0; i<= core_if->dev_if->num_out_eps; i++) { + DWC_PRINT("Device OUT EP %d Registers\n", i); + addr=&core_if->dev_if->out_ep_regs[i]->doepctl; + DWC_PRINT("DOEPCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->dev_if->out_ep_regs[i]->doepfn; + DWC_PRINT("DOEPFN @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->dev_if->out_ep_regs[i]->doepint; + DWC_PRINT("DOEPINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->dev_if->out_ep_regs[i]->doeptsiz; + DWC_PRINT("DOETSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->dev_if->out_ep_regs[i]->doepdma; + DWC_PRINT("DOEPDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->dev_if->out_ep_regs[i]->doepdmab; + DWC_PRINT("DOEPDMAB @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + + } + + + + return; +} + +/** + * This functions reads the SPRAM and prints its content + * + * @param core_if Programming view of DWC_otg controller. + */ +void dwc_otg_dump_spram(dwc_otg_core_if_t *core_if) +{ + volatile uint8_t *addr, *start_addr, *end_addr; + + DWC_PRINT("SPRAM Data:\n"); + start_addr = (void*)core_if->core_global_regs; + DWC_PRINT("Base Address: 0x%8X\n", (uint32_t)start_addr); + start_addr += 0x00028000; + end_addr=(void*)core_if->core_global_regs; + end_addr += 0x000280e0; + + for(addr = start_addr; addr < end_addr; addr+=16) + { + DWC_PRINT("0x%8X:\t%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\n", (uint32_t)addr, + addr[0], + addr[1], + addr[2], + addr[3], + addr[4], + addr[5], + addr[6], + addr[7], + addr[8], + addr[9], + addr[10], + addr[11], + addr[12], + addr[13], + addr[14], + addr[15] + ); + } + + return; +} +/** + * This function reads the host registers and prints them + * + * @param core_if Programming view of DWC_otg controller. + */ +void dwc_otg_dump_host_registers(dwc_otg_core_if_t *core_if) +{ + int i; + volatile uint32_t *addr; + + DWC_PRINT("Host Global Registers\n"); + addr=&core_if->host_if->host_global_regs->hcfg; + DWC_PRINT("HCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->host_if->host_global_regs->hfir; + DWC_PRINT("HFIR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->host_if->host_global_regs->hfnum; + DWC_PRINT("HFNUM @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->host_if->host_global_regs->hptxsts; + DWC_PRINT("HPTXSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->host_if->host_global_regs->haint; + DWC_PRINT("HAINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->host_if->host_global_regs->haintmsk; + DWC_PRINT("HAINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=core_if->host_if->hprt0; + DWC_PRINT("HPRT0 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + + for (i=0; icore_params->host_channels; i++) + { + DWC_PRINT("Host Channel %d Specific Registers\n", i); + addr=&core_if->host_if->hc_regs[i]->hcchar; + DWC_PRINT("HCCHAR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->host_if->hc_regs[i]->hcsplt; + DWC_PRINT("HCSPLT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->host_if->hc_regs[i]->hcint; + DWC_PRINT("HCINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->host_if->hc_regs[i]->hcintmsk; + DWC_PRINT("HCINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->host_if->hc_regs[i]->hctsiz; + DWC_PRINT("HCTSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->host_if->hc_regs[i]->hcdma; + DWC_PRINT("HCDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + } + return; +} + +/** + * This function reads the core global registers and prints them + * + * @param core_if Programming view of DWC_otg controller. + */ +void dwc_otg_dump_global_registers(dwc_otg_core_if_t *core_if) +{ + int i; + volatile uint32_t *addr; + + DWC_PRINT("Core Global Registers\n"); + addr=&core_if->core_global_regs->gotgctl; + DWC_PRINT("GOTGCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->core_global_regs->gotgint; + DWC_PRINT("GOTGINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->core_global_regs->gahbcfg; + DWC_PRINT("GAHBCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->core_global_regs->gusbcfg; + DWC_PRINT("GUSBCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->core_global_regs->grstctl; + DWC_PRINT("GRSTCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->core_global_regs->gintsts; + DWC_PRINT("GINTSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->core_global_regs->gintmsk; + DWC_PRINT("GINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->core_global_regs->grxstsr; + DWC_PRINT("GRXSTSR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + //addr=&core_if->core_global_regs->grxstsp; + //DWC_PRINT("GRXSTSP @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->core_global_regs->grxfsiz; + DWC_PRINT("GRXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->core_global_regs->gnptxfsiz; + DWC_PRINT("GNPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->core_global_regs->gnptxsts; + DWC_PRINT("GNPTXSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->core_global_regs->gi2cctl; + DWC_PRINT("GI2CCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->core_global_regs->gpvndctl; + DWC_PRINT("GPVNDCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->core_global_regs->ggpio; + DWC_PRINT("GGPIO @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->core_global_regs->guid; + DWC_PRINT("GUID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->core_global_regs->gsnpsid; + DWC_PRINT("GSNPSID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->core_global_regs->ghwcfg1; + DWC_PRINT("GHWCFG1 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->core_global_regs->ghwcfg2; + DWC_PRINT("GHWCFG2 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->core_global_regs->ghwcfg3; + DWC_PRINT("GHWCFG3 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->core_global_regs->ghwcfg4; + DWC_PRINT("GHWCFG4 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&core_if->core_global_regs->hptxfsiz; + DWC_PRINT("HPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + + for (i=0; ihwcfg4.b.num_dev_perio_in_ep; i++) + { + addr=&core_if->core_global_regs->dptxfsiz_dieptxf[i]; + DWC_PRINT("DPTXFSIZ[%d] @0x%08X : 0x%08X\n",i,(uint32_t)addr,dwc_read_reg32(addr)); + } +} + +/** + * Flush a Tx FIFO. + * + * @param core_if Programming view of DWC_otg controller. + * @param num Tx FIFO to flush. + */ +void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t *core_if, + const int num) +{ + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; + volatile grstctl_t greset = { .d32 = 0}; + int count = 0; + + DWC_DEBUGPL((DBG_CIL|DBG_PCDV), "Flush Tx FIFO %d\n", num); + + greset.b.txfflsh = 1; + greset.b.txfnum = num; + dwc_write_reg32(&global_regs->grstctl, greset.d32); + + do { + greset.d32 = dwc_read_reg32(&global_regs->grstctl); + if (++count > 10000) { + DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n", + __func__, greset.d32, + dwc_read_reg32(&global_regs->gnptxsts)); + break; + } + } + while (greset.b.txfflsh == 1); + + /* Wait for 3 PHY Clocks*/ + UDELAY(1); +} + +/** + * Flush Rx FIFO. + * + * @param core_if Programming view of DWC_otg controller. + */ +void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t *core_if) +{ + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; + volatile grstctl_t greset = { .d32 = 0}; + int count = 0; + + DWC_DEBUGPL((DBG_CIL|DBG_PCDV), "%s\n", __func__); + /* + * + */ + greset.b.rxfflsh = 1; + dwc_write_reg32(&global_regs->grstctl, greset.d32); + + do { + greset.d32 = dwc_read_reg32(&global_regs->grstctl); + if (++count > 10000) { + DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__, + greset.d32); + break; + } + } + while (greset.b.rxfflsh == 1); + + /* Wait for 3 PHY Clocks*/ + UDELAY(1); +} + +/** + * Do core a soft reset of the core. Be careful with this because it + * resets all the internal state machines of the core. + */ +void dwc_otg_core_reset(dwc_otg_core_if_t *core_if) +{ + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; + volatile grstctl_t greset = { .d32 = 0}; + int count = 0; + + DWC_DEBUGPL(DBG_CILV, "%s\n", __func__); + /* Wait for AHB master IDLE state. */ + do { + UDELAY(10); + greset.d32 = dwc_read_reg32(&global_regs->grstctl); + if (++count > 100000) { + DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x\n", __func__, + greset.d32); + return; + } + } + while (greset.b.ahbidle == 0); + + /* Core Soft Reset */ + count = 0; + greset.b.csftrst = 1; + dwc_write_reg32(&global_regs->grstctl, greset.d32); + do { + greset.d32 = dwc_read_reg32(&global_regs->grstctl); + if (++count > 10000) { + DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n", __func__, + greset.d32); + break; + } + } + while (greset.b.csftrst == 1); + + /* Wait for 3 PHY Clocks*/ + MDELAY(100); +} + + + +/** + * Register HCD callbacks. The callbacks are used to start and stop + * the HCD for interrupt processing. + * + * @param core_if Programming view of DWC_otg controller. + * @param cb the HCD callback structure. + * @param p pointer to be passed to callback function (usb_hcd*). + */ +void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t *core_if, + dwc_otg_cil_callbacks_t *cb, + void *p) +{ + core_if->hcd_cb = cb; + cb->p = p; +} + +/** + * Register PCD callbacks. The callbacks are used to start and stop + * the PCD for interrupt processing. + * + * @param core_if Programming view of DWC_otg controller. + * @param cb the PCD callback structure. + * @param p pointer to be passed to callback function (pcd*). + */ +void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t *core_if, + dwc_otg_cil_callbacks_t *cb, + void *p) +{ + core_if->pcd_cb = cb; + cb->p = p; +} + +#ifdef DWC_EN_ISOC + +/** + * This function writes isoc data per 1 (micro)frame into tx fifo + * + * @param core_if Programming view of DWC_otg controller. + * @param ep The EP to start the transfer on. + * + */ +void write_isoc_frame_data(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) +{ + dwc_otg_dev_in_ep_regs_t *ep_regs; + dtxfsts_data_t txstatus = {.d32 = 0}; + uint32_t len = 0; + uint32_t dwords; + + ep->xfer_len = ep->data_per_frame; + ep->xfer_count = 0; + + ep_regs = core_if->dev_if->in_ep_regs[ep->num]; + + len = ep->xfer_len - ep->xfer_count; + + if (len > ep->maxpacket) { + len = ep->maxpacket; + } + + dwords = (len + 3)/4; + + /* While there is space in the queue and space in the FIFO and + * More data to tranfer, Write packets to the Tx FIFO */ + txstatus.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts); + DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n",ep->num,txstatus.d32); + + while (txstatus.b.txfspcavail > dwords && + ep->xfer_count < ep->xfer_len && + ep->xfer_len != 0) { + /* Write the FIFO */ + dwc_otg_ep_write_packet(core_if, ep, 0); + + len = ep->xfer_len - ep->xfer_count; + if (len > ep->maxpacket) { + len = ep->maxpacket; + } + + dwords = (len + 3)/4; + txstatus.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts); + DWC_DEBUGPL(DBG_PCDV,"dtxfsts[%d]=0x%08x\n", ep->num, txstatus.d32); + } +} + + +/** + * This function initializes a descriptor chain for Isochronous transfer + * + * @param core_if Programming view of DWC_otg controller. + * @param ep The EP to start the transfer on. + * + */ +void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) +{ + deptsiz_data_t deptsiz = { .d32 = 0 }; + depctl_data_t depctl = { .d32 = 0 }; + dsts_data_t dsts = { .d32 = 0 }; + volatile uint32_t *addr; + + if(ep->is_in) { + addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl; + } else { + addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl; + } + + ep->xfer_len = ep->data_per_frame; + ep->xfer_count = 0; + ep->xfer_buff = ep->cur_pkt_addr; + ep->dma_addr = ep->cur_pkt_dma_addr; + + if(ep->is_in) { + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet + * exist ? 1 : 0) + */ + deptsiz.b.xfersize = ep->xfer_len; + deptsiz.b.pktcnt = + (ep->xfer_len - 1 + ep->maxpacket) / + ep->maxpacket; + deptsiz.b.mc = deptsiz.b.pktcnt; + dwc_write_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz, deptsiz.d32); + + /* Write the DMA register */ + if (core_if->dma_enable) { + dwc_write_reg32 (&(core_if->dev_if->in_ep_regs[ep->num]->diepdma), (uint32_t)ep->dma_addr); + } + } else { + deptsiz.b.pktcnt = + (ep->xfer_len + (ep->maxpacket - 1)) / + ep->maxpacket; + deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket; + + dwc_write_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doeptsiz, deptsiz.d32); + + if (core_if->dma_enable) { + dwc_write_reg32 (&(core_if->dev_if->out_ep_regs[ep->num]->doepdma), + (uint32_t)ep->dma_addr); + } + } + + + /** Enable endpoint, clear nak */ + + depctl.d32 = 0; + if(ep->bInterval == 1) { + dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); + ep->next_frame = dsts.b.soffn + ep->bInterval; + + if(ep->next_frame & 0x1) { + depctl.b.setd1pid = 1; + } else { + depctl.b.setd0pid = 1; + } + } else { + ep->next_frame += ep->bInterval; + + if(ep->next_frame & 0x1) { + depctl.b.setd1pid = 1; + } else { + depctl.b.setd0pid = 1; + } + } + depctl.b.epena = 1; + depctl.b.cnak = 1; + + dwc_modify_reg32(addr, 0, depctl.d32); + depctl.d32 = dwc_read_reg32(addr); + + if(ep->is_in && core_if->dma_enable == 0) { + write_isoc_frame_data(core_if, ep); + } + +} + +#endif //DWC_EN_ISOC diff --git a/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_cil.h b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_cil.h new file mode 100644 index 0000000000..95079920a9 --- /dev/null +++ b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_cil.h @@ -0,0 +1,1098 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $ + * $Revision: 1.2 $ + * $Date: 2008-11-21 05:39:15 $ + * $Change: 1099526 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and + * redistribute this Software in source and binary forms, with or without + * modification, provided that redistributions of source code must retain this + * notice. You may not view, use, disclose, copy or distribute this file or + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * ========================================================================== */ + +#if !defined(__DWC_CIL_H__) +#define __DWC_CIL_H__ + +#include +#include +#include + +#include "linux/dwc_otg_plat.h" +#include "dwc_otg_regs.h" +#ifdef DEBUG +#include "linux/timer.h" +#endif + +/** + * @file + * This file contains the interface to the Core Interface Layer. + */ + + +/** Macros defined for DWC OTG HW Release verison */ +#define OTG_CORE_REV_2_00 0x4F542000 +#define OTG_CORE_REV_2_60a 0x4F54260A +#define OTG_CORE_REV_2_71a 0x4F54271A +#define OTG_CORE_REV_2_72a 0x4F54272A + +/** +*/ +typedef struct iso_pkt_info +{ + uint32_t offset; + uint32_t length; + int32_t status; +} iso_pkt_info_t; +/** + * The dwc_ep structure represents the state of a single + * endpoint when acting in device mode. It contains the data items + * needed for an endpoint to be activated and transfer packets. + */ +typedef struct dwc_ep +{ + /** EP number used for register address lookup */ + uint8_t num; + /** EP direction 0 = OUT */ + unsigned is_in : 1; + /** EP active. */ + unsigned active : 1; + + /** Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic Tx FIFO + If dedicated Tx FIFOs are enabled for all IN Eps - Tx FIFO # FOR IN EPs*/ + unsigned tx_fifo_num : 4; + /** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */ + unsigned type : 2; +#define DWC_OTG_EP_TYPE_CONTROL 0 +#define DWC_OTG_EP_TYPE_ISOC 1 +#define DWC_OTG_EP_TYPE_BULK 2 +#define DWC_OTG_EP_TYPE_INTR 3 + + /** DATA start PID for INTR and BULK EP */ + unsigned data_pid_start : 1; + /** Frame (even/odd) for ISOC EP */ + unsigned even_odd_frame : 1; + /** Max Packet bytes */ + unsigned maxpacket : 11; + + /** Max Transfer size */ + unsigned maxxfer : 16; + + /** @name Transfer state */ + /** @{ */ + + /** + * Pointer to the beginning of the transfer buffer -- do not modify + * during transfer. + */ + + uint32_t dma_addr; + + uint32_t dma_desc_addr; + dwc_otg_dma_desc_t* desc_addr; + + + uint8_t *start_xfer_buff; + /** pointer to the transfer buffer */ + uint8_t *xfer_buff; + /** Number of bytes to transfer */ + unsigned xfer_len : 19; + /** Number of bytes transferred. */ + unsigned xfer_count : 19; + /** Sent ZLP */ + unsigned sent_zlp : 1; + /** Total len for control transfer */ + unsigned total_len : 19; + + /** stall clear flag */ + unsigned stall_clear_flag : 1; + + /** Allocated DMA Desc count */ + uint32_t desc_cnt; + +#ifdef DWC_EN_ISOC + /** + * Variables specific for ISOC EPs + * + */ + /** DMA addresses of ISOC buffers */ + uint32_t dma_addr0; + uint32_t dma_addr1; + + uint32_t iso_dma_desc_addr; + dwc_otg_dma_desc_t* iso_desc_addr; + + /** pointer to the transfer buffers */ + uint8_t *xfer_buff0; + uint8_t *xfer_buff1; + + /** number of ISOC Buffer is processing */ + uint32_t proc_buf_num; + /** Interval of ISOC Buffer processing */ + uint32_t buf_proc_intrvl; + /** Data size for regular frame */ + uint32_t data_per_frame; + + /* todo - pattern data support is to be implemented in the future */ + /** Data size for pattern frame */ + uint32_t data_pattern_frame; + /** Frame number of pattern data */ + uint32_t sync_frame; + + /** bInterval */ + uint32_t bInterval; + /** ISO Packet number per frame */ + uint32_t pkt_per_frm; + /** Next frame num for which will be setup DMA Desc */ + uint32_t next_frame; + /** Number of packets per buffer processing */ + uint32_t pkt_cnt; + /** Info for all isoc packets */ + iso_pkt_info_t *pkt_info; + /** current pkt number */ + uint32_t cur_pkt; + /** current pkt number */ + uint8_t *cur_pkt_addr; + /** current pkt number */ + uint32_t cur_pkt_dma_addr; +#endif //DWC_EN_ISOC +/** @} */ +} dwc_ep_t; + +/* + * Reasons for halting a host channel. + */ +typedef enum dwc_otg_halt_status +{ + DWC_OTG_HC_XFER_NO_HALT_STATUS, + DWC_OTG_HC_XFER_COMPLETE, + DWC_OTG_HC_XFER_URB_COMPLETE, + DWC_OTG_HC_XFER_ACK, + DWC_OTG_HC_XFER_NAK, + DWC_OTG_HC_XFER_NYET, + DWC_OTG_HC_XFER_STALL, + DWC_OTG_HC_XFER_XACT_ERR, + DWC_OTG_HC_XFER_FRAME_OVERRUN, + DWC_OTG_HC_XFER_BABBLE_ERR, + DWC_OTG_HC_XFER_DATA_TOGGLE_ERR, + DWC_OTG_HC_XFER_AHB_ERR, + DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE, + DWC_OTG_HC_XFER_URB_DEQUEUE +} dwc_otg_halt_status_e; + +/** + * Host channel descriptor. This structure represents the state of a single + * host channel when acting in host mode. It contains the data items needed to + * transfer packets to an endpoint via a host channel. + */ +typedef struct dwc_hc +{ + /** Host channel number used for register address lookup */ + uint8_t hc_num; + + /** Device to access */ + unsigned dev_addr : 7; + + /** EP to access */ + unsigned ep_num : 4; + + /** EP direction. 0: OUT, 1: IN */ + unsigned ep_is_in : 1; + + /** + * EP speed. + * One of the following values: + * - DWC_OTG_EP_SPEED_LOW + * - DWC_OTG_EP_SPEED_FULL + * - DWC_OTG_EP_SPEED_HIGH + */ + unsigned speed : 2; +#define DWC_OTG_EP_SPEED_LOW 0 +#define DWC_OTG_EP_SPEED_FULL 1 +#define DWC_OTG_EP_SPEED_HIGH 2 + + /** + * Endpoint type. + * One of the following values: + * - DWC_OTG_EP_TYPE_CONTROL: 0 + * - DWC_OTG_EP_TYPE_ISOC: 1 + * - DWC_OTG_EP_TYPE_BULK: 2 + * - DWC_OTG_EP_TYPE_INTR: 3 + */ + unsigned ep_type : 2; + + /** Max packet size in bytes */ + unsigned max_packet : 11; + + /** + * PID for initial transaction. + * 0: DATA0,
+ * 1: DATA2,
+ * 2: DATA1,
+ * 3: MDATA (non-Control EP), + * SETUP (Control EP) + */ + unsigned data_pid_start : 2; +#define DWC_OTG_HC_PID_DATA0 0 +#define DWC_OTG_HC_PID_DATA2 1 +#define DWC_OTG_HC_PID_DATA1 2 +#define DWC_OTG_HC_PID_MDATA 3 +#define DWC_OTG_HC_PID_SETUP 3 + + /** Number of periodic transactions per (micro)frame */ + unsigned multi_count: 2; + + /** @name Transfer State */ + /** @{ */ + + /** Pointer to the current transfer buffer position. */ + uint8_t *xfer_buff; + /** Total number of bytes to transfer. */ + uint32_t xfer_len; + /** Number of bytes transferred so far. */ + uint32_t xfer_count; + /** Packet count at start of transfer.*/ + uint16_t start_pkt_count; + + /** + * Flag to indicate whether the transfer has been started. Set to 1 if + * it has been started, 0 otherwise. + */ + uint8_t xfer_started; + + /** + * Set to 1 to indicate that a PING request should be issued on this + * channel. If 0, process normally. + */ + uint8_t do_ping; + + /** + * Set to 1 to indicate that the error count for this transaction is + * non-zero. Set to 0 if the error count is 0. + */ + uint8_t error_state; + + /** + * Set to 1 to indicate that this channel should be halted the next + * time a request is queued for the channel. This is necessary in + * slave mode if no request queue space is available when an attempt + * is made to halt the channel. + */ + uint8_t halt_on_queue; + + /** + * Set to 1 if the host channel has been halted, but the core is not + * finished flushing queued requests. Otherwise 0. + */ + uint8_t halt_pending; + + /** + * Reason for halting the host channel. + */ + dwc_otg_halt_status_e halt_status; + + /* + * Split settings for the host channel + */ + uint8_t do_split; /**< Enable split for the channel */ + uint8_t complete_split; /**< Enable complete split */ + uint8_t hub_addr; /**< Address of high speed hub */ + + uint8_t port_addr; /**< Port of the low/full speed device */ + /** Split transaction position + * One of the following values: + * - DWC_HCSPLIT_XACTPOS_MID + * - DWC_HCSPLIT_XACTPOS_BEGIN + * - DWC_HCSPLIT_XACTPOS_END + * - DWC_HCSPLIT_XACTPOS_ALL */ + uint8_t xact_pos; + + /** Set when the host channel does a short read. */ + uint8_t short_read; + + /** + * Number of requests issued for this channel since it was assigned to + * the current transfer (not counting PINGs). + */ + uint8_t requests; + + /** + * Queue Head for the transfer being processed by this channel. + */ + struct dwc_otg_qh *qh; + + /** @} */ + + /** Entry in list of host channels. */ + struct list_head hc_list_entry; +} dwc_hc_t; + +/** + * The following parameters may be specified when starting the module. These + * parameters define how the DWC_otg controller should be configured. + * Parameter values are passed to the CIL initialization function + * dwc_otg_cil_init. + */ +typedef struct dwc_otg_core_params +{ + int32_t opt; +#define dwc_param_opt_default 1 + + /** + * Specifies the OTG capabilities. The driver will automatically + * detect the value for this parameter if none is specified. + * 0 - HNP and SRP capable (default) + * 1 - SRP Only capable + * 2 - No HNP/SRP capable + */ + int32_t otg_cap; +#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0 +#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1 +#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 +#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE + + /** + * Specifies whether to use slave or DMA mode for accessing the data + * FIFOs. The driver will automatically detect the value for this + * parameter if none is specified. + * 0 - Slave + * 1 - DMA (default, if available) + */ + int32_t dma_enable; +#define dwc_param_dma_enable_default 1 + + /** + * When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data + * FIFOs in device mode. The driver will automatically detect the value for this + * parameter if none is specified. + * 0 - address DMA + * 1 - DMA Descriptor(default, if available) + */ + int32_t dma_desc_enable; +#define dwc_param_dma_desc_enable_default 0 + /** The DMA Burst size (applicable only for External DMA + * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32) + */ + int32_t dma_burst_size; /* Translate this to GAHBCFG values */ +#define dwc_param_dma_burst_size_default 32 + + /** + * Specifies the maximum speed of operation in host and device mode. + * The actual speed depends on the speed of the attached device and + * the value of phy_type. The actual speed depends on the speed of the + * attached device. + * 0 - High Speed (default) + * 1 - Full Speed + */ + int32_t speed; +#define dwc_param_speed_default 0 +#define DWC_SPEED_PARAM_HIGH 0 +#define DWC_SPEED_PARAM_FULL 1 + + /** Specifies whether low power mode is supported when attached + * to a Full Speed or Low Speed device in host mode. + * 0 - Don't support low power mode (default) + * 1 - Support low power mode + */ + int32_t host_support_fs_ls_low_power; +#define dwc_param_host_support_fs_ls_low_power_default 0 + + /** Specifies the PHY clock rate in low power mode when connected to a + * Low Speed device in host mode. This parameter is applicable only if + * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS + * then defaults to 6 MHZ otherwise 48 MHZ. + * + * 0 - 48 MHz + * 1 - 6 MHz + */ + int32_t host_ls_low_power_phy_clk; +#define dwc_param_host_ls_low_power_phy_clk_default 0 +#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 +#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 + + /** + * 0 - Use cC FIFO size parameters + * 1 - Allow dynamic FIFO sizing (default) + */ + int32_t enable_dynamic_fifo; +#define dwc_param_enable_dynamic_fifo_default 1 + + /** Total number of 4-byte words in the data FIFO memory. This + * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic + * Tx FIFOs. + * 32 to 32768 (default 8192) + * Note: The total FIFO memory depth in the FPGA configuration is 8192. + */ + int32_t data_fifo_size; +#define dwc_param_data_fifo_size_default 8192 + + /** Number of 4-byte words in the Rx FIFO in device mode when dynamic + * FIFO sizing is enabled. + * 16 to 32768 (default 1064) + */ + int32_t dev_rx_fifo_size; +#define dwc_param_dev_rx_fifo_size_default 1064 + + /** Number of 4-byte words in the non-periodic Tx FIFO in device mode + * when dynamic FIFO sizing is enabled. + * 16 to 32768 (default 1024) + */ + int32_t dev_nperio_tx_fifo_size; +#define dwc_param_dev_nperio_tx_fifo_size_default 1024 + + /** Number of 4-byte words in each of the periodic Tx FIFOs in device + * mode when dynamic FIFO sizing is enabled. + * 4 to 768 (default 256) + */ + uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS]; +#define dwc_param_dev_perio_tx_fifo_size_default 256 + + /** Number of 4-byte words in the Rx FIFO in host mode when dynamic + * FIFO sizing is enabled. + * 16 to 32768 (default 1024) + */ + int32_t host_rx_fifo_size; +#define dwc_param_host_rx_fifo_size_default 1024 + + /** Number of 4-byte words in the non-periodic Tx FIFO in host mode + * when Dynamic FIFO sizing is enabled in the core. + * 16 to 32768 (default 1024) + */ + int32_t host_nperio_tx_fifo_size; +#define dwc_param_host_nperio_tx_fifo_size_default 1024 + + /** Number of 4-byte words in the host periodic Tx FIFO when dynamic + * FIFO sizing is enabled. + * 16 to 32768 (default 1024) + */ + int32_t host_perio_tx_fifo_size; +#define dwc_param_host_perio_tx_fifo_size_default 1024 + + /** The maximum transfer size supported in bytes. + * 2047 to 65,535 (default 65,535) + */ + int32_t max_transfer_size; +#define dwc_param_max_transfer_size_default 65535 + + /** The maximum number of packets in a transfer. + * 15 to 511 (default 511) + */ + int32_t max_packet_count; +#define dwc_param_max_packet_count_default 511 + + /** The number of host channel registers to use. + * 1 to 16 (default 12) + * Note: The FPGA configuration supports a maximum of 12 host channels. + */ + int32_t host_channels; +#define dwc_param_host_channels_default 12 + + /** The number of endpoints in addition to EP0 available for device + * mode operations. + * 1 to 15 (default 6 IN and OUT) + * Note: The FPGA configuration supports a maximum of 6 IN and OUT + * endpoints in addition to EP0. + */ + int32_t dev_endpoints; +#define dwc_param_dev_endpoints_default 6 + + /** + * Specifies the type of PHY interface to use. By default, the driver + * will automatically detect the phy_type. + * + * 0 - Full Speed PHY + * 1 - UTMI+ (default) + * 2 - ULPI + */ + int32_t phy_type; +#define DWC_PHY_TYPE_PARAM_FS 0 +#define DWC_PHY_TYPE_PARAM_UTMI 1 +#define DWC_PHY_TYPE_PARAM_ULPI 2 +#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI + + /** + * Specifies the UTMI+ Data Width. This parameter is + * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI + * PHY_TYPE, this parameter indicates the data width between + * the MAC and the ULPI Wrapper.) Also, this parameter is + * applicable only if the OTG_HSPHY_WIDTH cC parameter was set + * to "8 and 16 bits", meaning that the core has been + * configured to work at either data path width. + * + * 8 or 16 bits (default 16) + */ + int32_t phy_utmi_width; +#define dwc_param_phy_utmi_width_default 16 + + /** + * Specifies whether the ULPI operates at double or single + * data rate. This parameter is only applicable if PHY_TYPE is + * ULPI. + * + * 0 - single data rate ULPI interface with 8 bit wide data + * bus (default) + * 1 - double data rate ULPI interface with 4 bit wide data + * bus + */ + int32_t phy_ulpi_ddr; +#define dwc_param_phy_ulpi_ddr_default 0 + + /** + * Specifies whether to use the internal or external supply to + * drive the vbus with a ULPI phy. + */ + int32_t phy_ulpi_ext_vbus; +#define DWC_PHY_ULPI_INTERNAL_VBUS 0 +#define DWC_PHY_ULPI_EXTERNAL_VBUS 1 +#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS + + /** + * Specifies whether to use the I2Cinterface for full speed PHY. This + * parameter is only applicable if PHY_TYPE is FS. + * 0 - No (default) + * 1 - Yes + */ + int32_t i2c_enable; +#define dwc_param_i2c_enable_default 0 + + int32_t ulpi_fs_ls; +#define dwc_param_ulpi_fs_ls_default 0 + + int32_t ts_dline; +#define dwc_param_ts_dline_default 0 + + /** + * Specifies whether dedicated transmit FIFOs are + * enabled for non periodic IN endpoints in device mode + * 0 - No + * 1 - Yes + */ + int32_t en_multiple_tx_fifo; +#define dwc_param_en_multiple_tx_fifo_default 1 + + /** Number of 4-byte words in each of the Tx FIFOs in device + * mode when dynamic FIFO sizing is enabled. + * 4 to 768 (default 256) + */ + uint32_t dev_tx_fifo_size[MAX_TX_FIFOS]; +#define dwc_param_dev_tx_fifo_size_default 256 + + /** Thresholding enable flag- + * bit 0 - enable non-ISO Tx thresholding + * bit 1 - enable ISO Tx thresholding + * bit 2 - enable Rx thresholding + */ + uint32_t thr_ctl; +#define dwc_param_thr_ctl_default 0 + + /** Thresholding length for Tx + * FIFOs in 32 bit DWORDs + */ + uint32_t tx_thr_length; +#define dwc_param_tx_thr_length_default 64 + + /** Thresholding length for Rx + * FIFOs in 32 bit DWORDs + */ + uint32_t rx_thr_length; +#define dwc_param_rx_thr_length_default 64 + + /** Per Transfer Interrupt + * mode enable flag + * 1 - Enabled + * 0 - Disabled + */ + uint32_t pti_enable; +#define dwc_param_pti_enable_default 0 + + /** Molti Processor Interrupt + * mode enable flag + * 1 - Enabled + * 0 - Disabled + */ + uint32_t mpi_enable; +#define dwc_param_mpi_enable_default 0 + +} dwc_otg_core_params_t; + +#ifdef DEBUG +struct dwc_otg_core_if; +typedef struct hc_xfer_info +{ + struct dwc_otg_core_if *core_if; + dwc_hc_t *hc; +} hc_xfer_info_t; +#endif + +/** + * The dwc_otg_core_if structure contains information needed to manage + * the DWC_otg controller acting in either host or device mode. It + * represents the programming view of the controller as a whole. + */ +typedef struct dwc_otg_core_if +{ + /** Parameters that define how the core should be configured.*/ + dwc_otg_core_params_t *core_params; + + /** Core Global registers starting at offset 000h. */ + dwc_otg_core_global_regs_t *core_global_regs; + + /** Device-specific information */ + dwc_otg_dev_if_t *dev_if; + /** Host-specific information */ + dwc_otg_host_if_t *host_if; + + /** Value from SNPSID register */ + uint32_t snpsid; + + /* + * Set to 1 if the core PHY interface bits in USBCFG have been + * initialized. + */ + uint8_t phy_init_done; + + /* + * SRP Success flag, set by srp success interrupt in FS I2C mode + */ + uint8_t srp_success; + uint8_t srp_timer_started; + + /* Common configuration information */ + /** Power and Clock Gating Control Register */ + volatile uint32_t *pcgcctl; +#define DWC_OTG_PCGCCTL_OFFSET 0xE00 + + /** Push/pop addresses for endpoints or host channels.*/ + uint32_t *data_fifo[MAX_EPS_CHANNELS]; +#define DWC_OTG_DATA_FIFO_OFFSET 0x1000 +#define DWC_OTG_DATA_FIFO_SIZE 0x1000 + + /** Total RAM for FIFOs (Bytes) */ + uint16_t total_fifo_size; + /** Size of Rx FIFO (Bytes) */ + uint16_t rx_fifo_size; + /** Size of Non-periodic Tx FIFO (Bytes) */ + uint16_t nperio_tx_fifo_size; + + + /** 1 if DMA is enabled, 0 otherwise. */ + uint8_t dma_enable; + + /** 1 if Descriptor DMA mode is enabled, 0 otherwise. */ + uint8_t dma_desc_enable; + + /** 1 if PTI Enhancement mode is enabled, 0 otherwise. */ + uint8_t pti_enh_enable; + + /** 1 if MPI Enhancement mode is enabled, 0 otherwise. */ + uint8_t multiproc_int_enable; + + /** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */ + uint8_t en_multiple_tx_fifo; + + /** Set to 1 if multiple packets of a high-bandwidth transfer is in + * process of being queued */ + uint8_t queuing_high_bandwidth; + + /** Hardware Configuration -- stored here for convenience.*/ + hwcfg1_data_t hwcfg1; + hwcfg2_data_t hwcfg2; + hwcfg3_data_t hwcfg3; + hwcfg4_data_t hwcfg4; + + /** Host and Device Configuration -- stored here for convenience.*/ + hcfg_data_t hcfg; + dcfg_data_t dcfg; + + /** The operational State, during transations + * (a_host>>a_peripherial and b_device=>b_host) this may not + * match the core but allows the software to determine + * transitions. + */ + uint8_t op_state; + + /** + * Set to 1 if the HCD needs to be restarted on a session request + * interrupt. This is required if no connector ID status change has + * occurred since the HCD was last disconnected. + */ + uint8_t restart_hcd_on_session_req; + + /** HCD callbacks */ + /** A-Device is a_host */ +#define A_HOST (1) + /** A-Device is a_suspend */ +#define A_SUSPEND (2) + /** A-Device is a_peripherial */ +#define A_PERIPHERAL (3) + /** B-Device is operating as a Peripheral. */ +#define B_PERIPHERAL (4) + /** B-Device is operating as a Host. */ +#define B_HOST (5) + + /** HCD callbacks */ + struct dwc_otg_cil_callbacks *hcd_cb; + /** PCD callbacks */ + struct dwc_otg_cil_callbacks *pcd_cb; + + /** Device mode Periodic Tx FIFO Mask */ + uint32_t p_tx_msk; + /** Device mode Periodic Tx FIFO Mask */ + uint32_t tx_msk; + + /** Workqueue object used for handling several interrupts */ + struct workqueue_struct *wq_otg; + + /** Work object used for handling "Connector ID Status Change" Interrupt */ + struct work_struct w_conn_id; + + /** Work object used for handling "Wakeup Detected" Interrupt */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) + struct work_struct w_wkp; +#else + struct delayed_work w_wkp; +#endif + +#ifdef DEBUG + uint32_t start_hcchar_val[MAX_EPS_CHANNELS]; + + hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS]; + struct timer_list hc_xfer_timer[MAX_EPS_CHANNELS]; + + uint32_t hfnum_7_samples; + uint64_t hfnum_7_frrem_accum; + uint32_t hfnum_0_samples; + uint64_t hfnum_0_frrem_accum; + uint32_t hfnum_other_samples; + uint64_t hfnum_other_frrem_accum; +#endif + + +} dwc_otg_core_if_t; + +/*We must clear S3C24XX_EINTPEND external interrupt register + * because after clearing in this register trigerred IRQ from + * H/W core in kernel interrupt can be occured again before OTG + * handlers clear all IRQ sources of Core registers because of + * timing latencies and Low Level IRQ Type. + */ + +#ifdef CONFIG_MACH_IPMATE +#define S3C2410X_CLEAR_EINTPEND() \ +do { \ + if (!dwc_otg_read_core_intr(core_if)) { \ + __raw_writel(1UL << 11,S3C24XX_EINTPEND); \ + } \ +} while (0) +#else +#define S3C2410X_CLEAR_EINTPEND() do { } while (0) +#endif + +/* + * The following functions are functions for works + * using during handling some interrupts + */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) + +extern void w_conn_id_status_change(void *p); +extern void w_wakeup_detected(void *p); + +#else + +extern void w_conn_id_status_change(struct work_struct *p); +extern void w_wakeup_detected(struct work_struct *p); + +#endif + + +/* + * The following functions support initialization of the CIL driver component + * and the DWC_otg controller. + */ +extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *_reg_base_addr, + dwc_otg_core_params_t *_core_params); +extern void dwc_otg_cil_remove(dwc_otg_core_if_t *_core_if); +extern void dwc_otg_core_init(dwc_otg_core_if_t *_core_if); +extern void dwc_otg_core_host_init(dwc_otg_core_if_t *_core_if); +extern void dwc_otg_core_dev_init(dwc_otg_core_if_t *_core_if); +extern void dwc_otg_enable_global_interrupts( dwc_otg_core_if_t *_core_if ); +extern void dwc_otg_disable_global_interrupts( dwc_otg_core_if_t *_core_if ); + +/** @name Device CIL Functions + * The following functions support managing the DWC_otg controller in device + * mode. + */ +/**@{*/ +extern void dwc_otg_wakeup(dwc_otg_core_if_t *_core_if); +extern void dwc_otg_read_setup_packet (dwc_otg_core_if_t *_core_if, uint32_t *_dest); +extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *_core_if); +extern void dwc_otg_ep0_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); +extern void dwc_otg_ep_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); +extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); +extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); +extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); +extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); +extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); +extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep, int _dma); +extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); +extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); +extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *_core_if); +extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t *_core_if); +extern void dwc_otg_dump_spram(dwc_otg_core_if_t *_core_if); +#ifdef DWC_EN_ISOC +extern void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep); +extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep); +#endif //DWC_EN_ISOC +/**@}*/ + +/** @name Host CIL Functions + * The following functions support managing the DWC_otg controller in host + * mode. + */ +/**@{*/ +extern void dwc_otg_hc_init(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc); +extern void dwc_otg_hc_halt(dwc_otg_core_if_t *_core_if, + dwc_hc_t *_hc, + dwc_otg_halt_status_e _halt_status); +extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc); +extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc); +extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc); +extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc); +extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc); +extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *_core_if); +extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *_core_if); + +/** + * This function Reads HPRT0 in preparation to modify. It keeps the + * WC bits 0 so that if they are read as 1, they won't clear when you + * write it back + */ +static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t *_core_if) +{ + hprt0_data_t hprt0; + hprt0.d32 = dwc_read_reg32(_core_if->host_if->hprt0); + hprt0.b.prtena = 0; + hprt0.b.prtconndet = 0; + hprt0.b.prtenchng = 0; + hprt0.b.prtovrcurrchng = 0; + return hprt0.d32; +} + +extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t *_core_if); +/**@}*/ + +/** @name Common CIL Functions + * The following functions support managing the DWC_otg controller in either + * device or host mode. + */ +/**@{*/ + +extern void dwc_otg_read_packet(dwc_otg_core_if_t *core_if, + uint8_t *dest, + uint16_t bytes); + +extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t *_core_if); + +extern void dwc_otg_flush_tx_fifo( dwc_otg_core_if_t *_core_if, + const int _num ); +extern void dwc_otg_flush_rx_fifo( dwc_otg_core_if_t *_core_if ); +extern void dwc_otg_core_reset( dwc_otg_core_if_t *_core_if ); + +extern dwc_otg_dma_desc_t* dwc_otg_ep_alloc_desc_chain(uint32_t * dma_desc_addr, uint32_t count); +extern void dwc_otg_ep_free_desc_chain(dwc_otg_dma_desc_t* desc_addr, uint32_t dma_desc_addr, uint32_t count); + +/** + * This function returns the Core Interrupt register. + */ +static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t *_core_if) +{ + return (dwc_read_reg32(&_core_if->core_global_regs->gintsts) & + dwc_read_reg32(&_core_if->core_global_regs->gintmsk)); +} + +/** + * This function returns the OTG Interrupt register. + */ +static inline uint32_t dwc_otg_read_otg_intr (dwc_otg_core_if_t *_core_if) +{ + return (dwc_read_reg32 (&_core_if->core_global_regs->gotgint)); +} + +/** + * This function reads the Device All Endpoints Interrupt register and + * returns the IN endpoint interrupt bits. + */ +static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *core_if) +{ + uint32_t v; + + if(core_if->multiproc_int_enable) { + v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachint) & + dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachintmsk); + } else { + v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->daint) & + dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk); + } + return (v & 0xffff); + +} + +/** + * This function reads the Device All Endpoints Interrupt register and + * returns the OUT endpoint interrupt bits. + */ +static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *core_if) +{ + uint32_t v; + + if(core_if->multiproc_int_enable) { + v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachint) & + dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachintmsk); + } else { + v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->daint) & + dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk); + } + + return ((v & 0xffff0000) >> 16); +} + +/** + * This function returns the Device IN EP Interrupt register + */ +static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t *core_if, + dwc_ep_t *ep) +{ + dwc_otg_dev_if_t *dev_if = core_if->dev_if; + uint32_t v, msk, emp; + + if(core_if->multiproc_int_enable) { + msk = dwc_read_reg32(&dev_if->dev_global_regs->diepeachintmsk[ep->num]); + emp = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk); + msk |= ((emp >> ep->num) & 0x1) << 7; + v = dwc_read_reg32(&dev_if->in_ep_regs[ep->num]->diepint) & msk; + } else { + msk = dwc_read_reg32(&dev_if->dev_global_regs->diepmsk); + emp = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk); + msk |= ((emp >> ep->num) & 0x1) << 7; + v = dwc_read_reg32(&dev_if->in_ep_regs[ep->num]->diepint) & msk; + } + + + return v; +} +/** + * This function returns the Device OUT EP Interrupt register + */ +static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *_core_if, + dwc_ep_t *_ep) +{ + dwc_otg_dev_if_t *dev_if = _core_if->dev_if; + uint32_t v; + doepmsk_data_t msk = { .d32 = 0 }; + + if(_core_if->multiproc_int_enable) { + msk.d32 = dwc_read_reg32(&dev_if->dev_global_regs->doepeachintmsk[_ep->num]); + if(_core_if->pti_enh_enable) { + msk.b.pktdrpsts = 1; + } + v = dwc_read_reg32( &dev_if->out_ep_regs[_ep->num]->doepint) & msk.d32; + } else { + msk.d32 = dwc_read_reg32(&dev_if->dev_global_regs->doepmsk); + if(_core_if->pti_enh_enable) { + msk.b.pktdrpsts = 1; + } + v = dwc_read_reg32( &dev_if->out_ep_regs[_ep->num]->doepint) & msk.d32; + } + return v; +} + +/** + * This function returns the Host All Channel Interrupt register + */ +static inline uint32_t dwc_otg_read_host_all_channels_intr (dwc_otg_core_if_t *_core_if) +{ + return (dwc_read_reg32 (&_core_if->host_if->host_global_regs->haint)); +} + +static inline uint32_t dwc_otg_read_host_channel_intr (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc) +{ + return (dwc_read_reg32 (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint)); +} + + +/** + * This function returns the mode of the operation, host or device. + * + * @return 0 - Device Mode, 1 - Host Mode + */ +static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t *_core_if) +{ + return (dwc_read_reg32( &_core_if->core_global_regs->gintsts ) & 0x1); +} + +static inline uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t *_core_if) +{ + return (dwc_otg_mode(_core_if) != DWC_HOST_MODE); +} +static inline uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t *_core_if) +{ + return (dwc_otg_mode(_core_if) == DWC_HOST_MODE); +} + +extern int32_t dwc_otg_handle_common_intr( dwc_otg_core_if_t *_core_if ); + + +/**@}*/ + +/** + * DWC_otg CIL callback structure. This structure allows the HCD and + * PCD to register functions used for starting and stopping the PCD + * and HCD for role change on for a DRD. + */ +typedef struct dwc_otg_cil_callbacks +{ + /** Start function for role change */ + int (*start) (void *_p); + /** Stop Function for role change */ + int (*stop) (void *_p); + /** Disconnect Function for role change */ + int (*disconnect) (void *_p); + /** Resume/Remote wakeup Function */ + int (*resume_wakeup) (void *_p); + /** Suspend function */ + int (*suspend) (void *_p); + /** Session Start (SRP) */ + int (*session_start) (void *_p); + /** Pointer passed to start() and stop() */ + void *p; +} dwc_otg_cil_callbacks_t; + +extern void dwc_otg_cil_register_pcd_callbacks( dwc_otg_core_if_t *_core_if, + dwc_otg_cil_callbacks_t *_cb, + void *_p); +extern void dwc_otg_cil_register_hcd_callbacks( dwc_otg_core_if_t *_core_if, + dwc_otg_cil_callbacks_t *_cb, + void *_p); + +#endif + diff --git a/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_cil_intr.c b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_cil_intr.c new file mode 100644 index 0000000000..61b17b35dc --- /dev/null +++ b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_cil_intr.c @@ -0,0 +1,750 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $ + * $Revision: 1.2 $ + * $Date: 2008-11-21 05:39:15 $ + * $Change: 1065567 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and + * redistribute this Software in source and binary forms, with or without + * modification, provided that redistributions of source code must retain this + * notice. You may not view, use, disclose, copy or distribute this file or + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * ========================================================================== */ + +/** @file + * + * The Core Interface Layer provides basic services for accessing and + * managing the DWC_otg hardware. These services are used by both the + * Host Controller Driver and the Peripheral Controller Driver. + * + * This file contains the Common Interrupt handlers. + */ +#include "linux/dwc_otg_plat.h" +#include "dwc_otg_regs.h" +#include "dwc_otg_cil.h" + +#ifdef DEBUG +inline const char *op_state_str(dwc_otg_core_if_t *core_if) +{ + return (core_if->op_state==A_HOST?"a_host": + (core_if->op_state==A_SUSPEND?"a_suspend": + (core_if->op_state==A_PERIPHERAL?"a_peripheral": + (core_if->op_state==B_PERIPHERAL?"b_peripheral": + (core_if->op_state==B_HOST?"b_host": + "unknown"))))); +} +#endif + +/** This function will log a debug message + * + * @param core_if Programming view of DWC_otg controller. + */ +int32_t dwc_otg_handle_mode_mismatch_intr (dwc_otg_core_if_t *core_if) +{ + gintsts_data_t gintsts; + DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n", + dwc_otg_mode(core_if) ? "Host" : "Device"); + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.modemismatch = 1; + dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32); + return 1; +} + +/** Start the HCD. Helper function for using the HCD callbacks. + * + * @param core_if Programming view of DWC_otg controller. + */ +static inline void hcd_start(dwc_otg_core_if_t *core_if) +{ + if (core_if->hcd_cb && core_if->hcd_cb->start) { + core_if->hcd_cb->start(core_if->hcd_cb->p); + } +} +/** Stop the HCD. Helper function for using the HCD callbacks. + * + * @param core_if Programming view of DWC_otg controller. + */ +static inline void hcd_stop(dwc_otg_core_if_t *core_if) +{ + if (core_if->hcd_cb && core_if->hcd_cb->stop) { + core_if->hcd_cb->stop(core_if->hcd_cb->p); + } +} +/** Disconnect the HCD. Helper function for using the HCD callbacks. + * + * @param core_if Programming view of DWC_otg controller. + */ +static inline void hcd_disconnect(dwc_otg_core_if_t *core_if) +{ + if (core_if->hcd_cb && core_if->hcd_cb->disconnect) { + core_if->hcd_cb->disconnect(core_if->hcd_cb->p); + } +} +/** Inform the HCD the a New Session has begun. Helper function for + * using the HCD callbacks. + * + * @param core_if Programming view of DWC_otg controller. + */ +static inline void hcd_session_start(dwc_otg_core_if_t *core_if) +{ + if (core_if->hcd_cb && core_if->hcd_cb->session_start) { + core_if->hcd_cb->session_start(core_if->hcd_cb->p); + } +} + +/** Start the PCD. Helper function for using the PCD callbacks. + * + * @param core_if Programming view of DWC_otg controller. + */ +static inline void pcd_start(dwc_otg_core_if_t *core_if) +{ + if (core_if->pcd_cb && core_if->pcd_cb->start) { + core_if->pcd_cb->start(core_if->pcd_cb->p); + } +} +/** Stop the PCD. Helper function for using the PCD callbacks. + * + * @param core_if Programming view of DWC_otg controller. + */ +static inline void pcd_stop(dwc_otg_core_if_t *core_if) +{ + if (core_if->pcd_cb && core_if->pcd_cb->stop) { + core_if->pcd_cb->stop(core_if->pcd_cb->p); + } +} +/** Suspend the PCD. Helper function for using the PCD callbacks. + * + * @param core_if Programming view of DWC_otg controller. + */ +static inline void pcd_suspend(dwc_otg_core_if_t *core_if) +{ + if (core_if->pcd_cb && core_if->pcd_cb->suspend) { + core_if->pcd_cb->suspend(core_if->pcd_cb->p); + } +} +/** Resume the PCD. Helper function for using the PCD callbacks. + * + * @param core_if Programming view of DWC_otg controller. + */ +static inline void pcd_resume(dwc_otg_core_if_t *core_if) +{ + if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) { + core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p); + } +} + +/** + * This function handles the OTG Interrupts. It reads the OTG + * Interrupt Register (GOTGINT) to determine what interrupt has + * occurred. + * + * @param core_if Programming view of DWC_otg controller. + */ +int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t *core_if) +{ + dwc_otg_core_global_regs_t *global_regs = + core_if->core_global_regs; + gotgint_data_t gotgint; + gotgctl_data_t gotgctl; + gintmsk_data_t gintmsk; + + gotgint.d32 = dwc_read_reg32(&global_regs->gotgint); + gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl); + DWC_DEBUGPL(DBG_CIL, "gotgctl=%08x\n", gotgctl.d32); + + if (gotgint.b.sesenddet) { + DWC_DEBUGPL(DBG_ANY, "OTG Interrupt: " + "Session End Detected++ (%s)\n", + op_state_str(core_if)); + gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl); + + if (core_if->op_state == B_HOST) { + pcd_start(core_if); + core_if->op_state = B_PERIPHERAL; + } else { + /* If not B_HOST and Device HNP still set. HNP + * Did not succeed!*/ + if (gotgctl.b.devhnpen) { + DWC_DEBUGPL(DBG_ANY, "Session End Detected\n"); + DWC_ERROR("Device Not Connected/Responding!\n"); + } + + /* If Session End Detected the B-Cable has + * been disconnected. */ + /* Reset PCD and Gadget driver to a + * clean state. */ + pcd_stop(core_if); + } + gotgctl.d32 = 0; + gotgctl.b.devhnpen = 1; + dwc_modify_reg32(&global_regs->gotgctl, + gotgctl.d32, 0); + } + if (gotgint.b.sesreqsucstschng) { + DWC_DEBUGPL(DBG_ANY, " OTG Interrupt: " + "Session Reqeust Success Status Change++\n"); + gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl); + if (gotgctl.b.sesreqscs) { + if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) && + (core_if->core_params->i2c_enable)) { + core_if->srp_success = 1; + } + else { + pcd_resume(core_if); + /* Clear Session Request */ + gotgctl.d32 = 0; + gotgctl.b.sesreq = 1; + dwc_modify_reg32(&global_regs->gotgctl, + gotgctl.d32, 0); + } + } + } + if (gotgint.b.hstnegsucstschng) { + /* Print statements during the HNP interrupt handling + * can cause it to fail.*/ + gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl); + if (gotgctl.b.hstnegscs) { + if (dwc_otg_is_host_mode(core_if)) { + core_if->op_state = B_HOST; + /* + * Need to disable SOF interrupt immediately. + * When switching from device to host, the PCD + * interrupt handler won't handle the + * interrupt if host mode is already set. The + * HCD interrupt handler won't get called if + * the HCD state is HALT. This means that the + * interrupt does not get handled and Linux + * complains loudly. + */ + gintmsk.d32 = 0; + gintmsk.b.sofintr = 1; + dwc_modify_reg32(&global_regs->gintmsk, + gintmsk.d32, 0); + pcd_stop(core_if); + /* + * Initialize the Core for Host mode. + */ + hcd_start(core_if); + core_if->op_state = B_HOST; + } + } else { + gotgctl.d32 = 0; + gotgctl.b.hnpreq = 1; + gotgctl.b.devhnpen = 1; + dwc_modify_reg32(&global_regs->gotgctl, + gotgctl.d32, 0); + DWC_DEBUGPL(DBG_ANY, "HNP Failed\n"); + DWC_ERROR("Device Not Connected/Responding\n"); + } + } + if (gotgint.b.hstnegdet) { + /* The disconnect interrupt is set at the same time as + * Host Negotiation Detected. During the mode + * switch all interrupts are cleared so the disconnect + * interrupt handler will not get executed. + */ + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " + "Host Negotiation Detected++ (%s)\n", + (dwc_otg_is_host_mode(core_if)?"Host":"Device")); + if (dwc_otg_is_device_mode(core_if)){ + DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n", core_if->op_state); + hcd_disconnect(core_if); + pcd_start(core_if); + core_if->op_state = A_PERIPHERAL; + } else { + /* + * Need to disable SOF interrupt immediately. When + * switching from device to host, the PCD interrupt + * handler won't handle the interrupt if host mode is + * already set. The HCD interrupt handler won't get + * called if the HCD state is HALT. This means that + * the interrupt does not get handled and Linux + * complains loudly. + */ + gintmsk.d32 = 0; + gintmsk.b.sofintr = 1; + dwc_modify_reg32(&global_regs->gintmsk, + gintmsk.d32, 0); + pcd_stop(core_if); + hcd_start(core_if); + core_if->op_state = A_HOST; + } + } + if (gotgint.b.adevtoutchng) { + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " + "A-Device Timeout Change++\n"); + } + if (gotgint.b.debdone) { + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " + "Debounce Done++\n"); + } + + /* Clear GOTGINT */ + dwc_write_reg32 (&core_if->core_global_regs->gotgint, gotgint.d32); + + return 1; +} + + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) + +void w_conn_id_status_change(void *p) +{ + dwc_otg_core_if_t *core_if = p; + +#else + +void w_conn_id_status_change(struct work_struct *p) +{ + dwc_otg_core_if_t *core_if = container_of(p, dwc_otg_core_if_t, w_conn_id); + +#endif + + + uint32_t count = 0; + gotgctl_data_t gotgctl = { .d32 = 0 }; + + gotgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl); + DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32); + DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts); + + /* B-Device connector (Device Mode) */ + if (gotgctl.b.conidsts) { + /* Wait for switch to device mode. */ + while (!dwc_otg_is_device_mode(core_if)){ + DWC_PRINT("Waiting for Peripheral Mode, Mode=%s\n", + (dwc_otg_is_host_mode(core_if)?"Host":"Peripheral")); + MDELAY(100); + if (++count > 10000) *(uint32_t*)NULL=0; + } + core_if->op_state = B_PERIPHERAL; + dwc_otg_core_init(core_if); + dwc_otg_enable_global_interrupts(core_if); + pcd_start(core_if); + } else { + /* A-Device connector (Host Mode) */ + while (!dwc_otg_is_host_mode(core_if)) { + DWC_PRINT("Waiting for Host Mode, Mode=%s\n", + (dwc_otg_is_host_mode(core_if)?"Host":"Peripheral")); + MDELAY(100); + if (++count > 10000) *(uint32_t*)NULL=0; + } + core_if->op_state = A_HOST; + /* + * Initialize the Core for Host mode. + */ + dwc_otg_core_init(core_if); + dwc_otg_enable_global_interrupts(core_if); + hcd_start(core_if); + } +} + + +/** + * This function handles the Connector ID Status Change Interrupt. It + * reads the OTG Interrupt Register (GOTCTL) to determine whether this + * is a Device to Host Mode transition or a Host Mode to Device + * Transition. + * + * This only occurs when the cable is connected/removed from the PHY + * connector. + * + * @param core_if Programming view of DWC_otg controller. + */ +int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t *core_if) +{ + + /* + * Need to disable SOF interrupt immediately. If switching from device + * to host, the PCD interrupt handler won't handle the interrupt if + * host mode is already set. The HCD interrupt handler won't get + * called if the HCD state is HALT. This means that the interrupt does + * not get handled and Linux complains loudly. + */ + gintmsk_data_t gintmsk = { .d32 = 0 }; + gintsts_data_t gintsts = { .d32 = 0 }; + + gintmsk.b.sofintr = 1; + dwc_modify_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0); + + DWC_DEBUGPL(DBG_CIL, " ++Connector ID Status Change Interrupt++ (%s)\n", + (dwc_otg_is_host_mode(core_if)?"Host":"Device")); + + /* + * Need to schedule a work, as there are possible DELAY function calls + */ + queue_work(core_if->wq_otg, &core_if->w_conn_id); + + /* Set flag and clear interrupt */ + gintsts.b.conidstschng = 1; + dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32); + + return 1; +} + +/** + * This interrupt indicates that a device is initiating the Session + * Request Protocol to request the host to turn on bus power so a new + * session can begin. The handler responds by turning on bus power. If + * the DWC_otg controller is in low power mode, the handler brings the + * controller out of low power mode before turning on bus power. + * + * @param core_if Programming view of DWC_otg controller. + */ +int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t *core_if) +{ + gintsts_data_t gintsts; + +#ifndef DWC_HOST_ONLY + hprt0_data_t hprt0; + DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n"); + + if (dwc_otg_is_device_mode(core_if)) { + DWC_PRINT("SRP: Device mode\n"); + } else { + DWC_PRINT("SRP: Host mode\n"); + + /* Turn on the port power bit. */ + hprt0.d32 = dwc_otg_read_hprt0(core_if); + hprt0.b.prtpwr = 1; + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); + + /* Start the Connection timer. So a message can be displayed + * if connect does not occur within 10 seconds. */ + hcd_session_start(core_if); + } +#endif + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.sessreqintr = 1; + dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32); + + return 1; +} + + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) +void w_wakeup_detected(void *p) +{ + dwc_otg_core_if_t* core_if = p; + +#else + +void w_wakeup_detected(struct work_struct *p) +{ + struct delayed_work *dw = container_of(p, struct delayed_work, work); + dwc_otg_core_if_t *core_if = container_of(dw, dwc_otg_core_if_t, w_wkp); + +#endif + /* + * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms + * so that OPT tests pass with all PHYs). + */ + hprt0_data_t hprt0 = {.d32=0}; +#if 0 + pcgcctl_data_t pcgcctl = {.d32=0}; + /* Restart the Phy Clock */ + pcgcctl.b.stoppclk = 1; + dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, 0); + UDELAY(10); +#endif //0 + hprt0.d32 = dwc_otg_read_hprt0(core_if); + DWC_DEBUGPL(DBG_ANY,"Resume: HPRT0=%0x\n", hprt0.d32); +// MDELAY(70); + hprt0.b.prtres = 0; /* Resume */ + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); + DWC_DEBUGPL(DBG_ANY,"Clear Resume: HPRT0=%0x\n", dwc_read_reg32(core_if->host_if->hprt0)); +} +/** + * This interrupt indicates that the DWC_otg controller has detected a + * resume or remote wakeup sequence. If the DWC_otg controller is in + * low power mode, the handler must brings the controller out of low + * power mode. The controller automatically begins resume + * signaling. The handler schedules a time to stop resume signaling. + */ +int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t *core_if) +{ + gintsts_data_t gintsts; + + DWC_DEBUGPL(DBG_ANY, "++Resume and Remote Wakeup Detected Interrupt++\n"); + + if (dwc_otg_is_device_mode(core_if)) { + dctl_data_t dctl = {.d32=0}; + DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", + dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts)); +#ifdef PARTIAL_POWER_DOWN + if (core_if->hwcfg4.b.power_optimiz) { + pcgcctl_data_t power = {.d32=0}; + + power.d32 = dwc_read_reg32(core_if->pcgcctl); + DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n", power.d32); + + power.b.stoppclk = 0; + dwc_write_reg32(core_if->pcgcctl, power.d32); + + power.b.pwrclmp = 0; + dwc_write_reg32(core_if->pcgcctl, power.d32); + + power.b.rstpdwnmodule = 0; + dwc_write_reg32(core_if->pcgcctl, power.d32); + } +#endif + /* Clear the Remote Wakeup Signalling */ + dctl.b.rmtwkupsig = 1; + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl, + dctl.d32, 0); + + if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) { + core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p); + } + + } else { + pcgcctl_data_t pcgcctl = {.d32=0}; + + /* Restart the Phy Clock */ + pcgcctl.b.stoppclk = 1; + dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, 0); + + queue_delayed_work(core_if->wq_otg, &core_if->w_wkp, ((70 * HZ / 1000) + 1)); + } + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.wkupintr = 1; + dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32); + + return 1; +} + +/** + * This interrupt indicates that a device has been disconnected from + * the root port. + */ +int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t *core_if) +{ + gintsts_data_t gintsts; + + DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n", + (dwc_otg_is_host_mode(core_if)?"Host":"Device"), + op_state_str(core_if)); + +/** @todo Consolidate this if statement. */ +#ifndef DWC_HOST_ONLY + if (core_if->op_state == B_HOST) { + /* If in device mode Disconnect and stop the HCD, then + * start the PCD. */ + hcd_disconnect(core_if); + pcd_start(core_if); + core_if->op_state = B_PERIPHERAL; + } else if (dwc_otg_is_device_mode(core_if)) { + gotgctl_data_t gotgctl = { .d32 = 0 }; + gotgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl); + if (gotgctl.b.hstsethnpen==1) { + /* Do nothing, if HNP in process the OTG + * interrupt "Host Negotiation Detected" + * interrupt will do the mode switch. + */ + } else if (gotgctl.b.devhnpen == 0) { + /* If in device mode Disconnect and stop the HCD, then + * start the PCD. */ + hcd_disconnect(core_if); + pcd_start(core_if); + core_if->op_state = B_PERIPHERAL; + } else { + DWC_DEBUGPL(DBG_ANY,"!a_peripheral && !devhnpen\n"); + } + } else { + if (core_if->op_state == A_HOST) { + /* A-Cable still connected but device disconnected. */ + hcd_disconnect(core_if); + } + } +#endif + + gintsts.d32 = 0; + gintsts.b.disconnect = 1; + dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32); + return 1; +} +/** + * This interrupt indicates that SUSPEND state has been detected on + * the USB. + * + * For HNP the USB Suspend interrupt signals the change from + * "a_peripheral" to "a_host". + * + * When power management is enabled the core will be put in low power + * mode. + */ +int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t *core_if) +{ + dsts_data_t dsts; + gintsts_data_t gintsts; + + DWC_DEBUGPL(DBG_ANY,"USB SUSPEND\n"); + + if (dwc_otg_is_device_mode(core_if)) { + /* Check the Device status register to determine if the Suspend + * state is active. */ + dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); + DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32); + DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d " + "HWCFG4.power Optimize=%d\n", + dsts.b.suspsts, core_if->hwcfg4.b.power_optimiz); + + +#ifdef PARTIAL_POWER_DOWN +/** @todo Add a module parameter for power management. */ + + if (dsts.b.suspsts && core_if->hwcfg4.b.power_optimiz) { + pcgcctl_data_t power = {.d32=0}; + DWC_DEBUGPL(DBG_CIL, "suspend\n"); + + power.b.pwrclmp = 1; + dwc_write_reg32(core_if->pcgcctl, power.d32); + + power.b.rstpdwnmodule = 1; + dwc_modify_reg32(core_if->pcgcctl, 0, power.d32); + + power.b.stoppclk = 1; + dwc_modify_reg32(core_if->pcgcctl, 0, power.d32); + + } else { + DWC_DEBUGPL(DBG_ANY,"disconnect?\n"); + } +#endif + /* PCD callback for suspend. */ + pcd_suspend(core_if); + } else { + if (core_if->op_state == A_PERIPHERAL) { + DWC_DEBUGPL(DBG_ANY,"a_peripheral->a_host\n"); + /* Clear the a_peripheral flag, back to a_host. */ + pcd_stop(core_if); + hcd_start(core_if); + core_if->op_state = A_HOST; + } + } + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.usbsuspend = 1; + dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32); + + return 1; +} + + +/** + * This function returns the Core Interrupt register. + */ +static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t *core_if) +{ + gintsts_data_t gintsts; + gintmsk_data_t gintmsk; + gintmsk_data_t gintmsk_common = {.d32=0}; + gintmsk_common.b.wkupintr = 1; + gintmsk_common.b.sessreqintr = 1; + gintmsk_common.b.conidstschng = 1; + gintmsk_common.b.otgintr = 1; + gintmsk_common.b.modemismatch = 1; + gintmsk_common.b.disconnect = 1; + gintmsk_common.b.usbsuspend = 1; + /** @todo: The port interrupt occurs while in device + * mode. Added code to CIL to clear the interrupt for now! + */ + gintmsk_common.b.portintr = 1; + + gintsts.d32 = dwc_read_reg32(&core_if->core_global_regs->gintsts); + gintmsk.d32 = dwc_read_reg32(&core_if->core_global_regs->gintmsk); +#ifdef DEBUG + /* if any common interrupts set */ + if (gintsts.d32 & gintmsk_common.d32) { + DWC_DEBUGPL(DBG_ANY, "gintsts=%08x gintmsk=%08x\n", + gintsts.d32, gintmsk.d32); + } +#endif + + return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32); + +} + +/** + * Common interrupt handler. + * + * The common interrupts are those that occur in both Host and Device mode. + * This handler handles the following interrupts: + * - Mode Mismatch Interrupt + * - Disconnect Interrupt + * - OTG Interrupt + * - Connector ID Status Change Interrupt + * - Session Request Interrupt. + * - Resume / Remote Wakeup Detected Interrupt. + * + */ +int32_t dwc_otg_handle_common_intr(dwc_otg_core_if_t *core_if) +{ + int retval = 0; + gintsts_data_t gintsts; + + gintsts.d32 = dwc_otg_read_common_intr(core_if); + + if (gintsts.b.modemismatch) { + retval |= dwc_otg_handle_mode_mismatch_intr(core_if); + } + if (gintsts.b.otgintr) { + retval |= dwc_otg_handle_otg_intr(core_if); + } + if (gintsts.b.conidstschng) { + retval |= dwc_otg_handle_conn_id_status_change_intr(core_if); + } + if (gintsts.b.disconnect) { + retval |= dwc_otg_handle_disconnect_intr(core_if); + } + if (gintsts.b.sessreqintr) { + retval |= dwc_otg_handle_session_req_intr(core_if); + } + if (gintsts.b.wkupintr) { + retval |= dwc_otg_handle_wakeup_detected_intr(core_if); + } + if (gintsts.b.usbsuspend) { + retval |= dwc_otg_handle_usb_suspend_intr(core_if); + } + if (gintsts.b.portintr && dwc_otg_is_device_mode(core_if)) { + /* The port interrupt occurs while in device mode with HPRT0 + * Port Enable/Disable. + */ + gintsts.d32 = 0; + gintsts.b.portintr = 1; + dwc_write_reg32(&core_if->core_global_regs->gintsts, + gintsts.d32); + retval |= 1; + + } + + S3C2410X_CLEAR_EINTPEND(); + + return retval; +} diff --git a/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_driver.c b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_driver.c new file mode 100644 index 0000000000..87d3fbbbc2 --- /dev/null +++ b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_driver.c @@ -0,0 +1,1265 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_driver.c $ + * $Revision: 1.7 $ + * $Date: 2008-11-21 05:39:15 $ + * $Change: 791271 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and + * redistribute this Software in source and binary forms, with or without + * modification, provided that redistributions of source code must retain this + * notice. You may not view, use, disclose, copy or distribute this file or + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * ========================================================================== */ + +/** @file + * The dwc_otg_driver module provides the initialization and cleanup entry + * points for the DWC_otg driver. This module will be dynamically installed + * after Linux is booted using the insmod command. When the module is + * installed, the dwc_otg_driver_init function is called. When the module is + * removed (using rmmod), the dwc_otg_driver_cleanup function is called. + * + * This module also defines a data structure for the dwc_otg_driver, which is + * used in conjunction with the standard ARM platform_device structure. These + * structures allow the OTG driver to comply with the standard Linux driver + * model in which devices and drivers are registered with a bus driver. This + * has the benefit that Linux can expose attributes of the driver and device + * in its special sysfs file system. Users can then read or write files in + * this file system to perform diagnostics on the driver components or the + * device. + */ + +#include +#include +#include +#include +#include +#include +#include +#include /* permission constants */ +#include +#include + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) +# include +#endif + +#include + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) +# include +#endif + +#include "linux/dwc_otg_plat.h" +#include "dwc_otg_attr.h" +#include "dwc_otg_driver.h" +#include "dwc_otg_cil.h" +#include "dwc_otg_pcd.h" +#include "dwc_otg_hcd.h" + +#define DWC_DRIVER_VERSION "2.72a 24-JUN-2008" +#define DWC_DRIVER_DESC "HS OTG USB Controller driver" + +static const char dwc_driver_name[] = "dwc_otg"; + +/*-------------------------------------------------------------------------*/ +/* Encapsulate the module parameter settings */ + +static dwc_otg_core_params_t dwc_otg_module_params = { + .opt = -1, + .otg_cap = -1, + .dma_enable = -1, + .dma_desc_enable = -1, + .dma_burst_size = -1, + .speed = -1, + .host_support_fs_ls_low_power = -1, + .host_ls_low_power_phy_clk = -1, + .enable_dynamic_fifo = -1, + .data_fifo_size = -1, + .dev_rx_fifo_size = -1, + .dev_nperio_tx_fifo_size = -1, + .dev_perio_tx_fifo_size = { + /* dev_perio_tx_fifo_size_1 */ + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1 + /* 15 */ + }, + .host_rx_fifo_size = -1, + .host_nperio_tx_fifo_size = -1, + .host_perio_tx_fifo_size = -1, + .max_transfer_size = -1, + .max_packet_count = -1, + .host_channels = -1, + .dev_endpoints = -1, + .phy_type = -1, + .phy_utmi_width = -1, + .phy_ulpi_ddr = -1, + .phy_ulpi_ext_vbus = -1, + .i2c_enable = -1, + .ulpi_fs_ls = -1, + .ts_dline = -1, + .en_multiple_tx_fifo = -1, + .dev_tx_fifo_size = { + /* dev_tx_fifo_size */ + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1 + /* 15 */ + }, + .thr_ctl = -1, + .tx_thr_length = -1, + .rx_thr_length = -1, + .pti_enable = -1, + .mpi_enable = -1, +}; + +/** + * This function shows the Driver Version. + */ +static ssize_t version_show(struct device_driver *dev, char *buf) +{ + return snprintf(buf, sizeof(DWC_DRIVER_VERSION)+2, "%s\n", + DWC_DRIVER_VERSION); +} +static DRIVER_ATTR(version, S_IRUGO, version_show, NULL); + +/** + * Global Debug Level Mask. + */ +uint32_t g_dbg_lvl = 0; /* OFF */ + +/** + * This function shows the driver Debug Level. + */ +static ssize_t dbg_level_show(struct device_driver *drv, char *buf) +{ + return sprintf(buf, "0x%0x\n", g_dbg_lvl); +} + +/** + * This function stores the driver Debug Level. + */ +static ssize_t dbg_level_store(struct device_driver *drv, const char *buf, + size_t count) +{ + g_dbg_lvl = simple_strtoul(buf, NULL, 16); + return count; +} +static DRIVER_ATTR(debuglevel, S_IRUGO|S_IWUSR, dbg_level_show, dbg_level_store); + +/** + * This function is called during module intialization to verify that + * the module parameters are in a valid state. + */ +static int check_parameters(dwc_otg_core_if_t *core_if) +{ + int i; + int retval = 0; + +/* Checks if the parameter is outside of its valid range of values */ +#define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \ + ((dwc_otg_module_params._param_ < (_low_)) || \ + (dwc_otg_module_params._param_ > (_high_))) + +/* If the parameter has been set by the user, check that the parameter value is + * within the value range of values. If not, report a module error. */ +#define DWC_OTG_PARAM_ERR(_param_, _low_, _high_, _string_) \ + do { \ + if (dwc_otg_module_params._param_ != -1) { \ + if (DWC_OTG_PARAM_TEST(_param_, (_low_), (_high_))) { \ + DWC_ERROR("`%d' invalid for parameter `%s'\n", \ + dwc_otg_module_params._param_, _string_); \ + dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \ + retval++; \ + } \ + } \ + } while (0) + + DWC_OTG_PARAM_ERR(opt,0,1,"opt"); + DWC_OTG_PARAM_ERR(otg_cap,0,2,"otg_cap"); + DWC_OTG_PARAM_ERR(dma_enable,0,1,"dma_enable"); + DWC_OTG_PARAM_ERR(dma_desc_enable,0,1,"dma_desc_enable"); + DWC_OTG_PARAM_ERR(speed,0,1,"speed"); + DWC_OTG_PARAM_ERR(host_support_fs_ls_low_power,0,1,"host_support_fs_ls_low_power"); + DWC_OTG_PARAM_ERR(host_ls_low_power_phy_clk,0,1,"host_ls_low_power_phy_clk"); + DWC_OTG_PARAM_ERR(enable_dynamic_fifo,0,1,"enable_dynamic_fifo"); + DWC_OTG_PARAM_ERR(data_fifo_size,32,32768,"data_fifo_size"); + DWC_OTG_PARAM_ERR(dev_rx_fifo_size,16,32768,"dev_rx_fifo_size"); + DWC_OTG_PARAM_ERR(dev_nperio_tx_fifo_size,16,32768,"dev_nperio_tx_fifo_size"); + DWC_OTG_PARAM_ERR(host_rx_fifo_size,16,32768,"host_rx_fifo_size"); + DWC_OTG_PARAM_ERR(host_nperio_tx_fifo_size,16,32768,"host_nperio_tx_fifo_size"); + DWC_OTG_PARAM_ERR(host_perio_tx_fifo_size,16,32768,"host_perio_tx_fifo_size"); + DWC_OTG_PARAM_ERR(max_transfer_size,2047,524288,"max_transfer_size"); + DWC_OTG_PARAM_ERR(max_packet_count,15,511,"max_packet_count"); + DWC_OTG_PARAM_ERR(host_channels,1,16,"host_channels"); + DWC_OTG_PARAM_ERR(dev_endpoints,1,15,"dev_endpoints"); + DWC_OTG_PARAM_ERR(phy_type,0,2,"phy_type"); + DWC_OTG_PARAM_ERR(phy_ulpi_ddr,0,1,"phy_ulpi_ddr"); + DWC_OTG_PARAM_ERR(phy_ulpi_ext_vbus,0,1,"phy_ulpi_ext_vbus"); + DWC_OTG_PARAM_ERR(i2c_enable,0,1,"i2c_enable"); + DWC_OTG_PARAM_ERR(ulpi_fs_ls,0,1,"ulpi_fs_ls"); + DWC_OTG_PARAM_ERR(ts_dline,0,1,"ts_dline"); + + if (dwc_otg_module_params.dma_burst_size != -1) { + if (DWC_OTG_PARAM_TEST(dma_burst_size,1,1) && + DWC_OTG_PARAM_TEST(dma_burst_size,4,4) && + DWC_OTG_PARAM_TEST(dma_burst_size,8,8) && + DWC_OTG_PARAM_TEST(dma_burst_size,16,16) && + DWC_OTG_PARAM_TEST(dma_burst_size,32,32) && + DWC_OTG_PARAM_TEST(dma_burst_size,64,64) && + DWC_OTG_PARAM_TEST(dma_burst_size,128,128) && + DWC_OTG_PARAM_TEST(dma_burst_size,256,256)) { + DWC_ERROR("`%d' invalid for parameter `dma_burst_size'\n", + dwc_otg_module_params.dma_burst_size); + dwc_otg_module_params.dma_burst_size = 32; + retval++; + } + + { + uint8_t brst_sz = 0; + while(dwc_otg_module_params.dma_burst_size > 1) { + brst_sz ++; + dwc_otg_module_params.dma_burst_size >>= 1; + } + dwc_otg_module_params.dma_burst_size = brst_sz; + } + } + + if (dwc_otg_module_params.phy_utmi_width != -1) { + if (DWC_OTG_PARAM_TEST(phy_utmi_width, 8, 8) && + DWC_OTG_PARAM_TEST(phy_utmi_width, 16, 16)) { + DWC_ERROR("`%d' invalid for parameter `phy_utmi_width'\n", + dwc_otg_module_params.phy_utmi_width); + dwc_otg_module_params.phy_utmi_width = 16; + retval++; + } + } + + for (i = 0; i < 15; i++) { + /** @todo should be like above */ + //DWC_OTG_PARAM_ERR(dev_perio_tx_fifo_size[i], 4, 768, "dev_perio_tx_fifo_size"); + if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) { + if (DWC_OTG_PARAM_TEST(dev_perio_tx_fifo_size[i], 4, 768)) { + DWC_ERROR("`%d' invalid for parameter `%s_%d'\n", + dwc_otg_module_params.dev_perio_tx_fifo_size[i], "dev_perio_tx_fifo_size", i); + dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default; + retval++; + } + } + } + + DWC_OTG_PARAM_ERR(en_multiple_tx_fifo, 0, 1, "en_multiple_tx_fifo"); + + for (i = 0; i < 15; i++) { + /** @todo should be like above */ + //DWC_OTG_PARAM_ERR(dev_tx_fifo_size[i], 4, 768, "dev_tx_fifo_size"); + if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) { + if (DWC_OTG_PARAM_TEST(dev_tx_fifo_size[i], 4, 768)) { + DWC_ERROR("`%d' invalid for parameter `%s_%d'\n", + dwc_otg_module_params.dev_tx_fifo_size[i], "dev_tx_fifo_size", i); + dwc_otg_module_params.dev_tx_fifo_size[i] = dwc_param_dev_tx_fifo_size_default; + retval++; + } + } + } + + DWC_OTG_PARAM_ERR(thr_ctl, 0, 7, "thr_ctl"); + DWC_OTG_PARAM_ERR(tx_thr_length, 8, 128, "tx_thr_length"); + DWC_OTG_PARAM_ERR(rx_thr_length, 8, 128, "rx_thr_length"); + + DWC_OTG_PARAM_ERR(pti_enable,0,1,"pti_enable"); + DWC_OTG_PARAM_ERR(mpi_enable,0,1,"mpi_enable"); + + /* At this point, all module parameters that have been set by the user + * are valid, and those that have not are left unset. Now set their + * default values and/or check the parameters against the hardware + * configurations of the OTG core. */ + +/* This sets the parameter to the default value if it has not been set by the + * user */ +#define DWC_OTG_PARAM_SET_DEFAULT(_param_) \ + ({ \ + int changed = 1; \ + if (dwc_otg_module_params._param_ == -1) { \ + changed = 0; \ + dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \ + } \ + changed; \ + }) + +/* This checks the macro agains the hardware configuration to see if it is + * valid. It is possible that the default value could be invalid. In this + * case, it will report a module error if the user touched the parameter. + * Otherwise it will adjust the value without any error. */ +#define DWC_OTG_PARAM_CHECK_VALID(_param_, _str_, _is_valid_, _set_valid_) \ + ({ \ + int changed = DWC_OTG_PARAM_SET_DEFAULT(_param_); \ + int error = 0; \ + if (!(_is_valid_)) { \ + if (changed) { \ + DWC_ERROR("`%d' invalid for parameter `%s'. Check HW configuration.\n", dwc_otg_module_params._param_, _str_); \ + error = 1; \ + } \ + dwc_otg_module_params._param_ = (_set_valid_); \ + } \ + error; \ + }) + + /* OTG Cap */ + retval += DWC_OTG_PARAM_CHECK_VALID(otg_cap, "otg_cap", + ({ + int valid; + valid = 1; + switch (dwc_otg_module_params.otg_cap) { + case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE: + if (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) + valid = 0; + break; + case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE: + if ((core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) && + (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) && + (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) && + (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) { + valid = 0; + } + break; + case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE: + /* always valid */ + break; + } + valid; + }), + (((core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) || + (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) || + (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) || + (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ? + DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE : + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE)); + + retval += DWC_OTG_PARAM_CHECK_VALID(dma_enable, "dma_enable", + ((dwc_otg_module_params.dma_enable == 1) && (core_if->hwcfg2.b.architecture == 0)) ? 0 : 1, + 0); + + retval += DWC_OTG_PARAM_CHECK_VALID(dma_desc_enable, "dma_desc_enable", + ((dwc_otg_module_params.dma_desc_enable == 1) && + ((dwc_otg_module_params.dma_enable == 0) || (core_if->hwcfg4.b.desc_dma == 0))) ? 0 : 1, + 0); + + retval += DWC_OTG_PARAM_CHECK_VALID(opt, "opt", 1, 0); + + DWC_OTG_PARAM_SET_DEFAULT(dma_burst_size); + + retval += DWC_OTG_PARAM_CHECK_VALID(host_support_fs_ls_low_power, + "host_support_fs_ls_low_power", + 1, 0); + + retval += DWC_OTG_PARAM_CHECK_VALID(enable_dynamic_fifo, + "enable_dynamic_fifo", + ((dwc_otg_module_params.enable_dynamic_fifo == 0) || + (core_if->hwcfg2.b.dynamic_fifo == 1)), 0); + + retval += DWC_OTG_PARAM_CHECK_VALID(data_fifo_size, + "data_fifo_size", + (dwc_otg_module_params.data_fifo_size <= core_if->hwcfg3.b.dfifo_depth), + core_if->hwcfg3.b.dfifo_depth); + + retval += DWC_OTG_PARAM_CHECK_VALID(dev_rx_fifo_size, + "dev_rx_fifo_size", + (dwc_otg_module_params.dev_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)), + dwc_read_reg32(&core_if->core_global_regs->grxfsiz)); + + retval += DWC_OTG_PARAM_CHECK_VALID(dev_nperio_tx_fifo_size, + "dev_nperio_tx_fifo_size", + (dwc_otg_module_params.dev_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)), + (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)); + + retval += DWC_OTG_PARAM_CHECK_VALID(host_rx_fifo_size, + "host_rx_fifo_size", + (dwc_otg_module_params.host_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)), + dwc_read_reg32(&core_if->core_global_regs->grxfsiz)); + + retval += DWC_OTG_PARAM_CHECK_VALID(host_nperio_tx_fifo_size, + "host_nperio_tx_fifo_size", + (dwc_otg_module_params.host_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)), + (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)); + + retval += DWC_OTG_PARAM_CHECK_VALID(host_perio_tx_fifo_size, + "host_perio_tx_fifo_size", + (dwc_otg_module_params.host_perio_tx_fifo_size <= ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16))), + ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16))); + + retval += DWC_OTG_PARAM_CHECK_VALID(max_transfer_size, + "max_transfer_size", + (dwc_otg_module_params.max_transfer_size < (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))), + ((1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1)); + + retval += DWC_OTG_PARAM_CHECK_VALID(max_packet_count, + "max_packet_count", + (dwc_otg_module_params.max_packet_count < (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))), + ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1)); + + retval += DWC_OTG_PARAM_CHECK_VALID(host_channels, + "host_channels", + (dwc_otg_module_params.host_channels <= (core_if->hwcfg2.b.num_host_chan + 1)), + (core_if->hwcfg2.b.num_host_chan + 1)); + + retval += DWC_OTG_PARAM_CHECK_VALID(dev_endpoints, + "dev_endpoints", + (dwc_otg_module_params.dev_endpoints <= (core_if->hwcfg2.b.num_dev_ep)), + core_if->hwcfg2.b.num_dev_ep); + +/* + * Define the following to disable the FS PHY Hardware checking. This is for + * internal testing only. + * + * #define NO_FS_PHY_HW_CHECKS + */ + +#ifdef NO_FS_PHY_HW_CHECKS + retval += DWC_OTG_PARAM_CHECK_VALID(phy_type, + "phy_type", 1, 0); +#else + retval += DWC_OTG_PARAM_CHECK_VALID(phy_type, + "phy_type", + ({ + int valid = 0; + if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_UTMI) && + ((core_if->hwcfg2.b.hs_phy_type == 1) || + (core_if->hwcfg2.b.hs_phy_type == 3))) { + valid = 1; + } + else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_ULPI) && + ((core_if->hwcfg2.b.hs_phy_type == 2) || + (core_if->hwcfg2.b.hs_phy_type == 3))) { + valid = 1; + } + else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) && + (core_if->hwcfg2.b.fs_phy_type == 1)) { + valid = 1; + } + valid; + }), + ({ + int set = DWC_PHY_TYPE_PARAM_FS; + if (core_if->hwcfg2.b.hs_phy_type) { + if ((core_if->hwcfg2.b.hs_phy_type == 3) || + (core_if->hwcfg2.b.hs_phy_type == 1)) { + set = DWC_PHY_TYPE_PARAM_UTMI; + } + else { + set = DWC_PHY_TYPE_PARAM_ULPI; + } + } + set; + })); +#endif + + retval += DWC_OTG_PARAM_CHECK_VALID(speed, "speed", + (dwc_otg_module_params.speed == 0) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1, + dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS ? 1 : 0); + + retval += DWC_OTG_PARAM_CHECK_VALID(host_ls_low_power_phy_clk, + "host_ls_low_power_phy_clk", + ((dwc_otg_module_params.host_ls_low_power_phy_clk == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1), + ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ : DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ)); + + DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ddr); + DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ext_vbus); + DWC_OTG_PARAM_SET_DEFAULT(phy_utmi_width); + DWC_OTG_PARAM_SET_DEFAULT(ulpi_fs_ls); + DWC_OTG_PARAM_SET_DEFAULT(ts_dline); + +#ifdef NO_FS_PHY_HW_CHECKS + retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable, "i2c_enable", 1, 0); +#else + retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable, + "i2c_enable", + (dwc_otg_module_params.i2c_enable == 1) && (core_if->hwcfg3.b.i2c == 0) ? 0 : 1, + 0); +#endif + + for (i = 0; i < 15; i++) { + int changed = 1; + int error = 0; + + if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] == -1) { + changed = 0; + dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default; + } + if (!(dwc_otg_module_params.dev_perio_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) { + if (changed) { + DWC_ERROR("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", dwc_otg_module_params.dev_perio_tx_fifo_size[i], i); + error = 1; + } + dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]); + } + retval += error; + } + + retval += DWC_OTG_PARAM_CHECK_VALID(en_multiple_tx_fifo, "en_multiple_tx_fifo", + ((dwc_otg_module_params.en_multiple_tx_fifo == 1) && (core_if->hwcfg4.b.ded_fifo_en == 0)) ? 0 : 1, + 0); + + for (i = 0; i < 15; i++) { + int changed = 1; + int error = 0; + + if (dwc_otg_module_params.dev_tx_fifo_size[i] == -1) { + changed = 0; + dwc_otg_module_params.dev_tx_fifo_size[i] = dwc_param_dev_tx_fifo_size_default; + } + if (!(dwc_otg_module_params.dev_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) { + if (changed) { + DWC_ERROR("%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", dwc_otg_module_params.dev_tx_fifo_size[i], i); + error = 1; + } + dwc_otg_module_params.dev_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]); + } + retval += error; + } + + retval += DWC_OTG_PARAM_CHECK_VALID(thr_ctl, "thr_ctl", + ((dwc_otg_module_params.thr_ctl != 0) && ((dwc_otg_module_params.dma_enable == 0) || (core_if->hwcfg4.b.ded_fifo_en == 0))) ? 0 : 1, + 0); + + DWC_OTG_PARAM_SET_DEFAULT(tx_thr_length); + DWC_OTG_PARAM_SET_DEFAULT(rx_thr_length); + + retval += DWC_OTG_PARAM_CHECK_VALID(pti_enable, "pti_enable", + ((dwc_otg_module_params.pti_enable == 0) || ((dwc_otg_module_params.pti_enable == 1) && (core_if->snpsid >= 0x4F54272A))) ? 1 : 0, + 0); + + retval += DWC_OTG_PARAM_CHECK_VALID(mpi_enable, "mpi_enable", + ((dwc_otg_module_params.mpi_enable == 0) || ((dwc_otg_module_params.mpi_enable == 1) && (core_if->hwcfg2.b.multi_proc_int == 1))) ? 1 : 0, + 0); + return retval; +} + +/** + * This function is the top level interrupt handler for the Common + * (Device and host modes) interrupts. + */ +static irqreturn_t dwc_otg_common_irq(int irq, void *dev +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) + , struct pt_regs *r +#endif + ) +{ + dwc_otg_device_t *otg_dev = dev; + int32_t retval = IRQ_NONE; + + retval = dwc_otg_handle_common_intr(otg_dev->core_if); + return IRQ_RETVAL(retval); +} + +/** + * This function is called when a platform_device is unregistered with the + * dwc_otg_driver. This happens, for example, when the rmmod command is + * executed. The device may or may not be electrically present. If it is + * present, the driver stops device processing. Any resources used on behalf + * of this device are freed. + * + * @param[in] pdev + */ +static int dwc_otg_driver_remove(struct platform_device *pdev) +{ + dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); + DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, pdev); + + if (!otg_dev) { + /* Memory allocation for the dwc_otg_device failed. */ + DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__); + return 0; + } + + /* + * Free the IRQ + */ + if (otg_dev->common_irq_installed) { + free_irq(otg_dev->irq, otg_dev); + } + +#ifndef DWC_DEVICE_ONLY + if (otg_dev->hcd) { + dwc_otg_hcd_remove(&pdev->dev); + } else { + DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__); + return 0; + } +#endif + +#ifndef DWC_HOST_ONLY + if (otg_dev->pcd) { + dwc_otg_pcd_remove(&pdev->dev); + } +#endif + if (otg_dev->core_if) { + dwc_otg_cil_remove(otg_dev->core_if); + } + + /* + * Remove the device attributes + */ + dwc_otg_attr_remove(otg_dev->parent); + + /* Disable USB port */ + dwc_write_reg32((uint32_t *)((uint8_t *)otg_dev->base + 0xe00), 0xf); + + /* + * Return the memory. + */ + if (otg_dev->base) { + iounmap(otg_dev->base); + } + + if (otg_dev->phys_addr != 0) { + release_mem_region(otg_dev->phys_addr, otg_dev->base_len); + } + + kfree(otg_dev); + + /* + * Clear the drvdata pointer. + */ + platform_set_drvdata(pdev, NULL); + + return 0; +} + +/** + * This function is called when an platform_device is bound to a + * dwc_otg_driver. It creates the driver components required to + * control the device (CIL, HCD, and PCD) and it initializes the + * device. The driver components are stored in a dwc_otg_device + * structure. A reference to the dwc_otg_device is saved in the + * platform_device. This allows the driver to access the dwc_otg_device + * structure on subsequent calls to driver methods for this device. + * + * @param[in] pdev platform_device definition + */ +static int dwc_otg_driver_probe(struct platform_device *pdev) +{ + int retval = 0; + uint32_t snpsid; + dwc_otg_device_t *otg_dev; + struct resource *res; + + dev_dbg(&pdev->dev, "dwc_otg_driver_probe(%p)\n", pdev); + + otg_dev= kzalloc(sizeof(dwc_otg_device_t), GFP_KERNEL); + if (!otg_dev) { + dev_err(&pdev->dev, "kmalloc of dwc_otg_device failed\n"); + retval = -ENOMEM; + goto fail; + } + + otg_dev->reg_offset = 0xFFFFFFFF; + + /* + * Retrieve the memory and IRQ resources. + */ + otg_dev->irq = platform_get_irq(pdev, 0); + if (otg_dev->irq <= 0) { + dev_err(&pdev->dev, "no device irq\n"); + retval = -EINVAL; + goto fail; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(&pdev->dev, "no CSR address\n"); + retval = -EINVAL; + goto fail; + } + + otg_dev->parent = &pdev->dev; + otg_dev->phys_addr = res->start; + otg_dev->base_len = res->end - res->start + 1; + if (request_mem_region(otg_dev->phys_addr, + otg_dev->base_len, + dwc_driver_name) == NULL) { + dev_err(&pdev->dev, "request_mem_region failed\n"); + retval = -EBUSY; + goto fail; + } + + /* + * Map the DWC_otg Core memory into virtual address space. + */ + otg_dev->base = ioremap(otg_dev->phys_addr, otg_dev->base_len); + if (!otg_dev->base) { + dev_err(&pdev->dev, "ioremap() failed\n"); + retval = -ENOMEM; + goto fail; + } + dev_dbg(&pdev->dev, "mapped base=0x%08x\n", (unsigned) otg_dev->base); + + /* Enable USB Port */ + dwc_write_reg32((uint32_t *)((uint8_t *)otg_dev->base + 0xe00), 0); + + /* + * Attempt to ensure this device is really a DWC_otg Controller. + * Read and verify the SNPSID register contents. The value should be + * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX". + */ + snpsid = dwc_read_reg32((uint32_t *)((uint8_t *)otg_dev->base + 0x40)); + + if ((snpsid & 0xFFFFF000) != OTG_CORE_REV_2_00) { + dev_err(&pdev->dev, "Bad value for SNPSID: 0x%08x\n", snpsid); + retval = -EINVAL; + goto fail; + } + + DWC_PRINT("Core Release: %x.%x%x%x\n", + (snpsid >> 12 & 0xF), + (snpsid >> 8 & 0xF), + (snpsid >> 4 & 0xF), + (snpsid & 0xF)); + + /* + * Initialize driver data to point to the global DWC_otg + * Device structure. + */ + platform_set_drvdata(pdev, otg_dev); + dev_dbg(&pdev->dev, "dwc_otg_device=0x%p\n", otg_dev); + + + otg_dev->core_if = dwc_otg_cil_init(otg_dev->base, + &dwc_otg_module_params); + + otg_dev->core_if->snpsid = snpsid; + + if (!otg_dev->core_if) { + dev_err(&pdev->dev, "CIL initialization failed!\n"); + retval = -ENOMEM; + goto fail; + } + + /* + * Validate parameter values. + */ + if (check_parameters(otg_dev->core_if)) { + retval = -EINVAL; + goto fail; + } + + /* + * Create Device Attributes in sysfs + */ + dwc_otg_attr_create(&pdev->dev); + + /* + * Disable the global interrupt until all the interrupt + * handlers are installed. + */ + dwc_otg_disable_global_interrupts(otg_dev->core_if); + + /* + * Install the interrupt handler for the common interrupts before + * enabling common interrupts in core_init below. + */ + DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", + otg_dev->irq); + retval = request_irq(otg_dev->irq, dwc_otg_common_irq, + IRQF_SHARED, "dwc_otg", otg_dev); + if (retval) { + DWC_ERROR("request of irq%d failed\n", otg_dev->irq); + retval = -EBUSY; + goto fail; + } else { + otg_dev->common_irq_installed = 1; + } + + /* + * Initialize the DWC_otg core. + */ + dwc_otg_core_init(otg_dev->core_if); + +#ifndef DWC_HOST_ONLY + /* + * Initialize the PCD + */ + retval = dwc_otg_pcd_init(&pdev->dev); + if (retval != 0) { + DWC_ERROR("dwc_otg_pcd_init failed\n"); + otg_dev->pcd = NULL; + goto fail; + } +#endif +#ifndef DWC_DEVICE_ONLY + /* + * Initialize the HCD + */ + retval = dwc_otg_hcd_init(&pdev->dev); + if (retval != 0) { + DWC_ERROR("dwc_otg_hcd_init failed\n"); + otg_dev->hcd = NULL; + goto fail; + } +#endif + + /* + * Enable the global interrupt after all the interrupt + * handlers are installed. + */ + dwc_otg_enable_global_interrupts(otg_dev->core_if); + + return 0; + + fail: + dwc_otg_driver_remove(pdev); + return retval; +} + +/** + * This structure defines the methods to be called by a bus driver + * during the lifecycle of a device on that bus. Both drivers and + * devices are registered with a bus driver. The bus driver matches + * devices to drivers based on information in the device and driver + * structures. + * + * The probe function is called when the bus driver matches a device + * to this driver. The remove function is called when a device is + * unregistered with the bus driver. + */ +static struct platform_driver dwc_otg_driver = { + .driver = { + .name = (char *)dwc_driver_name, + }, + .probe = dwc_otg_driver_probe, + .remove = dwc_otg_driver_remove, +}; + +/** + * This function is called when the dwc_otg_driver is installed with the + * insmod command. It registers the dwc_otg_driver structure with the + * appropriate bus driver. This will cause the dwc_otg_driver_probe function + * to be called. In addition, the bus driver will automatically expose + * attributes defined for the device and driver in the special sysfs file + * system. + * + * @return + */ +static int __init dwc_otg_driver_init(void) +{ + int retval = 0; + int error; + + printk(KERN_INFO "%s: version %s\n", dwc_driver_name, DWC_DRIVER_VERSION); + + retval = platform_driver_register(&dwc_otg_driver); + if (retval) { + printk(KERN_ERR "%s retval=%d\n", __func__, retval); + return retval; + } + + error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_version); + error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel); + + return retval; +} +module_init(dwc_otg_driver_init); + +/** + * This function is called when the driver is removed from the kernel + * with the rmmod command. The driver unregisters itself with its bus + * driver. + * + */ +static void __exit dwc_otg_driver_cleanup(void) +{ + printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n"); + + driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel); + driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version); + + platform_driver_unregister(&dwc_otg_driver); + + printk(KERN_INFO "%s module removed\n", dwc_driver_name); +} +module_exit(dwc_otg_driver_cleanup); + +MODULE_DESCRIPTION(DWC_DRIVER_DESC); +MODULE_AUTHOR("Synopsys Inc."); +MODULE_LICENSE("GPL"); + +module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444); +MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None"); +module_param_named(opt, dwc_otg_module_params.opt, int, 0444); +MODULE_PARM_DESC(opt, "OPT Mode"); +module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444); +MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled"); + +module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int, 0444); +MODULE_PARM_DESC(dma_desc_enable, "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled"); + +module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int, 0444); +MODULE_PARM_DESC(dma_burst_size, "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256"); +module_param_named(speed, dwc_otg_module_params.speed, int, 0444); +MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed"); +module_param_named(host_support_fs_ls_low_power, dwc_otg_module_params.host_support_fs_ls_low_power, int, 0444); +MODULE_PARM_DESC(host_support_fs_ls_low_power, "Support Low Power w/FS or LS 0=Support 1=Don't Support"); +module_param_named(host_ls_low_power_phy_clk, dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444); +MODULE_PARM_DESC(host_ls_low_power_phy_clk, "Low Speed Low Power Clock 0=48Mhz 1=6Mhz"); +module_param_named(enable_dynamic_fifo, dwc_otg_module_params.enable_dynamic_fifo, int, 0444); +MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing"); +module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int, 0444); +MODULE_PARM_DESC(data_fifo_size, "Total number of words in the data FIFO memory 32-32768"); +module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size, int, 0444); +MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768"); +module_param_named(dev_nperio_tx_fifo_size, dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444); +MODULE_PARM_DESC(dev_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768"); +module_param_named(dev_perio_tx_fifo_size_1, dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444); +MODULE_PARM_DESC(dev_perio_tx_fifo_size_1, "Number of words in the periodic Tx FIFO 4-768"); +module_param_named(dev_perio_tx_fifo_size_2, dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444); +MODULE_PARM_DESC(dev_perio_tx_fifo_size_2, "Number of words in the periodic Tx FIFO 4-768"); +module_param_named(dev_perio_tx_fifo_size_3, dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444); +MODULE_PARM_DESC(dev_perio_tx_fifo_size_3, "Number of words in the periodic Tx FIFO 4-768"); +module_param_named(dev_perio_tx_fifo_size_4, dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444); +MODULE_PARM_DESC(dev_perio_tx_fifo_size_4, "Number of words in the periodic Tx FIFO 4-768"); +module_param_named(dev_perio_tx_fifo_size_5, dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444); +MODULE_PARM_DESC(dev_perio_tx_fifo_size_5, "Number of words in the periodic Tx FIFO 4-768"); +module_param_named(dev_perio_tx_fifo_size_6, dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444); +MODULE_PARM_DESC(dev_perio_tx_fifo_size_6, "Number of words in the periodic Tx FIFO 4-768"); +module_param_named(dev_perio_tx_fifo_size_7, dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444); +MODULE_PARM_DESC(dev_perio_tx_fifo_size_7, "Number of words in the periodic Tx FIFO 4-768"); +module_param_named(dev_perio_tx_fifo_size_8, dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444); +MODULE_PARM_DESC(dev_perio_tx_fifo_size_8, "Number of words in the periodic Tx FIFO 4-768"); +module_param_named(dev_perio_tx_fifo_size_9, dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444); +MODULE_PARM_DESC(dev_perio_tx_fifo_size_9, "Number of words in the periodic Tx FIFO 4-768"); +module_param_named(dev_perio_tx_fifo_size_10, dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444); +MODULE_PARM_DESC(dev_perio_tx_fifo_size_10, "Number of words in the periodic Tx FIFO 4-768"); +module_param_named(dev_perio_tx_fifo_size_11, dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444); +MODULE_PARM_DESC(dev_perio_tx_fifo_size_11, "Number of words in the periodic Tx FIFO 4-768"); +module_param_named(dev_perio_tx_fifo_size_12, dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444); +MODULE_PARM_DESC(dev_perio_tx_fifo_size_12, "Number of words in the periodic Tx FIFO 4-768"); +module_param_named(dev_perio_tx_fifo_size_13, dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444); +MODULE_PARM_DESC(dev_perio_tx_fifo_size_13, "Number of words in the periodic Tx FIFO 4-768"); +module_param_named(dev_perio_tx_fifo_size_14, dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444); +MODULE_PARM_DESC(dev_perio_tx_fifo_size_14, "Number of words in the periodic Tx FIFO 4-768"); +module_param_named(dev_perio_tx_fifo_size_15, dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444); +MODULE_PARM_DESC(dev_perio_tx_fifo_size_15, "Number of words in the periodic Tx FIFO 4-768"); +module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size, int, 0444); +MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768"); +module_param_named(host_nperio_tx_fifo_size, dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444); +MODULE_PARM_DESC(host_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768"); +module_param_named(host_perio_tx_fifo_size, dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444); +MODULE_PARM_DESC(host_perio_tx_fifo_size, "Number of words in the host periodic Tx FIFO 16-32768"); +module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size, int, 0444); +/** @todo Set the max to 512K, modify checks */ +MODULE_PARM_DESC(max_transfer_size, "The maximum transfer size supported in bytes 2047-65535"); +module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count, int, 0444); +MODULE_PARM_DESC(max_packet_count, "The maximum number of packets in a transfer 15-511"); +module_param_named(host_channels, dwc_otg_module_params.host_channels, int, 0444); +MODULE_PARM_DESC(host_channels, "The number of host channel registers to use 1-16"); +module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int, 0444); +MODULE_PARM_DESC(dev_endpoints, "The number of endpoints in addition to EP0 available for device mode 1-15"); +module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444); +MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI"); +module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int, 0444); +MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits"); +module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444); +MODULE_PARM_DESC(phy_ulpi_ddr, "ULPI at double or single data rate 0=Single 1=Double"); +module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus, int, 0444); +MODULE_PARM_DESC(phy_ulpi_ext_vbus, "ULPI PHY using internal or external vbus 0=Internal"); +module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444); +MODULE_PARM_DESC(i2c_enable, "FS PHY Interface"); +module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444); +MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only"); +module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444); +MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs"); +module_param_named(debug, g_dbg_lvl, int, 0444); +MODULE_PARM_DESC(debug, ""); + +module_param_named(en_multiple_tx_fifo, dwc_otg_module_params.en_multiple_tx_fifo, int, 0444); +MODULE_PARM_DESC(en_multiple_tx_fifo, "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled"); +module_param_named(dev_tx_fifo_size_1, dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444); +MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768"); +module_param_named(dev_tx_fifo_size_2, dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444); +MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768"); +module_param_named(dev_tx_fifo_size_3, dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444); +MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768"); +module_param_named(dev_tx_fifo_size_4, dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444); +MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768"); +module_param_named(dev_tx_fifo_size_5, dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444); +MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768"); +module_param_named(dev_tx_fifo_size_6, dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444); +MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768"); +module_param_named(dev_tx_fifo_size_7, dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444); +MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768"); +module_param_named(dev_tx_fifo_size_8, dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444); +MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768"); +module_param_named(dev_tx_fifo_size_9, dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444); +MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768"); +module_param_named(dev_tx_fifo_size_10, dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444); +MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768"); +module_param_named(dev_tx_fifo_size_11, dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444); +MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768"); +module_param_named(dev_tx_fifo_size_12, dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444); +MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768"); +module_param_named(dev_tx_fifo_size_13, dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444); +MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768"); +module_param_named(dev_tx_fifo_size_14, dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444); +MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768"); +module_param_named(dev_tx_fifo_size_15, dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444); +MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768"); + +module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444); +MODULE_PARM_DESC(thr_ctl, "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled"); +module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int, 0444); +MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs"); +module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int, 0444); +MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs"); + +module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444); +MODULE_PARM_DESC(pti_enable, "Per Transfer Interrupt mode 0=disabled 1=enabled"); + +module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444); +MODULE_PARM_DESC(mpi_enable, "Multiprocessor Interrupt mode 0=disabled 1=enabled"); + +/** @page "Module Parameters" + * + * The following parameters may be specified when starting the module. + * These parameters define how the DWC_otg controller should be + * configured. Parameter values are passed to the CIL initialization + * function dwc_otg_cil_init + * + * Example: modprobe dwc_otg speed=1 otg_cap=1 + * + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +*/ diff --git a/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_driver.h b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_driver.h new file mode 100644 index 0000000000..fd7f0a4b9d --- /dev/null +++ b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_driver.h @@ -0,0 +1,83 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.h $ + * $Revision: 1.2 $ + * $Date: 2008-11-21 05:39:15 $ + * $Change: 1064918 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and + * redistribute this Software in source and binary forms, with or without + * modification, provided that redistributions of source code must retain this + * notice. You may not view, use, disclose, copy or distribute this file or + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * ========================================================================== */ + +#ifndef __DWC_OTG_DRIVER_H__ +#define __DWC_OTG_DRIVER_H__ + +/** @file + * This file contains the interface to the Linux driver. + */ +#include "dwc_otg_cil.h" + +/* Type declarations */ +struct dwc_otg_pcd; +struct dwc_otg_hcd; + +/** + * This structure is a wrapper that encapsulates the driver components used to + * manage a single DWC_otg controller. + */ +typedef struct dwc_otg_device { + /** Base address returned from ioremap() */ + void *base; + + struct device *parent; + + /** Pointer to the core interface structure. */ + dwc_otg_core_if_t *core_if; + + /** Register offset for Diagnostic API. */ + uint32_t reg_offset; + + /** Pointer to the PCD structure. */ + struct dwc_otg_pcd *pcd; + + /** Pointer to the HCD structure. */ + struct dwc_otg_hcd *hcd; + + /** Flag to indicate whether the common IRQ handler is installed. */ + uint8_t common_irq_installed; + + /* Interrupt request number. */ + unsigned int irq; + + /* Physical address of Control and Status registers, used by + * release_mem_region(). + */ + resource_size_t phys_addr; + + /* Length of memory region, used by release_mem_region(). */ + unsigned long base_len; +} dwc_otg_device_t; + +#endif diff --git a/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_hcd.c b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_hcd.c new file mode 100644 index 0000000000..fe643b6460 --- /dev/null +++ b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_hcd.c @@ -0,0 +1,2852 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $ + * $Revision: 1.4 $ + * $Date: 2008-11-21 05:39:15 $ + * $Change: 1064940 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and + * redistribute this Software in source and binary forms, with or without + * modification, provided that redistributions of source code must retain this + * notice. You may not view, use, disclose, copy or distribute this file or + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * ========================================================================== */ +#ifndef DWC_DEVICE_ONLY + +/** + * @file + * + * This file contains the implementation of the HCD. In Linux, the HCD + * implements the hc_driver API. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dwc_otg_driver.h" +#include "dwc_otg_hcd.h" +#include "dwc_otg_regs.h" + +static const char dwc_otg_hcd_name[] = "dwc_otg"; + +static const struct hc_driver dwc_otg_hc_driver = { + + .description = dwc_otg_hcd_name, + .product_desc = "DWC OTG Controller", + .hcd_priv_size = sizeof(dwc_otg_hcd_t), + + .irq = dwc_otg_hcd_irq, + + .flags = HCD_MEMORY | HCD_USB2, + + //.reset = + .start = dwc_otg_hcd_start, + //.suspend = + //.resume = + .stop = dwc_otg_hcd_stop, + + .urb_enqueue = dwc_otg_hcd_urb_enqueue, + .urb_dequeue = dwc_otg_hcd_urb_dequeue, + .endpoint_disable = dwc_otg_hcd_endpoint_disable, + + .get_frame_number = dwc_otg_hcd_get_frame_number, + + .hub_status_data = dwc_otg_hcd_hub_status_data, + .hub_control = dwc_otg_hcd_hub_control, + //.hub_suspend = + //.hub_resume = +}; + +/** + * Work queue function for starting the HCD when A-Cable is connected. + * The dwc_otg_hcd_start() must be called in a process context. + */ +static void hcd_start_func( +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) + void *_vp +#else + struct work_struct *_work +#endif + ) +{ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) + struct usb_hcd *usb_hcd = (struct usb_hcd *)_vp; +#else + struct delayed_work *dw = container_of(_work, struct delayed_work, work); + struct dwc_otg_hcd *otg_hcd = container_of(dw, struct dwc_otg_hcd, start_work); + struct usb_hcd *usb_hcd = container_of((void *)otg_hcd, struct usb_hcd, hcd_priv); +#endif + DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, usb_hcd); + if (usb_hcd) { + dwc_otg_hcd_start(usb_hcd); + } +} + +/** + * HCD Callback function for starting the HCD when A-Cable is + * connected. + * + * @param p void pointer to the struct usb_hcd + */ +static int32_t dwc_otg_hcd_start_cb(void *p) +{ + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(p); + dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; + hprt0_data_t hprt0; + + if (core_if->op_state == B_HOST) { + /* + * Reset the port. During a HNP mode switch the reset + * needs to occur within 1ms and have a duration of at + * least 50ms. + */ + hprt0.d32 = dwc_otg_read_hprt0(core_if); + hprt0.b.prtrst = 1; + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); + ((struct usb_hcd *)p)->self.is_b_host = 1; + } else { + ((struct usb_hcd *)p)->self.is_b_host = 0; + } + + /* Need to start the HCD in a non-interrupt context. */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) + INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func, p); +// INIT_DELAYED_WORK(&dwc_otg_hcd->start_work, hcd_start_func, p); +#else +// INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func); + INIT_DELAYED_WORK(&dwc_otg_hcd->start_work, hcd_start_func); +#endif +// schedule_work(&dwc_otg_hcd->start_work); + queue_delayed_work(core_if->wq_otg, &dwc_otg_hcd->start_work, 50 * HZ / 1000); + + return 1; +} + +/** + * HCD Callback function for stopping the HCD. + * + * @param p void pointer to the struct usb_hcd + */ +static int32_t dwc_otg_hcd_stop_cb(void *p) +{ + struct usb_hcd *usb_hcd = (struct usb_hcd *)p; + DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p); + dwc_otg_hcd_stop(usb_hcd); + return 1; +} + +static void del_xfer_timers(dwc_otg_hcd_t *hcd) +{ +#ifdef DEBUG + int i; + int num_channels = hcd->core_if->core_params->host_channels; + for (i = 0; i < num_channels; i++) { + del_timer(&hcd->core_if->hc_xfer_timer[i]); + } +#endif +} + +static void del_timers(dwc_otg_hcd_t *hcd) +{ + del_xfer_timers(hcd); + del_timer(&hcd->conn_timer); +} + +/** + * Processes all the URBs in a single list of QHs. Completes them with + * -ETIMEDOUT and frees the QTD. + */ +static void kill_urbs_in_qh_list(dwc_otg_hcd_t *hcd, struct list_head *qh_list) +{ + struct list_head *qh_item; + dwc_otg_qh_t *qh; + struct list_head *qtd_item; + dwc_otg_qtd_t *qtd; + + list_for_each(qh_item, qh_list) { + qh = list_entry(qh_item, dwc_otg_qh_t, qh_list_entry); + for (qtd_item = qh->qtd_list.next; + qtd_item != &qh->qtd_list; + qtd_item = qh->qtd_list.next) { + qtd = list_entry(qtd_item, dwc_otg_qtd_t, qtd_list_entry); + if (qtd->urb != NULL) { + dwc_otg_hcd_complete_urb(hcd, qtd->urb, + -ETIMEDOUT); + } + dwc_otg_hcd_qtd_remove_and_free(hcd, qtd); + } + } +} + +/** + * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic + * and periodic schedules. The QTD associated with each URB is removed from + * the schedule and freed. This function may be called when a disconnect is + * detected or when the HCD is being stopped. + */ +static void kill_all_urbs(dwc_otg_hcd_t *hcd) +{ + kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive); + kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active); + kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive); + kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready); + kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned); + kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued); +} + +/** + * HCD Callback function for disconnect of the HCD. + * + * @param p void pointer to the struct usb_hcd + */ +static int32_t dwc_otg_hcd_disconnect_cb(void *p) +{ + gintsts_data_t intr; + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(p); + + //DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p); + + /* + * Set status flags for the hub driver. + */ + dwc_otg_hcd->flags.b.port_connect_status_change = 1; + dwc_otg_hcd->flags.b.port_connect_status = 0; + + /* + * Shutdown any transfers in process by clearing the Tx FIFO Empty + * interrupt mask and status bits and disabling subsequent host + * channel interrupts. + */ + intr.d32 = 0; + intr.b.nptxfempty = 1; + intr.b.ptxfempty = 1; + intr.b.hcintr = 1; + dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, intr.d32, 0); + dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintsts, intr.d32, 0); + + del_timers(dwc_otg_hcd); + + /* + * Turn off the vbus power only if the core has transitioned to device + * mode. If still in host mode, need to keep power on to detect a + * reconnection. + */ + if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) { + if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) { + hprt0_data_t hprt0 = { .d32=0 }; + DWC_PRINT("Disconnect: PortPower off\n"); + hprt0.b.prtpwr = 0; + dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32); + } + + dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if); + } + + /* Respond with an error status to all URBs in the schedule. */ + kill_all_urbs(dwc_otg_hcd); + + if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) { + /* Clean up any host channels that were in use. */ + int num_channels; + int i; + dwc_hc_t *channel; + dwc_otg_hc_regs_t *hc_regs; + hcchar_data_t hcchar; + + num_channels = dwc_otg_hcd->core_if->core_params->host_channels; + + if (!dwc_otg_hcd->core_if->dma_enable) { + /* Flush out any channel requests in slave mode. */ + for (i = 0; i < num_channels; i++) { + channel = dwc_otg_hcd->hc_ptr_array[i]; + if (list_empty(&channel->hc_list_entry)) { + hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i]; + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + if (hcchar.b.chen) { + hcchar.b.chen = 0; + hcchar.b.chdis = 1; + hcchar.b.epdir = 0; + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); + } + } + } + } + + for (i = 0; i < num_channels; i++) { + channel = dwc_otg_hcd->hc_ptr_array[i]; + if (list_empty(&channel->hc_list_entry)) { + hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i]; + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + if (hcchar.b.chen) { + /* Halt the channel. */ + hcchar.b.chdis = 1; + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); + } + + dwc_otg_hc_cleanup(dwc_otg_hcd->core_if, channel); + list_add_tail(&channel->hc_list_entry, + &dwc_otg_hcd->free_hc_list); + } + } + } + + /* A disconnect will end the session so the B-Device is no + * longer a B-host. */ + ((struct usb_hcd *)p)->self.is_b_host = 0; + return 1; +} + +/** + * Connection timeout function. An OTG host is required to display a + * message if the device does not connect within 10 seconds. + */ +void dwc_otg_hcd_connect_timeout(unsigned long ptr) +{ + DWC_DEBUGPL(DBG_HCDV, "%s(%x)\n", __func__, (int)ptr); + DWC_PRINT("Connect Timeout\n"); + DWC_ERROR("Device Not Connected/Responding\n"); +} + +/** + * Start the connection timer. An OTG host is required to display a + * message if the device does not connect within 10 seconds. The + * timer is deleted if a port connect interrupt occurs before the + * timer expires. + */ +static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t *hcd) +{ + init_timer(&hcd->conn_timer); + hcd->conn_timer.function = dwc_otg_hcd_connect_timeout; + hcd->conn_timer.data = 0; + hcd->conn_timer.expires = jiffies + (HZ * 10); + add_timer(&hcd->conn_timer); +} + +/** + * HCD Callback function for disconnect of the HCD. + * + * @param p void pointer to the struct usb_hcd + */ +static int32_t dwc_otg_hcd_session_start_cb(void *p) +{ + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(p); + DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p); + dwc_otg_hcd_start_connect_timer(dwc_otg_hcd); + return 1; +} + +/** + * HCD Callback structure for handling mode switching. + */ +static dwc_otg_cil_callbacks_t hcd_cil_callbacks = { + .start = dwc_otg_hcd_start_cb, + .stop = dwc_otg_hcd_stop_cb, + .disconnect = dwc_otg_hcd_disconnect_cb, + .session_start = dwc_otg_hcd_session_start_cb, + .p = 0, +}; + +/** + * Reset tasklet function + */ +static void reset_tasklet_func(unsigned long data) +{ + dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *)data; + dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; + hprt0_data_t hprt0; + + DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n"); + + hprt0.d32 = dwc_otg_read_hprt0(core_if); + hprt0.b.prtrst = 1; + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); + mdelay(60); + + hprt0.b.prtrst = 0; + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); + dwc_otg_hcd->flags.b.port_reset_change = 1; +} + +static struct tasklet_struct reset_tasklet = { + .next = NULL, + .state = 0, + .count = ATOMIC_INIT(0), + .func = reset_tasklet_func, + .data = 0, +}; + +/** + * Initializes the HCD. This function allocates memory for and initializes the + * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the + * USB bus with the core and calls the hc_driver->start() function. It returns + * a negative error on failure. + */ +int dwc_otg_hcd_init(struct device *dev) +{ + dwc_otg_device_t *otg_dev = dev_get_drvdata(dev); + struct usb_hcd *hcd = NULL; + dwc_otg_hcd_t *dwc_otg_hcd = NULL; + + int num_channels; + int i; + dwc_hc_t *channel; + + int retval = 0; + + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n"); + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + /* 2.6.20+ requires dev.dma_mask to be set prior to calling usb_create_hcd() */ + + /* Set device flags indicating whether the HCD supports DMA. */ + if (otg_dev->core_if->dma_enable) { + DWC_PRINT("Using DMA mode\n"); + dev->dma_mask = (void *)~0; + dev->coherent_dma_mask = ~0; + + if (otg_dev->core_if->dma_desc_enable) { + DWC_PRINT("Device using Descriptor DMA mode\n"); + } else { + DWC_PRINT("Device using Buffer DMA mode\n"); + } + } else { + DWC_PRINT("Using Slave mode\n"); + dev->dma_mask = (void *)0; + dev->coherent_dma_mask = 0; + } +#endif + /* + * Allocate memory for the base HCD plus the DWC OTG HCD. + * Initialize the base HCD. + */ + hcd = usb_create_hcd(&dwc_otg_hc_driver, dev, dev_name(dev)); + if (!hcd) { + retval = -ENOMEM; + goto error1; + } + + dev_set_drvdata(dev, otg_dev); + hcd->regs = otg_dev->base; + hcd->rsrc_start = otg_dev->phys_addr; + hcd->rsrc_len = otg_dev->base_len; + hcd->self.otg_port = 1; + hcd->has_tt = 1; + + /* Initialize the DWC OTG HCD. */ + dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); + dwc_otg_hcd->core_if = otg_dev->core_if; + otg_dev->hcd = dwc_otg_hcd; + + /* */ + spin_lock_init(&dwc_otg_hcd->lock); + + /* Register the HCD CIL Callbacks */ + dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if, + &hcd_cil_callbacks, hcd); + + /* Initialize the non-periodic schedule. */ + INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive); + INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active); + + /* Initialize the periodic schedule. */ + INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive); + INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready); + INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned); + INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued); + + /* + * Create a host channel descriptor for each host channel implemented + * in the controller. Initialize the channel descriptor array. + */ + INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list); + num_channels = dwc_otg_hcd->core_if->core_params->host_channels; + memset(dwc_otg_hcd->hc_ptr_array, 0, sizeof(dwc_otg_hcd->hc_ptr_array)); + for (i = 0; i < num_channels; i++) { + channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL); + if (channel == NULL) { + retval = -ENOMEM; + DWC_ERROR("%s: host channel allocation failed\n", __func__); + goto error2; + } + memset(channel, 0, sizeof(dwc_hc_t)); + channel->hc_num = i; + dwc_otg_hcd->hc_ptr_array[i] = channel; +#ifdef DEBUG + init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]); +#endif + DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel); + } + + /* Initialize the Connection timeout timer. */ + init_timer(&dwc_otg_hcd->conn_timer); + + /* Initialize reset tasklet. */ + reset_tasklet.data = (unsigned long) dwc_otg_hcd; + dwc_otg_hcd->reset_tasklet = &reset_tasklet; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) + /* Set device flags indicating whether the HCD supports DMA. */ + if (otg_dev->core_if->dma_enable) { + DWC_PRINT("Using DMA mode\n"); + dev->dma_mask = (void *)~0; + dev->coherent_dma_mask = ~0; + + if (otg_dev->core_if->dma_desc_enable){ + DWC_PRINT("Device using Descriptor DMA mode\n"); + } else { + DWC_PRINT("Device using Buffer DMA mode\n"); + } + } else { + DWC_PRINT("Using Slave mode\n"); + dev->dma_mask = (void *)0; + dev->dev.coherent_dma_mask = 0; + } +#endif + /* + * Finish generic HCD initialization and start the HCD. This function + * allocates the DMA buffer pool, registers the USB bus, requests the + * IRQ line, and calls dwc_otg_hcd_start method. + */ + retval = usb_add_hcd(hcd, otg_dev->irq, IRQF_SHARED); + if (retval < 0) { + goto error2; + } + + /* + * Allocate space for storing data on status transactions. Normally no + * data is sent, but this space acts as a bit bucket. This must be + * done after usb_add_hcd since that function allocates the DMA buffer + * pool. + */ + if (otg_dev->core_if->dma_enable) { + dwc_otg_hcd->status_buf = + dma_alloc_coherent(dev, + DWC_OTG_HCD_STATUS_BUF_SIZE, + &dwc_otg_hcd->status_buf_dma, + GFP_KERNEL | GFP_DMA); + } else { + dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE, + GFP_KERNEL); + } + if (!dwc_otg_hcd->status_buf) { + retval = -ENOMEM; + DWC_ERROR("%s: status_buf allocation failed\n", __func__); + goto error3; + } + + dwc_otg_hcd->otg_dev = otg_dev; + + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n", + dev_name(dev), hcd->self.busnum); + + return 0; + + /* Error conditions */ + error3: + usb_remove_hcd(hcd); + error2: + dwc_otg_hcd_free(hcd); + usb_put_hcd(hcd); + + /* FIXME: 2008/05/03 by Steven + * write back to device: + * dwc_otg_hcd has already been released by dwc_otg_hcd_free() + */ + dev_set_drvdata(dev, otg_dev); + + error1: + return retval; +} + +/** + * Removes the HCD. + * Frees memory and resources associated with the HCD and deregisters the bus. + */ +void dwc_otg_hcd_remove(struct device *dev) +{ + dwc_otg_device_t *otg_dev = dev_get_drvdata(dev); + dwc_otg_hcd_t *dwc_otg_hcd; + struct usb_hcd *hcd; + + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE\n"); + + if (!otg_dev) { + DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__); + return; + } + + dwc_otg_hcd = otg_dev->hcd; + + if (!dwc_otg_hcd) { + DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__); + return; + } + + hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd); + + if (!hcd) { + DWC_DEBUGPL(DBG_ANY, "%s: dwc_otg_hcd_to_hcd(dwc_otg_hcd) NULL!\n", __func__); + return; + } + + /* Turn off all interrupts */ + dwc_write_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0); + dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gahbcfg, 1, 0); + + usb_remove_hcd(hcd); + dwc_otg_hcd_free(hcd); + usb_put_hcd(hcd); +} + +/* ========================================================================= + * Linux HC Driver Functions + * ========================================================================= */ + +/** + * Initializes dynamic portions of the DWC_otg HCD state. + */ +static void hcd_reinit(dwc_otg_hcd_t *hcd) +{ + struct list_head *item; + int num_channels; + int i; + dwc_hc_t *channel; + + hcd->flags.d32 = 0; + + hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active; + hcd->non_periodic_channels = 0; + hcd->periodic_channels = 0; + + /* + * Put all channels in the free channel list and clean up channel + * states. + */ + item = hcd->free_hc_list.next; + while (item != &hcd->free_hc_list) { + list_del(item); + item = hcd->free_hc_list.next; + } + num_channels = hcd->core_if->core_params->host_channels; + for (i = 0; i < num_channels; i++) { + channel = hcd->hc_ptr_array[i]; + list_add_tail(&channel->hc_list_entry, &hcd->free_hc_list); + dwc_otg_hc_cleanup(hcd->core_if, channel); + } + + /* Initialize the DWC core for host mode operation. */ + dwc_otg_core_host_init(hcd->core_if); +} + +/** Initializes the DWC_otg controller and its root hub and prepares it for host + * mode operation. Activates the root port. Returns 0 on success and a negative + * error code on failure. */ +int dwc_otg_hcd_start(struct usb_hcd *hcd) +{ + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); + dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; + struct usb_bus *bus; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) + struct usb_device *udev; + int retval; +#endif + + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n"); + + bus = hcd_to_bus(hcd); + + /* Initialize the bus state. If the core is in Device Mode + * HALT the USB bus and return. */ + if (dwc_otg_is_device_mode(core_if)) { +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) + hcd->state = HC_STATE_HALT; +#else + hcd->state = HC_STATE_RUNNING; +#endif + return 0; + } + hcd->state = HC_STATE_RUNNING; + + /* Initialize and connect root hub if one is not already attached */ + if (bus->root_hub) { + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n"); + /* Inform the HUB driver to resume. */ + usb_hcd_resume_root_hub(hcd); + } + else { + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Does Not Have Root Hub\n"); + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) + udev = usb_alloc_dev(NULL, bus, 0); + udev->speed = USB_SPEED_HIGH; + if (!udev) { + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error udev alloc\n"); + return -ENODEV; + } + if ((retval = usb_hcd_register_root_hub(udev, hcd)) != 0) { + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error registering %d\n", retval); + return -ENODEV; + } +#endif + } + + hcd_reinit(dwc_otg_hcd); + + return 0; +} + +static void qh_list_free(dwc_otg_hcd_t *hcd, struct list_head *qh_list) +{ + struct list_head *item; + dwc_otg_qh_t *qh; + + if (!qh_list->next) { + /* The list hasn't been initialized yet. */ + return; + } + + /* Ensure there are no QTDs or URBs left. */ + kill_urbs_in_qh_list(hcd, qh_list); + + for (item = qh_list->next; item != qh_list; item = qh_list->next) { + qh = list_entry(item, dwc_otg_qh_t, qh_list_entry); + dwc_otg_hcd_qh_remove_and_free(hcd, qh); + } +} + +/** + * Halts the DWC_otg host mode operations in a clean manner. USB transfers are + * stopped. + */ +void dwc_otg_hcd_stop(struct usb_hcd *hcd) +{ + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); + hprt0_data_t hprt0 = { .d32=0 }; + + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n"); + + /* Turn off all host-specific interrupts. */ + dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if); + + /* + * The root hub should be disconnected before this function is called. + * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) + * and the QH lists (via ..._hcd_endpoint_disable). + */ + + /* Turn off the vbus power */ + DWC_PRINT("PortPower off\n"); + hprt0.b.prtpwr = 0; + dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32); +} + +/** Returns the current frame number. */ +int dwc_otg_hcd_get_frame_number(struct usb_hcd *hcd) +{ + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); + hfnum_data_t hfnum; + + hfnum.d32 = dwc_read_reg32(&dwc_otg_hcd->core_if-> + host_if->host_global_regs->hfnum); + +#ifdef DEBUG_SOF + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n", hfnum.b.frnum); +#endif + return hfnum.b.frnum; +} + +/** + * Frees secondary storage associated with the dwc_otg_hcd structure contained + * in the struct usb_hcd field. + */ +void dwc_otg_hcd_free(struct usb_hcd *hcd) +{ + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); + int i; + + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n"); + + del_timers(dwc_otg_hcd); + + /* Free memory for QH/QTD lists */ + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive); + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active); + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive); + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready); + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned); + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued); + + /* Free memory for the host channels. */ + for (i = 0; i < MAX_EPS_CHANNELS; i++) { + dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i]; + if (hc != NULL) { + DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n", i, hc); + kfree(hc); + } + } + + if (dwc_otg_hcd->core_if->dma_enable) { + if (dwc_otg_hcd->status_buf_dma) { + dma_free_coherent(hcd->self.controller, + DWC_OTG_HCD_STATUS_BUF_SIZE, + dwc_otg_hcd->status_buf, + dwc_otg_hcd->status_buf_dma); + } + } else if (dwc_otg_hcd->status_buf != NULL) { + kfree(dwc_otg_hcd->status_buf); + } +} + +#ifdef DEBUG +static void dump_urb_info(struct urb *urb, char* fn_name) +{ + DWC_PRINT("%s, urb %p\n", fn_name, urb); + DWC_PRINT(" Device address: %d\n", usb_pipedevice(urb->pipe)); + DWC_PRINT(" Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe), + (usb_pipein(urb->pipe) ? "IN" : "OUT")); + DWC_PRINT(" Endpoint type: %s\n", + ({char *pipetype; + switch (usb_pipetype(urb->pipe)) { + case PIPE_CONTROL: pipetype = "CONTROL"; break; + case PIPE_BULK: pipetype = "BULK"; break; + case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break; + case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break; + default: pipetype = "UNKNOWN"; break; + }; pipetype;})); + DWC_PRINT(" Speed: %s\n", + ({char *speed; + switch (urb->dev->speed) { + case USB_SPEED_HIGH: speed = "HIGH"; break; + case USB_SPEED_FULL: speed = "FULL"; break; + case USB_SPEED_LOW: speed = "LOW"; break; + default: speed = "UNKNOWN"; break; + }; speed;})); + DWC_PRINT(" Max packet size: %d\n", + usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); + DWC_PRINT(" Data buffer length: %d\n", urb->transfer_buffer_length); + DWC_PRINT(" Transfer buffer: %p, Transfer DMA: %p\n", + urb->transfer_buffer, (void *)urb->transfer_dma); + DWC_PRINT(" Setup buffer: %p, Setup DMA: %p\n", + urb->setup_packet, (void *)urb->setup_dma); + DWC_PRINT(" Interval: %d\n", urb->interval); + if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { + int i; + for (i = 0; i < urb->number_of_packets; i++) { + DWC_PRINT(" ISO Desc %d:\n", i); + DWC_PRINT(" offset: %d, length %d\n", + urb->iso_frame_desc[i].offset, + urb->iso_frame_desc[i].length); + } + } +} + +static void dump_channel_info(dwc_otg_hcd_t *hcd, + dwc_otg_qh_t *qh) +{ + if (qh->channel != NULL) { + dwc_hc_t *hc = qh->channel; + struct list_head *item; + dwc_otg_qh_t *qh_item; + int num_channels = hcd->core_if->core_params->host_channels; + int i; + + dwc_otg_hc_regs_t *hc_regs; + hcchar_data_t hcchar; + hcsplt_data_t hcsplt; + hctsiz_data_t hctsiz; + uint32_t hcdma; + + hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num]; + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt); + hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); + hcdma = dwc_read_reg32(&hc_regs->hcdma); + + DWC_PRINT(" Assigned to channel %p:\n", hc); + DWC_PRINT(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32); + DWC_PRINT(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma); + DWC_PRINT(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n", + hc->dev_addr, hc->ep_num, hc->ep_is_in); + DWC_PRINT(" ep_type: %d\n", hc->ep_type); + DWC_PRINT(" max_packet: %d\n", hc->max_packet); + DWC_PRINT(" data_pid_start: %d\n", hc->data_pid_start); + DWC_PRINT(" xfer_started: %d\n", hc->xfer_started); + DWC_PRINT(" halt_status: %d\n", hc->halt_status); + DWC_PRINT(" xfer_buff: %p\n", hc->xfer_buff); + DWC_PRINT(" xfer_len: %d\n", hc->xfer_len); + DWC_PRINT(" qh: %p\n", hc->qh); + DWC_PRINT(" NP inactive sched:\n"); + list_for_each(item, &hcd->non_periodic_sched_inactive) { + qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry); + DWC_PRINT(" %p\n", qh_item); + } + DWC_PRINT(" NP active sched:\n"); + list_for_each(item, &hcd->non_periodic_sched_active) { + qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry); + DWC_PRINT(" %p\n", qh_item); + } + DWC_PRINT(" Channels: \n"); + for (i = 0; i < num_channels; i++) { + dwc_hc_t *hc = hcd->hc_ptr_array[i]; + DWC_PRINT(" %2d: %p\n", i, hc); + } + } +} +#endif + +/** Starts processing a USB transfer request specified by a USB Request Block + * (URB). mem_flags indicates the type of memory allocation to use while + * processing this URB. */ +int dwc_otg_hcd_urb_enqueue(struct usb_hcd *hcd, + struct urb *urb, +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) + int mem_flags +#else + gfp_t mem_flags +#endif + ) +{ + int retval = 0; + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); + dwc_otg_qtd_t *qtd; + +#ifdef DEBUG + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { + dump_urb_info(urb, "dwc_otg_hcd_urb_enqueue"); + } +#endif + if (!dwc_otg_hcd->flags.b.port_connect_status) { + /* No longer connected. */ + return -ENODEV; + } + + qtd = dwc_otg_hcd_qtd_create(urb); + if (qtd == NULL) { + DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n"); + return -ENOMEM; + } + + retval = dwc_otg_hcd_qtd_add(qtd, dwc_otg_hcd); + if (retval < 0) { + DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. " + "Error status %d\n", retval); + dwc_otg_hcd_qtd_free(qtd); + } + + return retval; +} + +/** Aborts/cancels a USB transfer request. Always returns 0 to indicate + * success. */ +int dwc_otg_hcd_urb_dequeue(struct usb_hcd *hcd, + struct urb *urb, + int status) +{ + unsigned long flags; + dwc_otg_hcd_t *dwc_otg_hcd; + dwc_otg_qtd_t *urb_qtd; + dwc_otg_qh_t *qh; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb); +#endif + + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n"); + + dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); + + SPIN_LOCK_IRQSAVE(&dwc_otg_hcd->lock, flags); + + urb_qtd = (dwc_otg_qtd_t *)urb->hcpriv; + qh = (dwc_otg_qh_t *)ep->hcpriv; + +#ifdef DEBUG + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { + dump_urb_info(urb, "dwc_otg_hcd_urb_dequeue"); + if (urb_qtd == qh->qtd_in_process) { + dump_channel_info(dwc_otg_hcd, qh); + } + } +#endif + + if (urb_qtd == qh->qtd_in_process) { + /* The QTD is in process (it has been assigned to a channel). */ + + if (dwc_otg_hcd->flags.b.port_connect_status) { + /* + * If still connected (i.e. in host mode), halt the + * channel so it can be used for other transfers. If + * no longer connected, the host registers can't be + * written to halt the channel since the core is in + * device mode. + */ + dwc_otg_hc_halt(dwc_otg_hcd->core_if, qh->channel, + DWC_OTG_HC_XFER_URB_DEQUEUE); + } + } + + /* + * Free the QTD and clean up the associated QH. Leave the QH in the + * schedule if it has any remaining QTDs. + */ + dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd, urb_qtd); + if (urb_qtd == qh->qtd_in_process) { + dwc_otg_hcd_qh_deactivate(dwc_otg_hcd, qh, 0); + qh->channel = NULL; + qh->qtd_in_process = NULL; + } else if (list_empty(&qh->qtd_list)) { + dwc_otg_hcd_qh_remove(dwc_otg_hcd, qh); + } + + SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags); + + urb->hcpriv = NULL; + + /* Higher layer software sets URB status. */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + usb_hcd_giveback_urb(hcd, urb, status); +#else + usb_hcd_giveback_urb(hcd, urb, NULL); +#endif + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { + DWC_PRINT("Called usb_hcd_giveback_urb()\n"); + DWC_PRINT(" urb->status = %d\n", urb->status); + } + + return 0; +} + +/** Frees resources in the DWC_otg controller related to a given endpoint. Also + * clears state in the HCD related to the endpoint. Any URBs for the endpoint + * must already be dequeued. */ +void dwc_otg_hcd_endpoint_disable(struct usb_hcd *hcd, + struct usb_host_endpoint *ep) +{ + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); + dwc_otg_qh_t *qh; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + unsigned long flags; + int retry = 0; +#endif + + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, " + "endpoint=%d\n", ep->desc.bEndpointAddress, + dwc_ep_addr_to_endpoint(ep->desc.bEndpointAddress)); + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) +rescan: + SPIN_LOCK_IRQSAVE(&dwc_otg_hcd->lock, flags); + qh = (dwc_otg_qh_t *)(ep->hcpriv); + if (!qh) + goto done; + + /** Check that the QTD list is really empty */ + if (!list_empty(&qh->qtd_list)) { + if (retry++ < 250) { + SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags); + schedule_timeout_uninterruptible(1); + goto rescan; + } + + DWC_WARN("DWC OTG HCD EP DISABLE:" + " QTD List for this endpoint is not empty\n"); + } + + dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd, qh); + ep->hcpriv = NULL; +done: + SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags); + +#else // LINUX_VERSION_CODE + + qh = (dwc_otg_qh_t *)(ep->hcpriv); + if (qh != NULL) { +#ifdef DEBUG + /** Check that the QTD list is really empty */ + if (!list_empty(&qh->qtd_list)) { + DWC_WARN("DWC OTG HCD EP DISABLE:" + " QTD List for this endpoint is not empty\n"); + } +#endif + dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd, qh); + ep->hcpriv = NULL; + } +#endif // LINUX_VERSION_CODE +} + +/** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if + * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid + * interrupt. + * + * This function is called by the USB core when an interrupt occurs */ +irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) + , struct pt_regs *regs +#endif + ) +{ + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); + return IRQ_RETVAL(dwc_otg_hcd_handle_intr(dwc_otg_hcd)); +} + +/** Creates Status Change bitmap for the root hub and root port. The bitmap is + * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 + * is the status change indicator for the single root port. Returns 1 if either + * change indicator is 1, otherwise returns 0. */ +int dwc_otg_hcd_hub_status_data(struct usb_hcd *hcd, char *buf) +{ + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); + + buf[0] = 0; + buf[0] |= (dwc_otg_hcd->flags.b.port_connect_status_change || + dwc_otg_hcd->flags.b.port_reset_change || + dwc_otg_hcd->flags.b.port_enable_change || + dwc_otg_hcd->flags.b.port_suspend_change || + dwc_otg_hcd->flags.b.port_over_current_change) << 1; + +#ifdef DEBUG + if (buf[0]) { + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:" + " Root port status changed\n"); + DWC_DEBUGPL(DBG_HCDV, " port_connect_status_change: %d\n", + dwc_otg_hcd->flags.b.port_connect_status_change); + DWC_DEBUGPL(DBG_HCDV, " port_reset_change: %d\n", + dwc_otg_hcd->flags.b.port_reset_change); + DWC_DEBUGPL(DBG_HCDV, " port_enable_change: %d\n", + dwc_otg_hcd->flags.b.port_enable_change); + DWC_DEBUGPL(DBG_HCDV, " port_suspend_change: %d\n", + dwc_otg_hcd->flags.b.port_suspend_change); + DWC_DEBUGPL(DBG_HCDV, " port_over_current_change: %d\n", + dwc_otg_hcd->flags.b.port_over_current_change); + } +#endif + return (buf[0] != 0); +} + +#ifdef DWC_HS_ELECT_TST +/* + * Quick and dirty hack to implement the HS Electrical Test + * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature. + * + * This code was copied from our userspace app "hset". It sends a + * Get Device Descriptor control sequence in two parts, first the + * Setup packet by itself, followed some time later by the In and + * Ack packets. Rather than trying to figure out how to add this + * functionality to the normal driver code, we just hijack the + * hardware, using these two function to drive the hardware + * directly. + */ + +dwc_otg_core_global_regs_t *global_regs; +dwc_otg_host_global_regs_t *hc_global_regs; +dwc_otg_hc_regs_t *hc_regs; +uint32_t *data_fifo; + +static void do_setup(void) +{ + gintsts_data_t gintsts; + hctsiz_data_t hctsiz; + hcchar_data_t hcchar; + haint_data_t haint; + hcint_data_t hcint; + + /* Enable HAINTs */ + dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001); + + /* Enable HCINTs */ + dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3); + + /* Read GINTSTS */ + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); + + /* Read HAINT */ + haint.d32 = dwc_read_reg32(&hc_global_regs->haint); + //fprintf(stderr, "HAINT: %08x\n", haint.d32); + + /* Read HCINT */ + hcint.d32 = dwc_read_reg32(&hc_regs->hcint); + //fprintf(stderr, "HCINT: %08x\n", hcint.d32); + + /* Read HCCHAR */ + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); + + /* Clear HCINT */ + dwc_write_reg32(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ + dwc_write_reg32(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ + dwc_write_reg32(&global_regs->gintsts, gintsts.d32); + + /* Read GINTSTS */ + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); + + /* + * Send Setup packet (Get Device Descriptor) + */ + + /* Make sure channel is disabled */ + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + if (hcchar.b.chen) { + //fprintf(stderr, "Channel already enabled 1, HCCHAR = %08x\n", hcchar.d32); + hcchar.b.chdis = 1; +// hcchar.b.chen = 1; + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); + //sleep(1); + mdelay(1000); + + /* Read GINTSTS */ + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); + + /* Read HAINT */ + haint.d32 = dwc_read_reg32(&hc_global_regs->haint); + //fprintf(stderr, "HAINT: %08x\n", haint.d32); + + /* Read HCINT */ + hcint.d32 = dwc_read_reg32(&hc_regs->hcint); + //fprintf(stderr, "HCINT: %08x\n", hcint.d32); + + /* Read HCCHAR */ + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); + + /* Clear HCINT */ + dwc_write_reg32(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ + dwc_write_reg32(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ + dwc_write_reg32(&global_regs->gintsts, gintsts.d32); + + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + //if (hcchar.b.chen) { + // fprintf(stderr, "** Channel _still_ enabled 1, HCCHAR = %08x **\n", hcchar.d32); + //} + } + + /* Set HCTSIZ */ + hctsiz.d32 = 0; + hctsiz.b.xfersize = 8; + hctsiz.b.pktcnt = 1; + hctsiz.b.pid = DWC_OTG_HC_PID_SETUP; + dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); + + /* Set HCCHAR */ + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; + hcchar.b.epdir = 0; + hcchar.b.epnum = 0; + hcchar.b.mps = 8; + hcchar.b.chen = 1; + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); + + /* Fill FIFO with Setup data for Get Device Descriptor */ + data_fifo = (uint32_t *)((char *)global_regs + 0x1000); + dwc_write_reg32(data_fifo++, 0x01000680); + dwc_write_reg32(data_fifo++, 0x00080000); + + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + //fprintf(stderr, "Waiting for HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32); + + /* Wait for host channel interrupt */ + do { + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + } while (gintsts.b.hcintr == 0); + + //fprintf(stderr, "Got HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32); + + /* Disable HCINTs */ + dwc_write_reg32(&hc_regs->hcintmsk, 0x0000); + + /* Disable HAINTs */ + dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000); + + /* Read HAINT */ + haint.d32 = dwc_read_reg32(&hc_global_regs->haint); + //fprintf(stderr, "HAINT: %08x\n", haint.d32); + + /* Read HCINT */ + hcint.d32 = dwc_read_reg32(&hc_regs->hcint); + //fprintf(stderr, "HCINT: %08x\n", hcint.d32); + + /* Read HCCHAR */ + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); + + /* Clear HCINT */ + dwc_write_reg32(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ + dwc_write_reg32(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ + dwc_write_reg32(&global_regs->gintsts, gintsts.d32); + + /* Read GINTSTS */ + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); +} + +static void do_in_ack(void) +{ + gintsts_data_t gintsts; + hctsiz_data_t hctsiz; + hcchar_data_t hcchar; + haint_data_t haint; + hcint_data_t hcint; + host_grxsts_data_t grxsts; + + /* Enable HAINTs */ + dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001); + + /* Enable HCINTs */ + dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3); + + /* Read GINTSTS */ + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); + + /* Read HAINT */ + haint.d32 = dwc_read_reg32(&hc_global_regs->haint); + //fprintf(stderr, "HAINT: %08x\n", haint.d32); + + /* Read HCINT */ + hcint.d32 = dwc_read_reg32(&hc_regs->hcint); + //fprintf(stderr, "HCINT: %08x\n", hcint.d32); + + /* Read HCCHAR */ + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); + + /* Clear HCINT */ + dwc_write_reg32(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ + dwc_write_reg32(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ + dwc_write_reg32(&global_regs->gintsts, gintsts.d32); + + /* Read GINTSTS */ + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); + + /* + * Receive Control In packet + */ + + /* Make sure channel is disabled */ + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + if (hcchar.b.chen) { + //fprintf(stderr, "Channel already enabled 2, HCCHAR = %08x\n", hcchar.d32); + hcchar.b.chdis = 1; + hcchar.b.chen = 1; + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); + //sleep(1); + mdelay(1000); + + /* Read GINTSTS */ + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); + + /* Read HAINT */ + haint.d32 = dwc_read_reg32(&hc_global_regs->haint); + //fprintf(stderr, "HAINT: %08x\n", haint.d32); + + /* Read HCINT */ + hcint.d32 = dwc_read_reg32(&hc_regs->hcint); + //fprintf(stderr, "HCINT: %08x\n", hcint.d32); + + /* Read HCCHAR */ + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); + + /* Clear HCINT */ + dwc_write_reg32(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ + dwc_write_reg32(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ + dwc_write_reg32(&global_regs->gintsts, gintsts.d32); + + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + //if (hcchar.b.chen) { + // fprintf(stderr, "** Channel _still_ enabled 2, HCCHAR = %08x **\n", hcchar.d32); + //} + } + + /* Set HCTSIZ */ + hctsiz.d32 = 0; + hctsiz.b.xfersize = 8; + hctsiz.b.pktcnt = 1; + hctsiz.b.pid = DWC_OTG_HC_PID_DATA1; + dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); + + /* Set HCCHAR */ + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; + hcchar.b.epdir = 1; + hcchar.b.epnum = 0; + hcchar.b.mps = 8; + hcchar.b.chen = 1; + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); + + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + //fprintf(stderr, "Waiting for RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32); + + /* Wait for receive status queue interrupt */ + do { + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + } while (gintsts.b.rxstsqlvl == 0); + + //fprintf(stderr, "Got RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32); + + /* Read RXSTS */ + grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp); + //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32); + + /* Clear RXSTSQLVL in GINTSTS */ + gintsts.d32 = 0; + gintsts.b.rxstsqlvl = 1; + dwc_write_reg32(&global_regs->gintsts, gintsts.d32); + + switch (grxsts.b.pktsts) { + case DWC_GRXSTS_PKTSTS_IN: + /* Read the data into the host buffer */ + if (grxsts.b.bcnt > 0) { + int i; + int word_count = (grxsts.b.bcnt + 3) / 4; + + data_fifo = (uint32_t *)((char *)global_regs + 0x1000); + + for (i = 0; i < word_count; i++) { + (void)dwc_read_reg32(data_fifo++); + } + } + + //fprintf(stderr, "Received %u bytes\n", (unsigned)grxsts.b.bcnt); + break; + + default: + //fprintf(stderr, "** Unexpected GRXSTS packet status 1 **\n"); + break; + } + + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + //fprintf(stderr, "Waiting for RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32); + + /* Wait for receive status queue interrupt */ + do { + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + } while (gintsts.b.rxstsqlvl == 0); + + //fprintf(stderr, "Got RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32); + + /* Read RXSTS */ + grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp); + //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32); + + /* Clear RXSTSQLVL in GINTSTS */ + gintsts.d32 = 0; + gintsts.b.rxstsqlvl = 1; + dwc_write_reg32(&global_regs->gintsts, gintsts.d32); + + switch (grxsts.b.pktsts) { + case DWC_GRXSTS_PKTSTS_IN_XFER_COMP: + break; + + default: + //fprintf(stderr, "** Unexpected GRXSTS packet status 2 **\n"); + break; + } + + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + //fprintf(stderr, "Waiting for HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32); + + /* Wait for host channel interrupt */ + do { + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + } while (gintsts.b.hcintr == 0); + + //fprintf(stderr, "Got HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32); + + /* Read HAINT */ + haint.d32 = dwc_read_reg32(&hc_global_regs->haint); + //fprintf(stderr, "HAINT: %08x\n", haint.d32); + + /* Read HCINT */ + hcint.d32 = dwc_read_reg32(&hc_regs->hcint); + //fprintf(stderr, "HCINT: %08x\n", hcint.d32); + + /* Read HCCHAR */ + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); + + /* Clear HCINT */ + dwc_write_reg32(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ + dwc_write_reg32(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ + dwc_write_reg32(&global_regs->gintsts, gintsts.d32); + + /* Read GINTSTS */ + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); + +// usleep(100000); +// mdelay(100); + mdelay(1); + + /* + * Send handshake packet + */ + + /* Read HAINT */ + haint.d32 = dwc_read_reg32(&hc_global_regs->haint); + //fprintf(stderr, "HAINT: %08x\n", haint.d32); + + /* Read HCINT */ + hcint.d32 = dwc_read_reg32(&hc_regs->hcint); + //fprintf(stderr, "HCINT: %08x\n", hcint.d32); + + /* Read HCCHAR */ + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); + + /* Clear HCINT */ + dwc_write_reg32(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ + dwc_write_reg32(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ + dwc_write_reg32(&global_regs->gintsts, gintsts.d32); + + /* Read GINTSTS */ + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); + + /* Make sure channel is disabled */ + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + if (hcchar.b.chen) { + //fprintf(stderr, "Channel already enabled 3, HCCHAR = %08x\n", hcchar.d32); + hcchar.b.chdis = 1; + hcchar.b.chen = 1; + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); + //sleep(1); + mdelay(1000); + + /* Read GINTSTS */ + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); + + /* Read HAINT */ + haint.d32 = dwc_read_reg32(&hc_global_regs->haint); + //fprintf(stderr, "HAINT: %08x\n", haint.d32); + + /* Read HCINT */ + hcint.d32 = dwc_read_reg32(&hc_regs->hcint); + //fprintf(stderr, "HCINT: %08x\n", hcint.d32); + + /* Read HCCHAR */ + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); + + /* Clear HCINT */ + dwc_write_reg32(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ + dwc_write_reg32(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ + dwc_write_reg32(&global_regs->gintsts, gintsts.d32); + + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + //if (hcchar.b.chen) { + // fprintf(stderr, "** Channel _still_ enabled 3, HCCHAR = %08x **\n", hcchar.d32); + //} + } + + /* Set HCTSIZ */ + hctsiz.d32 = 0; + hctsiz.b.xfersize = 0; + hctsiz.b.pktcnt = 1; + hctsiz.b.pid = DWC_OTG_HC_PID_DATA1; + dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); + + /* Set HCCHAR */ + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; + hcchar.b.epdir = 0; + hcchar.b.epnum = 0; + hcchar.b.mps = 8; + hcchar.b.chen = 1; + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); + + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + //fprintf(stderr, "Waiting for HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32); + + /* Wait for host channel interrupt */ + do { + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + } while (gintsts.b.hcintr == 0); + + //fprintf(stderr, "Got HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32); + + /* Disable HCINTs */ + dwc_write_reg32(&hc_regs->hcintmsk, 0x0000); + + /* Disable HAINTs */ + dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000); + + /* Read HAINT */ + haint.d32 = dwc_read_reg32(&hc_global_regs->haint); + //fprintf(stderr, "HAINT: %08x\n", haint.d32); + + /* Read HCINT */ + hcint.d32 = dwc_read_reg32(&hc_regs->hcint); + //fprintf(stderr, "HCINT: %08x\n", hcint.d32); + + /* Read HCCHAR */ + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); + + /* Clear HCINT */ + dwc_write_reg32(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ + dwc_write_reg32(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ + dwc_write_reg32(&global_regs->gintsts, gintsts.d32); + + /* Read GINTSTS */ + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); +} +#endif /* DWC_HS_ELECT_TST */ + +/** Handles hub class-specific requests. */ +int dwc_otg_hcd_hub_control(struct usb_hcd *hcd, + u16 typeReq, + u16 wValue, + u16 wIndex, + char *buf, + u16 wLength) +{ + int retval = 0; + + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); + dwc_otg_core_if_t *core_if = hcd_to_dwc_otg_hcd(hcd)->core_if; + struct usb_hub_descriptor *desc; + hprt0_data_t hprt0 = {.d32 = 0}; + + uint32_t port_status; + + switch (typeReq) { + case ClearHubFeature: + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "ClearHubFeature 0x%x\n", wValue); + switch (wValue) { + case C_HUB_LOCAL_POWER: + case C_HUB_OVER_CURRENT: + /* Nothing required here */ + break; + default: + retval = -EINVAL; + DWC_ERROR("DWC OTG HCD - " + "ClearHubFeature request %xh unknown\n", wValue); + } + break; + case ClearPortFeature: + if (!wIndex || wIndex > 1) + goto error; + + switch (wValue) { + case USB_PORT_FEAT_ENABLE: + DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - " + "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); + hprt0.d32 = dwc_otg_read_hprt0(core_if); + hprt0.b.prtena = 1; + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); + break; + case USB_PORT_FEAT_SUSPEND: + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); + hprt0.d32 = dwc_otg_read_hprt0(core_if); + hprt0.b.prtres = 1; + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); + /* Clear Resume bit */ + mdelay(100); + hprt0.b.prtres = 0; + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); + break; + case USB_PORT_FEAT_POWER: + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "ClearPortFeature USB_PORT_FEAT_POWER\n"); + hprt0.d32 = dwc_otg_read_hprt0(core_if); + hprt0.b.prtpwr = 0; + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); + break; + case USB_PORT_FEAT_INDICATOR: + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); + /* Port inidicator not supported */ + break; + case USB_PORT_FEAT_C_CONNECTION: + /* Clears drivers internal connect status change + * flag */ + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); + dwc_otg_hcd->flags.b.port_connect_status_change = 0; + break; + case USB_PORT_FEAT_C_RESET: + /* Clears the driver's internal Port Reset Change + * flag */ + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); + dwc_otg_hcd->flags.b.port_reset_change = 0; + break; + case USB_PORT_FEAT_C_ENABLE: + /* Clears the driver's internal Port + * Enable/Disable Change flag */ + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); + dwc_otg_hcd->flags.b.port_enable_change = 0; + break; + case USB_PORT_FEAT_C_SUSPEND: + /* Clears the driver's internal Port Suspend + * Change flag, which is set when resume signaling on + * the host port is complete */ + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); + dwc_otg_hcd->flags.b.port_suspend_change = 0; + break; + case USB_PORT_FEAT_C_OVER_CURRENT: + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); + dwc_otg_hcd->flags.b.port_over_current_change = 0; + break; + default: + retval = -EINVAL; + DWC_ERROR("DWC OTG HCD - " + "ClearPortFeature request %xh " + "unknown or unsupported\n", wValue); + } + break; + case GetHubDescriptor: + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "GetHubDescriptor\n"); + desc = (struct usb_hub_descriptor *)buf; + desc->bDescLength = 9; + desc->bDescriptorType = 0x29; + desc->bNbrPorts = 1; + desc->wHubCharacteristics = 0x08; + desc->bPwrOn2PwrGood = 1; + desc->bHubContrCurrent = 0; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,39) + desc->u.hs.DeviceRemovable[0] = 0; + desc->u.hs.DeviceRemovable[1] = 0xff; +#endif + break; + case GetHubStatus: + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "GetHubStatus\n"); + memset(buf, 0, 4); + break; + case GetPortStatus: + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "GetPortStatus\n"); + + if (!wIndex || wIndex > 1) + goto error; + + port_status = 0; + + if (dwc_otg_hcd->flags.b.port_connect_status_change) + port_status |= (1 << USB_PORT_FEAT_C_CONNECTION); + + if (dwc_otg_hcd->flags.b.port_enable_change) + port_status |= (1 << USB_PORT_FEAT_C_ENABLE); + + if (dwc_otg_hcd->flags.b.port_suspend_change) + port_status |= (1 << USB_PORT_FEAT_C_SUSPEND); + + if (dwc_otg_hcd->flags.b.port_reset_change) + port_status |= (1 << USB_PORT_FEAT_C_RESET); + + if (dwc_otg_hcd->flags.b.port_over_current_change) { + DWC_ERROR("Device Not Supported\n"); + port_status |= (1 << USB_PORT_FEAT_C_OVER_CURRENT); + } + + if (!dwc_otg_hcd->flags.b.port_connect_status) { + /* + * The port is disconnected, which means the core is + * either in device mode or it soon will be. Just + * return 0's for the remainder of the port status + * since the port register can't be read if the core + * is in device mode. + */ + *((__le32 *) buf) = cpu_to_le32(port_status); + break; + } + + hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0); + DWC_DEBUGPL(DBG_HCDV, " HPRT0: 0x%08x\n", hprt0.d32); + + if (hprt0.b.prtconnsts) + port_status |= (1 << USB_PORT_FEAT_CONNECTION); + + if (hprt0.b.prtena) + port_status |= (1 << USB_PORT_FEAT_ENABLE); + + if (hprt0.b.prtsusp) + port_status |= (1 << USB_PORT_FEAT_SUSPEND); + + if (hprt0.b.prtovrcurract) + port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT); + + if (hprt0.b.prtrst) + port_status |= (1 << USB_PORT_FEAT_RESET); + + if (hprt0.b.prtpwr) + port_status |= (1 << USB_PORT_FEAT_POWER); + + if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) + port_status |= USB_PORT_STAT_HIGH_SPEED; + else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED) + port_status |= USB_PORT_STAT_LOW_SPEED; + + if (hprt0.b.prttstctl) + port_status |= (1 << USB_PORT_FEAT_TEST); + + /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ + + *((__le32 *) buf) = cpu_to_le32(port_status); + + break; + case SetHubFeature: + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "SetHubFeature\n"); + /* No HUB features supported */ + break; + case SetPortFeature: + if (wValue != USB_PORT_FEAT_TEST && (!wIndex || wIndex > 1)) + goto error; + + if (!dwc_otg_hcd->flags.b.port_connect_status) { + /* + * The port is disconnected, which means the core is + * either in device mode or it soon will be. Just + * return without doing anything since the port + * register can't be written if the core is in device + * mode. + */ + break; + } + + switch (wValue) { + case USB_PORT_FEAT_SUSPEND: + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); + if (hcd->self.otg_port == wIndex && + hcd->self.b_hnp_enable) { + gotgctl_data_t gotgctl = {.d32=0}; + gotgctl.b.hstsethnpen = 1; + dwc_modify_reg32(&core_if->core_global_regs->gotgctl, + 0, gotgctl.d32); + core_if->op_state = A_SUSPEND; + } + hprt0.d32 = dwc_otg_read_hprt0(core_if); + hprt0.b.prtsusp = 1; + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); + //DWC_PRINT("SUSPEND: HPRT0=%0x\n", hprt0.d32); + /* Suspend the Phy Clock */ + { + pcgcctl_data_t pcgcctl = {.d32=0}; + pcgcctl.b.stoppclk = 1; + dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32); + } + + /* For HNP the bus must be suspended for at least 200ms. */ + if (hcd->self.b_hnp_enable) { + mdelay(200); + //DWC_PRINT("SUSPEND: wait complete! (%d)\n", _hcd->state); + } + break; + case USB_PORT_FEAT_POWER: + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "SetPortFeature - USB_PORT_FEAT_POWER\n"); + hprt0.d32 = dwc_otg_read_hprt0(core_if); + hprt0.b.prtpwr = 1; + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); + break; + case USB_PORT_FEAT_RESET: + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "SetPortFeature - USB_PORT_FEAT_RESET\n"); + hprt0.d32 = dwc_otg_read_hprt0(core_if); + /* When B-Host the Port reset bit is set in + * the Start HCD Callback function, so that + * the reset is started within 1ms of the HNP + * success interrupt. */ + if (!hcd->self.is_b_host) { + hprt0.b.prtrst = 1; + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); + } + /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ + MDELAY(60); + hprt0.b.prtrst = 0; + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); + break; + +#ifdef DWC_HS_ELECT_TST + case USB_PORT_FEAT_TEST: + { + uint32_t t; + gintmsk_data_t gintmsk; + + t = (wIndex >> 8); /* MSB wIndex USB */ + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "SetPortFeature - USB_PORT_FEAT_TEST %d\n", t); + warn("USB_PORT_FEAT_TEST %d\n", t); + if (t < 6) { + hprt0.d32 = dwc_otg_read_hprt0(core_if); + hprt0.b.prttstctl = t; + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); + } else { + /* Setup global vars with reg addresses (quick and + * dirty hack, should be cleaned up) + */ + global_regs = core_if->core_global_regs; + hc_global_regs = core_if->host_if->host_global_regs; + hc_regs = (dwc_otg_hc_regs_t *)((char *)global_regs + 0x500); + data_fifo = (uint32_t *)((char *)global_regs + 0x1000); + + if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */ + /* Save current interrupt mask */ + gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk); + + /* Disable all interrupts while we muck with + * the hardware directly + */ + dwc_write_reg32(&global_regs->gintmsk, 0); + + /* 15 second delay per the test spec */ + mdelay(15000); + + /* Drive suspend on the root port */ + hprt0.d32 = dwc_otg_read_hprt0(core_if); + hprt0.b.prtsusp = 1; + hprt0.b.prtres = 0; + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); + + /* 15 second delay per the test spec */ + mdelay(15000); + + /* Drive resume on the root port */ + hprt0.d32 = dwc_otg_read_hprt0(core_if); + hprt0.b.prtsusp = 0; + hprt0.b.prtres = 1; + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); + mdelay(100); + + /* Clear the resume bit */ + hprt0.b.prtres = 0; + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); + + /* Restore interrupts */ + dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32); + } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */ + /* Save current interrupt mask */ + gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk); + + /* Disable all interrupts while we muck with + * the hardware directly + */ + dwc_write_reg32(&global_regs->gintmsk, 0); + + /* 15 second delay per the test spec */ + mdelay(15000); + + /* Send the Setup packet */ + do_setup(); + + /* 15 second delay so nothing else happens for awhile */ + mdelay(15000); + + /* Restore interrupts */ + dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32); + } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */ + /* Save current interrupt mask */ + gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk); + + /* Disable all interrupts while we muck with + * the hardware directly + */ + dwc_write_reg32(&global_regs->gintmsk, 0); + + /* Send the Setup packet */ + do_setup(); + + /* 15 second delay so nothing else happens for awhile */ + mdelay(15000); + + /* Send the In and Ack packets */ + do_in_ack(); + + /* 15 second delay so nothing else happens for awhile */ + mdelay(15000); + + /* Restore interrupts */ + dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32); + } + } + break; + } +#endif /* DWC_HS_ELECT_TST */ + + case USB_PORT_FEAT_INDICATOR: + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); + /* Not supported */ + break; + default: + retval = -EINVAL; + DWC_ERROR("DWC OTG HCD - " + "SetPortFeature request %xh " + "unknown or unsupported\n", wValue); + break; + } + break; + default: + error: + retval = -EINVAL; + DWC_WARN("DWC OTG HCD - " + "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n", + typeReq, wIndex, wValue); + break; + } + + return retval; +} + +/** + * Assigns transactions from a QTD to a free host channel and initializes the + * host channel to perform the transactions. The host channel is removed from + * the free list. + * + * @param hcd The HCD state structure. + * @param qh Transactions from the first QTD for this QH are selected and + * assigned to a free host channel. + */ +static void assign_and_init_hc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) +{ + dwc_hc_t *hc; + dwc_otg_qtd_t *qtd; + struct urb *urb; + + DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, hcd, qh); + + hc = list_entry(hcd->free_hc_list.next, dwc_hc_t, hc_list_entry); + + /* Remove the host channel from the free list. */ + list_del_init(&hc->hc_list_entry); + + qtd = list_entry(qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); + urb = qtd->urb; + qh->channel = hc; + qh->qtd_in_process = qtd; + + /* + * Use usb_pipedevice to determine device address. This address is + * 0 before the SET_ADDRESS command and the correct address afterward. + */ + hc->dev_addr = usb_pipedevice(urb->pipe); + hc->ep_num = usb_pipeendpoint(urb->pipe); + + if (urb->dev->speed == USB_SPEED_LOW) { + hc->speed = DWC_OTG_EP_SPEED_LOW; + } else if (urb->dev->speed == USB_SPEED_FULL) { + hc->speed = DWC_OTG_EP_SPEED_FULL; + } else { + hc->speed = DWC_OTG_EP_SPEED_HIGH; + } + + hc->max_packet = dwc_max_packet(qh->maxp); + + hc->xfer_started = 0; + hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS; + hc->error_state = (qtd->error_count > 0); + hc->halt_on_queue = 0; + hc->halt_pending = 0; + hc->requests = 0; + + /* + * The following values may be modified in the transfer type section + * below. The xfer_len value may be reduced when the transfer is + * started to accommodate the max widths of the XferSize and PktCnt + * fields in the HCTSIZn register. + */ + hc->do_ping = qh->ping_state; + hc->ep_is_in = (usb_pipein(urb->pipe) != 0); + hc->data_pid_start = qh->data_toggle; + hc->multi_count = 1; + + if (hcd->core_if->dma_enable) { + hc->xfer_buff = (uint8_t *)urb->transfer_dma + urb->actual_length; + } else { + hc->xfer_buff = (uint8_t *)urb->transfer_buffer + urb->actual_length; + } + hc->xfer_len = urb->transfer_buffer_length - urb->actual_length; + hc->xfer_count = 0; + + /* + * Set the split attributes + */ + hc->do_split = 0; + if (qh->do_split) { + hc->do_split = 1; + hc->xact_pos = qtd->isoc_split_pos; + hc->complete_split = qtd->complete_split; + hc->hub_addr = urb->dev->tt->hub->devnum; + hc->port_addr = urb->dev->ttport; + } + + switch (usb_pipetype(urb->pipe)) { + case PIPE_CONTROL: + hc->ep_type = DWC_OTG_EP_TYPE_CONTROL; + switch (qtd->control_phase) { + case DWC_OTG_CONTROL_SETUP: + DWC_DEBUGPL(DBG_HCDV, " Control setup transaction\n"); + hc->do_ping = 0; + hc->ep_is_in = 0; + hc->data_pid_start = DWC_OTG_HC_PID_SETUP; + if (hcd->core_if->dma_enable) { + hc->xfer_buff = (uint8_t *)urb->setup_dma; + } else { + hc->xfer_buff = (uint8_t *)urb->setup_packet; + } + hc->xfer_len = 8; + break; + case DWC_OTG_CONTROL_DATA: + DWC_DEBUGPL(DBG_HCDV, " Control data transaction\n"); + hc->data_pid_start = qtd->data_toggle; + break; + case DWC_OTG_CONTROL_STATUS: + /* + * Direction is opposite of data direction or IN if no + * data. + */ + DWC_DEBUGPL(DBG_HCDV, " Control status transaction\n"); + if (urb->transfer_buffer_length == 0) { + hc->ep_is_in = 1; + } else { + hc->ep_is_in = (usb_pipein(urb->pipe) != USB_DIR_IN); + } + if (hc->ep_is_in) { + hc->do_ping = 0; + } + hc->data_pid_start = DWC_OTG_HC_PID_DATA1; + hc->xfer_len = 0; + if (hcd->core_if->dma_enable) { + hc->xfer_buff = (uint8_t *)hcd->status_buf_dma; + } else { + hc->xfer_buff = (uint8_t *)hcd->status_buf; + } + break; + } + break; + case PIPE_BULK: + hc->ep_type = DWC_OTG_EP_TYPE_BULK; + break; + case PIPE_INTERRUPT: + hc->ep_type = DWC_OTG_EP_TYPE_INTR; + break; + case PIPE_ISOCHRONOUS: + { + struct usb_iso_packet_descriptor *frame_desc; + frame_desc = &urb->iso_frame_desc[qtd->isoc_frame_index]; + hc->ep_type = DWC_OTG_EP_TYPE_ISOC; + if (hcd->core_if->dma_enable) { + hc->xfer_buff = (uint8_t *)urb->transfer_dma; + } else { + hc->xfer_buff = (uint8_t *)urb->transfer_buffer; + } + hc->xfer_buff += frame_desc->offset + qtd->isoc_split_offset; + hc->xfer_len = frame_desc->length - qtd->isoc_split_offset; + + if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) { + if (hc->xfer_len <= 188) { + hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL; + } + else { + hc->xact_pos = DWC_HCSPLIT_XACTPOS_BEGIN; + } + } + } + break; + } + + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { + /* + * This value may be modified when the transfer is started to + * reflect the actual transfer length. + */ + hc->multi_count = dwc_hb_mult(qh->maxp); + } + + dwc_otg_hc_init(hcd->core_if, hc); + hc->qh = qh; +} + +/** + * This function selects transactions from the HCD transfer schedule and + * assigns them to available host channels. It is called from HCD interrupt + * handler functions. + * + * @param hcd The HCD state structure. + * + * @return The types of new transactions that were assigned to host channels. + */ +dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *hcd) +{ + struct list_head *qh_ptr; + dwc_otg_qh_t *qh; + int num_channels; + dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE; + +#ifdef DEBUG_SOF + DWC_DEBUGPL(DBG_HCD, " Select Transactions\n"); +#endif + + /* Process entries in the periodic ready list. */ + qh_ptr = hcd->periodic_sched_ready.next; + while (qh_ptr != &hcd->periodic_sched_ready && + !list_empty(&hcd->free_hc_list)) { + + qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry); + assign_and_init_hc(hcd, qh); + + /* + * Move the QH from the periodic ready schedule to the + * periodic assigned schedule. + */ + qh_ptr = qh_ptr->next; + list_move(&qh->qh_list_entry, &hcd->periodic_sched_assigned); + + ret_val = DWC_OTG_TRANSACTION_PERIODIC; + } + + /* + * Process entries in the inactive portion of the non-periodic + * schedule. Some free host channels may not be used if they are + * reserved for periodic transfers. + */ + qh_ptr = hcd->non_periodic_sched_inactive.next; + num_channels = hcd->core_if->core_params->host_channels; + while (qh_ptr != &hcd->non_periodic_sched_inactive && + (hcd->non_periodic_channels < + num_channels - hcd->periodic_channels) && + !list_empty(&hcd->free_hc_list)) { + + qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry); + assign_and_init_hc(hcd, qh); + + /* + * Move the QH from the non-periodic inactive schedule to the + * non-periodic active schedule. + */ + qh_ptr = qh_ptr->next; + list_move(&qh->qh_list_entry, &hcd->non_periodic_sched_active); + + if (ret_val == DWC_OTG_TRANSACTION_NONE) { + ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC; + } else { + ret_val = DWC_OTG_TRANSACTION_ALL; + } + + hcd->non_periodic_channels++; + } + + return ret_val; +} + +/** + * Attempts to queue a single transaction request for a host channel + * associated with either a periodic or non-periodic transfer. This function + * assumes that there is space available in the appropriate request queue. For + * an OUT transfer or SETUP transaction in Slave mode, it checks whether space + * is available in the appropriate Tx FIFO. + * + * @param hcd The HCD state structure. + * @param hc Host channel descriptor associated with either a periodic or + * non-periodic transfer. + * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx + * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic + * transfers. + * + * @return 1 if a request is queued and more requests may be needed to + * complete the transfer, 0 if no more requests are required for this + * transfer, -1 if there is insufficient space in the Tx FIFO. + */ +static int queue_transaction(dwc_otg_hcd_t *hcd, + dwc_hc_t *hc, + uint16_t fifo_dwords_avail) +{ + int retval; + + if (hcd->core_if->dma_enable) { + if (!hc->xfer_started) { + dwc_otg_hc_start_transfer(hcd->core_if, hc); + hc->qh->ping_state = 0; + } + retval = 0; + } else if (hc->halt_pending) { + /* Don't queue a request if the channel has been halted. */ + retval = 0; + } else if (hc->halt_on_queue) { + dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status); + retval = 0; + } else if (hc->do_ping) { + if (!hc->xfer_started) { + dwc_otg_hc_start_transfer(hcd->core_if, hc); + } + retval = 0; + } else if (!hc->ep_is_in || + hc->data_pid_start == DWC_OTG_HC_PID_SETUP) { + if ((fifo_dwords_avail * 4) >= hc->max_packet) { + if (!hc->xfer_started) { + dwc_otg_hc_start_transfer(hcd->core_if, hc); + retval = 1; + } else { + retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc); + } + } else { + retval = -1; + } + } else { + if (!hc->xfer_started) { + dwc_otg_hc_start_transfer(hcd->core_if, hc); + retval = 1; + } else { + retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc); + } + } + + return retval; +} + +/** + * Processes active non-periodic channels and queues transactions for these + * channels to the DWC_otg controller. After queueing transactions, the NP Tx + * FIFO Empty interrupt is enabled if there are more transactions to queue as + * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx + * FIFO Empty interrupt is disabled. + */ +static void process_non_periodic_channels(dwc_otg_hcd_t *hcd) +{ + gnptxsts_data_t tx_status; + struct list_head *orig_qh_ptr; + dwc_otg_qh_t *qh; + int status; + int no_queue_space = 0; + int no_fifo_space = 0; + int more_to_do = 0; + + dwc_otg_core_global_regs_t *global_regs = hcd->core_if->core_global_regs; + + DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n"); +#ifdef DEBUG + tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts); + DWC_DEBUGPL(DBG_HCDV, " NP Tx Req Queue Space Avail (before queue): %d\n", + tx_status.b.nptxqspcavail); + DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (before queue): %d\n", + tx_status.b.nptxfspcavail); +#endif + /* + * Keep track of the starting point. Skip over the start-of-list + * entry. + */ + if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) { + hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next; + } + orig_qh_ptr = hcd->non_periodic_qh_ptr; + + /* + * Process once through the active list or until no more space is + * available in the request queue or the Tx FIFO. + */ + do { + tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts); + if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) { + no_queue_space = 1; + break; + } + + qh = list_entry(hcd->non_periodic_qh_ptr, dwc_otg_qh_t, qh_list_entry); + status = queue_transaction(hcd, qh->channel, tx_status.b.nptxfspcavail); + + if (status > 0) { + more_to_do = 1; + } else if (status < 0) { + no_fifo_space = 1; + break; + } + + /* Advance to next QH, skipping start-of-list entry. */ + hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next; + if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) { + hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next; + } + + } while (hcd->non_periodic_qh_ptr != orig_qh_ptr); + + if (!hcd->core_if->dma_enable) { + gintmsk_data_t intr_mask = {.d32 = 0}; + intr_mask.b.nptxfempty = 1; + +#ifdef DEBUG + tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts); + DWC_DEBUGPL(DBG_HCDV, " NP Tx Req Queue Space Avail (after queue): %d\n", + tx_status.b.nptxqspcavail); + DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (after queue): %d\n", + tx_status.b.nptxfspcavail); +#endif + if (more_to_do || no_queue_space || no_fifo_space) { + /* + * May need to queue more transactions as the request + * queue or Tx FIFO empties. Enable the non-periodic + * Tx FIFO empty interrupt. (Always use the half-empty + * level to ensure that new requests are loaded as + * soon as possible.) + */ + dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32); + } else { + /* + * Disable the Tx FIFO empty interrupt since there are + * no more transactions that need to be queued right + * now. This function is called from interrupt + * handlers to queue more transactions as transfer + * states change. + */ + dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0); + } + } +} + +/** + * Processes periodic channels for the next frame and queues transactions for + * these channels to the DWC_otg controller. After queueing transactions, the + * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions + * to queue as Periodic Tx FIFO or request queue space becomes available. + * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. + */ +static void process_periodic_channels(dwc_otg_hcd_t *hcd) +{ + hptxsts_data_t tx_status; + struct list_head *qh_ptr; + dwc_otg_qh_t *qh; + int status; + int no_queue_space = 0; + int no_fifo_space = 0; + + dwc_otg_host_global_regs_t *host_regs; + host_regs = hcd->core_if->host_if->host_global_regs; + + DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n"); +#ifdef DEBUG + tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts); + DWC_DEBUGPL(DBG_HCDV, " P Tx Req Queue Space Avail (before queue): %d\n", + tx_status.b.ptxqspcavail); + DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (before queue): %d\n", + tx_status.b.ptxfspcavail); +#endif + + qh_ptr = hcd->periodic_sched_assigned.next; + while (qh_ptr != &hcd->periodic_sched_assigned) { + tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts); + if (tx_status.b.ptxqspcavail == 0) { + no_queue_space = 1; + break; + } + + qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry); + + /* + * Set a flag if we're queuing high-bandwidth in slave mode. + * The flag prevents any halts to get into the request queue in + * the middle of multiple high-bandwidth packets getting queued. + */ + if (!hcd->core_if->dma_enable && + qh->channel->multi_count > 1) + { + hcd->core_if->queuing_high_bandwidth = 1; + } + + status = queue_transaction(hcd, qh->channel, tx_status.b.ptxfspcavail); + if (status < 0) { + no_fifo_space = 1; + break; + } + + /* + * In Slave mode, stay on the current transfer until there is + * nothing more to do or the high-bandwidth request count is + * reached. In DMA mode, only need to queue one request. The + * controller automatically handles multiple packets for + * high-bandwidth transfers. + */ + if (hcd->core_if->dma_enable || status == 0 || + qh->channel->requests == qh->channel->multi_count) { + qh_ptr = qh_ptr->next; + /* + * Move the QH from the periodic assigned schedule to + * the periodic queued schedule. + */ + list_move(&qh->qh_list_entry, &hcd->periodic_sched_queued); + + /* done queuing high bandwidth */ + hcd->core_if->queuing_high_bandwidth = 0; + } + } + + if (!hcd->core_if->dma_enable) { + dwc_otg_core_global_regs_t *global_regs; + gintmsk_data_t intr_mask = {.d32 = 0}; + + global_regs = hcd->core_if->core_global_regs; + intr_mask.b.ptxfempty = 1; +#ifdef DEBUG + tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts); + DWC_DEBUGPL(DBG_HCDV, " P Tx Req Queue Space Avail (after queue): %d\n", + tx_status.b.ptxqspcavail); + DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (after queue): %d\n", + tx_status.b.ptxfspcavail); +#endif + if (!list_empty(&hcd->periodic_sched_assigned) || + no_queue_space || no_fifo_space) { + /* + * May need to queue more transactions as the request + * queue or Tx FIFO empties. Enable the periodic Tx + * FIFO empty interrupt. (Always use the half-empty + * level to ensure that new requests are loaded as + * soon as possible.) + */ + dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32); + } else { + /* + * Disable the Tx FIFO empty interrupt since there are + * no more transactions that need to be queued right + * now. This function is called from interrupt + * handlers to queue more transactions as transfer + * states change. + */ + dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0); + } + } +} + +/** + * This function processes the currently active host channels and queues + * transactions for these channels to the DWC_otg controller. It is called + * from HCD interrupt handler functions. + * + * @param hcd The HCD state structure. + * @param tr_type The type(s) of transactions to queue (non-periodic, + * periodic, or both). + */ +void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *hcd, + dwc_otg_transaction_type_e tr_type) +{ +#ifdef DEBUG_SOF + DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n"); +#endif + /* Process host channels associated with periodic transfers. */ + if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC || + tr_type == DWC_OTG_TRANSACTION_ALL) && + !list_empty(&hcd->periodic_sched_assigned)) { + + process_periodic_channels(hcd); + } + + /* Process host channels associated with non-periodic transfers. */ + if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC || + tr_type == DWC_OTG_TRANSACTION_ALL) { + if (!list_empty(&hcd->non_periodic_sched_active)) { + process_non_periodic_channels(hcd); + } else { + /* + * Ensure NP Tx FIFO empty interrupt is disabled when + * there are no non-periodic transfers to process. + */ + gintmsk_data_t gintmsk = {.d32 = 0}; + gintmsk.b.nptxfempty = 1; + dwc_modify_reg32(&hcd->core_if->core_global_regs->gintmsk, + gintmsk.d32, 0); + } + } +} + +/** + * Sets the final status of an URB and returns it to the device driver. Any + * required cleanup of the URB is performed. + */ +void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t *hcd, struct urb *urb, int status) +{ +#ifdef DEBUG + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { + DWC_PRINT("%s: urb %p, device %d, ep %d %s, status=%d\n", + __func__, urb, usb_pipedevice(urb->pipe), + usb_pipeendpoint(urb->pipe), + usb_pipein(urb->pipe) ? "IN" : "OUT", status); + if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { + int i; + for (i = 0; i < urb->number_of_packets; i++) { + DWC_PRINT(" ISO Desc %d status: %d\n", + i, urb->iso_frame_desc[i].status); + } + } + } +#endif + + urb->status = status; + urb->hcpriv = NULL; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb, status); +#else + usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb, NULL); +#endif +} + +/* + * Returns the Queue Head for an URB. + */ +dwc_otg_qh_t *dwc_urb_to_qh(struct urb *urb) +{ + struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb); + return (dwc_otg_qh_t *)ep->hcpriv; +} + +#ifdef DEBUG +void dwc_print_setup_data(uint8_t *setup) +{ + int i; + if (CHK_DEBUG_LEVEL(DBG_HCD)){ + DWC_PRINT("Setup Data = MSB "); + for (i = 7; i >= 0; i--) DWC_PRINT("%02x ", setup[i]); + DWC_PRINT("\n"); + DWC_PRINT(" bmRequestType Tranfer = %s\n", (setup[0] & 0x80) ? "Device-to-Host" : "Host-to-Device"); + DWC_PRINT(" bmRequestType Type = "); + switch ((setup[0] & 0x60) >> 5) { + case 0: DWC_PRINT("Standard\n"); break; + case 1: DWC_PRINT("Class\n"); break; + case 2: DWC_PRINT("Vendor\n"); break; + case 3: DWC_PRINT("Reserved\n"); break; + } + DWC_PRINT(" bmRequestType Recipient = "); + switch (setup[0] & 0x1f) { + case 0: DWC_PRINT("Device\n"); break; + case 1: DWC_PRINT("Interface\n"); break; + case 2: DWC_PRINT("Endpoint\n"); break; + case 3: DWC_PRINT("Other\n"); break; + default: DWC_PRINT("Reserved\n"); break; + } + DWC_PRINT(" bRequest = 0x%0x\n", setup[1]); + DWC_PRINT(" wValue = 0x%0x\n", *((uint16_t *)&setup[2])); + DWC_PRINT(" wIndex = 0x%0x\n", *((uint16_t *)&setup[4])); + DWC_PRINT(" wLength = 0x%0x\n\n", *((uint16_t *)&setup[6])); + } +} +#endif + +void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *hcd) { +#if defined(DEBUG) && LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) + DWC_PRINT("Frame remaining at SOF:\n"); + DWC_PRINT(" samples %u, accum %llu, avg %llu\n", + hcd->frrem_samples, hcd->frrem_accum, + (hcd->frrem_samples > 0) ? + hcd->frrem_accum/hcd->frrem_samples : 0); + + DWC_PRINT("\n"); + DWC_PRINT("Frame remaining at start_transfer (uframe 7):\n"); + DWC_PRINT(" samples %u, accum %llu, avg %llu\n", + hcd->core_if->hfnum_7_samples, hcd->core_if->hfnum_7_frrem_accum, + (hcd->core_if->hfnum_7_samples > 0) ? + hcd->core_if->hfnum_7_frrem_accum/hcd->core_if->hfnum_7_samples : 0); + DWC_PRINT("Frame remaining at start_transfer (uframe 0):\n"); + DWC_PRINT(" samples %u, accum %llu, avg %llu\n", + hcd->core_if->hfnum_0_samples, hcd->core_if->hfnum_0_frrem_accum, + (hcd->core_if->hfnum_0_samples > 0) ? + hcd->core_if->hfnum_0_frrem_accum/hcd->core_if->hfnum_0_samples : 0); + DWC_PRINT("Frame remaining at start_transfer (uframe 1-6):\n"); + DWC_PRINT(" samples %u, accum %llu, avg %llu\n", + hcd->core_if->hfnum_other_samples, hcd->core_if->hfnum_other_frrem_accum, + (hcd->core_if->hfnum_other_samples > 0) ? + hcd->core_if->hfnum_other_frrem_accum/hcd->core_if->hfnum_other_samples : 0); + + DWC_PRINT("\n"); + DWC_PRINT("Frame remaining at sample point A (uframe 7):\n"); + DWC_PRINT(" samples %u, accum %llu, avg %llu\n", + hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a, + (hcd->hfnum_7_samples_a > 0) ? + hcd->hfnum_7_frrem_accum_a/hcd->hfnum_7_samples_a : 0); + DWC_PRINT("Frame remaining at sample point A (uframe 0):\n"); + DWC_PRINT(" samples %u, accum %llu, avg %llu\n", + hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a, + (hcd->hfnum_0_samples_a > 0) ? + hcd->hfnum_0_frrem_accum_a/hcd->hfnum_0_samples_a : 0); + DWC_PRINT("Frame remaining at sample point A (uframe 1-6):\n"); + DWC_PRINT(" samples %u, accum %llu, avg %llu\n", + hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a, + (hcd->hfnum_other_samples_a > 0) ? + hcd->hfnum_other_frrem_accum_a/hcd->hfnum_other_samples_a : 0); + + DWC_PRINT("\n"); + DWC_PRINT("Frame remaining at sample point B (uframe 7):\n"); + DWC_PRINT(" samples %u, accum %llu, avg %llu\n", + hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b, + (hcd->hfnum_7_samples_b > 0) ? + hcd->hfnum_7_frrem_accum_b/hcd->hfnum_7_samples_b : 0); + DWC_PRINT("Frame remaining at sample point B (uframe 0):\n"); + DWC_PRINT(" samples %u, accum %llu, avg %llu\n", + hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b, + (hcd->hfnum_0_samples_b > 0) ? + hcd->hfnum_0_frrem_accum_b/hcd->hfnum_0_samples_b : 0); + DWC_PRINT("Frame remaining at sample point B (uframe 1-6):\n"); + DWC_PRINT(" samples %u, accum %llu, avg %llu\n", + hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b, + (hcd->hfnum_other_samples_b > 0) ? + hcd->hfnum_other_frrem_accum_b/hcd->hfnum_other_samples_b : 0); +#endif +} + +void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *hcd) +{ +#ifdef DEBUG + int num_channels; + int i; + gnptxsts_data_t np_tx_status; + hptxsts_data_t p_tx_status; + + num_channels = hcd->core_if->core_params->host_channels; + DWC_PRINT("\n"); + DWC_PRINT("************************************************************\n"); + DWC_PRINT("HCD State:\n"); + DWC_PRINT(" Num channels: %d\n", num_channels); + for (i = 0; i < num_channels; i++) { + dwc_hc_t *hc = hcd->hc_ptr_array[i]; + DWC_PRINT(" Channel %d:\n", i); + DWC_PRINT(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n", + hc->dev_addr, hc->ep_num, hc->ep_is_in); + DWC_PRINT(" speed: %d\n", hc->speed); + DWC_PRINT(" ep_type: %d\n", hc->ep_type); + DWC_PRINT(" max_packet: %d\n", hc->max_packet); + DWC_PRINT(" data_pid_start: %d\n", hc->data_pid_start); + DWC_PRINT(" multi_count: %d\n", hc->multi_count); + DWC_PRINT(" xfer_started: %d\n", hc->xfer_started); + DWC_PRINT(" xfer_buff: %p\n", hc->xfer_buff); + DWC_PRINT(" xfer_len: %d\n", hc->xfer_len); + DWC_PRINT(" xfer_count: %d\n", hc->xfer_count); + DWC_PRINT(" halt_on_queue: %d\n", hc->halt_on_queue); + DWC_PRINT(" halt_pending: %d\n", hc->halt_pending); + DWC_PRINT(" halt_status: %d\n", hc->halt_status); + DWC_PRINT(" do_split: %d\n", hc->do_split); + DWC_PRINT(" complete_split: %d\n", hc->complete_split); + DWC_PRINT(" hub_addr: %d\n", hc->hub_addr); + DWC_PRINT(" port_addr: %d\n", hc->port_addr); + DWC_PRINT(" xact_pos: %d\n", hc->xact_pos); + DWC_PRINT(" requests: %d\n", hc->requests); + DWC_PRINT(" qh: %p\n", hc->qh); + if (hc->xfer_started) { + hfnum_data_t hfnum; + hcchar_data_t hcchar; + hctsiz_data_t hctsiz; + hcint_data_t hcint; + hcintmsk_data_t hcintmsk; + hfnum.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hfnum); + hcchar.d32 = dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->hcchar); + hctsiz.d32 = dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->hctsiz); + hcint.d32 = dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->hcint); + hcintmsk.d32 = dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->hcintmsk); + DWC_PRINT(" hfnum: 0x%08x\n", hfnum.d32); + DWC_PRINT(" hcchar: 0x%08x\n", hcchar.d32); + DWC_PRINT(" hctsiz: 0x%08x\n", hctsiz.d32); + DWC_PRINT(" hcint: 0x%08x\n", hcint.d32); + DWC_PRINT(" hcintmsk: 0x%08x\n", hcintmsk.d32); + } + if (hc->xfer_started && hc->qh && hc->qh->qtd_in_process) { + dwc_otg_qtd_t *qtd; + struct urb *urb; + qtd = hc->qh->qtd_in_process; + urb = qtd->urb; + DWC_PRINT(" URB Info:\n"); + DWC_PRINT(" qtd: %p, urb: %p\n", qtd, urb); + if (urb) { + DWC_PRINT(" Dev: %d, EP: %d %s\n", + usb_pipedevice(urb->pipe), usb_pipeendpoint(urb->pipe), + usb_pipein(urb->pipe) ? "IN" : "OUT"); + DWC_PRINT(" Max packet size: %d\n", + usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); + DWC_PRINT(" transfer_buffer: %p\n", urb->transfer_buffer); + DWC_PRINT(" transfer_dma: %p\n", (void *)urb->transfer_dma); + DWC_PRINT(" transfer_buffer_length: %d\n", urb->transfer_buffer_length); + DWC_PRINT(" actual_length: %d\n", urb->actual_length); + } + } + } + DWC_PRINT(" non_periodic_channels: %d\n", hcd->non_periodic_channels); + DWC_PRINT(" periodic_channels: %d\n", hcd->periodic_channels); + DWC_PRINT(" periodic_usecs: %d\n", hcd->periodic_usecs); + np_tx_status.d32 = dwc_read_reg32(&hcd->core_if->core_global_regs->gnptxsts); + DWC_PRINT(" NP Tx Req Queue Space Avail: %d\n", np_tx_status.b.nptxqspcavail); + DWC_PRINT(" NP Tx FIFO Space Avail: %d\n", np_tx_status.b.nptxfspcavail); + p_tx_status.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hptxsts); + DWC_PRINT(" P Tx Req Queue Space Avail: %d\n", p_tx_status.b.ptxqspcavail); + DWC_PRINT(" P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail); + dwc_otg_hcd_dump_frrem(hcd); + dwc_otg_dump_global_registers(hcd->core_if); + dwc_otg_dump_host_registers(hcd->core_if); + DWC_PRINT("************************************************************\n"); + DWC_PRINT("\n"); +#endif +} +#endif /* DWC_DEVICE_ONLY */ diff --git a/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_hcd.h b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_hcd.h new file mode 100644 index 0000000000..ee41dc96f9 --- /dev/null +++ b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_hcd.h @@ -0,0 +1,668 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $ + * $Revision: 1.3 $ + * $Date: 2008-12-15 06:51:32 $ + * $Change: 1064918 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and + * redistribute this Software in source and binary forms, with or without + * modification, provided that redistributions of source code must retain this + * notice. You may not view, use, disclose, copy or distribute this file or + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * ========================================================================== */ +#ifndef DWC_DEVICE_ONLY +#ifndef __DWC_HCD_H__ +#define __DWC_HCD_H__ + +#include +#include +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35) +#include +#else +#include <../drivers/usb/core/hcd.h> +#endif + +struct dwc_otg_device; + +#include "dwc_otg_cil.h" + +/** + * @file + * + * This file contains the structures, constants, and interfaces for + * the Host Contoller Driver (HCD). + * + * The Host Controller Driver (HCD) is responsible for translating requests + * from the USB Driver into the appropriate actions on the DWC_otg controller. + * It isolates the USBD from the specifics of the controller by providing an + * API to the USBD. + */ + +/** + * Phases for control transfers. + */ +typedef enum dwc_otg_control_phase { + DWC_OTG_CONTROL_SETUP, + DWC_OTG_CONTROL_DATA, + DWC_OTG_CONTROL_STATUS +} dwc_otg_control_phase_e; + +/** Transaction types. */ +typedef enum dwc_otg_transaction_type { + DWC_OTG_TRANSACTION_NONE, + DWC_OTG_TRANSACTION_PERIODIC, + DWC_OTG_TRANSACTION_NON_PERIODIC, + DWC_OTG_TRANSACTION_ALL +} dwc_otg_transaction_type_e; + +/** + * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, + * interrupt, or isochronous transfer. A single QTD is created for each URB + * (of one of these types) submitted to the HCD. The transfer associated with + * a QTD may require one or multiple transactions. + * + * A QTD is linked to a Queue Head, which is entered in either the + * non-periodic or periodic schedule for execution. When a QTD is chosen for + * execution, some or all of its transactions may be executed. After + * execution, the state of the QTD is updated. The QTD may be retired if all + * its transactions are complete or if an error occurred. Otherwise, it + * remains in the schedule so more transactions can be executed later. + */ +typedef struct dwc_otg_qtd { + /** + * Determines the PID of the next data packet for the data phase of + * control transfers. Ignored for other transfer types.
+ * One of the following values: + * - DWC_OTG_HC_PID_DATA0 + * - DWC_OTG_HC_PID_DATA1 + */ + uint8_t data_toggle; + + /** Current phase for control transfers (Setup, Data, or Status). */ + dwc_otg_control_phase_e control_phase; + + /** Keep track of the current split type + * for FS/LS endpoints on a HS Hub */ + uint8_t complete_split; + + /** How many bytes transferred during SSPLIT OUT */ + uint32_t ssplit_out_xfer_count; + + /** + * Holds the number of bus errors that have occurred for a transaction + * within this transfer. + */ + uint8_t error_count; + + /** + * Index of the next frame descriptor for an isochronous transfer. A + * frame descriptor describes the buffer position and length of the + * data to be transferred in the next scheduled (micro)frame of an + * isochronous transfer. It also holds status for that transaction. + * The frame index starts at 0. + */ + int isoc_frame_index; + + /** Position of the ISOC split on full/low speed */ + uint8_t isoc_split_pos; + + /** Position of the ISOC split in the buffer for the current frame */ + uint16_t isoc_split_offset; + + /** URB for this transfer */ + struct urb *urb; + + /** This list of QTDs */ + struct list_head qtd_list_entry; + +} dwc_otg_qtd_t; + +/** + * A Queue Head (QH) holds the static characteristics of an endpoint and + * maintains a list of transfers (QTDs) for that endpoint. A QH structure may + * be entered in either the non-periodic or periodic schedule. + */ +typedef struct dwc_otg_qh { + /** + * Endpoint type. + * One of the following values: + * - USB_ENDPOINT_XFER_CONTROL + * - USB_ENDPOINT_XFER_ISOC + * - USB_ENDPOINT_XFER_BULK + * - USB_ENDPOINT_XFER_INT + */ + uint8_t ep_type; + uint8_t ep_is_in; + + /** wMaxPacketSize Field of Endpoint Descriptor. */ + uint16_t maxp; + + /** + * Determines the PID of the next data packet for non-control + * transfers. Ignored for control transfers.
+ * One of the following values: + * - DWC_OTG_HC_PID_DATA0 + * - DWC_OTG_HC_PID_DATA1 + */ + uint8_t data_toggle; + + /** Ping state if 1. */ + uint8_t ping_state; + + /** + * List of QTDs for this QH. + */ + struct list_head qtd_list; + + /** Host channel currently processing transfers for this QH. */ + dwc_hc_t *channel; + + /** QTD currently assigned to a host channel for this QH. */ + dwc_otg_qtd_t *qtd_in_process; + + /** Full/low speed endpoint on high-speed hub requires split. */ + uint8_t do_split; + + /** @name Periodic schedule information */ + /** @{ */ + + /** Bandwidth in microseconds per (micro)frame. */ + uint8_t usecs; + + /** Interval between transfers in (micro)frames. */ + uint16_t interval; + + /** + * (micro)frame to initialize a periodic transfer. The transfer + * executes in the following (micro)frame. + */ + uint16_t sched_frame; + + /** (micro)frame at which last start split was initialized. */ + uint16_t start_split_frame; + + /** @} */ + + /** Entry for QH in either the periodic or non-periodic schedule. */ + struct list_head qh_list_entry; + + /* For non-dword aligned buffer support */ + uint8_t *dw_align_buf; + dma_addr_t dw_align_buf_dma; +} dwc_otg_qh_t; + +/** + * This structure holds the state of the HCD, including the non-periodic and + * periodic schedules. + */ +typedef struct dwc_otg_hcd { + /** The DWC otg device pointer */ + struct dwc_otg_device *otg_dev; + + /** DWC OTG Core Interface Layer */ + dwc_otg_core_if_t *core_if; + + /** Internal DWC HCD Flags */ + volatile union dwc_otg_hcd_internal_flags { + uint32_t d32; + struct { + unsigned port_connect_status_change : 1; + unsigned port_connect_status : 1; + unsigned port_reset_change : 1; + unsigned port_enable_change : 1; + unsigned port_suspend_change : 1; + unsigned port_over_current_change : 1; + unsigned reserved : 27; + } b; + } flags; + + /** + * Inactive items in the non-periodic schedule. This is a list of + * Queue Heads. Transfers associated with these Queue Heads are not + * currently assigned to a host channel. + */ + struct list_head non_periodic_sched_inactive; + + /** + * Active items in the non-periodic schedule. This is a list of + * Queue Heads. Transfers associated with these Queue Heads are + * currently assigned to a host channel. + */ + struct list_head non_periodic_sched_active; + + /** + * Pointer to the next Queue Head to process in the active + * non-periodic schedule. + */ + struct list_head *non_periodic_qh_ptr; + + /** + * Inactive items in the periodic schedule. This is a list of QHs for + * periodic transfers that are _not_ scheduled for the next frame. + * Each QH in the list has an interval counter that determines when it + * needs to be scheduled for execution. This scheduling mechanism + * allows only a simple calculation for periodic bandwidth used (i.e. + * must assume that all periodic transfers may need to execute in the + * same frame). However, it greatly simplifies scheduling and should + * be sufficient for the vast majority of OTG hosts, which need to + * connect to a small number of peripherals at one time. + * + * Items move from this list to periodic_sched_ready when the QH + * interval counter is 0 at SOF. + */ + struct list_head periodic_sched_inactive; + + /** + * List of periodic QHs that are ready for execution in the next + * frame, but have not yet been assigned to host channels. + * + * Items move from this list to periodic_sched_assigned as host + * channels become available during the current frame. + */ + struct list_head periodic_sched_ready; + + /** + * List of periodic QHs to be executed in the next frame that are + * assigned to host channels. + * + * Items move from this list to periodic_sched_queued as the + * transactions for the QH are queued to the DWC_otg controller. + */ + struct list_head periodic_sched_assigned; + + /** + * List of periodic QHs that have been queued for execution. + * + * Items move from this list to either periodic_sched_inactive or + * periodic_sched_ready when the channel associated with the transfer + * is released. If the interval for the QH is 1, the item moves to + * periodic_sched_ready because it must be rescheduled for the next + * frame. Otherwise, the item moves to periodic_sched_inactive. + */ + struct list_head periodic_sched_queued; + + /** + * Total bandwidth claimed so far for periodic transfers. This value + * is in microseconds per (micro)frame. The assumption is that all + * periodic transfers may occur in the same (micro)frame. + */ + uint16_t periodic_usecs; + + /** + * Frame number read from the core at SOF. The value ranges from 0 to + * DWC_HFNUM_MAX_FRNUM. + */ + uint16_t frame_number; + + /** + * Free host channels in the controller. This is a list of + * dwc_hc_t items. + */ + struct list_head free_hc_list; + + /** + * Number of host channels assigned to periodic transfers. Currently + * assuming that there is a dedicated host channel for each periodic + * transaction and at least one host channel available for + * non-periodic transactions. + */ + int periodic_channels; + + /** + * Number of host channels assigned to non-periodic transfers. + */ + int non_periodic_channels; + + /** + * Array of pointers to the host channel descriptors. Allows accessing + * a host channel descriptor given the host channel number. This is + * useful in interrupt handlers. + */ + dwc_hc_t *hc_ptr_array[MAX_EPS_CHANNELS]; + + /** + * Buffer to use for any data received during the status phase of a + * control transfer. Normally no data is transferred during the status + * phase. This buffer is used as a bit bucket. + */ + uint8_t *status_buf; + + /** + * DMA address for status_buf. + */ + dma_addr_t status_buf_dma; +#define DWC_OTG_HCD_STATUS_BUF_SIZE 64 + + /** + * Structure to allow starting the HCD in a non-interrupt context + * during an OTG role change. + */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) + struct work_struct start_work; +#else + struct delayed_work start_work; +#endif + + /** + * Connection timer. An OTG host must display a message if the device + * does not connect. Started when the VBus power is turned on via + * sysfs attribute "buspower". + */ + struct timer_list conn_timer; + + /* Tasket to do a reset */ + struct tasklet_struct *reset_tasklet; + + /* */ + spinlock_t lock; + +#ifdef DEBUG + uint32_t frrem_samples; + uint64_t frrem_accum; + + uint32_t hfnum_7_samples_a; + uint64_t hfnum_7_frrem_accum_a; + uint32_t hfnum_0_samples_a; + uint64_t hfnum_0_frrem_accum_a; + uint32_t hfnum_other_samples_a; + uint64_t hfnum_other_frrem_accum_a; + + uint32_t hfnum_7_samples_b; + uint64_t hfnum_7_frrem_accum_b; + uint32_t hfnum_0_samples_b; + uint64_t hfnum_0_frrem_accum_b; + uint32_t hfnum_other_samples_b; + uint64_t hfnum_other_frrem_accum_b; +#endif +} dwc_otg_hcd_t; + +/** Gets the dwc_otg_hcd from a struct usb_hcd */ +static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd) +{ + return (dwc_otg_hcd_t *)(hcd->hcd_priv); +} + +/** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */ +static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t *dwc_otg_hcd) +{ + return container_of((void *)dwc_otg_hcd, struct usb_hcd, hcd_priv); +} + +/** @name HCD Create/Destroy Functions */ +/** @{ */ +extern int dwc_otg_hcd_init(struct device *dev); +extern void dwc_otg_hcd_remove(struct device *dev); +/** @} */ + +/** @name Linux HC Driver API Functions */ +/** @{ */ + +extern int dwc_otg_hcd_start(struct usb_hcd *hcd); +extern void dwc_otg_hcd_stop(struct usb_hcd *hcd); +extern int dwc_otg_hcd_get_frame_number(struct usb_hcd *hcd); +extern void dwc_otg_hcd_free(struct usb_hcd *hcd); +extern int dwc_otg_hcd_urb_enqueue(struct usb_hcd *hcd, + struct urb *urb, +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) + int mem_flags +#else + gfp_t mem_flags +#endif + ); +extern int dwc_otg_hcd_urb_dequeue(struct usb_hcd *hcd, +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) +#endif + struct urb *urb, int status); +extern void dwc_otg_hcd_endpoint_disable(struct usb_hcd *hcd, + struct usb_host_endpoint *ep); +extern irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) + , struct pt_regs *regs +#endif + ); +extern int dwc_otg_hcd_hub_status_data(struct usb_hcd *hcd, + char *buf); +extern int dwc_otg_hcd_hub_control(struct usb_hcd *hcd, + u16 typeReq, + u16 wValue, + u16 wIndex, + char *buf, + u16 wLength); + +/** @} */ + +/** @name Transaction Execution Functions */ +/** @{ */ +extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *hcd); +extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *hcd, + dwc_otg_transaction_type_e tr_type); +extern void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t *_hcd, struct urb *urb, + int status); +/** @} */ + +/** @name Interrupt Handler Functions */ +/** @{ */ +extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t *dwc_otg_hcd); +extern int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t *dwc_otg_hcd); +extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *dwc_otg_hcd); +extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd); +extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd); +extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *dwc_otg_hcd); +extern int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t *dwc_otg_hcd); +extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(dwc_otg_hcd_t *dwc_otg_hcd); +extern int32_t dwc_otg_hcd_handle_disconnect_intr(dwc_otg_hcd_t *dwc_otg_hcd); +extern int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t *dwc_otg_hcd); +extern int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t *dwc_otg_hcd, uint32_t num); +extern int32_t dwc_otg_hcd_handle_session_req_intr(dwc_otg_hcd_t *dwc_otg_hcd); +extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr(dwc_otg_hcd_t *dwc_otg_hcd); +/** @} */ + + +/** @name Schedule Queue Functions */ +/** @{ */ + +/* Implemented in dwc_otg_hcd_queue.c */ +extern dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t *hcd, struct urb *urb); +extern void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, struct urb *urb); +extern void dwc_otg_hcd_qh_free(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh); +extern int dwc_otg_hcd_qh_add(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh); +extern void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh); +extern void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int sched_csplit); + +/** Remove and free a QH */ +static inline void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t *hcd, + dwc_otg_qh_t *qh) +{ + dwc_otg_hcd_qh_remove(hcd, qh); + dwc_otg_hcd_qh_free(hcd, qh); +} + +/** Allocates memory for a QH structure. + * @return Returns the memory allocate or NULL on error. */ +static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(void) +{ + return (dwc_otg_qh_t *) kmalloc(sizeof(dwc_otg_qh_t), GFP_KERNEL); +} + +extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(struct urb *urb); +extern void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t *qtd, struct urb *urb); +extern int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t *qtd, dwc_otg_hcd_t *dwc_otg_hcd); + +/** Allocates memory for a QTD structure. + * @return Returns the memory allocate or NULL on error. */ +static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(void) +{ + return (dwc_otg_qtd_t *) kmalloc(sizeof(dwc_otg_qtd_t), GFP_KERNEL); +} + +/** Frees the memory for a QTD structure. QTD should already be removed from + * list. + * @param[in] qtd QTD to free.*/ +static inline void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t *qtd) +{ + kfree(qtd); +} + +/** Removes a QTD from list. + * @param[in] hcd HCD instance. + * @param[in] qtd QTD to remove from list. */ +static inline void dwc_otg_hcd_qtd_remove(dwc_otg_hcd_t *hcd, dwc_otg_qtd_t *qtd) +{ + unsigned long flags; + SPIN_LOCK_IRQSAVE(&hcd->lock, flags); + list_del(&qtd->qtd_list_entry); + SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags); +} + +/** Remove and free a QTD */ +static inline void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t *hcd, dwc_otg_qtd_t *qtd) +{ + dwc_otg_hcd_qtd_remove(hcd, qtd); + dwc_otg_hcd_qtd_free(qtd); +} + +/** @} */ + + +/** @name Internal Functions */ +/** @{ */ +dwc_otg_qh_t *dwc_urb_to_qh(struct urb *urb); +void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *hcd); +void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *hcd); +/** @} */ + +/** Gets the usb_host_endpoint associated with an URB. */ +static inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *urb) +{ + struct usb_device *dev = urb->dev; + int ep_num = usb_pipeendpoint(urb->pipe); + + if (usb_pipein(urb->pipe)) + return dev->ep_in[ep_num]; + else + return dev->ep_out[ep_num]; +} + +/** + * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is + * qualified with its direction (possible 32 endpoints per device). + */ +#define dwc_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \ + ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4) + +/** Gets the QH that contains the list_head */ +#define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry) + +/** Gets the QTD that contains the list_head */ +#define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry) + +/** Check if QH is non-periodic */ +#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == USB_ENDPOINT_XFER_BULK) || \ + (_qh_ptr_->ep_type == USB_ENDPOINT_XFER_CONTROL)) + +/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */ +#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03)) + +/** Packet size for any kind of endpoint descriptor */ +#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) + +/** + * Returns true if _frame1 is less than or equal to _frame2. The comparison is + * done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the + * frame number when the max frame number is reached. + */ +static inline int dwc_frame_num_le(uint16_t frame1, uint16_t frame2) +{ + return ((frame2 - frame1) & DWC_HFNUM_MAX_FRNUM) <= + (DWC_HFNUM_MAX_FRNUM >> 1); +} + +/** + * Returns true if _frame1 is greater than _frame2. The comparison is done + * modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame + * number when the max frame number is reached. + */ +static inline int dwc_frame_num_gt(uint16_t frame1, uint16_t frame2) +{ + return (frame1 != frame2) && + (((frame1 - frame2) & DWC_HFNUM_MAX_FRNUM) < + (DWC_HFNUM_MAX_FRNUM >> 1)); +} + +/** + * Increments _frame by the amount specified by _inc. The addition is done + * modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value. + */ +static inline uint16_t dwc_frame_num_inc(uint16_t frame, uint16_t inc) +{ + return (frame + inc) & DWC_HFNUM_MAX_FRNUM; +} + +static inline uint16_t dwc_full_frame_num(uint16_t frame) +{ + return (frame & DWC_HFNUM_MAX_FRNUM) >> 3; +} + +static inline uint16_t dwc_micro_frame_num(uint16_t frame) +{ + return frame & 0x7; +} + +#ifdef DEBUG +/** + * Macro to sample the remaining PHY clocks left in the current frame. This + * may be used during debugging to determine the average time it takes to + * execute sections of code. There are two possible sample points, "a" and + * "b", so the _letter argument must be one of these values. + * + * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For + * example, "cat /sys/devices/lm0/hcd_frrem". + */ +#define dwc_sample_frrem(_hcd, _qh, _letter) \ +{ \ + hfnum_data_t hfnum; \ + dwc_otg_qtd_t *qtd; \ + qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \ + if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \ + hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum); \ + switch (hfnum.b.frnum & 0x7) { \ + case 7: \ + _hcd->hfnum_7_samples_##_letter++; \ + _hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \ + break; \ + case 0: \ + _hcd->hfnum_0_samples_##_letter++; \ + _hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \ + break; \ + default: \ + _hcd->hfnum_other_samples_##_letter++; \ + _hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \ + break; \ + } \ + } \ +} +#else +#define dwc_sample_frrem(_hcd, _qh, _letter) +#endif +#endif +#endif /* DWC_DEVICE_ONLY */ diff --git a/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c new file mode 100644 index 0000000000..bdf2db99f3 --- /dev/null +++ b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c @@ -0,0 +1,1873 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $ + * $Revision: 1.6.2.1 $ + * $Date: 2009-04-22 03:48:22 $ + * $Change: 1117667 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and + * redistribute this Software in source and binary forms, with or without + * modification, provided that redistributions of source code must retain this + * notice. You may not view, use, disclose, copy or distribute this file or + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * ========================================================================== */ +#ifndef DWC_DEVICE_ONLY + +#include + +#include "dwc_otg_driver.h" +#include "dwc_otg_hcd.h" +#include "dwc_otg_regs.h" + +/** @file + * This file contains the implementation of the HCD Interrupt handlers. + */ + +/** This function handles interrupts for the HCD. */ +int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t *dwc_otg_hcd) +{ + int retval = 0; + + dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; + gintsts_data_t gintsts; +#ifdef DEBUG + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; +#endif + + /* Check if HOST Mode */ + if (dwc_otg_is_host_mode(core_if)) { + gintsts.d32 = dwc_otg_read_core_intr(core_if); + if (!gintsts.d32) { + return 0; + } + +#ifdef DEBUG + /* Don't print debug message in the interrupt handler on SOF */ +# ifndef DEBUG_SOF + if (gintsts.d32 != DWC_SOF_INTR_MASK) +# endif + DWC_DEBUGPL(DBG_HCD, "\n"); +#endif + +#ifdef DEBUG +# ifndef DEBUG_SOF + if (gintsts.d32 != DWC_SOF_INTR_MASK) +# endif + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n", gintsts.d32); +#endif + if (gintsts.b.usbreset) { + DWC_PRINT("Usb Reset In Host Mode\n"); + } + + + if (gintsts.b.sofintr) { + retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd); + } + if (gintsts.b.rxstsqlvl) { + retval |= dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd); + } + if (gintsts.b.nptxfempty) { + retval |= dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd); + } + if (gintsts.b.i2cintr) { + /** @todo Implement i2cintr handler. */ + } + if (gintsts.b.portintr) { + retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd); + } + if (gintsts.b.hcintr) { + retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd); + } + if (gintsts.b.ptxfempty) { + retval |= dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd); + } +#ifdef DEBUG +# ifndef DEBUG_SOF + if (gintsts.d32 != DWC_SOF_INTR_MASK) +# endif + { + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Finished Servicing Interrupts\n"); + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n", + dwc_read_reg32(&global_regs->gintsts)); + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n", + dwc_read_reg32(&global_regs->gintmsk)); + } +#endif + +#ifdef DEBUG +# ifndef DEBUG_SOF + if (gintsts.d32 != DWC_SOF_INTR_MASK) +# endif + DWC_DEBUGPL(DBG_HCD, "\n"); +#endif + + } + + S3C2410X_CLEAR_EINTPEND(); + + return retval; +} + +#ifdef DWC_TRACK_MISSED_SOFS +#warning Compiling code to track missed SOFs +#define FRAME_NUM_ARRAY_SIZE 1000 +/** + * This function is for debug only. + */ +static inline void track_missed_sofs(uint16_t curr_frame_number) +{ + static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE]; + static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE]; + static int frame_num_idx = 0; + static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM; + static int dumped_frame_num_array = 0; + + if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) { + if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) != curr_frame_number) { + frame_num_array[frame_num_idx] = curr_frame_number; + last_frame_num_array[frame_num_idx++] = last_frame_num; + } + } else if (!dumped_frame_num_array) { + int i; + printk(KERN_EMERG USB_DWC "Frame Last Frame\n"); + printk(KERN_EMERG USB_DWC "----- ----------\n"); + for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) { + printk(KERN_EMERG USB_DWC "0x%04x 0x%04x\n", + frame_num_array[i], last_frame_num_array[i]); + } + dumped_frame_num_array = 1; + } + last_frame_num = curr_frame_number; +} +#endif + +/** + * Handles the start-of-frame interrupt in host mode. Non-periodic + * transactions may be queued to the DWC_otg controller for the current + * (micro)frame. Periodic transactions may be queued to the controller for the + * next (micro)frame. + */ +int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t *hcd) +{ + hfnum_data_t hfnum; + struct list_head *qh_entry; + dwc_otg_qh_t *qh; + dwc_otg_transaction_type_e tr_type; + gintsts_data_t gintsts = {.d32 = 0}; + + hfnum.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hfnum); + +#ifdef DEBUG_SOF + DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n"); +#endif + hcd->frame_number = hfnum.b.frnum; + +#ifdef DEBUG + hcd->frrem_accum += hfnum.b.frrem; + hcd->frrem_samples++; +#endif + +#ifdef DWC_TRACK_MISSED_SOFS + track_missed_sofs(hcd->frame_number); +#endif + + /* Determine whether any periodic QHs should be executed. */ + qh_entry = hcd->periodic_sched_inactive.next; + while (qh_entry != &hcd->periodic_sched_inactive) { + qh = list_entry(qh_entry, dwc_otg_qh_t, qh_list_entry); + qh_entry = qh_entry->next; + if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) { + /* + * Move QH to the ready list to be executed next + * (micro)frame. + */ + list_move(&qh->qh_list_entry, &hcd->periodic_sched_ready); + } + } + + tr_type = dwc_otg_hcd_select_transactions(hcd); + if (tr_type != DWC_OTG_TRANSACTION_NONE) { + dwc_otg_hcd_queue_transactions(hcd, tr_type); + } + + /* Clear interrupt */ + gintsts.b.sofintr = 1; + dwc_write_reg32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32); + + return 1; +} + +/** Handles the Rx Status Queue Level Interrupt, which indicates that there is at + * least one packet in the Rx FIFO. The packets are moved from the FIFO to + * memory if the DWC_otg controller is operating in Slave mode. */ +int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *dwc_otg_hcd) +{ + host_grxsts_data_t grxsts; + dwc_hc_t *hc = NULL; + + DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n"); + + grxsts.d32 = dwc_read_reg32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp); + + hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum]; + + /* Packet Status */ + DWC_DEBUGPL(DBG_HCDV, " Ch num = %d\n", grxsts.b.chnum); + DWC_DEBUGPL(DBG_HCDV, " Count = %d\n", grxsts.b.bcnt); + DWC_DEBUGPL(DBG_HCDV, " DPID = %d, hc.dpid = %d\n", grxsts.b.dpid, hc->data_pid_start); + DWC_DEBUGPL(DBG_HCDV, " PStatus = %d\n", grxsts.b.pktsts); + + switch (grxsts.b.pktsts) { + case DWC_GRXSTS_PKTSTS_IN: + /* Read the data into the host buffer. */ + if (grxsts.b.bcnt > 0) { + dwc_otg_read_packet(dwc_otg_hcd->core_if, + hc->xfer_buff, + grxsts.b.bcnt); + + /* Update the HC fields for the next packet received. */ + hc->xfer_count += grxsts.b.bcnt; + hc->xfer_buff += grxsts.b.bcnt; + } + + case DWC_GRXSTS_PKTSTS_IN_XFER_COMP: + case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR: + case DWC_GRXSTS_PKTSTS_CH_HALTED: + /* Handled in interrupt, just ignore data */ + break; + default: + DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n", grxsts.b.pktsts); + break; + } + + return 1; +} + +/** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More + * data packets may be written to the FIFO for OUT transfers. More requests + * may be written to the non-periodic request queue for IN transfers. This + * interrupt is enabled only in Slave mode. */ +int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd) +{ + DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n"); + dwc_otg_hcd_queue_transactions(dwc_otg_hcd, + DWC_OTG_TRANSACTION_NON_PERIODIC); + return 1; +} + +/** This interrupt occurs when the periodic Tx FIFO is half-empty. More data + * packets may be written to the FIFO for OUT transfers. More requests may be + * written to the periodic request queue for IN transfers. This interrupt is + * enabled only in Slave mode. */ +int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd) +{ + DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n"); + dwc_otg_hcd_queue_transactions(dwc_otg_hcd, + DWC_OTG_TRANSACTION_PERIODIC); + return 1; +} + +/** There are multiple conditions that can cause a port interrupt. This function + * determines which interrupt conditions have occurred and handles them + * appropriately. */ +int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t *dwc_otg_hcd) +{ + int retval = 0; + hprt0_data_t hprt0; + hprt0_data_t hprt0_modify; + + hprt0.d32 = dwc_read_reg32(dwc_otg_hcd->core_if->host_if->hprt0); + hprt0_modify.d32 = dwc_read_reg32(dwc_otg_hcd->core_if->host_if->hprt0); + + /* Clear appropriate bits in HPRT0 to clear the interrupt bit in + * GINTSTS */ + + hprt0_modify.b.prtena = 0; + hprt0_modify.b.prtconndet = 0; + hprt0_modify.b.prtenchng = 0; + hprt0_modify.b.prtovrcurrchng = 0; + + /* Port Connect Detected + * Set flag and clear if detected */ + if (hprt0.b.prtconndet) { + DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x " + "Port Connect Detected--\n", hprt0.d32); + dwc_otg_hcd->flags.b.port_connect_status_change = 1; + dwc_otg_hcd->flags.b.port_connect_status = 1; + hprt0_modify.b.prtconndet = 1; + + /* B-Device has connected, Delete the connection timer. */ + del_timer( &dwc_otg_hcd->conn_timer ); + + /* The Hub driver asserts a reset when it sees port connect + * status change flag */ + retval |= 1; + } + + /* Port Enable Changed + * Clear if detected - Set internal flag if disabled */ + if (hprt0.b.prtenchng) { + DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x " + "Port Enable Changed--\n", hprt0.d32); + hprt0_modify.b.prtenchng = 1; + if (hprt0.b.prtena == 1) { + int do_reset = 0; + dwc_otg_core_params_t *params = dwc_otg_hcd->core_if->core_params; + dwc_otg_core_global_regs_t *global_regs = dwc_otg_hcd->core_if->core_global_regs; + dwc_otg_host_if_t *host_if = dwc_otg_hcd->core_if->host_if; + + /* Check if we need to adjust the PHY clock speed for + * low power and adjust it */ + if (params->host_support_fs_ls_low_power) { + gusbcfg_data_t usbcfg; + + usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); + + if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED || + hprt0.b.prtspd == DWC_HPRT0_PRTSPD_FULL_SPEED) { + /* + * Low power + */ + hcfg_data_t hcfg; + if (usbcfg.b.phylpwrclksel == 0) { + /* Set PHY low power clock select for FS/LS devices */ + usbcfg.b.phylpwrclksel = 1; + dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); + do_reset = 1; + } + + hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg); + + if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED && + params->host_ls_low_power_phy_clk == + DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) { + /* 6 MHZ */ + DWC_DEBUGPL(DBG_CIL, "FS_PHY programming HCFG to 6 MHz (Low Power)\n"); + if (hcfg.b.fslspclksel != DWC_HCFG_6_MHZ) { + hcfg.b.fslspclksel = DWC_HCFG_6_MHZ; + dwc_write_reg32(&host_if->host_global_regs->hcfg, + hcfg.d32); + do_reset = 1; + } + } else { + /* 48 MHZ */ + DWC_DEBUGPL(DBG_CIL, "FS_PHY programming HCFG to 48 MHz ()\n"); + if (hcfg.b.fslspclksel != DWC_HCFG_48_MHZ) { + hcfg.b.fslspclksel = DWC_HCFG_48_MHZ; + dwc_write_reg32(&host_if->host_global_regs->hcfg, + hcfg.d32); + do_reset = 1; + } + } + } else { + /* + * Not low power + */ + if (usbcfg.b.phylpwrclksel == 1) { + usbcfg.b.phylpwrclksel = 0; + dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); + do_reset = 1; + } + } + + if (do_reset) { + tasklet_schedule(dwc_otg_hcd->reset_tasklet); + } + } + + if (!do_reset) { + /* Port has been enabled set the reset change flag */ + dwc_otg_hcd->flags.b.port_reset_change = 1; + } + } else { + dwc_otg_hcd->flags.b.port_enable_change = 1; + } + retval |= 1; + } + + /** Overcurrent Change Interrupt */ + if (hprt0.b.prtovrcurrchng) { + DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x " + "Port Overcurrent Changed--\n", hprt0.d32); + dwc_otg_hcd->flags.b.port_over_current_change = 1; + hprt0_modify.b.prtovrcurrchng = 1; + retval |= 1; + } + + /* Clear Port Interrupts */ + dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32); + + return retval; +} + +/** This interrupt indicates that one or more host channels has a pending + * interrupt. There are multiple conditions that can cause each host channel + * interrupt. This function determines which conditions have occurred for each + * host channel interrupt and handles them appropriately. */ +int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t *dwc_otg_hcd) +{ + int i; + int retval = 0; + haint_data_t haint; + + /* Clear appropriate bits in HCINTn to clear the interrupt bit in + * GINTSTS */ + + haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if); + + for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) { + if (haint.b2.chint & (1 << i)) { + retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i); + } + } + + return retval; +} + +/* Macro used to clear one channel interrupt */ +#define clear_hc_int(_hc_regs_, _intr_) \ +do { \ + hcint_data_t hcint_clear = {.d32 = 0}; \ + hcint_clear.b._intr_ = 1; \ + dwc_write_reg32(&(_hc_regs_)->hcint, hcint_clear.d32); \ +} while (0) + +/* + * Macro used to disable one channel interrupt. Channel interrupts are + * disabled when the channel is halted or released by the interrupt handler. + * There is no need to handle further interrupts of that type until the + * channel is re-assigned. In fact, subsequent handling may cause crashes + * because the channel structures are cleaned up when the channel is released. + */ +#define disable_hc_int(_hc_regs_, _intr_) \ +do { \ + hcintmsk_data_t hcintmsk = {.d32 = 0}; \ + hcintmsk.b._intr_ = 1; \ + dwc_modify_reg32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \ +} while (0) + +/** + * Gets the actual length of a transfer after the transfer halts. _halt_status + * holds the reason for the halt. + * + * For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE, + * *short_read is set to 1 upon return if less than the requested + * number of bytes were transferred. Otherwise, *short_read is set to 0 upon + * return. short_read may also be NULL on entry, in which case it remains + * unchanged. + */ +static uint32_t get_actual_xfer_length(dwc_hc_t *hc, + dwc_otg_hc_regs_t *hc_regs, + dwc_otg_qtd_t *qtd, + dwc_otg_halt_status_e halt_status, + int *short_read) +{ + hctsiz_data_t hctsiz; + uint32_t length; + + if (short_read != NULL) { + *short_read = 0; + } + hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); + + if (halt_status == DWC_OTG_HC_XFER_COMPLETE) { + if (hc->ep_is_in) { + length = hc->xfer_len - hctsiz.b.xfersize; + if (short_read != NULL) { + *short_read = (hctsiz.b.xfersize != 0); + } + } else if (hc->qh->do_split) { + length = qtd->ssplit_out_xfer_count; + } else { + length = hc->xfer_len; + } + } else { + /* + * Must use the hctsiz.pktcnt field to determine how much data + * has been transferred. This field reflects the number of + * packets that have been transferred via the USB. This is + * always an integral number of packets if the transfer was + * halted before its normal completion. (Can't use the + * hctsiz.xfersize field because that reflects the number of + * bytes transferred via the AHB, not the USB). + */ + length = (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet; + } + + return length; +} + +/** + * Updates the state of the URB after a Transfer Complete interrupt on the + * host channel. Updates the actual_length field of the URB based on the + * number of bytes transferred via the host channel. Sets the URB status + * if the data transfer is finished. + * + * @return 1 if the data transfer specified by the URB is completely finished, + * 0 otherwise. + */ +static int update_urb_state_xfer_comp(dwc_hc_t *hc, + dwc_otg_hc_regs_t *hc_regs, + struct urb *urb, + dwc_otg_qtd_t *qtd) +{ + int xfer_done = 0; + int short_read = 0; + int overflow_read=0; + uint32_t len = 0; + int max_packet; + + len = get_actual_xfer_length(hc, hc_regs, qtd, + DWC_OTG_HC_XFER_COMPLETE, + &short_read); + + /* Data overflow case: by Steven */ + if (len > urb->transfer_buffer_length) { + len = urb->transfer_buffer_length; + overflow_read = 1; + } + + /* non DWORD-aligned buffer case handling. */ + if (((uint32_t)hc->xfer_buff & 0x3) && len && hc->qh->dw_align_buf && hc->ep_is_in) { + memcpy(urb->transfer_buffer + urb->actual_length, hc->qh->dw_align_buf, len); + } + urb->actual_length +=len; + + max_packet = usb_maxpacket(urb->dev, urb->pipe, !usb_pipein(urb->pipe)); + if((len) && usb_pipebulk(urb->pipe) && + (urb->transfer_flags & URB_ZERO_PACKET) && + (urb->actual_length == urb->transfer_buffer_length) && + (!(urb->transfer_buffer_length % max_packet))) { + } else if (short_read || urb->actual_length == urb->transfer_buffer_length) { + xfer_done = 1; + if (short_read && (urb->transfer_flags & URB_SHORT_NOT_OK)) { + urb->status = -EREMOTEIO; + } else if (overflow_read) { + urb->status = -EOVERFLOW; + } else { + urb->status = 0; + } + } + +#ifdef DEBUG + { + hctsiz_data_t hctsiz; + hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); + DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n", + __func__, (hc->ep_is_in ? "IN" : "OUT"), hc->hc_num); + DWC_DEBUGPL(DBG_HCDV, " hc->xfer_len %d\n", hc->xfer_len); + DWC_DEBUGPL(DBG_HCDV, " hctsiz.xfersize %d\n", hctsiz.b.xfersize); + DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n", + urb->transfer_buffer_length); + DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n", urb->actual_length); + DWC_DEBUGPL(DBG_HCDV, " short_read %d, xfer_done %d\n", + short_read, xfer_done); + } +#endif + + return xfer_done; +} + +/* + * Save the starting data toggle for the next transfer. The data toggle is + * saved in the QH for non-control transfers and it's saved in the QTD for + * control transfers. + */ +static void save_data_toggle(dwc_hc_t *hc, + dwc_otg_hc_regs_t *hc_regs, + dwc_otg_qtd_t *qtd) +{ + hctsiz_data_t hctsiz; + hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); + + if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) { + dwc_otg_qh_t *qh = hc->qh; + if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) { + qh->data_toggle = DWC_OTG_HC_PID_DATA0; + } else { + qh->data_toggle = DWC_OTG_HC_PID_DATA1; + } + } else { + if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) { + qtd->data_toggle = DWC_OTG_HC_PID_DATA0; + } else { + qtd->data_toggle = DWC_OTG_HC_PID_DATA1; + } + } +} + +/** + * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic + * QHs, removes the QH from the active non-periodic schedule. If any QTDs are + * still linked to the QH, the QH is added to the end of the inactive + * non-periodic schedule. For periodic QHs, removes the QH from the periodic + * schedule if no more QTDs are linked to the QH. + */ +static void deactivate_qh(dwc_otg_hcd_t *hcd, + dwc_otg_qh_t *qh, + int free_qtd) +{ + int continue_split = 0; + dwc_otg_qtd_t *qtd; + + DWC_DEBUGPL(DBG_HCDV, " %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd); + + qtd = list_entry(qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); + + if (qtd->complete_split) { + continue_split = 1; + } else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID || + qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) { + continue_split = 1; + } + + if (free_qtd) { + dwc_otg_hcd_qtd_remove_and_free(hcd, qtd); + continue_split = 0; + } + + qh->channel = NULL; + qh->qtd_in_process = NULL; + dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split); +} + +/** + * Updates the state of an Isochronous URB when the transfer is stopped for + * any reason. The fields of the current entry in the frame descriptor array + * are set based on the transfer state and the input _halt_status. Completes + * the Isochronous URB if all the URB frames have been completed. + * + * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be + * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE. + */ +static dwc_otg_halt_status_e +update_isoc_urb_state(dwc_otg_hcd_t *hcd, + dwc_hc_t *hc, + dwc_otg_hc_regs_t *hc_regs, + dwc_otg_qtd_t *qtd, + dwc_otg_halt_status_e halt_status) +{ + struct urb *urb = qtd->urb; + dwc_otg_halt_status_e ret_val = halt_status; + struct usb_iso_packet_descriptor *frame_desc; + + frame_desc = &urb->iso_frame_desc[qtd->isoc_frame_index]; + switch (halt_status) { + case DWC_OTG_HC_XFER_COMPLETE: + frame_desc->status = 0; + frame_desc->actual_length = + get_actual_xfer_length(hc, hc_regs, qtd, + halt_status, NULL); + + /* non DWORD-aligned buffer case handling. */ + if (frame_desc->actual_length && ((uint32_t)hc->xfer_buff & 0x3) && + hc->qh->dw_align_buf && hc->ep_is_in) { + memcpy(urb->transfer_buffer + frame_desc->offset + qtd->isoc_split_offset, + hc->qh->dw_align_buf, frame_desc->actual_length); + + } + + break; + case DWC_OTG_HC_XFER_FRAME_OVERRUN: + printk("DWC_OTG_HC_XFER_FRAME_OVERRUN: %d\n", halt_status); + urb->error_count++; + if (hc->ep_is_in) { + frame_desc->status = -ENOSR; + } else { + frame_desc->status = -ECOMM; + } + frame_desc->actual_length = 0; + break; + case DWC_OTG_HC_XFER_BABBLE_ERR: + printk("DWC_OTG_HC_XFER_BABBLE_ERR: %d\n", halt_status); + urb->error_count++; + frame_desc->status = -EOVERFLOW; + /* Don't need to update actual_length in this case. */ + break; + case DWC_OTG_HC_XFER_XACT_ERR: + printk("DWC_OTG_HC_XFER_XACT_ERR: %d\n", halt_status); + urb->error_count++; + frame_desc->status = -EPROTO; + frame_desc->actual_length = + get_actual_xfer_length(hc, hc_regs, qtd, + halt_status, NULL); + + /* non DWORD-aligned buffer case handling. */ + if (frame_desc->actual_length && ((uint32_t)hc->xfer_buff & 0x3) && + hc->qh->dw_align_buf && hc->ep_is_in) { + memcpy(urb->transfer_buffer + frame_desc->offset + qtd->isoc_split_offset, + hc->qh->dw_align_buf, frame_desc->actual_length); + + } + break; + default: + + DWC_ERROR("%s: Unhandled _halt_status (%d)\n", __func__, + halt_status); + BUG(); + break; + } + + if (++qtd->isoc_frame_index == urb->number_of_packets) { + /* + * urb->status is not used for isoc transfers. + * The individual frame_desc statuses are used instead. + */ + dwc_otg_hcd_complete_urb(hcd, urb, 0); + ret_val = DWC_OTG_HC_XFER_URB_COMPLETE; + } else { + ret_val = DWC_OTG_HC_XFER_COMPLETE; + } + + return ret_val; +} + +/** + * Releases a host channel for use by other transfers. Attempts to select and + * queue more transactions since at least one host channel is available. + * + * @param hcd The HCD state structure. + * @param hc The host channel to release. + * @param qtd The QTD associated with the host channel. This QTD may be freed + * if the transfer is complete or an error has occurred. + * @param halt_status Reason the channel is being released. This status + * determines the actions taken by this function. + */ +static void release_channel(dwc_otg_hcd_t *hcd, + dwc_hc_t *hc, + dwc_otg_qtd_t *qtd, + dwc_otg_halt_status_e halt_status) +{ + dwc_otg_transaction_type_e tr_type; + int free_qtd; + + DWC_DEBUGPL(DBG_HCDV, " %s: channel %d, halt_status %d\n", + __func__, hc->hc_num, halt_status); + + switch (halt_status) { + case DWC_OTG_HC_XFER_URB_COMPLETE: + free_qtd = 1; + break; + case DWC_OTG_HC_XFER_AHB_ERR: + case DWC_OTG_HC_XFER_STALL: + case DWC_OTG_HC_XFER_BABBLE_ERR: + free_qtd = 1; + break; + case DWC_OTG_HC_XFER_XACT_ERR: + if (qtd->error_count >= 3) { + DWC_DEBUGPL(DBG_HCDV, " Complete URB with transaction error\n"); + free_qtd = 1; + qtd->urb->status = -EPROTO; + dwc_otg_hcd_complete_urb(hcd, qtd->urb, -EPROTO); + } else { + free_qtd = 0; + } + break; + case DWC_OTG_HC_XFER_URB_DEQUEUE: + /* + * The QTD has already been removed and the QH has been + * deactivated. Don't want to do anything except release the + * host channel and try to queue more transfers. + */ + goto cleanup; + case DWC_OTG_HC_XFER_NO_HALT_STATUS: + DWC_ERROR("%s: No halt_status, channel %d\n", __func__, hc->hc_num); + free_qtd = 0; + break; + default: + free_qtd = 0; + break; + } + + deactivate_qh(hcd, hc->qh, free_qtd); + + cleanup: + /* + * Release the host channel for use by other transfers. The cleanup + * function clears the channel interrupt enables and conditions, so + * there's no need to clear the Channel Halted interrupt separately. + */ + dwc_otg_hc_cleanup(hcd->core_if, hc); + list_add_tail(&hc->hc_list_entry, &hcd->free_hc_list); + + switch (hc->ep_type) { + case DWC_OTG_EP_TYPE_CONTROL: + case DWC_OTG_EP_TYPE_BULK: + hcd->non_periodic_channels--; + break; + + default: + /* + * Don't release reservations for periodic channels here. + * That's done when a periodic transfer is descheduled (i.e. + * when the QH is removed from the periodic schedule). + */ + break; + } + + /* Try to queue more transfers now that there's a free channel. */ + tr_type = dwc_otg_hcd_select_transactions(hcd); + if (tr_type != DWC_OTG_TRANSACTION_NONE) { + dwc_otg_hcd_queue_transactions(hcd, tr_type); + } +} + +/** + * Halts a host channel. If the channel cannot be halted immediately because + * the request queue is full, this function ensures that the FIFO empty + * interrupt for the appropriate queue is enabled so that the halt request can + * be queued when there is space in the request queue. + * + * This function may also be called in DMA mode. In that case, the channel is + * simply released since the core always halts the channel automatically in + * DMA mode. + */ +static void halt_channel(dwc_otg_hcd_t *hcd, + dwc_hc_t *hc, + dwc_otg_qtd_t *qtd, + dwc_otg_halt_status_e halt_status) +{ + if (hcd->core_if->dma_enable) { + release_channel(hcd, hc, qtd, halt_status); + return; + } + + /* Slave mode processing... */ + dwc_otg_hc_halt(hcd->core_if, hc, halt_status); + + if (hc->halt_on_queue) { + gintmsk_data_t gintmsk = {.d32 = 0}; + dwc_otg_core_global_regs_t *global_regs; + global_regs = hcd->core_if->core_global_regs; + + if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL || + hc->ep_type == DWC_OTG_EP_TYPE_BULK) { + /* + * Make sure the Non-periodic Tx FIFO empty interrupt + * is enabled so that the non-periodic schedule will + * be processed. + */ + gintmsk.b.nptxfempty = 1; + dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32); + } else { + /* + * Move the QH from the periodic queued schedule to + * the periodic assigned schedule. This allows the + * halt to be queued when the periodic schedule is + * processed. + */ + list_move(&hc->qh->qh_list_entry, + &hcd->periodic_sched_assigned); + + /* + * Make sure the Periodic Tx FIFO Empty interrupt is + * enabled so that the periodic schedule will be + * processed. + */ + gintmsk.b.ptxfempty = 1; + dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32); + } + } +} + +/** + * Performs common cleanup for non-periodic transfers after a Transfer + * Complete interrupt. This function should be called after any endpoint type + * specific handling is finished to release the host channel. + */ +static void complete_non_periodic_xfer(dwc_otg_hcd_t *hcd, + dwc_hc_t *hc, + dwc_otg_hc_regs_t *hc_regs, + dwc_otg_qtd_t *qtd, + dwc_otg_halt_status_e halt_status) +{ + hcint_data_t hcint; + + qtd->error_count = 0; + + hcint.d32 = dwc_read_reg32(&hc_regs->hcint); + if (hcint.b.nyet) { + /* + * Got a NYET on the last transaction of the transfer. This + * means that the endpoint should be in the PING state at the + * beginning of the next transfer. + */ + hc->qh->ping_state = 1; + clear_hc_int(hc_regs, nyet); + } + + /* + * Always halt and release the host channel to make it available for + * more transfers. There may still be more phases for a control + * transfer or more data packets for a bulk transfer at this point, + * but the host channel is still halted. A channel will be reassigned + * to the transfer when the non-periodic schedule is processed after + * the channel is released. This allows transactions to be queued + * properly via dwc_otg_hcd_queue_transactions, which also enables the + * Tx FIFO Empty interrupt if necessary. + */ + if (hc->ep_is_in) { + /* + * IN transfers in Slave mode require an explicit disable to + * halt the channel. (In DMA mode, this call simply releases + * the channel.) + */ + halt_channel(hcd, hc, qtd, halt_status); + } else { + /* + * The channel is automatically disabled by the core for OUT + * transfers in Slave mode. + */ + release_channel(hcd, hc, qtd, halt_status); + } +} + +/** + * Performs common cleanup for periodic transfers after a Transfer Complete + * interrupt. This function should be called after any endpoint type specific + * handling is finished to release the host channel. + */ +static void complete_periodic_xfer(dwc_otg_hcd_t *hcd, + dwc_hc_t *hc, + dwc_otg_hc_regs_t *hc_regs, + dwc_otg_qtd_t *qtd, + dwc_otg_halt_status_e halt_status) +{ + hctsiz_data_t hctsiz; + qtd->error_count = 0; + + hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); + if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) { + /* Core halts channel in these cases. */ + release_channel(hcd, hc, qtd, halt_status); + } else { + /* Flush any outstanding requests from the Tx queue. */ + halt_channel(hcd, hc, qtd, halt_status); + } +} + +/** + * Handles a host channel Transfer Complete interrupt. This handler may be + * called in either DMA mode or Slave mode. + */ +static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t *hcd, + dwc_hc_t *hc, + dwc_otg_hc_regs_t *hc_regs, + dwc_otg_qtd_t *qtd) +{ + int urb_xfer_done; + dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE; + struct urb *urb = qtd->urb; + int pipe_type = usb_pipetype(urb->pipe); + + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " + "Transfer Complete--\n", hc->hc_num); + + /* + * Handle xfer complete on CSPLIT. + */ + if (hc->qh->do_split) { + qtd->complete_split = 0; + } + + /* Update the QTD and URB states. */ + switch (pipe_type) { + case PIPE_CONTROL: + switch (qtd->control_phase) { + case DWC_OTG_CONTROL_SETUP: + if (urb->transfer_buffer_length > 0) { + qtd->control_phase = DWC_OTG_CONTROL_DATA; + } else { + qtd->control_phase = DWC_OTG_CONTROL_STATUS; + } + DWC_DEBUGPL(DBG_HCDV, " Control setup transaction done\n"); + halt_status = DWC_OTG_HC_XFER_COMPLETE; + break; + case DWC_OTG_CONTROL_DATA: { + urb_xfer_done = update_urb_state_xfer_comp(hc, hc_regs, urb, qtd); + if (urb_xfer_done) { + qtd->control_phase = DWC_OTG_CONTROL_STATUS; + DWC_DEBUGPL(DBG_HCDV, " Control data transfer done\n"); + } else { + save_data_toggle(hc, hc_regs, qtd); + } + halt_status = DWC_OTG_HC_XFER_COMPLETE; + break; + } + case DWC_OTG_CONTROL_STATUS: + DWC_DEBUGPL(DBG_HCDV, " Control transfer complete\n"); + if (urb->status == -EINPROGRESS) { + urb->status = 0; + } + dwc_otg_hcd_complete_urb(hcd, urb, urb->status); + halt_status = DWC_OTG_HC_XFER_URB_COMPLETE; + break; + } + + complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status); + break; + case PIPE_BULK: + DWC_DEBUGPL(DBG_HCDV, " Bulk transfer complete\n"); + urb_xfer_done = update_urb_state_xfer_comp(hc, hc_regs, urb, qtd); + if (urb_xfer_done) { + dwc_otg_hcd_complete_urb(hcd, urb, urb->status); + halt_status = DWC_OTG_HC_XFER_URB_COMPLETE; + } else { + halt_status = DWC_OTG_HC_XFER_COMPLETE; + } + + save_data_toggle(hc, hc_regs, qtd); + complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status); + break; + case PIPE_INTERRUPT: + DWC_DEBUGPL(DBG_HCDV, " Interrupt transfer complete\n"); + update_urb_state_xfer_comp(hc, hc_regs, urb, qtd); + + /* + * Interrupt URB is done on the first transfer complete + * interrupt. + */ + dwc_otg_hcd_complete_urb(hcd, urb, urb->status); + save_data_toggle(hc, hc_regs, qtd); + complete_periodic_xfer(hcd, hc, hc_regs, qtd, + DWC_OTG_HC_XFER_URB_COMPLETE); + break; + case PIPE_ISOCHRONOUS: + DWC_DEBUGPL(DBG_HCDV, " Isochronous transfer complete\n"); + if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) { + halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd, + DWC_OTG_HC_XFER_COMPLETE); + } + complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status); + break; + } + + disable_hc_int(hc_regs, xfercompl); + + return 1; +} + +/** + * Handles a host channel STALL interrupt. This handler may be called in + * either DMA mode or Slave mode. + */ +static int32_t handle_hc_stall_intr(dwc_otg_hcd_t *hcd, + dwc_hc_t *hc, + dwc_otg_hc_regs_t *hc_regs, + dwc_otg_qtd_t *qtd) +{ + struct urb *urb = qtd->urb; + int pipe_type = usb_pipetype(urb->pipe); + + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " + "STALL Received--\n", hc->hc_num); + + if (pipe_type == PIPE_CONTROL) { + dwc_otg_hcd_complete_urb(hcd, urb, -EPIPE); + } + + if (pipe_type == PIPE_BULK || pipe_type == PIPE_INTERRUPT) { + dwc_otg_hcd_complete_urb(hcd, urb, -EPIPE); + /* + * USB protocol requires resetting the data toggle for bulk + * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT) + * setup command is issued to the endpoint. Anticipate the + * CLEAR_FEATURE command since a STALL has occurred and reset + * the data toggle now. + */ + hc->qh->data_toggle = 0; + } + + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL); + + disable_hc_int(hc_regs, stall); + + return 1; +} + +/* + * Updates the state of the URB when a transfer has been stopped due to an + * abnormal condition before the transfer completes. Modifies the + * actual_length field of the URB to reflect the number of bytes that have + * actually been transferred via the host channel. + */ +static void update_urb_state_xfer_intr(dwc_hc_t *hc, + dwc_otg_hc_regs_t *hc_regs, + struct urb *urb, + dwc_otg_qtd_t *qtd, + dwc_otg_halt_status_e halt_status) +{ + uint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd, + halt_status, NULL); + urb->actual_length += bytes_transferred; + +#ifdef DEBUG + { + hctsiz_data_t hctsiz; + hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); + DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n", + __func__, (hc->ep_is_in ? "IN" : "OUT"), hc->hc_num); + DWC_DEBUGPL(DBG_HCDV, " hc->start_pkt_count %d\n", hc->start_pkt_count); + DWC_DEBUGPL(DBG_HCDV, " hctsiz.pktcnt %d\n", hctsiz.b.pktcnt); + DWC_DEBUGPL(DBG_HCDV, " hc->max_packet %d\n", hc->max_packet); + DWC_DEBUGPL(DBG_HCDV, " bytes_transferred %d\n", bytes_transferred); + DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n", urb->actual_length); + DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n", + urb->transfer_buffer_length); + } +#endif +} + +/** + * Handles a host channel NAK interrupt. This handler may be called in either + * DMA mode or Slave mode. + */ +static int32_t handle_hc_nak_intr(dwc_otg_hcd_t *hcd, + dwc_hc_t *hc, + dwc_otg_hc_regs_t *hc_regs, + dwc_otg_qtd_t *qtd) +{ + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " + "NAK Received--\n", hc->hc_num); + + /* + * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and + * interrupt. Re-start the SSPLIT transfer. + */ + if (hc->do_split) { + if (hc->complete_split) { + qtd->error_count = 0; + } + qtd->complete_split = 0; + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK); + goto handle_nak_done; + } + + switch (usb_pipetype(qtd->urb->pipe)) { + case PIPE_CONTROL: + case PIPE_BULK: + if (hcd->core_if->dma_enable && hc->ep_is_in) { + /* + * NAK interrupts are enabled on bulk/control IN + * transfers in DMA mode for the sole purpose of + * resetting the error count after a transaction error + * occurs. The core will continue transferring data. + */ + qtd->error_count = 0; + goto handle_nak_done; + } + + /* + * NAK interrupts normally occur during OUT transfers in DMA + * or Slave mode. For IN transfers, more requests will be + * queued as request queue space is available. + */ + qtd->error_count = 0; + + if (!hc->qh->ping_state) { + update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, + qtd, DWC_OTG_HC_XFER_NAK); + save_data_toggle(hc, hc_regs, qtd); + if (qtd->urb->dev->speed == USB_SPEED_HIGH) { + hc->qh->ping_state = 1; + } + } + + /* + * Halt the channel so the transfer can be re-started from + * the appropriate point or the PING protocol will + * start/continue. + */ + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK); + break; + case PIPE_INTERRUPT: + qtd->error_count = 0; + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK); + break; + case PIPE_ISOCHRONOUS: + /* Should never get called for isochronous transfers. */ + BUG(); + break; + } + + handle_nak_done: + disable_hc_int(hc_regs, nak); + + return 1; +} + +/** + * Handles a host channel ACK interrupt. This interrupt is enabled when + * performing the PING protocol in Slave mode, when errors occur during + * either Slave mode or DMA mode, and during Start Split transactions. + */ +static int32_t handle_hc_ack_intr(dwc_otg_hcd_t *hcd, + dwc_hc_t *hc, + dwc_otg_hc_regs_t *hc_regs, + dwc_otg_qtd_t *qtd) +{ + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " + "ACK Received--\n", hc->hc_num); + + if (hc->do_split) { + /* + * Handle ACK on SSPLIT. + * ACK should not occur in CSPLIT. + */ + if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) { + qtd->ssplit_out_xfer_count = hc->xfer_len; + } + if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) { + /* Don't need complete for isochronous out transfers. */ + qtd->complete_split = 1; + } + + /* ISOC OUT */ + if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) { + switch (hc->xact_pos) { + case DWC_HCSPLIT_XACTPOS_ALL: + break; + case DWC_HCSPLIT_XACTPOS_END: + qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL; + qtd->isoc_split_offset = 0; + break; + case DWC_HCSPLIT_XACTPOS_BEGIN: + case DWC_HCSPLIT_XACTPOS_MID: + /* + * For BEGIN or MID, calculate the length for + * the next microframe to determine the correct + * SSPLIT token, either MID or END. + */ + { + struct usb_iso_packet_descriptor *frame_desc; + + frame_desc = &qtd->urb->iso_frame_desc[qtd->isoc_frame_index]; + qtd->isoc_split_offset += 188; + + if ((frame_desc->length - qtd->isoc_split_offset) <= 188) { + qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_END; + } else { + qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_MID; + } + + } + break; + } + } else { + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK); + } + } else { + qtd->error_count = 0; + + if (hc->qh->ping_state) { + hc->qh->ping_state = 0; + /* + * Halt the channel so the transfer can be re-started + * from the appropriate point. This only happens in + * Slave mode. In DMA mode, the ping_state is cleared + * when the transfer is started because the core + * automatically executes the PING, then the transfer. + */ + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK); + } + } + + /* + * If the ACK occurred when _not_ in the PING state, let the channel + * continue transferring data after clearing the error count. + */ + + disable_hc_int(hc_regs, ack); + + return 1; +} + +/** + * Handles a host channel NYET interrupt. This interrupt should only occur on + * Bulk and Control OUT endpoints and for complete split transactions. If a + * NYET occurs at the same time as a Transfer Complete interrupt, it is + * handled in the xfercomp interrupt handler, not here. This handler may be + * called in either DMA mode or Slave mode. + */ +static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t *hcd, + dwc_hc_t *hc, + dwc_otg_hc_regs_t *hc_regs, + dwc_otg_qtd_t *qtd) +{ + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " + "NYET Received--\n", hc->hc_num); + + /* + * NYET on CSPLIT + * re-do the CSPLIT immediately on non-periodic + */ + if (hc->do_split && hc->complete_split) { + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { + int frnum = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(hcd)); + + if (dwc_full_frame_num(frnum) != + dwc_full_frame_num(hc->qh->sched_frame)) { + /* + * No longer in the same full speed frame. + * Treat this as a transaction error. + */ +#if 0 + /** @todo Fix system performance so this can + * be treated as an error. Right now complete + * splits cannot be scheduled precisely enough + * due to other system activity, so this error + * occurs regularly in Slave mode. + */ + qtd->error_count++; +#endif + qtd->complete_split = 0; + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR); + /** @todo add support for isoc release */ + goto handle_nyet_done; + } + } + + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET); + goto handle_nyet_done; + } + + hc->qh->ping_state = 1; + qtd->error_count = 0; + + update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd, + DWC_OTG_HC_XFER_NYET); + save_data_toggle(hc, hc_regs, qtd); + + /* + * Halt the channel and re-start the transfer so the PING + * protocol will start. + */ + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET); + +handle_nyet_done: + disable_hc_int(hc_regs, nyet); + return 1; +} + +/** + * Handles a host channel babble interrupt. This handler may be called in + * either DMA mode or Slave mode. + */ +static int32_t handle_hc_babble_intr(dwc_otg_hcd_t *hcd, + dwc_hc_t *hc, + dwc_otg_hc_regs_t *hc_regs, + dwc_otg_qtd_t *qtd) +{ + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " + "Babble Error--\n", hc->hc_num); + if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) { + dwc_otg_hcd_complete_urb(hcd, qtd->urb, -EOVERFLOW); + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR); + } else { + dwc_otg_halt_status_e halt_status; + halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd, + DWC_OTG_HC_XFER_BABBLE_ERR); + halt_channel(hcd, hc, qtd, halt_status); + } + disable_hc_int(hc_regs, bblerr); + return 1; +} + +/** + * Handles a host channel AHB error interrupt. This handler is only called in + * DMA mode. + */ +static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t *hcd, + dwc_hc_t *hc, + dwc_otg_hc_regs_t *hc_regs, + dwc_otg_qtd_t *qtd) +{ + hcchar_data_t hcchar; + hcsplt_data_t hcsplt; + hctsiz_data_t hctsiz; + uint32_t hcdma; + struct urb *urb = qtd->urb; + + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " + "AHB Error--\n", hc->hc_num); + + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt); + hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); + hcdma = dwc_read_reg32(&hc_regs->hcdma); + + DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num); + DWC_ERROR(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32); + DWC_ERROR(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma); + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n"); + DWC_ERROR(" Device address: %d\n", usb_pipedevice(urb->pipe)); + DWC_ERROR(" Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe), + (usb_pipein(urb->pipe) ? "IN" : "OUT")); + DWC_ERROR(" Endpoint type: %s\n", + ({char *pipetype; + switch (usb_pipetype(urb->pipe)) { + case PIPE_CONTROL: pipetype = "CONTROL"; break; + case PIPE_BULK: pipetype = "BULK"; break; + case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break; + case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break; + default: pipetype = "UNKNOWN"; break; + }; pipetype;})); + DWC_ERROR(" Speed: %s\n", + ({char *speed; + switch (urb->dev->speed) { + case USB_SPEED_HIGH: speed = "HIGH"; break; + case USB_SPEED_FULL: speed = "FULL"; break; + case USB_SPEED_LOW: speed = "LOW"; break; + default: speed = "UNKNOWN"; break; + }; speed;})); + DWC_ERROR(" Max packet size: %d\n", + usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); + DWC_ERROR(" Data buffer length: %d\n", urb->transfer_buffer_length); + DWC_ERROR(" Transfer buffer: %p, Transfer DMA: %p\n", + urb->transfer_buffer, (void *)urb->transfer_dma); + DWC_ERROR(" Setup buffer: %p, Setup DMA: %p\n", + urb->setup_packet, (void *)urb->setup_dma); + DWC_ERROR(" Interval: %d\n", urb->interval); + + dwc_otg_hcd_complete_urb(hcd, urb, -EIO); + + /* + * Force a channel halt. Don't call halt_channel because that won't + * write to the HCCHARn register in DMA mode to force the halt. + */ + dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR); + + disable_hc_int(hc_regs, ahberr); + return 1; +} + +/** + * Handles a host channel transaction error interrupt. This handler may be + * called in either DMA mode or Slave mode. + */ +static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t *hcd, + dwc_hc_t *hc, + dwc_otg_hc_regs_t *hc_regs, + dwc_otg_qtd_t *qtd) +{ + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " + "Transaction Error--\n", hc->hc_num); + + switch (usb_pipetype(qtd->urb->pipe)) { + case PIPE_CONTROL: + case PIPE_BULK: + qtd->error_count++; + if (!hc->qh->ping_state) { + update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, + qtd, DWC_OTG_HC_XFER_XACT_ERR); + save_data_toggle(hc, hc_regs, qtd); + if (!hc->ep_is_in && qtd->urb->dev->speed == USB_SPEED_HIGH) { + hc->qh->ping_state = 1; + } + } + + /* + * Halt the channel so the transfer can be re-started from + * the appropriate point or the PING protocol will start. + */ + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR); + break; + case PIPE_INTERRUPT: + qtd->error_count++; + if (hc->do_split && hc->complete_split) { + qtd->complete_split = 0; + } + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR); + break; + case PIPE_ISOCHRONOUS: + { + dwc_otg_halt_status_e halt_status; + halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd, + DWC_OTG_HC_XFER_XACT_ERR); + + halt_channel(hcd, hc, qtd, halt_status); + } + break; + } + + disable_hc_int(hc_regs, xacterr); + + return 1; +} + +/** + * Handles a host channel frame overrun interrupt. This handler may be called + * in either DMA mode or Slave mode. + */ +static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t *hcd, + dwc_hc_t *hc, + dwc_otg_hc_regs_t *hc_regs, + dwc_otg_qtd_t *qtd) +{ + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " + "Frame Overrun--\n", hc->hc_num); + + switch (usb_pipetype(qtd->urb->pipe)) { + case PIPE_CONTROL: + case PIPE_BULK: + break; + case PIPE_INTERRUPT: + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN); + break; + case PIPE_ISOCHRONOUS: + { + dwc_otg_halt_status_e halt_status; + halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd, + DWC_OTG_HC_XFER_FRAME_OVERRUN); + + halt_channel(hcd, hc, qtd, halt_status); + } + break; + } + + disable_hc_int(hc_regs, frmovrun); + + return 1; +} + +/** + * Handles a host channel data toggle error interrupt. This handler may be + * called in either DMA mode or Slave mode. + */ +static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t *hcd, + dwc_hc_t *hc, + dwc_otg_hc_regs_t *hc_regs, + dwc_otg_qtd_t *qtd) +{ + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " + "Data Toggle Error--\n", hc->hc_num); + + if (hc->ep_is_in) { + qtd->error_count = 0; + } else { + DWC_ERROR("Data Toggle Error on OUT transfer," + "channel %d\n", hc->hc_num); + } + + disable_hc_int(hc_regs, datatglerr); + + return 1; +} + +#ifdef DEBUG +/** + * This function is for debug only. It checks that a valid halt status is set + * and that HCCHARn.chdis is clear. If there's a problem, corrective action is + * taken and a warning is issued. + * @return 1 if halt status is ok, 0 otherwise. + */ +static inline int halt_status_ok(dwc_otg_hcd_t *hcd, + dwc_hc_t *hc, + dwc_otg_hc_regs_t *hc_regs, + dwc_otg_qtd_t *qtd) +{ + hcchar_data_t hcchar; + hctsiz_data_t hctsiz; + hcint_data_t hcint; + hcintmsk_data_t hcintmsk; + hcsplt_data_t hcsplt; + + if (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) { + /* + * This code is here only as a check. This condition should + * never happen. Ignore the halt if it does occur. + */ + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); + hcint.d32 = dwc_read_reg32(&hc_regs->hcint); + hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk); + hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt); + DWC_WARN("%s: hc->halt_status == DWC_OTG" + "channel %d, hcchar 0x%08x, hctsiz 0x%08x, " + "hcint 0x%08x, hcintmsk 0x%08x, " + "hcsplt 0x%08x, qtd->complete_split %d\n", + __func__, hc->hc_num, hcchar.d32, hctsiz.d32, + hcint.d32, hcintmsk.d32, + hcsplt.d32, qtd->complete_split); + + DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n", + __func__, hc->hc_num); + DWC_WARN("\n"); + clear_hc_int(hc_regs, chhltd); + return 0; + } + + /* + * This code is here only as a check. hcchar.chdis should + * never be set when the halt interrupt occurs. Halt the + * channel again if it does occur. + */ + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + if (hcchar.b.chdis) { + DWC_WARN("%s: hcchar.chdis set unexpectedly, " + "hcchar 0x%08x, trying to halt again\n", + __func__, hcchar.d32); + clear_hc_int(hc_regs, chhltd); + hc->halt_pending = 0; + halt_channel(hcd, hc, qtd, hc->halt_status); + return 0; + } + + return 1; +} +#endif + +/** + * Handles a host Channel Halted interrupt in DMA mode. This handler + * determines the reason the channel halted and proceeds accordingly. + */ +static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t *hcd, + dwc_hc_t *hc, + dwc_otg_hc_regs_t *hc_regs, + dwc_otg_qtd_t *qtd) +{ + hcint_data_t hcint; + hcintmsk_data_t hcintmsk; + int out_nak_enh = 0; + + /* For core with OUT NAK enhancement, the flow for high- + * speed CONTROL/BULK OUT is handled a little differently. + */ + if (hcd->core_if->snpsid >= 0x4F54271A) { + if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in && + (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL || + hc->ep_type == DWC_OTG_EP_TYPE_BULK)) { + printk(KERN_DEBUG "OUT NAK enhancement enabled\n"); + out_nak_enh = 1; + } else { + printk(KERN_DEBUG "OUT NAK enhancement disabled, not HS Ctrl/Bulk OUT EP\n"); + } + } else { +// printk(KERN_DEBUG "OUT NAK enhancement disabled, no core support\n"); + } + + if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE || + hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR) { + /* + * Just release the channel. A dequeue can happen on a + * transfer timeout. In the case of an AHB Error, the channel + * was forced to halt because there's no way to gracefully + * recover. + */ + release_channel(hcd, hc, qtd, hc->halt_status); + return; + } + + /* Read the HCINTn register to determine the cause for the halt. */ + hcint.d32 = dwc_read_reg32(&hc_regs->hcint); + hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk); + + if (hcint.b.xfercomp) { + /** @todo This is here because of a possible hardware bug. Spec + * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT + * interrupt w/ACK bit set should occur, but I only see the + * XFERCOMP bit, even with it masked out. This is a workaround + * for that behavior. Should fix this when hardware is fixed. + */ + if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) { + handle_hc_ack_intr(hcd, hc, hc_regs, qtd); + } + handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd); + } else if (hcint.b.stall) { + handle_hc_stall_intr(hcd, hc, hc_regs, qtd); + } else if (hcint.b.xacterr) { + if (out_nak_enh) { + if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) { + printk(KERN_DEBUG "XactErr with NYET/NAK/ACK\n"); + qtd->error_count = 0; + } else { + printk(KERN_DEBUG "XactErr without NYET/NAK/ACK\n"); + } + } + + /* + * Must handle xacterr before nak or ack. Could get a xacterr + * at the same time as either of these on a BULK/CONTROL OUT + * that started with a PING. The xacterr takes precedence. + */ + handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd); + } else if (!out_nak_enh) { + if (hcint.b.nyet) { + /* + * Must handle nyet before nak or ack. Could get a nyet at the + * same time as either of those on a BULK/CONTROL OUT that + * started with a PING. The nyet takes precedence. + */ + handle_hc_nyet_intr(hcd, hc, hc_regs, qtd); + } else if (hcint.b.bblerr) { + handle_hc_babble_intr(hcd, hc, hc_regs, qtd); + } else if (hcint.b.frmovrun) { + handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd); + } else if (hcint.b.nak && !hcintmsk.b.nak) { + /* + * If nak is not masked, it's because a non-split IN transfer + * is in an error state. In that case, the nak is handled by + * the nak interrupt handler, not here. Handle nak here for + * BULK/CONTROL OUT transfers, which halt on a NAK to allow + * rewinding the buffer pointer. + */ + handle_hc_nak_intr(hcd, hc, hc_regs, qtd); + } else if (hcint.b.ack && !hcintmsk.b.ack) { + /* + * If ack is not masked, it's because a non-split IN transfer + * is in an error state. In that case, the ack is handled by + * the ack interrupt handler, not here. Handle ack here for + * split transfers. Start splits halt on ACK. + */ + handle_hc_ack_intr(hcd, hc, hc_regs, qtd); + } else { + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { + /* + * A periodic transfer halted with no other channel + * interrupts set. Assume it was halted by the core + * because it could not be completed in its scheduled + * (micro)frame. + */ +#ifdef DEBUG + DWC_PRINT("%s: Halt channel %d (assume incomplete periodic transfer)\n", + __func__, hc->hc_num); +#endif + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE); + } else { + DWC_ERROR("%s: Channel %d, DMA Mode -- ChHltd set, but reason " + "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n", + __func__, hc->hc_num, hcint.d32, + dwc_read_reg32(&hcd->core_if->core_global_regs->gintsts)); + } + } + } else { + printk(KERN_DEBUG "NYET/NAK/ACK/other in non-error case, 0x%08x\n", hcint.d32); + } +} + +/** + * Handles a host channel Channel Halted interrupt. + * + * In slave mode, this handler is called only when the driver specifically + * requests a halt. This occurs during handling other host channel interrupts + * (e.g. nak, xacterr, stall, nyet, etc.). + * + * In DMA mode, this is the interrupt that occurs when the core has finished + * processing a transfer on a channel. Other host channel interrupts (except + * ahberr) are disabled in DMA mode. + */ +static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t *hcd, + dwc_hc_t *hc, + dwc_otg_hc_regs_t *hc_regs, + dwc_otg_qtd_t *qtd) +{ + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " + "Channel Halted--\n", hc->hc_num); + + if (hcd->core_if->dma_enable) { + handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd); + } else { +#ifdef DEBUG + if (!halt_status_ok(hcd, hc, hc_regs, qtd)) { + return 1; + } +#endif + release_channel(hcd, hc, qtd, hc->halt_status); + } + + return 1; +} + +/** Handles interrupt for a specific Host Channel */ +int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t *dwc_otg_hcd, uint32_t num) +{ + int retval = 0; + hcint_data_t hcint; + hcintmsk_data_t hcintmsk; + dwc_hc_t *hc; + dwc_otg_hc_regs_t *hc_regs; + dwc_otg_qtd_t *qtd; + + DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", num); + + hc = dwc_otg_hcd->hc_ptr_array[num]; + hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num]; + qtd = list_entry(hc->qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); + + hcint.d32 = dwc_read_reg32(&hc_regs->hcint); + hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk); + DWC_DEBUGPL(DBG_HCDV, " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n", + hcint.d32, hcintmsk.d32, (hcint.d32 & hcintmsk.d32)); + hcint.d32 = hcint.d32 & hcintmsk.d32; + + if (!dwc_otg_hcd->core_if->dma_enable) { + if (hcint.b.chhltd && hcint.d32 != 0x2) { + hcint.b.chhltd = 0; + } + } + + if (hcint.b.xfercomp) { + retval |= handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd); + /* + * If NYET occurred at same time as Xfer Complete, the NYET is + * handled by the Xfer Complete interrupt handler. Don't want + * to call the NYET interrupt handler in this case. + */ + hcint.b.nyet = 0; + } + if (hcint.b.chhltd) { + retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd); + } + if (hcint.b.ahberr) { + retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd); + } + if (hcint.b.stall) { + retval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd); + } + if (hcint.b.nak) { + retval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd); + } + if (hcint.b.ack) { + retval |= handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd); + } + if (hcint.b.nyet) { + retval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd); + } + if (hcint.b.xacterr) { + retval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd); + } + if (hcint.b.bblerr) { + retval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd); + } + if (hcint.b.frmovrun) { + retval |= handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd); + } + if (hcint.b.datatglerr) { + retval |= handle_hc_datatglerr_intr(dwc_otg_hcd, hc, hc_regs, qtd); + } + + return retval; +} + +#endif /* DWC_DEVICE_ONLY */ diff --git a/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c new file mode 100644 index 0000000000..cfb1f16410 --- /dev/null +++ b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c @@ -0,0 +1,684 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd_queue.c $ + * $Revision: 1.5 $ + * $Date: 2008-12-15 06:51:32 $ + * $Change: 537387 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and + * redistribute this Software in source and binary forms, with or without + * modification, provided that redistributions of source code must retain this + * notice. You may not view, use, disclose, copy or distribute this file or + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * ========================================================================== */ +#ifndef DWC_DEVICE_ONLY + +/** + * @file + * + * This file contains the functions to manage Queue Heads and Queue + * Transfer Descriptors. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dwc_otg_driver.h" +#include "dwc_otg_hcd.h" +#include "dwc_otg_regs.h" + +/** + * This function allocates and initializes a QH. + * + * @param hcd The HCD state structure for the DWC OTG controller. + * @param[in] urb Holds the information about the device/endpoint that we need + * to initialize the QH. + * + * @return Returns pointer to the newly allocated QH, or NULL on error. */ +dwc_otg_qh_t *dwc_otg_hcd_qh_create (dwc_otg_hcd_t *hcd, struct urb *urb) +{ + dwc_otg_qh_t *qh; + + /* Allocate memory */ + /** @todo add memflags argument */ + qh = dwc_otg_hcd_qh_alloc (); + if (qh == NULL) { + return NULL; + } + + dwc_otg_hcd_qh_init (hcd, qh, urb); + return qh; +} + +/** Free each QTD in the QH's QTD-list then free the QH. QH should already be + * removed from a list. QTD list should already be empty if called from URB + * Dequeue. + * + * @param[in] hcd HCD instance. + * @param[in] qh The QH to free. + */ +void dwc_otg_hcd_qh_free (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) +{ + dwc_otg_qtd_t *qtd; + struct list_head *pos; + unsigned long flags; + + /* Free each QTD in the QTD list */ + SPIN_LOCK_IRQSAVE(&hcd->lock, flags) + for (pos = qh->qtd_list.next; + pos != &qh->qtd_list; + pos = qh->qtd_list.next) + { + list_del (pos); + qtd = dwc_list_to_qtd (pos); + dwc_otg_hcd_qtd_free (qtd); + } + SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags) + + if (qh->dw_align_buf) { + dma_free_coherent((dwc_otg_hcd_to_hcd(hcd))->self.controller, + hcd->core_if->core_params->max_transfer_size, + qh->dw_align_buf, + qh->dw_align_buf_dma); + } + + kfree (qh); + return; +} + +/** Initializes a QH structure. + * + * @param[in] hcd The HCD state structure for the DWC OTG controller. + * @param[in] qh The QH to init. + * @param[in] urb Holds the information about the device/endpoint that we need + * to initialize the QH. */ +#define SCHEDULE_SLOP 10 +void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, struct urb *urb) +{ + char *speed, *type; + memset (qh, 0, sizeof (dwc_otg_qh_t)); + + /* Initialize QH */ + switch (usb_pipetype(urb->pipe)) { + case PIPE_CONTROL: + qh->ep_type = USB_ENDPOINT_XFER_CONTROL; + break; + case PIPE_BULK: + qh->ep_type = USB_ENDPOINT_XFER_BULK; + break; + case PIPE_ISOCHRONOUS: + qh->ep_type = USB_ENDPOINT_XFER_ISOC; + break; + case PIPE_INTERRUPT: + qh->ep_type = USB_ENDPOINT_XFER_INT; + break; + } + + qh->ep_is_in = usb_pipein(urb->pipe) ? 1 : 0; + + qh->data_toggle = DWC_OTG_HC_PID_DATA0; + qh->maxp = usb_maxpacket(urb->dev, urb->pipe, !(usb_pipein(urb->pipe))); + INIT_LIST_HEAD(&qh->qtd_list); + INIT_LIST_HEAD(&qh->qh_list_entry); + qh->channel = NULL; + + /* FS/LS Enpoint on HS Hub + * NOT virtual root hub */ + qh->do_split = 0; + if (((urb->dev->speed == USB_SPEED_LOW) || + (urb->dev->speed == USB_SPEED_FULL)) && + (urb->dev->tt) && (urb->dev->tt->hub) && (urb->dev->tt->hub->devnum != 1)) + { + DWC_DEBUGPL(DBG_HCD, "QH init: EP %d: TT found at hub addr %d, for port %d\n", + usb_pipeendpoint(urb->pipe), urb->dev->tt->hub->devnum, + urb->dev->ttport); + qh->do_split = 1; + } + + if (qh->ep_type == USB_ENDPOINT_XFER_INT || + qh->ep_type == USB_ENDPOINT_XFER_ISOC) { + /* Compute scheduling parameters once and save them. */ + hprt0_data_t hprt; + + /** @todo Account for split transfers in the bus time. */ + int bytecount = dwc_hb_mult(qh->maxp) * dwc_max_packet(qh->maxp); + + /* FIXME: work-around patch by Steven */ + qh->usecs = NS_TO_US(usb_calc_bus_time(urb->dev->speed, + usb_pipein(urb->pipe), + (qh->ep_type == USB_ENDPOINT_XFER_ISOC), + bytecount)); + + /* Start in a slightly future (micro)frame. */ + qh->sched_frame = dwc_frame_num_inc(hcd->frame_number, + SCHEDULE_SLOP); + qh->interval = urb->interval; +#if 0 + /* Increase interrupt polling rate for debugging. */ + if (qh->ep_type == USB_ENDPOINT_XFER_INT) { + qh->interval = 8; + } +#endif + hprt.d32 = dwc_read_reg32(hcd->core_if->host_if->hprt0); + if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) && + ((urb->dev->speed == USB_SPEED_LOW) || + (urb->dev->speed == USB_SPEED_FULL))) { + qh->interval *= 8; + qh->sched_frame |= 0x7; + qh->start_split_frame = qh->sched_frame; + } + + } + + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n"); + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", qh); + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n", + urb->dev->devnum); + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n", + usb_pipeendpoint(urb->pipe), + usb_pipein(urb->pipe) == USB_DIR_IN ? "IN" : "OUT"); + + switch(urb->dev->speed) { + case USB_SPEED_LOW: + speed = "low"; + break; + case USB_SPEED_FULL: + speed = "full"; + break; + case USB_SPEED_HIGH: + speed = "high"; + break; + default: + speed = "?"; + break; + } + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n", speed); + + switch (qh->ep_type) { + case USB_ENDPOINT_XFER_ISOC: + type = "isochronous"; + break; + case USB_ENDPOINT_XFER_INT: + type = "interrupt"; + break; + case USB_ENDPOINT_XFER_CONTROL: + type = "control"; + break; + case USB_ENDPOINT_XFER_BULK: + type = "bulk"; + break; + default: + type = "?"; + break; + } + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n",type); + +#ifdef DEBUG + if (qh->ep_type == USB_ENDPOINT_XFER_INT) { + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n", + qh->usecs); + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n", + qh->interval); + } +#endif + qh->dw_align_buf = NULL; + return; +} + +/** + * Checks that a channel is available for a periodic transfer. + * + * @return 0 if successful, negative error code otherise. + */ +static int periodic_channel_available(dwc_otg_hcd_t *hcd) +{ + /* + * Currently assuming that there is a dedicated host channnel for each + * periodic transaction plus at least one host channel for + * non-periodic transactions. + */ + int status; + int num_channels; + + num_channels = hcd->core_if->core_params->host_channels; + if ((hcd->periodic_channels + hcd->non_periodic_channels < num_channels) && + (hcd->periodic_channels < num_channels - 1)) { + status = 0; + } + else { + DWC_NOTICE("%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n", + __func__, num_channels, hcd->periodic_channels, + hcd->non_periodic_channels); + status = -ENOSPC; + } + + return status; +} + +/** + * Checks that there is sufficient bandwidth for the specified QH in the + * periodic schedule. For simplicity, this calculation assumes that all the + * transfers in the periodic schedule may occur in the same (micro)frame. + * + * @param hcd The HCD state structure for the DWC OTG controller. + * @param qh QH containing periodic bandwidth required. + * + * @return 0 if successful, negative error code otherwise. + */ +static int check_periodic_bandwidth(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) +{ + int status; + uint16_t max_claimed_usecs; + + status = 0; + + if (hcd->core_if->core_params->speed == DWC_SPEED_PARAM_HIGH) { + /* + * High speed mode. + * Max periodic usecs is 80% x 125 usec = 100 usec. + */ + max_claimed_usecs = 100 - qh->usecs; + } else { + /* + * Full speed mode. + * Max periodic usecs is 90% x 1000 usec = 900 usec. + */ + max_claimed_usecs = 900 - qh->usecs; + } + + if (hcd->periodic_usecs > max_claimed_usecs) { + DWC_NOTICE("%s: already claimed usecs %d, required usecs %d\n", + __func__, hcd->periodic_usecs, qh->usecs); + status = -ENOSPC; + } + + return status; +} + +/** + * Checks that the max transfer size allowed in a host channel is large enough + * to handle the maximum data transfer in a single (micro)frame for a periodic + * transfer. + * + * @param hcd The HCD state structure for the DWC OTG controller. + * @param qh QH for a periodic endpoint. + * + * @return 0 if successful, negative error code otherwise. + */ +static int check_max_xfer_size(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) +{ + int status; + uint32_t max_xfer_size; + uint32_t max_channel_xfer_size; + + status = 0; + + max_xfer_size = dwc_max_packet(qh->maxp) * dwc_hb_mult(qh->maxp); + max_channel_xfer_size = hcd->core_if->core_params->max_transfer_size; + + if (max_xfer_size > max_channel_xfer_size) { + DWC_NOTICE("%s: Periodic xfer length %d > " + "max xfer length for channel %d\n", + __func__, max_xfer_size, max_channel_xfer_size); + status = -ENOSPC; + } + + return status; +} + +/** + * Schedules an interrupt or isochronous transfer in the periodic schedule. + * + * @param hcd The HCD state structure for the DWC OTG controller. + * @param qh QH for the periodic transfer. The QH should already contain the + * scheduling information. + * + * @return 0 if successful, negative error code otherwise. + */ +static int schedule_periodic(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) +{ + int status = 0; + + status = periodic_channel_available(hcd); + if (status) { + DWC_NOTICE("%s: No host channel available for periodic " + "transfer.\n", __func__); + return status; + } + + status = check_periodic_bandwidth(hcd, qh); + if (status) { + DWC_NOTICE("%s: Insufficient periodic bandwidth for " + "periodic transfer.\n", __func__); + return status; + } + + status = check_max_xfer_size(hcd, qh); + if (status) { + DWC_NOTICE("%s: Channel max transfer size too small " + "for periodic transfer.\n", __func__); + return status; + } + + /* Always start in the inactive schedule. */ + list_add_tail(&qh->qh_list_entry, &hcd->periodic_sched_inactive); + + /* Reserve the periodic channel. */ + hcd->periodic_channels++; + + /* Update claimed usecs per (micro)frame. */ + hcd->periodic_usecs += qh->usecs; + + /* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */ + hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_allocated += qh->usecs / qh->interval; + if (qh->ep_type == USB_ENDPOINT_XFER_INT) { + hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_int_reqs++; + DWC_DEBUGPL(DBG_HCD, "Scheduled intr: qh %p, usecs %d, period %d\n", + qh, qh->usecs, qh->interval); + } else { + hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_isoc_reqs++; + DWC_DEBUGPL(DBG_HCD, "Scheduled isoc: qh %p, usecs %d, period %d\n", + qh, qh->usecs, qh->interval); + } + + return status; +} + +/** + * This function adds a QH to either the non periodic or periodic schedule if + * it is not already in the schedule. If the QH is already in the schedule, no + * action is taken. + * + * @return 0 if successful, negative error code otherwise. + */ +int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) +{ + unsigned long flags; + int status = 0; + + SPIN_LOCK_IRQSAVE(&hcd->lock, flags) + + if (!list_empty(&qh->qh_list_entry)) { + /* QH already in a schedule. */ + goto done; + } + + /* Add the new QH to the appropriate schedule */ + if (dwc_qh_is_non_per(qh)) { + /* Always start in the inactive schedule. */ + list_add_tail(&qh->qh_list_entry, &hcd->non_periodic_sched_inactive); + } else { + status = schedule_periodic(hcd, qh); + } + + done: + SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags) + + return status; +} + +/** + * Removes an interrupt or isochronous transfer from the periodic schedule. + * + * @param hcd The HCD state structure for the DWC OTG controller. + * @param qh QH for the periodic transfer. + */ +static void deschedule_periodic(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) +{ + list_del_init(&qh->qh_list_entry); + + /* Release the periodic channel reservation. */ + hcd->periodic_channels--; + + /* Update claimed usecs per (micro)frame. */ + hcd->periodic_usecs -= qh->usecs; + + /* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */ + hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_allocated -= qh->usecs / qh->interval; + + if (qh->ep_type == USB_ENDPOINT_XFER_INT) { + hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_int_reqs--; + DWC_DEBUGPL(DBG_HCD, "Descheduled intr: qh %p, usecs %d, period %d\n", + qh, qh->usecs, qh->interval); + } else { + hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_isoc_reqs--; + DWC_DEBUGPL(DBG_HCD, "Descheduled isoc: qh %p, usecs %d, period %d\n", + qh, qh->usecs, qh->interval); + } +} + +/** + * Removes a QH from either the non-periodic or periodic schedule. Memory is + * not freed. + * + * @param[in] hcd The HCD state structure. + * @param[in] qh QH to remove from schedule. */ +void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) +{ + unsigned long flags; + + SPIN_LOCK_IRQSAVE(&hcd->lock, flags); + + if (list_empty(&qh->qh_list_entry)) { + /* QH is not in a schedule. */ + goto done; + } + + if (dwc_qh_is_non_per(qh)) { + if (hcd->non_periodic_qh_ptr == &qh->qh_list_entry) { + hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next; + } + list_del_init(&qh->qh_list_entry); + } else { + deschedule_periodic(hcd, qh); + } + + done: + SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags) +} + +/** + * Deactivates a QH. For non-periodic QHs, removes the QH from the active + * non-periodic schedule. The QH is added to the inactive non-periodic + * schedule if any QTDs are still attached to the QH. + * + * For periodic QHs, the QH is removed from the periodic queued schedule. If + * there are any QTDs still attached to the QH, the QH is added to either the + * periodic inactive schedule or the periodic ready schedule and its next + * scheduled frame is calculated. The QH is placed in the ready schedule if + * the scheduled frame has been reached already. Otherwise it's placed in the + * inactive schedule. If there are no QTDs attached to the QH, the QH is + * completely removed from the periodic schedule. + */ +void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int sched_next_periodic_split) +{ + unsigned long flags; + SPIN_LOCK_IRQSAVE(&hcd->lock, flags); + + if (dwc_qh_is_non_per(qh)) { + dwc_otg_hcd_qh_remove(hcd, qh); + if (!list_empty(&qh->qtd_list)) { + /* Add back to inactive non-periodic schedule. */ + dwc_otg_hcd_qh_add(hcd, qh); + } + } else { + uint16_t frame_number = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(hcd)); + + if (qh->do_split) { + /* Schedule the next continuing periodic split transfer */ + if (sched_next_periodic_split) { + + qh->sched_frame = frame_number; + if (dwc_frame_num_le(frame_number, + dwc_frame_num_inc(qh->start_split_frame, 1))) { + /* + * Allow one frame to elapse after start + * split microframe before scheduling + * complete split, but DONT if we are + * doing the next start split in the + * same frame for an ISOC out. + */ + if ((qh->ep_type != USB_ENDPOINT_XFER_ISOC) || (qh->ep_is_in != 0)) { + qh->sched_frame = dwc_frame_num_inc(qh->sched_frame, 1); + } + } + } else { + qh->sched_frame = dwc_frame_num_inc(qh->start_split_frame, + qh->interval); + if (dwc_frame_num_le(qh->sched_frame, frame_number)) { + qh->sched_frame = frame_number; + } + qh->sched_frame |= 0x7; + qh->start_split_frame = qh->sched_frame; + } + } else { + qh->sched_frame = dwc_frame_num_inc(qh->sched_frame, qh->interval); + if (dwc_frame_num_le(qh->sched_frame, frame_number)) { + qh->sched_frame = frame_number; + } + } + + if (list_empty(&qh->qtd_list)) { + dwc_otg_hcd_qh_remove(hcd, qh); + } else { + /* + * Remove from periodic_sched_queued and move to + * appropriate queue. + */ + if (qh->sched_frame == frame_number) { + list_move(&qh->qh_list_entry, + &hcd->periodic_sched_ready); + } else { + list_move(&qh->qh_list_entry, + &hcd->periodic_sched_inactive); + } + } + } + + SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags); +} + +/** + * This function allocates and initializes a QTD. + * + * @param[in] urb The URB to create a QTD from. Each URB-QTD pair will end up + * pointing to each other so each pair should have a unique correlation. + * + * @return Returns pointer to the newly allocated QTD, or NULL on error. */ +dwc_otg_qtd_t *dwc_otg_hcd_qtd_create (struct urb *urb) +{ + dwc_otg_qtd_t *qtd; + + qtd = dwc_otg_hcd_qtd_alloc (); + if (qtd == NULL) { + return NULL; + } + + dwc_otg_hcd_qtd_init (qtd, urb); + return qtd; +} + +/** + * Initializes a QTD structure. + * + * @param[in] qtd The QTD to initialize. + * @param[in] urb The URB to use for initialization. */ +void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *qtd, struct urb *urb) +{ + memset (qtd, 0, sizeof (dwc_otg_qtd_t)); + qtd->urb = urb; + if (usb_pipecontrol(urb->pipe)) { + /* + * The only time the QTD data toggle is used is on the data + * phase of control transfers. This phase always starts with + * DATA1. + */ + qtd->data_toggle = DWC_OTG_HC_PID_DATA1; + qtd->control_phase = DWC_OTG_CONTROL_SETUP; + } + + /* start split */ + qtd->complete_split = 0; + qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL; + qtd->isoc_split_offset = 0; + + /* Store the qtd ptr in the urb to reference what QTD. */ + urb->hcpriv = qtd; + return; +} + +/** + * This function adds a QTD to the QTD-list of a QH. It will find the correct + * QH to place the QTD into. If it does not find a QH, then it will create a + * new QH. If the QH to which the QTD is added is not currently scheduled, it + * is placed into the proper schedule based on its EP type. + * + * @param[in] qtd The QTD to add + * @param[in] dwc_otg_hcd The DWC HCD structure + * + * @return 0 if successful, negative error code otherwise. + */ +int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *qtd, + dwc_otg_hcd_t *dwc_otg_hcd) +{ + struct usb_host_endpoint *ep; + dwc_otg_qh_t *qh; + unsigned long flags; + int retval = 0; + + struct urb *urb = qtd->urb; + + SPIN_LOCK_IRQSAVE(&dwc_otg_hcd->lock, flags); + + /* + * Get the QH which holds the QTD-list to insert to. Create QH if it + * doesn't exist. + */ + ep = dwc_urb_to_endpoint(urb); + qh = (dwc_otg_qh_t *)ep->hcpriv; + if (qh == NULL) { + qh = dwc_otg_hcd_qh_create (dwc_otg_hcd, urb); + if (qh == NULL) { + goto done; + } + ep->hcpriv = qh; + } + + retval = dwc_otg_hcd_qh_add(dwc_otg_hcd, qh); + if (retval == 0) { + list_add_tail(&qtd->qtd_list_entry, &qh->qtd_list); + } + + done: + SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags); + + return retval; +} + +#endif /* DWC_DEVICE_ONLY */ diff --git a/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_pcd.c b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_pcd.c new file mode 100644 index 0000000000..030a3f2856 --- /dev/null +++ b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_pcd.c @@ -0,0 +1,2523 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.c $ + * $Revision: 1.5 $ + * $Date: 2008-11-27 09:21:25 $ + * $Change: 1115682 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and + * redistribute this Software in source and binary forms, with or without + * modification, provided that redistributions of source code must retain this + * notice. You may not view, use, disclose, copy or distribute this file or + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * ========================================================================== */ +#ifndef DWC_HOST_ONLY + +/** @file + * This file implements the Peripheral Controller Driver. + * + * The Peripheral Controller Driver (PCD) is responsible for + * translating requests from the Function Driver into the appropriate + * actions on the DWC_otg controller. It isolates the Function Driver + * from the specifics of the controller by providing an API to the + * Function Driver. + * + * The Peripheral Controller Driver for Linux will implement the + * Gadget API, so that the existing Gadget drivers can be used. + * (Gadget Driver is the Linux terminology for a Function Driver.) + * + * The Linux Gadget API is defined in the header file + * . The USB EP operations API is + * defined in the structure usb_ep_ops and the USB + * Controller API is defined in the structure + * usb_gadget_ops. + * + * An important function of the PCD is managing interrupts generated + * by the DWC_otg controller. The implementation of the DWC_otg device + * mode interrupt service routines is in dwc_otg_pcd_intr.c. + * + * @todo Add Device Mode test modes (Test J mode, Test K mode, etc). + * @todo Does it work when the request size is greater than DEPTSIZ + * transfer size + * + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21) +# include +#else +# include +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) +#include +#else +#include +#endif + +#include "dwc_otg_driver.h" +#include "dwc_otg_pcd.h" + + +/** + * Static PCD pointer for use in usb_gadget_register_driver and + * usb_gadget_unregister_driver. Initialized in dwc_otg_pcd_init. + */ +static dwc_otg_pcd_t *s_pcd = 0; + + +/* Display the contents of the buffer */ +extern void dump_msg(const u8 *buf, unsigned int length); + + +/** + * This function completes a request. It call's the request call back. + */ +void dwc_otg_request_done(dwc_otg_pcd_ep_t *ep, dwc_otg_pcd_request_t *req, + int status) +{ + unsigned stopped = ep->stopped; + + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, ep); + list_del_init(&req->queue); + + if (req->req.status == -EINPROGRESS) { + req->req.status = status; + } else { + status = req->req.status; + } + + /* don't modify queue heads during completion callback */ + ep->stopped = 1; + SPIN_UNLOCK(&ep->pcd->lock); + req->req.complete(&ep->ep, &req->req); + SPIN_LOCK(&ep->pcd->lock); + + if (ep->pcd->request_pending > 0) { + --ep->pcd->request_pending; + } + + ep->stopped = stopped; +} + +/** + * This function terminates all the requsts in the EP request queue. + */ +void dwc_otg_request_nuke(dwc_otg_pcd_ep_t *ep) +{ + dwc_otg_pcd_request_t *req; + + ep->stopped = 1; + + /* called with irqs blocked?? */ + while (!list_empty(&ep->queue)) { + req = list_entry(ep->queue.next, dwc_otg_pcd_request_t, + queue); + dwc_otg_request_done(ep, req, -ESHUTDOWN); + } +} + +/* USB Endpoint Operations */ +/* + * The following sections briefly describe the behavior of the Gadget + * API endpoint operations implemented in the DWC_otg driver + * software. Detailed descriptions of the generic behavior of each of + * these functions can be found in the Linux header file + * include/linux/usb_gadget.h. + * + * The Gadget API provides wrapper functions for each of the function + * pointers defined in usb_ep_ops. The Gadget Driver calls the wrapper + * function, which then calls the underlying PCD function. The + * following sections are named according to the wrapper + * functions. Within each section, the corresponding DWC_otg PCD + * function name is specified. + * + */ + +/** + * This function assigns periodic Tx FIFO to an periodic EP + * in shared Tx FIFO mode + */ +static uint32_t assign_perio_tx_fifo(dwc_otg_core_if_t *core_if) +{ + uint32_t PerTxMsk = 1; + int i; + for(i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; ++i) + { + if((PerTxMsk & core_if->p_tx_msk) == 0) { + core_if->p_tx_msk |= PerTxMsk; + return i + 1; + } + PerTxMsk <<= 1; + } + return 0; +} +/** + * This function releases periodic Tx FIFO + * in shared Tx FIFO mode + */ +static void release_perio_tx_fifo(dwc_otg_core_if_t *core_if, uint32_t fifo_num) +{ + core_if->p_tx_msk = (core_if->p_tx_msk & (1 << (fifo_num - 1))) ^ core_if->p_tx_msk; +} +/** + * This function assigns periodic Tx FIFO to an periodic EP + * in shared Tx FIFO mode + */ +static uint32_t assign_tx_fifo(dwc_otg_core_if_t *core_if) +{ + uint32_t TxMsk = 1; + int i; + + for(i = 0; i < core_if->hwcfg4.b.num_in_eps; ++i) + { + if((TxMsk & core_if->tx_msk) == 0) { + core_if->tx_msk |= TxMsk; + return i + 1; + } + TxMsk <<= 1; + } + return 0; +} +/** + * This function releases periodic Tx FIFO + * in shared Tx FIFO mode + */ +static void release_tx_fifo(dwc_otg_core_if_t *core_if, uint32_t fifo_num) +{ + core_if->tx_msk = (core_if->tx_msk & (1 << (fifo_num - 1))) ^ core_if->tx_msk; +} + +/** + * This function is called by the Gadget Driver for each EP to be + * configured for the current configuration (SET_CONFIGURATION). + * + * This function initializes the dwc_otg_ep_t data structure, and then + * calls dwc_otg_ep_activate. + */ +static int dwc_otg_pcd_ep_enable(struct usb_ep *usb_ep, + const struct usb_endpoint_descriptor *ep_desc) +{ + dwc_otg_pcd_ep_t *ep = 0; + dwc_otg_pcd_t *pcd = 0; + unsigned long flags; + + DWC_DEBUGPL(DBG_PCDV,"%s(%p,%p)\n", __func__, usb_ep, ep_desc); + + ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep); + if (!usb_ep || !ep_desc || ep->desc || + ep_desc->bDescriptorType != USB_DT_ENDPOINT) { + DWC_WARN("%s, bad ep or descriptor\n", __func__); + return -EINVAL; + } + if (ep == &ep->pcd->ep0) { + DWC_WARN("%s, bad ep(0)\n", __func__); + return -EINVAL; + } + + /* Check FIFO size? */ + if (!ep_desc->wMaxPacketSize) { + DWC_WARN("%s, bad %s maxpacket\n", __func__, usb_ep->name); + return -ERANGE; + } + + pcd = ep->pcd; + if (!pcd->driver || pcd->gadget.speed == USB_SPEED_UNKNOWN) { + DWC_WARN("%s, bogus device state\n", __func__); + return -ESHUTDOWN; + } + + SPIN_LOCK_IRQSAVE(&pcd->lock, flags); + + ep->desc = ep_desc; + ep->ep.maxpacket = le16_to_cpu (ep_desc->wMaxPacketSize); + + /* + * Activate the EP + */ + ep->stopped = 0; + + ep->dwc_ep.is_in = (USB_DIR_IN & ep_desc->bEndpointAddress) != 0; + ep->dwc_ep.maxpacket = ep->ep.maxpacket; + + ep->dwc_ep.type = ep_desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; + + if(ep->dwc_ep.is_in) { + if(!pcd->otg_dev->core_if->en_multiple_tx_fifo) { + ep->dwc_ep.tx_fifo_num = 0; + + if (ep->dwc_ep.type == USB_ENDPOINT_XFER_ISOC) { + /* + * if ISOC EP then assign a Periodic Tx FIFO. + */ + ep->dwc_ep.tx_fifo_num = assign_perio_tx_fifo(pcd->otg_dev->core_if); + } + } else { + /* + * if Dedicated FIFOs mode is on then assign a Tx FIFO. + */ + ep->dwc_ep.tx_fifo_num = assign_tx_fifo(pcd->otg_dev->core_if); + + } + } + /* Set initial data PID. */ + if (ep->dwc_ep.type == USB_ENDPOINT_XFER_BULK) { + ep->dwc_ep.data_pid_start = 0; + } + + DWC_DEBUGPL(DBG_PCD, "Activate %s-%s: type=%d, mps=%d desc=%p\n", + ep->ep.name, (ep->dwc_ep.is_in ?"IN":"OUT"), + ep->dwc_ep.type, ep->dwc_ep.maxpacket, ep->desc); + + if(ep->dwc_ep.type != USB_ENDPOINT_XFER_ISOC) { + ep->dwc_ep.desc_addr = dwc_otg_ep_alloc_desc_chain(&ep->dwc_ep.dma_desc_addr, MAX_DMA_DESC_CNT); + } + + dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep); + SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags); + + return 0; +} + +/** + * This function is called when an EP is disabled due to disconnect or + * change in configuration. Any pending requests will terminate with a + * status of -ESHUTDOWN. + * + * This function modifies the dwc_otg_ep_t data structure for this EP, + * and then calls dwc_otg_ep_deactivate. + */ +static int dwc_otg_pcd_ep_disable(struct usb_ep *usb_ep) +{ + dwc_otg_pcd_ep_t *ep; + dwc_otg_pcd_t *pcd = 0; + unsigned long flags; + + DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, usb_ep); + ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep); + if (!usb_ep || !ep->desc) { + DWC_DEBUGPL(DBG_PCD, "%s, %s not enabled\n", __func__, + usb_ep ? ep->ep.name : NULL); + return -EINVAL; + } + + SPIN_LOCK_IRQSAVE(&ep->pcd->lock, flags); + + dwc_otg_request_nuke(ep); + + dwc_otg_ep_deactivate(GET_CORE_IF(ep->pcd), &ep->dwc_ep); + ep->desc = 0; + ep->stopped = 1; + + if(ep->dwc_ep.is_in) { + dwc_otg_flush_tx_fifo(GET_CORE_IF(ep->pcd), ep->dwc_ep.tx_fifo_num); + release_perio_tx_fifo(GET_CORE_IF(ep->pcd), ep->dwc_ep.tx_fifo_num); + release_tx_fifo(GET_CORE_IF(ep->pcd), ep->dwc_ep.tx_fifo_num); + } + + /* Free DMA Descriptors */ + pcd = ep->pcd; + + SPIN_UNLOCK_IRQRESTORE(&ep->pcd->lock, flags); + + if(ep->dwc_ep.type != USB_ENDPOINT_XFER_ISOC && ep->dwc_ep.desc_addr) { + dwc_otg_ep_free_desc_chain(ep->dwc_ep.desc_addr, ep->dwc_ep.dma_desc_addr, MAX_DMA_DESC_CNT); + } + + DWC_DEBUGPL(DBG_PCD, "%s disabled\n", usb_ep->name); + return 0; +} + + +/** + * This function allocates a request object to use with the specified + * endpoint. + * + * @param ep The endpoint to be used with with the request + * @param gfp_flags the GFP_* flags to use. + */ +static struct usb_request *dwc_otg_pcd_alloc_request(struct usb_ep *ep, +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) + int gfp_flags +#else + gfp_t gfp_flags +#endif + ) +{ + dwc_otg_pcd_request_t *req; + + DWC_DEBUGPL(DBG_PCDV,"%s(%p,%d)\n", __func__, ep, gfp_flags); + if (0 == ep) { + DWC_WARN("%s() %s\n", __func__, "Invalid EP!\n"); + return 0; + } + req = kmalloc(sizeof(dwc_otg_pcd_request_t), gfp_flags); + if (0 == req) { + DWC_WARN("%s() %s\n", __func__, + "request allocation failed!\n"); + return 0; + } + memset(req, 0, sizeof(dwc_otg_pcd_request_t)); + req->req.dma = DMA_ADDR_INVALID; + INIT_LIST_HEAD(&req->queue); + return &req->req; +} + +/** + * This function frees a request object. + * + * @param ep The endpoint associated with the request + * @param req The request being freed + */ +static void dwc_otg_pcd_free_request(struct usb_ep *ep, + struct usb_request *req) +{ + dwc_otg_pcd_request_t *request; + DWC_DEBUGPL(DBG_PCDV,"%s(%p,%p)\n", __func__, ep, req); + + if (0 == ep || 0 == req) { + DWC_WARN("%s() %s\n", __func__, + "Invalid ep or req argument!\n"); + return; + } + + request = container_of(req, dwc_otg_pcd_request_t, req); + kfree(request); +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) +/** + * This function allocates an I/O buffer to be used for a transfer + * to/from the specified endpoint. + * + * @param usb_ep The endpoint to be used with with the request + * @param bytes The desired number of bytes for the buffer + * @param dma Pointer to the buffer's DMA address; must be valid + * @param gfp_flags the GFP_* flags to use. + * @return address of a new buffer or null is buffer could not be allocated. + */ +static void *dwc_otg_pcd_alloc_buffer(struct usb_ep *usb_ep, unsigned bytes, + dma_addr_t *dma, +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) + int gfp_flags +#else + gfp_t gfp_flags +#endif + ) +{ + void *buf; + dwc_otg_pcd_ep_t *ep; + dwc_otg_pcd_t *pcd = 0; + + ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep); + pcd = ep->pcd; + + DWC_DEBUGPL(DBG_PCDV,"%s(%p,%d,%p,%0x)\n", __func__, usb_ep, bytes, + dma, gfp_flags); + + /* Check dword alignment */ + if ((bytes & 0x3UL) != 0) { + DWC_WARN("%s() Buffer size is not a multiple of" + "DWORD size (%d)",__func__, bytes); + } + + if (GET_CORE_IF(pcd)->dma_enable) { + buf = dma_alloc_coherent (NULL, bytes, dma, gfp_flags); + } + else { + buf = kmalloc(bytes, gfp_flags); + } + + /* Check dword alignment */ + if (((int)buf & 0x3UL) != 0) { + DWC_WARN("%s() Buffer is not DWORD aligned (%p)", + __func__, buf); + } + + return buf; +} + +/** + * This function frees an I/O buffer that was allocated by alloc_buffer. + * + * @param usb_ep the endpoint associated with the buffer + * @param buf address of the buffer + * @param dma The buffer's DMA address + * @param bytes The number of bytes of the buffer + */ +static void dwc_otg_pcd_free_buffer(struct usb_ep *usb_ep, void *buf, + dma_addr_t dma, unsigned bytes) +{ + dwc_otg_pcd_ep_t *ep; + dwc_otg_pcd_t *pcd = 0; + + ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep); + pcd = ep->pcd; + + DWC_DEBUGPL(DBG_PCDV,"%s(%p,%p,%0x,%d)\n", __func__, ep, buf, dma, bytes); + + if (GET_CORE_IF(pcd)->dma_enable) { + dma_free_coherent (NULL, bytes, buf, dma); + } + else { + kfree(buf); + } +} +#endif + + +/** + * This function is used to submit an I/O Request to an EP. + * + * - When the request completes the request's completion callback + * is called to return the request to the driver. + * - An EP, except control EPs, may have multiple requests + * pending. + * - Once submitted the request cannot be examined or modified. + * - Each request is turned into one or more packets. + * - A BULK EP can queue any amount of data; the transfer is + * packetized. + * - Zero length Packets are specified with the request 'zero' + * flag. + */ +static int dwc_otg_pcd_ep_queue(struct usb_ep *usb_ep, + struct usb_request *usb_req, +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) + int gfp_flags +#else + gfp_t gfp_flags +#endif + ) +{ + int prevented = 0; + dwc_otg_pcd_request_t *req; + dwc_otg_pcd_ep_t *ep; + dwc_otg_pcd_t *pcd; + unsigned long flags = 0; + dwc_otg_core_if_t *_core_if; + + DWC_DEBUGPL(DBG_PCDV,"%s(%p,%p,%d)\n", + __func__, usb_ep, usb_req, gfp_flags); + + req = container_of(usb_req, dwc_otg_pcd_request_t, req); + if (!usb_req || !usb_req->complete || !usb_req->buf || + !list_empty(&req->queue)) { + DWC_WARN("%s, bad params\n", __func__); + return -EINVAL; + } + + ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep); + if (!usb_ep || (!ep->desc && ep->dwc_ep.num != 0)/* || ep->stopped != 0*/) { + DWC_WARN("%s, bad ep\n", __func__); + return -EINVAL; + } + + pcd = ep->pcd; + if (!pcd->driver || pcd->gadget.speed == USB_SPEED_UNKNOWN) { + DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n", pcd->gadget.speed); + DWC_WARN("%s, bogus device state\n", __func__); + return -ESHUTDOWN; + } + + + DWC_DEBUGPL(DBG_PCD, "%s queue req %p, len %d buf %p\n", + usb_ep->name, usb_req, usb_req->length, usb_req->buf); + + if (!GET_CORE_IF(pcd)->core_params->opt) { + if (ep->dwc_ep.num != 0) { + DWC_ERROR("%s queue req %p, len %d buf %p\n", + usb_ep->name, usb_req, usb_req->length, usb_req->buf); + } + } + + SPIN_LOCK_IRQSAVE(&ep->pcd->lock, flags); + + + /************************************************** + New add by kaiker ,for DMA mode bug + ************************************************/ + //by kaiker ,for RT3052 USB OTG device mode + + _core_if = GET_CORE_IF(pcd); + + if (_core_if->dma_enable) + { + usb_req->dma = virt_to_phys((void *)usb_req->buf); + + if(ep->dwc_ep.is_in) + { +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) || defined(CONFIG_MIPS) + if(usb_req->length) + dma_cache_wback_inv((unsigned long)usb_req->buf, usb_req->length + 2); +#endif + } + } + + + +#if defined(DEBUG) & defined(VERBOSE) + dump_msg(usb_req->buf, usb_req->length); +#endif + + usb_req->status = -EINPROGRESS; + usb_req->actual = 0; + + /* + * For EP0 IN without premature status, zlp is required? + */ + if (ep->dwc_ep.num == 0 && ep->dwc_ep.is_in) { + DWC_DEBUGPL(DBG_PCDV, "%s-OUT ZLP\n", usb_ep->name); + //_req->zero = 1; + } + + /* Start the transfer */ + if (list_empty(&ep->queue) && !ep->stopped) { + /* EP0 Transfer? */ + if (ep->dwc_ep.num == 0) { + switch (pcd->ep0state) { + case EP0_IN_DATA_PHASE: + DWC_DEBUGPL(DBG_PCD, + "%s ep0: EP0_IN_DATA_PHASE\n", + __func__); + break; + + case EP0_OUT_DATA_PHASE: + DWC_DEBUGPL(DBG_PCD, + "%s ep0: EP0_OUT_DATA_PHASE\n", + __func__); + if (pcd->request_config) { + /* Complete STATUS PHASE */ + ep->dwc_ep.is_in = 1; + pcd->ep0state = EP0_IN_STATUS_PHASE; + } + break; + + case EP0_IN_STATUS_PHASE: + DWC_DEBUGPL(DBG_PCD, + "%s ep0: EP0_IN_STATUS_PHASE\n", + __func__); + break; + + default: + DWC_DEBUGPL(DBG_ANY, "ep0: odd state %d\n", + pcd->ep0state); + SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags); + return -EL2HLT; + } + ep->dwc_ep.dma_addr = usb_req->dma; + ep->dwc_ep.start_xfer_buff = usb_req->buf; + ep->dwc_ep.xfer_buff = usb_req->buf; + ep->dwc_ep.xfer_len = usb_req->length; + ep->dwc_ep.xfer_count = 0; + ep->dwc_ep.sent_zlp = 0; + ep->dwc_ep.total_len = ep->dwc_ep.xfer_len; + + if(usb_req->zero) { + if((ep->dwc_ep.xfer_len % ep->dwc_ep.maxpacket == 0) + && (ep->dwc_ep.xfer_len != 0)) { + ep->dwc_ep.sent_zlp = 1; + } + + } + + dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep->dwc_ep); + } + else { + + uint32_t max_transfer = GET_CORE_IF(ep->pcd)->core_params->max_transfer_size; + + /* Setup and start the Transfer */ + ep->dwc_ep.dma_addr = usb_req->dma; + ep->dwc_ep.start_xfer_buff = usb_req->buf; + ep->dwc_ep.xfer_buff = usb_req->buf; + ep->dwc_ep.sent_zlp = 0; + ep->dwc_ep.total_len = usb_req->length; + ep->dwc_ep.xfer_len = 0; + ep->dwc_ep.xfer_count = 0; + + if(max_transfer > MAX_TRANSFER_SIZE) { + ep->dwc_ep.maxxfer = max_transfer - (max_transfer % ep->dwc_ep.maxpacket); + } else { + ep->dwc_ep.maxxfer = max_transfer; + } + + if(usb_req->zero) { + if((ep->dwc_ep.total_len % ep->dwc_ep.maxpacket == 0) + && (ep->dwc_ep.total_len != 0)) { + ep->dwc_ep.sent_zlp = 1; + } + + } + dwc_otg_ep_start_transfer(GET_CORE_IF(pcd), &ep->dwc_ep); + } + } + + if ((req != 0) || prevented) { + ++pcd->request_pending; + list_add_tail(&req->queue, &ep->queue); + if (ep->dwc_ep.is_in && ep->stopped && !(GET_CORE_IF(pcd)->dma_enable)) { + /** @todo NGS Create a function for this. */ + diepmsk_data_t diepmsk = { .d32 = 0}; + diepmsk.b.intktxfemp = 1; + if(&GET_CORE_IF(pcd)->multiproc_int_enable) { + dwc_modify_reg32(&GET_CORE_IF(pcd)->dev_if->dev_global_regs->diepeachintmsk[ep->dwc_ep.num], + 0, diepmsk.d32); + } else { + dwc_modify_reg32(&GET_CORE_IF(pcd)->dev_if->dev_global_regs->diepmsk, 0, diepmsk.d32); + } + } + } + + SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags); + return 0; +} + +/** + * This function cancels an I/O request from an EP. + */ +static int dwc_otg_pcd_ep_dequeue(struct usb_ep *usb_ep, + struct usb_request *usb_req) +{ + dwc_otg_pcd_request_t *req; + dwc_otg_pcd_ep_t *ep; + dwc_otg_pcd_t *pcd; + unsigned long flags; + + DWC_DEBUGPL(DBG_PCDV,"%s(%p,%p)\n", __func__, usb_ep, usb_req); + + ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep); + if (!usb_ep || !usb_req || (!ep->desc && ep->dwc_ep.num != 0)) { + DWC_WARN("%s, bad argument\n", __func__); + return -EINVAL; + } + pcd = ep->pcd; + if (!pcd->driver || pcd->gadget.speed == USB_SPEED_UNKNOWN) { + DWC_WARN("%s, bogus device state\n", __func__); + return -ESHUTDOWN; + } + + SPIN_LOCK_IRQSAVE(&pcd->lock, flags); + DWC_DEBUGPL(DBG_PCDV, "%s %s %s %p\n", __func__, usb_ep->name, + ep->dwc_ep.is_in ? "IN" : "OUT", + usb_req); + + /* make sure it's actually queued on this endpoint */ + list_for_each_entry(req, &ep->queue, queue) + { + if (&req->req == usb_req) { + break; + } + } + + if (&req->req != usb_req) { + SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags); + return -EINVAL; + } + + if (!list_empty(&req->queue)) { + dwc_otg_request_done(ep, req, -ECONNRESET); + } + else { + req = 0; + } + + SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags); + + return req ? 0 : -EOPNOTSUPP; +} + +/** + * usb_ep_set_halt stalls an endpoint. + * + * usb_ep_clear_halt clears an endpoint halt and resets its data + * toggle. + * + * Both of these functions are implemented with the same underlying + * function. The behavior depends on the value argument. + * + * @param[in] usb_ep the Endpoint to halt or clear halt. + * @param[in] value + * - 0 means clear_halt. + * - 1 means set_halt, + * - 2 means clear stall lock flag. + * - 3 means set stall lock flag. + */ +static int dwc_otg_pcd_ep_set_halt(struct usb_ep *usb_ep, int value) +{ + int retval = 0; + unsigned long flags; + dwc_otg_pcd_ep_t *ep = 0; + + + DWC_DEBUGPL(DBG_PCD,"HALT %s %d\n", usb_ep->name, value); + + ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep); + + if (!usb_ep || (!ep->desc && ep != &ep->pcd->ep0) || + ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) { + DWC_WARN("%s, bad ep\n", __func__); + return -EINVAL; + } + + SPIN_LOCK_IRQSAVE(&ep->pcd->lock, flags); + if (!list_empty(&ep->queue)) { + DWC_WARN("%s() %s XFer In process\n", __func__, usb_ep->name); + retval = -EAGAIN; + } + else if (value == 0) { + dwc_otg_ep_clear_stall(ep->pcd->otg_dev->core_if, + &ep->dwc_ep); + } + else if(value == 1) { + if (ep->dwc_ep.is_in == 1 && ep->pcd->otg_dev->core_if->dma_desc_enable) { + dtxfsts_data_t txstatus; + fifosize_data_t txfifosize; + + txfifosize.d32 = dwc_read_reg32(&ep->pcd->otg_dev->core_if->core_global_regs->dptxfsiz_dieptxf[ep->dwc_ep.tx_fifo_num]); + txstatus.d32 = dwc_read_reg32(&ep->pcd->otg_dev->core_if->dev_if->in_ep_regs[ep->dwc_ep.num]->dtxfsts); + + if(txstatus.b.txfspcavail < txfifosize.b.depth) { + DWC_WARN("%s() %s Data In Tx Fifo\n", __func__, usb_ep->name); + retval = -EAGAIN; + } + else { + if (ep->dwc_ep.num == 0) { + ep->pcd->ep0state = EP0_STALL; + } + + ep->stopped = 1; + dwc_otg_ep_set_stall(ep->pcd->otg_dev->core_if, + &ep->dwc_ep); + } + } + else { + if (ep->dwc_ep.num == 0) { + ep->pcd->ep0state = EP0_STALL; + } + + ep->stopped = 1; + dwc_otg_ep_set_stall(ep->pcd->otg_dev->core_if, + &ep->dwc_ep); + } + } + else if (value == 2) { + ep->dwc_ep.stall_clear_flag = 0; + } + else if (value == 3) { + ep->dwc_ep.stall_clear_flag = 1; + } + + SPIN_UNLOCK_IRQRESTORE(&ep->pcd->lock, flags); + return retval; +} + +/** + * This function allocates a DMA Descriptor chain for the Endpoint + * buffer to be used for a transfer to/from the specified endpoint. + */ +dwc_otg_dma_desc_t* dwc_otg_ep_alloc_desc_chain(uint32_t * dma_desc_addr, uint32_t count) +{ + + return dma_alloc_coherent(NULL, count * sizeof(dwc_otg_dma_desc_t), dma_desc_addr, GFP_KERNEL); +} + +/** + * This function frees a DMA Descriptor chain that was allocated by ep_alloc_desc. + */ +void dwc_otg_ep_free_desc_chain(dwc_otg_dma_desc_t* desc_addr, uint32_t dma_desc_addr, uint32_t count) +{ + dma_free_coherent(NULL, count * sizeof(dwc_otg_dma_desc_t), desc_addr, dma_desc_addr); +} + +#ifdef DWC_EN_ISOC + +/** + * This function initializes a descriptor chain for Isochronous transfer + * + * @param core_if Programming view of DWC_otg controller. + * @param dwc_ep The EP to start the transfer on. + * + */ +void dwc_otg_iso_ep_start_ddma_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep) +{ + + dsts_data_t dsts = { .d32 = 0}; + depctl_data_t depctl = { .d32 = 0 }; + volatile uint32_t *addr; + int i, j; + + if(dwc_ep->is_in) + dwc_ep->desc_cnt = dwc_ep->buf_proc_intrvl / dwc_ep->bInterval; + else + dwc_ep->desc_cnt = dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm / dwc_ep->bInterval; + + + /** Allocate descriptors for double buffering */ + dwc_ep->iso_desc_addr = dwc_otg_ep_alloc_desc_chain(&dwc_ep->iso_dma_desc_addr,dwc_ep->desc_cnt*2); + if(dwc_ep->desc_addr) { + DWC_WARN("%s, can't allocate DMA descriptor chain\n", __func__); + return; + } + + dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); + + /** ISO OUT EP */ + if(dwc_ep->is_in == 0) { + desc_sts_data_t sts = { .d32 =0 }; + dwc_otg_dma_desc_t* dma_desc = dwc_ep->iso_desc_addr; + dma_addr_t dma_ad; + uint32_t data_per_desc; + dwc_otg_dev_out_ep_regs_t *out_regs = + core_if->dev_if->out_ep_regs[dwc_ep->num]; + int offset; + + addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl; + dma_ad = (dma_addr_t)dwc_read_reg32(&(out_regs->doepdma)); + + /** Buffer 0 descriptors setup */ + dma_ad = dwc_ep->dma_addr0; + + sts.b_iso_out.bs = BS_HOST_READY; + sts.b_iso_out.rxsts = 0; + sts.b_iso_out.l = 0; + sts.b_iso_out.sp = 0; + sts.b_iso_out.ioc = 0; + sts.b_iso_out.pid = 0; + sts.b_iso_out.framenum = 0; + + offset = 0; + for(i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; i+= dwc_ep->pkt_per_frm) + { + + for(j = 0; j < dwc_ep->pkt_per_frm; ++j) + { + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ? + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket; + + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0; + sts.b_iso_out.rxbytes = data_per_desc; + writel((uint32_t)dma_ad, &dma_desc->buf); + writel(sts.d32, &dma_desc->status); + + offset += data_per_desc; + dma_desc ++; + (uint32_t)dma_ad += data_per_desc; + } + } + + for(j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) + { + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ? + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket; + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0; + sts.b_iso_out.rxbytes = data_per_desc; + writel((uint32_t)dma_ad, &dma_desc->buf); + writel(sts.d32, &dma_desc->status); + + offset += data_per_desc; + dma_desc ++; + (uint32_t)dma_ad += data_per_desc; + } + + sts.b_iso_out.ioc = 1; + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ? + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket; + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0; + sts.b_iso_out.rxbytes = data_per_desc; + + writel((uint32_t)dma_ad, &dma_desc->buf); + writel(sts.d32, &dma_desc->status); + dma_desc ++; + + /** Buffer 1 descriptors setup */ + sts.b_iso_out.ioc = 0; + dma_ad = dwc_ep->dma_addr1; + + offset = 0; + for(i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; i+= dwc_ep->pkt_per_frm) + { + for(j = 0; j < dwc_ep->pkt_per_frm; ++j) + { + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ? + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket; + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0; + sts.b_iso_out.rxbytes = data_per_desc; + writel((uint32_t)dma_ad, &dma_desc->buf); + writel(sts.d32, &dma_desc->status); + + offset += data_per_desc; + dma_desc ++; + (uint32_t)dma_ad += data_per_desc; + } + } + for(j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) + { + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ? + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket; + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0; + sts.b_iso_out.rxbytes = data_per_desc; + writel((uint32_t)dma_ad, &dma_desc->buf); + writel(sts.d32, &dma_desc->status); + + offset += data_per_desc; + dma_desc ++; + (uint32_t)dma_ad += data_per_desc; + } + + sts.b_iso_out.ioc = 1; + sts.b_iso_out.l = 1; + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ? + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket; + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0; + sts.b_iso_out.rxbytes = data_per_desc; + + writel((uint32_t)dma_ad, &dma_desc->buf); + writel(sts.d32, &dma_desc->status); + + dwc_ep->next_frame = 0; + + /** Write dma_ad into DOEPDMA register */ + dwc_write_reg32(&(out_regs->doepdma),(uint32_t)dwc_ep->iso_dma_desc_addr); + + } + /** ISO IN EP */ + else { + desc_sts_data_t sts = { .d32 =0 }; + dwc_otg_dma_desc_t* dma_desc = dwc_ep->iso_desc_addr; + dma_addr_t dma_ad; + dwc_otg_dev_in_ep_regs_t *in_regs = + core_if->dev_if->in_ep_regs[dwc_ep->num]; + unsigned int frmnumber; + fifosize_data_t txfifosize,rxfifosize; + + txfifosize.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[dwc_ep->num]->dtxfsts); + rxfifosize.d32 = dwc_read_reg32(&core_if->core_global_regs->grxfsiz); + + + addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl; + + dma_ad = dwc_ep->dma_addr0; + + dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); + + sts.b_iso_in.bs = BS_HOST_READY; + sts.b_iso_in.txsts = 0; + sts.b_iso_in.sp = (dwc_ep->data_per_frame % dwc_ep->maxpacket)? 1 : 0; + sts.b_iso_in.ioc = 0; + sts.b_iso_in.pid = dwc_ep->pkt_per_frm; + + + frmnumber = dwc_ep->next_frame; + + sts.b_iso_in.framenum = frmnumber; + sts.b_iso_in.txbytes = dwc_ep->data_per_frame; + sts.b_iso_in.l = 0; + + /** Buffer 0 descriptors setup */ + for(i = 0; i < dwc_ep->desc_cnt - 1; i++) + { + writel((uint32_t)dma_ad, &dma_desc->buf); + writel(sts.d32, &dma_desc->status); + dma_desc ++; + + (uint32_t)dma_ad += dwc_ep->data_per_frame; + sts.b_iso_in.framenum += dwc_ep->bInterval; + } + + sts.b_iso_in.ioc = 1; + writel((uint32_t)dma_ad, &dma_desc->buf); + writel(sts.d32, &dma_desc->status); + ++dma_desc; + + /** Buffer 1 descriptors setup */ + sts.b_iso_in.ioc = 0; + dma_ad = dwc_ep->dma_addr1; + + for(i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; i+= dwc_ep->pkt_per_frm) + { + writel((uint32_t)dma_ad, &dma_desc->buf); + writel(sts.d32, &dma_desc->status); + dma_desc ++; + + (uint32_t)dma_ad += dwc_ep->data_per_frame; + sts.b_iso_in.framenum += dwc_ep->bInterval; + + sts.b_iso_in.ioc = 0; + } + sts.b_iso_in.ioc = 1; + sts.b_iso_in.l = 1; + + writel((uint32_t)dma_ad, &dma_desc->buf); + writel(sts.d32, &dma_desc->status); + + dwc_ep->next_frame = sts.b_iso_in.framenum + dwc_ep->bInterval; + + /** Write dma_ad into diepdma register */ + dwc_write_reg32(&(in_regs->diepdma),(uint32_t)dwc_ep->iso_dma_desc_addr); + } + /** Enable endpoint, clear nak */ + depctl.d32 = 0; + depctl.b.epena = 1; + depctl.b.usbactep = 1; + depctl.b.cnak = 1; + + dwc_modify_reg32(addr, depctl.d32,depctl.d32); + depctl.d32 = dwc_read_reg32(addr); +} + +/** + * This function initializes a descriptor chain for Isochronous transfer + * + * @param core_if Programming view of DWC_otg controller. + * @param ep The EP to start the transfer on. + * + */ + +void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) +{ + depctl_data_t depctl = { .d32 = 0 }; + volatile uint32_t *addr; + + + if(ep->is_in) { + addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl; + } else { + addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl; + } + + + if(core_if->dma_enable == 0 || core_if->dma_desc_enable!= 0) { + return; + } else { + deptsiz_data_t deptsiz = { .d32 = 0 }; + + ep->xfer_len = ep->data_per_frame * ep->buf_proc_intrvl / ep->bInterval; + ep->pkt_cnt = (ep->xfer_len - 1 + ep->maxpacket) / + ep->maxpacket; + ep->xfer_count = 0; + ep->xfer_buff = (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0; + ep->dma_addr = (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0; + + if(ep->is_in) { + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet + * exist ? 1 : 0) + */ + deptsiz.b.mc = ep->pkt_per_frm; + deptsiz.b.xfersize = ep->xfer_len; + deptsiz.b.pktcnt = + (ep->xfer_len - 1 + ep->maxpacket) / + ep->maxpacket; + dwc_write_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz, deptsiz.d32); + + /* Write the DMA register */ + dwc_write_reg32 (&(core_if->dev_if->in_ep_regs[ep->num]->diepdma), (uint32_t)ep->dma_addr); + + } else { + deptsiz.b.pktcnt = + (ep->xfer_len + (ep->maxpacket - 1)) / + ep->maxpacket; + deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket; + + dwc_write_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doeptsiz, deptsiz.d32); + + /* Write the DMA register */ + dwc_write_reg32 (&(core_if->dev_if->out_ep_regs[ep->num]->doepdma), (uint32_t)ep->dma_addr); + + } + /** Enable endpoint, clear nak */ + depctl.d32 = 0; + dwc_modify_reg32(addr, depctl.d32,depctl.d32); + + depctl.b.epena = 1; + depctl.b.cnak = 1; + + dwc_modify_reg32(addr, depctl.d32,depctl.d32); + } +} + + +/** + * This function does the setup for a data transfer for an EP and + * starts the transfer. For an IN transfer, the packets will be + * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, + * the packets are unloaded from the Rx FIFO in the ISR. the ISR. + * + * @param core_if Programming view of DWC_otg controller. + * @param ep The EP to start the transfer on. + */ + +void dwc_otg_iso_ep_start_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) +{ + if(core_if->dma_enable) { + if(core_if->dma_desc_enable) { + if(ep->is_in) { + ep->desc_cnt = ep->pkt_cnt / ep->pkt_per_frm; + } else { + ep->desc_cnt = ep->pkt_cnt; + } + dwc_otg_iso_ep_start_ddma_transfer(core_if, ep); + } else { + if(core_if->pti_enh_enable) { + dwc_otg_iso_ep_start_buf_transfer(core_if, ep); + } else { + ep->cur_pkt_addr = (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0; + ep->cur_pkt_dma_addr = (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0; + dwc_otg_iso_ep_start_frm_transfer(core_if, ep); + } + } + } else { + ep->cur_pkt_addr = (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0; + ep->cur_pkt_dma_addr = (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0; + dwc_otg_iso_ep_start_frm_transfer(core_if, ep); + } +} + +/** + * This function does the setup for a data transfer for an EP and + * starts the transfer. For an IN transfer, the packets will be + * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, + * the packets are unloaded from the Rx FIFO in the ISR. the ISR. + * + * @param core_if Programming view of DWC_otg controller. + * @param ep The EP to start the transfer on. + */ + +void dwc_otg_iso_ep_stop_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) +{ + depctl_data_t depctl = { .d32 = 0 }; + volatile uint32_t *addr; + + if(ep->is_in == 1) { + addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl; + } + else { + addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl; + } + + /* disable the ep */ + depctl.d32 = dwc_read_reg32(addr); + + depctl.b.epdis = 1; + depctl.b.snak = 1; + + dwc_write_reg32(addr, depctl.d32); + + if(core_if->dma_desc_enable && + ep->iso_desc_addr && ep->iso_dma_desc_addr) { + dwc_otg_ep_free_desc_chain(ep->iso_desc_addr,ep->iso_dma_desc_addr,ep->desc_cnt * 2); + } + + /* reset varibales */ + ep->dma_addr0 = 0; + ep->dma_addr1 = 0; + ep->xfer_buff0 = 0; + ep->xfer_buff1 = 0; + ep->data_per_frame = 0; + ep->data_pattern_frame = 0; + ep->sync_frame = 0; + ep->buf_proc_intrvl = 0; + ep->bInterval = 0; + ep->proc_buf_num = 0; + ep->pkt_per_frm = 0; + ep->pkt_per_frm = 0; + ep->desc_cnt = 0; + ep->iso_desc_addr = 0; + ep->iso_dma_desc_addr = 0; +} + + +/** + * This function is used to submit an ISOC Transfer Request to an EP. + * + * - Every time a sync period completes the request's completion callback + * is called to provide data to the gadget driver. + * - Once submitted the request cannot be modified. + * - Each request is turned into periodic data packets untill ISO + * Transfer is stopped.. + */ +static int dwc_otg_pcd_iso_ep_start(struct usb_ep *usb_ep, struct usb_iso_request *req, +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) + int gfp_flags +#else + gfp_t gfp_flags +#endif +) +{ + dwc_otg_pcd_ep_t *ep; + dwc_otg_pcd_t *pcd; + dwc_ep_t *dwc_ep; + unsigned long flags = 0; + int32_t frm_data; + dwc_otg_core_if_t *core_if; + dcfg_data_t dcfg; + dsts_data_t dsts; + + + if (!req || !req->process_buffer || !req->buf0 || !req->buf1) { + DWC_WARN("%s, bad params\n", __func__); + return -EINVAL; + } + + ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep); + + if (!usb_ep || !ep->desc || ep->dwc_ep.num == 0) { + DWC_WARN("%s, bad ep\n", __func__); + return -EINVAL; + } + + pcd = ep->pcd; + core_if = GET_CORE_IF(pcd); + + dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg); + + if (!pcd->driver || pcd->gadget.speed == USB_SPEED_UNKNOWN) { + DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n", pcd->gadget.speed); + DWC_WARN("%s, bogus device state\n", __func__); + return -ESHUTDOWN; + } + + SPIN_LOCK_IRQSAVE(&ep->pcd->lock, flags); + + dwc_ep = &ep->dwc_ep; + + if(ep->iso_req) { + DWC_WARN("%s, iso request in progress\n", __func__); + } + req->status = -EINPROGRESS; + + dwc_ep->dma_addr0 = req->dma0; + dwc_ep->dma_addr1 = req->dma1; + + dwc_ep->xfer_buff0 = req->buf0; + dwc_ep->xfer_buff1 = req->buf1; + + ep->iso_req = req; + + dwc_ep->data_per_frame = req->data_per_frame; + + /** @todo - pattern data support is to be implemented in the future */ + dwc_ep->data_pattern_frame = req->data_pattern_frame; + dwc_ep->sync_frame = req->sync_frame; + + dwc_ep->buf_proc_intrvl = req->buf_proc_intrvl; + + dwc_ep->bInterval = 1 << (ep->desc->bInterval - 1); + + dwc_ep->proc_buf_num = 0; + + dwc_ep->pkt_per_frm = 0; + frm_data = ep->dwc_ep.data_per_frame; + while(frm_data > 0) { + dwc_ep->pkt_per_frm++; + frm_data -= ep->dwc_ep.maxpacket; + } + + dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); + + if(req->flags & USB_REQ_ISO_ASAP) { + dwc_ep->next_frame = dsts.b.soffn + 1; + if(dwc_ep->bInterval != 1){ + dwc_ep->next_frame = dwc_ep->next_frame + (dwc_ep->bInterval - 1 - dwc_ep->next_frame % dwc_ep->bInterval); + } + } else { + dwc_ep->next_frame = req->start_frame; + } + + + if(!core_if->pti_enh_enable) { + dwc_ep->pkt_cnt = dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm / dwc_ep->bInterval; + } else { + dwc_ep->pkt_cnt = + (dwc_ep->data_per_frame * (dwc_ep->buf_proc_intrvl / dwc_ep->bInterval) + - 1 + dwc_ep->maxpacket) / dwc_ep->maxpacket; + } + + if(core_if->dma_desc_enable) { + dwc_ep->desc_cnt = + dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm / dwc_ep->bInterval; + } + + dwc_ep->pkt_info = kmalloc(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt, GFP_KERNEL); + if(!dwc_ep->pkt_info) { + return -ENOMEM; + } + if(core_if->pti_enh_enable) { + memset(dwc_ep->pkt_info, 0, sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt); + } + + dwc_ep->cur_pkt = 0; + + SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags); + + dwc_otg_iso_ep_start_transfer(core_if, dwc_ep); + + return 0; +} + +/** + * This function stops ISO EP Periodic Data Transfer. + */ +static int dwc_otg_pcd_iso_ep_stop(struct usb_ep *usb_ep, struct usb_iso_request *req) +{ + dwc_otg_pcd_ep_t *ep; + dwc_otg_pcd_t *pcd; + dwc_ep_t *dwc_ep; + unsigned long flags; + + ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep); + + if (!usb_ep || !ep->desc || ep->dwc_ep.num == 0) { + DWC_WARN("%s, bad ep\n", __func__); + return -EINVAL; + } + + pcd = ep->pcd; + + if (!pcd->driver || pcd->gadget.speed == USB_SPEED_UNKNOWN) { + DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n", pcd->gadget.speed); + DWC_WARN("%s, bogus device state\n", __func__); + return -ESHUTDOWN; + } + + dwc_ep = &ep->dwc_ep; + + dwc_otg_iso_ep_stop_transfer(GET_CORE_IF(pcd), dwc_ep); + + kfree(dwc_ep->pkt_info); + + SPIN_LOCK_IRQSAVE(&pcd->lock, flags); + + if(ep->iso_req != req) { + return -EINVAL; + } + + req->status = -ECONNRESET; + + SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags); + + + ep->iso_req = 0; + + return 0; +} + +/** + * This function is used for perodical data exchnage between PCD and gadget drivers. + * for Isochronous EPs + * + * - Every time a sync period completes this function is called to + * perform data exchange between PCD and gadget + */ +void dwc_otg_iso_buffer_done(dwc_otg_pcd_ep_t *ep, dwc_otg_pcd_iso_request_t *req) +{ + int i; + struct usb_gadget_iso_packet_descriptor *iso_packet; + dwc_ep_t *dwc_ep; + + dwc_ep = &ep->dwc_ep; + + if(ep->iso_req->status == -ECONNRESET) { + DWC_PRINT("Device has already disconnected\n"); + /*Device has been disconnected*/ + return; + } + + if(dwc_ep->proc_buf_num != 0) { + iso_packet = ep->iso_req->iso_packet_desc0; + } + + else { + iso_packet = ep->iso_req->iso_packet_desc1; + } + + /* Fill in ISOC packets descriptors & pass to gadget driver*/ + + for(i = 0; i < dwc_ep->pkt_cnt; ++i) { + iso_packet[i].status = dwc_ep->pkt_info[i].status; + iso_packet[i].offset = dwc_ep->pkt_info[i].offset; + iso_packet[i].actual_length = dwc_ep->pkt_info[i].length; + dwc_ep->pkt_info[i].status = 0; + dwc_ep->pkt_info[i].offset = 0; + dwc_ep->pkt_info[i].length = 0; + } + + /* Call callback function to process data buffer */ + ep->iso_req->status = 0;/* success */ + + SPIN_UNLOCK(&ep->pcd->lock); + ep->iso_req->process_buffer(&ep->ep, ep->iso_req); + SPIN_LOCK(&ep->pcd->lock); +} + + +static struct usb_iso_request *dwc_otg_pcd_alloc_iso_request(struct usb_ep *ep,int packets, +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) + int gfp_flags +#else + gfp_t gfp_flags +#endif +) +{ + struct usb_iso_request *pReq = NULL; + uint32_t req_size; + + + req_size = sizeof(struct usb_iso_request); + req_size += (2 * packets * (sizeof(struct usb_gadget_iso_packet_descriptor))); + + + pReq = kmalloc(req_size, gfp_flags); + if (!pReq) { + DWC_WARN("%s, can't allocate Iso Request\n", __func__); + return 0; + } + pReq->iso_packet_desc0 = (void*) (pReq + 1); + + pReq->iso_packet_desc1 = pReq->iso_packet_desc0 + packets; + + return pReq; +} + +static void dwc_otg_pcd_free_iso_request(struct usb_ep *ep, struct usb_iso_request *req) +{ + kfree(req); +} + +static struct usb_isoc_ep_ops dwc_otg_pcd_ep_ops = +{ + .ep_ops = + { + .enable = dwc_otg_pcd_ep_enable, + .disable = dwc_otg_pcd_ep_disable, + + .alloc_request = dwc_otg_pcd_alloc_request, + .free_request = dwc_otg_pcd_free_request, + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) + .alloc_buffer = dwc_otg_pcd_alloc_buffer, + .free_buffer = dwc_otg_pcd_free_buffer, +#endif + + .queue = dwc_otg_pcd_ep_queue, + .dequeue = dwc_otg_pcd_ep_dequeue, + + .set_halt = dwc_otg_pcd_ep_set_halt, + .fifo_status = 0, + .fifo_flush = 0, + }, + .iso_ep_start = dwc_otg_pcd_iso_ep_start, + .iso_ep_stop = dwc_otg_pcd_iso_ep_stop, + .alloc_iso_request = dwc_otg_pcd_alloc_iso_request, + .free_iso_request = dwc_otg_pcd_free_iso_request, +}; + +#else + + +static struct usb_ep_ops dwc_otg_pcd_ep_ops = +{ + .enable = dwc_otg_pcd_ep_enable, + .disable = dwc_otg_pcd_ep_disable, + + .alloc_request = dwc_otg_pcd_alloc_request, + .free_request = dwc_otg_pcd_free_request, + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) + .alloc_buffer = dwc_otg_pcd_alloc_buffer, + .free_buffer = dwc_otg_pcd_free_buffer, +#endif + + .queue = dwc_otg_pcd_ep_queue, + .dequeue = dwc_otg_pcd_ep_dequeue, + + .set_halt = dwc_otg_pcd_ep_set_halt, + .fifo_status = 0, + .fifo_flush = 0, + + +}; + +#endif /* DWC_EN_ISOC */ +/* Gadget Operations */ +/** + * The following gadget operations will be implemented in the DWC_otg + * PCD. Functions in the API that are not described below are not + * implemented. + * + * The Gadget API provides wrapper functions for each of the function + * pointers defined in usb_gadget_ops. The Gadget Driver calls the + * wrapper function, which then calls the underlying PCD function. The + * following sections are named according to the wrapper functions + * (except for ioctl, which doesn't have a wrapper function). Within + * each section, the corresponding DWC_otg PCD function name is + * specified. + * + */ + +/** + *Gets the USB Frame number of the last SOF. + */ +static int dwc_otg_pcd_get_frame(struct usb_gadget *gadget) +{ + dwc_otg_pcd_t *pcd; + + DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, gadget); + + if (gadget == 0) { + return -ENODEV; + } + else { + pcd = container_of(gadget, dwc_otg_pcd_t, gadget); + dwc_otg_get_frame_number(GET_CORE_IF(pcd)); + } + + return 0; +} + +void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t *pcd) +{ + uint32_t *addr = (uint32_t *)&(GET_CORE_IF(pcd)->core_global_regs->gotgctl); + gotgctl_data_t mem; + gotgctl_data_t val; + + val.d32 = dwc_read_reg32(addr); + if (val.b.sesreq) { + DWC_ERROR("Session Request Already active!\n"); + return; + } + + DWC_NOTICE("Session Request Initated\n"); + mem.d32 = dwc_read_reg32(addr); + mem.b.sesreq = 1; + dwc_write_reg32(addr, mem.d32); + + /* Start the SRP timer */ + dwc_otg_pcd_start_srp_timer(pcd); + return; +} + +void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t *pcd, int set) +{ + dctl_data_t dctl = {.d32=0}; + volatile uint32_t *addr = &(GET_CORE_IF(pcd)->dev_if->dev_global_regs->dctl); + + if (dwc_otg_is_device_mode(GET_CORE_IF(pcd))) { + if (pcd->remote_wakeup_enable) { + if (set) { + dctl.b.rmtwkupsig = 1; + dwc_modify_reg32(addr, 0, dctl.d32); + DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n"); + mdelay(1); + dwc_modify_reg32(addr, dctl.d32, 0); + DWC_DEBUGPL(DBG_PCD, "Clear Remote Wakeup\n"); + } + else { + } + } + else { + DWC_DEBUGPL(DBG_PCD, "Remote Wakeup is disabled\n"); + } + } + return; +} + +/** + * Initiates Session Request Protocol (SRP) to wakeup the host if no + * session is in progress. If a session is already in progress, but + * the device is suspended, remote wakeup signaling is started. + * + */ +static int dwc_otg_pcd_wakeup(struct usb_gadget *gadget) +{ + unsigned long flags; + dwc_otg_pcd_t *pcd; + dsts_data_t dsts; + gotgctl_data_t gotgctl; + + DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, gadget); + + if (gadget == 0) { + return -ENODEV; + } + else { + pcd = container_of(gadget, dwc_otg_pcd_t, gadget); + } + SPIN_LOCK_IRQSAVE(&pcd->lock, flags); + + /* + * This function starts the Protocol if no session is in progress. If + * a session is already in progress, but the device is suspended, + * remote wakeup signaling is started. + */ + + /* Check if valid session */ + gotgctl.d32 = dwc_read_reg32(&(GET_CORE_IF(pcd)->core_global_regs->gotgctl)); + if (gotgctl.b.bsesvld) { + /* Check if suspend state */ + dsts.d32 = dwc_read_reg32(&(GET_CORE_IF(pcd)->dev_if->dev_global_regs->dsts)); + if (dsts.b.suspsts) { + dwc_otg_pcd_remote_wakeup(pcd, 1); + } + } + else { + dwc_otg_pcd_initiate_srp(pcd); + } + + SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags); + return 0; +} + +static const struct usb_gadget_ops dwc_otg_pcd_ops = +{ + .get_frame = dwc_otg_pcd_get_frame, + .wakeup = dwc_otg_pcd_wakeup, + // current versions must always be self-powered +}; + +/** + * This function updates the otg values in the gadget structure. + */ +void dwc_otg_pcd_update_otg(dwc_otg_pcd_t *pcd, const unsigned reset) +{ + + if (!pcd->gadget.is_otg) + return; + + if (reset) { + pcd->b_hnp_enable = 0; + pcd->a_hnp_support = 0; + pcd->a_alt_hnp_support = 0; + } + + pcd->gadget.b_hnp_enable = pcd->b_hnp_enable; + pcd->gadget.a_hnp_support = pcd->a_hnp_support; + pcd->gadget.a_alt_hnp_support = pcd->a_alt_hnp_support; +} + +/** + * This function is the top level PCD interrupt handler. + */ +static irqreturn_t dwc_otg_pcd_irq(int irq, void *dev +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) + , struct pt_regs *r +#endif + ) +{ + dwc_otg_pcd_t *pcd = dev; + int32_t retval = IRQ_NONE; + + retval = dwc_otg_pcd_handle_intr(pcd); + return IRQ_RETVAL(retval); +} + +/** + * PCD Callback function for initializing the PCD when switching to + * device mode. + * + * @param p void pointer to the dwc_otg_pcd_t + */ +static int32_t dwc_otg_pcd_start_cb(void *p) +{ + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)p; + + /* + * Initialized the Core for Device mode. + */ + if (dwc_otg_is_device_mode(GET_CORE_IF(pcd))) { + dwc_otg_core_dev_init(GET_CORE_IF(pcd)); + } + return 1; +} + +/** + * PCD Callback function for stopping the PCD when switching to Host + * mode. + * + * @param p void pointer to the dwc_otg_pcd_t + */ +static int32_t dwc_otg_pcd_stop_cb(void *p) +{ + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)p; + extern void dwc_otg_pcd_stop(dwc_otg_pcd_t *_pcd); + + dwc_otg_pcd_stop(pcd); + return 1; +} + + +/** + * PCD Callback function for notifying the PCD when resuming from + * suspend. + * + * @param p void pointer to the dwc_otg_pcd_t + */ +static int32_t dwc_otg_pcd_suspend_cb(void *p) +{ + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)p; + + if (pcd->driver && pcd->driver->resume) { + SPIN_UNLOCK(&pcd->lock); + pcd->driver->suspend(&pcd->gadget); + SPIN_LOCK(&pcd->lock); + } + + return 1; +} + + +/** + * PCD Callback function for notifying the PCD when resuming from + * suspend. + * + * @param p void pointer to the dwc_otg_pcd_t + */ +static int32_t dwc_otg_pcd_resume_cb(void *p) +{ + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)p; + + if (pcd->driver && pcd->driver->resume) { + SPIN_UNLOCK(&pcd->lock); + pcd->driver->resume(&pcd->gadget); + SPIN_LOCK(&pcd->lock); + } + + /* Stop the SRP timeout timer. */ + if ((GET_CORE_IF(pcd)->core_params->phy_type != DWC_PHY_TYPE_PARAM_FS) || + (!GET_CORE_IF(pcd)->core_params->i2c_enable)) { + if (GET_CORE_IF(pcd)->srp_timer_started) { + GET_CORE_IF(pcd)->srp_timer_started = 0; + del_timer(&pcd->srp_timer); + } + } + return 1; +} + + +/** + * PCD Callback structure for handling mode switching. + */ +static dwc_otg_cil_callbacks_t pcd_callbacks = +{ + .start = dwc_otg_pcd_start_cb, + .stop = dwc_otg_pcd_stop_cb, + .suspend = dwc_otg_pcd_suspend_cb, + .resume_wakeup = dwc_otg_pcd_resume_cb, + .p = 0, /* Set at registration */ +}; + +/** + * This function is called when the SRP timer expires. The SRP should + * complete within 6 seconds. + */ +static void srp_timeout(unsigned long ptr) +{ + gotgctl_data_t gotgctl; + dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *)ptr; + volatile uint32_t *addr = &core_if->core_global_regs->gotgctl; + + gotgctl.d32 = dwc_read_reg32(addr); + + core_if->srp_timer_started = 0; + + if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) && + (core_if->core_params->i2c_enable)) { + DWC_PRINT("SRP Timeout\n"); + + if ((core_if->srp_success) && + (gotgctl.b.bsesvld)) { + if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) { + core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p); + } + + /* Clear Session Request */ + gotgctl.d32 = 0; + gotgctl.b.sesreq = 1; + dwc_modify_reg32(&core_if->core_global_regs->gotgctl, + gotgctl.d32, 0); + + core_if->srp_success = 0; + } + else { + DWC_ERROR("Device not connected/responding\n"); + gotgctl.b.sesreq = 0; + dwc_write_reg32(addr, gotgctl.d32); + } + } + else if (gotgctl.b.sesreq) { + DWC_PRINT("SRP Timeout\n"); + + DWC_ERROR("Device not connected/responding\n"); + gotgctl.b.sesreq = 0; + dwc_write_reg32(addr, gotgctl.d32); + } + else { + DWC_PRINT(" SRP GOTGCTL=%0x\n", gotgctl.d32); + } +} + +/** + * Start the SRP timer to detect when the SRP does not complete within + * 6 seconds. + * + * @param pcd the pcd structure. + */ +void dwc_otg_pcd_start_srp_timer(dwc_otg_pcd_t *pcd) +{ + struct timer_list *srp_timer = &pcd->srp_timer; + GET_CORE_IF(pcd)->srp_timer_started = 1; + init_timer(srp_timer); + srp_timer->function = srp_timeout; + srp_timer->data = (unsigned long)GET_CORE_IF(pcd); + srp_timer->expires = jiffies + (HZ*6); + add_timer(srp_timer); +} + +/** + * Tasklet + * + */ +extern void start_next_request(dwc_otg_pcd_ep_t *ep); + +static void start_xfer_tasklet_func (unsigned long data) +{ + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t*)data; + dwc_otg_core_if_t *core_if = pcd->otg_dev->core_if; + + int i; + depctl_data_t diepctl; + + DWC_DEBUGPL(DBG_PCDV, "Start xfer tasklet\n"); + + diepctl.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[0]->diepctl); + + if (pcd->ep0.queue_sof) { + pcd->ep0.queue_sof = 0; + start_next_request (&pcd->ep0); + // break; + } + + for (i=0; idev_if->num_in_eps; i++) + { + depctl_data_t diepctl; + diepctl.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[i]->diepctl); + + if (pcd->in_ep[i].queue_sof) { + pcd->in_ep[i].queue_sof = 0; + start_next_request (&pcd->in_ep[i]); + // break; + } + } + + return; +} + + + + + + + +static struct tasklet_struct start_xfer_tasklet = { + .next = NULL, + .state = 0, + .count = ATOMIC_INIT(0), + .func = start_xfer_tasklet_func, + .data = 0, +}; +/** + * This function initialized the pcd Dp structures to there default + * state. + * + * @param pcd the pcd structure. + */ +void dwc_otg_pcd_reinit(dwc_otg_pcd_t *pcd) +{ + static const char * names[] = + { + + "ep0", + "ep1in", + "ep2in", + "ep3in", + "ep4in", + "ep5in", + "ep6in", + "ep7in", + "ep8in", + "ep9in", + "ep10in", + "ep11in", + "ep12in", + "ep13in", + "ep14in", + "ep15in", + "ep1out", + "ep2out", + "ep3out", + "ep4out", + "ep5out", + "ep6out", + "ep7out", + "ep8out", + "ep9out", + "ep10out", + "ep11out", + "ep12out", + "ep13out", + "ep14out", + "ep15out" + + }; + + int i; + int in_ep_cntr, out_ep_cntr; + uint32_t hwcfg1; + uint32_t num_in_eps = (GET_CORE_IF(pcd))->dev_if->num_in_eps; + uint32_t num_out_eps = (GET_CORE_IF(pcd))->dev_if->num_out_eps; + dwc_otg_pcd_ep_t *ep; + + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pcd); + + INIT_LIST_HEAD (&pcd->gadget.ep_list); + pcd->gadget.ep0 = &pcd->ep0.ep; + pcd->gadget.speed = USB_SPEED_UNKNOWN; + + INIT_LIST_HEAD (&pcd->gadget.ep0->ep_list); + + /** + * Initialize the EP0 structure. + */ + ep = &pcd->ep0; + + /* Init EP structure */ + ep->desc = 0; + ep->pcd = pcd; + ep->stopped = 1; + + /* Init DWC ep structure */ + ep->dwc_ep.num = 0; + ep->dwc_ep.active = 0; + ep->dwc_ep.tx_fifo_num = 0; + /* Control until ep is actvated */ + ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL; + ep->dwc_ep.maxpacket = MAX_PACKET_SIZE; + ep->dwc_ep.dma_addr = 0; + ep->dwc_ep.start_xfer_buff = 0; + ep->dwc_ep.xfer_buff = 0; + ep->dwc_ep.xfer_len = 0; + ep->dwc_ep.xfer_count = 0; + ep->dwc_ep.sent_zlp = 0; + ep->dwc_ep.total_len = 0; + ep->queue_sof = 0; + ep->dwc_ep.desc_addr = 0; + ep->dwc_ep.dma_desc_addr = 0; + + + /* Init the usb_ep structure. */ + ep->ep.name = names[0]; + ep->ep.ops = (struct usb_ep_ops*)&dwc_otg_pcd_ep_ops; + + /** + * @todo NGS: What should the max packet size be set to + * here? Before EP type is set? + */ + ep->ep.maxpacket = MAX_PACKET_SIZE; + + list_add_tail (&ep->ep.ep_list, &pcd->gadget.ep_list); + + INIT_LIST_HEAD (&ep->queue); + /** + * Initialize the EP structures. + */ + in_ep_cntr = 0; + hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 3; + + for (i = 1; in_ep_cntr < num_in_eps; i++) + { + if((hwcfg1 & 0x1) == 0) { + dwc_otg_pcd_ep_t *ep = &pcd->in_ep[in_ep_cntr]; + in_ep_cntr ++; + + /* Init EP structure */ + ep->desc = 0; + ep->pcd = pcd; + ep->stopped = 1; + + /* Init DWC ep structure */ + ep->dwc_ep.is_in = 1; + ep->dwc_ep.num = i; + ep->dwc_ep.active = 0; + ep->dwc_ep.tx_fifo_num = 0; + + /* Control until ep is actvated */ + ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL; + ep->dwc_ep.maxpacket = MAX_PACKET_SIZE; + ep->dwc_ep.dma_addr = 0; + ep->dwc_ep.start_xfer_buff = 0; + ep->dwc_ep.xfer_buff = 0; + ep->dwc_ep.xfer_len = 0; + ep->dwc_ep.xfer_count = 0; + ep->dwc_ep.sent_zlp = 0; + ep->dwc_ep.total_len = 0; + ep->queue_sof = 0; + ep->dwc_ep.desc_addr = 0; + ep->dwc_ep.dma_desc_addr = 0; + + /* Init the usb_ep structure. */ + ep->ep.name = names[i]; + ep->ep.ops = (struct usb_ep_ops*)&dwc_otg_pcd_ep_ops; + + /** + * @todo NGS: What should the max packet size be set to + * here? Before EP type is set? + */ + ep->ep.maxpacket = MAX_PACKET_SIZE; + + list_add_tail (&ep->ep.ep_list, &pcd->gadget.ep_list); + + INIT_LIST_HEAD (&ep->queue); + } + hwcfg1 >>= 2; + } + + out_ep_cntr = 0; + hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 2; + + for (i = 1; out_ep_cntr < num_out_eps; i++) + { + if((hwcfg1 & 0x1) == 0) { + dwc_otg_pcd_ep_t *ep = &pcd->out_ep[out_ep_cntr]; + out_ep_cntr++; + + /* Init EP structure */ + ep->desc = 0; + ep->pcd = pcd; + ep->stopped = 1; + + /* Init DWC ep structure */ + ep->dwc_ep.is_in = 0; + ep->dwc_ep.num = i; + ep->dwc_ep.active = 0; + ep->dwc_ep.tx_fifo_num = 0; + /* Control until ep is actvated */ + ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL; + ep->dwc_ep.maxpacket = MAX_PACKET_SIZE; + ep->dwc_ep.dma_addr = 0; + ep->dwc_ep.start_xfer_buff = 0; + ep->dwc_ep.xfer_buff = 0; + ep->dwc_ep.xfer_len = 0; + ep->dwc_ep.xfer_count = 0; + ep->dwc_ep.sent_zlp = 0; + ep->dwc_ep.total_len = 0; + ep->queue_sof = 0; + + /* Init the usb_ep structure. */ + ep->ep.name = names[15 + i]; + ep->ep.ops = (struct usb_ep_ops*)&dwc_otg_pcd_ep_ops; + /** + * @todo NGS: What should the max packet size be set to + * here? Before EP type is set? + */ + ep->ep.maxpacket = MAX_PACKET_SIZE; + + list_add_tail (&ep->ep.ep_list, &pcd->gadget.ep_list); + + INIT_LIST_HEAD (&ep->queue); + } + hwcfg1 >>= 2; + } + + /* remove ep0 from the list. There is a ep0 pointer.*/ + list_del_init (&pcd->ep0.ep.ep_list); + + pcd->ep0state = EP0_DISCONNECT; + pcd->ep0.ep.maxpacket = MAX_EP0_SIZE; + pcd->ep0.dwc_ep.maxpacket = MAX_EP0_SIZE; + pcd->ep0.dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL; +} + +/** + * This function releases the Gadget device. + * required by device_unregister(). + * + * @todo Should this do something? Should it free the PCD? + */ +static void dwc_otg_pcd_gadget_release(struct device *dev) +{ + DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, dev); +} + + + +/** + * This function initialized the PCD portion of the driver. + * + */ + +int dwc_otg_pcd_init(struct device *dev) +{ + static char pcd_name[] = "dwc_otg_pcd"; + dwc_otg_pcd_t *pcd; + dwc_otg_core_if_t* core_if; + dwc_otg_dev_if_t* dev_if; + dwc_otg_device_t *otg_dev = dev_get_drvdata(dev); + int retval = 0; + + + DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n",__func__, dev); + /* + * Allocate PCD structure + */ + pcd = kmalloc(sizeof(dwc_otg_pcd_t), GFP_KERNEL); + + if (pcd == 0) { + return -ENOMEM; + } + + memset(pcd, 0, sizeof(dwc_otg_pcd_t)); + spin_lock_init(&pcd->lock); + + otg_dev->pcd = pcd; + s_pcd = pcd; + pcd->gadget.name = pcd_name; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) + strcpy(pcd->gadget.dev.bus_id, "gadget"); +#else + dev_set_name(&pcd->gadget.dev, "%s", "gadget"); +#endif + + pcd->otg_dev = dev_get_drvdata(dev); + + pcd->gadget.dev.parent = dev; + pcd->gadget.dev.release = dwc_otg_pcd_gadget_release; + pcd->gadget.ops = &dwc_otg_pcd_ops; + + core_if = GET_CORE_IF(pcd); + dev_if = core_if->dev_if; + + if(core_if->hwcfg4.b.ded_fifo_en) { + DWC_PRINT("Dedicated Tx FIFOs mode\n"); + } + else { + DWC_PRINT("Shared Tx FIFO mode\n"); + } + + /* If the module is set to FS or if the PHY_TYPE is FS then the gadget + * should not report as dual-speed capable. replace the following line + * with the block of code below it once the software is debugged for + * this. If is_dualspeed = 0 then the gadget driver should not report + * a device qualifier descriptor when queried. */ + if ((GET_CORE_IF(pcd)->core_params->speed == DWC_SPEED_PARAM_FULL) || + ((GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == 2) && + (GET_CORE_IF(pcd)->hwcfg2.b.fs_phy_type == 1) && + (GET_CORE_IF(pcd)->core_params->ulpi_fs_ls))) { + pcd->gadget.is_dualspeed = 0; + } + else { + pcd->gadget.is_dualspeed = 1; + } + + if ((otg_dev->core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE) || + (otg_dev->core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST) || + (otg_dev->core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) || + (otg_dev->core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) { + pcd->gadget.is_otg = 0; + } + else { + pcd->gadget.is_otg = 1; + } + + + pcd->driver = 0; + /* Register the gadget device */ + retval = device_register(&pcd->gadget.dev); + if (retval != 0) { + kfree (pcd); + return retval; + } + + + /* + * Initialized the Core for Device mode. + */ + if (dwc_otg_is_device_mode(core_if)) { + dwc_otg_core_dev_init(core_if); + } + + /* + * Initialize EP structures + */ + dwc_otg_pcd_reinit(pcd); + + /* + * Register the PCD Callbacks. + */ + dwc_otg_cil_register_pcd_callbacks(otg_dev->core_if, &pcd_callbacks, + pcd); + /* + * Setup interupt handler + */ + DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n", otg_dev->irq); + retval = request_irq(otg_dev->irq, dwc_otg_pcd_irq, + IRQF_SHARED, pcd->gadget.name, pcd); + if (retval != 0) { + DWC_ERROR("request of irq%d failed\n", otg_dev->irq); + device_unregister(&pcd->gadget.dev); + kfree (pcd); + return -EBUSY; + } + + /* + * Initialize the DMA buffer for SETUP packets + */ + if (GET_CORE_IF(pcd)->dma_enable) { + pcd->setup_pkt = dma_alloc_coherent (NULL, sizeof (*pcd->setup_pkt) * 5, &pcd->setup_pkt_dma_handle, 0); + if (pcd->setup_pkt == 0) { + free_irq(otg_dev->irq, pcd); + device_unregister(&pcd->gadget.dev); + kfree (pcd); + return -ENOMEM; + } + + pcd->status_buf = dma_alloc_coherent (NULL, sizeof (uint16_t), &pcd->status_buf_dma_handle, 0); + if (pcd->status_buf == 0) { + dma_free_coherent(NULL, sizeof(*pcd->setup_pkt), pcd->setup_pkt, pcd->setup_pkt_dma_handle); + free_irq(otg_dev->irq, pcd); + device_unregister(&pcd->gadget.dev); + kfree (pcd); + return -ENOMEM; + } + + if (GET_CORE_IF(pcd)->dma_desc_enable) { + dev_if->setup_desc_addr[0] = dwc_otg_ep_alloc_desc_chain(&dev_if->dma_setup_desc_addr[0], 1); + dev_if->setup_desc_addr[1] = dwc_otg_ep_alloc_desc_chain(&dev_if->dma_setup_desc_addr[1], 1); + dev_if->in_desc_addr = dwc_otg_ep_alloc_desc_chain(&dev_if->dma_in_desc_addr, 1); + dev_if->out_desc_addr = dwc_otg_ep_alloc_desc_chain(&dev_if->dma_out_desc_addr, 1); + + if(dev_if->setup_desc_addr[0] == 0 + || dev_if->setup_desc_addr[1] == 0 + || dev_if->in_desc_addr == 0 + || dev_if->out_desc_addr == 0 ) { + + if(dev_if->out_desc_addr) + dwc_otg_ep_free_desc_chain(dev_if->out_desc_addr, dev_if->dma_out_desc_addr, 1); + if(dev_if->in_desc_addr) + dwc_otg_ep_free_desc_chain(dev_if->in_desc_addr, dev_if->dma_in_desc_addr, 1); + if(dev_if->setup_desc_addr[1]) + dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[1], dev_if->dma_setup_desc_addr[1], 1); + if(dev_if->setup_desc_addr[0]) + dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[0], dev_if->dma_setup_desc_addr[0], 1); + + + dma_free_coherent(NULL, sizeof(*pcd->status_buf), pcd->status_buf, pcd->setup_pkt_dma_handle); + dma_free_coherent(NULL, sizeof(*pcd->setup_pkt), pcd->setup_pkt, pcd->setup_pkt_dma_handle); + + free_irq(otg_dev->irq, pcd); + device_unregister(&pcd->gadget.dev); + kfree (pcd); + + return -ENOMEM; + } + } + } + else { + pcd->setup_pkt = kmalloc (sizeof (*pcd->setup_pkt) * 5, GFP_KERNEL); + if (pcd->setup_pkt == 0) { + free_irq(otg_dev->irq, pcd); + device_unregister(&pcd->gadget.dev); + kfree (pcd); + return -ENOMEM; + } + + pcd->status_buf = kmalloc (sizeof (uint16_t), GFP_KERNEL); + if (pcd->status_buf == 0) { + kfree(pcd->setup_pkt); + free_irq(otg_dev->irq, pcd); + device_unregister(&pcd->gadget.dev); + kfree (pcd); + return -ENOMEM; + } + } + + + /* Initialize tasklet */ + start_xfer_tasklet.data = (unsigned long)pcd; + pcd->start_xfer_tasklet = &start_xfer_tasklet; + + return 0; +} + +/** + * Cleanup the PCD. + */ +void dwc_otg_pcd_remove(struct device *dev) +{ + dwc_otg_device_t *otg_dev = dev_get_drvdata(dev); + dwc_otg_pcd_t *pcd = otg_dev->pcd; + dwc_otg_dev_if_t* dev_if = GET_CORE_IF(pcd)->dev_if; + + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, dev); + + /* + * Free the IRQ + */ + free_irq(otg_dev->irq, pcd); + + /* start with the driver above us */ + if (pcd->driver) { + /* should have been done already by driver model core */ + DWC_WARN("driver '%s' is still registered\n", + pcd->driver->driver.name); + usb_gadget_unregister_driver(pcd->driver); + } + device_unregister(&pcd->gadget.dev); + + if (GET_CORE_IF(pcd)->dma_enable) { + dma_free_coherent (NULL, sizeof (*pcd->setup_pkt) * 5, pcd->setup_pkt, pcd->setup_pkt_dma_handle); + dma_free_coherent (NULL, sizeof (uint16_t), pcd->status_buf, pcd->status_buf_dma_handle); + if (GET_CORE_IF(pcd)->dma_desc_enable) { + dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[0], dev_if->dma_setup_desc_addr[0], 1); + dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[1], dev_if->dma_setup_desc_addr[1], 1); + dwc_otg_ep_free_desc_chain(dev_if->in_desc_addr, dev_if->dma_in_desc_addr, 1); + dwc_otg_ep_free_desc_chain(dev_if->out_desc_addr, dev_if->dma_out_desc_addr, 1); + } + } + else { + kfree (pcd->setup_pkt); + kfree (pcd->status_buf); + } + + kfree(pcd); + otg_dev->pcd = 0; +} + +/** + * This function registers a gadget driver with the PCD. + * + * When a driver is successfully registered, it will receive control + * requests including set_configuration(), which enables non-control + * requests. then usb traffic follows until a disconnect is reported. + * then a host may connect again, or the driver might get unbound. + * + * @param driver The driver being registered + */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37) +int usb_gadget_probe_driver(struct usb_gadget_driver *driver, int (*bind)(struct usb_gadget *)) +#else +int usb_gadget_register_driver(struct usb_gadget_driver *driver) +#endif +{ + int retval; + int (*d_bind)(struct usb_gadget *); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37) + d_bind = bind; +#else + d_bind = driver->bind; +#endif + + DWC_DEBUGPL(DBG_PCD, "registering gadget driver '%s'\n", driver->driver.name); + + if (!driver || driver->speed == USB_SPEED_UNKNOWN || + !d_bind || + !driver->unbind || + !driver->disconnect || + !driver->setup) { + DWC_DEBUGPL(DBG_PCDV,"EINVAL\n"); + return -EINVAL; + } + if (s_pcd == 0) { + DWC_DEBUGPL(DBG_PCDV,"ENODEV\n"); + return -ENODEV; + } + if (s_pcd->driver != 0) { + DWC_DEBUGPL(DBG_PCDV,"EBUSY (%p)\n", s_pcd->driver); + return -EBUSY; + } + + /* hook up the driver */ + s_pcd->driver = driver; + s_pcd->gadget.dev.driver = &driver->driver; + + DWC_DEBUGPL(DBG_PCD, "bind to driver %s\n", driver->driver.name); + retval = d_bind(&s_pcd->gadget); + if (retval) { + DWC_ERROR("bind to driver %s --> error %d\n", + driver->driver.name, retval); + s_pcd->driver = 0; + s_pcd->gadget.dev.driver = 0; + return retval; + } + DWC_DEBUGPL(DBG_ANY, "registered gadget driver '%s'\n", + driver->driver.name); + return 0; +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37) +EXPORT_SYMBOL(usb_gadget_probe_driver); +#else +EXPORT_SYMBOL(usb_gadget_register_driver); +#endif + +/** + * This function unregisters a gadget driver + * + * @param driver The driver being unregistered + */ +int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) +{ + //DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, _driver); + + if (s_pcd == 0) { + DWC_DEBUGPL(DBG_ANY, "%s Return(%d): s_pcd==0\n", __func__, + -ENODEV); + return -ENODEV; + } + if (driver == 0 || driver != s_pcd->driver) { + DWC_DEBUGPL(DBG_ANY, "%s Return(%d): driver?\n", __func__, + -EINVAL); + return -EINVAL; + } + + driver->unbind(&s_pcd->gadget); + s_pcd->driver = 0; + + DWC_DEBUGPL(DBG_ANY, "unregistered driver '%s'\n", + driver->driver.name); + return 0; +} +EXPORT_SYMBOL(usb_gadget_unregister_driver); + +#endif /* DWC_HOST_ONLY */ diff --git a/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_pcd.h b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_pcd.h new file mode 100644 index 0000000000..48de957840 --- /dev/null +++ b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_pcd.h @@ -0,0 +1,248 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $ + * $Revision: 1.2 $ + * $Date: 2008-11-21 05:39:15 $ + * $Change: 1103515 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and + * redistribute this Software in source and binary forms, with or without + * modification, provided that redistributions of source code must retain this + * notice. You may not view, use, disclose, copy or distribute this file or + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * ========================================================================== */ +#ifndef DWC_HOST_ONLY +#if !defined(__DWC_PCD_H__) +#define __DWC_PCD_H__ + +#include +#include +#include +#include + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21) +# include +#else +# include +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) +#include +#else +#include +#endif +#include +#include + +struct dwc_otg_device; + +#include "dwc_otg_cil.h" + +/** + * @file + * + * This file contains the structures, constants, and interfaces for + * the Perpherial Contoller Driver (PCD). + * + * The Peripheral Controller Driver (PCD) for Linux will implement the + * Gadget API, so that the existing Gadget drivers can be used. For + * the Mass Storage Function driver the File-backed USB Storage Gadget + * (FBS) driver will be used. The FBS driver supports the + * Control-Bulk (CB), Control-Bulk-Interrupt (CBI), and Bulk-Only + * transports. + * + */ + +/** Invalid DMA Address */ +#define DMA_ADDR_INVALID (~(dma_addr_t)0) +/** Maxpacket size for EP0 */ +#define MAX_EP0_SIZE 64 +/** Maxpacket size for any EP */ +#define MAX_PACKET_SIZE 1024 + +/** Max Transfer size for any EP */ +#define MAX_TRANSFER_SIZE 65535 + +/** Max DMA Descriptor count for any EP */ +#define MAX_DMA_DESC_CNT 64 + +/** + * Get the pointer to the core_if from the pcd pointer. + */ +#define GET_CORE_IF( _pcd ) (_pcd->otg_dev->core_if) + +/** + * States of EP0. + */ +typedef enum ep0_state +{ + EP0_DISCONNECT, /* no host */ + EP0_IDLE, + EP0_IN_DATA_PHASE, + EP0_OUT_DATA_PHASE, + EP0_IN_STATUS_PHASE, + EP0_OUT_STATUS_PHASE, + EP0_STALL, +} ep0state_e; + +/** Fordward declaration.*/ +struct dwc_otg_pcd; + +/** DWC_otg iso request structure. + * + */ +typedef struct usb_iso_request dwc_otg_pcd_iso_request_t; + +/** PCD EP structure. + * This structure describes an EP, there is an array of EPs in the PCD + * structure. + */ +typedef struct dwc_otg_pcd_ep +{ + /** USB EP data */ + struct usb_ep ep; + /** USB EP Descriptor */ + const struct usb_endpoint_descriptor *desc; + + /** queue of dwc_otg_pcd_requests. */ + struct list_head queue; + unsigned stopped : 1; + unsigned disabling : 1; + unsigned dma : 1; + unsigned queue_sof : 1; + +#ifdef DWC_EN_ISOC + /** DWC_otg Isochronous Transfer */ + struct usb_iso_request* iso_req; +#endif //DWC_EN_ISOC + + /** DWC_otg ep data. */ + dwc_ep_t dwc_ep; + + /** Pointer to PCD */ + struct dwc_otg_pcd *pcd; +}dwc_otg_pcd_ep_t; + + + +/** DWC_otg PCD Structure. + * This structure encapsulates the data for the dwc_otg PCD. + */ +typedef struct dwc_otg_pcd +{ + /** USB gadget */ + struct usb_gadget gadget; + /** USB gadget driver pointer*/ + struct usb_gadget_driver *driver; + /** The DWC otg device pointer. */ + struct dwc_otg_device *otg_dev; + + /** State of EP0 */ + ep0state_e ep0state; + /** EP0 Request is pending */ + unsigned ep0_pending : 1; + /** Indicates when SET CONFIGURATION Request is in process */ + unsigned request_config : 1; + /** The state of the Remote Wakeup Enable. */ + unsigned remote_wakeup_enable : 1; + /** The state of the B-Device HNP Enable. */ + unsigned b_hnp_enable : 1; + /** The state of A-Device HNP Support. */ + unsigned a_hnp_support : 1; + /** The state of the A-Device Alt HNP support. */ + unsigned a_alt_hnp_support : 1; + /** Count of pending Requests */ + unsigned request_pending; + + /** SETUP packet for EP0 + * This structure is allocated as a DMA buffer on PCD initialization + * with enough space for up to 3 setup packets. + */ + union + { + struct usb_ctrlrequest req; + uint32_t d32[2]; + } *setup_pkt; + + dma_addr_t setup_pkt_dma_handle; + + /** 2-byte dma buffer used to return status from GET_STATUS */ + uint16_t *status_buf; + dma_addr_t status_buf_dma_handle; + + /** EP0 */ + dwc_otg_pcd_ep_t ep0; + + /** Array of IN EPs. */ + dwc_otg_pcd_ep_t in_ep[ MAX_EPS_CHANNELS - 1]; + /** Array of OUT EPs. */ + dwc_otg_pcd_ep_t out_ep[ MAX_EPS_CHANNELS - 1]; + /** number of valid EPs in the above array. */ +// unsigned num_eps : 4; + spinlock_t lock; + /** Timer for SRP. If it expires before SRP is successful + * clear the SRP. */ + struct timer_list srp_timer; + + /** Tasklet to defer starting of TEST mode transmissions until + * Status Phase has been completed. + */ + struct tasklet_struct test_mode_tasklet; + + /** Tasklet to delay starting of xfer in DMA mode */ + struct tasklet_struct *start_xfer_tasklet; + + /** The test mode to enter when the tasklet is executed. */ + unsigned test_mode; + +} dwc_otg_pcd_t; + + +/** DWC_otg request structure. + * This structure is a list of requests. + */ +typedef struct +{ + struct usb_request req; /**< USB Request. */ + struct list_head queue; /**< queue of these requests. */ +} dwc_otg_pcd_request_t; + + +extern int dwc_otg_pcd_init(struct device *dev); + +//extern void dwc_otg_pcd_remove( struct dwc_otg_device *_otg_dev ); +extern void dwc_otg_pcd_remove( struct device *dev); +extern int32_t dwc_otg_pcd_handle_intr( dwc_otg_pcd_t *pcd ); +extern void dwc_otg_pcd_start_srp_timer(dwc_otg_pcd_t *pcd ); + +extern void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t *pcd); +extern void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t *pcd, int set); + +extern void dwc_otg_iso_buffer_done(dwc_otg_pcd_ep_t *ep, dwc_otg_pcd_iso_request_t *req); +extern void dwc_otg_request_done(dwc_otg_pcd_ep_t *_ep, dwc_otg_pcd_request_t *req, + int status); +extern void dwc_otg_request_nuke(dwc_otg_pcd_ep_t *_ep); +extern void dwc_otg_pcd_update_otg(dwc_otg_pcd_t *_pcd, + const unsigned reset); + +#endif +#endif /* DWC_HOST_ONLY */ diff --git a/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_pcd_intr.c b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_pcd_intr.c new file mode 100644 index 0000000000..fd44fd89c3 --- /dev/null +++ b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_pcd_intr.c @@ -0,0 +1,3654 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_intr.c $ + * $Revision: 1.2 $ + * $Date: 2008-11-21 05:39:15 $ + * $Change: 1115682 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and + * redistribute this Software in source and binary forms, with or without + * modification, provided that redistributions of source code must retain this + * notice. You may not view, use, disclose, copy or distribute this file or + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * ========================================================================== */ +#ifndef DWC_HOST_ONLY +#include +#include +#include + +#include "dwc_otg_driver.h" +#include "dwc_otg_pcd.h" + + +#define DEBUG_EP0 + +/* request functions defined in "dwc_otg_pcd.c" */ + +/** @file + * This file contains the implementation of the PCD Interrupt handlers. + * + * The PCD handles the device interrupts. Many conditions can cause a + * device interrupt. When an interrupt occurs, the device interrupt + * service routine determines the cause of the interrupt and + * dispatches handling to the appropriate function. These interrupt + * handling functions are described below. + * All interrupt registers are processed from LSB to MSB. + */ + + +/** + * This function prints the ep0 state for debug purposes. + */ +static inline void print_ep0_state(dwc_otg_pcd_t *pcd) +{ +#ifdef DEBUG + char str[40]; + + switch (pcd->ep0state) { + case EP0_DISCONNECT: + strcpy(str, "EP0_DISCONNECT"); + break; + case EP0_IDLE: + strcpy(str, "EP0_IDLE"); + break; + case EP0_IN_DATA_PHASE: + strcpy(str, "EP0_IN_DATA_PHASE"); + break; + case EP0_OUT_DATA_PHASE: + strcpy(str, "EP0_OUT_DATA_PHASE"); + break; + case EP0_IN_STATUS_PHASE: + strcpy(str,"EP0_IN_STATUS_PHASE"); + break; + case EP0_OUT_STATUS_PHASE: + strcpy(str,"EP0_OUT_STATUS_PHASE"); + break; + case EP0_STALL: + strcpy(str,"EP0_STALL"); + break; + default: + strcpy(str,"EP0_INVALID"); + } + + DWC_DEBUGPL(DBG_ANY, "%s(%d)\n", str, pcd->ep0state); +#endif +} + +/** + * This function returns pointer to in ep struct with number ep_num + */ +static inline dwc_otg_pcd_ep_t* get_in_ep(dwc_otg_pcd_t *pcd, uint32_t ep_num) +{ + int i; + int num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps; + if(ep_num == 0) { + return &pcd->ep0; + } + else { + for(i = 0; i < num_in_eps; ++i) + { + if(pcd->in_ep[i].dwc_ep.num == ep_num) + return &pcd->in_ep[i]; + } + return 0; + } +} +/** + * This function returns pointer to out ep struct with number ep_num + */ +static inline dwc_otg_pcd_ep_t* get_out_ep(dwc_otg_pcd_t *pcd, uint32_t ep_num) +{ + int i; + int num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps; + if(ep_num == 0) { + return &pcd->ep0; + } + else { + for(i = 0; i < num_out_eps; ++i) + { + if(pcd->out_ep[i].dwc_ep.num == ep_num) + return &pcd->out_ep[i]; + } + return 0; + } +} +/** + * This functions gets a pointer to an EP from the wIndex address + * value of the control request. + */ +static dwc_otg_pcd_ep_t *get_ep_by_addr (dwc_otg_pcd_t *pcd, u16 wIndex) +{ + dwc_otg_pcd_ep_t *ep; + + if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0) + return &pcd->ep0; + list_for_each_entry(ep, &pcd->gadget.ep_list, ep.ep_list) + { + u8 bEndpointAddress; + + if (!ep->desc) + continue; + + bEndpointAddress = ep->desc->bEndpointAddress; + if((wIndex & (USB_DIR_IN | USB_ENDPOINT_NUMBER_MASK)) + == (bEndpointAddress & (USB_DIR_IN | USB_ENDPOINT_NUMBER_MASK))) + return ep; + } + return NULL; +} + +/** + * This function checks the EP request queue, if the queue is not + * empty the next request is started. + */ +void start_next_request(dwc_otg_pcd_ep_t *ep) +{ + dwc_otg_pcd_request_t *req = 0; + uint32_t max_transfer = GET_CORE_IF(ep->pcd)->core_params->max_transfer_size; + + if (!list_empty(&ep->queue)) { + req = list_entry(ep->queue.next, + dwc_otg_pcd_request_t, queue); + + /* Setup and start the Transfer */ + ep->dwc_ep.dma_addr = req->req.dma; + ep->dwc_ep.start_xfer_buff = req->req.buf; + ep->dwc_ep.xfer_buff = req->req.buf; + ep->dwc_ep.sent_zlp = 0; + ep->dwc_ep.total_len = req->req.length; + ep->dwc_ep.xfer_len = 0; + ep->dwc_ep.xfer_count = 0; + + if(max_transfer > MAX_TRANSFER_SIZE) { + ep->dwc_ep.maxxfer = max_transfer - (max_transfer % ep->dwc_ep.maxpacket); + } else { + ep->dwc_ep.maxxfer = max_transfer; + } + + if(req->req.zero) { + if((ep->dwc_ep.total_len % ep->dwc_ep.maxpacket == 0) + && (ep->dwc_ep.total_len != 0)) { + ep->dwc_ep.sent_zlp = 1; + } + + } + + dwc_otg_ep_start_transfer(GET_CORE_IF(ep->pcd), &ep->dwc_ep); + } +} + +/** + * This function handles the SOF Interrupts. At this time the SOF + * Interrupt is disabled. + */ +int32_t dwc_otg_pcd_handle_sof_intr(dwc_otg_pcd_t *pcd) +{ + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); + + gintsts_data_t gintsts; + + DWC_DEBUGPL(DBG_PCD, "SOF\n"); + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.sofintr = 1; + dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32); + + return 1; +} + + +/** + * This function handles the Rx Status Queue Level Interrupt, which + * indicates that there is a least one packet in the Rx FIFO. The + * packets are moved from the FIFO to memory, where they will be + * processed when the Endpoint Interrupt Register indicates Transfer + * Complete or SETUP Phase Done. + * + * Repeat the following until the Rx Status Queue is empty: + * -# Read the Receive Status Pop Register (GRXSTSP) to get Packet + * info + * -# If Receive FIFO is empty then skip to step Clear the interrupt + * and exit + * -# If SETUP Packet call dwc_otg_read_setup_packet to copy the + * SETUP data to the buffer + * -# If OUT Data Packet call dwc_otg_read_packet to copy the data + * to the destination buffer + */ +int32_t dwc_otg_pcd_handle_rx_status_q_level_intr(dwc_otg_pcd_t *pcd) +{ + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; + gintmsk_data_t gintmask = {.d32=0}; + device_grxsts_data_t status; + dwc_otg_pcd_ep_t *ep; + gintsts_data_t gintsts; +#ifdef DEBUG + static char *dpid_str[] ={ "D0", "D2", "D1", "MDATA" }; +#endif + + //DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _pcd); + /* Disable the Rx Status Queue Level interrupt */ + gintmask.b.rxstsqlvl= 1; + dwc_modify_reg32(&global_regs->gintmsk, gintmask.d32, 0); + + /* Get the Status from the top of the FIFO */ + status.d32 = dwc_read_reg32(&global_regs->grxstsp); + + DWC_DEBUGPL(DBG_PCD, "EP:%d BCnt:%d DPID:%s " + "pktsts:%x Frame:%d(0x%0x)\n", + status.b.epnum, status.b.bcnt, + dpid_str[status.b.dpid], + status.b.pktsts, status.b.fn, status.b.fn); + /* Get pointer to EP structure */ + ep = get_out_ep(pcd, status.b.epnum); + + switch (status.b.pktsts) { + case DWC_DSTS_GOUT_NAK: + DWC_DEBUGPL(DBG_PCDV, "Global OUT NAK\n"); + break; + case DWC_STS_DATA_UPDT: + DWC_DEBUGPL(DBG_PCDV, "OUT Data Packet\n"); + if (status.b.bcnt && ep->dwc_ep.xfer_buff) { + /** @todo NGS Check for buffer overflow? */ + dwc_otg_read_packet(core_if, + ep->dwc_ep.xfer_buff, + status.b.bcnt); + ep->dwc_ep.xfer_count += status.b.bcnt; + ep->dwc_ep.xfer_buff += status.b.bcnt; + } + break; + case DWC_STS_XFER_COMP: + DWC_DEBUGPL(DBG_PCDV, "OUT Complete\n"); + break; + case DWC_DSTS_SETUP_COMP: +#ifdef DEBUG_EP0 + DWC_DEBUGPL(DBG_PCDV, "Setup Complete\n"); +#endif + break; +case DWC_DSTS_SETUP_UPDT: + dwc_otg_read_setup_packet(core_if, pcd->setup_pkt->d32); +#ifdef DEBUG_EP0 + DWC_DEBUGPL(DBG_PCD, + "SETUP PKT: %02x.%02x v%04x i%04x l%04x\n", + pcd->setup_pkt->req.bRequestType, + pcd->setup_pkt->req.bRequest, + pcd->setup_pkt->req.wValue, + pcd->setup_pkt->req.wIndex, + pcd->setup_pkt->req.wLength); +#endif + ep->dwc_ep.xfer_count += status.b.bcnt; + break; + default: + DWC_DEBUGPL(DBG_PCDV, "Invalid Packet Status (0x%0x)\n", + status.b.pktsts); + break; + } + + /* Enable the Rx Status Queue Level interrupt */ + dwc_modify_reg32(&global_regs->gintmsk, 0, gintmask.d32); + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.rxstsqlvl = 1; + dwc_write_reg32 (&global_regs->gintsts, gintsts.d32); + + //DWC_DEBUGPL(DBG_PCDV, "EXIT: %s\n", __func__); + return 1; +} +/** + * This function examines the Device IN Token Learning Queue to + * determine the EP number of the last IN token received. This + * implementation is for the Mass Storage device where there are only + * 2 IN EPs (Control-IN and BULK-IN). + * + * The EP numbers for the first six IN Tokens are in DTKNQR1 and there + * are 8 EP Numbers in each of the other possible DTKNQ Registers. + * + * @param core_if Programming view of DWC_otg controller. + * + */ +static inline int get_ep_of_last_in_token(dwc_otg_core_if_t *core_if) +{ + dwc_otg_device_global_regs_t *dev_global_regs = + core_if->dev_if->dev_global_regs; + const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth; + /* Number of Token Queue Registers */ + const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8; + dtknq1_data_t dtknqr1; + uint32_t in_tkn_epnums[4]; + int ndx = 0; + int i = 0; + volatile uint32_t *addr = &dev_global_regs->dtknqr1; + int epnum = 0; + + //DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH); + + + /* Read the DTKNQ Registers */ + for (i = 0; i < DTKNQ_REG_CNT; i++) + { + in_tkn_epnums[ i ] = dwc_read_reg32(addr); + DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i+1, + in_tkn_epnums[i]); + if (addr == &dev_global_regs->dvbusdis) { + addr = &dev_global_regs->dtknqr3_dthrctl; + } + else { + ++addr; + } + + } + + /* Copy the DTKNQR1 data to the bit field. */ + dtknqr1.d32 = in_tkn_epnums[0]; + /* Get the EP numbers */ + in_tkn_epnums[0] = dtknqr1.b.epnums0_5; + ndx = dtknqr1.b.intknwptr - 1; + + //DWC_DEBUGPL(DBG_PCDV,"ndx=%d\n",ndx); + if (ndx == -1) { + /** @todo Find a simpler way to calculate the max + * queue position.*/ + int cnt = TOKEN_Q_DEPTH; + if (TOKEN_Q_DEPTH <= 6) { + cnt = TOKEN_Q_DEPTH - 1; + } + else if (TOKEN_Q_DEPTH <= 14) { + cnt = TOKEN_Q_DEPTH - 7; + } + else if (TOKEN_Q_DEPTH <= 22) { + cnt = TOKEN_Q_DEPTH - 15; + } + else { + cnt = TOKEN_Q_DEPTH - 23; + } + epnum = (in_tkn_epnums[ DTKNQ_REG_CNT - 1 ] >> (cnt * 4)) & 0xF; + } + else { + if (ndx <= 5) { + epnum = (in_tkn_epnums[0] >> (ndx * 4)) & 0xF; + } + else if (ndx <= 13) { + ndx -= 6; + epnum = (in_tkn_epnums[1] >> (ndx * 4)) & 0xF; + } + else if (ndx <= 21) { + ndx -= 14; + epnum = (in_tkn_epnums[2] >> (ndx * 4)) & 0xF; + } + else if (ndx <= 29) { + ndx -= 22; + epnum = (in_tkn_epnums[3] >> (ndx * 4)) & 0xF; + } + } + //DWC_DEBUGPL(DBG_PCD,"epnum=%d\n",epnum); + return epnum; +} + +/** + * This interrupt occurs when the non-periodic Tx FIFO is half-empty. + * The active request is checked for the next packet to be loaded into + * the non-periodic Tx FIFO. + */ +int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr(dwc_otg_pcd_t *pcd) +{ + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); + dwc_otg_core_global_regs_t *global_regs = + core_if->core_global_regs; + dwc_otg_dev_in_ep_regs_t *ep_regs; + gnptxsts_data_t txstatus = {.d32 = 0}; + gintsts_data_t gintsts; + + int epnum = 0; + dwc_otg_pcd_ep_t *ep = 0; + uint32_t len = 0; + int dwords; + + /* Get the epnum from the IN Token Learning Queue. */ + epnum = get_ep_of_last_in_token(core_if); + ep = get_in_ep(pcd, epnum); + + DWC_DEBUGPL(DBG_PCD, "NP TxFifo Empty: %s(%d) \n", ep->ep.name, epnum); + ep_regs = core_if->dev_if->in_ep_regs[epnum]; + + len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count; + if (len > ep->dwc_ep.maxpacket) { + len = ep->dwc_ep.maxpacket; + } + dwords = (len + 3)/4; + + + /* While there is space in the queue and space in the FIFO and + * More data to tranfer, Write packets to the Tx FIFO */ + txstatus.d32 = dwc_read_reg32(&global_regs->gnptxsts); + DWC_DEBUGPL(DBG_PCDV, "b4 GNPTXSTS=0x%08x\n",txstatus.d32); + + while (txstatus.b.nptxqspcavail > 0 && + txstatus.b.nptxfspcavail > dwords && + ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len) { + /* Write the FIFO */ + dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0); + len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count; + + if (len > ep->dwc_ep.maxpacket) { + len = ep->dwc_ep.maxpacket; + } + + dwords = (len + 3)/4; + txstatus.d32 = dwc_read_reg32(&global_regs->gnptxsts); + DWC_DEBUGPL(DBG_PCDV,"GNPTXSTS=0x%08x\n",txstatus.d32); + } + + DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n", + dwc_read_reg32(&global_regs->gnptxsts)); + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.nptxfempty = 1; + dwc_write_reg32 (&global_regs->gintsts, gintsts.d32); + + return 1; +} + +/** + * This function is called when dedicated Tx FIFO Empty interrupt occurs. + * The active request is checked for the next packet to be loaded into + * apropriate Tx FIFO. + */ +static int32_t write_empty_tx_fifo(dwc_otg_pcd_t *pcd, uint32_t epnum) +{ + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); + dwc_otg_dev_if_t* dev_if = core_if->dev_if; + dwc_otg_dev_in_ep_regs_t *ep_regs; + dtxfsts_data_t txstatus = {.d32 = 0}; + dwc_otg_pcd_ep_t *ep = 0; + uint32_t len = 0; + int dwords; + + ep = get_in_ep(pcd, epnum); + + DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %s(%d) \n", ep->ep.name, epnum); + + ep_regs = core_if->dev_if->in_ep_regs[epnum]; + + len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count; + + if (len > ep->dwc_ep.maxpacket) { + len = ep->dwc_ep.maxpacket; + } + + dwords = (len + 3)/4; + + /* While there is space in the queue and space in the FIFO and + * More data to tranfer, Write packets to the Tx FIFO */ + txstatus.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts); + DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n",epnum,txstatus.d32); + + while (txstatus.b.txfspcavail > dwords && + ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len && + ep->dwc_ep.xfer_len != 0) { + /* Write the FIFO */ + dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0); + + len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count; + if (len > ep->dwc_ep.maxpacket) { + len = ep->dwc_ep.maxpacket; + } + + dwords = (len + 3)/4; + txstatus.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts); + DWC_DEBUGPL(DBG_PCDV,"dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32); + } + + DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n",epnum,dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts)); + + return 1; +} + + +/** + * This function is called when the Device is disconnected. It stops + * any active requests and informs the Gadget driver of the + * disconnect. + */ +void dwc_otg_pcd_stop(dwc_otg_pcd_t *pcd) +{ + int i, num_in_eps, num_out_eps; + dwc_otg_pcd_ep_t *ep; + + gintmsk_data_t intr_mask = {.d32 = 0}; + + num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps; + num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps; + + DWC_DEBUGPL(DBG_PCDV, "%s() \n", __func__); + /* don't disconnect drivers more than once */ + if (pcd->ep0state == EP0_DISCONNECT) { + DWC_DEBUGPL(DBG_ANY, "%s() Already Disconnected\n", __func__); + return; + } + pcd->ep0state = EP0_DISCONNECT; + + /* Reset the OTG state. */ + dwc_otg_pcd_update_otg(pcd, 1); + + /* Disable the NP Tx Fifo Empty Interrupt. */ + intr_mask.b.nptxfempty = 1; + dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, + intr_mask.d32, 0); + + /* Flush the FIFOs */ + /**@todo NGS Flush Periodic FIFOs */ + dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), 0x10); + dwc_otg_flush_rx_fifo(GET_CORE_IF(pcd)); + + /* prevent new request submissions, kill any outstanding requests */ + ep = &pcd->ep0; + dwc_otg_request_nuke(ep); + /* prevent new request submissions, kill any outstanding requests */ + for (i = 0; i < num_in_eps; i++) + { + dwc_otg_pcd_ep_t *ep = &pcd->in_ep[i]; + dwc_otg_request_nuke(ep); + } + /* prevent new request submissions, kill any outstanding requests */ + for (i = 0; i < num_out_eps; i++) + { + dwc_otg_pcd_ep_t *ep = &pcd->out_ep[i]; + dwc_otg_request_nuke(ep); + } + + /* report disconnect; the driver is already quiesced */ + if (pcd->driver && pcd->driver->disconnect) { + SPIN_UNLOCK(&pcd->lock); + pcd->driver->disconnect(&pcd->gadget); + SPIN_LOCK(&pcd->lock); + } +} + +/** + * This interrupt indicates that ... + */ +int32_t dwc_otg_pcd_handle_i2c_intr(dwc_otg_pcd_t *pcd) +{ + gintmsk_data_t intr_mask = { .d32 = 0}; + gintsts_data_t gintsts; + + DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "i2cintr"); + intr_mask.b.i2cintr = 1; + dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, + intr_mask.d32, 0); + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.i2cintr = 1; + dwc_write_reg32 (&GET_CORE_IF(pcd)->core_global_regs->gintsts, + gintsts.d32); + return 1; +} + + +/** + * This interrupt indicates that ... + */ +int32_t dwc_otg_pcd_handle_early_suspend_intr(dwc_otg_pcd_t *pcd) +{ + gintsts_data_t gintsts; +#if defined(VERBOSE) + DWC_PRINT("Early Suspend Detected\n"); +#endif + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.erlysuspend = 1; + dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, + gintsts.d32); + return 1; +} + +/** + * This function configures EPO to receive SETUP packets. + * + * @todo NGS: Update the comments from the HW FS. + * + * -# Program the following fields in the endpoint specific registers + * for Control OUT EP 0, in order to receive a setup packet + * - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back + * setup packets) + * - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back + * to back setup packets) + * - In DMA mode, DOEPDMA0 Register with a memory address to + * store any setup packets received + * + * @param core_if Programming view of DWC_otg controller. + * @param pcd Programming view of the PCD. + */ +static inline void ep0_out_start(dwc_otg_core_if_t *core_if, dwc_otg_pcd_t *pcd) +{ + dwc_otg_dev_if_t *dev_if = core_if->dev_if; + deptsiz0_data_t doeptsize0 = { .d32 = 0}; + dwc_otg_dma_desc_t* dma_desc; + depctl_data_t doepctl = { .d32 = 0 }; + +#ifdef VERBOSE + DWC_DEBUGPL(DBG_PCDV,"%s() doepctl0=%0x\n", __func__, + dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl)); +#endif + + doeptsize0.b.supcnt = 3; + doeptsize0.b.pktcnt = 1; + doeptsize0.b.xfersize = 8*3; + + + if (core_if->dma_enable) { + if (!core_if->dma_desc_enable) { + /** put here as for Hermes mode deptisz register should not be written */ + dwc_write_reg32(&dev_if->out_ep_regs[0]->doeptsiz, + doeptsize0.d32); + + /** @todo dma needs to handle multiple setup packets (up to 3) */ + dwc_write_reg32(&dev_if->out_ep_regs[0]->doepdma, + pcd->setup_pkt_dma_handle); + } else { + dev_if->setup_desc_index = (dev_if->setup_desc_index + 1) & 1; + dma_desc = dev_if->setup_desc_addr[dev_if->setup_desc_index]; + + /** DMA Descriptor Setup */ + dma_desc->status.b.bs = BS_HOST_BUSY; + dma_desc->status.b.l = 1; + dma_desc->status.b.ioc = 1; + dma_desc->status.b.bytes = pcd->ep0.dwc_ep.maxpacket; + dma_desc->buf = pcd->setup_pkt_dma_handle; + dma_desc->status.b.bs = BS_HOST_READY; + + /** DOEPDMA0 Register write */ + dwc_write_reg32(&dev_if->out_ep_regs[0]->doepdma, dev_if->dma_setup_desc_addr[dev_if->setup_desc_index]); + } + + } else { + /** put here as for Hermes mode deptisz register should not be written */ + dwc_write_reg32(&dev_if->out_ep_regs[0]->doeptsiz, + doeptsize0.d32); + } + + /** DOEPCTL0 Register write */ + doepctl.b.epena = 1; + doepctl.b.cnak = 1; + dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32); + +#ifdef VERBOSE + DWC_DEBUGPL(DBG_PCDV,"doepctl0=%0x\n", + dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl)); + DWC_DEBUGPL(DBG_PCDV,"diepctl0=%0x\n", + dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl)); +#endif +} + + +/** + * This interrupt occurs when a USB Reset is detected. When the USB + * Reset Interrupt occurs the device state is set to DEFAULT and the + * EP0 state is set to IDLE. + * -# Set the NAK bit for all OUT endpoints (DOEPCTLn.SNAK = 1) + * -# Unmask the following interrupt bits + * - DAINTMSK.INEP0 = 1 (Control 0 IN endpoint) + * - DAINTMSK.OUTEP0 = 1 (Control 0 OUT endpoint) + * - DOEPMSK.SETUP = 1 + * - DOEPMSK.XferCompl = 1 + * - DIEPMSK.XferCompl = 1 + * - DIEPMSK.TimeOut = 1 + * -# Program the following fields in the endpoint specific registers + * for Control OUT EP 0, in order to receive a setup packet + * - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back + * setup packets) + * - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back + * to back setup packets) + * - In DMA mode, DOEPDMA0 Register with a memory address to + * store any setup packets received + * At this point, all the required initialization, except for enabling + * the control 0 OUT endpoint is done, for receiving SETUP packets. + */ +int32_t dwc_otg_pcd_handle_usb_reset_intr(dwc_otg_pcd_t * pcd) +{ + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); + dwc_otg_dev_if_t *dev_if = core_if->dev_if; + depctl_data_t doepctl = { .d32 = 0}; + + daint_data_t daintmsk = { .d32 = 0}; + doepmsk_data_t doepmsk = { .d32 = 0}; + diepmsk_data_t diepmsk = { .d32 = 0}; + + dcfg_data_t dcfg = { .d32=0 }; + grstctl_t resetctl = { .d32=0 }; + dctl_data_t dctl = {.d32=0}; + int i = 0; + gintsts_data_t gintsts; + + DWC_PRINT("USB RESET\n"); +#ifdef DWC_EN_ISOC + for(i = 1;i < 16; ++i) + { + dwc_otg_pcd_ep_t *ep; + dwc_ep_t *dwc_ep; + ep = get_in_ep(pcd,i); + if(ep != 0){ + dwc_ep = &ep->dwc_ep; + dwc_ep->next_frame = 0xffffffff; + } + } +#endif /* DWC_EN_ISOC */ + + /* reset the HNP settings */ + dwc_otg_pcd_update_otg(pcd, 1); + + /* Clear the Remote Wakeup Signalling */ + dctl.b.rmtwkupsig = 1; + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl, + dctl.d32, 0); + + /* Set NAK for all OUT EPs */ + doepctl.b.snak = 1; + for (i=0; i <= dev_if->num_out_eps; i++) + { + dwc_write_reg32(&dev_if->out_ep_regs[i]->doepctl, + doepctl.d32); + } + + /* Flush the NP Tx FIFO */ + dwc_otg_flush_tx_fifo(core_if, 0x10); + /* Flush the Learning Queue */ + resetctl.b.intknqflsh = 1; + dwc_write_reg32(&core_if->core_global_regs->grstctl, resetctl.d32); + + if(core_if->multiproc_int_enable) { + daintmsk.b.inep0 = 1; + daintmsk.b.outep0 = 1; + dwc_write_reg32(&dev_if->dev_global_regs->deachintmsk, daintmsk.d32); + + doepmsk.b.setup = 1; + doepmsk.b.xfercompl = 1; + doepmsk.b.ahberr = 1; + doepmsk.b.epdisabled = 1; + + if(core_if->dma_desc_enable) { + doepmsk.b.stsphsercvd = 1; + doepmsk.b.bna = 1; + } +/* + doepmsk.b.babble = 1; + doepmsk.b.nyet = 1; + + if(core_if->dma_enable) { + doepmsk.b.nak = 1; + } +*/ + dwc_write_reg32(&dev_if->dev_global_regs->doepeachintmsk[0], doepmsk.d32); + + diepmsk.b.xfercompl = 1; + diepmsk.b.timeout = 1; + diepmsk.b.epdisabled = 1; + diepmsk.b.ahberr = 1; + diepmsk.b.intknepmis = 1; + + if(core_if->dma_desc_enable) { + diepmsk.b.bna = 1; + } +/* + if(core_if->dma_enable) { + diepmsk.b.nak = 1; + } +*/ + dwc_write_reg32(&dev_if->dev_global_regs->diepeachintmsk[0], diepmsk.d32); + } else{ + daintmsk.b.inep0 = 1; + daintmsk.b.outep0 = 1; + dwc_write_reg32(&dev_if->dev_global_regs->daintmsk, daintmsk.d32); + + doepmsk.b.setup = 1; + doepmsk.b.xfercompl = 1; + doepmsk.b.ahberr = 1; + doepmsk.b.epdisabled = 1; + + if(core_if->dma_desc_enable) { + doepmsk.b.stsphsercvd = 1; + doepmsk.b.bna = 1; + } +/* + doepmsk.b.babble = 1; + doepmsk.b.nyet = 1; + doepmsk.b.nak = 1; +*/ + dwc_write_reg32(&dev_if->dev_global_regs->doepmsk, doepmsk.d32); + + diepmsk.b.xfercompl = 1; + diepmsk.b.timeout = 1; + diepmsk.b.epdisabled = 1; + diepmsk.b.ahberr = 1; + diepmsk.b.intknepmis = 1; + + if(core_if->dma_desc_enable) { + diepmsk.b.bna = 1; + } + +// diepmsk.b.nak = 1; + + dwc_write_reg32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32); + } + + /* Reset Device Address */ + dcfg.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dcfg); + dcfg.b.devaddr = 0; + dwc_write_reg32(&dev_if->dev_global_regs->dcfg, dcfg.d32); + + /* setup EP0 to receive SETUP packets */ + ep0_out_start(core_if, pcd); + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.usbreset = 1; + dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32); + + return 1; +} + +/** + * Get the device speed from the device status register and convert it + * to USB speed constant. + * + * @param core_if Programming view of DWC_otg controller. + */ +static int get_device_speed(dwc_otg_core_if_t *core_if) +{ + dsts_data_t dsts; + enum usb_device_speed speed = USB_SPEED_UNKNOWN; + dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); + + switch (dsts.b.enumspd) { + case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: + speed = USB_SPEED_HIGH; + break; + case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: + case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ: + speed = USB_SPEED_FULL; + break; + + case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ: + speed = USB_SPEED_LOW; + break; + } + + return speed; +} + +/** + * Read the device status register and set the device speed in the + * data structure. + * Set up EP0 to receive SETUP packets by calling dwc_ep0_activate. + */ +int32_t dwc_otg_pcd_handle_enum_done_intr(dwc_otg_pcd_t *pcd) +{ + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; + gintsts_data_t gintsts; + gusbcfg_data_t gusbcfg; + dwc_otg_core_global_regs_t *global_regs = + GET_CORE_IF(pcd)->core_global_regs; + uint8_t utmi16b, utmi8b; + DWC_DEBUGPL(DBG_PCD, "SPEED ENUM\n"); + + if (GET_CORE_IF(pcd)->snpsid >= 0x4F54260A) { + utmi16b = 6; + utmi8b = 9; + } else { + utmi16b = 4; + utmi8b = 8; + } + dwc_otg_ep0_activate(GET_CORE_IF(pcd), &ep0->dwc_ep); + +#ifdef DEBUG_EP0 + print_ep0_state(pcd); +#endif + + if (pcd->ep0state == EP0_DISCONNECT) { + pcd->ep0state = EP0_IDLE; + } + else if (pcd->ep0state == EP0_STALL) { + pcd->ep0state = EP0_IDLE; + } + + pcd->ep0state = EP0_IDLE; + + ep0->stopped = 0; + + pcd->gadget.speed = get_device_speed(GET_CORE_IF(pcd)); + + /* Set USB turnaround time based on device speed and PHY interface. */ + gusbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); + if (pcd->gadget.speed == USB_SPEED_HIGH) { + if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == DWC_HWCFG2_HS_PHY_TYPE_ULPI) { + /* ULPI interface */ + gusbcfg.b.usbtrdtim = 9; + } + if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == DWC_HWCFG2_HS_PHY_TYPE_UTMI) { + /* UTMI+ interface */ + if (GET_CORE_IF(pcd)->hwcfg4.b.utmi_phy_data_width == 0) { + gusbcfg.b.usbtrdtim = utmi8b; + } + else if (GET_CORE_IF(pcd)->hwcfg4.b.utmi_phy_data_width == 1) { + gusbcfg.b.usbtrdtim = utmi16b; + } + else if (GET_CORE_IF(pcd)->core_params->phy_utmi_width == 8) { + gusbcfg.b.usbtrdtim = utmi8b; + } + else { + gusbcfg.b.usbtrdtim = utmi16b; + } + } + if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI) { + /* UTMI+ OR ULPI interface */ + if (gusbcfg.b.ulpi_utmi_sel == 1) { + /* ULPI interface */ + gusbcfg.b.usbtrdtim = 9; + } + else { + /* UTMI+ interface */ + if (GET_CORE_IF(pcd)->core_params->phy_utmi_width == 16) { + gusbcfg.b.usbtrdtim = utmi16b; + } + else { + gusbcfg.b.usbtrdtim = utmi8b; + } + } + } + } + else { + /* Full or low speed */ + gusbcfg.b.usbtrdtim = 9; + } + dwc_write_reg32(&global_regs->gusbcfg, gusbcfg.d32); + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.enumdone = 1; + dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, + gintsts.d32); + return 1; +} + +/** + * This interrupt indicates that the ISO OUT Packet was dropped due to + * Rx FIFO full or Rx Status Queue Full. If this interrupt occurs + * read all the data from the Rx FIFO. + */ +int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(dwc_otg_pcd_t *pcd) +{ + gintmsk_data_t intr_mask = { .d32 = 0}; + gintsts_data_t gintsts; + + DWC_PRINT("INTERRUPT Handler not implemented for %s\n", + "ISOC Out Dropped"); + + intr_mask.b.isooutdrop = 1; + dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, + intr_mask.d32, 0); + + /* Clear interrupt */ + + gintsts.d32 = 0; + gintsts.b.isooutdrop = 1; + dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, + gintsts.d32); + + return 1; +} + +/** + * This interrupt indicates the end of the portion of the micro-frame + * for periodic transactions. If there is a periodic transaction for + * the next frame, load the packets into the EP periodic Tx FIFO. + */ +int32_t dwc_otg_pcd_handle_end_periodic_frame_intr(dwc_otg_pcd_t *pcd) +{ + gintmsk_data_t intr_mask = { .d32 = 0}; + gintsts_data_t gintsts; + DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "EOP"); + + intr_mask.b.eopframe = 1; + dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, + intr_mask.d32, 0); + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.eopframe = 1; + dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, gintsts.d32); + + return 1; +} + +/** + * This interrupt indicates that EP of the packet on the top of the + * non-periodic Tx FIFO does not match EP of the IN Token received. + * + * The "Device IN Token Queue" Registers are read to determine the + * order the IN Tokens have been received. The non-periodic Tx FIFO + * is flushed, so it can be reloaded in the order seen in the IN Token + * Queue. + */ +int32_t dwc_otg_pcd_handle_ep_mismatch_intr(dwc_otg_core_if_t *core_if) +{ + gintsts_data_t gintsts; + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if); + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.epmismatch = 1; + dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32); + + return 1; +} + +/** + * This funcion stalls EP0. + */ +static inline void ep0_do_stall(dwc_otg_pcd_t *pcd, const int err_val) +{ + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; + struct usb_ctrlrequest *ctrl = &pcd->setup_pkt->req; + DWC_WARN("req %02x.%02x protocol STALL; err %d\n", + ctrl->bRequestType, ctrl->bRequest, err_val); + + ep0->dwc_ep.is_in = 1; + dwc_otg_ep_set_stall(pcd->otg_dev->core_if, &ep0->dwc_ep); + pcd->ep0.stopped = 1; + pcd->ep0state = EP0_IDLE; + ep0_out_start(GET_CORE_IF(pcd), pcd); +} + +/** + * This functions delegates the setup command to the gadget driver. + */ +static inline void do_gadget_setup(dwc_otg_pcd_t *pcd, + struct usb_ctrlrequest * ctrl) +{ + int ret = 0; + if (pcd->driver && pcd->driver->setup) { + SPIN_UNLOCK(&pcd->lock); + ret = pcd->driver->setup(&pcd->gadget, ctrl); + SPIN_LOCK(&pcd->lock); + if (ret < 0) { + ep0_do_stall(pcd, ret); + } + + /** @todo This is a g_file_storage gadget driver specific + * workaround: a DELAYED_STATUS result from the fsg_setup + * routine will result in the gadget queueing a EP0 IN status + * phase for a two-stage control transfer. Exactly the same as + * a SET_CONFIGURATION/SET_INTERFACE except that this is a class + * specific request. Need a generic way to know when the gadget + * driver will queue the status phase. Can we assume when we + * call the gadget driver setup() function that it will always + * queue and require the following flag? Need to look into + * this. + */ + + if (ret == 256 + 999) { + pcd->request_config = 1; + } + } +} + +/** + * This function starts the Zero-Length Packet for the IN status phase + * of a 2 stage control transfer. + */ +static inline void do_setup_in_status_phase(dwc_otg_pcd_t *pcd) +{ + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; + if (pcd->ep0state == EP0_STALL) { + return; + } + + pcd->ep0state = EP0_IN_STATUS_PHASE; + + /* Prepare for more SETUP Packets */ + DWC_DEBUGPL(DBG_PCD, "EP0 IN ZLP\n"); + ep0->dwc_ep.xfer_len = 0; + ep0->dwc_ep.xfer_count = 0; + ep0->dwc_ep.is_in = 1; + ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle; + dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep); + + /* Prepare for more SETUP Packets */ +// if(GET_CORE_IF(pcd)->dma_enable == 0) ep0_out_start(GET_CORE_IF(pcd), pcd); +} + +/** + * This function starts the Zero-Length Packet for the OUT status phase + * of a 2 stage control transfer. + */ +static inline void do_setup_out_status_phase(dwc_otg_pcd_t *pcd) +{ + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; + if (pcd->ep0state == EP0_STALL) { + DWC_DEBUGPL(DBG_PCD, "EP0 STALLED\n"); + return; + } + pcd->ep0state = EP0_OUT_STATUS_PHASE; + + DWC_DEBUGPL(DBG_PCD, "EP0 OUT ZLP\n"); + ep0->dwc_ep.xfer_len = 0; + ep0->dwc_ep.xfer_count = 0; + ep0->dwc_ep.is_in = 0; + ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle; + dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep); + + /* Prepare for more SETUP Packets */ + if(GET_CORE_IF(pcd)->dma_enable == 0) { + ep0_out_start(GET_CORE_IF(pcd), pcd); + } +} + +/** + * Clear the EP halt (STALL) and if pending requests start the + * transfer. + */ +static inline void pcd_clear_halt(dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep) +{ + if(ep->dwc_ep.stall_clear_flag == 0) + dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep); + + /* Reactive the EP */ + dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep); + if (ep->stopped) { + ep->stopped = 0; + /* If there is a request in the EP queue start it */ + + /** @todo FIXME: this causes an EP mismatch in DMA mode. + * epmismatch not yet implemented. */ + + /* + * Above fixme is solved by implmenting a tasklet to call the + * start_next_request(), outside of interrupt context at some + * time after the current time, after a clear-halt setup packet. + * Still need to implement ep mismatch in the future if a gadget + * ever uses more than one endpoint at once + */ + ep->queue_sof = 1; + tasklet_schedule (pcd->start_xfer_tasklet); + } + /* Start Control Status Phase */ + do_setup_in_status_phase(pcd); +} + +/** + * This function is called when the SET_FEATURE TEST_MODE Setup packet + * is sent from the host. The Device Control register is written with + * the Test Mode bits set to the specified Test Mode. This is done as + * a tasklet so that the "Status" phase of the control transfer + * completes before transmitting the TEST packets. + * + * @todo This has not been tested since the tasklet struct was put + * into the PCD struct! + * + */ +static void do_test_mode(unsigned long data) +{ + dctl_data_t dctl; + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)data; + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); + int test_mode = pcd->test_mode; + + +// DWC_WARN("%s() has not been tested since being rewritten!\n", __func__); + + dctl.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dctl); + switch (test_mode) { + case 1: // TEST_J + dctl.b.tstctl = 1; + break; + + case 2: // TEST_K + dctl.b.tstctl = 2; + break; + + case 3: // TEST_SE0_NAK + dctl.b.tstctl = 3; + break; + + case 4: // TEST_PACKET + dctl.b.tstctl = 4; + break; + + case 5: // TEST_FORCE_ENABLE + dctl.b.tstctl = 5; + break; + } + dwc_write_reg32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32); +} + +/** + * This function process the GET_STATUS Setup Commands. + */ +static inline void do_get_status(dwc_otg_pcd_t *pcd) +{ + struct usb_ctrlrequest ctrl = pcd->setup_pkt->req; + dwc_otg_pcd_ep_t *ep; + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; + uint16_t *status = pcd->status_buf; + +#ifdef DEBUG_EP0 + DWC_DEBUGPL(DBG_PCD, + "GET_STATUS %02x.%02x v%04x i%04x l%04x\n", + ctrl.bRequestType, ctrl.bRequest, + ctrl.wValue, ctrl.wIndex, ctrl.wLength); +#endif + + switch (ctrl.bRequestType & USB_RECIP_MASK) { + case USB_RECIP_DEVICE: + *status = 0x1; /* Self powered */ + *status |= pcd->remote_wakeup_enable << 1; + break; + + case USB_RECIP_INTERFACE: + *status = 0; + break; + + case USB_RECIP_ENDPOINT: + ep = get_ep_by_addr(pcd, ctrl.wIndex); + if (ep == 0 || ctrl.wLength > 2) { + ep0_do_stall(pcd, -EOPNOTSUPP); + return; + } + /** @todo check for EP stall */ + *status = ep->stopped; + break; + } + pcd->ep0_pending = 1; + ep0->dwc_ep.start_xfer_buff = (uint8_t *)status; + ep0->dwc_ep.xfer_buff = (uint8_t *)status; + ep0->dwc_ep.dma_addr = pcd->status_buf_dma_handle; + ep0->dwc_ep.xfer_len = 2; + ep0->dwc_ep.xfer_count = 0; + ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len; + dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep); +} +/** + * This function process the SET_FEATURE Setup Commands. + */ +static inline void do_set_feature(dwc_otg_pcd_t *pcd) +{ + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); + dwc_otg_core_global_regs_t *global_regs = + core_if->core_global_regs; + struct usb_ctrlrequest ctrl = pcd->setup_pkt->req; + dwc_otg_pcd_ep_t *ep = 0; + int32_t otg_cap_param = core_if->core_params->otg_cap; + gotgctl_data_t gotgctl = { .d32 = 0 }; + + DWC_DEBUGPL(DBG_PCD, "SET_FEATURE:%02x.%02x v%04x i%04x l%04x\n", + ctrl.bRequestType, ctrl.bRequest, + ctrl.wValue, ctrl.wIndex, ctrl.wLength); + DWC_DEBUGPL(DBG_PCD,"otg_cap=%d\n", otg_cap_param); + + + switch (ctrl.bRequestType & USB_RECIP_MASK) { + case USB_RECIP_DEVICE: + switch (ctrl.wValue) { + case USB_DEVICE_REMOTE_WAKEUP: + pcd->remote_wakeup_enable = 1; + break; + + case USB_DEVICE_TEST_MODE: + /* Setup the Test Mode tasklet to do the Test + * Packet generation after the SETUP Status + * phase has completed. */ + + /** @todo This has not been tested since the + * tasklet struct was put into the PCD + * struct! */ + pcd->test_mode_tasklet.next = 0; + pcd->test_mode_tasklet.state = 0; + atomic_set(&pcd->test_mode_tasklet.count, 0); + pcd->test_mode_tasklet.func = do_test_mode; + pcd->test_mode_tasklet.data = (unsigned long)pcd; + pcd->test_mode = ctrl.wIndex >> 8; + tasklet_schedule(&pcd->test_mode_tasklet); + break; + + case USB_DEVICE_B_HNP_ENABLE: + DWC_DEBUGPL(DBG_PCDV, "SET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n"); + + /* dev may initiate HNP */ + if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) { + pcd->b_hnp_enable = 1; + dwc_otg_pcd_update_otg(pcd, 0); + DWC_DEBUGPL(DBG_PCD, "Request B HNP\n"); + /**@todo Is the gotgctl.devhnpen cleared + * by a USB Reset? */ + gotgctl.b.devhnpen = 1; + gotgctl.b.hnpreq = 1; + dwc_write_reg32(&global_regs->gotgctl, gotgctl.d32); + } + else { + ep0_do_stall(pcd, -EOPNOTSUPP); + } + break; + + case USB_DEVICE_A_HNP_SUPPORT: + /* RH port supports HNP */ + DWC_DEBUGPL(DBG_PCDV, "SET_FEATURE: USB_DEVICE_A_HNP_SUPPORT\n"); + if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) { + pcd->a_hnp_support = 1; + dwc_otg_pcd_update_otg(pcd, 0); + } + else { + ep0_do_stall(pcd, -EOPNOTSUPP); + } + break; + + case USB_DEVICE_A_ALT_HNP_SUPPORT: + /* other RH port does */ + DWC_DEBUGPL(DBG_PCDV, "SET_FEATURE: USB_DEVICE_A_ALT_HNP_SUPPORT\n"); + if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) { + pcd->a_alt_hnp_support = 1; + dwc_otg_pcd_update_otg(pcd, 0); + } + else { + ep0_do_stall(pcd, -EOPNOTSUPP); + } + break; + } + do_setup_in_status_phase(pcd); + break; + + case USB_RECIP_INTERFACE: + do_gadget_setup(pcd, &ctrl); + break; + + case USB_RECIP_ENDPOINT: + if (ctrl.wValue == USB_ENDPOINT_HALT) { + ep = get_ep_by_addr(pcd, ctrl.wIndex); + if (ep == 0) { + ep0_do_stall(pcd, -EOPNOTSUPP); + return; + } + ep->stopped = 1; + dwc_otg_ep_set_stall(core_if, &ep->dwc_ep); + } + do_setup_in_status_phase(pcd); + break; + } +} + +/** + * This function process the CLEAR_FEATURE Setup Commands. + */ +static inline void do_clear_feature(dwc_otg_pcd_t *pcd) +{ + struct usb_ctrlrequest ctrl = pcd->setup_pkt->req; + dwc_otg_pcd_ep_t *ep = 0; + + DWC_DEBUGPL(DBG_PCD, + "CLEAR_FEATURE:%02x.%02x v%04x i%04x l%04x\n", + ctrl.bRequestType, ctrl.bRequest, + ctrl.wValue, ctrl.wIndex, ctrl.wLength); + + switch (ctrl.bRequestType & USB_RECIP_MASK) { + case USB_RECIP_DEVICE: + switch (ctrl.wValue) { + case USB_DEVICE_REMOTE_WAKEUP: + pcd->remote_wakeup_enable = 0; + break; + + case USB_DEVICE_TEST_MODE: + /** @todo Add CLEAR_FEATURE for TEST modes. */ + break; + } + do_setup_in_status_phase(pcd); + break; + + case USB_RECIP_ENDPOINT: + ep = get_ep_by_addr(pcd, ctrl.wIndex); + if (ep == 0) { + ep0_do_stall(pcd, -EOPNOTSUPP); + return; + } + + pcd_clear_halt(pcd, ep); + + break; + } +} + +/** + * This function process the SET_ADDRESS Setup Commands. + */ +static inline void do_set_address(dwc_otg_pcd_t *pcd) +{ + dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if; + struct usb_ctrlrequest ctrl = pcd->setup_pkt->req; + + if (ctrl.bRequestType == USB_RECIP_DEVICE) { + dcfg_data_t dcfg = {.d32=0}; + +#ifdef DEBUG_EP0 +// DWC_DEBUGPL(DBG_PCDV, "SET_ADDRESS:%d\n", ctrl.wValue); +#endif + dcfg.b.devaddr = ctrl.wValue; + dwc_modify_reg32(&dev_if->dev_global_regs->dcfg, 0, dcfg.d32); + do_setup_in_status_phase(pcd); + } +} + +/** + * This function processes SETUP commands. In Linux, the USB Command + * processing is done in two places - the first being the PCD and the + * second in the Gadget Driver (for example, the File-Backed Storage + * Gadget Driver). + * + *
Parameter NameMeaning
otg_capSpecifies the OTG capabilities. The driver will automatically detect the + value for this parameter if none is specified. + - 0: HNP and SRP capable (default, if available) + - 1: SRP Only capable + - 2: No HNP/SRP capable +
dma_enableSpecifies whether to use slave or DMA mode for accessing the data FIFOs. + The driver will automatically detect the value for this parameter if none is + specified. + - 0: Slave + - 1: DMA (default, if available) +
dma_burst_sizeThe DMA Burst size (applicable only for External DMA Mode). + - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32) +
speedSpecifies the maximum speed of operation in host and device mode. The + actual speed depends on the speed of the attached device and the value of + phy_type. + - 0: High Speed (default) + - 1: Full Speed +
host_support_fs_ls_low_powerSpecifies whether low power mode is supported when attached to a Full + Speed or Low Speed device in host mode. + - 0: Don't support low power mode (default) + - 1: Support low power mode +
host_ls_low_power_phy_clkSpecifies the PHY clock rate in low power mode when connected to a Low + Speed device in host mode. This parameter is applicable only if + HOST_SUPPORT_FS_LS_LOW_POWER is enabled. + - 0: 48 MHz (default) + - 1: 6 MHz +
enable_dynamic_fifo Specifies whether FIFOs may be resized by the driver software. + - 0: Use cC FIFO size parameters + - 1: Allow dynamic FIFO sizing (default) +
data_fifo_sizeTotal number of 4-byte words in the data FIFO memory. This memory + includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs. + - Values: 32 to 32768 (default 8192) + + Note: The total FIFO memory depth in the FPGA configuration is 8192. +
dev_rx_fifo_sizeNumber of 4-byte words in the Rx FIFO in device mode when dynamic + FIFO sizing is enabled. + - Values: 16 to 32768 (default 1064) +
dev_nperio_tx_fifo_sizeNumber of 4-byte words in the non-periodic Tx FIFO in device mode when + dynamic FIFO sizing is enabled. + - Values: 16 to 32768 (default 1024) +
dev_perio_tx_fifo_size_n (n = 1 to 15)Number of 4-byte words in each of the periodic Tx FIFOs in device mode + when dynamic FIFO sizing is enabled. + - Values: 4 to 768 (default 256) +
host_rx_fifo_sizeNumber of 4-byte words in the Rx FIFO in host mode when dynamic FIFO + sizing is enabled. + - Values: 16 to 32768 (default 1024) +
host_nperio_tx_fifo_sizeNumber of 4-byte words in the non-periodic Tx FIFO in host mode when + dynamic FIFO sizing is enabled in the core. + - Values: 16 to 32768 (default 1024) +
host_perio_tx_fifo_sizeNumber of 4-byte words in the host periodic Tx FIFO when dynamic FIFO + sizing is enabled. + - Values: 16 to 32768 (default 1024) +
max_transfer_sizeThe maximum transfer size supported in bytes. + - Values: 2047 to 65,535 (default 65,535) +
max_packet_countThe maximum number of packets in a transfer. + - Values: 15 to 511 (default 511) +
host_channelsThe number of host channel registers to use. + - Values: 1 to 16 (default 12) + + Note: The FPGA configuration supports a maximum of 12 host channels. +
dev_endpointsThe number of endpoints in addition to EP0 available for device mode + operations. + - Values: 1 to 15 (default 6 IN and OUT) + + Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in + addition to EP0. +
phy_typeSpecifies the type of PHY interface to use. By default, the driver will + automatically detect the phy_type. + - 0: Full Speed + - 1: UTMI+ (default, if available) + - 2: ULPI +
phy_utmi_widthSpecifies the UTMI+ Data Width. This parameter is applicable for a + phy_type of UTMI+. Also, this parameter is applicable only if the + OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the + core has been configured to work at either data path width. + - Values: 8 or 16 bits (default 16) +
phy_ulpi_ddrSpecifies whether the ULPI operates at double or single data rate. This + parameter is only applicable if phy_type is ULPI. + - 0: single data rate ULPI interface with 8 bit wide data bus (default) + - 1: double data rate ULPI interface with 4 bit wide data bus +
i2c_enableSpecifies whether to use the I2C interface for full speed PHY. This + parameter is only applicable if PHY_TYPE is FS. + - 0: Disabled (default) + - 1: Enabled +
otg_en_multiple_tx_fifoSpecifies whether dedicatedto tx fifos are enabled for non periodic IN EPs. + The driver will automatically detect the value for this parameter if none is + specified. + - 0: Disabled + - 1: Enabled (default, if available) +
dev_tx_fifo_size_n (n = 1 to 15)Number of 4-byte words in each of the Tx FIFOs in device mode + when dynamic FIFO sizing is enabled. + - Values: 4 to 768 (default 256) +
+ * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
Command Driver Description
GET_STATUS PCD Command is processed as + * defined in chapter 9 of the USB 2.0 Specification chapter 9 + *
CLEAR_FEATURE PCD The Device and Endpoint + * requests are the ENDPOINT_HALT feature is procesed, all others the + * interface requests are ignored.
SET_FEATURE PCD The Device and Endpoint + * requests are processed by the PCD. Interface requests are passed + * to the Gadget Driver.
SET_ADDRESS PCD Program the DCFG reg, + * with device address received
GET_DESCRIPTOR Gadget Driver Return the + * requested descriptor
SET_DESCRIPTOR Gadget Driver Optional - + * not implemented by any of the existing Gadget Drivers.
SET_CONFIGURATION Gadget Driver Disable + * all EPs and enable EPs for new configuration.
GET_CONFIGURATION Gadget Driver Return + * the current configuration
SET_INTERFACE Gadget Driver Disable all + * EPs and enable EPs for new configuration.
GET_INTERFACE Gadget Driver Return the + * current interface.
SYNC_FRAME PCD Display debug + * message.
+ * + * When the SETUP Phase Done interrupt occurs, the PCD SETUP commands are + * processed by pcd_setup. Calling the Function Driver's setup function from + * pcd_setup processes the gadget SETUP commands. + */ +static inline void pcd_setup(dwc_otg_pcd_t *pcd) +{ + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); + dwc_otg_dev_if_t *dev_if = core_if->dev_if; + struct usb_ctrlrequest ctrl = pcd->setup_pkt->req; + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; + + deptsiz0_data_t doeptsize0 = { .d32 = 0}; + +#ifdef DEBUG_EP0 + DWC_DEBUGPL(DBG_PCD, "SETUP %02x.%02x v%04x i%04x l%04x\n", + ctrl.bRequestType, ctrl.bRequest, + ctrl.wValue, ctrl.wIndex, ctrl.wLength); +#endif + + doeptsize0.d32 = dwc_read_reg32(&dev_if->out_ep_regs[0]->doeptsiz); + + /** @todo handle > 1 setup packet , assert error for now */ + + if (core_if->dma_enable && core_if->dma_desc_enable == 0 && (doeptsize0.b.supcnt < 2)) { + DWC_ERROR ("\n\n----------- CANNOT handle > 1 setup packet in DMA mode\n\n"); + } + + /* Clean up the request queue */ + dwc_otg_request_nuke(ep0); + ep0->stopped = 0; + + if (ctrl.bRequestType & USB_DIR_IN) { + ep0->dwc_ep.is_in = 1; + pcd->ep0state = EP0_IN_DATA_PHASE; + } + else { + ep0->dwc_ep.is_in = 0; + pcd->ep0state = EP0_OUT_DATA_PHASE; + } + + if(ctrl.wLength == 0) { + ep0->dwc_ep.is_in = 1; + pcd->ep0state = EP0_IN_STATUS_PHASE; + } + + if ((ctrl.bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD) { + /* handle non-standard (class/vendor) requests in the gadget driver */ + do_gadget_setup(pcd, &ctrl); + return; + } + + /** @todo NGS: Handle bad setup packet? */ + +/////////////////////////////////////////// +//// --- Standard Request handling --- //// + + switch (ctrl.bRequest) { + case USB_REQ_GET_STATUS: + do_get_status(pcd); + break; + + case USB_REQ_CLEAR_FEATURE: + do_clear_feature(pcd); + break; + + case USB_REQ_SET_FEATURE: + do_set_feature(pcd); + break; + + case USB_REQ_SET_ADDRESS: + do_set_address(pcd); + break; + + case USB_REQ_SET_INTERFACE: + case USB_REQ_SET_CONFIGURATION: +// _pcd->request_config = 1; /* Configuration changed */ + do_gadget_setup(pcd, &ctrl); + break; + + case USB_REQ_SYNCH_FRAME: + do_gadget_setup(pcd, &ctrl); + break; + + default: + /* Call the Gadget Driver's setup functions */ + do_gadget_setup(pcd, &ctrl); + break; + } +} + +/** + * This function completes the ep0 control transfer. + */ +static int32_t ep0_complete_request(dwc_otg_pcd_ep_t *ep) +{ + dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd); + dwc_otg_dev_if_t *dev_if = core_if->dev_if; + dwc_otg_dev_in_ep_regs_t *in_ep_regs = + dev_if->in_ep_regs[ep->dwc_ep.num]; +#ifdef DEBUG_EP0 + dwc_otg_dev_out_ep_regs_t *out_ep_regs = + dev_if->out_ep_regs[ep->dwc_ep.num]; +#endif + deptsiz0_data_t deptsiz; + desc_sts_data_t desc_sts; + dwc_otg_pcd_request_t *req; + int is_last = 0; + dwc_otg_pcd_t *pcd = ep->pcd; + + //DWC_DEBUGPL(DBG_PCDV, "%s() %s\n", __func__, _ep->ep.name); + + if (pcd->ep0_pending && list_empty(&ep->queue)) { + if (ep->dwc_ep.is_in) { +#ifdef DEBUG_EP0 + DWC_DEBUGPL(DBG_PCDV, "Do setup OUT status phase\n"); +#endif + do_setup_out_status_phase(pcd); + } + else { +#ifdef DEBUG_EP0 + DWC_DEBUGPL(DBG_PCDV, "Do setup IN status phase\n"); +#endif + do_setup_in_status_phase(pcd); + } + pcd->ep0_pending = 0; + return 1; + } + + if (list_empty(&ep->queue)) { + return 0; + } + req = list_entry(ep->queue.next, dwc_otg_pcd_request_t, queue); + + + if (pcd->ep0state == EP0_OUT_STATUS_PHASE || pcd->ep0state == EP0_IN_STATUS_PHASE) { + is_last = 1; + } + else if (ep->dwc_ep.is_in) { + deptsiz.d32 = dwc_read_reg32(&in_ep_regs->dieptsiz); + if(core_if->dma_desc_enable != 0) + desc_sts.d32 = readl(dev_if->in_desc_addr); +#ifdef DEBUG_EP0 + DWC_DEBUGPL(DBG_PCDV, "%s len=%d xfersize=%d pktcnt=%d\n", + ep->ep.name, ep->dwc_ep.xfer_len, + deptsiz.b.xfersize, deptsiz.b.pktcnt); +#endif + + if (((core_if->dma_desc_enable == 0) && (deptsiz.b.xfersize == 0)) || + ((core_if->dma_desc_enable != 0) && (desc_sts.b.bytes == 0))) { + req->req.actual = ep->dwc_ep.xfer_count; + /* Is a Zero Len Packet needed? */ + if (req->req.zero) { +#ifdef DEBUG_EP0 + DWC_DEBUGPL(DBG_PCD, "Setup Rx ZLP\n"); +#endif + req->req.zero = 0; + } + do_setup_out_status_phase(pcd); + } + } + else { + /* ep0-OUT */ +#ifdef DEBUG_EP0 + deptsiz.d32 = dwc_read_reg32(&out_ep_regs->doeptsiz); + DWC_DEBUGPL(DBG_PCDV, "%s len=%d xsize=%d pktcnt=%d\n", + ep->ep.name, ep->dwc_ep.xfer_len, + deptsiz.b.xfersize, + deptsiz.b.pktcnt); +#endif + req->req.actual = ep->dwc_ep.xfer_count; + /* Is a Zero Len Packet needed? */ + if (req->req.zero) { +#ifdef DEBUG_EP0 + DWC_DEBUGPL(DBG_PCDV, "Setup Tx ZLP\n"); +#endif + req->req.zero = 0; + } + if(core_if->dma_desc_enable == 0) + do_setup_in_status_phase(pcd); + } + + /* Complete the request */ + if (is_last) { + dwc_otg_request_done(ep, req, 0); + ep->dwc_ep.start_xfer_buff = 0; + ep->dwc_ep.xfer_buff = 0; + ep->dwc_ep.xfer_len = 0; + return 1; + } + return 0; +} + +/** + * This function completes the request for the EP. If there are + * additional requests for the EP in the queue they will be started. + */ +static void complete_ep(dwc_otg_pcd_ep_t *ep) +{ + dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd); + dwc_otg_dev_if_t *dev_if = core_if->dev_if; + dwc_otg_dev_in_ep_regs_t *in_ep_regs = + dev_if->in_ep_regs[ep->dwc_ep.num]; + deptsiz_data_t deptsiz; + desc_sts_data_t desc_sts; + dwc_otg_pcd_request_t *req = 0; + dwc_otg_dma_desc_t* dma_desc; + uint32_t byte_count = 0; + int is_last = 0; + int i; + + DWC_DEBUGPL(DBG_PCDV,"%s() %s-%s\n", __func__, ep->ep.name, + (ep->dwc_ep.is_in?"IN":"OUT")); + + /* Get any pending requests */ + if (!list_empty(&ep->queue)) { + req = list_entry(ep->queue.next, dwc_otg_pcd_request_t, + queue); + if (!req) { + printk("complete_ep 0x%p, req = NULL!\n", ep); + return; + } + } + else { + printk("complete_ep 0x%p, ep->queue empty!\n", ep); + return; + } + DWC_DEBUGPL(DBG_PCD, "Requests %d\n", ep->pcd->request_pending); + + if (ep->dwc_ep.is_in) { + deptsiz.d32 = dwc_read_reg32(&in_ep_regs->dieptsiz); + + if (core_if->dma_enable) { + if(core_if->dma_desc_enable == 0) { + if (deptsiz.b.xfersize == 0 && deptsiz.b.pktcnt == 0) { + byte_count = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count; + + ep->dwc_ep.xfer_buff += byte_count; + ep->dwc_ep.dma_addr += byte_count; + ep->dwc_ep.xfer_count += byte_count; + + DWC_DEBUGPL(DBG_PCDV, "%s len=%d xfersize=%d pktcnt=%d\n", + ep->ep.name, ep->dwc_ep.xfer_len, + deptsiz.b.xfersize, deptsiz.b.pktcnt); + + + if(ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) { + dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep); + } else if(ep->dwc_ep.sent_zlp) { + /* + * This fragment of code should initiate 0 + * length trasfer in case if it is queued + * a trasfer with size divisible to EPs max + * packet size and with usb_request zero field + * is set, which means that after data is transfered, + * it is also should be transfered + * a 0 length packet at the end. For Slave and + * Buffer DMA modes in this case SW has + * to initiate 2 transfers one with transfer size, + * and the second with 0 size. For Desriptor + * DMA mode SW is able to initiate a transfer, + * which will handle all the packets including + * the last 0 legth. + */ + ep->dwc_ep.sent_zlp = 0; + dwc_otg_ep_start_zl_transfer(core_if, &ep->dwc_ep); + } else { + is_last = 1; + } + } else { + DWC_WARN("Incomplete transfer (%s-%s [siz=%d pkt=%d])\n", + ep->ep.name, (ep->dwc_ep.is_in?"IN":"OUT"), + deptsiz.b.xfersize, deptsiz.b.pktcnt); + } + } else { + dma_desc = ep->dwc_ep.desc_addr; + byte_count = 0; + ep->dwc_ep.sent_zlp = 0; + + for(i = 0; i < ep->dwc_ep.desc_cnt; ++i) { + desc_sts.d32 = readl(dma_desc); + byte_count += desc_sts.b.bytes; + dma_desc++; + } + + if(byte_count == 0) { + ep->dwc_ep.xfer_count = ep->dwc_ep.total_len; + is_last = 1; + } else { + DWC_WARN("Incomplete transfer\n"); + } + } + } else { + if (deptsiz.b.xfersize == 0 && deptsiz.b.pktcnt == 0) { + /* Check if the whole transfer was completed, + * if no, setup transfer for next portion of data + */ + DWC_DEBUGPL(DBG_PCDV, "%s len=%d xfersize=%d pktcnt=%d\n", + ep->ep.name, ep->dwc_ep.xfer_len, + deptsiz.b.xfersize, deptsiz.b.pktcnt); + if(ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) { + dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep); + } else if(ep->dwc_ep.sent_zlp) { + /* + * This fragment of code should initiate 0 + * length trasfer in case if it is queued + * a trasfer with size divisible to EPs max + * packet size and with usb_request zero field + * is set, which means that after data is transfered, + * it is also should be transfered + * a 0 length packet at the end. For Slave and + * Buffer DMA modes in this case SW has + * to initiate 2 transfers one with transfer size, + * and the second with 0 size. For Desriptor + * DMA mode SW is able to initiate a transfer, + * which will handle all the packets including + * the last 0 legth. + */ + ep->dwc_ep.sent_zlp = 0; + dwc_otg_ep_start_zl_transfer(core_if, &ep->dwc_ep); + } else { + is_last = 1; + } + } + else { + DWC_WARN("Incomplete transfer (%s-%s [siz=%d pkt=%d])\n", + ep->ep.name, (ep->dwc_ep.is_in?"IN":"OUT"), + deptsiz.b.xfersize, deptsiz.b.pktcnt); + } + } + } else { + dwc_otg_dev_out_ep_regs_t *out_ep_regs = + dev_if->out_ep_regs[ep->dwc_ep.num]; + desc_sts.d32 = 0; + if(core_if->dma_enable) { + if(core_if->dma_desc_enable) { + dma_desc = ep->dwc_ep.desc_addr; + byte_count = 0; + ep->dwc_ep.sent_zlp = 0; + for(i = 0; i < ep->dwc_ep.desc_cnt; ++i) { + desc_sts.d32 = readl(dma_desc); + byte_count += desc_sts.b.bytes; + dma_desc++; + } + + ep->dwc_ep.xfer_count = ep->dwc_ep.total_len + - byte_count + ((4 - (ep->dwc_ep.total_len & 0x3)) & 0x3); + is_last = 1; + } else { + deptsiz.d32 = 0; + deptsiz.d32 = dwc_read_reg32(&out_ep_regs->doeptsiz); + + byte_count = (ep->dwc_ep.xfer_len - + ep->dwc_ep.xfer_count - deptsiz.b.xfersize); + ep->dwc_ep.xfer_buff += byte_count; + ep->dwc_ep.dma_addr += byte_count; + ep->dwc_ep.xfer_count += byte_count; + + /* Check if the whole transfer was completed, + * if no, setup transfer for next portion of data + */ + if(ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) { + dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep); + } + else if(ep->dwc_ep.sent_zlp) { + /* + * This fragment of code should initiate 0 + * length trasfer in case if it is queued + * a trasfer with size divisible to EPs max + * packet size and with usb_request zero field + * is set, which means that after data is transfered, + * it is also should be transfered + * a 0 length packet at the end. For Slave and + * Buffer DMA modes in this case SW has + * to initiate 2 transfers one with transfer size, + * and the second with 0 size. For Desriptor + * DMA mode SW is able to initiate a transfer, + * which will handle all the packets including + * the last 0 legth. + */ + ep->dwc_ep.sent_zlp = 0; + dwc_otg_ep_start_zl_transfer(core_if, &ep->dwc_ep); + } else { + is_last = 1; + } + } + } else { + /* Check if the whole transfer was completed, + * if no, setup transfer for next portion of data + */ + if(ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) { + dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep); + } + else if(ep->dwc_ep.sent_zlp) { + /* + * This fragment of code should initiate 0 + * length trasfer in case if it is queued + * a trasfer with size divisible to EPs max + * packet size and with usb_request zero field + * is set, which means that after data is transfered, + * it is also should be transfered + * a 0 length packet at the end. For Slave and + * Buffer DMA modes in this case SW has + * to initiate 2 transfers one with transfer size, + * and the second with 0 size. For Desriptor + * DMA mode SW is able to initiate a transfer, + * which will handle all the packets including + * the last 0 legth. + */ + ep->dwc_ep.sent_zlp = 0; + dwc_otg_ep_start_zl_transfer(core_if, &ep->dwc_ep); + } else { + is_last = 1; + } + } + +#ifdef DEBUG + + DWC_DEBUGPL(DBG_PCDV, "addr %p, %s len=%d cnt=%d xsize=%d pktcnt=%d\n", + &out_ep_regs->doeptsiz, ep->ep.name, ep->dwc_ep.xfer_len, + ep->dwc_ep.xfer_count, + deptsiz.b.xfersize, + deptsiz.b.pktcnt); +#endif + } + + /* Complete the request */ + if (is_last) { + req->req.actual = ep->dwc_ep.xfer_count; + + dwc_otg_request_done(ep, req, 0); + + ep->dwc_ep.start_xfer_buff = 0; + ep->dwc_ep.xfer_buff = 0; + ep->dwc_ep.xfer_len = 0; + + /* If there is a request in the queue start it.*/ + start_next_request(ep); + } +} + + +#ifdef DWC_EN_ISOC + +/** + * This function BNA interrupt for Isochronous EPs + * + */ +static void dwc_otg_pcd_handle_iso_bna(dwc_otg_pcd_ep_t *ep) +{ + dwc_ep_t *dwc_ep = &ep->dwc_ep; + volatile uint32_t *addr; + depctl_data_t depctl = {.d32 = 0}; + dwc_otg_pcd_t *pcd = ep->pcd; + dwc_otg_dma_desc_t *dma_desc; + int i; + + dma_desc = dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * (dwc_ep->proc_buf_num); + + if(dwc_ep->is_in) { + desc_sts_data_t sts = {.d32 = 0}; + for(i = 0;i < dwc_ep->desc_cnt; ++i, ++dma_desc) + { + sts.d32 = readl(&dma_desc->status); + sts.b_iso_in.bs = BS_HOST_READY; + writel(sts.d32,&dma_desc->status); + } + } + else { + desc_sts_data_t sts = {.d32 = 0}; + for(i = 0;i < dwc_ep->desc_cnt; ++i, ++dma_desc) + { + sts.d32 = readl(&dma_desc->status); + sts.b_iso_out.bs = BS_HOST_READY; + writel(sts.d32,&dma_desc->status); + } + } + + if(dwc_ep->is_in == 0){ + addr = &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->num]->doepctl; + } + else{ + addr = &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl; + } + depctl.b.epena = 1; + dwc_modify_reg32(addr,depctl.d32,depctl.d32); +} + +/** + * This function sets latest iso packet information(non-PTI mode) + * + * @param core_if Programming view of DWC_otg controller. + * @param ep The EP to start the transfer on. + * + */ +void set_current_pkt_info(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) +{ + deptsiz_data_t deptsiz = { .d32 = 0 }; + dma_addr_t dma_addr; + uint32_t offset; + + if(ep->proc_buf_num) + dma_addr = ep->dma_addr1; + else + dma_addr = ep->dma_addr0; + + + if(ep->is_in) { + deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz); + offset = ep->data_per_frame; + } else { + deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doeptsiz); + offset = ep->data_per_frame + (0x4 & (0x4 - (ep->data_per_frame & 0x3))); + } + + if(!deptsiz.b.xfersize) { + ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame; + ep->pkt_info[ep->cur_pkt].offset = ep->cur_pkt_dma_addr - dma_addr; + ep->pkt_info[ep->cur_pkt].status = 0; + } else { + ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame; + ep->pkt_info[ep->cur_pkt].offset = ep->cur_pkt_dma_addr - dma_addr; + ep->pkt_info[ep->cur_pkt].status = -ENODATA; + } + ep->cur_pkt_addr += offset; + ep->cur_pkt_dma_addr += offset; + ep->cur_pkt++; +} + +/** + * This function sets latest iso packet information(DDMA mode) + * + * @param core_if Programming view of DWC_otg controller. + * @param dwc_ep The EP to start the transfer on. + * + */ +static void set_ddma_iso_pkts_info(dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep) +{ + dwc_otg_dma_desc_t* dma_desc; + desc_sts_data_t sts = {.d32 = 0}; + iso_pkt_info_t *iso_packet; + uint32_t data_per_desc; + uint32_t offset; + int i, j; + + iso_packet = dwc_ep->pkt_info; + + /** Reinit closed DMA Descriptors*/ + /** ISO OUT EP */ + if(dwc_ep->is_in == 0) { + dma_desc = dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * dwc_ep->proc_buf_num; + offset = 0; + + for(i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; i+= dwc_ep->pkt_per_frm) + { + for(j = 0; j < dwc_ep->pkt_per_frm; ++j) + { + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ? + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket; + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0; + + sts.d32 = readl(&dma_desc->status); + + /* Write status in iso_packet_decsriptor */ + iso_packet->status = sts.b_iso_out.rxsts + (sts.b_iso_out.bs^BS_DMA_DONE); + if(iso_packet->status) { + iso_packet->status = -ENODATA; + } + + /* Received data length */ + if(!sts.b_iso_out.rxbytes){ + iso_packet->length = data_per_desc - sts.b_iso_out.rxbytes; + } else { + iso_packet->length = data_per_desc - sts.b_iso_out.rxbytes + + (4 - dwc_ep->data_per_frame % 4); + } + + iso_packet->offset = offset; + + offset += data_per_desc; + dma_desc ++; + iso_packet ++; + } + } + + for(j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) + { + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ? + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket; + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0; + + sts.d32 = readl(&dma_desc->status); + + /* Write status in iso_packet_decsriptor */ + iso_packet->status = sts.b_iso_out.rxsts + (sts.b_iso_out.bs^BS_DMA_DONE); + if(iso_packet->status) { + iso_packet->status = -ENODATA; + } + + /* Received data length */ + iso_packet->length = dwc_ep->data_per_frame - sts.b_iso_out.rxbytes; + + iso_packet->offset = offset; + + offset += data_per_desc; + iso_packet++; + dma_desc++; + } + + sts.d32 = readl(&dma_desc->status); + + /* Write status in iso_packet_decsriptor */ + iso_packet->status = sts.b_iso_out.rxsts + (sts.b_iso_out.bs^BS_DMA_DONE); + if(iso_packet->status) { + iso_packet->status = -ENODATA; + } + /* Received data length */ + if(!sts.b_iso_out.rxbytes){ + iso_packet->length = dwc_ep->data_per_frame - sts.b_iso_out.rxbytes; + } else { + iso_packet->length = dwc_ep->data_per_frame - sts.b_iso_out.rxbytes + + (4 - dwc_ep->data_per_frame % 4); + } + + iso_packet->offset = offset; + } + else /** ISO IN EP */ + { + dma_desc = dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * dwc_ep->proc_buf_num; + + for(i = 0; i < dwc_ep->desc_cnt - 1; i++) + { + sts.d32 = readl(&dma_desc->status); + + /* Write status in iso packet descriptor */ + iso_packet->status = sts.b_iso_in.txsts + (sts.b_iso_in.bs^BS_DMA_DONE); + if(iso_packet->status != 0) { + iso_packet->status = -ENODATA; + + } + /* Bytes has been transfered */ + iso_packet->length = dwc_ep->data_per_frame - sts.b_iso_in.txbytes; + + dma_desc ++; + iso_packet++; + } + + sts.d32 = readl(&dma_desc->status); + while(sts.b_iso_in.bs == BS_DMA_BUSY) { + sts.d32 = readl(&dma_desc->status); + } + + /* Write status in iso packet descriptor ??? do be done with ERROR codes*/ + iso_packet->status = sts.b_iso_in.txsts + (sts.b_iso_in.bs^BS_DMA_DONE); + if(iso_packet->status != 0) { + iso_packet->status = -ENODATA; + } + + /* Bytes has been transfered */ + iso_packet->length = dwc_ep->data_per_frame - sts.b_iso_in.txbytes; + } +} + +/** + * This function reinitialize DMA Descriptors for Isochronous transfer + * + * @param core_if Programming view of DWC_otg controller. + * @param dwc_ep The EP to start the transfer on. + * + */ +static void reinit_ddma_iso_xfer(dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep) +{ + int i, j; + dwc_otg_dma_desc_t* dma_desc; + dma_addr_t dma_ad; + volatile uint32_t *addr; + desc_sts_data_t sts = { .d32 =0 }; + uint32_t data_per_desc; + + if(dwc_ep->is_in == 0) { + addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl; + } + else { + addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl; + } + + + if(dwc_ep->proc_buf_num == 0) { + /** Buffer 0 descriptors setup */ + dma_ad = dwc_ep->dma_addr0; + } + else { + /** Buffer 1 descriptors setup */ + dma_ad = dwc_ep->dma_addr1; + } + + + /** Reinit closed DMA Descriptors*/ + /** ISO OUT EP */ + if(dwc_ep->is_in == 0) { + dma_desc = dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * dwc_ep->proc_buf_num; + + sts.b_iso_out.bs = BS_HOST_READY; + sts.b_iso_out.rxsts = 0; + sts.b_iso_out.l = 0; + sts.b_iso_out.sp = 0; + sts.b_iso_out.ioc = 0; + sts.b_iso_out.pid = 0; + sts.b_iso_out.framenum = 0; + + for(i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; i+= dwc_ep->pkt_per_frm) + { + for(j = 0; j < dwc_ep->pkt_per_frm; ++j) + { + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ? + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket; + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0; + sts.b_iso_out.rxbytes = data_per_desc; + writel((uint32_t)dma_ad, &dma_desc->buf); + writel(sts.d32, &dma_desc->status); + + (uint32_t)dma_ad += data_per_desc; + dma_desc ++; + } + } + + for(j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) + { + + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ? + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket; + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0; + sts.b_iso_out.rxbytes = data_per_desc; + + writel((uint32_t)dma_ad, &dma_desc->buf); + writel(sts.d32, &dma_desc->status); + + dma_desc++; + (uint32_t)dma_ad += data_per_desc; + } + + sts.b_iso_out.ioc = 1; + sts.b_iso_out.l = dwc_ep->proc_buf_num; + + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ? + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket; + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0; + sts.b_iso_out.rxbytes = data_per_desc; + + writel((uint32_t)dma_ad, &dma_desc->buf); + writel(sts.d32, &dma_desc->status); + } + else /** ISO IN EP */ + { + dma_desc = dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * dwc_ep->proc_buf_num; + + sts.b_iso_in.bs = BS_HOST_READY; + sts.b_iso_in.txsts = 0; + sts.b_iso_in.sp = 0; + sts.b_iso_in.ioc = 0; + sts.b_iso_in.pid = dwc_ep->pkt_per_frm; + sts.b_iso_in.framenum = dwc_ep->next_frame; + sts.b_iso_in.txbytes = dwc_ep->data_per_frame; + sts.b_iso_in.l = 0; + + for(i = 0; i < dwc_ep->desc_cnt - 1; i++) + { + writel((uint32_t)dma_ad, &dma_desc->buf); + writel(sts.d32, &dma_desc->status); + + sts.b_iso_in.framenum += dwc_ep->bInterval; + (uint32_t)dma_ad += dwc_ep->data_per_frame; + dma_desc ++; + } + + sts.b_iso_in.ioc = 1; + sts.b_iso_in.l = dwc_ep->proc_buf_num; + + writel((uint32_t)dma_ad, &dma_desc->buf); + writel(sts.d32, &dma_desc->status); + + dwc_ep->next_frame = sts.b_iso_in.framenum + dwc_ep->bInterval * 1; + } + dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1; +} + + +/** + * This function is to handle Iso EP transfer complete interrupt + * in case Iso out packet was dropped + * + * @param core_if Programming view of DWC_otg controller. + * @param dwc_ep The EP for wihich transfer complete was asserted + * + */ +static uint32_t handle_iso_out_pkt_dropped(dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep) +{ + uint32_t dma_addr; + uint32_t drp_pkt; + uint32_t drp_pkt_cnt; + deptsiz_data_t deptsiz = { .d32 = 0 }; + depctl_data_t depctl = { .d32 = 0 }; + int i; + + deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz); + + drp_pkt = dwc_ep->pkt_cnt - deptsiz.b.pktcnt; + drp_pkt_cnt = dwc_ep->pkt_per_frm - (drp_pkt % dwc_ep->pkt_per_frm); + + /* Setting dropped packets status */ + for(i = 0; i < drp_pkt_cnt; ++i) { + dwc_ep->pkt_info[drp_pkt].status = -ENODATA; + drp_pkt ++; + deptsiz.b.pktcnt--; + } + + + if(deptsiz.b.pktcnt > 0) { + deptsiz.b.xfersize = dwc_ep->xfer_len - (dwc_ep->pkt_cnt - deptsiz.b.pktcnt) * dwc_ep->maxpacket; + } else { + deptsiz.b.xfersize = 0; + deptsiz.b.pktcnt = 0; + } + + dwc_write_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz, deptsiz.d32); + + if(deptsiz.b.pktcnt > 0) { + if(dwc_ep->proc_buf_num) { + dma_addr = dwc_ep->dma_addr1 + dwc_ep->xfer_len - deptsiz.b.xfersize; + } else { + dma_addr = dwc_ep->dma_addr0 + dwc_ep->xfer_len - deptsiz.b.xfersize;; + } + + dwc_write_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepdma, dma_addr); + + /** Re-enable endpoint, clear nak */ + depctl.d32 = 0; + depctl.b.epena = 1; + depctl.b.cnak = 1; + + dwc_modify_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl, + depctl.d32,depctl.d32); + return 0; + } else { + return 1; + } +} + +/** + * This function sets iso packets information(PTI mode) + * + * @param core_if Programming view of DWC_otg controller. + * @param ep The EP to start the transfer on. + * + */ +static uint32_t set_iso_pkts_info(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) +{ + int i, j; + dma_addr_t dma_ad; + iso_pkt_info_t *packet_info = ep->pkt_info; + uint32_t offset; + uint32_t frame_data; + deptsiz_data_t deptsiz; + + if(ep->proc_buf_num == 0) { + /** Buffer 0 descriptors setup */ + dma_ad = ep->dma_addr0; + } + else { + /** Buffer 1 descriptors setup */ + dma_ad = ep->dma_addr1; + } + + + if(ep->is_in) { + deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz); + } else { + deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doeptsiz); + } + + if(!deptsiz.b.xfersize) { + offset = 0; + for(i = 0; i < ep->pkt_cnt; i += ep->pkt_per_frm) + { + frame_data = ep->data_per_frame; + for(j = 0; j < ep->pkt_per_frm; ++j) { + + /* Packet status - is not set as initially + * it is set to 0 and if packet was sent + successfully, status field will remain 0*/ + + + /* Bytes has been transfered */ + packet_info->length = (ep->maxpacket < frame_data) ? + ep->maxpacket : frame_data; + + /* Received packet offset */ + packet_info->offset = offset; + offset += packet_info->length; + frame_data -= packet_info->length; + + packet_info ++; + } + } + return 1; + } else { + /* This is a workaround for in case of Transfer Complete with + * PktDrpSts interrupts merging - in this case Transfer complete + * interrupt for Isoc Out Endpoint is asserted without PktDrpSts + * set and with DOEPTSIZ register non zero. Investigations showed, + * that this happens when Out packet is dropped, but because of + * interrupts merging during first interrupt handling PktDrpSts + * bit is cleared and for next merged interrupts it is not reset. + * In this case SW hadles the interrupt as if PktDrpSts bit is set. + */ + if(ep->is_in) { + return 1; + } else { + return handle_iso_out_pkt_dropped(core_if, ep); + } + } +} + +/** + * This function is to handle Iso EP transfer complete interrupt + * + * @param ep The EP for which transfer complete was asserted + * + */ +static void complete_iso_ep(dwc_otg_pcd_ep_t *ep) +{ + dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd); + dwc_ep_t *dwc_ep = &ep->dwc_ep; + uint8_t is_last = 0; + + if(core_if->dma_enable) { + if(core_if->dma_desc_enable) { + set_ddma_iso_pkts_info(core_if, dwc_ep); + reinit_ddma_iso_xfer(core_if, dwc_ep); + is_last = 1; + } else { + if(core_if->pti_enh_enable) { + if(set_iso_pkts_info(core_if, dwc_ep)) { + dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1; + dwc_otg_iso_ep_start_buf_transfer(core_if, dwc_ep); + is_last = 1; + } + } else { + set_current_pkt_info(core_if, dwc_ep); + if(dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) { + is_last = 1; + dwc_ep->cur_pkt = 0; + dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1; + if(dwc_ep->proc_buf_num) { + dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1; + dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1; + } else { + dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0; + dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0; + } + + } + dwc_otg_iso_ep_start_frm_transfer(core_if, dwc_ep); + } + } + } else { + set_current_pkt_info(core_if, dwc_ep); + if(dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) { + is_last = 1; + dwc_ep->cur_pkt = 0; + dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1; + if(dwc_ep->proc_buf_num) { + dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1; + dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1; + } else { + dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0; + dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0; + } + + } + dwc_otg_iso_ep_start_frm_transfer(core_if, dwc_ep); + } + if(is_last) + dwc_otg_iso_buffer_done(ep, ep->iso_req); +} + +#endif //DWC_EN_ISOC + + +/** + * This function handles EP0 Control transfers. + * + * The state of the control tranfers are tracked in + * ep0state. + */ +static void handle_ep0(dwc_otg_pcd_t *pcd) +{ + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; + desc_sts_data_t desc_sts; + deptsiz0_data_t deptsiz; + uint32_t byte_count; + +#ifdef DEBUG_EP0 + DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__); + print_ep0_state(pcd); +#endif + + switch (pcd->ep0state) { + case EP0_DISCONNECT: + break; + + case EP0_IDLE: + pcd->request_config = 0; + + pcd_setup(pcd); + break; + + case EP0_IN_DATA_PHASE: +#ifdef DEBUG_EP0 + DWC_DEBUGPL(DBG_PCD, "DATA_IN EP%d-%s: type=%d, mps=%d\n", + ep0->dwc_ep.num, (ep0->dwc_ep.is_in ?"IN":"OUT"), + ep0->dwc_ep.type, ep0->dwc_ep.maxpacket); +#endif + + if (core_if->dma_enable != 0) { + /* + * For EP0 we can only program 1 packet at a time so we + * need to do the make calculations after each complete. + * Call write_packet to make the calculations, as in + * slave mode, and use those values to determine if we + * can complete. + */ + if(core_if->dma_desc_enable == 0) { + deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[0]->dieptsiz); + byte_count = ep0->dwc_ep.xfer_len - deptsiz.b.xfersize; + } + else { + desc_sts.d32 = readl(core_if->dev_if->in_desc_addr); + byte_count = ep0->dwc_ep.xfer_len - desc_sts.b.bytes; + } + ep0->dwc_ep.xfer_count += byte_count; + ep0->dwc_ep.xfer_buff += byte_count; + ep0->dwc_ep.dma_addr += byte_count; + } + if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) { + dwc_otg_ep0_continue_transfer (GET_CORE_IF(pcd), &ep0->dwc_ep); + DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n"); + } + else if(ep0->dwc_ep.sent_zlp) { + dwc_otg_ep0_continue_transfer (GET_CORE_IF(pcd), &ep0->dwc_ep); + ep0->dwc_ep.sent_zlp = 0; + DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n"); + } + else { + ep0_complete_request(ep0); + DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n"); + } + break; + case EP0_OUT_DATA_PHASE: +#ifdef DEBUG_EP0 + DWC_DEBUGPL(DBG_PCD, "DATA_OUT EP%d-%s: type=%d, mps=%d\n", + ep0->dwc_ep.num, (ep0->dwc_ep.is_in ?"IN":"OUT"), + ep0->dwc_ep.type, ep0->dwc_ep.maxpacket); +#endif + if (core_if->dma_enable != 0) { + if(core_if->dma_desc_enable == 0) { + deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->out_ep_regs[0]->doeptsiz); + byte_count = ep0->dwc_ep.maxpacket - deptsiz.b.xfersize; + } + else { + desc_sts.d32 = readl(core_if->dev_if->out_desc_addr); + byte_count = ep0->dwc_ep.maxpacket - desc_sts.b.bytes; + } + ep0->dwc_ep.xfer_count += byte_count; + ep0->dwc_ep.xfer_buff += byte_count; + ep0->dwc_ep.dma_addr += byte_count; + } + if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) { + dwc_otg_ep0_continue_transfer (GET_CORE_IF(pcd), &ep0->dwc_ep); + DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n"); + } + else if(ep0->dwc_ep.sent_zlp) { + dwc_otg_ep0_continue_transfer (GET_CORE_IF(pcd), &ep0->dwc_ep); + ep0->dwc_ep.sent_zlp = 0; + DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n"); + } + else { + ep0_complete_request(ep0); + DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n"); + } + break; + + + case EP0_IN_STATUS_PHASE: + case EP0_OUT_STATUS_PHASE: + DWC_DEBUGPL(DBG_PCD, "CASE: EP0_STATUS\n"); + ep0_complete_request(ep0); + pcd->ep0state = EP0_IDLE; + ep0->stopped = 1; + ep0->dwc_ep.is_in = 0; /* OUT for next SETUP */ + + /* Prepare for more SETUP Packets */ + if(core_if->dma_enable) { + ep0_out_start(core_if, pcd); + } + break; + + case EP0_STALL: + DWC_ERROR("EP0 STALLed, should not get here pcd_setup()\n"); + break; + } +#ifdef DEBUG_EP0 + print_ep0_state(pcd); +#endif +} + + +/** + * Restart transfer + */ +static void restart_transfer(dwc_otg_pcd_t *pcd, const uint32_t epnum) +{ + dwc_otg_core_if_t *core_if; + dwc_otg_dev_if_t *dev_if; + deptsiz_data_t dieptsiz = {.d32=0}; + dwc_otg_pcd_ep_t *ep; + + ep = get_in_ep(pcd, epnum); + +#ifdef DWC_EN_ISOC + if(ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) { + return; + } +#endif /* DWC_EN_ISOC */ + + core_if = GET_CORE_IF(pcd); + dev_if = core_if->dev_if; + + dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dieptsiz); + + DWC_DEBUGPL(DBG_PCD,"xfer_buff=%p xfer_count=%0x xfer_len=%0x" + " stopped=%d\n", ep->dwc_ep.xfer_buff, + ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len , + ep->stopped); + /* + * If xfersize is 0 and pktcnt in not 0, resend the last packet. + */ + if (dieptsiz.b.pktcnt && dieptsiz.b.xfersize == 0 && + ep->dwc_ep.start_xfer_buff != 0) { + if (ep->dwc_ep.total_len <= ep->dwc_ep.maxpacket) { + ep->dwc_ep.xfer_count = 0; + ep->dwc_ep.xfer_buff = ep->dwc_ep.start_xfer_buff; + ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count; + } + else { + ep->dwc_ep.xfer_count -= ep->dwc_ep.maxpacket; + /* convert packet size to dwords. */ + ep->dwc_ep.xfer_buff -= ep->dwc_ep.maxpacket; + ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count; + } + ep->stopped = 0; + DWC_DEBUGPL(DBG_PCD,"xfer_buff=%p xfer_count=%0x " + "xfer_len=%0x stopped=%d\n", + ep->dwc_ep.xfer_buff, + ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len , + ep->stopped + ); + if (epnum == 0) { + dwc_otg_ep0_start_transfer(core_if, &ep->dwc_ep); + } + else { + dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep); + } + } +} + + +/** + * handle the IN EP disable interrupt. + */ +static inline void handle_in_ep_disable_intr(dwc_otg_pcd_t *pcd, + const uint32_t epnum) +{ + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); + dwc_otg_dev_if_t *dev_if = core_if->dev_if; + deptsiz_data_t dieptsiz = {.d32=0}; + dctl_data_t dctl = {.d32=0}; + dwc_otg_pcd_ep_t *ep; + dwc_ep_t *dwc_ep; + + ep = get_in_ep(pcd, epnum); + dwc_ep = &ep->dwc_ep; + + if(dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { + dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num); + return; + } + + DWC_DEBUGPL(DBG_PCD,"diepctl%d=%0x\n", epnum, + dwc_read_reg32(&dev_if->in_ep_regs[epnum]->diepctl)); + dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dieptsiz); + + DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n", + dieptsiz.b.pktcnt, + dieptsiz.b.xfersize); + + if (ep->stopped) { + /* Flush the Tx FIFO */ + dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num); + /* Clear the Global IN NP NAK */ + dctl.d32 = 0; + dctl.b.cgnpinnak = 1; + dwc_modify_reg32(&dev_if->dev_global_regs->dctl, + dctl.d32, 0); + /* Restart the transaction */ + if (dieptsiz.b.pktcnt != 0 || + dieptsiz.b.xfersize != 0) { + restart_transfer(pcd, epnum); + } + } + else { + /* Restart the transaction */ + if (dieptsiz.b.pktcnt != 0 || + dieptsiz.b.xfersize != 0) { + restart_transfer(pcd, epnum); + } + DWC_DEBUGPL(DBG_ANY, "STOPPED!!!\n"); + } +} + +/** + * Handler for the IN EP timeout handshake interrupt. + */ +static inline void handle_in_ep_timeout_intr(dwc_otg_pcd_t *pcd, + const uint32_t epnum) +{ + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); + dwc_otg_dev_if_t *dev_if = core_if->dev_if; + +#ifdef DEBUG + deptsiz_data_t dieptsiz = {.d32=0}; + uint32_t num = 0; +#endif + dctl_data_t dctl = {.d32=0}; + dwc_otg_pcd_ep_t *ep; + + gintmsk_data_t intr_mask = {.d32 = 0}; + + ep = get_in_ep(pcd, epnum); + + /* Disable the NP Tx Fifo Empty Interrrupt */ + if (!core_if->dma_enable) { + intr_mask.b.nptxfempty = 1; + dwc_modify_reg32(&core_if->core_global_regs->gintmsk, intr_mask.d32, 0); + } + /** @todo NGS Check EP type. + * Implement for Periodic EPs */ + /* + * Non-periodic EP + */ + /* Enable the Global IN NAK Effective Interrupt */ + intr_mask.b.ginnakeff = 1; + dwc_modify_reg32(&core_if->core_global_regs->gintmsk, + 0, intr_mask.d32); + + /* Set Global IN NAK */ + dctl.b.sgnpinnak = 1; + dwc_modify_reg32(&dev_if->dev_global_regs->dctl, + dctl.d32, dctl.d32); + + ep->stopped = 1; + +#ifdef DEBUG + dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[num]->dieptsiz); + DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n", + dieptsiz.b.pktcnt, + dieptsiz.b.xfersize); +#endif + +#ifdef DISABLE_PERIODIC_EP + /* + * Set the NAK bit for this EP to + * start the disable process. + */ + diepctl.d32 = 0; + diepctl.b.snak = 1; + dwc_modify_reg32(&dev_if->in_ep_regs[num]->diepctl, diepctl.d32, diepctl.d32); + ep->disabling = 1; + ep->stopped = 1; +#endif +} + +/** + * Handler for the IN EP NAK interrupt. + */ +static inline int32_t handle_in_ep_nak_intr(dwc_otg_pcd_t *pcd, + const uint32_t epnum) +{ + /** @todo implement ISR */ + dwc_otg_core_if_t* core_if; + diepmsk_data_t intr_mask = { .d32 = 0}; + + DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "IN EP NAK"); + core_if = GET_CORE_IF(pcd); + intr_mask.b.nak = 1; + + if(core_if->multiproc_int_enable) { + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->diepeachintmsk[epnum], + intr_mask.d32, 0); + } else { + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->diepmsk, + intr_mask.d32, 0); + } + + return 1; +} + +/** + * Handler for the OUT EP Babble interrupt. + */ +static inline int32_t handle_out_ep_babble_intr(dwc_otg_pcd_t *pcd, + const uint32_t epnum) +{ + /** @todo implement ISR */ + dwc_otg_core_if_t* core_if; + doepmsk_data_t intr_mask = { .d32 = 0}; + + DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "OUT EP Babble"); + core_if = GET_CORE_IF(pcd); + intr_mask.b.babble = 1; + + if(core_if->multiproc_int_enable) { + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepeachintmsk[epnum], + intr_mask.d32, 0); + } else { + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk, + intr_mask.d32, 0); + } + + return 1; +} + +/** + * Handler for the OUT EP NAK interrupt. + */ +static inline int32_t handle_out_ep_nak_intr(dwc_otg_pcd_t *pcd, + const uint32_t epnum) +{ + /** @todo implement ISR */ + dwc_otg_core_if_t* core_if; + doepmsk_data_t intr_mask = { .d32 = 0}; + + DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "OUT EP NAK"); + core_if = GET_CORE_IF(pcd); + intr_mask.b.nak = 1; + + if(core_if->multiproc_int_enable) { + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepeachintmsk[epnum], + intr_mask.d32, 0); + } else { + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk, + intr_mask.d32, 0); + } + + return 1; +} + +/** + * Handler for the OUT EP NYET interrupt. + */ +static inline int32_t handle_out_ep_nyet_intr(dwc_otg_pcd_t *pcd, + const uint32_t epnum) +{ + /** @todo implement ISR */ + dwc_otg_core_if_t* core_if; + doepmsk_data_t intr_mask = { .d32 = 0}; + + DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "OUT EP NYET"); + core_if = GET_CORE_IF(pcd); + intr_mask.b.nyet = 1; + + if(core_if->multiproc_int_enable) { + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepeachintmsk[epnum], + intr_mask.d32, 0); + } else { + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk, + intr_mask.d32, 0); + } + + return 1; +} + +/** + * This interrupt indicates that an IN EP has a pending Interrupt. + * The sequence for handling the IN EP interrupt is shown below: + * -# Read the Device All Endpoint Interrupt register + * -# Repeat the following for each IN EP interrupt bit set (from + * LSB to MSB). + * -# Read the Device Endpoint Interrupt (DIEPINTn) register + * -# If "Transfer Complete" call the request complete function + * -# If "Endpoint Disabled" complete the EP disable procedure. + * -# If "AHB Error Interrupt" log error + * -# If "Time-out Handshake" log error + * -# If "IN Token Received when TxFIFO Empty" write packet to Tx + * FIFO. + * -# If "IN Token EP Mismatch" (disable, this is handled by EP + * Mismatch Interrupt) + */ +static int32_t dwc_otg_pcd_handle_in_ep_intr(dwc_otg_pcd_t *pcd) +{ +#define CLEAR_IN_EP_INTR(__core_if,__epnum,__intr) \ +do { \ + diepint_data_t diepint = {.d32=0}; \ + diepint.b.__intr = 1; \ + dwc_write_reg32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \ + diepint.d32); \ +} while (0) + + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); + dwc_otg_dev_if_t *dev_if = core_if->dev_if; + diepint_data_t diepint = {.d32=0}; + dctl_data_t dctl = {.d32=0}; + depctl_data_t depctl = {.d32=0}; + uint32_t ep_intr; + uint32_t epnum = 0; + dwc_otg_pcd_ep_t *ep; + dwc_ep_t *dwc_ep; + gintmsk_data_t intr_mask = {.d32 = 0}; + + + + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pcd); + + /* Read in the device interrupt bits */ + ep_intr = dwc_otg_read_dev_all_in_ep_intr(core_if); + + /* Service the Device IN interrupts for each endpoint */ + while(ep_intr) { + if (ep_intr&0x1) { + uint32_t empty_msk; + /* Get EP pointer */ + ep = get_in_ep(pcd, epnum); + dwc_ep = &ep->dwc_ep; + + depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->diepctl); + empty_msk = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk); + + DWC_DEBUGPL(DBG_PCDV, + "IN EP INTERRUPT - %d\nepmty_msk - %8x diepctl - %8x\n", + epnum, + empty_msk, + depctl.d32); + + DWC_DEBUGPL(DBG_PCD, + "EP%d-%s: type=%d, mps=%d\n", + dwc_ep->num, (dwc_ep->is_in ?"IN":"OUT"), + dwc_ep->type, dwc_ep->maxpacket); + + diepint.d32 = dwc_otg_read_dev_in_ep_intr(core_if, dwc_ep); + + DWC_DEBUGPL(DBG_PCDV, "EP %d Interrupt Register - 0x%x\n", epnum, diepint.d32); + /* Transfer complete */ + if (diepint.b.xfercompl) { + /* Disable the NP Tx FIFO Empty + * Interrrupt */ + if(core_if->en_multiple_tx_fifo == 0) { + intr_mask.b.nptxfempty = 1; + dwc_modify_reg32(&core_if->core_global_regs->gintmsk, intr_mask.d32, 0); + } + else { + /* Disable the Tx FIFO Empty Interrupt for this EP */ + uint32_t fifoemptymsk = 0x1 << dwc_ep->num; + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk, + fifoemptymsk, 0); + } + /* Clear the bit in DIEPINTn for this interrupt */ + CLEAR_IN_EP_INTR(core_if,epnum,xfercompl); + + /* Complete the transfer */ + if (epnum == 0) { + handle_ep0(pcd); + } +#ifdef DWC_EN_ISOC + else if(dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { + if(!ep->stopped) + complete_iso_ep(ep); + } +#endif //DWC_EN_ISOC + else { + + complete_ep(ep); + } + } + /* Endpoint disable */ + if (diepint.b.epdisabled) { + DWC_DEBUGPL(DBG_ANY,"EP%d IN disabled\n", epnum); + handle_in_ep_disable_intr(pcd, epnum); + + /* Clear the bit in DIEPINTn for this interrupt */ + CLEAR_IN_EP_INTR(core_if,epnum,epdisabled); + } + /* AHB Error */ + if (diepint.b.ahberr) { + DWC_DEBUGPL(DBG_ANY,"EP%d IN AHB Error\n", epnum); + /* Clear the bit in DIEPINTn for this interrupt */ + CLEAR_IN_EP_INTR(core_if,epnum,ahberr); + } + /* TimeOUT Handshake (non-ISOC IN EPs) */ + if (diepint.b.timeout) { + DWC_DEBUGPL(DBG_ANY,"EP%d IN Time-out\n", epnum); + handle_in_ep_timeout_intr(pcd, epnum); + + CLEAR_IN_EP_INTR(core_if,epnum,timeout); + } + /** IN Token received with TxF Empty */ + if (diepint.b.intktxfemp) { + DWC_DEBUGPL(DBG_ANY,"EP%d IN TKN TxFifo Empty\n", + epnum); + if (!ep->stopped && epnum != 0) { + + diepmsk_data_t diepmsk = { .d32 = 0}; + diepmsk.b.intktxfemp = 1; + + if(core_if->multiproc_int_enable) { + dwc_modify_reg32(&dev_if->dev_global_regs->diepeachintmsk[epnum], + diepmsk.d32, 0); + } else { + dwc_modify_reg32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32, 0); + } + start_next_request(ep); + } + else if(core_if->dma_desc_enable && epnum == 0 && + pcd->ep0state == EP0_OUT_STATUS_PHASE) { + // EP0 IN set STALL + depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->diepctl); + + /* set the disable and stall bits */ + if (depctl.b.epena) { + depctl.b.epdis = 1; + } + depctl.b.stall = 1; + dwc_write_reg32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32); + } + CLEAR_IN_EP_INTR(core_if,epnum,intktxfemp); + } + /** IN Token Received with EP mismatch */ + if (diepint.b.intknepmis) { + DWC_DEBUGPL(DBG_ANY,"EP%d IN TKN EP Mismatch\n", epnum); + CLEAR_IN_EP_INTR(core_if,epnum,intknepmis); + } + /** IN Endpoint NAK Effective */ + if (diepint.b.inepnakeff) { + DWC_DEBUGPL(DBG_ANY,"EP%d IN EP NAK Effective\n", epnum); + /* Periodic EP */ + if (ep->disabling) { + depctl.d32 = 0; + depctl.b.snak = 1; + depctl.b.epdis = 1; + dwc_modify_reg32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32, depctl.d32); + } + CLEAR_IN_EP_INTR(core_if,epnum,inepnakeff); + + } + + /** IN EP Tx FIFO Empty Intr */ + if (diepint.b.emptyintr) { + DWC_DEBUGPL(DBG_ANY,"EP%d Tx FIFO Empty Intr \n", epnum); + write_empty_tx_fifo(pcd, epnum); + + CLEAR_IN_EP_INTR(core_if,epnum,emptyintr); + + } + + /** IN EP BNA Intr */ + if (diepint.b.bna) { + CLEAR_IN_EP_INTR(core_if,epnum,bna); + if(core_if->dma_desc_enable) { +#ifdef DWC_EN_ISOC + if(dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { + /* + * This checking is performed to prevent first "false" BNA + * handling occuring right after reconnect + */ + if(dwc_ep->next_frame != 0xffffffff) + dwc_otg_pcd_handle_iso_bna(ep); + } + else +#endif //DWC_EN_ISOC + { + dctl.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dctl); + + /* If Global Continue on BNA is disabled - disable EP */ + if(!dctl.b.gcontbna) { + depctl.d32 = 0; + depctl.b.snak = 1; + depctl.b.epdis = 1; + dwc_modify_reg32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32, depctl.d32); + } else { + start_next_request(ep); + } + } + } + } + /* NAK Interrutp */ + if (diepint.b.nak) { + DWC_DEBUGPL(DBG_ANY,"EP%d IN NAK Interrupt\n", epnum); + handle_in_ep_nak_intr(pcd, epnum); + + CLEAR_IN_EP_INTR(core_if,epnum,nak); + } + } + epnum++; + ep_intr >>=1; + } + + return 1; +#undef CLEAR_IN_EP_INTR +} + +/** + * This interrupt indicates that an OUT EP has a pending Interrupt. + * The sequence for handling the OUT EP interrupt is shown below: + * -# Read the Device All Endpoint Interrupt register + * -# Repeat the following for each OUT EP interrupt bit set (from + * LSB to MSB). + * -# Read the Device Endpoint Interrupt (DOEPINTn) register + * -# If "Transfer Complete" call the request complete function + * -# If "Endpoint Disabled" complete the EP disable procedure. + * -# If "AHB Error Interrupt" log error + * -# If "Setup Phase Done" process Setup Packet (See Standard USB + * Command Processing) + */ +static int32_t dwc_otg_pcd_handle_out_ep_intr(dwc_otg_pcd_t *pcd) +{ +#define CLEAR_OUT_EP_INTR(__core_if,__epnum,__intr) \ +do { \ + doepint_data_t doepint = {.d32=0}; \ + doepint.b.__intr = 1; \ + dwc_write_reg32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \ + doepint.d32); \ +} while (0) + + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); + dwc_otg_dev_if_t *dev_if = core_if->dev_if; + uint32_t ep_intr; + doepint_data_t doepint = {.d32=0}; + dctl_data_t dctl = {.d32=0}; + depctl_data_t doepctl = {.d32=0}; + uint32_t epnum = 0; + dwc_otg_pcd_ep_t *ep; + dwc_ep_t *dwc_ep; + + DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__); + + /* Read in the device interrupt bits */ + ep_intr = dwc_otg_read_dev_all_out_ep_intr(core_if); + + while(ep_intr) { + if (ep_intr&0x1) { + /* Get EP pointer */ + ep = get_out_ep(pcd, epnum); + dwc_ep = &ep->dwc_ep; + +#ifdef VERBOSE + DWC_DEBUGPL(DBG_PCDV, + "EP%d-%s: type=%d, mps=%d\n", + dwc_ep->num, (dwc_ep->is_in ?"IN":"OUT"), + dwc_ep->type, dwc_ep->maxpacket); +#endif + doepint.d32 = dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep); + + /* Transfer complete */ + if (doepint.b.xfercompl) { + + if (epnum == 0) { + /* Clear the bit in DOEPINTn for this interrupt */ + CLEAR_OUT_EP_INTR(core_if,epnum,xfercompl); + if(core_if->dma_desc_enable == 0 || pcd->ep0state != EP0_IDLE) + handle_ep0(pcd); +#ifdef DWC_EN_ISOC + } else if(dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { + if (doepint.b.pktdrpsts == 0) { + /* Clear the bit in DOEPINTn for this interrupt */ + CLEAR_OUT_EP_INTR(core_if,epnum,xfercompl); + complete_iso_ep(ep); + } else { + + doepint_data_t doepint = {.d32=0}; + doepint.b.xfercompl = 1; + doepint.b.pktdrpsts = 1; + dwc_write_reg32(&core_if->dev_if->out_ep_regs[epnum]->doepint, + doepint.d32); + if(handle_iso_out_pkt_dropped(core_if,dwc_ep)) { + complete_iso_ep(ep); + } + } +#endif //DWC_EN_ISOC + } else { + /* Clear the bit in DOEPINTn for this interrupt */ + CLEAR_OUT_EP_INTR(core_if,epnum,xfercompl); + complete_ep(ep); + } + + } + + /* Endpoint disable */ + if (doepint.b.epdisabled) { + + /* Clear the bit in DOEPINTn for this interrupt */ + CLEAR_OUT_EP_INTR(core_if,epnum,epdisabled); + } + /* AHB Error */ + if (doepint.b.ahberr) { + DWC_DEBUGPL(DBG_PCD,"EP%d OUT AHB Error\n", epnum); + DWC_DEBUGPL(DBG_PCD,"EP DMA REG %d \n", core_if->dev_if->out_ep_regs[epnum]->doepdma); + CLEAR_OUT_EP_INTR(core_if,epnum,ahberr); + } + /* Setup Phase Done (contorl EPs) */ + if (doepint.b.setup) { +#ifdef DEBUG_EP0 + DWC_DEBUGPL(DBG_PCD,"EP%d SETUP Done\n", + epnum); +#endif + CLEAR_OUT_EP_INTR(core_if,epnum,setup); + + handle_ep0(pcd); + } + + /** OUT EP BNA Intr */ + if (doepint.b.bna) { + CLEAR_OUT_EP_INTR(core_if,epnum,bna); + if(core_if->dma_desc_enable) { +#ifdef DWC_EN_ISOC + if(dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { + /* + * This checking is performed to prevent first "false" BNA + * handling occuring right after reconnect + */ + if(dwc_ep->next_frame != 0xffffffff) + dwc_otg_pcd_handle_iso_bna(ep); + } + else +#endif //DWC_EN_ISOC + { + dctl.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dctl); + + /* If Global Continue on BNA is disabled - disable EP*/ + if(!dctl.b.gcontbna) { + doepctl.d32 = 0; + doepctl.b.snak = 1; + doepctl.b.epdis = 1; + dwc_modify_reg32(&dev_if->out_ep_regs[epnum]->doepctl, doepctl.d32, doepctl.d32); + } else { + start_next_request(ep); + } + } + } + } + if (doepint.b.stsphsercvd) { + CLEAR_OUT_EP_INTR(core_if,epnum,stsphsercvd); + if(core_if->dma_desc_enable) { + do_setup_in_status_phase(pcd); + } + } + /* Babble Interrutp */ + if (doepint.b.babble) { + DWC_DEBUGPL(DBG_ANY,"EP%d OUT Babble\n", epnum); + handle_out_ep_babble_intr(pcd, epnum); + + CLEAR_OUT_EP_INTR(core_if,epnum,babble); + } + /* NAK Interrutp */ + if (doepint.b.nak) { + DWC_DEBUGPL(DBG_ANY,"EP%d OUT NAK\n", epnum); + handle_out_ep_nak_intr(pcd, epnum); + + CLEAR_OUT_EP_INTR(core_if,epnum,nak); + } + /* NYET Interrutp */ + if (doepint.b.nyet) { + DWC_DEBUGPL(DBG_ANY,"EP%d OUT NYET\n", epnum); + handle_out_ep_nyet_intr(pcd, epnum); + + CLEAR_OUT_EP_INTR(core_if,epnum,nyet); + } + } + + epnum++; + ep_intr >>=1; + } + + return 1; + +#undef CLEAR_OUT_EP_INTR +} + + +/** + * Incomplete ISO IN Transfer Interrupt. + * This interrupt indicates one of the following conditions occurred + * while transmitting an ISOC transaction. + * - Corrupted IN Token for ISOC EP. + * - Packet not complete in FIFO. + * The follow actions will be taken: + * -# Determine the EP + * -# Set incomplete flag in dwc_ep structure + * -# Disable EP; when "Endpoint Disabled" interrupt is received + * Flush FIFO + */ +int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr(dwc_otg_pcd_t *pcd) +{ + gintsts_data_t gintsts; + + +#ifdef DWC_EN_ISOC + dwc_otg_dev_if_t *dev_if; + deptsiz_data_t deptsiz = { .d32 = 0}; + depctl_data_t depctl = { .d32 = 0}; + dsts_data_t dsts = { .d32 = 0}; + dwc_ep_t *dwc_ep; + int i; + + dev_if = GET_CORE_IF(pcd)->dev_if; + + for(i = 1; i <= dev_if->num_in_eps; ++i) { + dwc_ep = &pcd->in_ep[i].dwc_ep; + if(dwc_ep->active && + dwc_ep->type == USB_ENDPOINT_XFER_ISOC) + { + deptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->dieptsiz); + depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl); + + if(depctl.b.epdis && deptsiz.d32) { + set_current_pkt_info(GET_CORE_IF(pcd), dwc_ep); + if(dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) { + dwc_ep->cur_pkt = 0; + dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1; + + if(dwc_ep->proc_buf_num) { + dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1; + dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1; + } else { + dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0; + dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0; + } + + } + + dsts.d32 = dwc_read_reg32(&GET_CORE_IF(pcd)->dev_if->dev_global_regs->dsts); + dwc_ep->next_frame = dsts.b.soffn; + + dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF(pcd), dwc_ep); + } + } + } + +#else + gintmsk_data_t intr_mask = { .d32 = 0}; + DWC_PRINT("INTERRUPT Handler not implemented for %s\n", + "IN ISOC Incomplete"); + + intr_mask.b.incomplisoin = 1; + dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, + intr_mask.d32, 0); +#endif //DWC_EN_ISOC + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.incomplisoin = 1; + dwc_write_reg32 (&GET_CORE_IF(pcd)->core_global_regs->gintsts, + gintsts.d32); + + return 1; +} + +/** + * Incomplete ISO OUT Transfer Interrupt. + * + * This interrupt indicates that the core has dropped an ISO OUT + * packet. The following conditions can be the cause: + * - FIFO Full, the entire packet would not fit in the FIFO. + * - CRC Error + * - Corrupted Token + * The follow actions will be taken: + * -# Determine the EP + * -# Set incomplete flag in dwc_ep structure + * -# Read any data from the FIFO + * -# Disable EP. when "Endpoint Disabled" interrupt is received + * re-enable EP. + */ +int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr(dwc_otg_pcd_t *pcd) +{ + /* @todo implement ISR */ + gintsts_data_t gintsts; + +#ifdef DWC_EN_ISOC + dwc_otg_dev_if_t *dev_if; + deptsiz_data_t deptsiz = { .d32 = 0}; + depctl_data_t depctl = { .d32 = 0}; + dsts_data_t dsts = { .d32 = 0}; + dwc_ep_t *dwc_ep; + int i; + + dev_if = GET_CORE_IF(pcd)->dev_if; + + for(i = 1; i <= dev_if->num_out_eps; ++i) { + dwc_ep = &pcd->in_ep[i].dwc_ep; + if(pcd->out_ep[i].dwc_ep.active && + pcd->out_ep[i].dwc_ep.type == USB_ENDPOINT_XFER_ISOC) + { + deptsiz.d32 = dwc_read_reg32(&dev_if->out_ep_regs[i]->doeptsiz); + depctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[i]->doepctl); + + if(depctl.b.epdis && deptsiz.d32) { + set_current_pkt_info(GET_CORE_IF(pcd), &pcd->out_ep[i].dwc_ep); + if(dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) { + dwc_ep->cur_pkt = 0; + dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1; + + if(dwc_ep->proc_buf_num) { + dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1; + dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1; + } else { + dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0; + dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0; + } + + } + + dsts.d32 = dwc_read_reg32(&GET_CORE_IF(pcd)->dev_if->dev_global_regs->dsts); + dwc_ep->next_frame = dsts.b.soffn; + + dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF(pcd), dwc_ep); + } + } + } +#else + /** @todo implement ISR */ + gintmsk_data_t intr_mask = { .d32 = 0}; + + DWC_PRINT("INTERRUPT Handler not implemented for %s\n", + "OUT ISOC Incomplete"); + + intr_mask.b.incomplisoout = 1; + dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, + intr_mask.d32, 0); + +#endif // DWC_EN_ISOC + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.incomplisoout = 1; + dwc_write_reg32 (&GET_CORE_IF(pcd)->core_global_regs->gintsts, + gintsts.d32); + + return 1; +} + +/** + * This function handles the Global IN NAK Effective interrupt. + * + */ +int32_t dwc_otg_pcd_handle_in_nak_effective(dwc_otg_pcd_t *pcd) +{ + dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if; + depctl_data_t diepctl = { .d32 = 0}; + depctl_data_t diepctl_rd = { .d32 = 0}; + gintmsk_data_t intr_mask = { .d32 = 0}; + gintsts_data_t gintsts; + int i; + + DWC_DEBUGPL(DBG_PCD, "Global IN NAK Effective\n"); + + /* Disable all active IN EPs */ + diepctl.b.epdis = 1; + diepctl.b.snak = 1; + + for (i=0; i <= dev_if->num_in_eps; i++) + { + diepctl_rd.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl); + if (diepctl_rd.b.epena) { + dwc_write_reg32(&dev_if->in_ep_regs[i]->diepctl, + diepctl.d32); + } + } + /* Disable the Global IN NAK Effective Interrupt */ + intr_mask.b.ginnakeff = 1; + dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, + intr_mask.d32, 0); + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.ginnakeff = 1; + dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, + gintsts.d32); + + return 1; +} + +/** + * OUT NAK Effective. + * + */ +int32_t dwc_otg_pcd_handle_out_nak_effective(dwc_otg_pcd_t *pcd) +{ + gintmsk_data_t intr_mask = { .d32 = 0}; + gintsts_data_t gintsts; + + DWC_PRINT("INTERRUPT Handler not implemented for %s\n", + "Global IN NAK Effective\n"); + /* Disable the Global IN NAK Effective Interrupt */ + intr_mask.b.goutnakeff = 1; + dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, + intr_mask.d32, 0); + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.goutnakeff = 1; + dwc_write_reg32 (&GET_CORE_IF(pcd)->core_global_regs->gintsts, + gintsts.d32); + + return 1; +} + + +/** + * PCD interrupt handler. + * + * The PCD handles the device interrupts. Many conditions can cause a + * device interrupt. When an interrupt occurs, the device interrupt + * service routine determines the cause of the interrupt and + * dispatches handling to the appropriate function. These interrupt + * handling functions are described below. + * + * All interrupt registers are processed from LSB to MSB. + * + */ +int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t *pcd) +{ + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); +#ifdef VERBOSE + dwc_otg_core_global_regs_t *global_regs = + core_if->core_global_regs; +#endif + gintsts_data_t gintr_status; + int32_t retval = 0; + + +#ifdef VERBOSE + DWC_DEBUGPL(DBG_ANY, "%s() gintsts=%08x gintmsk=%08x\n", + __func__, + dwc_read_reg32(&global_regs->gintsts), + dwc_read_reg32(&global_regs->gintmsk)); +#endif + + if (dwc_otg_is_device_mode(core_if)) { + SPIN_LOCK(&pcd->lock); +#ifdef VERBOSE + DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%08x gintmsk=%08x\n", + __func__, + dwc_read_reg32(&global_regs->gintsts), + dwc_read_reg32(&global_regs->gintmsk)); +#endif + + gintr_status.d32 = dwc_otg_read_core_intr(core_if); + +/* + if (!gintr_status.d32) { + SPIN_UNLOCK(&pcd->lock); + return 0; + } +*/ + DWC_DEBUGPL(DBG_PCDV, "%s: gintsts&gintmsk=%08x\n", + __func__, gintr_status.d32); + + if (gintr_status.b.sofintr) { + retval |= dwc_otg_pcd_handle_sof_intr(pcd); + } + if (gintr_status.b.rxstsqlvl) { + retval |= dwc_otg_pcd_handle_rx_status_q_level_intr(pcd); + } + if (gintr_status.b.nptxfempty) { + retval |= dwc_otg_pcd_handle_np_tx_fifo_empty_intr(pcd); + } + if (gintr_status.b.ginnakeff) { + retval |= dwc_otg_pcd_handle_in_nak_effective(pcd); + } + if (gintr_status.b.goutnakeff) { + retval |= dwc_otg_pcd_handle_out_nak_effective(pcd); + } + if (gintr_status.b.i2cintr) { + retval |= dwc_otg_pcd_handle_i2c_intr(pcd); + } + if (gintr_status.b.erlysuspend) { + retval |= dwc_otg_pcd_handle_early_suspend_intr(pcd); + } + if (gintr_status.b.usbreset) { + retval |= dwc_otg_pcd_handle_usb_reset_intr(pcd); + } + if (gintr_status.b.enumdone) { + retval |= dwc_otg_pcd_handle_enum_done_intr(pcd); + } + if (gintr_status.b.isooutdrop) { + retval |= dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(pcd); + } + if (gintr_status.b.eopframe) { + retval |= dwc_otg_pcd_handle_end_periodic_frame_intr(pcd); + } + if (gintr_status.b.epmismatch) { + retval |= dwc_otg_pcd_handle_ep_mismatch_intr(core_if); + } + if (gintr_status.b.inepint) { + if(!core_if->multiproc_int_enable) { + retval |= dwc_otg_pcd_handle_in_ep_intr(pcd); + } + } + if (gintr_status.b.outepintr) { + if(!core_if->multiproc_int_enable) { + retval |= dwc_otg_pcd_handle_out_ep_intr(pcd); + } + } + if (gintr_status.b.incomplisoin) { + retval |= dwc_otg_pcd_handle_incomplete_isoc_in_intr(pcd); + } + if (gintr_status.b.incomplisoout) { + retval |= dwc_otg_pcd_handle_incomplete_isoc_out_intr(pcd); + } + + /* In MPI mode De vice Endpoints intterrupts are asserted + * without setting outepintr and inepint bits set, so these + * Interrupt handlers are called without checking these bit-fields + */ + if(core_if->multiproc_int_enable) { + retval |= dwc_otg_pcd_handle_in_ep_intr(pcd); + retval |= dwc_otg_pcd_handle_out_ep_intr(pcd); + } +#ifdef VERBOSE + DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%0x\n", __func__, + dwc_read_reg32(&global_regs->gintsts)); +#endif + SPIN_UNLOCK(&pcd->lock); + } + + S3C2410X_CLEAR_EINTPEND(); + + return retval; +} + +#endif /* DWC_HOST_ONLY */ diff --git a/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_regs.h b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_regs.h new file mode 100644 index 0000000000..826576671b --- /dev/null +++ b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_regs.h @@ -0,0 +1,2075 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $ + * $Revision: 1.2 $ + * $Date: 2008-11-21 05:39:15 $ + * $Change: 1099526 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and + * redistribute this Software in source and binary forms, with or without + * modification, provided that redistributions of source code must retain this + * notice. You may not view, use, disclose, copy or distribute this file or + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * ========================================================================== */ + +#ifndef __DWC_OTG_REGS_H__ +#define __DWC_OTG_REGS_H__ + +/** + * @file + * + * This file contains the data structures for accessing the DWC_otg core registers. + * + * The application interfaces with the HS OTG core by reading from and + * writing to the Control and Status Register (CSR) space through the + * AHB Slave interface. These registers are 32 bits wide, and the + * addresses are 32-bit-block aligned. + * CSRs are classified as follows: + * - Core Global Registers + * - Device Mode Registers + * - Device Global Registers + * - Device Endpoint Specific Registers + * - Host Mode Registers + * - Host Global Registers + * - Host Port CSRs + * - Host Channel Specific Registers + * + * Only the Core Global registers can be accessed in both Device and + * Host modes. When the HS OTG core is operating in one mode, either + * Device or Host, the application must not access registers from the + * other mode. When the core switches from one mode to another, the + * registers in the new mode of operation must be reprogrammed as they + * would be after a power-on reset. + */ + +/** Maximum number of Periodic FIFOs */ +#define MAX_PERIO_FIFOS 15 +/** Maximum number of Transmit FIFOs */ +#define MAX_TX_FIFOS 15 + +/** Maximum number of Endpoints/HostChannels */ +#define MAX_EPS_CHANNELS 16 + +/****************************************************************************/ +/** DWC_otg Core registers . + * The dwc_otg_core_global_regs structure defines the size + * and relative field offsets for the Core Global registers. + */ +typedef struct dwc_otg_core_global_regs +{ + /** OTG Control and Status Register. Offset: 000h */ + volatile uint32_t gotgctl; + /** OTG Interrupt Register. Offset: 004h */ + volatile uint32_t gotgint; + /**Core AHB Configuration Register. Offset: 008h */ + volatile uint32_t gahbcfg; + +#define DWC_GLBINTRMASK 0x0001 +#define DWC_DMAENABLE 0x0020 +#define DWC_NPTXEMPTYLVL_EMPTY 0x0080 +#define DWC_NPTXEMPTYLVL_HALFEMPTY 0x0000 +#define DWC_PTXEMPTYLVL_EMPTY 0x0100 +#define DWC_PTXEMPTYLVL_HALFEMPTY 0x0000 + + /**Core USB Configuration Register. Offset: 00Ch */ + volatile uint32_t gusbcfg; + /**Core Reset Register. Offset: 010h */ + volatile uint32_t grstctl; + /**Core Interrupt Register. Offset: 014h */ + volatile uint32_t gintsts; + /**Core Interrupt Mask Register. Offset: 018h */ + volatile uint32_t gintmsk; + /**Receive Status Queue Read Register (Read Only). Offset: 01Ch */ + volatile uint32_t grxstsr; + /**Receive Status Queue Read & POP Register (Read Only). Offset: 020h*/ + volatile uint32_t grxstsp; + /**Receive FIFO Size Register. Offset: 024h */ + volatile uint32_t grxfsiz; + /**Non Periodic Transmit FIFO Size Register. Offset: 028h */ + volatile uint32_t gnptxfsiz; + /**Non Periodic Transmit FIFO/Queue Status Register (Read + * Only). Offset: 02Ch */ + volatile uint32_t gnptxsts; + /**I2C Access Register. Offset: 030h */ + volatile uint32_t gi2cctl; + /**PHY Vendor Control Register. Offset: 034h */ + volatile uint32_t gpvndctl; + /**General Purpose Input/Output Register. Offset: 038h */ + volatile uint32_t ggpio; + /**User ID Register. Offset: 03Ch */ + volatile uint32_t guid; + /**Synopsys ID Register (Read Only). Offset: 040h */ + volatile uint32_t gsnpsid; + /**User HW Config1 Register (Read Only). Offset: 044h */ + volatile uint32_t ghwcfg1; + /**User HW Config2 Register (Read Only). Offset: 048h */ + volatile uint32_t ghwcfg2; +#define DWC_SLAVE_ONLY_ARCH 0 +#define DWC_EXT_DMA_ARCH 1 +#define DWC_INT_DMA_ARCH 2 + +#define DWC_MODE_HNP_SRP_CAPABLE 0 +#define DWC_MODE_SRP_ONLY_CAPABLE 1 +#define DWC_MODE_NO_HNP_SRP_CAPABLE 2 +#define DWC_MODE_SRP_CAPABLE_DEVICE 3 +#define DWC_MODE_NO_SRP_CAPABLE_DEVICE 4 +#define DWC_MODE_SRP_CAPABLE_HOST 5 +#define DWC_MODE_NO_SRP_CAPABLE_HOST 6 + + /**User HW Config3 Register (Read Only). Offset: 04Ch */ + volatile uint32_t ghwcfg3; + /**User HW Config4 Register (Read Only). Offset: 050h*/ + volatile uint32_t ghwcfg4; + /** Reserved Offset: 054h-0FFh */ + volatile uint32_t reserved[43]; + /** Host Periodic Transmit FIFO Size Register. Offset: 100h */ + volatile uint32_t hptxfsiz; + /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled, + otherwise Device Transmit FIFO#n Register. + * Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15). */ + volatile uint32_t dptxfsiz_dieptxf[15]; +} dwc_otg_core_global_regs_t; + +/** + * This union represents the bit fields of the Core OTG Control + * and Status Register (GOTGCTL). Set the bits using the bit + * fields then write the d32 value to the register. + */ +typedef union gotgctl_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned sesreqscs : 1; + unsigned sesreq : 1; + unsigned reserved2_7 : 6; + unsigned hstnegscs : 1; + unsigned hnpreq : 1; + unsigned hstsethnpen : 1; + unsigned devhnpen : 1; + unsigned reserved12_15 : 4; + unsigned conidsts : 1; + unsigned reserved17 : 1; + unsigned asesvld : 1; + unsigned bsesvld : 1; + unsigned currmod : 1; + unsigned reserved21_31 : 11; + } b; +} gotgctl_data_t; + +/** + * This union represents the bit fields of the Core OTG Interrupt Register + * (GOTGINT). Set/clear the bits using the bit fields then write the d32 + * value to the register. + */ +typedef union gotgint_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /** Current Mode */ + unsigned reserved0_1 : 2; + + /** Session End Detected */ + unsigned sesenddet : 1; + + unsigned reserved3_7 : 5; + + /** Session Request Success Status Change */ + unsigned sesreqsucstschng : 1; + /** Host Negotiation Success Status Change */ + unsigned hstnegsucstschng : 1; + + unsigned reserver10_16 : 7; + + /** Host Negotiation Detected */ + unsigned hstnegdet : 1; + /** A-Device Timeout Change */ + unsigned adevtoutchng : 1; + /** Debounce Done */ + unsigned debdone : 1; + + unsigned reserved31_20 : 12; + + } b; +} gotgint_data_t; + + +/** + * This union represents the bit fields of the Core AHB Configuration + * Register (GAHBCFG). Set/clear the bits using the bit fields then + * write the d32 value to the register. + */ +typedef union gahbcfg_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned glblintrmsk : 1; +#define DWC_GAHBCFG_GLBINT_ENABLE 1 + + unsigned hburstlen : 4; +#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR 1 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7 + + unsigned dmaenable : 1; +#define DWC_GAHBCFG_DMAENABLE 1 + unsigned reserved : 1; + unsigned nptxfemplvl_txfemplvl : 1; + unsigned ptxfemplvl : 1; +#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1 +#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 + unsigned reserved9_31 : 23; + } b; +} gahbcfg_data_t; + +/** + * This union represents the bit fields of the Core USB Configuration + * Register (GUSBCFG). Set the bits using the bit fields then write + * the d32 value to the register. + */ +typedef union gusbcfg_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned toutcal : 3; + unsigned phyif : 1; + unsigned ulpi_utmi_sel : 1; + unsigned fsintf : 1; + unsigned physel : 1; + unsigned ddrsel : 1; + unsigned srpcap : 1; + unsigned hnpcap : 1; + unsigned usbtrdtim : 4; + unsigned nptxfrwnden : 1; + unsigned phylpwrclksel : 1; + unsigned otgutmifssel : 1; + unsigned ulpi_fsls : 1; + unsigned ulpi_auto_res : 1; + unsigned ulpi_clk_sus_m : 1; + unsigned ulpi_ext_vbus_drv : 1; + unsigned ulpi_int_vbus_indicator : 1; + unsigned term_sel_dl_pulse : 1; + unsigned reserved23_27 : 5; + unsigned tx_end_delay : 1; + unsigned reserved29_31 : 3; + } b; +} gusbcfg_data_t; + +/** + * This union represents the bit fields of the Core Reset Register + * (GRSTCTL). Set/clear the bits using the bit fields then write the + * d32 value to the register. + */ +typedef union grstctl_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /** Core Soft Reset (CSftRst) (Device and Host) + * + * The application can flush the control logic in the + * entire core using this bit. This bit resets the + * pipelines in the AHB Clock domain as well as the + * PHY Clock domain. + * + * The state machines are reset to an IDLE state, the + * control bits in the CSRs are cleared, all the + * transmit FIFOs and the receive FIFO are flushed. + * + * The status mask bits that control the generation of + * the interrupt, are cleared, to clear the + * interrupt. The interrupt status bits are not + * cleared, so the application can get the status of + * any events that occurred in the core after it has + * set this bit. + * + * Any transactions on the AHB are terminated as soon + * as possible following the protocol. Any + * transactions on the USB are terminated immediately. + * + * The configuration settings in the CSRs are + * unchanged, so the software doesn't have to + * reprogram these registers (Device + * Configuration/Host Configuration/Core System + * Configuration/Core PHY Configuration). + * + * The application can write to this bit, any time it + * wants to reset the core. This is a self clearing + * bit and the core clears this bit after all the + * necessary logic is reset in the core, which may + * take several clocks, depending on the current state + * of the core. + */ + unsigned csftrst : 1; + /** Hclk Soft Reset + * + * The application uses this bit to reset the control logic in + * the AHB clock domain. Only AHB clock domain pipelines are + * reset. + */ + unsigned hsftrst : 1; + /** Host Frame Counter Reset (Host Only)
+ * + * The application can reset the (micro)frame number + * counter inside the core, using this bit. When the + * (micro)frame counter is reset, the subsequent SOF + * sent out by the core, will have a (micro)frame + * number of 0. + */ + unsigned hstfrm : 1; + /** In Token Sequence Learning Queue Flush + * (INTknQFlsh) (Device Only) + */ + unsigned intknqflsh : 1; + /** RxFIFO Flush (RxFFlsh) (Device and Host) + * + * The application can flush the entire Receive FIFO + * using this bit.

The application must first + * ensure that the core is not in the middle of a + * transaction.

The application should write into + * this bit, only after making sure that neither the + * DMA engine is reading from the RxFIFO nor the MAC + * is writing the data in to the FIFO.

The + * application should wait until the bit is cleared + * before performing any other operations. This bit + * will takes 8 clocks (slowest of PHY or AHB clock) + * to clear. + */ + unsigned rxfflsh : 1; + /** TxFIFO Flush (TxFFlsh) (Device and Host). + * + * This bit is used to selectively flush a single or + * all transmit FIFOs. The application must first + * ensure that the core is not in the middle of a + * transaction.

The application should write into + * this bit, only after making sure that neither the + * DMA engine is writing into the TxFIFO nor the MAC + * is reading the data out of the FIFO.

The + * application should wait until the core clears this + * bit, before performing any operations. This bit + * will takes 8 clocks (slowest of PHY or AHB clock) + * to clear. + */ + unsigned txfflsh : 1; + + /** TxFIFO Number (TxFNum) (Device and Host). + * + * This is the FIFO number which needs to be flushed, + * using the TxFIFO Flush bit. This field should not + * be changed until the TxFIFO Flush bit is cleared by + * the core. + * - 0x0 : Non Periodic TxFIFO Flush + * - 0x1 : Periodic TxFIFO #1 Flush in device mode + * or Periodic TxFIFO in host mode + * - 0x2 : Periodic TxFIFO #2 Flush in device mode. + * - ... + * - 0xF : Periodic TxFIFO #15 Flush in device mode + * - 0x10: Flush all the Transmit NonPeriodic and + * Transmit Periodic FIFOs in the core + */ + unsigned txfnum : 5; + /** Reserved */ + unsigned reserved11_29 : 19; + /** DMA Request Signal. Indicated DMA request is in + * probress. Used for debug purpose. */ + unsigned dmareq : 1; + /** AHB Master Idle. Indicates the AHB Master State + * Machine is in IDLE condition. */ + unsigned ahbidle : 1; + } b; +} grstctl_t; + + +/** + * This union represents the bit fields of the Core Interrupt Mask + * Register (GINTMSK). Set/clear the bits using the bit fields then + * write the d32 value to the register. + */ +typedef union gintmsk_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned reserved0 : 1; + unsigned modemismatch : 1; + unsigned otgintr : 1; + unsigned sofintr : 1; + unsigned rxstsqlvl : 1; + unsigned nptxfempty : 1; + unsigned ginnakeff : 1; + unsigned goutnakeff : 1; + unsigned reserved8 : 1; + unsigned i2cintr : 1; + unsigned erlysuspend : 1; + unsigned usbsuspend : 1; + unsigned usbreset : 1; + unsigned enumdone : 1; + unsigned isooutdrop : 1; + unsigned eopframe : 1; + unsigned reserved16 : 1; + unsigned epmismatch : 1; + unsigned inepintr : 1; + unsigned outepintr : 1; + unsigned incomplisoin : 1; + unsigned incomplisoout : 1; + unsigned reserved22_23 : 2; + unsigned portintr : 1; + unsigned hcintr : 1; + unsigned ptxfempty : 1; + unsigned reserved27 : 1; + unsigned conidstschng : 1; + unsigned disconnect : 1; + unsigned sessreqintr : 1; + unsigned wkupintr : 1; + } b; +} gintmsk_data_t; +/** + * This union represents the bit fields of the Core Interrupt Register + * (GINTSTS). Set/clear the bits using the bit fields then write the + * d32 value to the register. + */ +typedef union gintsts_data +{ + /** raw register data */ + uint32_t d32; +#define DWC_SOF_INTR_MASK 0x0008 + /** register bits */ + struct + { +#define DWC_HOST_MODE 1 + unsigned curmode : 1; + unsigned modemismatch : 1; + unsigned otgintr : 1; + unsigned sofintr : 1; + unsigned rxstsqlvl : 1; + unsigned nptxfempty : 1; + unsigned ginnakeff : 1; + unsigned goutnakeff : 1; + unsigned reserved8 : 1; + unsigned i2cintr : 1; + unsigned erlysuspend : 1; + unsigned usbsuspend : 1; + unsigned usbreset : 1; + unsigned enumdone : 1; + unsigned isooutdrop : 1; + unsigned eopframe : 1; + unsigned intokenrx : 1; + unsigned epmismatch : 1; + unsigned inepint: 1; + unsigned outepintr : 1; + unsigned incomplisoin : 1; + unsigned incomplisoout : 1; + unsigned reserved22_23 : 2; + unsigned portintr : 1; + unsigned hcintr : 1; + unsigned ptxfempty : 1; + unsigned reserved27 : 1; + unsigned conidstschng : 1; + unsigned disconnect : 1; + unsigned sessreqintr : 1; + unsigned wkupintr : 1; + } b; +} gintsts_data_t; + + +/** + * This union represents the bit fields in the Device Receive Status Read and + * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 + * element then read out the bits using the bit elements. + */ +typedef union device_grxsts_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned epnum : 4; + unsigned bcnt : 11; + unsigned dpid : 2; + +#define DWC_STS_DATA_UPDT 0x2 // OUT Data Packet +#define DWC_STS_XFER_COMP 0x3 // OUT Data Transfer Complete + +#define DWC_DSTS_GOUT_NAK 0x1 // Global OUT NAK +#define DWC_DSTS_SETUP_COMP 0x4 // Setup Phase Complete +#define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet + unsigned pktsts : 4; + unsigned fn : 4; + unsigned reserved : 7; + } b; +} device_grxsts_data_t; + +/** + * This union represents the bit fields in the Host Receive Status Read and + * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 + * element then read out the bits using the bit elements. + */ +typedef union host_grxsts_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned chnum : 4; + unsigned bcnt : 11; + unsigned dpid : 2; + + unsigned pktsts : 4; +#define DWC_GRXSTS_PKTSTS_IN 0x2 +#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP 0x3 +#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5 +#define DWC_GRXSTS_PKTSTS_CH_HALTED 0x7 + + unsigned reserved : 11; + } b; +} host_grxsts_data_t; + +/** + * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, + * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the d32 element then + * read out the bits using the bit elements. + */ +typedef union fifosize_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned startaddr : 16; + unsigned depth : 16; + } b; +} fifosize_data_t; + +/** + * This union represents the bit fields in the Non-Periodic Transmit + * FIFO/Queue Status Register (GNPTXSTS). Read the register into the + * d32 element then read out the bits using the bit + * elements. + */ +typedef union gnptxsts_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned nptxfspcavail : 16; + unsigned nptxqspcavail : 8; + /** Top of the Non-Periodic Transmit Request Queue + * - bit 24 - Terminate (Last entry for the selected + * channel/EP) + * - bits 26:25 - Token Type + * - 2'b00 - IN/OUT + * - 2'b01 - Zero Length OUT + * - 2'b10 - PING/Complete Split + * - 2'b11 - Channel Halt + * - bits 30:27 - Channel/EP Number + */ + unsigned nptxqtop_terminate : 1; + unsigned nptxqtop_token : 2; + unsigned nptxqtop_chnep : 4; + unsigned reserved : 1; + } b; +} gnptxsts_data_t; + +/** + * This union represents the bit fields in the Transmit + * FIFO Status Register (DTXFSTS). Read the register into the + * d32 element then read out the bits using the bit + * elements. + */ +typedef union dtxfsts_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned txfspcavail : 16; + unsigned reserved : 16; + } b; +} dtxfsts_data_t; + +/** + * This union represents the bit fields in the I2C Control Register + * (I2CCTL). Read the register into the d32 element then read out the + * bits using the bit elements. + */ +typedef union gi2cctl_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned rwdata : 8; + unsigned regaddr : 8; + unsigned addr : 7; + unsigned i2cen : 1; + unsigned ack : 1; + unsigned i2csuspctl : 1; + unsigned i2cdevaddr : 2; + unsigned reserved : 2; + unsigned rw : 1; + unsigned bsydne : 1; + } b; +} gi2cctl_data_t; + +/** + * This union represents the bit fields in the User HW Config1 + * Register. Read the register into the d32 element then read + * out the bits using the bit elements. + */ +typedef union hwcfg1_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned ep_dir0 : 2; + unsigned ep_dir1 : 2; + unsigned ep_dir2 : 2; + unsigned ep_dir3 : 2; + unsigned ep_dir4 : 2; + unsigned ep_dir5 : 2; + unsigned ep_dir6 : 2; + unsigned ep_dir7 : 2; + unsigned ep_dir8 : 2; + unsigned ep_dir9 : 2; + unsigned ep_dir10 : 2; + unsigned ep_dir11 : 2; + unsigned ep_dir12 : 2; + unsigned ep_dir13 : 2; + unsigned ep_dir14 : 2; + unsigned ep_dir15 : 2; + } b; +} hwcfg1_data_t; + +/** + * This union represents the bit fields in the User HW Config2 + * Register. Read the register into the d32 element then read + * out the bits using the bit elements. + */ +typedef union hwcfg2_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /* GHWCFG2 */ + unsigned op_mode : 3; +#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0 +#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1 +#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2 +#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3 +#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4 +#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5 +#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6 + + unsigned architecture : 2; + unsigned point2point : 1; + unsigned hs_phy_type : 2; +#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0 +#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1 +#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2 +#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3 + + unsigned fs_phy_type : 2; + unsigned num_dev_ep : 4; + unsigned num_host_chan : 4; + unsigned perio_ep_supported : 1; + unsigned dynamic_fifo : 1; + unsigned multi_proc_int : 1; + unsigned reserved21 : 1; + unsigned nonperio_tx_q_depth : 2; + unsigned host_perio_tx_q_depth : 2; + unsigned dev_token_q_depth : 5; + unsigned reserved31 : 1; + } b; +} hwcfg2_data_t; + +/** + * This union represents the bit fields in the User HW Config3 + * Register. Read the register into the d32 element then read + * out the bits using the bit elements. + */ +typedef union hwcfg3_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /* GHWCFG3 */ + unsigned xfer_size_cntr_width : 4; + unsigned packet_size_cntr_width : 3; + unsigned otg_func : 1; + unsigned i2c : 1; + unsigned vendor_ctrl_if : 1; + unsigned optional_features : 1; + unsigned synch_reset_type : 1; + unsigned ahb_phy_clock_synch : 1; + unsigned reserved15_13 : 3; + unsigned dfifo_depth : 16; + } b; +} hwcfg3_data_t; + +/** + * This union represents the bit fields in the User HW Config4 + * Register. Read the register into the d32 element then read + * out the bits using the bit elements. + */ +typedef union hwcfg4_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned num_dev_perio_in_ep : 4; + unsigned power_optimiz : 1; + unsigned min_ahb_freq : 9; + unsigned utmi_phy_data_width : 2; + unsigned num_dev_mode_ctrl_ep : 4; + unsigned iddig_filt_en : 1; + unsigned vbus_valid_filt_en : 1; + unsigned a_valid_filt_en : 1; + unsigned b_valid_filt_en : 1; + unsigned session_end_filt_en : 1; + unsigned ded_fifo_en : 1; + unsigned num_in_eps : 4; + unsigned desc_dma : 1; + unsigned desc_dma_dyn : 1; + } b; +} hwcfg4_data_t; + +//////////////////////////////////////////// +// Device Registers +/** + * Device Global Registers. Offsets 800h-BFFh + * + * The following structures define the size and relative field offsets + * for the Device Mode Registers. + * + * These registers are visible only in Device mode and must not be + * accessed in Host mode, as the results are unknown. + */ +typedef struct dwc_otg_dev_global_regs +{ + /** Device Configuration Register. Offset 800h */ + volatile uint32_t dcfg; + /** Device Control Register. Offset: 804h */ + volatile uint32_t dctl; + /** Device Status Register (Read Only). Offset: 808h */ + volatile uint32_t dsts; + /** Reserved. Offset: 80Ch */ + uint32_t unused; + /** Device IN Endpoint Common Interrupt Mask + * Register. Offset: 810h */ + volatile uint32_t diepmsk; + /** Device OUT Endpoint Common Interrupt Mask + * Register. Offset: 814h */ + volatile uint32_t doepmsk; + /** Device All Endpoints Interrupt Register. Offset: 818h */ + volatile uint32_t daint; + /** Device All Endpoints Interrupt Mask Register. Offset: + * 81Ch */ + volatile uint32_t daintmsk; + /** Device IN Token Queue Read Register-1 (Read Only). + * Offset: 820h */ + volatile uint32_t dtknqr1; + /** Device IN Token Queue Read Register-2 (Read Only). + * Offset: 824h */ + volatile uint32_t dtknqr2; + /** Device VBUS discharge Register. Offset: 828h */ + volatile uint32_t dvbusdis; + /** Device VBUS Pulse Register. Offset: 82Ch */ + volatile uint32_t dvbuspulse; + /** Device IN Token Queue Read Register-3 (Read Only). / + * Device Thresholding control register (Read/Write) + * Offset: 830h */ + volatile uint32_t dtknqr3_dthrctl; + /** Device IN Token Queue Read Register-4 (Read Only). / + * Device IN EPs empty Inr. Mask Register (Read/Write) + * Offset: 834h */ + volatile uint32_t dtknqr4_fifoemptymsk; + /** Device Each Endpoint Interrupt Register (Read Only). / + * Offset: 838h */ + volatile uint32_t deachint; + /** Device Each Endpoint Interrupt mask Register (Read/Write). / + * Offset: 83Ch */ + volatile uint32_t deachintmsk; + /** Device Each In Endpoint Interrupt mask Register (Read/Write). / + * Offset: 840h */ + volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS]; + /** Device Each Out Endpoint Interrupt mask Register (Read/Write). / + * Offset: 880h */ + volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS]; +} dwc_otg_device_global_regs_t; + +/** + * This union represents the bit fields in the Device Configuration + * Register. Read the register into the d32 member then + * set/clear the bits using the bit elements. Write the + * d32 member to the dcfg register. + */ +typedef union dcfg_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /** Device Speed */ + unsigned devspd : 2; + /** Non Zero Length Status OUT Handshake */ + unsigned nzstsouthshk : 1; +#define DWC_DCFG_SEND_STALL 1 + + unsigned reserved3 : 1; + /** Device Addresses */ + unsigned devaddr : 7; + /** Periodic Frame Interval */ + unsigned perfrint : 2; +#define DWC_DCFG_FRAME_INTERVAL_80 0 +#define DWC_DCFG_FRAME_INTERVAL_85 1 +#define DWC_DCFG_FRAME_INTERVAL_90 2 +#define DWC_DCFG_FRAME_INTERVAL_95 3 + + unsigned reserved13_17 : 5; + /** In Endpoint Mis-match count */ + unsigned epmscnt : 5; + /** Enable Descriptor DMA in Device mode */ + unsigned descdma : 1; + } b; +} dcfg_data_t; + +/** + * This union represents the bit fields in the Device Control + * Register. Read the register into the d32 member then + * set/clear the bits using the bit elements. + */ +typedef union dctl_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /** Remote Wakeup */ + unsigned rmtwkupsig : 1; + /** Soft Disconnect */ + unsigned sftdiscon : 1; + /** Global Non-Periodic IN NAK Status */ + unsigned gnpinnaksts : 1; + /** Global OUT NAK Status */ + unsigned goutnaksts : 1; + /** Test Control */ + unsigned tstctl : 3; + /** Set Global Non-Periodic IN NAK */ + unsigned sgnpinnak : 1; + /** Clear Global Non-Periodic IN NAK */ + unsigned cgnpinnak : 1; + /** Set Global OUT NAK */ + unsigned sgoutnak : 1; + /** Clear Global OUT NAK */ + unsigned cgoutnak : 1; + + /** Power-On Programming Done */ + unsigned pwronprgdone : 1; + /** Global Continue on BNA */ + unsigned gcontbna : 1; + /** Global Multi Count */ + unsigned gmc : 2; + /** Ignore Frame Number for ISOC EPs */ + unsigned ifrmnum : 1; + /** NAK on Babble */ + unsigned nakonbble : 1; + + unsigned reserved16_31 : 16; + } b; +} dctl_data_t; + +/** + * This union represents the bit fields in the Device Status + * Register. Read the register into the d32 member then + * set/clear the bits using the bit elements. + */ +typedef union dsts_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /** Suspend Status */ + unsigned suspsts : 1; + /** Enumerated Speed */ + unsigned enumspd : 2; +#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 +#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 +#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2 +#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3 + /** Erratic Error */ + unsigned errticerr : 1; + unsigned reserved4_7: 4; + /** Frame or Microframe Number of the received SOF */ + unsigned soffn : 14; + unsigned reserved22_31 : 10; + } b; +} dsts_data_t; + + +/** + * This union represents the bit fields in the Device IN EP Interrupt + * Register and the Device IN EP Common Mask Register. + * + * - Read the register into the d32 member then set/clear the + * bits using the bit elements. + */ +typedef union diepint_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /** Transfer complete mask */ + unsigned xfercompl : 1; + /** Endpoint disable mask */ + unsigned epdisabled : 1; + /** AHB Error mask */ + unsigned ahberr : 1; + /** TimeOUT Handshake mask (non-ISOC EPs) */ + unsigned timeout : 1; + /** IN Token received with TxF Empty mask */ + unsigned intktxfemp : 1; + /** IN Token Received with EP mismatch mask */ + unsigned intknepmis : 1; + /** IN Endpoint HAK Effective mask */ + unsigned inepnakeff : 1; + /** IN Endpoint HAK Effective mask */ + unsigned emptyintr : 1; + + unsigned txfifoundrn : 1; + + /** BNA Interrupt mask */ + unsigned bna : 1; + + unsigned reserved10_12 : 3; + /** BNA Interrupt mask */ + unsigned nak : 1; + + unsigned reserved14_31 : 18; + } b; +} diepint_data_t; + +/** + * This union represents the bit fields in the Device IN EP + * Common/Dedicated Interrupt Mask Register. + */ +typedef union diepint_data diepmsk_data_t; + +/** + * This union represents the bit fields in the Device OUT EP Interrupt + * Registerand Device OUT EP Common Interrupt Mask Register. + * + * - Read the register into the d32 member then set/clear the + * bits using the bit elements. + */ +typedef union doepint_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /** Transfer complete */ + unsigned xfercompl : 1; + /** Endpoint disable */ + unsigned epdisabled : 1; + /** AHB Error */ + unsigned ahberr : 1; + /** Setup Phase Done (contorl EPs) */ + unsigned setup : 1; + /** OUT Token Received when Endpoint Disabled */ + unsigned outtknepdis : 1; + + unsigned stsphsercvd : 1; + /** Back-to-Back SETUP Packets Received */ + unsigned back2backsetup : 1; + + unsigned reserved7 : 1; + /** OUT packet Error */ + unsigned outpkterr : 1; + /** BNA Interrupt */ + unsigned bna : 1; + + unsigned reserved10 : 1; + /** Packet Drop Status */ + unsigned pktdrpsts : 1; + /** Babble Interrupt */ + unsigned babble : 1; + /** NAK Interrupt */ + unsigned nak : 1; + /** NYET Interrupt */ + unsigned nyet : 1; + + unsigned reserved15_31 : 17; + } b; +} doepint_data_t; + +/** + * This union represents the bit fields in the Device OUT EP + * Common/Dedicated Interrupt Mask Register. + */ +typedef union doepint_data doepmsk_data_t; + +/** + * This union represents the bit fields in the Device All EP Interrupt + * and Mask Registers. + * - Read the register into the d32 member then set/clear the + * bits using the bit elements. + */ +typedef union daint_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /** IN Endpoint bits */ + unsigned in : 16; + /** OUT Endpoint bits */ + unsigned out : 16; + } ep; + struct + { + /** IN Endpoint bits */ + unsigned inep0 : 1; + unsigned inep1 : 1; + unsigned inep2 : 1; + unsigned inep3 : 1; + unsigned inep4 : 1; + unsigned inep5 : 1; + unsigned inep6 : 1; + unsigned inep7 : 1; + unsigned inep8 : 1; + unsigned inep9 : 1; + unsigned inep10 : 1; + unsigned inep11 : 1; + unsigned inep12 : 1; + unsigned inep13 : 1; + unsigned inep14 : 1; + unsigned inep15 : 1; + /** OUT Endpoint bits */ + unsigned outep0 : 1; + unsigned outep1 : 1; + unsigned outep2 : 1; + unsigned outep3 : 1; + unsigned outep4 : 1; + unsigned outep5 : 1; + unsigned outep6 : 1; + unsigned outep7 : 1; + unsigned outep8 : 1; + unsigned outep9 : 1; + unsigned outep10 : 1; + unsigned outep11 : 1; + unsigned outep12 : 1; + unsigned outep13 : 1; + unsigned outep14 : 1; + unsigned outep15 : 1; + } b; +} daint_data_t; + +/** + * This union represents the bit fields in the Device IN Token Queue + * Read Registers. + * - Read the register into the d32 member. + * - READ-ONLY Register + */ +typedef union dtknq1_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /** In Token Queue Write Pointer */ + unsigned intknwptr : 5; + /** Reserved */ + unsigned reserved05_06 : 2; + /** write pointer has wrapped. */ + unsigned wrap_bit : 1; + /** EP Numbers of IN Tokens 0 ... 4 */ + unsigned epnums0_5 : 24; + }b; +} dtknq1_data_t; + +/** + * This union represents Threshold control Register + * - Read and write the register into the d32 member. + * - READ-WRITABLE Register + */ +typedef union dthrctl_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /** non ISO Tx Thr. Enable */ + unsigned non_iso_thr_en : 1; + /** ISO Tx Thr. Enable */ + unsigned iso_thr_en : 1; + /** Tx Thr. Length */ + unsigned tx_thr_len : 9; + /** Reserved */ + unsigned reserved11_15 : 5; + /** Rx Thr. Enable */ + unsigned rx_thr_en : 1; + /** Rx Thr. Length */ + unsigned rx_thr_len : 9; + /** Reserved */ + unsigned reserved26_31 : 6; + }b; +} dthrctl_data_t; + + +/** + * Device Logical IN Endpoint-Specific Registers. Offsets + * 900h-AFCh + * + * There will be one set of endpoint registers per logical endpoint + * implemented. + * + * These registers are visible only in Device mode and must not be + * accessed in Host mode, as the results are unknown. + */ +typedef struct dwc_otg_dev_in_ep_regs +{ + /** Device IN Endpoint Control Register. Offset:900h + + * (ep_num * 20h) + 00h */ + volatile uint32_t diepctl; + /** Reserved. Offset:900h + (ep_num * 20h) + 04h */ + uint32_t reserved04; + /** Device IN Endpoint Interrupt Register. Offset:900h + + * (ep_num * 20h) + 08h */ + volatile uint32_t diepint; + /** Reserved. Offset:900h + (ep_num * 20h) + 0Ch */ + uint32_t reserved0C; + /** Device IN Endpoint Transfer Size + * Register. Offset:900h + (ep_num * 20h) + 10h */ + volatile uint32_t dieptsiz; + /** Device IN Endpoint DMA Address Register. Offset:900h + + * (ep_num * 20h) + 14h */ + volatile uint32_t diepdma; + /** Device IN Endpoint Transmit FIFO Status Register. Offset:900h + + * (ep_num * 20h) + 18h */ + volatile uint32_t dtxfsts; + /** Device IN Endpoint DMA Buffer Register. Offset:900h + + * (ep_num * 20h) + 1Ch */ + volatile uint32_t diepdmab; +} dwc_otg_dev_in_ep_regs_t; + +/** + * Device Logical OUT Endpoint-Specific Registers. Offsets: + * B00h-CFCh + * + * There will be one set of endpoint registers per logical endpoint + * implemented. + * + * These registers are visible only in Device mode and must not be + * accessed in Host mode, as the results are unknown. + */ +typedef struct dwc_otg_dev_out_ep_regs +{ + /** Device OUT Endpoint Control Register. Offset:B00h + + * (ep_num * 20h) + 00h */ + volatile uint32_t doepctl; + /** Device OUT Endpoint Frame number Register. Offset: + * B00h + (ep_num * 20h) + 04h */ + volatile uint32_t doepfn; + /** Device OUT Endpoint Interrupt Register. Offset:B00h + + * (ep_num * 20h) + 08h */ + volatile uint32_t doepint; + /** Reserved. Offset:B00h + (ep_num * 20h) + 0Ch */ + uint32_t reserved0C; + /** Device OUT Endpoint Transfer Size Register. Offset: + * B00h + (ep_num * 20h) + 10h */ + volatile uint32_t doeptsiz; + /** Device OUT Endpoint DMA Address Register. Offset:B00h + * + (ep_num * 20h) + 14h */ + volatile uint32_t doepdma; + /** Reserved. Offset:B00h + * (ep_num * 20h) + 1Ch */ + uint32_t unused; + /** Device OUT Endpoint DMA Buffer Register. Offset:B00h + * + (ep_num * 20h) + 1Ch */ + uint32_t doepdmab; +} dwc_otg_dev_out_ep_regs_t; + +/** + * This union represents the bit fields in the Device EP Control + * Register. Read the register into the d32 member then + * set/clear the bits using the bit elements. + */ +typedef union depctl_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /** Maximum Packet Size + * IN/OUT EPn + * IN/OUT EP0 - 2 bits + * 2'b00: 64 Bytes + * 2'b01: 32 + * 2'b10: 16 + * 2'b11: 8 */ + unsigned mps : 11; +#define DWC_DEP0CTL_MPS_64 0 +#define DWC_DEP0CTL_MPS_32 1 +#define DWC_DEP0CTL_MPS_16 2 +#define DWC_DEP0CTL_MPS_8 3 + + /** Next Endpoint + * IN EPn/IN EP0 + * OUT EPn/OUT EP0 - reserved */ + unsigned nextep : 4; + + /** USB Active Endpoint */ + unsigned usbactep : 1; + + /** Endpoint DPID (INTR/Bulk IN and OUT endpoints) + * This field contains the PID of the packet going to + * be received or transmitted on this endpoint. The + * application should program the PID of the first + * packet going to be received or transmitted on this + * endpoint , after the endpoint is + * activated. Application use the SetD1PID and + * SetD0PID fields of this register to program either + * D0 or D1 PID. + * + * The encoding for this field is + * - 0: D0 + * - 1: D1 + */ + unsigned dpid : 1; + + /** NAK Status */ + unsigned naksts : 1; + + /** Endpoint Type + * 2'b00: Control + * 2'b01: Isochronous + * 2'b10: Bulk + * 2'b11: Interrupt */ + unsigned eptype : 2; + + /** Snoop Mode + * OUT EPn/OUT EP0 + * IN EPn/IN EP0 - reserved */ + unsigned snp : 1; + + /** Stall Handshake */ + unsigned stall : 1; + + /** Tx Fifo Number + * IN EPn/IN EP0 + * OUT EPn/OUT EP0 - reserved */ + unsigned txfnum : 4; + + /** Clear NAK */ + unsigned cnak : 1; + /** Set NAK */ + unsigned snak : 1; + /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints) + * Writing to this field sets the Endpoint DPID (DPID) + * field in this register to DATA0. Set Even + * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints) + * Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) + * frame. + */ + unsigned setd0pid : 1; + /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints) + * Writing to this field sets the Endpoint DPID (DPID) + * field in this register to DATA1 Set Odd + * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints) + * Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to odd (micro) frame. + */ + unsigned setd1pid : 1; + + /** Endpoint Disable */ + unsigned epdis : 1; + /** Endpoint Enable */ + unsigned epena : 1; + } b; +} depctl_data_t; + +/** + * This union represents the bit fields in the Device EP Transfer + * Size Register. Read the register into the d32 member then + * set/clear the bits using the bit elements. + */ +typedef union deptsiz_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** Transfer size */ + unsigned xfersize : 19; + /** Packet Count */ + unsigned pktcnt : 10; + /** Multi Count - Periodic IN endpoints */ + unsigned mc : 2; + unsigned reserved : 1; + } b; +} deptsiz_data_t; + +/** + * This union represents the bit fields in the Device EP 0 Transfer + * Size Register. Read the register into the d32 member then + * set/clear the bits using the bit elements. + */ +typedef union deptsiz0_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** Transfer size */ + unsigned xfersize : 7; + /** Reserved */ + unsigned reserved7_18 : 12; + /** Packet Count */ + unsigned pktcnt : 1; + /** Reserved */ + unsigned reserved20_28 : 9; + /**Setup Packet Count (DOEPTSIZ0 Only) */ + unsigned supcnt : 2; + unsigned reserved31; + } b; +} deptsiz0_data_t; + + +///////////////////////////////////////////////// +// DMA Descriptor Specific Structures +// + +/** Buffer status definitions */ + +#define BS_HOST_READY 0x0 +#define BS_DMA_BUSY 0x1 +#define BS_DMA_DONE 0x2 +#define BS_HOST_BUSY 0x3 + +/** Receive/Transmit status definitions */ + +#define RTS_SUCCESS 0x0 +#define RTS_BUFFLUSH 0x1 +#define RTS_RESERVED 0x2 +#define RTS_BUFERR 0x3 + + +/** + * This union represents the bit fields in the DMA Descriptor + * status quadlet. Read the quadlet into the d32 member then + * set/clear the bits using the bit, b_iso_out and + * b_iso_in elements. + */ +typedef union desc_sts_data +{ + /** raw register data */ + uint32_t d32; + /** quadlet bits */ + struct { + /** Received number of bytes */ + unsigned bytes : 16; + + unsigned reserved16_22 : 7; + /** Multiple Transfer - only for OUT EPs */ + unsigned mtrf : 1; + /** Setup Packet received - only for OUT EPs */ + unsigned sr : 1; + /** Interrupt On Complete */ + unsigned ioc : 1; + /** Short Packet */ + unsigned sp : 1; + /** Last */ + unsigned l : 1; + /** Receive Status */ + unsigned sts : 2; + /** Buffer Status */ + unsigned bs : 2; + } b; + +#ifdef DWC_EN_ISOC + /** iso out quadlet bits */ + struct { + /** Received number of bytes */ + unsigned rxbytes : 11; + + unsigned reserved11 : 1; + /** Frame Number */ + unsigned framenum : 11; + /** Received ISO Data PID */ + unsigned pid : 2; + /** Interrupt On Complete */ + unsigned ioc : 1; + /** Short Packet */ + unsigned sp : 1; + /** Last */ + unsigned l : 1; + /** Receive Status */ + unsigned rxsts : 2; + /** Buffer Status */ + unsigned bs : 2; + } b_iso_out; + + /** iso in quadlet bits */ + struct { + /** Transmited number of bytes */ + unsigned txbytes : 12; + /** Frame Number */ + unsigned framenum : 11; + /** Transmited ISO Data PID */ + unsigned pid : 2; + /** Interrupt On Complete */ + unsigned ioc : 1; + /** Short Packet */ + unsigned sp : 1; + /** Last */ + unsigned l : 1; + /** Transmit Status */ + unsigned txsts : 2; + /** Buffer Status */ + unsigned bs : 2; + } b_iso_in; +#endif //DWC_EN_ISOC +} desc_sts_data_t; + +/** + * DMA Descriptor structure + * + * DMA Descriptor structure contains two quadlets: + * Status quadlet and Data buffer pointer. + */ +typedef struct dwc_otg_dma_desc +{ + /** DMA Descriptor status quadlet */ + desc_sts_data_t status; + /** DMA Descriptor data buffer pointer */ + dma_addr_t buf; +} dwc_otg_dma_desc_t; + +/** + * The dwc_otg_dev_if structure contains information needed to manage + * the DWC_otg controller acting in device mode. It represents the + * programming view of the device-specific aspects of the controller. + */ +typedef struct dwc_otg_dev_if +{ + /** Pointer to device Global registers. + * Device Global Registers starting at offset 800h + */ + dwc_otg_device_global_regs_t *dev_global_regs; +#define DWC_DEV_GLOBAL_REG_OFFSET 0x800 + + /** + * Device Logical IN Endpoint-Specific Registers 900h-AFCh + */ + dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS]; +#define DWC_DEV_IN_EP_REG_OFFSET 0x900 +#define DWC_EP_REG_OFFSET 0x20 + + /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */ + dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS]; +#define DWC_DEV_OUT_EP_REG_OFFSET 0xB00 + + /* Device configuration information*/ + uint8_t speed; /**< Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS */ + uint8_t num_in_eps; /**< Number # of Tx EP range: 0-15 exept ep0 */ + uint8_t num_out_eps; /**< Number # of Rx EP range: 0-15 exept ep 0*/ + + /** Size of periodic FIFOs (Bytes) */ + uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS]; + + /** Size of Tx FIFOs (Bytes) */ + uint16_t tx_fifo_size[MAX_TX_FIFOS]; + + /** Thresholding enable flags and length varaiables **/ + uint16_t rx_thr_en; + uint16_t iso_tx_thr_en; + uint16_t non_iso_tx_thr_en; + + uint16_t rx_thr_length; + uint16_t tx_thr_length; + + /** + * Pointers to the DMA Descriptors for EP0 Control + * transfers (virtual and physical) + */ + + /** 2 descriptors for SETUP packets */ + uint32_t dma_setup_desc_addr[2]; + dwc_otg_dma_desc_t* setup_desc_addr[2]; + + /** Pointer to Descriptor with latest SETUP packet */ + dwc_otg_dma_desc_t* psetup; + + /** Index of current SETUP handler descriptor */ + uint32_t setup_desc_index; + + /** Descriptor for Data In or Status In phases */ + uint32_t dma_in_desc_addr; + dwc_otg_dma_desc_t* in_desc_addr;; + + /** Descriptor for Data Out or Status Out phases */ + uint32_t dma_out_desc_addr; + dwc_otg_dma_desc_t* out_desc_addr; + +} dwc_otg_dev_if_t; + + + + +///////////////////////////////////////////////// +// Host Mode Register Structures +// +/** + * The Host Global Registers structure defines the size and relative + * field offsets for the Host Mode Global Registers. Host Global + * Registers offsets 400h-7FFh. +*/ +typedef struct dwc_otg_host_global_regs +{ + /** Host Configuration Register. Offset: 400h */ + volatile uint32_t hcfg; + /** Host Frame Interval Register. Offset: 404h */ + volatile uint32_t hfir; + /** Host Frame Number / Frame Remaining Register. Offset: 408h */ + volatile uint32_t hfnum; + /** Reserved. Offset: 40Ch */ + uint32_t reserved40C; + /** Host Periodic Transmit FIFO/ Queue Status Register. Offset: 410h */ + volatile uint32_t hptxsts; + /** Host All Channels Interrupt Register. Offset: 414h */ + volatile uint32_t haint; + /** Host All Channels Interrupt Mask Register. Offset: 418h */ + volatile uint32_t haintmsk; +} dwc_otg_host_global_regs_t; + +/** + * This union represents the bit fields in the Host Configuration Register. + * Read the register into the d32 member then set/clear the bits using + * the bit elements. Write the d32 member to the hcfg register. + */ +typedef union hcfg_data +{ + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct + { + /** FS/LS Phy Clock Select */ + unsigned fslspclksel : 2; +#define DWC_HCFG_30_60_MHZ 0 +#define DWC_HCFG_48_MHZ 1 +#define DWC_HCFG_6_MHZ 2 + + /** FS/LS Only Support */ + unsigned fslssupp : 1; + } b; +} hcfg_data_t; + +/** + * This union represents the bit fields in the Host Frame Remaing/Number + * Register. + */ +typedef union hfir_data +{ + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct + { + unsigned frint : 16; + unsigned reserved : 16; + } b; +} hfir_data_t; + +/** + * This union represents the bit fields in the Host Frame Remaing/Number + * Register. + */ +typedef union hfnum_data +{ + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct + { + unsigned frnum : 16; +#define DWC_HFNUM_MAX_FRNUM 0x3FFF + unsigned frrem : 16; + } b; +} hfnum_data_t; + +typedef union hptxsts_data +{ + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct + { + unsigned ptxfspcavail : 16; + unsigned ptxqspcavail : 8; + /** Top of the Periodic Transmit Request Queue + * - bit 24 - Terminate (last entry for the selected channel) + * - bits 26:25 - Token Type + * - 2'b00 - Zero length + * - 2'b01 - Ping + * - 2'b10 - Disable + * - bits 30:27 - Channel Number + * - bit 31 - Odd/even microframe + */ + unsigned ptxqtop_terminate : 1; + unsigned ptxqtop_token : 2; + unsigned ptxqtop_chnum : 4; + unsigned ptxqtop_odd : 1; + } b; +} hptxsts_data_t; + +/** + * This union represents the bit fields in the Host Port Control and Status + * Register. Read the register into the d32 member then set/clear the + * bits using the bit elements. Write the d32 member to the + * hprt0 register. + */ +typedef union hprt0_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned prtconnsts : 1; + unsigned prtconndet : 1; + unsigned prtena : 1; + unsigned prtenchng : 1; + unsigned prtovrcurract : 1; + unsigned prtovrcurrchng : 1; + unsigned prtres : 1; + unsigned prtsusp : 1; + unsigned prtrst : 1; + unsigned reserved9 : 1; + unsigned prtlnsts : 2; + unsigned prtpwr : 1; + unsigned prttstctl : 4; + unsigned prtspd : 2; +#define DWC_HPRT0_PRTSPD_HIGH_SPEED 0 +#define DWC_HPRT0_PRTSPD_FULL_SPEED 1 +#define DWC_HPRT0_PRTSPD_LOW_SPEED 2 + unsigned reserved19_31 : 13; + } b; +} hprt0_data_t; + +/** + * This union represents the bit fields in the Host All Interrupt + * Register. + */ +typedef union haint_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned ch0 : 1; + unsigned ch1 : 1; + unsigned ch2 : 1; + unsigned ch3 : 1; + unsigned ch4 : 1; + unsigned ch5 : 1; + unsigned ch6 : 1; + unsigned ch7 : 1; + unsigned ch8 : 1; + unsigned ch9 : 1; + unsigned ch10 : 1; + unsigned ch11 : 1; + unsigned ch12 : 1; + unsigned ch13 : 1; + unsigned ch14 : 1; + unsigned ch15 : 1; + unsigned reserved : 16; + } b; + + struct + { + unsigned chint : 16; + unsigned reserved : 16; + } b2; +} haint_data_t; + +/** + * This union represents the bit fields in the Host All Interrupt + * Register. + */ +typedef union haintmsk_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned ch0 : 1; + unsigned ch1 : 1; + unsigned ch2 : 1; + unsigned ch3 : 1; + unsigned ch4 : 1; + unsigned ch5 : 1; + unsigned ch6 : 1; + unsigned ch7 : 1; + unsigned ch8 : 1; + unsigned ch9 : 1; + unsigned ch10 : 1; + unsigned ch11 : 1; + unsigned ch12 : 1; + unsigned ch13 : 1; + unsigned ch14 : 1; + unsigned ch15 : 1; + unsigned reserved : 16; + } b; + + struct + { + unsigned chint : 16; + unsigned reserved : 16; + } b2; +} haintmsk_data_t; + +/** + * Host Channel Specific Registers. 500h-5FCh + */ +typedef struct dwc_otg_hc_regs +{ + /** Host Channel 0 Characteristic Register. Offset: 500h + (chan_num * 20h) + 00h */ + volatile uint32_t hcchar; + /** Host Channel 0 Split Control Register. Offset: 500h + (chan_num * 20h) + 04h */ + volatile uint32_t hcsplt; + /** Host Channel 0 Interrupt Register. Offset: 500h + (chan_num * 20h) + 08h */ + volatile uint32_t hcint; + /** Host Channel 0 Interrupt Mask Register. Offset: 500h + (chan_num * 20h) + 0Ch */ + volatile uint32_t hcintmsk; + /** Host Channel 0 Transfer Size Register. Offset: 500h + (chan_num * 20h) + 10h */ + volatile uint32_t hctsiz; + /** Host Channel 0 DMA Address Register. Offset: 500h + (chan_num * 20h) + 14h */ + volatile uint32_t hcdma; + /** Reserved. Offset: 500h + (chan_num * 20h) + 18h - 500h + (chan_num * 20h) + 1Ch */ + uint32_t reserved[2]; +} dwc_otg_hc_regs_t; + +/** + * This union represents the bit fields in the Host Channel Characteristics + * Register. Read the register into the d32 member then set/clear the + * bits using the bit elements. Write the d32 member to the + * hcchar register. + */ +typedef union hcchar_data +{ + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct + { + /** Maximum packet size in bytes */ + unsigned mps : 11; + + /** Endpoint number */ + unsigned epnum : 4; + + /** 0: OUT, 1: IN */ + unsigned epdir : 1; + + unsigned reserved : 1; + + /** 0: Full/high speed device, 1: Low speed device */ + unsigned lspddev : 1; + + /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */ + unsigned eptype : 2; + + /** Packets per frame for periodic transfers. 0 is reserved. */ + unsigned multicnt : 2; + + /** Device address */ + unsigned devaddr : 7; + + /** + * Frame to transmit periodic transaction. + * 0: even, 1: odd + */ + unsigned oddfrm : 1; + + /** Channel disable */ + unsigned chdis : 1; + + /** Channel enable */ + unsigned chen : 1; + } b; +} hcchar_data_t; + +typedef union hcsplt_data +{ + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct + { + /** Port Address */ + unsigned prtaddr : 7; + + /** Hub Address */ + unsigned hubaddr : 7; + + /** Transaction Position */ + unsigned xactpos : 2; +#define DWC_HCSPLIT_XACTPOS_MID 0 +#define DWC_HCSPLIT_XACTPOS_END 1 +#define DWC_HCSPLIT_XACTPOS_BEGIN 2 +#define DWC_HCSPLIT_XACTPOS_ALL 3 + + /** Do Complete Split */ + unsigned compsplt : 1; + + /** Reserved */ + unsigned reserved : 14; + + /** Split Enble */ + unsigned spltena : 1; + } b; +} hcsplt_data_t; + + +/** + * This union represents the bit fields in the Host All Interrupt + * Register. + */ +typedef union hcint_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /** Transfer Complete */ + unsigned xfercomp : 1; + /** Channel Halted */ + unsigned chhltd : 1; + /** AHB Error */ + unsigned ahberr : 1; + /** STALL Response Received */ + unsigned stall : 1; + /** NAK Response Received */ + unsigned nak : 1; + /** ACK Response Received */ + unsigned ack : 1; + /** NYET Response Received */ + unsigned nyet : 1; + /** Transaction Err */ + unsigned xacterr : 1; + /** Babble Error */ + unsigned bblerr : 1; + /** Frame Overrun */ + unsigned frmovrun : 1; + /** Data Toggle Error */ + unsigned datatglerr : 1; + /** Reserved */ + unsigned reserved : 21; + } b; +} hcint_data_t; + +/** + * This union represents the bit fields in the Host Channel Transfer Size + * Register. Read the register into the d32 member then set/clear the + * bits using the bit elements. Write the d32 member to the + * hcchar register. + */ +typedef union hctsiz_data +{ + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct + { + /** Total transfer size in bytes */ + unsigned xfersize : 19; + + /** Data packets to transfer */ + unsigned pktcnt : 10; + + /** + * Packet ID for next data packet + * 0: DATA0 + * 1: DATA2 + * 2: DATA1 + * 3: MDATA (non-Control), SETUP (Control) + */ + unsigned pid : 2; +#define DWC_HCTSIZ_DATA0 0 +#define DWC_HCTSIZ_DATA1 2 +#define DWC_HCTSIZ_DATA2 1 +#define DWC_HCTSIZ_MDATA 3 +#define DWC_HCTSIZ_SETUP 3 + + /** Do PING protocol when 1 */ + unsigned dopng : 1; + } b; +} hctsiz_data_t; + +/** + * This union represents the bit fields in the Host Channel Interrupt Mask + * Register. Read the register into the d32 member then set/clear the + * bits using the bit elements. Write the d32 member to the + * hcintmsk register. + */ +typedef union hcintmsk_data +{ + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct + { + unsigned xfercompl : 1; + unsigned chhltd : 1; + unsigned ahberr : 1; + unsigned stall : 1; + unsigned nak : 1; + unsigned ack : 1; + unsigned nyet : 1; + unsigned xacterr : 1; + unsigned bblerr : 1; + unsigned frmovrun : 1; + unsigned datatglerr : 1; + unsigned reserved : 21; + } b; +} hcintmsk_data_t; + +/** OTG Host Interface Structure. + * + * The OTG Host Interface Structure structure contains information + * needed to manage the DWC_otg controller acting in host mode. It + * represents the programming view of the host-specific aspects of the + * controller. + */ +typedef struct dwc_otg_host_if +{ + /** Host Global Registers starting at offset 400h.*/ + dwc_otg_host_global_regs_t *host_global_regs; +#define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400 + + /** Host Port 0 Control and Status Register */ + volatile uint32_t *hprt0; +#define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440 + + + /** Host Channel Specific Registers at offsets 500h-5FCh. */ + dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS]; +#define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500 +#define DWC_OTG_CHAN_REGS_OFFSET 0x20 + + + /* Host configuration information */ + /** Number of Host Channels (range: 1-16) */ + uint8_t num_host_channels; + /** Periodic EPs supported (0: no, 1: yes) */ + uint8_t perio_eps_supported; + /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */ + uint16_t perio_tx_fifo_size; + +} dwc_otg_host_if_t; + + +/** + * This union represents the bit fields in the Power and Clock Gating Control + * Register. Read the register into the d32 member then set/clear the + * bits using the bit elements. + */ +typedef union pcgcctl_data +{ + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct + { + /** Stop Pclk */ + unsigned stoppclk : 1; + /** Gate Hclk */ + unsigned gatehclk : 1; + /** Power Clamp */ + unsigned pwrclmp : 1; + /** Reset Power Down Modules */ + unsigned rstpdwnmodule : 1; + /** PHY Suspended */ + unsigned physuspended : 1; + + unsigned reserved : 27; + } b; +} pcgcctl_data_t; + + +#endif diff --git a/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/linux/dwc_otg_plat.h b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/linux/dwc_otg_plat.h new file mode 100644 index 0000000000..618151b42a --- /dev/null +++ b/target/linux/ramips/files-3.7/drivers/usb/dwc_otg/linux/dwc_otg_plat.h @@ -0,0 +1,260 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/platform/dwc_otg_plat.h $ + * $Revision: 1.2 $ + * $Date: 2008-11-21 05:39:16 $ + * $Change: 1064915 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and + * redistribute this Software in source and binary forms, with or without + * modification, provided that redistributions of source code must retain this + * notice. You may not view, use, disclose, copy or distribute this file or + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * ========================================================================== */ + +#if !defined(__DWC_OTG_PLAT_H__) +#define __DWC_OTG_PLAT_H__ + +#include +#include +#include +#include +#include + +/** + * @file + * + * This file contains the Platform Specific constants, interfaces + * (functions and macros) for Linux. + * + */ +//#if !defined(__LINUX_ARM_ARCH__) +//#error "The contents of this file is Linux specific!!!" +//#endif + +/** + * Reads the content of a register. + * + * @param reg address of register to read. + * @return contents of the register. + * + + * Usage:
+ * uint32_t dev_ctl = dwc_read_reg32(&dev_regs->dctl); + */ +static __inline__ uint32_t dwc_read_reg32( volatile uint32_t *reg) +{ + return readl(reg); +}; + +/** + * Writes a register with a 32 bit value. + * + * @param reg address of register to read. + * @param value to write to _reg. + * + * Usage:
+ * dwc_write_reg32(&dev_regs->dctl, 0); + */ +static __inline__ void dwc_write_reg32( volatile uint32_t *reg, const uint32_t value) +{ + writel( value, reg ); +}; + +/** + * This function modifies bit values in a register. Using the + * algorithm: (reg_contents & ~clear_mask) | set_mask. + * + * @param reg address of register to read. + * @param clear_mask bit mask to be cleared. + * @param set_mask bit mask to be set. + * + * Usage:
+ * // Clear the SOF Interrupt Mask bit and
+ * // set the OTG Interrupt mask bit, leaving all others as they were. + * dwc_modify_reg32(&dev_regs->gintmsk, DWC_SOF_INT, DWC_OTG_INT); + */ +static __inline__ + void dwc_modify_reg32( volatile uint32_t *reg, const uint32_t clear_mask, const uint32_t set_mask) +{ + writel( (readl(reg) & ~clear_mask) | set_mask, reg ); +}; + + +/** + * Wrapper for the OS micro-second delay function. + * @param[in] usecs Microseconds of delay + */ +static __inline__ void UDELAY( const uint32_t usecs ) +{ + udelay( usecs ); +} + +/** + * Wrapper for the OS milli-second delay function. + * @param[in] msecs milliseconds of delay + */ +static __inline__ void MDELAY( const uint32_t msecs ) +{ + mdelay( msecs ); +} + +/** + * Wrapper for the Linux spin_lock. On the ARM (Integrator) + * spin_lock() is a nop. + * + * @param lock Pointer to the spinlock. + */ +static __inline__ void SPIN_LOCK( spinlock_t *lock ) +{ + spin_lock(lock); +} + +/** + * Wrapper for the Linux spin_unlock. On the ARM (Integrator) + * spin_lock() is a nop. + * + * @param lock Pointer to the spinlock. + */ +static __inline__ void SPIN_UNLOCK( spinlock_t *lock ) +{ + spin_unlock(lock); +} + +/** + * Wrapper (macro) for the Linux spin_lock_irqsave. On the ARM + * (Integrator) spin_lock() is a nop. + * + * @param l Pointer to the spinlock. + * @param f unsigned long for irq flags storage. + */ +#define SPIN_LOCK_IRQSAVE( l, f ) spin_lock_irqsave(l,f); + +/** + * Wrapper (macro) for the Linux spin_unlock_irqrestore. On the ARM + * (Integrator) spin_lock() is a nop. + * + * @param l Pointer to the spinlock. + * @param f unsigned long for irq flags storage. + */ +#define SPIN_UNLOCK_IRQRESTORE( l,f ) spin_unlock_irqrestore(l,f); + +/* + * Debugging support vanishes in non-debug builds. + */ + + +/** + * The Debug Level bit-mask variable. + */ +extern uint32_t g_dbg_lvl; +/** + * Set the Debug Level variable. + */ +static inline uint32_t SET_DEBUG_LEVEL( const uint32_t new ) +{ + uint32_t old = g_dbg_lvl; + g_dbg_lvl = new; + return old; +} + +/** When debug level has the DBG_CIL bit set, display CIL Debug messages. */ +#define DBG_CIL (0x2) +/** When debug level has the DBG_CILV bit set, display CIL Verbose debug + * messages */ +#define DBG_CILV (0x20) +/** When debug level has the DBG_PCD bit set, display PCD (Device) debug + * messages */ +#define DBG_PCD (0x4) +/** When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug + * messages */ +#define DBG_PCDV (0x40) +/** When debug level has the DBG_HCD bit set, display Host debug messages */ +#define DBG_HCD (0x8) +/** When debug level has the DBG_HCDV bit set, display Verbose Host debug + * messages */ +#define DBG_HCDV (0x80) +/** When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host + * mode. */ +#define DBG_HCD_URB (0x800) + +/** When debug level has any bit set, display debug messages */ +#define DBG_ANY (0xFF) + +/** All debug messages off */ +#define DBG_OFF 0 + +/** Prefix string for DWC_DEBUG print macros. */ +#define USB_DWC "dwc_otg: " + +/** + * Print a debug message when the Global debug level variable contains + * the bit defined in lvl. + * + * @param[in] lvl - Debug level, use one of the DBG_ constants above. + * @param[in] x - like printf + * + * Example:

+ * + * DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr); + * + *
+ * results in:
+ * + * usb-DWC_otg: dwc_otg_cil_init(ca867000) + * + */ +#ifdef DEBUG + +# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)printk( KERN_DEBUG USB_DWC x ); }while(0) +# define DWC_DEBUGP(x...) DWC_DEBUGPL(DBG_ANY, x ) + +# define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl) + +#else + +# define DWC_DEBUGPL(lvl, x...) do{}while(0) +# define DWC_DEBUGP(x...) + +# define CHK_DEBUG_LEVEL(level) (0) + +#endif /*DEBUG*/ + +/** + * Print an Error message. + */ +#define DWC_ERROR(x...) printk( KERN_ERR USB_DWC x ) +/** + * Print a Warning message. + */ +#define DWC_WARN(x...) printk( KERN_WARNING USB_DWC x ) +/** + * Print a notice (normal but significant message). + */ +#define DWC_NOTICE(x...) printk( KERN_NOTICE USB_DWC x ) +/** + * Basic message printing. + */ +#define DWC_PRINT(x...) printk( KERN_INFO USB_DWC x ) + +#endif + diff --git a/target/linux/ramips/files-3.7/drivers/watchdog/ramips_wdt.c b/target/linux/ramips/files-3.7/drivers/watchdog/ramips_wdt.c new file mode 100644 index 0000000000..fa7e9e85ef --- /dev/null +++ b/target/linux/ramips/files-3.7/drivers/watchdog/ramips_wdt.c @@ -0,0 +1,355 @@ +/* + * Ralink RT288X/RT305X built-in hardware watchdog timer + * + * Copyright (C) 2011 Gabor Juhos + * + * This driver was based on: drivers/watchdog/ixp4xx_wdt.c + * Author: Deepak Saxena + * Copyright 2004 (c) MontaVista, Software, Inc. + * + * which again was based on sa1100 driver, + * Copyright (C) 2000 Oleg Drokin + * + * parts of the driver are based on Ralink's 2.6.21 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRIVER_NAME "ramips-wdt" + +#define RAMIPS_WDT_TIMEOUT 0 /* seconds */ +#define RAMIPS_WDT_PRESCALE 65536 + +#define TIMER_REG_TMRSTAT 0x00 +#define TIMER_REG_TMR1LOAD 0x20 +#define TIMER_REG_TMR1CTL 0x28 + +#define TMRSTAT_TMR1RST BIT(5) + +#define TMR1CTL_ENABLE BIT(7) +#define TMR1CTL_MODE_SHIFT 4 +#define TMR1CTL_MODE_MASK 0x3 +#define TMR1CTL_MODE_FREE_RUNNING 0x0 +#define TMR1CTL_MODE_PERIODIC 0x1 +#define TMR1CTL_MODE_TIMEOUT 0x2 +#define TMR1CTL_MODE_WDT 0x3 +#define TMR1CTL_PRESCALE_MASK 0xf +#define TMR1CTL_PRESCALE_65536 0xf + +static int nowayout = WATCHDOG_NOWAYOUT; +module_param(nowayout, int, 0); +MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started " + "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); + +static int ramips_wdt_timeout = RAMIPS_WDT_TIMEOUT; +module_param_named(timeout, ramips_wdt_timeout, int, 0); +MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds, 0 means use maximum " + "(default=" __MODULE_STRING(RAMIPS_WDT_TIMEOUT) "s)"); + +static unsigned long ramips_wdt_flags; + +#define WDT_FLAGS_BUSY 0 +#define WDT_FLAGS_EXPECT_CLOSE 1 + +static struct clk *ramips_wdt_clk; +static unsigned long ramips_wdt_freq; +static int ramips_wdt_max_timeout; +static void __iomem *ramips_wdt_base; + +static inline void ramips_wdt_wr(unsigned reg, u32 val) +{ + __raw_writel(val, ramips_wdt_base + reg); +} + +static inline u32 ramips_wdt_rr(unsigned reg) +{ + return __raw_readl(ramips_wdt_base + reg); +} + +static inline void ramips_wdt_keepalive(void) +{ + ramips_wdt_wr(TIMER_REG_TMR1LOAD, ramips_wdt_timeout * ramips_wdt_freq); +} + +static inline void ramips_wdt_enable(void) +{ + u32 t; + + ramips_wdt_keepalive(); + + t = ramips_wdt_rr(TIMER_REG_TMR1CTL); + t |= TMR1CTL_ENABLE; + ramips_wdt_wr(TIMER_REG_TMR1CTL, t); +} + +static inline void ramips_wdt_disable(void) +{ + u32 t; + + ramips_wdt_keepalive(); + + t = ramips_wdt_rr(TIMER_REG_TMR1CTL); + t &= ~TMR1CTL_ENABLE; + ramips_wdt_wr(TIMER_REG_TMR1CTL, t); +} + +static int ramips_wdt_set_timeout(int val) +{ + if (val < 1 || val > ramips_wdt_max_timeout) { + pr_warn(DRIVER_NAME + ": timeout value %d must be 0 < timeout <= %d, using %d\n", + val, ramips_wdt_max_timeout, ramips_wdt_timeout); + return -EINVAL; + } + + ramips_wdt_timeout = val; + ramips_wdt_keepalive(); + + return 0; +} + +static int ramips_wdt_open(struct inode *inode, struct file *file) +{ + u32 t; + + if (test_and_set_bit(WDT_FLAGS_BUSY, &ramips_wdt_flags)) + return -EBUSY; + + clear_bit(WDT_FLAGS_EXPECT_CLOSE, &ramips_wdt_flags); + + t = ramips_wdt_rr(TIMER_REG_TMR1CTL); + t &= ~(TMR1CTL_MODE_MASK << TMR1CTL_MODE_SHIFT | + TMR1CTL_PRESCALE_MASK); + t |= (TMR1CTL_MODE_WDT << TMR1CTL_MODE_SHIFT | + TMR1CTL_PRESCALE_65536); + ramips_wdt_wr(TIMER_REG_TMR1CTL, t); + + ramips_wdt_enable(); + + return nonseekable_open(inode, file); +} + +static int ramips_wdt_release(struct inode *inode, struct file *file) +{ + if (test_bit(WDT_FLAGS_EXPECT_CLOSE, &ramips_wdt_flags)) + ramips_wdt_disable(); + else { + pr_crit(DRIVER_NAME ": device closed unexpectedly, " + "watchdog timer will not stop!\n"); + ramips_wdt_keepalive(); + } + + clear_bit(WDT_FLAGS_BUSY, &ramips_wdt_flags); + clear_bit(WDT_FLAGS_EXPECT_CLOSE, &ramips_wdt_flags); + + return 0; +} + +static ssize_t ramips_wdt_write(struct file *file, const char *data, + size_t len, loff_t *ppos) +{ + if (len) { + if (!nowayout) { + size_t i; + + clear_bit(WDT_FLAGS_EXPECT_CLOSE, &ramips_wdt_flags); + + for (i = 0; i != len; i++) { + char c; + + if (get_user(c, data + i)) + return -EFAULT; + + if (c == 'V') + set_bit(WDT_FLAGS_EXPECT_CLOSE, + &ramips_wdt_flags); + } + } + + ramips_wdt_keepalive(); + } + + return len; +} + +static const struct watchdog_info ramips_wdt_info = { + .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | + WDIOF_MAGICCLOSE, + .firmware_version = 0, + .identity = "RAMIPS watchdog", +}; + +static long ramips_wdt_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + void __user *argp = (void __user *)arg; + int __user *p = argp; + int err; + int t; + + switch (cmd) { + case WDIOC_GETSUPPORT: + err = copy_to_user(argp, &ramips_wdt_info, + sizeof(ramips_wdt_info)) ? -EFAULT : 0; + break; + + case WDIOC_GETSTATUS: + err = put_user(0, p); + break; + + case WDIOC_KEEPALIVE: + ramips_wdt_keepalive(); + err = 0; + break; + + case WDIOC_SETTIMEOUT: + err = get_user(t, p); + if (err) + break; + + err = ramips_wdt_set_timeout(t); + if (err) + break; + + /* fallthrough */ + case WDIOC_GETTIMEOUT: + err = put_user(ramips_wdt_timeout, p); + break; + + default: + err = -ENOTTY; + break; + } + + return err; +} + +static const struct file_operations ramips_wdt_fops = { + .owner = THIS_MODULE, + .llseek = no_llseek, + .write = ramips_wdt_write, + .unlocked_ioctl = ramips_wdt_ioctl, + .open = ramips_wdt_open, + .release = ramips_wdt_release, +}; + +static struct miscdevice ramips_wdt_miscdev = { + .minor = WATCHDOG_MINOR, + .name = "watchdog", + .fops = &ramips_wdt_fops, +}; + +static int ramips_wdt_probe(struct platform_device *pdev) +{ + struct resource *res; + int err; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "no memory resource found\n"); + return -EINVAL; + } + + ramips_wdt_base = ioremap(res->start, resource_size(res)); + if (!ramips_wdt_base) + return -ENOMEM; + + ramips_wdt_clk = clk_get(&pdev->dev, "wdt"); + if (IS_ERR(ramips_wdt_clk)) { + err = PTR_ERR(ramips_wdt_clk); + goto err_unmap; + } + + err = clk_enable(ramips_wdt_clk); + if (err) + goto err_clk_put; + + ramips_wdt_freq = clk_get_rate(ramips_wdt_clk) / RAMIPS_WDT_PRESCALE; + if (!ramips_wdt_freq) { + err = -EINVAL; + goto err_clk_disable; + } + + ramips_wdt_max_timeout = (0xfffful / ramips_wdt_freq); + if (ramips_wdt_timeout < 1 || + ramips_wdt_timeout > ramips_wdt_max_timeout) { + ramips_wdt_timeout = ramips_wdt_max_timeout; + dev_info(&pdev->dev, + "timeout value must be 0 < timeout <= %d, using %d\n", + ramips_wdt_max_timeout, ramips_wdt_timeout); + } + + err = misc_register(&ramips_wdt_miscdev); + if (err) { + dev_err(&pdev->dev, + "unable to register misc device, err=%d\n", err); + goto err_clk_disable; + } + + return 0; + +err_clk_disable: + clk_disable(ramips_wdt_clk); +err_clk_put: + clk_put(ramips_wdt_clk); +err_unmap: + iounmap(ramips_wdt_base); + return err; +} + +static int ramips_wdt_remove(struct platform_device *pdev) +{ + misc_deregister(&ramips_wdt_miscdev); + clk_disable(ramips_wdt_clk); + clk_put(ramips_wdt_clk); + iounmap(ramips_wdt_base); + return 0; +} + +static void ramips_wdt_shutdown(struct platform_device *pdev) +{ + ramips_wdt_disable(); +} + +static struct platform_driver ramips_wdt_driver = { + .remove = ramips_wdt_remove, + .shutdown = ramips_wdt_shutdown, + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init ramips_wdt_init(void) +{ + return platform_driver_probe(&ramips_wdt_driver, ramips_wdt_probe); +} +module_init(ramips_wdt_init); + +static void __exit ramips_wdt_exit(void) +{ + platform_driver_unregister(&ramips_wdt_driver); +} +module_exit(ramips_wdt_exit); + +MODULE_DESCRIPTION("Ralink RT288X/RT305X hardware watchdog driver"); +MODULE_AUTHOR("Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef __ASM_MACH_RALINK_COMMON_H -#define __ASM_MACH_RALINK_COMMON_H - -#define RAMIPS_SYS_TYPE_LEN 64 -extern unsigned char ramips_sys_type[RAMIPS_SYS_TYPE_LEN]; -extern unsigned long ramips_mem_base; -extern unsigned long ramips_mem_size_min; -extern unsigned long ramips_mem_size_max; -extern unsigned long (*ramips_get_mem_size)(void); - -void ramips_intc_irq_init(unsigned intc_base, unsigned irq, unsigned irq_base); -u32 ramips_intc_get_status(void); - -void ramips_soc_prom_init(void); -void ramips_soc_setup(void); -void ramips_early_serial_setup(int line, unsigned base, unsigned freq, - unsigned irq); - -#endif /* __ASM_MACH_RALINK_COMMON_H */ diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/dev-gpio-buttons.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/dev-gpio-buttons.h deleted file mode 100644 index 8eb5e16906..0000000000 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/dev-gpio-buttons.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Ralink SoC GPIO button support - * - * Copyright (C) 2010-2011 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef __ASM_MACH_RALINK_DEV_GPIO_BUTTONS_H -#define __ASM_MACH_RALINK_DEV_GPIO_BUTTONS_H - -#include -#include - -#ifdef CONFIG_RALINK_DEV_GPIO_BUTTONS -void -ramips_register_gpio_buttons(int id, unsigned poll_interval, unsigned nbuttons, - struct gpio_keys_button *buttons); -#else -static inline void -ramips_register_gpio_buttons(int id, unsigned poll_interval, unsigned nbuttons, - struct gpio_keys_button *buttons) -{ -} -#endif - -#endif /* __ASM_MACH_RALINK_DEV_GPIO_BUTTONS_H */ diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/dev-gpio-leds.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/dev-gpio-leds.h deleted file mode 100644 index 24233abde6..0000000000 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/dev-gpio-leds.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Ralink SoC GPIO LED device support - * - * Copyright (C) 2009-2011 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef __ASM_MACH_RALINK_DEV_GPIO_LEDS_H -#define __ASM_MACH_RALINK_DEV_GPIO_LEDS_H - -#include - -#ifdef CONFIG_RALINK_DEV_GPIO_LEDS -void ramips_register_gpio_leds(int id, unsigned num_leds, - struct gpio_led *leds); -#else -static inline void ramips_register_gpio_leds(int id, unsigned num_leds, - struct gpio_led *leds) -{ -} -#endif - -#endif /* __ASM_MACH_RALINK_DEV_GPIO_LEDS_H */ diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/gpio.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/gpio.h deleted file mode 100644 index f68ee16856..0000000000 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/gpio.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Ralink SoC GPIO API support - * - * Copyright (C) 2008-2009 Gabor Juhos - * Copyright (C) 2008 Imre Kaloz - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - */ - -#ifndef __ASM_MACH_RALINK_GPIO_H -#define __ASM_MACH_RALINK_GPIO_H - -#define ARCH_NR_GPIOS 128 -#include - -#define gpio_get_value __gpio_get_value -#define gpio_set_value __gpio_set_value -#define gpio_cansleep __gpio_cansleep -#define gpio_to_irq __gpio_to_irq - -#endif /* __ASM_MACH_RALINK_GPIO_H */ diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/machine.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/machine.h deleted file mode 100644 index 200f737f71..0000000000 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/machine.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Ralink machine types - * - * Copyright (C) 2010 Joonas Lahtinen - * Copyright (C) 2009 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include - -enum ramips_mach_type { - RAMIPS_MACH_GENERIC, - /* RT2880 based machines */ - RAMIPS_MACH_F5D8235_V1, /* Belkin F5D8235 v1 */ - RAMIPS_MACH_BR6524N, /* Edimax BR6524N */ - RAMIPS_MACH_RT_N15, /* Asus RT-N15 */ - RAMIPS_MACH_V11ST_FE, /* Ralink V11ST-FE */ - RAMIPS_MACH_WLI_TX4_AG300N, /* Buffalo WLI-TX4-AG300N */ - RAMIPS_MACH_WZR_AGL300NH, /* Buffalo WZR-AGL300NH */ - - /* RT3050 based machines */ - RAMIPS_MACH_3G_6200N, /* Edimax 3G-6200N */ - RAMIPS_MACH_ALL0256N, /* Allnet ALL0256N */ - RAMIPS_MACH_CARAMBOLA, /* 8devices Carambola */ - RAMIPS_MACH_DIR_300_B1, /* D-Link DIR-300 B1 */ - RAMIPS_MACH_DIR_600_B1, /* D-Link DIR-600 B1 */ - RAMIPS_MACH_DIR_600_B2, /* D-Link DIR-600 B2 */ - RAMIPS_MACH_DIR_615_D, /* D-Link DIR-615 D */ - RAMIPS_MACH_DIR_620_A1, /* D-Link DIR-620 A1 */ - RAMIPS_MACH_RT_G32_B1, /* Asus RT-G32 B1 */ - RAMIPS_MACH_RT_N10_PLUS, /* Asus RT-N10+ */ - RAMIPS_MACH_NW718, /* Netcore NW718 */ - RAMIPS_MACH_WL_330N, /* Asus WL-330N */ - RAMIPS_MACH_WL_330N3G, /* Asus WL-330N3G */ - - /* RT3052 based machines */ - RAMIPS_MACH_3G300M, /* Tenda 3G300M */ - RAMIPS_MACH_ALL0239_3G, /* ALL0239-3G */ - RAMIPS_MACH_ARGUS_ATP52B, /* Argus ATP-52B */ - RAMIPS_MACH_BC2, /* NexAira BC2 */ - RAMIPS_MACH_BR6425, /* Edimax BR-6425 */ - RAMIPS_MACH_BROADWAY, /* Hauppauge Broadway */ - RAMIPS_MACH_DAP_1350, /* D-Link DAP-1350 */ - RAMIPS_MACH_ESR_9753, /* Senao / EnGenius ESR-9753*/ - RAMIPS_MACH_F5D8235_V2, /* Belkin F5D8235 v2 */ - RAMIPS_MACH_FONERA20N, /* La Fonera 2.0N */ - RAMIPS_MACH_RT_N13U, /* ASUS RT-N13U */ - RAMIPS_MACH_FREESTATION5, /* ARC Freestation5 */ - RAMIPS_MACH_HW550_3G, /* Aztech HW550-3G */ - RAMIPS_MACH_MOFI3500_3GN, /* MoFi Network MOFI3500-3GN */ - RAMIPS_MACH_NBG_419N, /* ZyXEL NBG-419N */ - RAMIPS_MACH_OMNI_EMB, /* Omnima MiniEMBWiFi */ - RAMIPS_MACH_PSR_680W, /* Petatel PSR-680W Wireless 3G Router*/ - RAMIPS_MACH_PWH2004, /* Prolink 2004H / Abocom 5205 */ - RAMIPS_MACH_SL_R7205, /* Skylink SL-R7205 Wireless 3G Router*/ - RAMIPS_MACH_V22RW_2X2, /* Ralink AP-RT3052-V22RW-2X2 */ - RAMIPS_MACH_W306R_V20, /* Tenda W306R_V20 */ - RAMIPS_MACH_W502U, /* ALFA Networks W502U */ - RAMIPS_MACH_WCR150GN, /* Sparklan WCR-150GN */ - RAMIPS_MACH_WHR_G300N, /* Buffalo WHR-G300N */ - RAMIPS_MACH_WL341V3, /* Sitecom WL-341 v3 */ - RAMIPS_MACH_WL351, /* Sitecom WL-351 v1 002 */ - RAMIPS_MACH_WR512_3GN, /* SH-WR512NU/WS-WR512N1-like 3GN*/ - RAMIPS_MACH_WR6202, /* Accton WR6202 */ - RAMIPS_MACH_MZKW300NH2, /* Planex MZK-W300NH2 Router */ - RAMIPS_MACH_XDXRN502J, /* unknown XDX-RN502J */ - RAMIPS_MACH_UR_326N4G, /* UPVEL ROUTER */ - RAMIPS_MACH_UR_336UN, /* UPVEL ROUTER */ - - /* RT3352 based machines */ - RAMIPS_MACH_ALL5002, /* Allnet ALL5002 */ - RAMIPS_MACH_DIR_615_H1, - - /* RT3662 based machines */ - RAMIPS_MACH_DIR_645, /* D-Link DIR-645 */ - RAMIPS_MACH_OMNI_EMB_HPM, /* Omnima EMB HPM */ - RAMIPS_MACH_RT_N56U, /* Asus RT-N56U */ - - /* RT3883 based machines */ - RAMIPS_MACH_TEW_691GR, /* TRENDnet TEW-691GR */ - RAMIPS_MACH_TEW_692GR, /* TRENDnet TEW-692GR */ - - /* RT5350 based machines */ - RAMIPS_MACH_AIR3GII, /* AirLive Air3GII */ -}; diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/ramips_eth_platform.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/ramips_eth_platform.h deleted file mode 100644 index 57c0556b93..0000000000 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/ramips_eth_platform.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * based on Ralink SDK3.3 - * Copyright (C) 2009 John Crispin - */ - -#ifndef _RAMIPS_ETH_PLATFORM_H -#define _RAMIPS_ETH_PLATFORM_H - -#include - -struct ramips_eth_platform_data -{ - unsigned char mac[6]; - void (*reset_fe)(void); - int min_pkt_len; - unsigned long sys_freq; - - int speed; - int duplex; - int tx_fc; - int rx_fc; - - u32 phy_mask; - phy_interface_t phy_if_mode; -}; - -#endif /* _RAMIPS_ETH_PLATFORM_H */ - diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/ramips_gpio.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/ramips_gpio.h deleted file mode 100644 index 32fc7a7402..0000000000 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/ramips_gpio.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Ralink SoC specific GPIO support - * - * Copyright (C) 2011 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef _RAMIPS_GPIO_H -#define _RAMIPS_GPIO_H - -#include -#include - -enum ramips_gpio_reg { - RAMIPS_GPIO_REG_INT = 0, /* Interrupt status */ - RAMIPS_GPIO_REG_EDGE, - RAMIPS_GPIO_REG_RENA, - RAMIPS_GPIO_REG_FENA, - RAMIPS_GPIO_REG_DATA, - RAMIPS_GPIO_REG_DIR, /* Direction, 0:in, 1: out */ - RAMIPS_GPIO_REG_POL, /* Polarity, 0: normal, 1: invert */ - RAMIPS_GPIO_REG_SET, - RAMIPS_GPIO_REG_RESET, - RAMIPS_GPIO_REG_TOGGLE, - RAMIPS_GPIO_REG_MAX -}; - -struct ramips_gpio_chip { - struct gpio_chip chip; - unsigned long map_base; - unsigned long map_size; - u8 regs[RAMIPS_GPIO_REG_MAX]; - - spinlock_t lock; - void __iomem *regs_base; -}; - -struct ramips_gpio_data { - unsigned int num_chips; - struct ramips_gpio_chip *chips; -}; - -int ramips_gpio_init(struct ramips_gpio_data *data); - -#endif /* _RAMIPS_GPIO_H */ diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/ramips_nand_platform.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/ramips_nand_platform.h deleted file mode 100644 index 54203db8ea..0000000000 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/ramips_nand_platform.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Platform data definition for the built-in NAND controller of the - * Ralink RT305X/RT3662/RT3883 SoCs - * - * Copyright (C) 2011-2012 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef _RAMIPS_NAND_PLATFORM_H -#define _RAMIPS_NAND_PLATFORM_H - -#define RAMIPS_NAND_DRIVER_NAME "ramips-nand" - -struct ramips_nand_platform_data { - const char *name; - struct mtd_partition *parts; - int nr_parts; -}; - -#endif /* _RAMIPS_NAND_PLATFORM_H */ diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x.h deleted file mode 100644 index 10d7263324..0000000000 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Ralink RT288x SoC specific definitions - * - * Copyright (C) 2008-2011 Gabor Juhos - * Copyright (C) 2008 Imre Kaloz - * - * Parts of this file are based on Ralink's 2.6.21 BSP - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef _RT288X_H_ -#define _RT288X_H_ - -#include -#include - -#define RT288X_MEM_SIZE_MIN (2 * 1024 * 1024) -#define RT288X_MEM_SIZE_MAX (128 * 1024 * 1024) - -#define RT288X_CPU_IRQ_BASE 0 -#define RT288X_INTC_IRQ_BASE 8 -#define RT288X_INTC_IRQ_COUNT 32 -#define RT288X_GPIO_IRQ_BASE 40 - -#define RT288X_CPU_IRQ_INTC (RT288X_CPU_IRQ_BASE + 2) -#define RT288X_CPU_IRQ_PCI (RT288X_CPU_IRQ_BASE + 4) -#define RT288X_CPU_IRQ_FE (RT288X_CPU_IRQ_BASE + 5) -#define RT288X_CPU_IRQ_WNIC (RT288X_CPU_IRQ_BASE + 6) -#define RT288X_CPU_IRQ_COUNTER (RT288X_CPU_IRQ_BASE + 7) - -#define RT2880_INTC_IRQ_TIMER0 (RT288X_INTC_IRQ_BASE + 0) -#define RT2880_INTC_IRQ_TIMER1 (RT288X_INTC_IRQ_BASE + 1) -#define RT2880_INTC_IRQ_UART0 (RT288X_INTC_IRQ_BASE + 2) -#define RT2880_INTC_IRQ_PIO (RT288X_INTC_IRQ_BASE + 3) -#define RT2880_INTC_IRQ_PCM (RT288X_INTC_IRQ_BASE + 4) -#define RT2880_INTC_IRQ_UART1 (RT288X_INTC_IRQ_BASE + 8) -#define RT2880_INTC_IRQ_IA (RT288X_INTC_IRQ_BASE + 23) - -#define RT288X_GPIO_IRQ(x) (RT288X_GPIO_IRQ_BASE + (x)) -#define RT288X_GPIO_COUNT 32 - -extern void __iomem *rt288x_sysc_base; -extern void __iomem *rt288x_memc_base; - -static inline void rt288x_sysc_wr(u32 val, unsigned reg) -{ - __raw_writel(val, rt288x_sysc_base + reg); -} - -static inline u32 rt288x_sysc_rr(unsigned reg) -{ - return __raw_readl(rt288x_sysc_base + reg); -} - -static inline void rt288x_memc_wr(u32 val, unsigned reg) -{ - __raw_writel(val, rt288x_memc_base + reg); -} - -static inline u32 rt288x_memc_rr(unsigned reg) -{ - return __raw_readl(rt288x_memc_base + reg); -} - -void rt288x_gpio_init(u32 mode); - -#ifdef CONFIG_PCI -int rt288x_register_pci(void); -#else -static inline int rt288x_register_pci(void) { return 0; } -#endif /* CONFIG_PCI */ - -#endif /* _RT228X_H_ */ diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h deleted file mode 100644 index 5e27363324..0000000000 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Ralink RT288x specific CPU feature overrides - * - * Copyright (C) 2008-2009 Gabor Juhos - * Copyright (C) 2008 Imre Kaloz - * - * This file was derived from: include/asm-mips/cpu-features.h - * Copyright (C) 2003, 2004 Ralf Baechle - * Copyright (C) 2004 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - */ -#ifndef __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H -#define __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H - -#define cpu_has_tlb 1 -#define cpu_has_4kex 1 -#define cpu_has_3k_cache 0 -#define cpu_has_4k_cache 1 -#define cpu_has_tx39_cache 0 -#define cpu_has_sb1_cache 0 -#define cpu_has_fpu 0 -#define cpu_has_32fpr 0 -#define cpu_has_counter 1 -#define cpu_has_watch 1 -#define cpu_has_divec 1 - -#define cpu_has_prefetch 1 -#define cpu_has_ejtag 1 -#define cpu_has_llsc 1 - -#define cpu_has_mips16 1 -#define cpu_has_mdmx 0 -#define cpu_has_mips3d 0 -#define cpu_has_smartmips 0 - -#define cpu_has_mips32r1 1 -#define cpu_has_mips32r2 1 -#define cpu_has_mips64r1 0 -#define cpu_has_mips64r2 0 - -#define cpu_has_dsp 0 -#define cpu_has_mipsmt 0 - -#define cpu_has_64bits 0 -#define cpu_has_64bit_zero_reg 0 -#define cpu_has_64bit_gp_regs 0 -#define cpu_has_64bit_addresses 0 - -#define cpu_dcache_line_size() 16 -#define cpu_icache_line_size() 16 - -#endif /* __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H */ diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x/irq.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x/irq.h deleted file mode 100644 index 61264f3c6a..0000000000 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x/irq.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (C) 2008 Gabor Juhos - * Copyright (C) 2008 Imre Kaloz - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ -#ifndef __ASM_MACH_RALINK_RT288X_IRQ_H -#define __ASM_MACH_RALINK_RT288X_IRQ_H - -#define MIPS_CPU_IRQ_BASE 0 -#define NR_IRQS 48 - -#include_next - -#endif /* __ASM_MACH_RALINK_RT288X_IRQ_H */ diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h deleted file mode 100644 index b5f4812b5c..0000000000 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Ralink RT288x SoC register definitions - * - * Copyright (C) 2008-2010 Gabor Juhos - * Copyright (C) 2008 Imre Kaloz - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef _RT288X_REGS_H_ -#define _RT288X_REGS_H_ - -#include - -#define RT2880_SYSC_BASE 0x00300000 -#define RT2880_TIMER_BASE 0x00300100 -#define RT2880_INTC_BASE 0x00300200 -#define RT2880_MEMC_BASE 0x00300300 -#define RT2880_UART0_BASE 0x00300500 -#define RT2880_PIO_BASE 0x00300600 -#define RT2880_I2C_BASE 0x00300900 -#define RT2880_SPI_BASE 0x00300b00 -#define RT2880_UART1_BASE 0x00300c00 -#define RT2880_FE_BASE 0x00400000 -#define RT2880_ROM_BASE 0x00410000 -#define RT2880_PCM_BASE 0x00420000 -#define RT2880_PCI_BASE 0x00440000 -#define RT2880_WMAC_BASE 0x00480000 -#define RT2880_FLASH1_BASE 0x01000000 -#define RT2880_FLASH0_BASE 0x1dc00000 -#define RT2880_SDRAM_BASE 0x08000000 - -#define RT2880_SYSC_SIZE 0x100 -#define RT2880_TIMER_SIZE 0x100 -#define RT2880_INTC_SIZE 0x100 -#define RT2880_MEMC_SIZE 0x100 -#define RT2880_UART0_SIZE 0x100 -#define RT2880_PIO_SIZE 0x100 -#define RT2880_UART1_SIZE 0x100 -#define RT2880_FLASH1_SIZE (16 * 1024 * 1024) -#define RT2880_FLASH0_SIZE (32 * 1024 * 1024) - -/* SYSC registers */ -#define SYSC_REG_CHIP_NAME0 0x000 /* Chip Name 0 */ -#define SYSC_REG_CHIP_NAME1 0x004 /* Chip Name 1 */ -#define SYSC_REG_CHIP_ID 0x00c /* Chip Identification */ -#define SYSC_REG_SYSTEM_CONFIG 0x010 /* System Configuration */ -#define SYSC_REG_CLKCFG 0x030 -#define SYSC_REG_RESET_CTRL 0x034 /* Reset Control*/ -#define SYSC_REG_RESET_STATUS 0x038 /* Reset Status*/ -#define SYSC_REG_GPIO_MODE 0x060 /* GPIO Purpose Select */ -#define SYSC_REG_IA_ADDRESS 0x310 /* Illegal Access Address */ -#define SYSC_REG_IA_TYPE 0x314 /* Illegal Access Type */ - -#define CHIP_ID_ID_MASK 0xff -#define CHIP_ID_ID_SHIFT 8 -#define CHIP_ID_REV_MASK 0xff - -#define SYSTEM_CONFIG_CPUCLK_SHIFT 20 -#define SYSTEM_CONFIG_CPUCLK_MASK 0x3 -#define SYSTEM_CONFIG_CPUCLK_250 0x0 -#define SYSTEM_CONFIG_CPUCLK_266 0x1 -#define SYSTEM_CONFIG_CPUCLK_280 0x2 -#define SYSTEM_CONFIG_CPUCLK_300 0x3 - -#define CLKCFG_SRAM_CS_N_WDT BIT(9) - -#define RT2880_RESET_SYSTEM BIT(0) -#define RT2880_RESET_TIMER BIT(1) -#define RT2880_RESET_INTC BIT(2) -#define RT2880_RESET_MEMC BIT(3) -#define RT2880_RESET_CPU BIT(4) -#define RT2880_RESET_UART0 BIT(5) -#define RT2880_RESET_PIO BIT(6) -#define RT2880_RESET_I2C BIT(9) -#define RT2880_RESET_SPI BIT(11) -#define RT2880_RESET_UART1 BIT(12) -#define RT2880_RESET_PCI BIT(16) -#define RT2880_RESET_WMAC BIT(17) -#define RT2880_RESET_FE BIT(18) -#define RT2880_RESET_PCM BIT(19) - -#define RT2880_GPIO_MODE_I2C BIT(0) -#define RT2880_GPIO_MODE_UART0 BIT(1) -#define RT2880_GPIO_MODE_SPI BIT(2) -#define RT2880_GPIO_MODE_UART1 BIT(3) -#define RT2880_GPIO_MODE_JTAG BIT(4) -#define RT2880_GPIO_MODE_MDIO BIT(5) -#define RT2880_GPIO_MODE_SDRAM BIT(6) -#define RT2880_GPIO_MODE_PCI BIT(7) - -#define RT2880_INTC_INT_TIMER0 BIT(0) -#define RT2880_INTC_INT_TIMER1 BIT(1) -#define RT2880_INTC_INT_UART0 BIT(2) -#define RT2880_INTC_INT_PIO BIT(3) -#define RT2880_INTC_INT_PCM BIT(4) -#define RT2880_INTC_INT_UART1 BIT(8) -#define RT2880_INTC_INT_IA BIT(23) -#define RT2880_INTC_INT_GLOBAL BIT(31) - -/* MEMC registers */ -#define MEMC_REG_SDRAM_CFG0 0x00 -#define MEMC_REG_SDRAM_CFG1 0x04 -#define MEMC_REG_FLASH_CFG0 0x08 -#define MEMC_REG_FLASH_CFG1 0x0c -#define MEMC_REG_IA_ADDR 0x10 -#define MEMC_REG_IA_TYPE 0x14 - -#define FLASH_CFG_WIDTH_SHIFT 26 -#define FLASH_CFG_WIDTH_MASK 0x3 -#define FLASH_CFG_WIDTH_8BIT 0x0 -#define FLASH_CFG_WIDTH_16BIT 0x1 -#define FLASH_CFG_WIDTH_32BIT 0x2 - -/* UART registers */ -#define UART_REG_RX 0 -#define UART_REG_TX 1 -#define UART_REG_IER 2 -#define UART_REG_IIR 3 -#define UART_REG_FCR 4 -#define UART_REG_LCR 5 -#define UART_REG_MCR 6 -#define UART_REG_LSR 7 - -#endif /* _RT288X_REGS_H_ */ diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x.h deleted file mode 100644 index c59135c1ab..0000000000 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x.h +++ /dev/null @@ -1,169 +0,0 @@ -/* - * Ralink RT305x SoC specific definitions - * - * Copyright (C) 2009-2011 Gabor Juhos - * - * Parts of this file are based on Ralink's 2.6.21 BSP - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef _RT305X_H_ -#define _RT305X_H_ - -#include -#include - -enum rt305x_soc_type { - RT305X_SOC_UNKNOWN = 0, - RT305X_SOC_RT3050, - RT305X_SOC_RT3052, - RT305X_SOC_RT3350, - RT305X_SOC_RT3352, - RT305X_SOC_RT5350, -}; - -extern enum rt305x_soc_type rt305x_soc; - -static inline int soc_is_rt3050(void) -{ - return rt305x_soc == RT305X_SOC_RT3050; -} - -static inline int soc_is_rt3052(void) -{ - return rt305x_soc == RT305X_SOC_RT3052; -} - -static inline int soc_is_rt305x(void) -{ - return soc_is_rt3050() || soc_is_rt3052(); -} - -static inline int soc_is_rt3350(void) -{ - return rt305x_soc == RT305X_SOC_RT3350; -} - -static inline int soc_is_rt3352(void) -{ - return rt305x_soc == RT305X_SOC_RT3352; -} - -static inline int soc_is_rt5350(void) -{ - return rt305x_soc == RT305X_SOC_RT5350; -} - -#define RT305X_MEM_SIZE_MIN (2 * 1024 * 1024) -#define RT305X_MEM_SIZE_MAX (64 * 1024 * 1024) - -#define RT3352_MEM_SIZE_MIN (2 * 1024 * 1024) -#define RT3352_MEM_SIZE_MAX (256 * 1024 * 1024) - -#define RT305X_CPU_IRQ_BASE 0 -#define RT305X_INTC_IRQ_BASE 8 -#define RT305X_INTC_IRQ_COUNT 32 -#define RT305X_GPIO_IRQ_BASE 40 - -#define RT305X_CPU_IRQ_INTC (RT305X_CPU_IRQ_BASE + 2) -#define RT305X_CPU_IRQ_FE (RT305X_CPU_IRQ_BASE + 5) -#define RT305X_CPU_IRQ_WNIC (RT305X_CPU_IRQ_BASE + 6) -#define RT305X_CPU_IRQ_COUNTER (RT305X_CPU_IRQ_BASE + 7) - -#define RT305X_INTC_IRQ_SYSCTL (RT305X_INTC_IRQ_BASE + 0) -#define RT305X_INTC_IRQ_TIMER0 (RT305X_INTC_IRQ_BASE + 1) -#define RT305X_INTC_IRQ_TIMER1 (RT305X_INTC_IRQ_BASE + 2) -#define RT305X_INTC_IRQ_IA (RT305X_INTC_IRQ_BASE + 3) -#define RT305X_INTC_IRQ_PCM (RT305X_INTC_IRQ_BASE + 4) -#define RT305X_INTC_IRQ_UART0 (RT305X_INTC_IRQ_BASE + 5) -#define RT305X_INTC_IRQ_PIO (RT305X_INTC_IRQ_BASE + 6) -#define RT305X_INTC_IRQ_DMA (RT305X_INTC_IRQ_BASE + 7) -#define RT305X_INTC_IRQ_NAND (RT305X_INTC_IRQ_BASE + 8) -#define RT305X_INTC_IRQ_PERFC (RT305X_INTC_IRQ_BASE + 9) -#define RT305X_INTC_IRQ_I2S (RT305X_INTC_IRQ_BASE + 10) -#define RT305X_INTC_IRQ_UART1 (RT305X_INTC_IRQ_BASE + 12) -#define RT305X_INTC_IRQ_ESW (RT305X_INTC_IRQ_BASE + 17) -#define RT305X_INTC_IRQ_OTG (RT305X_INTC_IRQ_BASE + 18) - -extern void __iomem *rt305x_sysc_base; -extern void __iomem *rt305x_memc_base; - -static inline void rt305x_sysc_wr(u32 val, unsigned reg) -{ - __raw_writel(val, rt305x_sysc_base + reg); -} - -static inline u32 rt305x_sysc_rr(unsigned reg) -{ - return __raw_readl(rt305x_sysc_base + reg); -} - -static inline void rt305x_memc_wr(u32 val, unsigned reg) -{ - __raw_writel(val, rt305x_memc_base + reg); -} - -static inline u32 rt305x_memc_rr(unsigned reg) -{ - return __raw_readl(rt305x_memc_base + reg); -} - -#define RT305X_GPIO_I2C_SD 1 -#define RT305X_GPIO_I2C_SCLK 2 -#define RT305X_GPIO_SPI_EN 3 -#define RT305X_GPIO_SPI_CLK 4 -#define RT305X_GPIO_SPI_DOUT 5 -#define RT305X_GPIO_SPI_DIN 6 -/* GPIO 7-14 is shared between UART0, PCM and I2S interfaces */ -#define RT305X_GPIO_7 7 -#define RT305X_GPIO_8 8 -#define RT305X_GPIO_9 9 -#define RT305X_GPIO_10 10 -#define RT305X_GPIO_11 11 -#define RT305X_GPIO_12 12 -#define RT305X_GPIO_13 13 -#define RT305X_GPIO_14 14 -#define RT305X_GPIO_UART1_TXD 15 -#define RT305X_GPIO_UART1_RXD 16 -#define RT305X_GPIO_JTAG_TDO 17 -#define RT305X_GPIO_JTAG_TDI 18 -#define RT305X_GPIO_JTAG_TMS 19 -#define RT305X_GPIO_JTAG_TCLK 20 -#define RT305X_GPIO_JTAG_TRST_N 21 -#define RT305X_GPIO_MDIO_MDC 22 -#define RT305X_GPIO_MDIO_MDIO 23 -#define RT305X_GPIO_SDRAM_MD16 24 -#define RT305X_GPIO_SDRAM_MD17 25 -#define RT305X_GPIO_SDRAM_MD18 26 -#define RT305X_GPIO_SDRAM_MD19 27 -#define RT305X_GPIO_SDRAM_MD20 28 -#define RT305X_GPIO_SDRAM_MD21 29 -#define RT305X_GPIO_SDRAM_MD22 30 -#define RT305X_GPIO_SDRAM_MD23 31 -#define RT305X_GPIO_SDRAM_MD24 32 -#define RT305X_GPIO_SDRAM_MD25 33 -#define RT305X_GPIO_SDRAM_MD26 34 -#define RT305X_GPIO_SDRAM_MD27 35 -#define RT305X_GPIO_SDRAM_MD28 36 -#define RT305X_GPIO_SDRAM_MD29 37 -#define RT305X_GPIO_SDRAM_MD30 38 -#define RT305X_GPIO_SDRAM_MD31 39 -#define RT305X_GPIO_GE0_TXD0 40 -#define RT305X_GPIO_GE0_TXD1 41 -#define RT305X_GPIO_GE0_TXD2 42 -#define RT305X_GPIO_GE0_TXD3 43 -#define RT305X_GPIO_GE0_TXEN 44 -#define RT305X_GPIO_GE0_TXCLK 45 -#define RT305X_GPIO_GE0_RXD0 46 -#define RT305X_GPIO_GE0_RXD1 47 -#define RT305X_GPIO_GE0_RXD2 48 -#define RT305X_GPIO_GE0_RXD3 49 -#define RT305X_GPIO_GE0_RXDV 50 -#define RT305X_GPIO_GE0_RXCLK 51 - -void rt305x_gpio_init(u32 mode); - -#endif /* _RT305X_H_ */ diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h deleted file mode 100644 index 8c1261106c..0000000000 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Ralink RT305x specific CPU feature overrides - * - * Copyright (C) 2008-2009 Gabor Juhos - * Copyright (C) 2008 Imre Kaloz - * - * This file was derived from: include/asm-mips/cpu-features.h - * Copyright (C) 2003, 2004 Ralf Baechle - * Copyright (C) 2004 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - */ -#ifndef __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H -#define __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H - -#define cpu_has_tlb 1 -#define cpu_has_4kex 1 -#define cpu_has_3k_cache 0 -#define cpu_has_4k_cache 1 -#define cpu_has_tx39_cache 0 -#define cpu_has_sb1_cache 0 -#define cpu_has_fpu 0 -#define cpu_has_32fpr 0 -#define cpu_has_counter 1 -#define cpu_has_watch 1 -#define cpu_has_divec 1 - -#define cpu_has_prefetch 1 -#define cpu_has_ejtag 1 -#define cpu_has_llsc 1 - -#define cpu_has_mips16 1 -#define cpu_has_mdmx 0 -#define cpu_has_mips3d 0 -#define cpu_has_smartmips 0 - -#define cpu_has_mips32r1 1 -#define cpu_has_mips32r2 1 -#define cpu_has_mips64r1 0 -#define cpu_has_mips64r2 0 - -#define cpu_has_dsp 1 -#define cpu_has_mipsmt 0 - -#define cpu_has_64bits 0 -#define cpu_has_64bit_zero_reg 0 -#define cpu_has_64bit_gp_regs 0 -#define cpu_has_64bit_addresses 0 - -#define cpu_dcache_line_size() 32 -#define cpu_icache_line_size() 32 - -#endif /* __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H */ diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x/irq.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x/irq.h deleted file mode 100644 index a72d677142..0000000000 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x/irq.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (C) 2008 Gabor Juhos - * Copyright (C) 2008 Imre Kaloz - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ -#ifndef __ASM_MACH_RALINK_RT305X_IRQ_H -#define __ASM_MACH_RALINK_RT305X_IRQ_H - -#define MIPS_CPU_IRQ_BASE 0 -#define NR_IRQS 48 - -#include_next - -#endif /* __ASM_MACH_RALINK_RT305X_IRQ_H */ diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h deleted file mode 100644 index 2098c5cc1f..0000000000 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Ralink RT305x SoC platform device registration - * - * Copyright (C) 2010 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef _RT305X_ESW_PLATFORM_H -#define _RT305X_ESW_PLATFORM_H - -enum { - RT305X_ESW_VLAN_CONFIG_NONE = 0, - RT305X_ESW_VLAN_CONFIG_LLLLW, - RT305X_ESW_VLAN_CONFIG_WLLLL, -}; - -struct rt305x_esw_platform_data -{ - u8 vlan_config; - u32 reg_initval_fct2; - u32 reg_initval_fpa2; -}; - -#endif /* _RT305X_ESW_PLATFORM_H */ diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h deleted file mode 100644 index 943facb6de..0000000000 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h +++ /dev/null @@ -1,216 +0,0 @@ -/* - * Ralink RT305 SoC register definitions - * - * Copyright (C) 2009 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef _RT305X_REGS_H_ -#define _RT305X_REGS_H_ - -#include - -#define RT305X_SDRAM_BASE 0x00000000 -#define RT305X_SYSC_BASE 0x10000000 -#define RT305X_TIMER_BASE 0x10000100 -#define RT305X_INTC_BASE 0x10000200 -#define RT305X_MEMC_BASE 0x10000300 -#define RT305X_PCM_BASE 0x10000400 -#define RT305X_UART0_BASE 0x10000500 -#define RT305X_PIO_BASE 0x10000600 -#define RT305X_GDMA_BASE 0x10000700 -#define RT305X_NANDC_BASE 0x10000800 -#define RT305X_I2C_BASE 0x10000900 -#define RT305X_I2S_BASE 0x10000a00 -#define RT305X_SPI_BASE 0x10000b00 -#define RT305X_UART1_BASE 0x10000c00 -#define RT305X_FE_BASE 0x10100000 -#define RT305X_SWITCH_BASE 0x10110000 -#define RT305X_WMAC_BASE 0x10180000 -#define RT305X_OTG_BASE 0x101c0000 -#define RT305X_ROM_BASE 0x00400000 -#define RT305X_FLASH1_BASE 0x1b000000 -#define RT305X_FLASH0_BASE 0x1f000000 - -#define RT305X_SYSC_SIZE 0x100 -#define RT305X_TIMER_SIZE 0x100 -#define RT305X_INTC_SIZE 0x100 -#define RT305X_MEMC_SIZE 0x100 -#define RT305X_UART0_SIZE 0x100 -#define RT305X_PIO_SIZE 0x100 -#define RT305X_UART1_SIZE 0x100 -#define RT305X_SPI_SIZE 0x100 -#define RT305X_FLASH1_SIZE (16 * 1024 * 1024) -#define RT305X_FLASH0_SIZE (8 * 1024 * 1024) - -#define RT3352_EHCI_BASE 0x101c0000 -#define RT3352_EHCI_SIZE 0x1000 -#define RT3352_OHCI_BASE 0x101c1000 -#define RT3352_OHCI_SIZE 0x1000 - -/* SYSC registers */ -#define SYSC_REG_CHIP_NAME0 0x000 /* Chip Name 0 */ -#define SYSC_REG_CHIP_NAME1 0x004 /* Chip Name 1 */ -#define SYSC_REG_CHIP_ID 0x00c /* Chip Identification */ -#define SYSC_REG_SYSTEM_CONFIG 0x010 /* System Configuration */ -#define SYSC_REG_RESET_CTRL 0x034 /* Reset Control*/ -#define SYSC_REG_RESET_STATUS 0x038 /* Reset Status*/ -#define SYSC_REG_GPIO_MODE 0x060 /* GPIO Purpose Select */ -#define SYSC_REG_IA_ADDRESS 0x310 /* Illegal Access Address */ -#define SYSC_REG_IA_TYPE 0x314 /* Illegal Access Type */ - -#define RT3352_SYSC_REG_SYSCFG1 0x014 -#define RT3352_SYSC_REG_CLKCFG1 0x030 -#define RT3352_SYSC_REG_RSTCTRL 0x034 -#define RT3352_SYSC_REG_USB_PS 0x05c - -#define RT3052_CHIP_NAME0 0x30335452 -#define RT3052_CHIP_NAME1 0x20203235 - -#define RT3350_CHIP_NAME0 0x33335452 -#define RT3350_CHIP_NAME1 0x20203035 - -#define RT3352_CHIP_NAME0 0x33335452 -#define RT3352_CHIP_NAME1 0x20203235 - -#define RT5350_CHIP_NAME0 0x33355452 -#define RT5350_CHIP_NAME1 0x20203035 - -#define CHIP_ID_ID_MASK 0xff -#define CHIP_ID_ID_SHIFT 8 -#define CHIP_ID_REV_MASK 0xff - -#define RT305X_SYSCFG_CPUCLK_SHIFT 18 -#define RT305X_SYSCFG_CPUCLK_MASK 0x1 -#define RT305X_SYSCFG_CPUCLK_LOW 0x0 -#define RT305X_SYSCFG_CPUCLK_HIGH 0x1 -#define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT 2 -#define RT305X_SYSCFG_SRAM_CS0_MODE_MASK 0x3 -#define RT305X_SYSCFG_SRAM_CS0_MODE_NORMAL 0 -#define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 1 -#define RT305X_SYSCFG_SRAM_CS0_MODE_BTCOEX 2 - -#define RT3352_SYSCFG0_CPUCLK_SHIFT 8 -#define RT3352_SYSCFG0_CPUCLK_MASK 0x1 -#define RT3352_SYSCFG0_CPUCLK_LOW 0x0 -#define RT3352_SYSCFG0_CPUCLK_HIGH 0x1 - -#define RT5350_SYSCFG0_CPUCLK_SHIFT 8 -#define RT5350_SYSCFG0_CPUCLK_MASK 0x3 -#define RT5350_SYSCFG0_CPUCLK_360 0x0 -#define RT5350_SYSCFG0_CPUCLK_320 0x2 -#define RT5350_SYSCFG0_CPUCLK_300 0x3 -#define RT5350_SYSCFG0_DRAM_SIZE_SHIFT 12 -#define RT5350_SYSCFG0_DRAM_SIZE_MASK 7 -#define RT5350_SYSCFG0_DRAM_SIZE_2M 0 -#define RT5350_SYSCFG0_DRAM_SIZE_8M 1 -#define RT5350_SYSCFG0_DRAM_SIZE_16M 2 -#define RT5350_SYSCFG0_DRAM_SIZE_32M 3 -#define RT5350_SYSCFG0_DRAM_SIZE_64M 4 - -#define RT3352_SYSCFG0_XTAL_SEL BIT(20) - -#define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10) - -#define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18) -#define RT3352_CLKCFG1_UPHY1_CLK_EN BIT(20) - -#define RT305X_GPIO_MODE_I2C BIT(0) -#define RT305X_GPIO_MODE_SPI BIT(1) -#define RT305X_GPIO_MODE_UART0_SHIFT 2 -#define RT305X_GPIO_MODE_UART0_MASK 0x7 -#define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT) -#define RT305X_GPIO_MODE_UARTF 0x0 -#define RT305X_GPIO_MODE_PCM_UARTF 0x1 -#define RT305X_GPIO_MODE_PCM_I2S 0x2 -#define RT305X_GPIO_MODE_I2S_UARTF 0x3 -#define RT305X_GPIO_MODE_PCM_GPIO 0x4 -#define RT305X_GPIO_MODE_GPIO_UARTF 0x5 -#define RT305X_GPIO_MODE_GPIO_I2S 0x6 -#define RT305X_GPIO_MODE_GPIO 0x7 -#define RT305X_GPIO_MODE_UART1 BIT(5) -#define RT305X_GPIO_MODE_JTAG BIT(6) -#define RT305X_GPIO_MODE_MDIO BIT(7) -#define RT305X_GPIO_MODE_SDRAM BIT(8) -#define RT305X_GPIO_MODE_RGMII BIT(9) - -#define RT305X_RESET_SYSTEM BIT(0) -#define RT305X_RESET_TIMER BIT(8) -#define RT305X_RESET_INTC BIT(9) -#define RT305X_RESET_MEMC BIT(10) -#define RT305X_RESET_PCM BIT(11) -#define RT305X_RESET_UART0 BIT(12) -#define RT305X_RESET_PIO BIT(13) -#define RT305X_RESET_DMA BIT(14) -#define RT305X_RESET_I2C BIT(16) -#define RT305X_RESET_I2S BIT(17) -#define RT305X_RESET_SPI BIT(18) -#define RT305X_RESET_UART1 BIT(19) -#define RT305X_RESET_WNIC BIT(20) -#define RT305X_RESET_FE BIT(21) -#define RT305X_RESET_OTG BIT(22) -#define RT305X_RESET_ESW BIT(23) - -#define RT3352_RSTCTRL_SYS BIT(0) -#define RT3352_RSTCTRL_TIMER BIT(8) -#define RT3352_RSTCTRL_INTC BIT(9) -#define RT3352_RSTCTRL_MEMC BIT(10) -#define RT3352_RSTCTRL_PCM BIT(11) -#define RT3352_RSTCTRL_UART0 BIT(12) -#define RT3352_RSTCTRL_PIO BIT(13) -#define RT3352_RSTCTRL_DMA BIT(14) -#define RT3352_RSTCTRL_I2C BIT(16) -#define RT3352_RSTCTRL_I2S BIT(17) -#define RT3352_RSTCTRL_SPI BIT(18) -#define RT3352_RSTCTRL_UART1 BIT(19) -#define RT3352_RSTCTRL_WNIC BIT(20) -#define RT3352_RSTCTRL_FE BIT(21) -#define RT3352_RSTCTRL_UHST BIT(22) -#define RT3352_RSTCTRL_ESW BIT(23) -#define RT3352_RSTCTRL_EPHY BIT(24) -#define RT3352_RSTCTRL_UDEV BIT(25) - -#define RT305X_INTC_INT_SYSCTL BIT(0) -#define RT305X_INTC_INT_TIMER0 BIT(1) -#define RT305X_INTC_INT_TIMER1 BIT(2) -#define RT305X_INTC_INT_IA BIT(3) -#define RT305X_INTC_INT_PCM BIT(4) -#define RT305X_INTC_INT_UART0 BIT(5) -#define RT305X_INTC_INT_PIO BIT(6) -#define RT305X_INTC_INT_DMA BIT(7) -#define RT305X_INTC_INT_NAND BIT(8) -#define RT305X_INTC_INT_PERFC BIT(9) -#define RT305X_INTC_INT_I2S BIT(10) -#define RT305X_INTC_INT_UART1 BIT(12) -#define RT305X_INTC_INT_ESW BIT(17) -#define RT305X_INTC_INT_OTG BIT(18) -#define RT305X_INTC_INT_GLOBAL BIT(31) - -/* MEMC registers */ -#define MEMC_REG_SDRAM_CFG0 0x00 -#define MEMC_REG_SDRAM_CFG1 0x04 -#define MEMC_REG_FLASH_CFG0 0x08 -#define MEMC_REG_FLASH_CFG1 0x0c -#define MEMC_REG_IA_ADDR 0x10 -#define MEMC_REG_IA_TYPE 0x14 - -#define FLASH_CFG_WIDTH_SHIFT 26 -#define FLASH_CFG_WIDTH_MASK 0x3 -#define FLASH_CFG_WIDTH_8BIT 0x0 -#define FLASH_CFG_WIDTH_16BIT 0x1 -#define FLASH_CFG_WIDTH_32BIT 0x2 - -/* UART registers */ -#define UART_REG_RX 0 -#define UART_REG_TX 1 -#define UART_REG_IER 2 -#define UART_REG_IIR 3 -#define UART_REG_FCR 4 -#define UART_REG_LCR 5 -#define UART_REG_MCR 6 -#define UART_REG_LSR 7 - -#endif /* _RT305X_REGS_H_ */ diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883.h deleted file mode 100644 index cf8fb6fd10..0000000000 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Ralink RT3662/RT3883 SoC specific definitions - * - * Copyright (C) 2011-2012 Gabor Juhos - * - * Parts of this file are based on Ralink's 2.6.21 BSP - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef _RT3883_H_ -#define _RT3883_H_ - -#include -#include - -#define RT3883_MEM_SIZE_MIN (2 * 1024 * 1024) -#define RT3883_MEM_SIZE_MAX (256 * 1024 * 1024) - -#define RT3883_CPU_IRQ_BASE 0 -#define RT3883_CPU_IRQ_COUNT 8 -#define RT3883_INTC_IRQ_BASE (RT3883_CPU_IRQ_BASE + RT3883_CPU_IRQ_COUNT) -#define RT3883_INTC_IRQ_COUNT 32 -#define RT3883_GPIO_IRQ_BASE (RT3883_INTC_IRQ_BASE + RT3883_INTC_IRQ_COUNT) -#define RT3883_GPIO_IRQ_COUNT 96 -#define RT3883_PCI_IRQ_BASE (RT3883_GPIO_IRQ_BASE + RT3883_GPIO_IRQ_COUNT) -#define RT3883_PCI_IRQ_COUNT 3 - -#define RT3883_CPU_IRQ_INTC (RT3883_CPU_IRQ_BASE + 2) -#define RT3883_CPU_IRQ_PCI (RT3883_CPU_IRQ_BASE + 4) -#define RT3883_CPU_IRQ_FE (RT3883_CPU_IRQ_BASE + 5) -#define RT3883_CPU_IRQ_WLAN (RT3883_CPU_IRQ_BASE + 6) -#define RT3883_CPU_IRQ_COUNTER (RT3883_CPU_IRQ_BASE + 7) - -#define RT3883_INTC_IRQ_SYSCTL (RT3883_INTC_IRQ_BASE + 0) -#define RT3883_INTC_IRQ_TIMER0 (RT3883_INTC_IRQ_BASE + 1) -#define RT3883_INTC_IRQ_TIMER1 (RT3883_INTC_IRQ_BASE + 2) -#define RT3883_INTC_IRQ_IA (RT3883_INTC_IRQ_BASE + 3) -#define RT3883_INTC_IRQ_PCM (RT3883_INTC_IRQ_BASE + 4) -#define RT3883_INTC_IRQ_UART0 (RT3883_INTC_IRQ_BASE + 5) -#define RT3883_INTC_IRQ_PIO (RT3883_INTC_IRQ_BASE + 6) -#define RT3883_INTC_IRQ_DMA (RT3883_INTC_IRQ_BASE + 7) -#define RT3883_INTC_IRQ_NAND (RT3883_INTC_IRQ_BASE + 8) -#define RT3883_INTC_IRQ_PERFC (RT3883_INTC_IRQ_BASE + 9) -#define RT3883_INTC_IRQ_I2S (RT3883_INTC_IRQ_BASE + 10) -#define RT3883_INTC_IRQ_UART1 (RT3883_INTC_IRQ_BASE + 12) -#define RT3883_INTC_IRQ_UHST (RT3883_INTC_IRQ_BASE + 18) -#define RT3883_INTC_IRQ_UDEV (RT3883_INTC_IRQ_BASE + 19) - -#define RT3883_PCI_IRQ_PCI0 (RT3883_PCI_IRQ_BASE + 0) -#define RT3883_PCI_IRQ_PCI1 (RT3883_PCI_IRQ_BASE + 1) -#define RT3883_PCI_IRQ_PCIE (RT3883_PCI_IRQ_BASE + 2) - -extern void __iomem *rt3883_sysc_base; -extern void __iomem *rt3883_memc_base; - -static inline void rt3883_sysc_wr(u32 val, unsigned reg) -{ - __raw_writel(val, rt3883_sysc_base + reg); -} - -static inline u32 rt3883_sysc_rr(unsigned reg) -{ - return __raw_readl(rt3883_sysc_base + reg); -} - -static inline void rt3883_memc_wr(u32 val, unsigned reg) -{ - __raw_writel(val, rt3883_memc_base + reg); -} - -static inline u32 rt3883_memc_rr(unsigned reg) -{ - return __raw_readl(rt3883_memc_base + reg); -} - -#define RT3883_GPIO_I2C_SD 1 -#define RT3883_GPIO_I2C_SCLK 2 -#define RT3883_GPIO_SPI_CS0 3 -#define RT3883_GPIO_SPI_CLK 4 -#define RT3883_GPIO_SPI_MOSI 5 -#define RT3883_GPIO_SPI_MISO 6 -/* GPIO 7-14 is shared between UART0, PCM and I2S interfaces */ -#define RT3883_GPIO_7 7 -#define RT3883_GPIO_8 8 -#define RT3883_GPIO_9 9 -#define RT3883_GPIO_10 10 -#define RT3883_GPIO_11 11 -#define RT3883_GPIO_12 12 -#define RT3883_GPIO_13 13 -#define RT3883_GPIO_14 14 -#define RT3883_GPIO_UART1_TXD 15 -#define RT3883_GPIO_UART1_RXD 16 -#define RT3883_GPIO_JTAG_TDO 17 -#define RT3883_GPIO_JTAG_TDI 18 -#define RT3883_GPIO_JTAG_TMS 19 -#define RT3883_GPIO_JTAG_TCLK 20 -#define RT3883_GPIO_JTAG_TRST_N 21 -#define RT3883_GPIO_MDIO_MDC 22 -#define RT3883_GPIO_MDIO_MDIO 23 -#define RT3883_GPIO_LNA_PE_A0 32 -#define RT3883_GPIO_LNA_PE_A1 33 -#define RT3883_GPIO_LNA_PE_A2 34 -#define RT3883_GPIO_LNA_PE_G0 35 -#define RT3883_GPIO_LNA_PE_G1 36 -#define RT3883_GPIO_LNA_PE_G2 37 -#define RT3883_GPIO_PCI_AD0 40 -#define RT3883_GPIO_PCI_AD31 71 -#define RT3883_GPIO_GE2_TXD0 72 -#define RT3883_GPIO_GE2_TXD1 73 -#define RT3883_GPIO_GE2_TXD2 74 -#define RT3883_GPIO_GE2_TXD3 75 -#define RT3883_GPIO_GE2_TXEN 76 -#define RT3883_GPIO_GE2_TXCLK 77 -#define RT3883_GPIO_GE2_RXD0 78 -#define RT3883_GPIO_GE2_RXD1 79 -#define RT3883_GPIO_GE2_RXD2 80 -#define RT3883_GPIO_GE2_RXD3 81 -#define RT3883_GPIO_GE2_RXDV 82 -#define RT3883_GPIO_GE2_RXCLK 83 -#define RT3883_GPIO_GE1_TXD0 84 -#define RT3883_GPIO_GE1_TXD1 85 -#define RT3883_GPIO_GE1_TXD2 86 -#define RT3883_GPIO_GE1_TXD3 87 -#define RT3883_GPIO_GE1_TXEN 88 -#define RT3883_GPIO_GE1_TXCLK 89 -#define RT3883_GPIO_GE1_RXD0 90 -#define RT3883_GPIO_GE1_RXD1 91 -#define RT3883_GPIO_GE1_RXD2 92 -#define RT3883_GPIO_GE1_RXD3 93 -#define RT3883_GPIO_GE1_RXDV 94 -#define RT3883_GPIO_GE1_RXCLK 95 - -void rt3883_gpio_init(u32 mode); - -#define RT3883_PCI_MODE_PCI 0x01 -#define RT3883_PCI_MODE_PCIE 0x02 -#define RT3883_PCI_MODE_BOTH (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE) - -struct pci_dev; - -#ifdef CONFIG_PCI -void rt3883_pci_init(unsigned mode); -void rt3883_pci_set_plat_dev_init(int (*f)(struct pci_dev *)); -#else -static inline void rt3883_pci_init(unsigned mode) {} -static inline void rt3883_pci_set_plat_dev_init(int (*f)(struct pci_dev *)) {} -#endif /* CONFIG_PCI */ - -#endif /* _RT3883_H_ */ diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h deleted file mode 100644 index ac435dd330..0000000000 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Ralink RT3662/RT3883 specific CPU feature overrides - * - * Copyright (C) 2011-2012 Gabor Juhos - * - * This file was derived from: include/asm-mips/cpu-features.h - * Copyright (C) 2003, 2004 Ralf Baechle - * Copyright (C) 2004 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - */ -#ifndef __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H -#define __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H - -#define cpu_has_tlb 1 -#define cpu_has_4kex 1 -#define cpu_has_3k_cache 0 -#define cpu_has_4k_cache 1 -#define cpu_has_tx39_cache 0 -#define cpu_has_sb1_cache 0 -#define cpu_has_fpu 0 -#define cpu_has_32fpr 0 -#define cpu_has_counter 1 -#define cpu_has_watch 1 -#define cpu_has_divec 1 - -#define cpu_has_prefetch 1 -#define cpu_has_ejtag 1 -#define cpu_has_llsc 1 - -#define cpu_has_mips16 1 -#define cpu_has_mdmx 0 -#define cpu_has_mips3d 0 -#define cpu_has_smartmips 0 - -#define cpu_has_mips32r1 1 -#define cpu_has_mips32r2 1 -#define cpu_has_mips64r1 0 -#define cpu_has_mips64r2 0 - -#define cpu_has_dsp 1 -#define cpu_has_mipsmt 0 - -#define cpu_has_64bits 0 -#define cpu_has_64bit_zero_reg 0 -#define cpu_has_64bit_gp_regs 0 -#define cpu_has_64bit_addresses 0 - -#define cpu_dcache_line_size() 32 -#define cpu_icache_line_size() 32 - -#endif /* __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H */ diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883/irq.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883/irq.h deleted file mode 100644 index 635d68c101..0000000000 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883/irq.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2012 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ -#ifndef __ASM_MACH_RALINK_RT3883_IRQ_H -#define __ASM_MACH_RALINK_RT3883_IRQ_H - -#define MIPS_CPU_IRQ_BASE 0 -#define NR_IRQS 140 - -#include_next - -#endif /* __ASM_MACH_RALINK_RT3883_IRQ_H */ diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883_regs.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883_regs.h deleted file mode 100644 index b36cabe858..0000000000 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883_regs.h +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Ralink RT3662/RT3883 SoC register definitions - * - * Copyright (C) 2011-2012 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef _RT3883_REGS_H_ -#define _RT3883_REGS_H_ - -#include - -#define RT3883_SDRAM_BASE 0x00000000 -#define RT3883_SYSC_BASE 0x10000000 -#define RT3883_TIMER_BASE 0x10000100 -#define RT3883_INTC_BASE 0x10000200 -#define RT3883_MEMC_BASE 0x10000300 -#define RT3883_UART0_BASE 0x10000500 -#define RT3883_PIO_BASE 0x10000600 -#define RT3883_FSCC_BASE 0x10000700 -#define RT3883_NANDC_BASE 0x10000810 -#define RT3883_I2C_BASE 0x10000900 -#define RT3883_I2S_BASE 0x10000a00 -#define RT3883_SPI_BASE 0x10000b00 -#define RT3883_UART1_BASE 0x10000c00 -#define RT3883_PCM_BASE 0x10002000 -#define RT3883_GDMA_BASE 0x10002800 -#define RT3883_CODEC1_BASE 0x10003000 -#define RT3883_CODEC2_BASE 0x10003800 -#define RT3883_FE_BASE 0x10100000 -#define RT3883_ROM_BASE 0x10118000 -#define RT3883_USBDEV_BASE 0x10112000 -#define RT3883_PCI_BASE 0x10140000 -#define RT3883_WLAN_BASE 0x10180000 -#define RT3883_USBHOST_BASE 0x101c0000 -#define RT3883_BOOT_BASE 0x1c000000 -#define RT3883_SRAM_BASE 0x1e000000 -#define RT3883_PCIMEM_BASE 0x20000000 - -#define RT3883_EHCI_BASE (RT3883_USBHOST_BASE) -#define RT3883_OHCI_BASE (RT3883_USBHOST_BASE + 0x1000) - -#define RT3883_SYSC_SIZE 0x100 -#define RT3883_TIMER_SIZE 0x100 -#define RT3883_INTC_SIZE 0x100 -#define RT3883_MEMC_SIZE 0x100 -#define RT3883_UART0_SIZE 0x100 -#define RT3883_UART1_SIZE 0x100 -#define RT3883_PIO_SIZE 0x100 -#define RT3883_FSCC_SIZE 0x100 -#define RT3883_NANDC_SIZE 0x0f0 -#define RT3883_I2C_SIZE 0x100 -#define RT3883_I2S_SIZE 0x100 -#define RT3883_SPI_SIZE 0x100 -#define RT3883_PCM_SIZE 0x800 -#define RT3883_GDMA_SIZE 0x800 -#define RT3883_CODEC1_SIZE 0x800 -#define RT3883_CODEC2_SIZE 0x800 -#define RT3883_FE_SIZE 0x10000 -#define RT3883_ROM_SIZE 0x4000 -#define RT3883_USBDEV_SIZE 0x4000 -#define RT3883_PCI_SIZE 0x40000 -#define RT3883_WLAN_SIZE 0x40000 -#define RT3883_USBHOST_SIZE 0x40000 -#define RT3883_BOOT_SIZE (32 * 1024 * 1024) -#define RT3883_SRAM_SIZE (32 * 1024 * 1024) - -/* SYSC registers */ -#define RT3883_SYSC_REG_CHIPID0_3 0x00 /* Chip ID 0 */ -#define RT3883_SYSC_REG_CHIPID4_7 0x04 /* Chip ID 1 */ -#define RT3883_SYSC_REG_REVID 0x0c /* Chip Revision Identification */ -#define RT3883_SYSC_REG_SYSCFG0 0x10 /* System Configuration 0 */ -#define RT3883_SYSC_REG_SYSCFG1 0x14 /* System Configuration 1 */ -#define RT3883_SYSC_REG_CLKCFG0 0x2c /* Clock Configuration 0 */ -#define RT3883_SYSC_REG_CLKCFG1 0x30 /* Clock Configuration 1 */ -#define RT3883_SYSC_REG_RSTCTRL 0x34 /* Reset Control*/ -#define RT3883_SYSC_REG_RSTSTAT 0x38 /* Reset Status*/ -#define RT3883_SYSC_REG_USB_PS 0x5c /* USB Power saving control */ -#define RT3883_SYSC_REG_GPIO_MODE 0x60 /* GPIO Purpose Select */ -#define RT3883_SYSC_REG_PCIE_CLK_GEN0 0x7c -#define RT3883_SYSC_REG_PCIE_CLK_GEN1 0x80 -#define RT3883_SYSC_REG_PCIE_CLK_GEN2 0x84 -#define RT3883_SYSC_REG_PMU 0x88 -#define RT3883_SYSC_REG_PMU1 0x8c - -#define RT3883_REVID_VER_ID_MASK 0x0f -#define RT3883_REVID_VER_ID_SHIFT 8 -#define RT3883_REVID_ECO_ID_MASK 0x0f - -#define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17) -#define RT3883_SYSCFG0_CPUCLK_SHIFT 8 -#define RT3883_SYSCFG0_CPUCLK_MASK 0x3 -#define RT3883_SYSCFG0_CPUCLK_250 0x0 -#define RT3883_SYSCFG0_CPUCLK_384 0x1 -#define RT3883_SYSCFG0_CPUCLK_480 0x2 -#define RT3883_SYSCFG0_CPUCLK_500 0x3 - -#define RT3883_SYSCFG1_USB0_HOST_MODE BIT(10) -#define RT3883_SYSCFG1_PCIE_RC_MODE BIT(8) -#define RT3883_SYSCFG1_PCI_HOST_MODE BIT(7) -#define RT3883_SYSCFG1_PCI_66M_MODE BIT(6) -#define RT3883_SYSCFG1_GPIO2_AS_WDT_OUT BIT(2) - -#define RT3883_CLKCFG1_PCIE_CLK_EN BIT(21) -#define RT3883_CLKCFG1_UPHY1_CLK_EN BIT(20) -#define RT3883_CLKCFG1_PCI_CLK_EN BIT(19) -#define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18) - -#define RT3883_GPIO_MODE_I2C BIT(0) -#define RT3883_GPIO_MODE_SPI BIT(1) -#define RT3883_GPIO_MODE_UART0_SHIFT 2 -#define RT3883_GPIO_MODE_UART0_MASK 0x7 -#define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT) -#define RT3883_GPIO_MODE_UARTF 0x0 -#define RT3883_GPIO_MODE_PCM_UARTF 0x1 -#define RT3883_GPIO_MODE_PCM_I2S 0x2 -#define RT3883_GPIO_MODE_I2S_UARTF 0x3 -#define RT3883_GPIO_MODE_PCM_GPIO 0x4 -#define RT3883_GPIO_MODE_GPIO_UARTF 0x5 -#define RT3883_GPIO_MODE_GPIO_I2S 0x6 -#define RT3883_GPIO_MODE_GPIO 0x7 -#define RT3883_GPIO_MODE_UART1 BIT(5) -#define RT3883_GPIO_MODE_JTAG BIT(6) -#define RT3883_GPIO_MODE_MDIO BIT(7) -#define RT3883_GPIO_MODE_GE1 BIT(9) -#define RT3883_GPIO_MODE_GE2 BIT(10) -#define RT3883_GPIO_MODE_PCI_SHIFT 11 -#define RT3883_GPIO_MODE_PCI_MASK 0x7 -#define RT3883_GPIO_MODE_PCI(_x) ((_x) << RT3883_GPIO_MODE_PCI_SHIFT) -#define RT3883_GPIO_MODE_PCI_DEV 0 -#define RT3883_GPIO_MODE_PCI_HOST2 1 -#define RT3883_GPIO_MODE_PCI_HOST1 2 -#define RT3883_GPIO_MODE_PCI_FNC 3 -#define RT3883_GPIO_MODE_PCI_GPIO 7 -#define RT3883_GPIO_MODE_LNA_A_SHIFT 16 -#define RT3883_GPIO_MODE_LNA_A_MASK 0x3 -#define RT3883_GPIO_MODE_LNA_A(_x) ((_x) << RT3883_GPIO_MODE_LNA_A_SHIFT) -#define RT3883_GPIO_MODE_LNA_A_GPIO 0x3 -#define RT3883_GPIO_MODE_LNA_G_SHIFT 18 -#define RT3883_GPIO_MODE_LNA_G_MASK 0x3 -#define RT3883_GPIO_MODE_LNA_G(_x) ((_x) << RT3883_GPIO_MODE_LNA_G_SHIFT) -#define RT3883_GPIO_MODE_LNA_G_GPIO 0x3 - -#define RT3883_RSTCTRL_PCIE_PCI_PDM BIT(27) -#define RT3883_RSTCTRL_FLASH BIT(26) -#define RT3883_RSTCTRL_UDEV BIT(25) -#define RT3883_RSTCTRL_PCI BIT(24) -#define RT3883_RSTCTRL_PCIE BIT(23) -#define RT3883_RSTCTRL_UHST BIT(22) -#define RT3883_RSTCTRL_FE BIT(21) -#define RT3883_RSTCTRL_WLAN BIT(20) -#define RT3883_RSTCTRL_UART1 BIT(29) -#define RT3883_RSTCTRL_SPI BIT(18) -#define RT3883_RSTCTRL_I2S BIT(17) -#define RT3883_RSTCTRL_I2C BIT(16) -#define RT3883_RSTCTRL_NAND BIT(15) -#define RT3883_RSTCTRL_DMA BIT(14) -#define RT3883_RSTCTRL_PIO BIT(13) -#define RT3883_RSTCTRL_UART BIT(12) -#define RT3883_RSTCTRL_PCM BIT(11) -#define RT3883_RSTCTRL_MC BIT(10) -#define RT3883_RSTCTRL_INTC BIT(9) -#define RT3883_RSTCTRL_TIMER BIT(8) -#define RT3883_RSTCTRL_SYS BIT(0) - -#define RT3883_INTC_INT_SYSCTL BIT(0) -#define RT3883_INTC_INT_TIMER0 BIT(1) -#define RT3883_INTC_INT_TIMER1 BIT(2) -#define RT3883_INTC_INT_IA BIT(3) -#define RT3883_INTC_INT_PCM BIT(4) -#define RT3883_INTC_INT_UART0 BIT(5) -#define RT3883_INTC_INT_PIO BIT(6) -#define RT3883_INTC_INT_DMA BIT(7) -#define RT3883_INTC_INT_NAND BIT(8) -#define RT3883_INTC_INT_PERFC BIT(9) -#define RT3883_INTC_INT_I2S BIT(10) -#define RT3883_INTC_INT_UART1 BIT(12) -#define RT3883_INTC_INT_UHST BIT(18) -#define RT3883_INTC_INT_UDEV BIT(19) - -/* FLASH/SRAM/Codec Controller registers */ -#define RT3883_FSCC_REG_FLASH_CFG0 0x00 -#define RT3883_FSCC_REG_FLASH_CFG1 0x04 -#define RT3883_FSCC_REG_CODEC_CFG0 0x40 -#define RT3883_FSCC_REG_CODEC_CFG1 0x44 - -#define RT3883_FLASH_CFG_WIDTH_SHIFT 26 -#define RT3883_FLASH_CFG_WIDTH_MASK 0x3 -#define RT3883_FLASH_CFG_WIDTH_8BIT 0x0 -#define RT3883_FLASH_CFG_WIDTH_16BIT 0x1 -#define RT3883_FLASH_CFG_WIDTH_32BIT 0x2 - - -/* UART registers */ -#define RT3883_UART_REG_RX 0 -#define RT3883_UART_REG_TX 1 -#define RT3883_UART_REG_IER 2 -#define RT3883_UART_REG_IIR 3 -#define RT3883_UART_REG_FCR 4 -#define RT3883_UART_REG_LCR 5 -#define RT3883_UART_REG_MCR 6 -#define RT3883_UART_REG_LSR 7 - -#endif /* _RT3883_REGS_H_ */ diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/war.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/war.h deleted file mode 100644 index a7b712cf2d..0000000000 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/war.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle - */ -#ifndef __ASM_MACH_RALINK_WAR_H -#define __ASM_MACH_RALINK_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MACH_RALINK_WAR_H */ diff --git a/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c b/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c deleted file mode 100644 index f67902272c..0000000000 --- a/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c +++ /dev/null @@ -1,250 +0,0 @@ -/* - * Ralink RT288x SoC PCI register definitions - * - * Copyright (C) 2009 John Crispin - * Copyright (C) 2009 Gabor Juhos - * - * Parts of this file are based on Ralink's 2.6.21 BSP - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include - -#include -#include - -#define RT2880_PCI_MEM_BASE 0x20000000 -#define RT2880_PCI_MEM_SIZE 0x10000000 -#define RT2880_PCI_IO_BASE 0x00460000 -#define RT2880_PCI_IO_SIZE 0x00010000 - -#define RT2880_PCI_REG_PCICFG_ADDR 0x00 -#define RT2880_PCI_REG_PCIMSK_ADDR 0x0c -#define RT2880_PCI_REG_BAR0SETUP_ADDR 0x10 -#define RT2880_PCI_REG_IMBASEBAR0_ADDR 0x18 -#define RT2880_PCI_REG_CONFIG_ADDR 0x20 -#define RT2880_PCI_REG_CONFIG_DATA 0x24 -#define RT2880_PCI_REG_MEMBASE 0x28 -#define RT2880_PCI_REG_IOBASE 0x2c -#define RT2880_PCI_REG_ID 0x30 -#define RT2880_PCI_REG_CLASS 0x34 -#define RT2880_PCI_REG_SUBID 0x38 -#define RT2880_PCI_REG_ARBCTL 0x80 - -static void __iomem *rt2880_pci_base; -static DEFINE_SPINLOCK(rt2880_pci_lock); - -static u32 rt2880_pci_reg_read(u32 reg) -{ - return readl(rt2880_pci_base + reg); -} - -static void rt2880_pci_reg_write(u32 val, u32 reg) -{ - writel(val, rt2880_pci_base + reg); -} - -static inline u32 rt2880_pci_get_cfgaddr(unsigned int bus, unsigned int slot, - unsigned int func, unsigned int where) -{ - return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | - 0x80000000); -} - -static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *val) -{ - unsigned long flags; - u32 address; - u32 data; - - address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), - PCI_FUNC(devfn), where); - - spin_lock_irqsave(&rt2880_pci_lock, flags); - rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR); - data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA); - spin_unlock_irqrestore(&rt2880_pci_lock, flags); - - switch (size) { - case 1: - *val = (data >> ((where & 3) << 3)) & 0xff; - break; - case 2: - *val = (data >> ((where & 3) << 3)) & 0xffff; - break; - case 4: - *val = data; - break; - } - - return PCIBIOS_SUCCESSFUL; -} - -static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) -{ - unsigned long flags; - u32 address; - u32 data; - - address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), - PCI_FUNC(devfn), where); - - spin_lock_irqsave(&rt2880_pci_lock, flags); - rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR); - data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA); - - switch (size) { - case 1: - data = (data & ~(0xff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - break; - case 2: - data = (data & ~(0xffff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - break; - case 4: - data = val; - break; - } - - rt2880_pci_reg_write(data, RT2880_PCI_REG_CONFIG_DATA); - spin_unlock_irqrestore(&rt2880_pci_lock, flags); - - return PCIBIOS_SUCCESSFUL; -} - -static struct pci_ops rt2880_pci_ops = { - .read = rt2880_pci_config_read, - .write = rt2880_pci_config_write, -}; - -static struct resource rt2880_pci_mem_resource = { - .name = "PCI MEM space", - .start = RT2880_PCI_MEM_BASE, - .end = RT2880_PCI_MEM_BASE + RT2880_PCI_MEM_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - -static struct resource rt2880_pci_io_resource = { - .name = "PCI IO space", - .start = RT2880_PCI_IO_BASE, - .end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1, - .flags = IORESOURCE_IO, -}; - -static struct pci_controller rt2880_pci_controller = { - .pci_ops = &rt2880_pci_ops, - .mem_resource = &rt2880_pci_mem_resource, - .io_resource = &rt2880_pci_io_resource, -}; - -static inline u32 rt2880_pci_read_u32(unsigned long reg) -{ - unsigned long flags; - u32 address; - u32 ret; - - address = rt2880_pci_get_cfgaddr(0, 0, 0, reg); - - spin_lock_irqsave(&rt2880_pci_lock, flags); - rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR); - ret = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA); - spin_unlock_irqrestore(&rt2880_pci_lock, flags); - - return ret; -} - -static inline void rt2880_pci_write_u32(unsigned long reg, u32 val) -{ - unsigned long flags; - u32 address; - - address = rt2880_pci_get_cfgaddr(0, 0, 0, reg); - - spin_lock_irqsave(&rt2880_pci_lock, flags); - rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR); - rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA); - spin_unlock_irqrestore(&rt2880_pci_lock, flags); -} - -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - u16 cmd; - int irq = -1; - - if (dev->bus->number != 0) - return irq; - - switch (PCI_SLOT(dev->devfn)) { - case 0x00: - rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000); - (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0); - break; - case 0x11: - irq = RT288X_CPU_IRQ_PCI; - break; - default: - printk("%s:%s[%d] trying to alloc unknown pci irq\n", - __FILE__, __func__, __LINE__); - BUG(); - break; - } - - pci_write_config_byte((struct pci_dev*)dev, PCI_CACHE_LINE_SIZE, 0x14); - pci_write_config_byte((struct pci_dev*)dev, PCI_LATENCY_TIMER, 0xFF); - pci_read_config_word((struct pci_dev*)dev, PCI_COMMAND, &cmd); - cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK | - PCI_COMMAND_SERR | PCI_COMMAND_WAIT | PCI_COMMAND_PARITY; - pci_write_config_word((struct pci_dev*)dev, PCI_COMMAND, cmd); - pci_write_config_byte((struct pci_dev*)dev, PCI_INTERRUPT_LINE, - dev->irq); - return irq; -} - -int __init rt288x_register_pci(void) -{ - void __iomem *io_map_base; - int i; - - rt2880_pci_base = ioremap_nocache(RT2880_PCI_BASE, PAGE_SIZE); - - io_map_base = ioremap(RT2880_PCI_IO_BASE, RT2880_PCI_IO_SIZE); - rt2880_pci_controller.io_map_base = (unsigned long) io_map_base; - set_io_port_base((unsigned long) io_map_base); - - ioport_resource.start = RT2880_PCI_IO_BASE; - ioport_resource.end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1; - - rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR); - for(i = 0; i < 0xfffff; i++) {} - - rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL); - rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR); - rt2880_pci_reg_write(RT2880_PCI_MEM_BASE, RT2880_PCI_REG_MEMBASE); - rt2880_pci_reg_write(RT2880_PCI_IO_BASE, RT2880_PCI_REG_IOBASE); - rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR); - rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID); - rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS); - rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID); - rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR); - - rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000); - (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0); - - register_pci_controller(&rt2880_pci_controller); - return 0; -} - -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/target/linux/ramips/files/arch/mips/pci/pci-rt3883.c b/target/linux/ramips/files/arch/mips/pci/pci-rt3883.c deleted file mode 100644 index 8a4c8ce61a..0000000000 --- a/target/linux/ramips/files/arch/mips/pci/pci-rt3883.c +++ /dev/null @@ -1,487 +0,0 @@ -/* - * Ralink RT3883 SoC PCI support - * - * Copyright (C) 2011-2012 Gabor Juhos - * - * Parts of this file are based on Ralink's 2.6.21 BSP - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include - -#include -#include - -#define RT3883_MEMORY_BASE 0x00000000 -#define RT3883_MEMORY_SIZE 0x02000000 - -#define RT3883_PCI_MEM_BASE 0x20000000 -#define RT3883_PCI_MEM_SIZE 0x10000000 -#define RT3883_PCI_IO_BASE 0x10160000 -#define RT3883_PCI_IO_SIZE 0x00010000 - -#define RT3883_PCI_REG_PCICFG_ADDR 0x00 -#define RT3883_PCI_REG_PCIRAW_ADDR 0x04 -#define RT3883_PCI_REG_PCIINT_ADDR 0x08 -#define RT3883_PCI_REG_PCIMSK_ADDR 0x0c -#define RT3833_PCI_PCIINT_PCIE BIT(20) -#define RT3833_PCI_PCIINT_PCI1 BIT(19) -#define RT3833_PCI_PCIINT_PCI0 BIT(18) - -#define RT3883_PCI_REG_CONFIG_ADDR 0x20 -#define RT3883_PCI_REG_CONFIG_DATA 0x24 -#define RT3883_PCI_REG_MEMBASE 0x28 -#define RT3883_PCI_REG_IOBASE 0x2c -#define RT3883_PCI_REG_ARBCTL 0x80 - -#define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000) -#define RT3883_PCI_REG_BAR0SETUP_ADDR(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10) -#define RT3883_PCI_REG_IMBASEBAR0_ADDR(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18) -#define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30) -#define RT3883_PCI_REG_CLASS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x34) -#define RT3883_PCI_REG_SUBID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x38) -#define RT3883_PCI_REG_STATUS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x50) - -static int (*rt3883_pci_plat_dev_init)(struct pci_dev *dev); -static void __iomem *rt3883_pci_base; -static DEFINE_SPINLOCK(rt3883_pci_lock); - -static inline u32 rt3883_pci_rr(unsigned reg) -{ - return readl(rt3883_pci_base + reg); -} - -static inline void rt3883_pci_wr(u32 val, unsigned reg) -{ - writel(val, rt3883_pci_base + reg); -} - -static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot, - unsigned int func, unsigned int where) -{ - return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | - 0x80000000); -} - -static u32 rt3883_pci_read_u32(unsigned bus, unsigned slot, - unsigned func, unsigned reg) -{ - unsigned long flags; - u32 address; - u32 ret; - - address = rt3883_pci_get_cfgaddr(bus, slot, func, reg); - - spin_lock_irqsave(&rt3883_pci_lock, flags); - rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR); - ret = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA); - spin_unlock_irqrestore(&rt3883_pci_lock, flags); - - return ret; -} - -static void rt3883_pci_write_u32(unsigned bus, unsigned slot, - unsigned func, unsigned reg, u32 val) -{ - unsigned long flags; - u32 address; - - address = rt3883_pci_get_cfgaddr(bus, slot, func, reg); - - spin_lock_irqsave(&rt3883_pci_lock, flags); - rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR); - rt3883_pci_wr(val, RT3883_PCI_REG_CONFIG_DATA); - spin_unlock_irqrestore(&rt3883_pci_lock, flags); -} - -static void rt3883_pci_irq_handler(unsigned int irq, struct irq_desc *desc) -{ - u32 pending; - - pending = rt3883_pci_rr(RT3883_PCI_REG_PCIINT_ADDR) & - rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR); - - if (!pending) { - spurious_interrupt(); - return; - } - - if (pending & RT3833_PCI_PCIINT_PCI0) - generic_handle_irq(RT3883_PCI_IRQ_PCI0); - - if (pending & RT3833_PCI_PCIINT_PCI1) - generic_handle_irq(RT3883_PCI_IRQ_PCI1); - - if (pending & RT3833_PCI_PCIINT_PCIE) - generic_handle_irq(RT3883_PCI_IRQ_PCIE); -} - -static void rt3883_pci_irq_unmask(struct irq_data *d) -{ - int irq = d->irq; - u32 mask; - u32 t; - - switch (irq) { - case RT3883_PCI_IRQ_PCI0: - mask = RT3833_PCI_PCIINT_PCI0; - break; - case RT3883_PCI_IRQ_PCI1: - mask = RT3833_PCI_PCIINT_PCI1; - break; - case RT3883_PCI_IRQ_PCIE: - mask = RT3833_PCI_PCIINT_PCIE; - break; - default: - BUG(); - } - - t = rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR); - rt3883_pci_wr(t | mask, RT3883_PCI_REG_PCIMSK_ADDR); - /* flush write */ - rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR); -} - -static void rt3883_pci_irq_mask(struct irq_data *d) -{ - int irq = d->irq; - u32 mask; - u32 t; - - switch (irq) { - case RT3883_PCI_IRQ_PCI0: - mask = RT3833_PCI_PCIINT_PCI0; - break; - case RT3883_PCI_IRQ_PCI1: - mask = RT3833_PCI_PCIINT_PCI1; - break; - case RT3883_PCI_IRQ_PCIE: - mask = RT3833_PCI_PCIINT_PCIE; - break; - default: - BUG(); - } - - t = rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR); - rt3883_pci_wr(t & ~mask, RT3883_PCI_REG_PCIMSK_ADDR); - /* flush write */ - rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR); -} - -static struct irq_chip rt3883_pci_irq_chip = { - .name = "RT3883 PCI", - .irq_mask = rt3883_pci_irq_mask, - .irq_unmask = rt3883_pci_irq_unmask, - .irq_mask_ack = rt3883_pci_irq_mask, -}; - -static void __init rt3883_pci_irq_init(void) -{ - int i; - - /* disable all interrupts */ - rt3883_pci_wr(0, RT3883_PCI_REG_PCIMSK_ADDR); - - for (i = RT3883_PCI_IRQ_BASE; - i < RT3883_PCI_IRQ_BASE + RT3883_PCI_IRQ_COUNT; i++) { - irq_set_chip_and_handler(i, &rt3883_pci_irq_chip, - handle_level_irq); - } - - irq_set_chained_handler(RT3883_CPU_IRQ_PCI, rt3883_pci_irq_handler); -} - -static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *val) -{ - unsigned long flags; - u32 address; - u32 data; - - address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), - PCI_FUNC(devfn), where); - - spin_lock_irqsave(&rt3883_pci_lock, flags); - rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR); - data = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA); - spin_unlock_irqrestore(&rt3883_pci_lock, flags); - - switch (size) { - case 1: - *val = (data >> ((where & 3) << 3)) & 0xff; - break; - case 2: - *val = (data >> ((where & 3) << 3)) & 0xffff; - break; - case 4: - *val = data; - break; - } - - return PCIBIOS_SUCCESSFUL; -} - -static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) -{ - unsigned long flags; - u32 address; - u32 data; - - address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), - PCI_FUNC(devfn), where); - - spin_lock_irqsave(&rt3883_pci_lock, flags); - rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR); - data = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA); - - switch (size) { - case 1: - data = (data & ~(0xff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - break; - case 2: - data = (data & ~(0xffff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - break; - case 4: - data = val; - break; - } - - rt3883_pci_wr(data, RT3883_PCI_REG_CONFIG_DATA); - spin_unlock_irqrestore(&rt3883_pci_lock, flags); - - return PCIBIOS_SUCCESSFUL; -} - -static struct pci_ops rt3883_pci_ops = { - .read = rt3883_pci_config_read, - .write = rt3883_pci_config_write, -}; - -static struct resource rt3883_pci_mem_resource = { - .name = "PCI MEM space", - .start = RT3883_PCI_MEM_BASE, - .end = RT3883_PCI_MEM_BASE + RT3883_PCI_MEM_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - -static struct resource rt3883_pci_io_resource = { - .name = "PCI IO space", - .start = RT3883_PCI_IO_BASE, - .end = RT3883_PCI_IO_BASE + RT3883_PCI_IO_SIZE - 1, - .flags = IORESOURCE_IO, -}; - -static struct pci_controller rt3883_pci_controller = { - .pci_ops = &rt3883_pci_ops, - .mem_resource = &rt3883_pci_mem_resource, - .io_resource = &rt3883_pci_io_resource, -}; - -static void rt3883_pci_preinit(unsigned mode) -{ - u32 syscfg1; - u32 rstctrl; - u32 clkcfg1; - - if (mode & RT3883_PCI_MODE_PCIE) { - u32 val; - - val = rt3883_sysc_rr(RT3883_SYSC_REG_SYSCFG1); - val &= ~(0x30); - val |= (2 << 4); - rt3883_sysc_wr(val, RT3883_SYSC_REG_SYSCFG1); - - val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN0); - val &= ~BIT(31); - rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN0); - - val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN1); - val &= 0x80ffffff; - rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN1); - - val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN1); - val |= 0xa << 24; - rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN1); - - val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN0); - val |= BIT(31); - rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN0); - - msleep(50); - } - - syscfg1 = rt3883_sysc_rr(RT3883_SYSC_REG_SYSCFG1); - syscfg1 &= ~(RT3883_SYSCFG1_PCIE_RC_MODE | - RT3883_SYSCFG1_PCI_HOST_MODE); - - rstctrl = rt3883_sysc_rr(RT3883_SYSC_REG_RSTCTRL); - rstctrl |= (RT3883_RSTCTRL_PCI | RT3883_RSTCTRL_PCIE); - - clkcfg1 = rt3883_sysc_rr(RT3883_SYSC_REG_CLKCFG1); - clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN | - RT3883_CLKCFG1_PCIE_CLK_EN); - - if (mode & RT3883_PCI_MODE_PCI) { - syscfg1 |= RT3883_SYSCFG1_PCI_HOST_MODE; - clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN; - rstctrl &= ~RT3883_RSTCTRL_PCI; - } - if (mode & RT3883_PCI_MODE_PCIE) { - syscfg1 |= RT3883_SYSCFG1_PCI_HOST_MODE | - RT3883_SYSCFG1_PCIE_RC_MODE; - clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN; - rstctrl &= ~RT3883_RSTCTRL_PCIE; - } - - rt3883_sysc_wr(syscfg1, RT3883_SYSC_REG_SYSCFG1); - rt3883_sysc_wr(rstctrl, RT3883_SYSC_REG_RSTCTRL); - rt3883_sysc_wr(clkcfg1, RT3883_SYSC_REG_CLKCFG1); - - msleep(500); -} - -static int rt3883_pcie_ready(void) -{ - u32 status; - - msleep(500); - - status = rt3883_pci_rr(RT3883_PCI_REG_STATUS(1)); - if (status & BIT(0)) - return 0; - - /* TODO: reset PCIe and turn off PCIe clock */ - - return -ENODEV; -} - -void __init rt3883_pci_init(unsigned mode) -{ - u32 val; - int err; - - rt3883_pci_preinit(mode); - - rt3883_pci_base = ioremap(RT3883_PCI_BASE, PAGE_SIZE); - if (rt3883_pci_base == NULL) { - pr_err("failed to ioremap PCI registers\n"); - return; - } - - rt3883_pci_wr(0, RT3883_PCI_REG_PCICFG_ADDR); - if (mode & RT3883_PCI_MODE_PCI) - rt3883_pci_wr(BIT(16), RT3883_PCI_REG_PCICFG_ADDR); - - msleep(500); - - if (mode & RT3883_PCI_MODE_PCIE) { - err = rt3883_pcie_ready(); - if (err) - return; - } - - if (mode & RT3883_PCI_MODE_PCI) - rt3883_pci_wr(0x79, RT3883_PCI_REG_ARBCTL); - - rt3883_pci_wr(RT3883_PCI_MEM_BASE, RT3883_PCI_REG_MEMBASE); - rt3883_pci_wr(RT3883_PCI_IO_BASE, RT3883_PCI_REG_IOBASE); - - /* PCI */ - rt3883_pci_wr(0x03ff0000, RT3883_PCI_REG_BAR0SETUP_ADDR(0)); - rt3883_pci_wr(RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0_ADDR(0)); - rt3883_pci_wr(0x08021814, RT3883_PCI_REG_ID(0)); - rt3883_pci_wr(0x00800001, RT3883_PCI_REG_CLASS(0)); - rt3883_pci_wr(0x28801814, RT3883_PCI_REG_SUBID(0)); - - /* PCIe */ - rt3883_pci_wr(0x01ff0000, RT3883_PCI_REG_BAR0SETUP_ADDR(1)); - rt3883_pci_wr(RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0_ADDR(1)); - rt3883_pci_wr(0x08021814, RT3883_PCI_REG_ID(1)); - rt3883_pci_wr(0x06040001, RT3883_PCI_REG_CLASS(1)); - rt3883_pci_wr(0x28801814, RT3883_PCI_REG_SUBID(1)); - - rt3883_pci_irq_init(); - - /* PCIe */ - val = rt3883_pci_read_u32(0, 0x01, 0, PCI_COMMAND); - val |= 0x7; - rt3883_pci_write_u32(0, 0x01, 0, PCI_COMMAND, val); - - /* PCI */ - val = rt3883_pci_read_u32(0, 0x00, 0, PCI_COMMAND); - val |= 0x7; - rt3883_pci_write_u32(0, 0x00, 0, PCI_COMMAND, val); - - ioport_resource.start = rt3883_pci_io_resource.start; - ioport_resource.end = rt3883_pci_io_resource.end; - - register_pci_controller(&rt3883_pci_controller); -} - -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - int irq = -1; - - switch (dev->bus->number) { - case 0: - switch (PCI_SLOT(dev->devfn)) { - case 0x00: - rt3883_pci_wr(0x03ff0001, - RT3883_PCI_REG_BAR0SETUP_ADDR(0)); - rt3883_pci_wr(0x03ff0001, - RT3883_PCI_REG_BAR0SETUP_ADDR(1)); - - rt3883_pci_write_u32(0, 0x00, 0, PCI_BASE_ADDRESS_0, - RT3883_MEMORY_BASE); - rt3883_pci_read_u32(0, 0x00, 0, PCI_BASE_ADDRESS_0); - - irq = RT3883_CPU_IRQ_PCI; - break; - case 0x01: - rt3883_pci_write_u32(0, 0x01, 0, PCI_IO_BASE, - 0x00000101); - break; - case 0x11: - irq = RT3883_PCI_IRQ_PCI0; - break; - case 0x12: - irq = RT3883_PCI_IRQ_PCI1; - break; - } - break; - - case 1: - irq = RT3883_PCI_IRQ_PCIE; - break; - - default: - dev_err(&dev->dev, "no IRQ specified\n"); - return irq; - } - - return irq; -} - -void __init rt3883_pci_set_plat_dev_init(int (*f)(struct pci_dev *dev)) -{ - rt3883_pci_plat_dev_init = f; -} - -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - if (rt3883_pci_plat_dev_init) - return rt3883_pci_plat_dev_init(dev); - - return 0; -} diff --git a/target/linux/ramips/files/arch/mips/ralink/Kconfig b/target/linux/ramips/files/arch/mips/ralink/Kconfig deleted file mode 100644 index 74bca6d0e9..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/Kconfig +++ /dev/null @@ -1,83 +0,0 @@ -if MIPS_RALINK - -choice - prompt "Ralink SoC selection" - default SOC_RT288X - help - Select Ralink MIPS SoC type. - - config RALINK_RT288X - bool "RT288x" - select SOC_RT288X - - config RALINK_RT305X - bool "RT305x" - select SOC_RT305X - - config RALINK_RT3883 - bool "RT3883" - select SOC_RT3883 - -endchoice - -source "arch/mips/ralink/rt288x/Kconfig" -source "arch/mips/ralink/rt305x/Kconfig" -source "arch/mips/ralink/rt3883/Kconfig" - -config SOC_RT288X - bool - select CEVT_R4K - select CSRC_R4K - select DMA_NONCOHERENT - select IRQ_CPU - select ARCH_REQUIRE_GPIOLIB - select SYS_HAS_CPU_MIPS32_R1 - select SYS_HAS_CPU_MIPS32_R2 - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_HAS_EARLY_PRINTK - select MIPS_MACHINE - select HAVE_CLK - -config SOC_RT305X - bool - select CEVT_R4K - select CSRC_R4K - select DMA_NONCOHERENT - select IRQ_CPU - select ARCH_REQUIRE_GPIOLIB - select SYS_HAS_CPU_MIPS32_R1 - select SYS_HAS_CPU_MIPS32_R2 - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_HAS_EARLY_PRINTK - select MIPS_MACHINE - select USB_ARCH_HAS_HCD - select USB_ARCH_HAS_OHCI - select USB_ARCH_HAS_EHCI - select HAVE_CLK - -config SOC_RT3883 - bool - select CEVT_R4K - select CSRC_R4K - select DMA_NONCOHERENT - select IRQ_CPU - select ARCH_REQUIRE_GPIOLIB - select SYS_HAS_CPU_MIPS32_R1 - select SYS_HAS_CPU_MIPS32_R2 - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_HAS_EARLY_PRINTK - select MIPS_MACHINE - select USB_ARCH_HAS_OHCI - select USB_ARCH_HAS_EHCI - select HAVE_CLK - -config RALINK_DEV_GPIO_BUTTONS - def_bool n - -config RALINK_DEV_GPIO_LEDS - def_bool n - -endif diff --git a/target/linux/ramips/files/arch/mips/ralink/Platform b/target/linux/ramips/files/arch/mips/ralink/Platform deleted file mode 100644 index 1b540492c2..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/Platform +++ /dev/null @@ -1,26 +0,0 @@ -# -# Ralink SoC common stuff -# -core-$(CONFIG_MIPS_RALINK) += arch/mips/ralink/common/ -cflags-$(CONFIG_MIPS_RALINK) += -I$(srctree)/arch/mips/include/asm/mach-ralink - -# -# Ralink RT288x -# -core-$(CONFIG_RALINK_RT288X) += arch/mips/ralink/rt288x/ -cflags-$(CONFIG_RALINK_RT288X) += -I$(srctree)//arch/mips/include/asm/mach-ralink/rt288x -load-$(CONFIG_RALINK_RT288X) += 0xffffffff88000000 - -# -# Ralink RT305x -# -core-$(CONFIG_RALINK_RT305X) += arch/mips/ralink/rt305x/ -cflags-$(CONFIG_RALINK_RT305X) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt305x -load-$(CONFIG_RALINK_RT305X) += 0xffffffff80000000 - -# -# Ralink RT3883 -# -core-$(CONFIG_RALINK_RT3883) += arch/mips/ralink/rt3883/ -cflags-$(CONFIG_RALINK_RT3883) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt3883 -load-$(CONFIG_RALINK_RT3883) += 0xffffffff80000000 diff --git a/target/linux/ramips/files/arch/mips/ralink/common/Makefile b/target/linux/ramips/files/arch/mips/ralink/common/Makefile deleted file mode 100644 index adab85f689..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/common/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# Makefile for the Ralink common stuff -# -# Copyright (C) 2009-2010 Gabor Juhos -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of the GNU General Public License version 2 as published -# by the Free Software Foundation. - -obj-y := prom.o setup.o intc.o gpio.o - -obj-$(CONFIG_RALINK_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o -obj-$(CONFIG_RALINK_DEV_GPIO_LEDS) += dev-gpio-leds.o diff --git a/target/linux/ramips/files/arch/mips/ralink/common/dev-gpio-buttons.c b/target/linux/ramips/files/arch/mips/ralink/common/dev-gpio-buttons.c deleted file mode 100644 index 75a2a17143..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/common/dev-gpio-buttons.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Ralink SoC GPIO button support - * - * Copyright (C) 2010 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include "linux/init.h" -#include -#include - -#include - -void __init ramips_register_gpio_buttons(int id, - unsigned poll_interval, - unsigned nbuttons, - struct gpio_keys_button *buttons) -{ - struct platform_device *pdev; - struct gpio_keys_platform_data pdata; - struct gpio_keys_button *p; - int err; - - p = kmalloc(nbuttons * sizeof(*p), GFP_KERNEL); - if (!p) - return; - - memcpy(p, buttons, nbuttons * sizeof(*p)); - - pdev = platform_device_alloc("gpio-keys-polled", id); - if (!pdev) - goto err_free_buttons; - - memset(&pdata, 0, sizeof(pdata)); - pdata.poll_interval = poll_interval; - pdata.nbuttons = nbuttons; - pdata.buttons = p; - - err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); - if (err) - goto err_put_pdev; - - err = platform_device_add(pdev); - if (err) - goto err_put_pdev; - - return; - -err_put_pdev: - platform_device_put(pdev); - -err_free_buttons: - kfree(p); -} diff --git a/target/linux/ramips/files/arch/mips/ralink/common/dev-gpio-leds.c b/target/linux/ramips/files/arch/mips/ralink/common/dev-gpio-leds.c deleted file mode 100644 index a45a7cb779..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/common/dev-gpio-leds.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Ralink SoC GPIO LED device support - * - * Copyright (C) 2009 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include - -#include - -void __init ramips_register_gpio_leds(int id, unsigned num_leds, - struct gpio_led *leds) -{ - struct platform_device *pdev; - struct gpio_led_platform_data pdata; - struct gpio_led *p; - int err; - - p = kmalloc(num_leds * sizeof(*p), GFP_KERNEL); - if (!p) - return; - - memcpy(p, leds, num_leds * sizeof(*p)); - - pdev = platform_device_alloc("leds-gpio", id); - if (!pdev) - goto err_free_leds; - - memset(&pdata, 0, sizeof(pdata)); - pdata.num_leds = num_leds; - pdata.leds = p; - - err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); - if (err) - goto err_put_pdev; - - err = platform_device_add(pdev); - if (err) - goto err_put_pdev; - - return; - -err_put_pdev: - platform_device_put(pdev); - -err_free_leds: - kfree(p); -} diff --git a/target/linux/ramips/files/arch/mips/ralink/common/gpio.c b/target/linux/ramips/files/arch/mips/ralink/common/gpio.c deleted file mode 100644 index f03d145b6d..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/common/gpio.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Ralink SoC specific GPIO support - * - * Copyright (C) 2009-2011 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include - -#include - -static inline struct ramips_gpio_chip *to_ramips_gpio(struct gpio_chip *chip) -{ - struct ramips_gpio_chip *rg; - - rg = container_of(chip, struct ramips_gpio_chip, chip); - return rg; -} - -static inline void ramips_gpio_wr(struct ramips_gpio_chip *rg, u8 reg, u32 val) -{ - __raw_writel(val, rg->regs_base + rg->regs[reg]); -} - -static inline u32 ramips_gpio_rr(struct ramips_gpio_chip *rg, u8 reg) -{ - return __raw_readl(rg->regs_base + rg->regs[reg]); -} - -static int ramips_gpio_direction_input(struct gpio_chip *chip, unsigned offset) -{ - struct ramips_gpio_chip *rg = to_ramips_gpio(chip); - unsigned long flags; - u32 t; - - spin_lock_irqsave(&rg->lock, flags); - t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DIR); - t &= ~(1 << offset); - ramips_gpio_wr(rg, RAMIPS_GPIO_REG_DIR, t); - spin_unlock_irqrestore(&rg->lock, flags); - - return 0; -} - -static int ramips_gpio_direction_output(struct gpio_chip *chip, - unsigned offset, int value) -{ - struct ramips_gpio_chip *rg = to_ramips_gpio(chip); - unsigned long flags; - u32 reg; - u32 t; - - reg = (value) ? RAMIPS_GPIO_REG_SET : RAMIPS_GPIO_REG_RESET; - - spin_lock_irqsave(&rg->lock, flags); - ramips_gpio_wr(rg, reg, 1 << offset); - - t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DIR); - t |= 1 << offset; - ramips_gpio_wr(rg, RAMIPS_GPIO_REG_DIR, t); - spin_unlock_irqrestore(&rg->lock, flags); - - return 0; -} - -static void ramips_gpio_set(struct gpio_chip *chip, unsigned offset, int value) -{ - struct ramips_gpio_chip *rg = to_ramips_gpio(chip); - u32 reg; - - reg = (value) ? RAMIPS_GPIO_REG_SET : RAMIPS_GPIO_REG_RESET; - ramips_gpio_wr(rg, reg, 1 << offset); -} - -static int ramips_gpio_get(struct gpio_chip *chip, unsigned offset) -{ - struct ramips_gpio_chip *rg = to_ramips_gpio(chip); - u32 t; - - t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DATA); - return !!(t & (1 << offset)); -} - -static __init void ramips_gpio_chip_add(struct ramips_gpio_chip *rg) -{ - spin_lock_init(&rg->lock); - - rg->regs_base = ioremap(rg->map_base, rg->map_size); - - rg->chip.direction_input = ramips_gpio_direction_input; - rg->chip.direction_output = ramips_gpio_direction_output; - rg->chip.get = ramips_gpio_get; - rg->chip.set = ramips_gpio_set; - - /* set polarity to low for all lines */ - ramips_gpio_wr(rg, RAMIPS_GPIO_REG_POL, 0); - - gpiochip_add(&rg->chip); -} - -__init int ramips_gpio_init(struct ramips_gpio_data *data) -{ - int i; - - for (i = 0; i < data->num_chips; i++) - ramips_gpio_chip_add(&data->chips[i]); - - return 0; -} diff --git a/target/linux/ramips/files/arch/mips/ralink/common/intc.c b/target/linux/ramips/files/arch/mips/ralink/common/intc.c deleted file mode 100644 index 65e42b423b..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/common/intc.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Ralink SoC Interrupt controller routines - * - * Copyright (C) 2009 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include - -#include -#include - -#include - -/* INTC register offsets */ -#define INTC_REG_STATUS0 0x00 -#define INTC_REG_STATUS1 0x04 -#define INTC_REG_TYPE 0x20 -#define INTC_REG_RAW_STATUS 0x30 -#define INTC_REG_ENABLE 0x34 -#define INTC_REG_DISABLE 0x38 - -#define INTC_INT_GLOBAL BIT(31) -#define INTC_IRQ_COUNT 32 - -static unsigned int ramips_intc_irq_base; -static void __iomem *ramips_intc_base; - -static inline void ramips_intc_wr(u32 val, unsigned reg) -{ - __raw_writel(val, ramips_intc_base + reg); -} - -static inline u32 ramips_intc_rr(unsigned reg) -{ - return __raw_readl(ramips_intc_base + reg); -} - -static void ramips_intc_irq_unmask(struct irq_data *d) -{ - unsigned int irq = d->irq - ramips_intc_irq_base; - - ramips_intc_wr((1 << irq), INTC_REG_ENABLE); -} - -static void ramips_intc_irq_mask(struct irq_data *d) -{ - unsigned int irq = d->irq - ramips_intc_irq_base; - - ramips_intc_wr((1 << irq), INTC_REG_DISABLE); -} - -static struct irq_chip ramips_intc_irq_chip = { - .name = "INTC", - .irq_unmask = ramips_intc_irq_unmask, - .irq_mask = ramips_intc_irq_mask, - .irq_mask_ack = ramips_intc_irq_mask, -}; - -static struct irqaction ramips_intc_irqaction = { - .handler = no_action, - .name = "cascade [INTC]", -}; - -void __init ramips_intc_irq_init(unsigned intc_base, unsigned irq, - unsigned irq_base) -{ - int i; - - ramips_intc_base = ioremap_nocache(intc_base, PAGE_SIZE); - ramips_intc_irq_base = irq_base; - - /* disable all interrupts */ - ramips_intc_wr(~0, INTC_REG_DISABLE); - - /* route all INTC interrupts to MIPS HW0 interrupt */ - ramips_intc_wr(0, INTC_REG_TYPE); - - for (i = ramips_intc_irq_base; - i < ramips_intc_irq_base + INTC_IRQ_COUNT; i++) - irq_set_chip_and_handler(i, &ramips_intc_irq_chip, - handle_level_irq); - - setup_irq(irq, &ramips_intc_irqaction); - ramips_intc_wr(INTC_INT_GLOBAL, INTC_REG_ENABLE); -} - -u32 ramips_intc_get_status(void) -{ - return ramips_intc_rr(INTC_REG_STATUS0); -} diff --git a/target/linux/ramips/files/arch/mips/ralink/common/prom.c b/target/linux/ramips/files/arch/mips/ralink/common/prom.c deleted file mode 100644 index 26169d366d..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/common/prom.c +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Ralink SoC specific prom routines - * - * Copyright (C) 2010 Joonas Lahtinen - * Copyright (C) 2009 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include - -#include -#include - -#include -#include - -unsigned long ramips_mem_base; -unsigned long ramips_mem_size_min; -unsigned long ramips_mem_size_max; - -static inline void *to_ram_addr(void *addr) -{ - u32 base; - - base = KSEG0ADDR(ramips_mem_base); - if (((u32) addr > base) && - ((u32) addr < (base + ramips_mem_size_max))) - return addr; - - base = KSEG1ADDR(ramips_mem_base); - if (((u32) addr > base) && - ((u32) addr < (base + ramips_mem_size_max))) - return addr; - - /* some U-Boot variants uses physical addresses */ - base = ramips_mem_base; - if (((u32) addr > base) && - ((u32) addr < (base + ramips_mem_size_max))) - return (void *)KSEG0ADDR(addr); - - return NULL; -} - -static char ramips_cmdline_buf[COMMAND_LINE_SIZE] __initdata; -static void __init prom_append_cmdline(const char *name, - const char *value) -{ - snprintf(ramips_cmdline_buf, sizeof(ramips_cmdline_buf), - " %s=%s", name, value); - strlcat(arcs_cmdline, ramips_cmdline_buf, sizeof(arcs_cmdline)); -} - -#ifdef CONFIG_IMAGE_CMDLINE_HACK -extern char __image_cmdline[]; - -static int __init use_image_cmdline(void) -{ - char *p = __image_cmdline; - int replace = 0; - - if (*p == '-') { - replace = 1; - p++; - } - - if (*p == '\0') - return 0; - - if (replace) { - strlcpy(arcs_cmdline, p, sizeof(arcs_cmdline)); - } else { - strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); - strlcat(arcs_cmdline, p, sizeof(arcs_cmdline)); - } - - return 1; -} -#else -static int inline use_image_cmdline(void) { return 0; } -#endif - -static __init void prom_init_cmdline(int argc, char **argv) -{ - int i; - - if (use_image_cmdline()) - return; - - if (!argv) { - printk(KERN_DEBUG "argv=%p is invalid, skipping\n", - argv); - return; - } - - for (i = 0; i < argc; i++) { - char *p = to_ram_addr(argv[i]); - - if (!p) { - printk(KERN_DEBUG - "argv[%d]=%p is invalid, skipping\n", - i, argv[i]); - continue; - } - - printk(KERN_DEBUG "argv[%d]: %s\n", i, p); - strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); - strlcat(arcs_cmdline, p, sizeof(arcs_cmdline)); - } -} - -static __init char *prom_append_env(char **env, const char *envname) -{ -#define PROM_MAX_ENVS 256 - int len = strlen(envname); - int i; - - if (!env) { - printk(KERN_DEBUG "env=%p is not in RAM, skipping\n", - env); - return NULL; - } - - for (i = 0; i < PROM_MAX_ENVS; i++) { - char *p = to_ram_addr(env[i]); - - if (!p) - break; - - printk(KERN_DEBUG "env[%d]: %s\n", i, p); - if (strncmp(envname, p, len) == 0 && p[len] == '=') - prom_append_cmdline(envname, p + len + 1); - } - - return NULL; -#undef PROM_MAX_ENVS -} - -void __init prom_init(void) -{ - int argc; - char **envp; - char **argv; - - ramips_soc_prom_init(); - - printk(KERN_DEBUG - "prom: fw_arg0=%08x, fw_arg1=%08x, fw_arg2=%08x, fw_arg3=%08x\n", - (unsigned int)fw_arg0, (unsigned int)fw_arg1, - (unsigned int)fw_arg2, (unsigned int)fw_arg3); - - argc = fw_arg0; - argv = to_ram_addr((void *)fw_arg1); - prom_init_cmdline(argc, argv); - - envp = to_ram_addr((void *)fw_arg2); - prom_append_env(envp, "board"); - prom_append_env(envp, "ethaddr"); -} - -void __init prom_free_prom_memory(void) -{ - /* We do not have to prom memory to free */ -} diff --git a/target/linux/ramips/files/arch/mips/ralink/common/setup.c b/target/linux/ramips/files/arch/mips/ralink/common/setup.c deleted file mode 100644 index 1af855e649..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/common/setup.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Ralink SoC common setup - * - * Copyright (C) 2008-2009 Gabor Juhos - * Copyright (C) 2008 Imre Kaloz - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include - -#include -#include - -#include -#include - -unsigned char ramips_sys_type[RAMIPS_SYS_TYPE_LEN]; -unsigned long (*ramips_get_mem_size)(void); - -const char *get_system_type(void) -{ - return ramips_sys_type; -} - -static void __init detect_mem_size(void) -{ - unsigned long size; - - if (ramips_get_mem_size) { - size = ramips_get_mem_size(); - } else { - void *base; - - base = (void *) KSEG1ADDR(detect_mem_size); - for (size = ramips_mem_size_min; size < ramips_mem_size_max; - size <<= 1 ) { - if (!memcmp(base, base + size, 1024)) - break; - } - } - - add_memory_region(ramips_mem_base, size, BOOT_MEM_RAM); -} - -void __init ramips_early_serial_setup(int line, unsigned base, unsigned freq, - unsigned irq) -{ - struct uart_port p; - int err; - - memset(&p, 0, sizeof(p)); - p.flags = UPF_SKIP_TEST | UPF_FIXED_TYPE; - p.iotype = UPIO_AU; - p.uartclk = freq; - p.regshift = 2; - p.type = PORT_16550A; - - p.mapbase = base; - p.membase = ioremap_nocache(p.mapbase, PAGE_SIZE); - p.line = line; - p.irq = irq; - - err = early_serial_setup(&p); - if (err) - printk(KERN_ERR "early serial%d registration failed %d\n", - line, err); -} - -void __init plat_mem_setup(void) -{ - set_io_port_base(KSEG1); - - detect_mem_size(); - ramips_soc_setup(); -} - -__setup("board=", mips_machtype_setup); - -static int __init ramips_machine_setup(void) -{ - mips_machine_setup(); - return 0; -} - -arch_initcall(ramips_machine_setup); - -static void __init ramips_generic_init(void) -{ -} - -MIPS_MACHINE(RAMIPS_MACH_GENERIC, "Generic", "Generic Ralink board", - ramips_generic_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt288x/Kconfig b/target/linux/ramips/files/arch/mips/ralink/rt288x/Kconfig deleted file mode 100644 index 739561c640..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt288x/Kconfig +++ /dev/null @@ -1,36 +0,0 @@ -if RALINK_RT288X - -menu "Ralink RT288x machine selection" - -config RT288X_MACH_F5D8235_V1 - bool "Belkin F5D8235 V1 board support" - select RALINK_DEV_GPIO_LEDS - -config RT288X_MACH_BR6524N - bool "Edimax BR6524N support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT288X_MACH_RT_N15 - bool "Asus RT-N15 board support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT288X_MACH_V11ST_FE - bool "Ralink V11ST-FE board support" - select HW_HAS_PCI - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT288X_MACH_WLI_TX4_AG300N - bool "Buffalo WLI-TX4-AG300N board support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT288X_MACH_WZR_AGL300NH - bool "Buffalo WZR-AGL300NH board support" - select RALINK_DEV_GPIO_LEDS - -endmenu - -endif diff --git a/target/linux/ramips/files/arch/mips/ralink/rt288x/Makefile b/target/linux/ramips/files/arch/mips/ralink/rt288x/Makefile deleted file mode 100644 index eb60c5d10d..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt288x/Makefile +++ /dev/null @@ -1,21 +0,0 @@ -# -# Makefile for the Ralink RT288x SoC specific parts of the kernel -# -# Copyright (C) 2010 Joonas Lahtinen -# Copyright (C) 2008-2009 Gabor Juhos -# Copyright (C) 2008 Imre Kaloz -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of the GNU General Public License version 2 as published -# by the Free Software Foundation. - -obj-y := irq.o setup.o rt288x.o devices.o clock.o - -obj-$(CONFIG_EARLY_PRINTK) += early_printk.o - -obj-$(CONFIG_RT288X_MACH_F5D8235_V1) += mach-f5d8235-v1.o -obj-$(CONFIG_RT288X_MACH_BR6524N) += mach-br6524n.o -obj-$(CONFIG_RT288X_MACH_RT_N15) += mach-rt-n15.o -obj-$(CONFIG_RT288X_MACH_V11ST_FE) += mach-v11st-fe.o -obj-$(CONFIG_RT288X_MACH_WLI_TX4_AG300N) += mach-wli-tx4-ag300n.o -obj-$(CONFIG_RT288X_MACH_WZR_AGL300NH) += mach-wzr-agl300nh.o diff --git a/target/linux/ramips/files/arch/mips/ralink/rt288x/clock.c b/target/linux/ramips/files/arch/mips/ralink/rt288x/clock.c deleted file mode 100644 index 36d754dbf6..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt288x/clock.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Ralink RT288X clock API - * - * Copyright (C) 2011 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include "common.h" - -struct clk { - unsigned long rate; -}; - -static struct clk rt288x_cpu_clk; -static struct clk rt288x_sys_clk; -static struct clk rt288x_wdt_clk; -static struct clk rt288x_uart_clk; - -void __init rt288x_clocks_init(void) -{ - u32 t; - - t = rt288x_sysc_rr(SYSC_REG_SYSTEM_CONFIG); - t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK); - - switch (t) { - case SYSTEM_CONFIG_CPUCLK_250: - rt288x_cpu_clk.rate = 250000000; - break; - case SYSTEM_CONFIG_CPUCLK_266: - rt288x_cpu_clk.rate = 266666667; - break; - case SYSTEM_CONFIG_CPUCLK_280: - rt288x_cpu_clk.rate = 280000000; - break; - case SYSTEM_CONFIG_CPUCLK_300: - rt288x_cpu_clk.rate = 300000000; - break; - } - - rt288x_sys_clk.rate = rt288x_cpu_clk.rate / 2; - rt288x_uart_clk.rate = rt288x_sys_clk.rate; - rt288x_wdt_clk.rate = rt288x_sys_clk.rate; -} - -/* - * Linux clock API - */ -struct clk *clk_get(struct device *dev, const char *id) -{ - if (!strcmp(id, "sys")) - return &rt288x_sys_clk; - - if (!strcmp(id, "cpu")) - return &rt288x_cpu_clk; - - if (!strcmp(id, "wdt")) - return &rt288x_wdt_clk; - - if (!strcmp(id, "uart")) - return &rt288x_uart_clk; - - return ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(clk_get); - -int clk_enable(struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - return clk->rate; -} -EXPORT_SYMBOL(clk_get_rate); - -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt288x/common.h b/target/linux/ramips/files/arch/mips/ralink/rt288x/common.h deleted file mode 100644 index f2415c58ba..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt288x/common.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Ralink RT288X SoC common defines - * - * Copyright (C) 2011 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef _RT288X_COMMON_H -#define _RT288X_COMMON_H - -void rt288x_clocks_init(void); - -#endif /* _RT288X_COMMON_H */ \ No newline at end of file diff --git a/target/linux/ramips/files/arch/mips/ralink/rt288x/devices.c b/target/linux/ramips/files/arch/mips/ralink/rt288x/devices.c deleted file mode 100644 index 196810a30f..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt288x/devices.c +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Ralink RT288x SoC platform device registration - * - * Copyright (C) 2008-2011 Gabor Juhos - * Copyright (C) 2008 Imre Kaloz - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include - -#include "devices.h" - -static struct resource rt288x_flash0_resources[] = { - { - .flags = IORESOURCE_MEM, - .start = KSEG1ADDR(RT2880_FLASH0_BASE), - .end = KSEG1ADDR(RT2880_FLASH0_BASE) + - RT2880_FLASH0_SIZE - 1, - }, -}; - -struct physmap_flash_data rt288x_flash0_data; -static struct platform_device rt288x_flash0_device = { - .name = "physmap-flash", - .resource = rt288x_flash0_resources, - .num_resources = ARRAY_SIZE(rt288x_flash0_resources), - .dev = { - .platform_data = &rt288x_flash0_data, - }, -}; - -static struct resource rt288x_flash1_resources[] = { - { - .flags = IORESOURCE_MEM, - .start = KSEG1ADDR(RT2880_FLASH1_BASE), - .end = KSEG1ADDR(RT2880_FLASH1_BASE) + - RT2880_FLASH1_SIZE - 1, - }, -}; - -struct physmap_flash_data rt288x_flash1_data; -static struct platform_device rt288x_flash1_device = { - .name = "physmap-flash", - .resource = rt288x_flash1_resources, - .num_resources = ARRAY_SIZE(rt288x_flash1_resources), - .dev = { - .platform_data = &rt288x_flash1_data, - }, -}; - -static int rt288x_flash_instance __initdata; -void __init rt288x_register_flash(unsigned int id) -{ - struct platform_device *pdev; - struct physmap_flash_data *pdata; - u32 t; - int reg; - - switch (id) { - case 0: - pdev = &rt288x_flash0_device; - reg = MEMC_REG_FLASH_CFG0; - break; - case 1: - pdev = &rt288x_flash1_device; - reg = MEMC_REG_FLASH_CFG1; - break; - default: - return; - } - - t = rt288x_memc_rr(reg); - t = (t >> FLASH_CFG_WIDTH_SHIFT) & FLASH_CFG_WIDTH_MASK; - - pdata = pdev->dev.platform_data; - switch (t) { - case FLASH_CFG_WIDTH_8BIT: - pdata->width = 1; - break; - case FLASH_CFG_WIDTH_16BIT: - pdata->width = 2; - break; - case FLASH_CFG_WIDTH_32BIT: - pdata->width = 4; - break; - default: - printk(KERN_ERR "RT288x: flash bank%u witdh is invalid\n", id); - return; - } - - pdev->id = rt288x_flash_instance; - - platform_device_register(pdev); - rt288x_flash_instance++; -} - -static struct resource rt288x_wifi_resources[] = { - { - .start = RT2880_WMAC_BASE, - .end = RT2880_WMAC_BASE + 0x3FFFF, - .flags = IORESOURCE_MEM, - }, { - .start = RT288X_CPU_IRQ_WNIC, - .end = RT288X_CPU_IRQ_WNIC, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct rt2x00_platform_data rt288x_wifi_data; -static struct platform_device rt288x_wifi_device = { - .name = "rt2800_wmac", - .resource = rt288x_wifi_resources, - .num_resources = ARRAY_SIZE(rt288x_wifi_resources), - .dev = { - .platform_data = &rt288x_wifi_data, - } -}; - -void __init rt288x_register_wifi(void) -{ - rt288x_wifi_data.eeprom_file_name = "soc_wmac.eeprom"; - platform_device_register(&rt288x_wifi_device); -} - -static void rt288x_fe_reset(void) -{ - rt288x_sysc_wr(RT2880_RESET_FE, SYSC_REG_RESET_CTRL); -} - -static struct resource rt288x_eth_resources[] = { - { - .start = RT2880_FE_BASE, - .end = RT2880_FE_BASE + PAGE_SIZE - 1, - .flags = IORESOURCE_MEM, - }, { - .start = RT288X_CPU_IRQ_FE, - .end = RT288X_CPU_IRQ_FE, - .flags = IORESOURCE_IRQ, - }, -}; - -struct ramips_eth_platform_data rt288x_eth_data; -static struct platform_device rt288x_eth_device = { - .name = "ramips_eth", - .resource = rt288x_eth_resources, - .num_resources = ARRAY_SIZE(rt288x_eth_resources), - .dev = { - .platform_data = &rt288x_eth_data, - } -}; - -void __init rt288x_register_ethernet(void) -{ - struct clk *clk; - - clk = clk_get(NULL, "sys"); - if (IS_ERR(clk)) - panic("unable to get SYS clock, err=%ld", PTR_ERR(clk)); - - rt288x_eth_data.sys_freq = clk_get_rate(clk); - rt288x_eth_data.reset_fe = rt288x_fe_reset; - rt288x_eth_data.min_pkt_len = 64; - - if (!is_valid_ether_addr(rt288x_eth_data.mac)) - random_ether_addr(rt288x_eth_data.mac); - - platform_device_register(&rt288x_eth_device); -} - -static struct resource rt288x_wdt_resources[] = { - { - .start = RT2880_TIMER_BASE, - .end = RT2880_TIMER_BASE + RT2880_TIMER_SIZE - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device rt288x_wdt_device = { - .name = "ramips-wdt", - .id = -1, - .resource = rt288x_wdt_resources, - .num_resources = ARRAY_SIZE(rt288x_wdt_resources), -}; - -void __init rt288x_register_wdt(void) -{ - u32 t; - - /* enable WDT reset output on pin SRAM_CS_N */ - t = rt288x_sysc_rr(SYSC_REG_CLKCFG); - t |= CLKCFG_SRAM_CS_N_WDT; - rt288x_sysc_wr(t, SYSC_REG_CLKCFG); - - platform_device_register(&rt288x_wdt_device); -} diff --git a/target/linux/ramips/files/arch/mips/ralink/rt288x/devices.h b/target/linux/ramips/files/arch/mips/ralink/rt288x/devices.h deleted file mode 100644 index d097e5d90e..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt288x/devices.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Ralink RT288x SoC specific platform definitions - * - * Copyright (C) 2008-2011 Gabor Juhos - * Copyright (C) 2008 Imre Kaloz - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef __ASM_MACH_RT288X_PLATFORM_H -#define __ASM_MACH_RT288X_PLATFORM_H - -struct physmap_flash_data; - -extern struct physmap_flash_data rt288x_flash0_data; -extern struct physmap_flash_data rt288x_flash1_data; -void rt288x_register_flash(unsigned int id); - -void rt288x_register_wifi(void); - -extern struct ramips_eth_platform_data rt288x_eth_data; -void rt288x_register_ethernet(void); - -void rt288x_register_wdt(void); - -#endif /* __ASM_MACH_RT288X_PLATFORM_H */ diff --git a/target/linux/ramips/files/arch/mips/ralink/rt288x/early_printk.c b/target/linux/ramips/files/arch/mips/ralink/rt288x/early_printk.c deleted file mode 100644 index 9fd7adb543..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt288x/early_printk.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Ralink RT288x SoC early printk support - * - * Copyright (C) 2009 Gabor Juhos - * Copyright (C) 2008 Imre Kaloz - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include - -#include - -#include - -#define UART_READ(r) \ - __raw_readl((void __iomem *)(KSEG1ADDR(RT2880_UART1_BASE) + 4 * (r))) - -#define UART_WRITE(r, v) \ - __raw_writel((v), (void __iomem *)(KSEG1ADDR(RT2880_UART1_BASE) + 4 * (r))) - -void prom_putchar(unsigned char ch) -{ - while (((UART_READ(UART_REG_LSR)) & UART_LSR_THRE) == 0); - UART_WRITE(UART_REG_TX, ch); - while (((UART_READ(UART_REG_LSR)) & UART_LSR_THRE) == 0); -} diff --git a/target/linux/ramips/files/arch/mips/ralink/rt288x/irq.c b/target/linux/ramips/files/arch/mips/ralink/rt288x/irq.c deleted file mode 100644 index 5465a4560d..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt288x/irq.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Ralink RT288x SoC specific interrupt handling - * - * Copyright (C) 2008-2009 Gabor Juhos - * Copyright (C) 2008 Imre Kaloz - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include - -#include -#include - -#include -#include -#include - -static void rt288x_intc_irq_dispatch(void) -{ - u32 pending; - - pending = ramips_intc_get_status(); - - if (pending & RT2880_INTC_INT_TIMER0) - do_IRQ(RT2880_INTC_IRQ_TIMER0); - - else if (pending & RT2880_INTC_INT_TIMER1) - do_IRQ(RT2880_INTC_IRQ_TIMER1); - - else if (pending & RT2880_INTC_INT_UART0) - do_IRQ(RT2880_INTC_IRQ_UART0); - - else if (pending & RT2880_INTC_INT_PCM) - do_IRQ(RT2880_INTC_IRQ_PCM); - - else if (pending & RT2880_INTC_INT_UART1) - do_IRQ(RT2880_INTC_IRQ_UART1); - - /* TODO: handle PIO interrupts as well */ - - else - spurious_interrupt(); -} - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned long pending; - - pending = read_c0_status() & read_c0_cause() & ST0_IM; - - if (pending & STATUSF_IP7) - do_IRQ(RT288X_CPU_IRQ_COUNTER); - - else if (pending & STATUSF_IP4) - do_IRQ(RT288X_CPU_IRQ_PCI); - - else if (pending & STATUSF_IP5) - do_IRQ(RT288X_CPU_IRQ_FE); - - else if (pending & STATUSF_IP6) - do_IRQ(RT288X_CPU_IRQ_WNIC); - - else if (pending & STATUSF_IP2) - rt288x_intc_irq_dispatch(); - - else - spurious_interrupt(); -} - -void __init arch_init_irq(void) -{ - mips_cpu_irq_init(); - ramips_intc_irq_init(RT2880_INTC_BASE, RT288X_CPU_IRQ_INTC, - RT288X_INTC_IRQ_BASE); -} diff --git a/target/linux/ramips/files/arch/mips/ralink/rt288x/mach-br6524n.c b/target/linux/ramips/files/arch/mips/ralink/rt288x/mach-br6524n.c deleted file mode 100644 index ff4746cda5..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt288x/mach-br6524n.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Edimax BR6524N board support - * - * Copyright (C) 2012 Florian Fainelli - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "devices.h" - -#define BR6524N_GPIO_STATUS_LED 12 -#define BR6524N_GPIO_BUTTON_WPS 0 - -#define BR6524N_KEYS_POLL_INTERVAL 20 -#define BR6524N_KEYS_DEBOUNCE_INTERVAL (3 * BR6524N_KEYS_POLL_INTERVAL) - -static struct gpio_led br6524n_leds_gpio[] __initdata = { - { - .name = "br6524n:green:status", - .gpio = BR6524N_GPIO_STATUS_LED, - .active_low = 1, - } -}; - -static struct gpio_keys_button br6524n_gpio_buttons[] __initdata = { - { - .desc = "wps", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = BR6524N_KEYS_DEBOUNCE_INTERVAL, - .gpio = BR6524N_GPIO_BUTTON_WPS, - } -}; - -static void __init br6524n_fe_init(void) -{ - rt288x_gpio_init(RT2880_GPIO_MODE_UART0); - - rt288x_register_flash(0); - - ramips_register_gpio_leds(-1, ARRAY_SIZE(br6524n_leds_gpio), - br6524n_leds_gpio); - - ramips_register_gpio_buttons(-1, BR6524N_KEYS_POLL_INTERVAL, - ARRAY_SIZE(br6524n_gpio_buttons), - br6524n_gpio_buttons); - - rt288x_register_wifi(); - - /* Board is connected to an IC+ IP175C Fast Ethernet switch */ - rt288x_eth_data.speed = SPEED_100; - rt288x_eth_data.duplex = DUPLEX_FULL; - rt288x_eth_data.tx_fc = 1; - rt288x_eth_data.rx_fc = 1; - rt288x_eth_data.phy_mask = BIT(0); - rt288x_register_ethernet(); - - rt288x_register_wdt(); -} - -MIPS_MACHINE(RAMIPS_MACH_BR6524N, "BR6524N", "Edimax BR6524N", br6524n_fe_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt288x/mach-f5d8235-v1.c b/target/linux/ramips/files/arch/mips/ralink/rt288x/mach-f5d8235-v1.c deleted file mode 100644 index 7679572bb5..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt288x/mach-f5d8235-v1.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Belkin F5D825 V1 board support - * - * Copyright (C) 2011 Cezary Jackiewicz - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#include -#include - -#include - -#define F5D8235_GPIO_RTL8366_SCK 2 -#define F5D8235_GPIO_RTL8366_SDA 1 - -#define F5D8235_GPIO_LED_USB_BLUE 7 -#define F5D8235_GPIO_LED_USB_ORANGE 8 -#define F5D8235_GPIO_BUTTON_WPS 0 -#define F5D8235_GPIO_BUTTON_RESET 9 - -#define F5D8235_KEYS_POLL_INTERVAL 20 -#define F5D8235_KEYS_DEBOUNCE_INTERVAL (3 * F5D8235_KEYS_POLL_INTERVAL) - -static struct rtl8366_platform_data f5d8235_rtl8366s_data = { - .gpio_sda = F5D8235_GPIO_RTL8366_SDA, - .gpio_sck = F5D8235_GPIO_RTL8366_SCK, -}; - -static struct platform_device f5d8235_rtl8366s_device = { - .name = RTL8366S_DRIVER_NAME, - .id = -1, - .dev = { - .platform_data = &f5d8235_rtl8366s_data, - } -}; - -static struct gpio_led f5d8235_leds_gpio[] __initdata = { - { - .name = "f5d8235-v1:blue:storage", - .gpio = F5D8235_GPIO_LED_USB_BLUE, - .active_low = 1, - },{ - .name = "f5d8235-v1:orange:storage", - .gpio = F5D8235_GPIO_LED_USB_ORANGE, - .active_low = 1, - } -}; - -static struct gpio_keys_button f5d8235_gpio_buttons[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = F5D8235_KEYS_DEBOUNCE_INTERVAL, - .gpio = F5D8235_GPIO_BUTTON_RESET, - .active_low = 1, - }, { - .desc = "wps", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = F5D8235_KEYS_DEBOUNCE_INTERVAL, - .gpio = F5D8235_GPIO_BUTTON_WPS, - .active_low = 1, - } -}; - -static void __init f5d8235_init(void) -{ - rt288x_gpio_init(RT2880_GPIO_MODE_UART0 | RT2880_GPIO_MODE_I2C); - - rt288x_register_flash(0); - rt288x_register_wifi(); - rt288x_register_wdt(); - - ramips_register_gpio_leds(-1, ARRAY_SIZE(f5d8235_leds_gpio), - f5d8235_leds_gpio); - - ramips_register_gpio_buttons(-1, F5D8235_KEYS_POLL_INTERVAL, - ARRAY_SIZE(f5d8235_gpio_buttons), - f5d8235_gpio_buttons); - - platform_device_register(&f5d8235_rtl8366s_device); - - rt288x_eth_data.speed = SPEED_1000; - rt288x_eth_data.duplex = DUPLEX_FULL; - rt288x_eth_data.tx_fc = 1; - rt288x_eth_data.rx_fc = 1; - rt288x_register_ethernet(); -} - -MIPS_MACHINE(RAMIPS_MACH_F5D8235_V1, "F5D8235_V1", - "Belkin F5D8235 v1", f5d8235_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt288x/mach-rt-n15.c b/target/linux/ramips/files/arch/mips/ralink/rt288x/mach-rt-n15.c deleted file mode 100644 index 1085b82f91..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt288x/mach-rt-n15.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Asus RT-N15 board support - * - * Copyright (C) 2009-2010 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "devices.h" - -#define RT_N15_GPIO_LED_POWER 11 -#define RT_N15_GPIO_BUTTON_WPS 0 -#define RT_N15_GPIO_BUTTON_RESET 12 - -#define RT_N15_GPIO_RTL8366_SCK 2 -#define RT_N15_GPIO_RTL8366_SDA 1 - -#define RT_N15_KEYS_POLL_INTERVAL 20 -#define RT_N15_KEYS_DEBOUNCE_INTERVAL (3 * RT_N15_KEYS_POLL_INTERVAL) - -static struct gpio_led rt_n15_leds_gpio[] __initdata = { - { - .name = "rt-n15:blue:power", - .gpio = RT_N15_GPIO_LED_POWER, - .active_low = 1, - } -}; - -static struct gpio_keys_button rt_n15_gpio_buttons[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = RT_N15_KEYS_DEBOUNCE_INTERVAL, - .gpio = RT_N15_GPIO_BUTTON_RESET, - .active_low = 1, - }, { - .desc = "wps", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = RT_N15_KEYS_DEBOUNCE_INTERVAL, - .gpio = RT_N15_GPIO_BUTTON_WPS, - .active_low = 1, - } -}; - -static struct rtl8366_platform_data rt_n15_rtl8366s_data = { - .gpio_sda = RT_N15_GPIO_RTL8366_SDA, - .gpio_sck = RT_N15_GPIO_RTL8366_SCK, -}; - -static struct platform_device rt_n15_rtl8366s_device = { - .name = RTL8366S_DRIVER_NAME, - .id = -1, - .dev = { - .platform_data = &rt_n15_rtl8366s_data, - } -}; - -static void __init rt_n15_init(void) -{ - rt288x_gpio_init(RT2880_GPIO_MODE_UART0 | RT2880_GPIO_MODE_I2C); - - rt288x_register_flash(0); - - ramips_register_gpio_leds(-1, ARRAY_SIZE(rt_n15_leds_gpio), - rt_n15_leds_gpio); - - ramips_register_gpio_buttons(-1, RT_N15_KEYS_POLL_INTERVAL, - ARRAY_SIZE(rt_n15_gpio_buttons), - rt_n15_gpio_buttons); - - platform_device_register(&rt_n15_rtl8366s_device); - - rt288x_register_wifi(); - - rt288x_eth_data.speed = SPEED_1000; - rt288x_eth_data.duplex = DUPLEX_FULL; - rt288x_eth_data.tx_fc = 1; - rt288x_eth_data.rx_fc = 1; - rt288x_register_ethernet(); - rt288x_register_wdt(); -} - -MIPS_MACHINE(RAMIPS_MACH_RT_N15, "RT-N15", "Asus RT-N15", rt_n15_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt288x/mach-v11st-fe.c b/target/linux/ramips/files/arch/mips/ralink/rt288x/mach-v11st-fe.c deleted file mode 100644 index 667fe92dc0..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt288x/mach-v11st-fe.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Ralink V11ST-FE board support - * - * Copyright (C) 2012 Florian Fainelli - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "devices.h" - -#define V11ST_FE_GPIO_STATUS_LED 12 -#define V11ST_FE_GPIO_BUTTON_WPS 0 - -#define V11ST_FE_KEYS_POLL_INTERVAL 20 -#define V11ST_FE_KEYS_DEBOUNCE_INTERVAL (3 * V11ST_FE_KEYS_POLL_INTERVAL) - -static struct gpio_led v11st_fe_leds_gpio[] __initdata = { - { - .name = "v11st-fe:green:status", - .gpio = V11ST_FE_GPIO_STATUS_LED, - .active_low = 1, - } -}; - -static struct gpio_keys_button v11st_fe_gpio_buttons[] __initdata = { - { - .desc = "wps", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = V11ST_FE_KEYS_DEBOUNCE_INTERVAL, - .gpio = V11ST_FE_GPIO_BUTTON_WPS, - } -}; - -static void __init rt_v11st_fe_init(void) -{ - rt288x_gpio_init(RT2880_GPIO_MODE_UART0); - - rt288x_register_flash(0); - - ramips_register_gpio_leds(-1, ARRAY_SIZE(v11st_fe_leds_gpio), - v11st_fe_leds_gpio); - - ramips_register_gpio_buttons(-1, V11ST_FE_KEYS_POLL_INTERVAL, - ARRAY_SIZE(v11st_fe_gpio_buttons), - v11st_fe_gpio_buttons); - - rt288x_register_wifi(); - - /* Board is connected to an IC+ IP175C Fast Ethernet switch */ - rt288x_eth_data.speed = SPEED_100; - rt288x_eth_data.duplex = DUPLEX_FULL; - rt288x_eth_data.tx_fc = 1; - rt288x_eth_data.rx_fc = 1; - rt288x_eth_data.phy_mask = BIT(0); - rt288x_register_ethernet(); - - rt288x_register_wdt(); - rt288x_register_pci(); -} - -MIPS_MACHINE(RAMIPS_MACH_V11ST_FE, "V11ST-FE", "Ralink V11ST-FE", rt_v11st_fe_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt288x/mach-wli-tx4-ag300n.c b/target/linux/ramips/files/arch/mips/ralink/rt288x/mach-wli-tx4-ag300n.c deleted file mode 100644 index 02fac0b3c5..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt288x/mach-wli-tx4-ag300n.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Buffalo WLI-TX4-AG300N board support - * - * Copyright (C) 2011 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "devices.h" - -#define WLI_TX4_AG300N_GPIO_LED_DIAG 10 -#define WLI_TX4_AG300N_GPIO_LED_POWER 12 -#define WLI_TX4_AG300N_GPIO_LED_SECURITY 13 - -#define WLI_TX4_AG300N_GPIO_BUTTON_AOSS 0 -#define WLI_TX4_AG300N_GPIO_BUTTON_BW_SWITCH 8 -#define WLI_TX4_AG300N_GPIO_BUTTON_RESET 9 - -#define WLI_TX4_AG300N_KEYS_POLL_INTERVAL 20 -#define WLI_TX4_AG300N_KEYS_DEBOUNCE_INTERVAL (3 * WLI_TX4_AG300N_KEYS_POLL_INTERVAL) - -static struct gpio_led wli_tx4_ag300n_leds_gpio[] __initdata = { - { - .name = "buffalo:blue:power", - .gpio = WLI_TX4_AG300N_GPIO_LED_POWER, - .active_low = 1, - }, - { - .name = "buffalo:red:diag", - .gpio = WLI_TX4_AG300N_GPIO_LED_DIAG, - .active_low = 1, - }, - { - .name = "buffalo:blue:security", - .gpio = WLI_TX4_AG300N_GPIO_LED_SECURITY, - .active_low = 0, - }, -}; - -static struct gpio_keys_button wli_tx4_ag300n_gpio_buttons[] __initdata = { - { - .desc = "Reset button", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = WLI_TX4_AG300N_KEYS_DEBOUNCE_INTERVAL, - .gpio = WLI_TX4_AG300N_GPIO_BUTTON_RESET, - .active_low = 1, - }, - { - .desc = "AOSS button", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = WLI_TX4_AG300N_KEYS_DEBOUNCE_INTERVAL, - .gpio = WLI_TX4_AG300N_GPIO_BUTTON_AOSS, - .active_low = 1, - }, - { - .desc = "Bandwidth switch", - .type = EV_KEY, - .code = BTN_0, - .debounce_interval = WLI_TX4_AG300N_KEYS_DEBOUNCE_INTERVAL, - .gpio = WLI_TX4_AG300N_GPIO_BUTTON_BW_SWITCH, - .active_low = 0, - }, -}; - -static void __init wli_tx4_ag300n_init(void) -{ - rt288x_gpio_init(RT2880_GPIO_MODE_UART0); - - ramips_register_gpio_leds(-1, ARRAY_SIZE(wli_tx4_ag300n_leds_gpio), - wli_tx4_ag300n_leds_gpio); - ramips_register_gpio_buttons(-1, WLI_TX4_AG300N_KEYS_POLL_INTERVAL, - ARRAY_SIZE(wli_tx4_ag300n_gpio_buttons), - wli_tx4_ag300n_gpio_buttons); - - rt288x_register_flash(0); - rt288x_register_wifi(); - rt288x_register_wdt(); - - rt288x_eth_data.speed = SPEED_100; - rt288x_eth_data.duplex = DUPLEX_FULL; - rt288x_eth_data.tx_fc = 1; - rt288x_eth_data.rx_fc = 1; - rt288x_register_ethernet(); -} - -MIPS_MACHINE(RAMIPS_MACH_WLI_TX4_AG300N, "WLI-TX4-AG300N", - "Buffalo WLI-TX4-AG300N", wli_tx4_ag300n_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt288x/mach-wzr-agl300nh.c b/target/linux/ramips/files/arch/mips/ralink/rt288x/mach-wzr-agl300nh.c deleted file mode 100644 index 6bd7a45423..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt288x/mach-wzr-agl300nh.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Buffalo WZR-AGL300NH board support - * - * Copyright (C) 2010 Joonas Lahtinen - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "devices.h" - -/* - * MTD layout from stock firmware: - * mtd0: 00030000 00010000 "uboot" - * mtd1: 00010000 00010000 "uboot_environ" - * mtd2: 00010000 00010000 "factory_default" - * mtd3: 000b0000 00010000 "linux" - * mtd4: 002f0000 00010000 "rootfs" - * mtd5: 00010000 00010000 "user_property" - */ - -static struct mtd_partition wzr_agl300nh_partitions[] = { - { - .name = "uboot", - .offset = 0, - .size = 0x030000, - .mask_flags = MTD_WRITEABLE, - }, { - .name = "uboot_environ", - .offset = 0x030000, - .size = 0x010000, - .mask_flags = MTD_WRITEABLE, - }, { - .name = "factory_default", - .offset = 0x040000, - .size = 0x010000, - .mask_flags = MTD_WRITEABLE, - }, { - .name = "linux", - .offset = 0x050000, - .size = 0x0b0000, - }, { - .name = "rootfs", - .offset = 0x100000, - .size = 0x2f0000, - }, { - .name = "user_property", - .offset = 0x3f0000, - .size = 0x010000, - } -}; - -static void __init wzr_agl300nh_init(void) -{ - rt288x_gpio_init(RT2880_GPIO_MODE_UART0); - - rt288x_flash0_data.nr_parts = ARRAY_SIZE(wzr_agl300nh_partitions); - rt288x_flash0_data.parts = wzr_agl300nh_partitions; - rt288x_register_flash(0); - - rt288x_register_wifi(); - rt288x_register_wdt(); -} - -MIPS_MACHINE(RAMIPS_MACH_WZR_AGL300NH, "WZR-AGL300NH", - "Buffalo WZR-AGL300NH", wzr_agl300nh_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt288x/rt288x.c b/target/linux/ramips/files/arch/mips/ralink/rt288x/rt288x.c deleted file mode 100644 index c51ad98b3a..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt288x/rt288x.c +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Ralink RT288x SoC specific setup - * - * Copyright (C) 2008-2011 Gabor Juhos - * Copyright (C) 2008 Imre Kaloz - * - * Parts of this file are based on Ralink's 2.6.21 BSP - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include - -#include -#include -#include -#include - -void __iomem * rt288x_sysc_base; -void __iomem * rt288x_memc_base; - -void __init ramips_soc_prom_init(void) -{ - void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE); - u32 n0; - u32 n1; - u32 id; - - n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); - n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); - id = __raw_readl(sysc + SYSC_REG_CHIP_ID); - - snprintf(ramips_sys_type, RAMIPS_SYS_TYPE_LEN, - "Ralink %c%c%c%c%c%c%c%c id:%u rev:%u", - (char) (n0 & 0xff), (char) ((n0 >> 8) & 0xff), - (char) ((n0 >> 16) & 0xff), (char) ((n0 >> 24) & 0xff), - (char) (n1 & 0xff), (char) ((n1 >> 8) & 0xff), - (char) ((n1 >> 16) & 0xff), (char) ((n1 >> 24) & 0xff), - (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK, - (id & CHIP_ID_REV_MASK)); - - ramips_mem_base = RT2880_SDRAM_BASE; - ramips_mem_size_min = RT288X_MEM_SIZE_MIN; - ramips_mem_size_max = RT288X_MEM_SIZE_MAX; -} - -static struct ramips_gpio_chip rt288x_gpio_chips[] = { - { - .chip = { - .label = "RT288X-GPIO0", - .base = 0, - .ngpio = 24, - }, - .regs = { - [RAMIPS_GPIO_REG_INT] = 0x00, - [RAMIPS_GPIO_REG_EDGE] = 0x04, - [RAMIPS_GPIO_REG_RENA] = 0x08, - [RAMIPS_GPIO_REG_FENA] = 0x0c, - [RAMIPS_GPIO_REG_DATA] = 0x20, - [RAMIPS_GPIO_REG_DIR] = 0x24, - [RAMIPS_GPIO_REG_POL] = 0x28, - [RAMIPS_GPIO_REG_SET] = 0x2c, - [RAMIPS_GPIO_REG_RESET] = 0x30, - [RAMIPS_GPIO_REG_TOGGLE] = 0x34, - }, - .map_base = RT2880_PIO_BASE, - .map_size = RT2880_PIO_SIZE, - }, - { - .chip = { - .label = "RT288X-GPIO1", - .base = 24, - .ngpio = 16, - }, - .regs = { - [RAMIPS_GPIO_REG_INT] = 0x38, - [RAMIPS_GPIO_REG_EDGE] = 0x3c, - [RAMIPS_GPIO_REG_RENA] = 0x40, - [RAMIPS_GPIO_REG_FENA] = 0x44, - [RAMIPS_GPIO_REG_DATA] = 0x48, - [RAMIPS_GPIO_REG_DIR] = 0x4c, - [RAMIPS_GPIO_REG_POL] = 0x50, - [RAMIPS_GPIO_REG_SET] = 0x54, - [RAMIPS_GPIO_REG_RESET] = 0x58, - [RAMIPS_GPIO_REG_TOGGLE] = 0x5c, - }, - .map_base = RT2880_PIO_BASE, - .map_size = RT2880_PIO_SIZE, - }, - { - .chip = { - .label = "RT288X-GPIO2", - .base = 40, - .ngpio = 32, - }, - .regs = { - [RAMIPS_GPIO_REG_INT] = 0x60, - [RAMIPS_GPIO_REG_EDGE] = 0x64, - [RAMIPS_GPIO_REG_RENA] = 0x68, - [RAMIPS_GPIO_REG_FENA] = 0x6c, - [RAMIPS_GPIO_REG_DATA] = 0x70, - [RAMIPS_GPIO_REG_DIR] = 0x74, - [RAMIPS_GPIO_REG_POL] = 0x78, - [RAMIPS_GPIO_REG_SET] = 0x7c, - [RAMIPS_GPIO_REG_RESET] = 0x80, - [RAMIPS_GPIO_REG_TOGGLE] = 0x84, - }, - .map_base = RT2880_PIO_BASE, - .map_size = RT2880_PIO_SIZE, - }, -}; - -static struct ramips_gpio_data rt288x_gpio_data = { - .chips = rt288x_gpio_chips, - .num_chips = ARRAY_SIZE(rt288x_gpio_chips), -}; - -static void rt288x_gpio_reserve(int first, int last) -{ - for (; first <= last; first++) - gpio_request(first, "reserved"); -} - -void __init rt288x_gpio_init(u32 mode) -{ - rt288x_sysc_wr(mode, SYSC_REG_GPIO_MODE); - - ramips_gpio_init(&rt288x_gpio_data); - if ((mode & RT2880_GPIO_MODE_I2C) == 0) - rt288x_gpio_reserve(1, 2); - - if ((mode & RT2880_GPIO_MODE_SPI) == 0) - rt288x_gpio_reserve(3, 6); - - if ((mode & RT2880_GPIO_MODE_UART0) == 0) - rt288x_gpio_reserve(7, 14); - - if ((mode & RT2880_GPIO_MODE_JTAG) == 0) - rt288x_gpio_reserve(17, 21); - - if ((mode & RT2880_GPIO_MODE_MDIO) == 0) - rt288x_gpio_reserve(22, 23); - - if ((mode & RT2880_GPIO_MODE_SDRAM) == 0) - rt288x_gpio_reserve(24, 39); - - if ((mode & RT2880_GPIO_MODE_PCI) == 0) - rt288x_gpio_reserve(40, 71); -} diff --git a/target/linux/ramips/files/arch/mips/ralink/rt288x/setup.c b/target/linux/ramips/files/arch/mips/ralink/rt288x/setup.c deleted file mode 100644 index be474b5292..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt288x/setup.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Ralink RT288x SoC specific setup - * - * Copyright (C) 2008 Gabor Juhos - * Copyright (C) 2008 Imre Kaloz - * - * Parts of this file are based on Ralink's 2.6.21 BSP - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include "common.h" - -static void rt288x_restart(char *command) -{ - rt288x_sysc_wr(RT2880_RESET_SYSTEM, SYSC_REG_RESET_CTRL); - while (1) - if (cpu_wait) - cpu_wait(); -} - -static void rt288x_halt(void) -{ - while (1) - cpu_wait(); -} - -unsigned int __cpuinit get_c0_compare_irq(void) -{ - return CP0_LEGACY_COMPARE_IRQ; -} - -void __init ramips_soc_setup(void) -{ - struct clk *clk; - - rt288x_sysc_base = ioremap_nocache(RT2880_SYSC_BASE, RT2880_SYSC_SIZE); - rt288x_memc_base = ioremap_nocache(RT2880_MEMC_BASE, RT2880_MEMC_SIZE); - - rt288x_clocks_init(); - - clk = clk_get(NULL, "cpu"); - if (IS_ERR(clk)) - panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); - - printk(KERN_INFO "%s running at %lu.%02lu MHz\n", ramips_sys_type, - clk_get_rate(clk) / 1000000, - (clk_get_rate(clk) % 1000000) * 100 / 1000000); - - _machine_restart = rt288x_restart; - _machine_halt = rt288x_halt; - pm_power_off = rt288x_halt; - - clk = clk_get(NULL, "uart"); - if (IS_ERR(clk)) - panic("unable to get UART clock, err=%ld", PTR_ERR(clk)); - - ramips_early_serial_setup(0, RT2880_UART0_BASE, clk_get_rate(clk), - RT2880_INTC_IRQ_UART0); - ramips_early_serial_setup(1, RT2880_UART1_BASE, clk_get_rate(clk), - RT2880_INTC_IRQ_UART1); -} - -void __init plat_time_init(void) -{ - struct clk *clk; - - clk = clk_get(NULL, "cpu"); - if (IS_ERR(clk)) - panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); - - mips_hpt_frequency = clk_get_rate(clk) / 2; -} diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/Kconfig b/target/linux/ramips/files/arch/mips/ralink/rt305x/Kconfig deleted file mode 100644 index 700a983388..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/Kconfig +++ /dev/null @@ -1,219 +0,0 @@ -if RALINK_RT305X - -menu "Ralink RT350x machine selection" - -config RT305X_MACH_CARAMBOLA - bool "8devices Carambola dev board support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_3G_6200N - bool "Edimax 3G-6200N board support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_3G300M - bool "Tenda 3G300M board support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_BR6425 - bool "Edimax BR-6425 board support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_WR6202 - bool "Accton WR6202" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_AIR3GII - bool "AirLive Air3GII board support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_ALL0256N - bool "Allnet ALL0256N support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_ALL5002 - bool "Allnet ALL5002 support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_W502U - bool "ALFA Networks W502U board support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_ARGUS_ATP52B - bool "Argus ATP-52B support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_RT_G32_REVB - bool "Asus RT-G32 revB board support" - select RALINK_DEV_GPIO_BUTTONS - -config RT305X_MACH_RT_N10_PLUS - bool "Asus RT-N10+ board support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_WL_330N - bool "Asus WL-330N board support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_WL_330N3G - bool "Asus WL-330N3G board support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_HW550_3G - bool "Aztech HW550-3G support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_F5D8235_V2 - bool "Belkin F5D8235 v2 support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_WHR_G300N - bool "Buffalo WHR-G300N support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_DIR_300_REVB - bool "D-Link DIR-300 revB board support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_DIR_615_H1 - bool "D-Link DIR-615 H1 board support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_DAP_1350 - bool "D-Link DAP-1350 board support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_ESR_9753 - bool "EnGenius ESR-9753 support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_BROADWAY - bool "Hauppauge Broadway support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_FONERA20N - bool "La Fonera20N board support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_RT_N13U - bool "ASUS RT-N13U board support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_FREESTATION5 - bool "ARC FreeStation5" - -config RT305X_MACH_MOFI3500_3GN - bool "MoFi Network MOFI3500-3GN support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_WR512_3GN - bool "SH-WR512NU/WS-WR512N1-like 3GN router" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_UR_326N4G - bool "UR-326N4G Wireless N router" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_UR_336UN - bool "UR-336UN Wireless N router" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_NW718 - bool "Netcore NW718" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_BC2 - bool "NexAira BC2" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_OMNI_EMB - bool "Omnima MiniEMBWiFi" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_PSR_680W - bool "Petatel PSR-680W Wireless 3G Router support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_PWH2004 - bool "Prolink PWH2004 / Abocom WR5205 support (32M RAM, 8M flash)" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_V22RW_2X2 - bool "Ralink AP-RT3052-V22RW-2X2 board support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_W306R_V20 - bool "Tenda W306R V2.0 board support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_WL341V3 - bool "Sitecom WL-341 v3 board support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_WL351 - bool "Sitecom WL-351 support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_SL_R7205 - bool "Skyline SL-R7205 Wireless 3G Router support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_WCR150GN - bool "Sparklan WCR-150GN support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_NBG_419N - bool "ZyXEL NBG-419N support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_MZKW300NH2 - bool "Planex MZK-W300NH2 Router support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT305X_MACH_XDX_RN502J - bool "Unknown board XDX-RN502J" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -endmenu - -endif diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/Makefile b/target/linux/ramips/files/arch/mips/ralink/rt305x/Makefile deleted file mode 100644 index 47e9ce52ba..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/Makefile +++ /dev/null @@ -1,56 +0,0 @@ -# -# Makefile for the Ralink RT305x SoC specific parts of the kernel -# -# Copyright (C) 2009-2011 Gabor Juhos -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of the GNU General Public License version 2 as published -# by the Free Software Foundation. - -obj-y := irq.o setup.o devices.o rt305x.o clock.o - -obj-$(CONFIG_EARLY_PRINTK) += early_printk.o - -obj-$(CONFIG_RT305X_MACH_3G_6200N) += mach-3g-6200n.o -obj-$(CONFIG_RT305X_MACH_3G300M) += mach-3g300m.o -obj-$(CONFIG_RT305X_MACH_ARGUS_ATP52B) += mach-argus-atp52b.o -obj-$(CONFIG_RT305X_MACH_BC2) += mach-bc2.o -obj-$(CONFIG_RT305X_MACH_AIR3GII) += mach-air3gii.o -obj-$(CONFIG_RT305X_MACH_ALL0256N) += mach-all0256n.o -obj-$(CONFIG_RT305X_MACH_ALL5002) += mach-all5002.o -obj-$(CONFIG_RT305X_MACH_BR6425) += mach-br6425.o -obj-$(CONFIG_RT305X_MACH_BROADWAY) += mach-broadway.o -obj-$(CONFIG_RT305X_MACH_CARAMBOLA) += mach-carambola.o -obj-$(CONFIG_RT305X_MACH_DIR_300_REVB) += mach-dir-300-revb.o -obj-$(CONFIG_RT305X_MACH_DIR_615_H1) += mach-dir-615-h1.o -obj-$(CONFIG_RT305X_MACH_DAP_1350) += mach-dap-1350.o -obj-$(CONFIG_RT305X_MACH_ESR_9753) += mach-esr-9753.o -obj-$(CONFIG_RT305X_MACH_F5D8235_V2) += mach-f5d8235-v2.o -obj-$(CONFIG_RT305X_MACH_FONERA20N) += mach-fonera20n.o -obj-$(CONFIG_RT305X_MACH_RT_N13U) += mach-rt-n13u.o -obj-$(CONFIG_RT305X_MACH_FREESTATION5) += mach-freestation5.o -obj-$(CONFIG_RT305X_MACH_HW550_3G) += mach-hw550-3g.o -obj-$(CONFIG_RT305X_MACH_MOFI3500_3GN) += mach-mofi3500-3gn.o -obj-$(CONFIG_RT305X_MACH_NBG_419N) += mach-nbg-419n.o -obj-$(CONFIG_RT305X_MACH_NW718) += mach-nw718.o -obj-$(CONFIG_RT305X_MACH_OMNI_EMB) += mach-omni-emb.o -obj-$(CONFIG_RT305X_MACH_PSR_680W) += mach-psr-680w.o -obj-$(CONFIG_RT305X_MACH_PWH2004) += mach-pwh2004.o -obj-$(CONFIG_RT305X_MACH_RT_G32_REVB) += mach-rt-g32-revb.o -obj-$(CONFIG_RT305X_MACH_RT_N10_PLUS) += mach-rt-n10-plus.o -obj-$(CONFIG_RT305X_MACH_SL_R7205) += mach-sl-r7205.o -obj-$(CONFIG_RT305X_MACH_V22RW_2X2) += mach-v22rw-2x2.o -obj-$(CONFIG_RT305X_MACH_W306R_V20) += mach-w306r-v20.o -obj-$(CONFIG_RT305X_MACH_W502U) += mach-w502u.o -obj-$(CONFIG_RT305X_MACH_WCR150GN) += mach-wcr150gn.o -obj-$(CONFIG_RT305X_MACH_WHR_G300N) += mach-whr-g300n.o -obj-$(CONFIG_RT305X_MACH_WR512_3GN) += mach-wr512-3gn.o -obj-$(CONFIG_RT305X_MACH_UR_326N4G) += mach-ur-326n4g.o -obj-$(CONFIG_RT305X_MACH_UR_336UN) += mach-ur-336un.o -obj-$(CONFIG_RT305X_MACH_WL_330N) += mach-wl-330n.o -obj-$(CONFIG_RT305X_MACH_WL_330N3G) += mach-wl-330n3g.o -obj-$(CONFIG_RT305X_MACH_WL341V3) += mach-wl341v3.o -obj-$(CONFIG_RT305X_MACH_WL351) += mach-wl351.o -obj-$(CONFIG_RT305X_MACH_WR6202) += mach-wr6202.o -obj-$(CONFIG_RT305X_MACH_MZKW300NH2) += mach-mzk-w300nh2.o -obj-$(CONFIG_RT305X_MACH_XDX_RN502J) += mach-xdx-rn502j.o diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c deleted file mode 100644 index c46a1747b5..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Ralink RT305X clock API - * - * Copyright (C) 2011 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include "common.h" - -struct clk { - unsigned long rate; -}; - -static struct clk rt305x_cpu_clk; -static struct clk rt305x_sys_clk; -static struct clk rt305x_wdt_clk; -static struct clk rt305x_uart_clk; - -void __init rt305x_clocks_init(void) -{ - u32 t; - - t = rt305x_sysc_rr(SYSC_REG_SYSTEM_CONFIG); - - if (soc_is_rt305x() || soc_is_rt3350()) { - t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) & - RT305X_SYSCFG_CPUCLK_MASK; - switch (t) { - case RT305X_SYSCFG_CPUCLK_LOW: - rt305x_cpu_clk.rate = 320000000; - break; - case RT305X_SYSCFG_CPUCLK_HIGH: - rt305x_cpu_clk.rate = 384000000; - break; - } - rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3; - rt305x_uart_clk.rate = rt305x_sys_clk.rate; - rt305x_wdt_clk.rate = rt305x_sys_clk.rate; - } else if (soc_is_rt3352()) { - t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) & - RT3352_SYSCFG0_CPUCLK_MASK; - switch (t) { - case RT3352_SYSCFG0_CPUCLK_LOW: - rt305x_cpu_clk.rate = 384000000; - break; - case RT3352_SYSCFG0_CPUCLK_HIGH: - rt305x_cpu_clk.rate = 400000000; - break; - } - rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3; - rt305x_uart_clk.rate = 40000000; - rt305x_wdt_clk.rate = rt305x_sys_clk.rate; - } else if (soc_is_rt5350()) { - t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) & - RT5350_SYSCFG0_CPUCLK_MASK; - switch (t) { - case RT5350_SYSCFG0_CPUCLK_360: - rt305x_cpu_clk.rate = 360000000; - rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3; - break; - case RT5350_SYSCFG0_CPUCLK_320: - rt305x_cpu_clk.rate = 320000000; - rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 4; - break; - case RT5350_SYSCFG0_CPUCLK_300: - rt305x_cpu_clk.rate = 300000000; - rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3; - break; - default: - BUG(); - } - rt305x_uart_clk.rate = 40000000; - rt305x_wdt_clk.rate = rt305x_sys_clk.rate; - } else { - BUG(); - } - -} - -/* - * Linux clock API - */ -struct clk *clk_get(struct device *dev, const char *id) -{ - if (!strcmp(id, "sys")) - return &rt305x_sys_clk; - - if (!strcmp(id, "cpu")) - return &rt305x_cpu_clk; - - if (!strcmp(id, "wdt")) - return &rt305x_wdt_clk; - - if (!strcmp(id, "uart")) - return &rt305x_uart_clk; - - return ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(clk_get); - -int clk_enable(struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - return clk->rate; -} -EXPORT_SYMBOL(clk_get_rate); - -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/common.h b/target/linux/ramips/files/arch/mips/ralink/rt305x/common.h deleted file mode 100644 index 48ac43e81b..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/common.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Ralink RT305x SoC common defines - * - * Copyright (C) 2011 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef _RT305X_COMMON_H -#define _RT305X_COMMON_H - -void rt305x_clocks_init(void); - -#endif /* _RT305X_COMMON_H */ \ No newline at end of file diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/devices.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/devices.c deleted file mode 100644 index f16ba6d5f1..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/devices.c +++ /dev/null @@ -1,428 +0,0 @@ -/* - * Ralink RT305x SoC platform device registration - * - * Copyright (C) 2009-2010 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include "devices.h" - -#include -#include - -static struct resource rt305x_flash0_resources[] = { - { - .flags = IORESOURCE_MEM, - .start = KSEG1ADDR(RT305X_FLASH0_BASE), - .end = KSEG1ADDR(RT305X_FLASH0_BASE) + - RT305X_FLASH0_SIZE - 1, - }, -}; - -struct physmap_flash_data rt305x_flash0_data; -static struct platform_device rt305x_flash0_device = { - .name = "physmap-flash", - .resource = rt305x_flash0_resources, - .num_resources = ARRAY_SIZE(rt305x_flash0_resources), - .dev = { - .platform_data = &rt305x_flash0_data, - }, -}; - -static struct resource rt305x_flash1_resources[] = { - { - .flags = IORESOURCE_MEM, - .start = KSEG1ADDR(RT305X_FLASH1_BASE), - .end = KSEG1ADDR(RT305X_FLASH1_BASE) + - RT305X_FLASH1_SIZE - 1, - }, -}; - -struct physmap_flash_data rt305x_flash1_data; -static struct platform_device rt305x_flash1_device = { - .name = "physmap-flash", - .resource = rt305x_flash1_resources, - .num_resources = ARRAY_SIZE(rt305x_flash1_resources), - .dev = { - .platform_data = &rt305x_flash1_data, - }, -}; - -static int rt305x_flash_instance __initdata; -void __init rt305x_register_flash(unsigned int id) -{ - struct platform_device *pdev; - struct physmap_flash_data *pdata; - u32 t; - int reg; - - switch (id) { - case 0: - pdev = &rt305x_flash0_device; - reg = MEMC_REG_FLASH_CFG0; - break; - case 1: - pdev = &rt305x_flash1_device; - reg = MEMC_REG_FLASH_CFG1; - break; - default: - return; - } - - t = rt305x_memc_rr(reg); - t = (t >> FLASH_CFG_WIDTH_SHIFT) & FLASH_CFG_WIDTH_MASK; - - pdata = pdev->dev.platform_data; - switch (t) { - case FLASH_CFG_WIDTH_8BIT: - pdata->width = 1; - break; - case FLASH_CFG_WIDTH_16BIT: - pdata->width = 2; - break; - case FLASH_CFG_WIDTH_32BIT: - pdata->width = 4; - break; - default: - printk(KERN_ERR "RT305x: flash bank%u witdh is invalid\n", id); - return; - } - - pdev->id = rt305x_flash_instance; - - platform_device_register(pdev); - rt305x_flash_instance++; -} - -static void rt305x_fe_reset(void) -{ - u32 reset_bits = RT305X_RESET_FE; - - if (soc_is_rt5350()) - reset_bits |= RT305X_RESET_ESW; - rt305x_sysc_wr(reset_bits, SYSC_REG_RESET_CTRL); - rt305x_sysc_wr(0, SYSC_REG_RESET_CTRL); -} - -static struct resource rt305x_eth_resources[] = { - { - .start = RT305X_FE_BASE, - .end = RT305X_FE_BASE + PAGE_SIZE - 1, - .flags = IORESOURCE_MEM, - }, { - .start = RT305X_CPU_IRQ_FE, - .end = RT305X_CPU_IRQ_FE, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct ramips_eth_platform_data ramips_eth_data = { - .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 }, - .reset_fe = rt305x_fe_reset, - .min_pkt_len = 64, -}; - -static struct platform_device rt305x_eth_device = { - .name = "ramips_eth", - .resource = rt305x_eth_resources, - .num_resources = ARRAY_SIZE(rt305x_eth_resources), - .dev = { - .platform_data = &ramips_eth_data, - } -}; - -static struct resource rt305x_esw_resources[] = { - { - .start = RT305X_SWITCH_BASE, - .end = RT305X_SWITCH_BASE + PAGE_SIZE - 1, - .flags = IORESOURCE_MEM, - }, -}; - -struct rt305x_esw_platform_data rt305x_esw_data = { - /* All ports are LAN ports. */ - .vlan_config = RT305X_ESW_VLAN_CONFIG_NONE, - .reg_initval_fct2 = 0x00d6500c, - /* - * ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1, - * turbo mii off, rgmi 3.3v off - * port5: disabled - * port6: enabled, gige, full-duplex, rx/tx-flow-control - */ - .reg_initval_fpa2 = 0x3f502b28, -}; - -static struct platform_device rt305x_esw_device = { - .name = "rt305x-esw", - .resource = rt305x_esw_resources, - .num_resources = ARRAY_SIZE(rt305x_esw_resources), - .dev = { - .platform_data = &rt305x_esw_data, - } -}; - -void __init rt305x_register_ethernet(void) -{ - struct clk *clk; - - clk = clk_get(NULL, "sys"); - if (IS_ERR(clk)) - panic("unable to get SYS clock, err=%ld", PTR_ERR(clk)); - - ramips_eth_data.sys_freq = clk_get_rate(clk); - - platform_device_register(&rt305x_esw_device); - platform_device_register(&rt305x_eth_device); -} - -static struct resource rt305x_wifi_resources[] = { - { - .start = RT305X_WMAC_BASE, - .end = RT305X_WMAC_BASE + 0x3FFFF, - .flags = IORESOURCE_MEM, - }, { - .start = RT305X_CPU_IRQ_WNIC, - .end = RT305X_CPU_IRQ_WNIC, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct rt2x00_platform_data rt305x_wifi_data; -static struct platform_device rt305x_wifi_device = { - .name = "rt2800_wmac", - .resource = rt305x_wifi_resources, - .num_resources = ARRAY_SIZE(rt305x_wifi_resources), - .dev = { - .platform_data = &rt305x_wifi_data, - } -}; - -void __init rt305x_register_wifi(void) -{ - u32 t; - - rt305x_wifi_data.eeprom_file_name = "soc_wmac.eeprom"; - - if (soc_is_rt3352() || soc_is_rt5350()) { - t = rt305x_sysc_rr(SYSC_REG_SYSTEM_CONFIG); - t &= RT3352_SYSCFG0_XTAL_SEL; - if (!t) - rt305x_wifi_data.clk_is_20mhz = 1; - } - platform_device_register(&rt305x_wifi_device); -} - -static struct resource rt305x_wdt_resources[] = { - { - .start = RT305X_TIMER_BASE, - .end = RT305X_TIMER_BASE + RT305X_TIMER_SIZE - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device rt305x_wdt_device = { - .name = "ramips-wdt", - .id = -1, - .resource = rt305x_wdt_resources, - .num_resources = ARRAY_SIZE(rt305x_wdt_resources), -}; - -void __init rt305x_register_wdt(void) -{ - u32 t; - - /* enable WDT reset output on pin SRAM_CS_N */ - t = rt305x_sysc_rr(SYSC_REG_SYSTEM_CONFIG); - t |= RT305X_SYSCFG_SRAM_CS0_MODE_WDT << - RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT; - rt305x_sysc_wr(t, SYSC_REG_SYSTEM_CONFIG); - - platform_device_register(&rt305x_wdt_device); -} - -static struct resource rt305x_spi_resources[] = { - { - .flags = IORESOURCE_MEM, - .start = RT305X_SPI_BASE, - .end = RT305X_SPI_BASE + RT305X_SPI_SIZE - 1, - }, -}; - -static struct platform_device rt305x_spi_device = { - .name = "ramips-spi", - .id = 0, - .resource = rt305x_spi_resources, - .num_resources = ARRAY_SIZE(rt305x_spi_resources), -}; - -void __init rt305x_register_spi(struct spi_board_info *info, int n) -{ - spi_register_board_info(info, n); - platform_device_register(&rt305x_spi_device); -} - -static struct resource rt305x_dwc_otg_resources[] = { - { - .start = RT305X_OTG_BASE, - .end = RT305X_OTG_BASE + 0x3FFFF, - .flags = IORESOURCE_MEM, - }, { - .start = RT305X_INTC_IRQ_OTG, - .end = RT305X_INTC_IRQ_OTG, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device rt305x_dwc_otg_device = { - .name = "dwc_otg", - .resource = rt305x_dwc_otg_resources, - .num_resources = ARRAY_SIZE(rt305x_dwc_otg_resources), - .dev = { - .platform_data = NULL, - } -}; - -static atomic_t rt3352_usb_pwr_ref = ATOMIC_INIT(0); - -static int rt3352_usb_power_on(struct platform_device *pdev) -{ - - if (atomic_inc_return(&rt3352_usb_pwr_ref) == 1) { - u32 t; - - t = rt305x_sysc_rr(RT3352_SYSC_REG_USB_PS); - - /* enable clock for port0's and port1's phys */ - t = rt305x_sysc_rr(RT3352_SYSC_REG_CLKCFG1); - t |= RT3352_CLKCFG1_UPHY0_CLK_EN | RT3352_CLKCFG1_UPHY1_CLK_EN; - rt305x_sysc_wr(t, RT3352_SYSC_REG_CLKCFG1); - mdelay(500); - - /* pull USBHOST and USBDEV out from reset */ - t = rt305x_sysc_rr(RT3352_SYSC_REG_RSTCTRL); - t &= ~(RT3352_RSTCTRL_UHST | RT3352_RSTCTRL_UDEV); - rt305x_sysc_wr(t, RT3352_SYSC_REG_RSTCTRL); - mdelay(500); - - /* enable host mode */ - t = rt305x_sysc_rr(RT3352_SYSC_REG_SYSCFG1); - t |= RT3352_SYSCFG1_USB0_HOST_MODE; - rt305x_sysc_wr(t, RT3352_SYSC_REG_SYSCFG1); - - t = rt305x_sysc_rr(RT3352_SYSC_REG_USB_PS); - } - - return 0; -} - -static void rt3352_usb_power_off(struct platform_device *pdev) -{ - - if (atomic_dec_return(&rt3352_usb_pwr_ref) == 0) { - u32 t; - - /* put USBHOST and USBDEV into reset */ - t = rt305x_sysc_rr(RT3352_SYSC_REG_RSTCTRL); - t |= RT3352_RSTCTRL_UHST | RT3352_RSTCTRL_UDEV; - rt305x_sysc_wr(t, RT3352_SYSC_REG_RSTCTRL); - udelay(10000); - - /* disable clock for port0's and port1's phys*/ - t = rt305x_sysc_rr(RT3352_SYSC_REG_CLKCFG1); - t &= ~(RT3352_CLKCFG1_UPHY0_CLK_EN | RT3352_CLKCFG1_UPHY1_CLK_EN); - rt305x_sysc_wr(t, RT3352_SYSC_REG_CLKCFG1); - udelay(10000); - } -} - -static struct usb_ehci_pdata rt3352_ehci_data = { - .power_on = rt3352_usb_power_on, - .power_off = rt3352_usb_power_off, -}; - -static struct resource rt3352_ehci_resources[] = { - { - .start = RT3352_EHCI_BASE, - .end = RT3352_EHCI_BASE + RT3352_EHCI_SIZE - 1, - .flags = IORESOURCE_MEM, - }, { - .start = RT305X_INTC_IRQ_OTG, - .end = RT305X_INTC_IRQ_OTG, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 rt3352_ehci_dmamask = DMA_BIT_MASK(32); -static struct platform_device rt3352_ehci_device = { - .name = "ehci-platform", - .id = -1, - .resource = rt3352_ehci_resources, - .num_resources = ARRAY_SIZE(rt3352_ehci_resources), - .dev = { - .dma_mask = &rt3352_ehci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &rt3352_ehci_data, - }, -}; - -static struct resource rt3352_ohci_resources[] = { - { - .start = RT3352_OHCI_BASE, - .end = RT3352_OHCI_BASE + RT3352_OHCI_SIZE - 1, - .flags = IORESOURCE_MEM, - }, { - .start = RT305X_INTC_IRQ_OTG, - .end = RT305X_INTC_IRQ_OTG, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct usb_ohci_pdata rt3352_ohci_data = { - .power_on = rt3352_usb_power_on, - .power_off = rt3352_usb_power_off, -}; - -static u64 rt3352_ohci_dmamask = DMA_BIT_MASK(32); -static struct platform_device rt3352_ohci_device = { - .name = "ohci-platform", - .id = -1, - .resource = rt3352_ohci_resources, - .num_resources = ARRAY_SIZE(rt3352_ohci_resources), - .dev = { - .dma_mask = &rt3352_ohci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &rt3352_ohci_data, - }, -}; - -void __init rt305x_register_usb(void) -{ - if (soc_is_rt305x() || soc_is_rt3350()) { - platform_device_register(&rt305x_dwc_otg_device); - } else if (soc_is_rt3352() || soc_is_rt5350()) { - platform_device_register(&rt3352_ehci_device); - platform_device_register(&rt3352_ohci_device); - } else { - BUG(); - } -} diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/devices.h b/target/linux/ramips/files/arch/mips/ralink/rt305x/devices.h deleted file mode 100644 index 22c9ce4232..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/devices.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Ralink RT305x SoC specific platform device definitions - * - * Copyright (C) 2009-2011 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef __RT305X_DEVICES_H -#define __RT305X_DEVICES_H - -#include - -struct physmap_flash_data; -struct spi_board_info; - -extern struct physmap_flash_data rt305x_flash0_data; -extern struct physmap_flash_data rt305x_flash1_data; - -extern struct rt305x_esw_platform_data rt305x_esw_data; - -void rt305x_register_flash(unsigned int id); -void rt305x_register_ethernet(void); -void rt305x_register_wifi(void); -void rt305x_register_wdt(void); -void rt305x_register_spi(struct spi_board_info *info, int n); -void rt305x_register_usb(void); - -#endif /* __RT305X_DEVICES_H */ - diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/early_printk.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/early_printk.c deleted file mode 100644 index 602df863ef..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/early_printk.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Ralink RT305x SoC early printk support - * - * Copyright (C) 2009 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include - -#include - -#include - -#define UART_READ(r) \ - __raw_readl((void __iomem *)(KSEG1ADDR(RT305X_UART1_BASE) + 4 * (r))) - -#define UART_WRITE(r, v) \ - __raw_writel((v), (void __iomem *)(KSEG1ADDR(RT305X_UART1_BASE) + 4 * (r))) - -void prom_putchar(unsigned char ch) -{ - while (((UART_READ(UART_REG_LSR)) & UART_LSR_THRE) == 0); - UART_WRITE(UART_REG_TX, ch); - while (((UART_READ(UART_REG_LSR)) & UART_LSR_THRE) == 0); -} diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/irq.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/irq.c deleted file mode 100644 index fcac2dd860..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/irq.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Ralink RT305x SoC specific interrupt handling - * - * Copyright (C) 2009 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include - -#include -#include - -#include -#include -#include - -static void rt305x_intc_irq_dispatch(void) -{ - u32 pending; - - pending = ramips_intc_get_status(); - - if (pending & RT305X_INTC_INT_TIMER0) - do_IRQ(RT305X_INTC_IRQ_TIMER0); - - else if (pending & RT305X_INTC_INT_TIMER1) - do_IRQ(RT305X_INTC_IRQ_TIMER1); - - else if (pending & RT305X_INTC_INT_UART0) - do_IRQ(RT305X_INTC_IRQ_UART0); - - else if (pending & RT305X_INTC_INT_UART1) - do_IRQ(RT305X_INTC_IRQ_UART1); - - else if (pending & RT305X_INTC_INT_PERFC) - do_IRQ(RT305X_INTC_IRQ_PERFC); - - else if (pending & RT305X_INTC_INT_OTG) - do_IRQ(RT305X_INTC_IRQ_OTG); - - /* TODO: handle PIO interrupts as well */ - - else - spurious_interrupt(); -} - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned long pending; - - pending = read_c0_status() & read_c0_cause() & ST0_IM; - - if (pending & STATUSF_IP7) - do_IRQ(RT305X_CPU_IRQ_COUNTER); - - else if (pending & STATUSF_IP5) - do_IRQ(RT305X_CPU_IRQ_FE); - - else if (pending & STATUSF_IP6) - do_IRQ(RT305X_CPU_IRQ_WNIC); - - else if (pending & STATUSF_IP2) - rt305x_intc_irq_dispatch(); - - else - spurious_interrupt(); -} - -void __init arch_init_irq(void) -{ - mips_cpu_irq_init(); - ramips_intc_irq_init(RT305X_INTC_BASE, RT305X_CPU_IRQ_INTC, - RT305X_INTC_IRQ_BASE); - - cp0_perfcount_irq = RT305X_INTC_IRQ_PERFC; -} diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-3g-6200n.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-3g-6200n.c deleted file mode 100644 index ade4fe9008..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-3g-6200n.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Edimax 3g-6200n board support - * - * Copyright (C) 2011 Andrzej Hajda - * Copyright (C) 2012 Lukasz Golebiowski - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - - -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define EDIMAX_GPIO_BUTTON_WPS 12 -#define EDIMAX_GPIO_BTN_0 13 /* Wifi on/off switch button */ - -#define EDIMAX_GPIO_LED_POWER 9 -#define EDIMAX_GPIO_LED_WLAN 14 -#define EDIMAX_GPIO_LED_3G 7 - -#define EDIMAX_KEYS_POLL_INTERVAL 20 -#define EDIMAX_KEYS_DEBOUNCE_INTERVAL (3 * EDIMAX_KEYS_POLL_INTERVAL) - -static struct gpio_led edimax_leds_gpio[] __initdata = { - { - .name = "edimax:green:power", - .gpio = EDIMAX_GPIO_LED_POWER, - .active_low = 1, - }, { - .name = "edimax:amber:wlan", - .gpio = EDIMAX_GPIO_LED_WLAN, - .active_low = 1, - }, { - .name = "edimax:blue:3g", - .gpio = EDIMAX_GPIO_LED_3G, - .active_low = 1, - } -}; - -static struct gpio_keys_button edimax_gpio_buttons[] __initdata = { - { - .desc = "wps", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = EDIMAX_KEYS_DEBOUNCE_INTERVAL, - .gpio = EDIMAX_GPIO_BUTTON_WPS, - .active_low = 1, - }, { - .desc = "wlanswitch", - .type = EV_KEY, - .code = BTN_0, - .debounce_interval = EDIMAX_KEYS_DEBOUNCE_INTERVAL, - .gpio = EDIMAX_GPIO_BTN_0, - .active_low = 1, - } -}; - -static void __init edimax_init(void) -{ - rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); - - rt305x_register_flash(0); - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; - rt305x_register_ethernet(); - ramips_register_gpio_leds(-1, ARRAY_SIZE(edimax_leds_gpio), - edimax_leds_gpio); - ramips_register_gpio_buttons(-1, EDIMAX_KEYS_POLL_INTERVAL, - ARRAY_SIZE(edimax_gpio_buttons), - edimax_gpio_buttons); - rt305x_register_wifi(); - rt305x_register_wdt(); - rt305x_register_usb(); -} - -MIPS_MACHINE(RAMIPS_MACH_3G_6200N, "3G-6200N", "Edimax 3g-6200n", - edimax_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-3g300m.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-3g300m.c deleted file mode 100644 index e4993b303e..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-3g300m.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Tenda 3G300M board support - * - * Copyright (C) 2013 Cezary Jackiewicz - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define TENDA_3G300M_GPIO_BUTTON_RESET 0 -#define TENDA_3G300M_GPIO_BUTTON_MODE 10 - -#define TENDA_3G300M_GPIO_LED_3GROUTER 11 -#define TENDA_3G300M_GPIO_LED_AP 12 -#define TENDA_3G300M_GPIO_LED_WISPROUTER 9 -#define TENDA_3G300M_GPIO_LED_WIRELESSROUTER 13 -#define TENDA_3G300M_GPIO_LED_3G 7 -#define TENDA_3G300M_GPIO_LED_WPSRESET 14 - -#define TENDA_3G300M_KEYS_POLL_INTERVAL 20 -#define TENDA_3G300M_KEYS_DEBOUNCE_INTERVAL (3 * TENDA_3G300M_KEYS_POLL_INTERVAL) - -const struct flash_platform_data tenda_3g300m_flash = { - .type = "mx25l3205d", -}; - -struct spi_board_info tenda_3g300m_spi_slave_info[] __initdata = { - { - .modalias = "m25p80", - .platform_data = &tenda_3g300m_flash, - .irq = -1, - .max_speed_hz = 10000000, - .bus_num = 0, - .chip_select = 0, - } -}; - -static struct gpio_led tenda_3g300m_leds_gpio[] __initdata = { - { - .name = "tenda:blue:3grouter", - .gpio = TENDA_3G300M_GPIO_LED_3GROUTER, - .active_low = 1, - },{ - .name = "tenda:blue:ap", - .gpio = TENDA_3G300M_GPIO_LED_AP, - .active_low = 1, - },{ - .name = "tenda:blue:wisprouter", - .gpio = TENDA_3G300M_GPIO_LED_WISPROUTER, - .active_low = 1, - },{ - .name = "tenda:blue:wirelessrouter", - .gpio = TENDA_3G300M_GPIO_LED_WIRELESSROUTER, - .active_low = 1, - },{ - .name = "tenda:blue:3g", - .gpio = TENDA_3G300M_GPIO_LED_3G, - .active_low = 1, - },{ - .name = "tenda:blue:wpsreset", - .gpio = TENDA_3G300M_GPIO_LED_WPSRESET, - .active_low = 1, - } -}; - -static struct gpio_keys_button tenda_3g300m_gpio_buttons[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = TENDA_3G300M_KEYS_DEBOUNCE_INTERVAL, - .gpio = TENDA_3G300M_GPIO_BUTTON_RESET, - .active_low = 1, - },{ - .desc = "mode", - .type = EV_KEY, - .code = BTN_0, - .debounce_interval = TENDA_3G300M_KEYS_DEBOUNCE_INTERVAL, - .gpio = TENDA_3G300M_GPIO_BUTTON_MODE, - .active_low = 1, - } -}; - -static void __init tenda_3g300m_init(void) -{ - rt305x_gpio_init((RT305X_GPIO_MODE_GPIO << - RT305X_GPIO_MODE_UART0_SHIFT) | - RT305X_GPIO_MODE_JTAG); - - rt305x_register_spi(tenda_3g300m_spi_slave_info, - ARRAY_SIZE(tenda_3g300m_spi_slave_info)); - - ramips_register_gpio_leds(-1, ARRAY_SIZE(tenda_3g300m_leds_gpio), - tenda_3g300m_leds_gpio); - - ramips_register_gpio_buttons(-1, TENDA_3G300M_KEYS_POLL_INTERVAL, - ARRAY_SIZE(tenda_3g300m_gpio_buttons), - tenda_3g300m_gpio_buttons); - - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; - rt305x_register_ethernet(); - - rt305x_register_wifi(); - - rt305x_register_wdt(); - - rt305x_register_usb(); -} - -MIPS_MACHINE(RAMIPS_MACH_3G300M, "3G300M", "Tenda 3G300M", - tenda_3g300m_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-air3gii.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-air3gii.c deleted file mode 100644 index aca238abe1..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-air3gii.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * AirLive Air3GII board support - * - * Copyright (C) 2012 Cezary Jackiewicz - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define AIR3GII_GPIO_BUTTON_WPS 7 - -#define AIR3GII_GPIO_LED_WLAN 8 -#define AIR3GII_GPIO_LED_MOBILE 9 - -#define AIR3GII_KEYS_POLL_INTERVAL 20 -#define AIR3GII_KEYS_DEBOUNCE_INTERVAL (3 * AIR3GII_KEYS_POLL_INTERVAL) - -const struct flash_platform_data air3gii_flash = { - .type = "en25q32b", -}; - -struct spi_board_info air3gii_spi_slave_info[] __initdata = { - { - .modalias = "m25p80", - .platform_data = &air3gii_flash, - .irq = -1, - .max_speed_hz = 10000000, - .bus_num = 0, - .chip_select = 0, - }, -}; - -static struct gpio_led air3gii_leds_gpio[] __initdata = { - { - .name = "airlive:green:wlan", - .gpio = AIR3GII_GPIO_LED_WLAN, - .active_low = 0, - }, { - .name = "airlive:green:mobile", - .gpio = AIR3GII_GPIO_LED_MOBILE, - .active_low = 1, - } -}; - -static struct gpio_keys_button air3gii_gpio_buttons[] __initdata = { - { - .desc = "wps", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = AIR3GII_KEYS_DEBOUNCE_INTERVAL, - .gpio = AIR3GII_GPIO_BUTTON_WPS, - .active_low = 1, - } -}; - -static void __init air3gii_init(void) -{ - rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); - - rt305x_register_spi(air3gii_spi_slave_info, - ARRAY_SIZE(air3gii_spi_slave_info)); - - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; - rt305x_register_ethernet(); - - ramips_register_gpio_leds(-1, ARRAY_SIZE(air3gii_leds_gpio), - air3gii_leds_gpio); - - ramips_register_gpio_buttons(-1, AIR3GII_KEYS_POLL_INTERVAL, - ARRAY_SIZE(air3gii_gpio_buttons), - air3gii_gpio_buttons); - - rt305x_register_wifi(); - rt305x_register_wdt(); - rt305x_register_usb(); -} - -MIPS_MACHINE(RAMIPS_MACH_AIR3GII, "AIR3GII", "AirLive Air3GII", - air3gii_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-all0256n.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-all0256n.c deleted file mode 100644 index 7f5e00b418..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-all0256n.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Allnet ALL0256N board support - * - * Copyright (C) 2012 Daniel Golle - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define ALL0256N_GPIO_BUTTON_RESET 0 -#define ALL0256N_GPIO_LED_RSSI_LOW 14 -#define ALL0256N_GPIO_LED_RSSI_MED 12 -#define ALL0256N_GPIO_LED_RSSI_HIGH 13 -#define ALL0256N_KEYS_POLL_INTERVAL 20 -#define ALL0256N_KEYS_DEBOUNCE_INTERVAL (3 * ALL0256N_KEYS_POLL_INTERVAL) - -const struct flash_platform_data all0256n_flash = { - .type = "mx25l3205d", -}; - -struct spi_board_info all0256n_spi_slave_info[] __initdata = { - { - .modalias = "m25p80", - .platform_data = &all0256n_flash, - .irq = -1, - .max_speed_hz = 10000000, - .bus_num = 0, - .chip_select = 0, - }, -}; - -static struct gpio_keys_button all0256n_gpio_buttons[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = ALL0256N_KEYS_DEBOUNCE_INTERVAL, - .gpio = ALL0256N_GPIO_BUTTON_RESET, - .active_low = 1, - } -}; - -static struct gpio_led all0256n_leds_gpio[] __initdata = { - { - .name = "all0256n:green:rssilow", - .gpio = ALL0256N_GPIO_LED_RSSI_LOW, - .active_low = 1, - }, { - .name = "all0256n:green:rssimed", - .gpio = ALL0256N_GPIO_LED_RSSI_MED, - .active_low = 1, - }, { - .name = "all0256n:green:rssihigh", - .gpio = ALL0256N_GPIO_LED_RSSI_HIGH, - .active_low = 1, - } -}; - -static void __init all0256n_init(void) -{ - rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); - rt305x_register_spi(all0256n_spi_slave_info, - ARRAY_SIZE(all0256n_spi_slave_info)); - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_NONE; - rt305x_register_ethernet(); - ramips_register_gpio_leds(-1, ARRAY_SIZE(all0256n_leds_gpio), - all0256n_leds_gpio); - ramips_register_gpio_buttons(-1, ALL0256N_KEYS_POLL_INTERVAL, - ARRAY_SIZE(all0256n_gpio_buttons), - all0256n_gpio_buttons); - rt305x_register_wifi(); - rt305x_register_wdt(); -} - -MIPS_MACHINE(RAMIPS_MACH_ALL0256N, "ALL0256N", "Allnet ALL0256N", - all0256n_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-all5002.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-all5002.c deleted file mode 100644 index 71938f028c..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-all5002.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Allnet ALL5002 - * - * Copyright (C) 2012 Daniel Golle - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -// #define ALL5002_GPIO_BUTTON_RESET 0 -// #define ALL5002_GPIO_LED_RSSI_LOW 14 -// #define ALL5002_GPIO_LED_RSSI_MED 12 -// #define ALL5002_GPIO_LED_RSSI_HIGH 13 -// #define ALL5002_BUTTONS_POLL_INTERVAL 20 - -const struct flash_platform_data all5002_flash = { - .type = "mx25l25635e", -}; - -struct spi_board_info all5002_spi_slave_info[] __initdata = { - { - .modalias = "m25p80", - .platform_data = &all5002_flash, - .irq = -1, - .max_speed_hz = 10000000, - .bus_num = 0, - .chip_select = 0, - }, -}; - -static void __init all5002_init(void) -{ - rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); - rt305x_register_spi(all5002_spi_slave_info, - ARRAY_SIZE(all5002_spi_slave_info)); - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_NONE; - rt305x_register_ethernet(); - rt305x_register_wifi(); - rt305x_register_wdt(); - rt305x_register_usb(); -} - -MIPS_MACHINE(RAMIPS_MACH_ALL5002, "ALL5002", "Allnet ALL5002/ALL5003", - all5002_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-argus-atp52b.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-argus-atp52b.c deleted file mode 100644 index b683485d71..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-argus-atp52b.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Argus ATP-52B router support - * http://www.argus-co.com/english/productsview.php?id=70&cid=81 - * - * Copyright (C) 2011 Roman Yeryomin - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define ARGUS_ATP52B_GPIO_LED_RUN 9 -#define ARGUS_ATP52B_GPIO_LED_NET 13 -#define ARGUS_ATP52B_GPIO_BUTTON_WPS 0 -#define ARGUS_ATP52B_GPIO_BUTTON_RESET 10 -#define ARGUS_ATP52B_KEYS_POLL_INTERVAL 20 -#define ARGUS_ATP52B_KEYS_DEBOUNCE_INTERVAL (3 * ARGUS_ATP52B_KEYS_POLL_INTERVAL) - -static struct gpio_led argus_atp52b_leds_gpio[] __initdata = { - { - .name = "argus-atp52b:green:run", - .gpio = ARGUS_ATP52B_GPIO_LED_RUN, - .active_low = 1, - }, - { - .name = "argus-atp52b:amber:net", - .gpio = ARGUS_ATP52B_GPIO_LED_NET, - .active_low = 1, - } -}; - -static struct gpio_keys_button argus_atp52b_gpio_buttons[] __initdata = { - { - .desc = "wps", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = ARGUS_ATP52B_KEYS_DEBOUNCE_INTERVAL, - .gpio = ARGUS_ATP52B_GPIO_BUTTON_WPS, - .active_low = 1, - }, - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = ARGUS_ATP52B_KEYS_DEBOUNCE_INTERVAL, - .gpio = ARGUS_ATP52B_GPIO_BUTTON_RESET, - .active_low = 1, - } -}; - -static void __init argus_atp52b_init(void) -{ - rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); - - rt305x_register_flash(0); - - ramips_register_gpio_leds(-1, ARRAY_SIZE(argus_atp52b_leds_gpio), - argus_atp52b_leds_gpio); - ramips_register_gpio_buttons(-1, ARGUS_ATP52B_KEYS_POLL_INTERVAL, - ARRAY_SIZE(argus_atp52b_gpio_buttons), - argus_atp52b_gpio_buttons); - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL; - rt305x_register_ethernet(); - rt305x_register_wifi(); - rt305x_register_wdt(); - rt305x_register_usb(); -} - -MIPS_MACHINE(RAMIPS_MACH_ARGUS_ATP52B, "ARGUS_ATP52B", "Argus ATP-52B", - argus_atp52b_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-bc2.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-bc2.c deleted file mode 100644 index 7a21488511..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-bc2.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * NexAira BC2 board support - * - * Copyright (C) 2011 Adam J. Porter - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define BC2_GPIO_BUTTON_RESET 17 -#define BC2_GPIO_LED_USB 20 - -#define BC2_KEYS_POLL_INTERVAL 20 -#define BC2_KEYS_DEBOUNCE_INTERVAL (3 * BC2_KEYS_POLL_INTERVAL) - -static struct gpio_led bc2_leds_gpio[] __initdata = { - { - .name = "bc2:blue:usb", - .gpio = BC2_GPIO_LED_USB, - .active_low = 1, - } -}; - -static struct gpio_keys_button bc2_gpio_buttons[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = BC2_KEYS_DEBOUNCE_INTERVAL, - .gpio = BC2_GPIO_BUTTON_RESET, - .active_low = 1, - } -}; - -static void __init bc2_init(void) -{ - rt305x_gpio_init((RT305X_GPIO_MODE_GPIO << - RT305X_GPIO_MODE_UART0_SHIFT) | - RT305X_GPIO_MODE_JTAG); - - rt305x_register_flash(0); - - ramips_register_gpio_leds(-1, ARRAY_SIZE(bc2_leds_gpio), - bc2_leds_gpio); - - ramips_register_gpio_buttons(-1, BC2_KEYS_POLL_INTERVAL, - ARRAY_SIZE(bc2_gpio_buttons), - bc2_gpio_buttons); - - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; - rt305x_register_ethernet(); - rt305x_register_wifi(); - rt305x_register_wdt(); - rt305x_register_usb(); -} - -MIPS_MACHINE(RAMIPS_MACH_BC2, "BC2", "NexAira BC2", - bc2_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-br6425.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-br6425.c deleted file mode 100644 index 3a24516496..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-br6425.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Edimax BR-6425 board support - * - * Copyright (C) 2012 OpenWrt.org - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define BR6425_GPIO_LED_POWER 9 -#define BR6425_GPIO_BUTTON_RESET 12 -#define BR6425_GPIO_SWITCH_RFKILL 13 -#define BR6425_GPIO_LED_WLAN 14 -#define BR6425_KEYS_POLL_INTERVAL 20 -#define BR6425_KEYS_DEBOUNCE_INTERVAL (3 * BR6425_KEYS_POLL_INTERVAL) - -static struct gpio_keys_button br6425_gpio_buttons[] __initdata = { - { - .desc = "reset_wps", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = BR6425_KEYS_DEBOUNCE_INTERVAL, - .gpio = BR6425_GPIO_BUTTON_RESET, - .active_low = 1, - }, - { - .desc = "RFKILL switch", - .type = EV_SW, - .code = KEY_RFKILL, - .debounce_interval = BR6425_KEYS_DEBOUNCE_INTERVAL, - .gpio = BR6425_GPIO_SWITCH_RFKILL, - .active_low = 1, - }, -}; - -static struct gpio_led br6425_leds_gpio[] __initdata = { - { - .name = "edimax:green:power", - .gpio = BR6425_GPIO_LED_POWER, - .active_low = 1, - }, { - .name = "edimax:orange:wlan", - .gpio = BR6425_GPIO_LED_WLAN, - .active_low = 1, - }, -}; - -static void __init br6425_init(void) -{ - rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); - rt305x_register_flash(0); - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; - rt305x_register_ethernet(); - ramips_register_gpio_leds(-1, ARRAY_SIZE(br6425_leds_gpio), - br6425_leds_gpio); - ramips_register_gpio_buttons(-1, BR6425_KEYS_POLL_INTERVAL, - ARRAY_SIZE(br6425_gpio_buttons), - br6425_gpio_buttons); - rt305x_register_wifi(); - rt305x_register_wdt(); -} - -MIPS_MACHINE(RAMIPS_MACH_BR6425, "BR-6425", "Edimax BR-6425", - br6425_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-broadway.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-broadway.c deleted file mode 100644 index 74dfaa30b0..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-broadway.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Hauppauge/PCTV Broadway Support - * - * Copyright (C) 2012 Devin Heitmueller - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define BROADWAY_GPIO_LED_DISKMOUNT 9 -#define BROADWAY_GPIO_LED_WPS 14 - -#define BROADWAY_GPIO_BUTTON_WPS 0 -#define BROADWAY_GPIO_BUTTON_FACTORYRESET 13 - -#define BROADWAY_KEYS_POLL_INTERVAL 20 -#define BROADWAY_KEYS_DEBOUNCE_INTERVAL (3 * BROADWAY_KEYS_POLL_INTERVAL) - -static struct gpio_led broadway_leds_gpio[] __initdata = { - { - .name = "red:diskmounted", - .gpio = BROADWAY_GPIO_LED_DISKMOUNT, - .active_low = 1, - }, - { - .name = "red:wps_active", - .gpio = BROADWAY_GPIO_LED_WPS, - .active_low = 1, - }, -}; - -static struct gpio_keys_button broadway_gpio_buttons[] __initdata = { - { - .desc = "Factory Reset button", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = BROADWAY_KEYS_DEBOUNCE_INTERVAL, - .gpio = BROADWAY_GPIO_BUTTON_FACTORYRESET, - .active_low = 1, - }, -#ifdef DJH_WPS_BUTTON_NOT_WIRED_TO_GPIO - { - .desc = "WPS button", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = BROADWAY_KEYS_DEBOUNCE_INTERVAL, - .gpio = BROADWAY_GPIO_BUTTON_WPS, - .active_low = 1, - }, -#endif -}; - -static void __init broadway_init(void) -{ - rt305x_gpio_init((RT305X_GPIO_MODE_GPIO << - RT305X_GPIO_MODE_UART0_SHIFT)); - - rt305x_register_flash(0); - - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL; - rt305x_register_ethernet(); - - ramips_register_gpio_leds(-1, ARRAY_SIZE(broadway_leds_gpio), - broadway_leds_gpio); - ramips_register_gpio_buttons(-1, BROADWAY_KEYS_POLL_INTERVAL, - ARRAY_SIZE(broadway_gpio_buttons), - broadway_gpio_buttons); - - rt305x_register_wifi(); - rt305x_register_wdt(); - rt305x_register_usb(); -} - -MIPS_MACHINE(RAMIPS_MACH_BROADWAY, "BROADWAY", "Hauppauge Broadway", - broadway_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-carambola.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-carambola.c deleted file mode 100644 index c24527a7ba..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-carambola.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * 8devices Carambola dev board support - * - * Copyright (C) 2012 Tobias Diedrich - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -static void __init carambola_init(void) -{ - /* Ugh, inverted logic... - * This actually puts the pins into GPIO mode rather I2C, SPI, ... */ - rt305x_gpio_init(RT305X_GPIO_MODE_UART0(RT305X_GPIO_MODE_GPIO) | - RT305X_GPIO_MODE_I2C | - RT305X_GPIO_MODE_SPI | - RT305X_GPIO_MODE_JTAG | - RT305X_GPIO_MODE_MDIO); - - rt305x_register_flash(0); - - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_NONE; - rt305x_register_ethernet(); - rt305x_register_wifi(); - rt305x_register_wdt(); - rt305x_register_usb(); -} - -MIPS_MACHINE(RAMIPS_MACH_CARAMBOLA, "CARAMBOLA", "8devices Carambola", - carambola_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-dap-1350.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-dap-1350.c deleted file mode 100644 index 17a49aac5a..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-dap-1350.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * D-Link DAP-1350 board support - */ - -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define DAP_1350_GPIO_LED_POWER_BLUE 8 -#define DAP_1350_GPIO_LED_POWER_RED 9 -#define DAP_1350_GPIO_LED_WPS 14 - -#define DAP_1350_GPIO_BUTTON_WPS 0 /* active low */ -#define DAP_1350_GPIO_BUTTON_RESET 10 /* active low */ -#define DAP_1350_GPIO_SWITCH_MODE_AP 7 /* active low */ -#define DAP_1350_GPIO_SWITCH_MODE_RT 11 /* active low */ - -#define DAP_1350_KEYS_POLL_INTERVAL 20 -#define DAP_1350_KEYS_DEBOUNCE_INTERVAL (3 * DAP_1350_KEYS_POLL_INTERVAL) - -static struct gpio_led dap_1350_leds_gpio[] __initdata = { - { - .name = "d-link:blue:power", - .gpio = DAP_1350_GPIO_LED_POWER_BLUE, - .active_low = 1, - }, { - .name = "d-link:red:power", - .gpio = DAP_1350_GPIO_LED_POWER_RED, - .active_low = 1, - }, { - .name = "d-link:blue:wps", - .gpio = DAP_1350_GPIO_LED_WPS, - .active_low = 1, - } -}; - -static struct gpio_keys_button dap_1350_gpio_buttons[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = DAP_1350_KEYS_DEBOUNCE_INTERVAL, - .gpio = DAP_1350_GPIO_BUTTON_RESET, - .active_low = 1, - }, { - .desc = "wps", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = DAP_1350_KEYS_DEBOUNCE_INTERVAL, - .gpio = DAP_1350_GPIO_BUTTON_WPS, - .active_low = 1, - }, { - .desc = "rt", - .type = EV_KEY, - .code = BTN_0, - .debounce_interval = DAP_1350_KEYS_DEBOUNCE_INTERVAL, - .gpio = DAP_1350_GPIO_SWITCH_MODE_RT, - .active_low = 1, - }, { - .desc = "ap", - .type = EV_KEY, - .code = BTN_1, - .debounce_interval = DAP_1350_KEYS_DEBOUNCE_INTERVAL, - .gpio = DAP_1350_GPIO_SWITCH_MODE_AP, - .active_low = 1, - } -}; - -static void __init dap_1350_init(void) -{ - rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); - - rt305x_register_flash(0); - - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; - rt305x_register_ethernet(); - ramips_register_gpio_leds(-1, ARRAY_SIZE(dap_1350_leds_gpio), - dap_1350_leds_gpio); - ramips_register_gpio_buttons(-1, DAP_1350_KEYS_POLL_INTERVAL, - ARRAY_SIZE(dap_1350_gpio_buttons), - dap_1350_gpio_buttons); - rt305x_register_wifi(); - rt305x_register_wdt(); - rt305x_register_usb(); -} - -MIPS_MACHINE(RAMIPS_MACH_DAP_1350, "DAP-1350", "D-Link DAP-1350", - dap_1350_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-dir-300-revb.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-dir-300-revb.c deleted file mode 100644 index 3ae1b7852c..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-dir-300-revb.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * D-Link DIR-300 rev B board support - * - * Copyright (C) 2009-2010 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define DIR_300B_GPIO_LED_STATUS_AMBER 8 -#define DIR_300B_GPIO_LED_STATUS_GREEN 9 -#define DIR_300B_GPIO_LED_WPS 13 -/* - * NOTE: The wan led is also connected to the switch, both - * switch and gpio must be active to make it light up - */ -#define DIR_300B_GPIO_LED_WAN_GREEN 12 -#define DIR_300B_GPIO_LED_WAN_AMBER 14 - -/* - * NOTE: the WPS led in DIR-620 consists of two antiparallel leds, - * so they can't be lit simultaneously - */ -#define DIR_620_GPIO_LED_WPS_AMBER 11 - -#define DIR_300B_GPIO_BUTTON_WPS 0 /* active low */ -#define DIR_300B_GPIO_BUTTON_RESET 10 /* active low */ - -#define DIR_300B_KEYS_POLL_INTERVAL 20 -#define DIR_300B_KEYS_DEBOUNCE_INTERVAL (3 * DIR_300B_KEYS_POLL_INTERVAL) - -static struct gpio_led dir_300b_leds_gpio[] __initdata = { - { - .name = "d-link:amber:status", - .gpio = DIR_300B_GPIO_LED_STATUS_AMBER, - .active_low = 1, - }, { - .name = "d-link:green:status", - .gpio = DIR_300B_GPIO_LED_STATUS_GREEN, - .active_low = 1, - }, { - .name = "d-link:amber:wan", - .gpio = DIR_300B_GPIO_LED_WAN_AMBER, - .active_low = 1, - }, { - .name = "d-link:green:wan", - .gpio = DIR_300B_GPIO_LED_WAN_GREEN, - .active_low = 1, - }, { - .name = "d-link:blue:wps", - .gpio = DIR_300B_GPIO_LED_WPS, - .active_low = 1, - } -}; - -static struct gpio_keys_button dir_300b_gpio_buttons[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = DIR_300B_KEYS_DEBOUNCE_INTERVAL, - .gpio = DIR_300B_GPIO_BUTTON_RESET, - .active_low = 1, - }, { - .desc = "wps", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = DIR_300B_KEYS_DEBOUNCE_INTERVAL, - .gpio = DIR_300B_GPIO_BUTTON_WPS, - .active_low = 1, - } -}; - -static struct gpio_led dir_620_leds_gpio[] __initdata = { - { - .name = "d-link:amber:status", - .gpio = DIR_300B_GPIO_LED_STATUS_AMBER, - .active_low = 1, - }, { - .name = "d-link:green:status", - .gpio = DIR_300B_GPIO_LED_STATUS_GREEN, - .active_low = 1, - }, { - .name = "d-link:amber:wan", - .gpio = DIR_300B_GPIO_LED_WAN_AMBER, - .active_low = 1, - }, { - .name = "d-link:green:wan", - .gpio = DIR_300B_GPIO_LED_WAN_GREEN, - .active_low = 1, - }, { - .name = "d-link:blue:wps", - .gpio = DIR_300B_GPIO_LED_WPS, - }, { - .name = "d-link:amber:wps", - .gpio = DIR_620_GPIO_LED_WPS_AMBER, - } -}; - -static void __init dir_common_init(void) -{ - rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); - - rt305x_register_flash(0); - - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; - rt305x_register_ethernet(); - ramips_register_gpio_buttons(-1, DIR_300B_KEYS_POLL_INTERVAL, - ARRAY_SIZE(dir_300b_gpio_buttons), - dir_300b_gpio_buttons); - rt305x_register_wifi(); - rt305x_register_wdt(); -} - -static void __init dir_300b_init(void) -{ - dir_common_init(); - ramips_register_gpio_leds(-1, ARRAY_SIZE(dir_300b_leds_gpio), - dir_300b_leds_gpio); -} - -static void __init dir_620a1_init(void) -{ - dir_common_init(); - ramips_register_gpio_leds(-1, ARRAY_SIZE(dir_620_leds_gpio), - dir_620_leds_gpio); - rt305x_register_usb(); -} - -MIPS_MACHINE(RAMIPS_MACH_DIR_300_B1, "DIR-300-B1", "D-Link DIR-300 B1", - dir_300b_init); - -MIPS_MACHINE(RAMIPS_MACH_DIR_600_B1, "DIR-600-B1", "D-Link DIR-600 B1", - dir_300b_init); - -MIPS_MACHINE(RAMIPS_MACH_DIR_600_B2, "DIR-600-B2", "D-Link DIR-600 B2", - dir_300b_init); - -MIPS_MACHINE(RAMIPS_MACH_DIR_615_D, "DIR-615-D", "D-Link DIR-615 D", - dir_300b_init); - -MIPS_MACHINE(RAMIPS_MACH_DIR_620_A1, "DIR-620-A1", "D-Link DIR-620 A1", - dir_620a1_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-dir-615-h1.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-dir-615-h1.c deleted file mode 100644 index dbfe4aa92f..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-dir-615-h1.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * D-Link DIR-615 H1 - * - * Copyright (C) 2012 Mikko Hissa - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define DIR_615_H1_GPIO_LED_WAN_AMBER 12 /* active low */ -#define DIR_615_H1_GPIO_LED_WAN_GREEN 13 /* active low */ -#define DIR_615_H1_GPIO_LED_WPS_BLUE 14 /* active low */ - -#define DIR_615_H1_GPIO_LED_STATUS_AMBER 7 -#define DIR_615_H1_GPIO_LED_STATUS_GREEN 9 - -#define DIR_615_H1_GPIO_BUTTON_RESET 10 /* active low */ -#define DIR_615_H1_GPIO_BUTTON_WPS 0 /* active low */ - -#define DIR_615_H1_KEYS_POLL_INTERVAL 20 -#define DIR_615_H1_KEYS_DEBOUNCE_INTERVAL (3 * DIR_615_H1_KEYS_POLL_INTERVAL) - -static struct gpio_led dir_615_h1_leds_gpio[] __initdata = { - { - .name = "d-link:amber:status", - .gpio = DIR_615_H1_GPIO_LED_STATUS_AMBER, - }, { - .name = "d-link:green:status", - .gpio = DIR_615_H1_GPIO_LED_STATUS_GREEN, - }, { - .name = "d-link:amber:wan", - .gpio = DIR_615_H1_GPIO_LED_WAN_AMBER, - .active_low = 1, - }, { - .name = "d-link:green:wan", - .gpio = DIR_615_H1_GPIO_LED_WAN_GREEN, - .active_low = 1, - }, { - .name = "d-link:blue:wps", - .gpio = DIR_615_H1_GPIO_LED_WPS_BLUE, - .active_low = 1, - } -}; - -static struct gpio_keys_button dir_615_h1_gpio_buttons[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = DIR_615_H1_KEYS_DEBOUNCE_INTERVAL, - .gpio = DIR_615_H1_GPIO_BUTTON_RESET, - .active_low = 1, - }, { - .desc = "wps", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = DIR_615_H1_KEYS_DEBOUNCE_INTERVAL, - .gpio = DIR_615_H1_GPIO_BUTTON_WPS, - .active_low = 1, - } -}; - -const struct flash_platform_data dir615h1_flash = { - .type = "mx25l3205d", -}; - -struct spi_board_info dir615h1_spi_slave_info[] __initdata = { - { - .modalias = "m25p80", - .platform_data = &dir615h1_flash, - .irq = -1, - .max_speed_hz = 10000000, - .bus_num = 0, - .chip_select = 0, - }, -}; - -static void __init dir615h1_init(void) -{ - rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); - rt305x_register_spi(dir615h1_spi_slave_info, - ARRAY_SIZE(dir615h1_spi_slave_info)); - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; - rt305x_register_ethernet(); - ramips_register_gpio_leds(-1, ARRAY_SIZE(dir_615_h1_leds_gpio), - dir_615_h1_leds_gpio); - ramips_register_gpio_buttons(-1, DIR_615_H1_KEYS_POLL_INTERVAL, - ARRAY_SIZE(dir_615_h1_gpio_buttons), - dir_615_h1_gpio_buttons); - rt305x_register_wifi(); - rt305x_register_wdt(); -} - -MIPS_MACHINE(RAMIPS_MACH_DIR_615_H1, "DIR-615-H1", "D-Link DIR-615 H1", - dir615h1_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-esr-9753.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-esr-9753.c deleted file mode 100644 index d5f65df5ec..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-esr-9753.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Senao / EnGenius ESR-9753 board support - * - * Copyright (C) 2011 Artur Wronowski - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define ESR_9753_GPIO_LED_POWER 8 -#define ESR_9753_GPIO_LED_WPS 14 - -#define ESR_9753_GPIO_BUTTON_WPS 0 /* active low */ -#define ESR_9753_GPIO_BUTTON_RESET 10 /* active low */ - -#define ESR_9753_KEYS_POLL_INTERVAL 20 -#define ESR_9753_KEYS_DEBOUNCE_INTERVAL (3 * ESR_9753_KEYS_POLL_INTERVAL) - -static struct gpio_led esr_9753_leds_gpio[] __initdata = { - { - .name = "esr-9753:orange:power", - .gpio = ESR_9753_GPIO_LED_POWER, - .active_low = 1, - }, { - .name = "esr-9753:orange:wps", - .gpio = ESR_9753_GPIO_LED_WPS, - .active_low = 1, - } -}; - -static struct gpio_keys_button esr_9753_gpio_buttons[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = ESR_9753_KEYS_DEBOUNCE_INTERVAL, - .gpio = ESR_9753_GPIO_BUTTON_RESET, - .active_low = 1, - }, { - .desc = "wps", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = ESR_9753_KEYS_DEBOUNCE_INTERVAL, - .gpio = ESR_9753_GPIO_BUTTON_WPS, - .active_low = 1, - } -}; - -static void __init esr_9753_init(void) -{ - rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); - - rt305x_register_flash(0); - - ramips_register_gpio_leds(-1, ARRAY_SIZE(esr_9753_leds_gpio), - esr_9753_leds_gpio); - - ramips_register_gpio_buttons(-1, ESR_9753_KEYS_POLL_INTERVAL, - ARRAY_SIZE(esr_9753_gpio_buttons), - esr_9753_gpio_buttons); - - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL; - rt305x_register_ethernet(); - rt305x_register_wifi(); - rt305x_register_wdt(); -} - -MIPS_MACHINE(RAMIPS_MACH_ESR_9753, "ESR-9753", "Senao / EnGenius ESR-9753", - esr_9753_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-f5d8235-v2.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-f5d8235-v2.c deleted file mode 100644 index 073fc75a6e..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-f5d8235-v2.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Belkin F5D8235 v2 board support - * - * Copyright (C) 2010 Roman Yeryomin - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include - -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define F5D8235_V2_GPIO_LED_INTERNET_BLUE 5 -#define F5D8235_V2_GPIO_LED_INTERNET_AMBER 6 -#define F5D8235_V2_GPIO_LED_MODEM_BLUE 11 -#define F5D8235_V2_GPIO_LED_MODEM_AMBER 8 -#define F5D8235_V2_GPIO_LED_ROUTER 9 -#define F5D8235_V2_GPIO_LED_STORAGE_BLUE 23 -#define F5D8235_V2_GPIO_LED_STORAGE_AMBER 22 -#define F5D8235_V2_GPIO_LED_SECURITY_BLUE 13 -#define F5D8235_V2_GPIO_LED_SECURITY_AMBER 12 - -static struct gpio_led f5d8235v2_leds_gpio[] __initdata = { - { - .name = "f5d8235v2:blue:internet", - .gpio = F5D8235_V2_GPIO_LED_INTERNET_BLUE, - .active_low = 1, - }, { - .name = "f5d8235v2:amber:internet", - .gpio = F5D8235_V2_GPIO_LED_INTERNET_AMBER, - .active_low = 1, - }, { - .name = "f5d8235v2:blue:modem", - .gpio = F5D8235_V2_GPIO_LED_MODEM_BLUE, - .active_low = 1, - }, { - .name = "f5d8235v2:amber:modem", - .gpio = F5D8235_V2_GPIO_LED_MODEM_AMBER, - .active_low = 1, - }, { - .name = "f5d8235v2:blue:router", - .gpio = F5D8235_V2_GPIO_LED_ROUTER, - .active_low = 1, - }, { - .name = "f5d8235v2:blue:storage", - .gpio = F5D8235_V2_GPIO_LED_STORAGE_BLUE, - .active_low = 1, - }, { - .name = "f5d8235v2:amber:storage", - .gpio = F5D8235_V2_GPIO_LED_STORAGE_AMBER, - .active_low = 1, - }, { - .name = "f5d8235v2:blue:security", - .gpio = F5D8235_V2_GPIO_LED_SECURITY_BLUE, - .active_low = 1, - }, { - .name = "f5d8235v2:amber:security", - .gpio = F5D8235_V2_GPIO_LED_SECURITY_AMBER, - .active_low = 1, - } -}; - -static struct rtl8366_platform_data f5d8235v2_switch_data = { - .gpio_sda = RT305X_GPIO_I2C_SD, - .gpio_sck = RT305X_GPIO_I2C_SCLK, -}; - -static struct platform_device f5d8235v2_switch = { - .name = RTL8366RB_DRIVER_NAME, - .id = -1, - .dev = { - .platform_data = &f5d8235v2_switch_data, - } -}; - -static void __init f5d8235v2_init(void) -{ - rt305x_gpio_init((RT305X_GPIO_MODE_GPIO << - RT305X_GPIO_MODE_UART0_SHIFT) | - RT305X_GPIO_MODE_I2C | - RT305X_GPIO_MODE_SPI | - RT305X_GPIO_MODE_MDIO); - - rt305x_register_flash(0); - - ramips_register_gpio_leds(-1, ARRAY_SIZE(f5d8235v2_leds_gpio), - f5d8235v2_leds_gpio); - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_NONE; - rt305x_register_ethernet(); - platform_device_register(&f5d8235v2_switch); - rt305x_register_wifi(); - rt305x_register_wdt(); - rt305x_register_usb(); -} - -MIPS_MACHINE(RAMIPS_MACH_F5D8235_V2, "F5D8235_V2", "Belkin F5D8235 v2", - f5d8235v2_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-fonera20n.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-fonera20n.c deleted file mode 100644 index a433e40e91..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-fonera20n.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * La Fonera20N board support - * - * Copyright (C) 2009 John Crispin - * Copyright (C) 2010 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define FONERA20N_GPIO_BUTTON_RESET 12 -#define FONERA20N_GPIO_SWITCH 13 -#define FONERA20N_GPIO_LED_WIFI 7 -#define FONERA20N_GPIO_LED_POWER 9 -#define FONERA20N_GPIO_LED_USB 14 - -#define FONERA20N_KEYS_POLL_INTERVAL 20 -#define FONERA20N_KEYS_DEBOUNCE_INTERVAL (3 * FONERA20N_KEYS_POLL_INTERVAL) - -static struct gpio_led fonera20n_leds_gpio[] __initdata = { - { - .name = "fonera20n:orange:wifi", - .gpio = FONERA20N_GPIO_LED_WIFI, - .active_low = 1, - }, { - .name = "fonera20n:green:power", - .gpio = FONERA20N_GPIO_LED_POWER, - .active_low = 1, - }, { - .name = "fonera20n:orange:usb", - .gpio = FONERA20N_GPIO_LED_USB, - .active_low = 1, - } -}; - -static struct gpio_keys_button fonera20n_gpio_buttons[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = FONERA20N_KEYS_DEBOUNCE_INTERVAL, - .gpio = FONERA20N_GPIO_BUTTON_RESET, - .active_low = 1, - }, { - .desc = "switch", - .type = EV_KEY, - .code = BTN_1, - .debounce_interval = FONERA20N_KEYS_DEBOUNCE_INTERVAL, - .gpio = FONERA20N_GPIO_SWITCH, - .active_low = 1, - } -}; - -static void __init fonera20n_init(void) -{ - rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); - - rt305x_register_flash(0); - - ramips_register_gpio_leds(-1, ARRAY_SIZE(fonera20n_leds_gpio), - fonera20n_leds_gpio); - - ramips_register_gpio_buttons(-1, FONERA20N_KEYS_POLL_INTERVAL, - ARRAY_SIZE(fonera20n_gpio_buttons), - fonera20n_gpio_buttons); - - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; - rt305x_register_ethernet(); - rt305x_register_wifi(); - rt305x_register_wdt(); - rt305x_register_usb(); -} - -MIPS_MACHINE(RAMIPS_MACH_FONERA20N, "FONERA20N", "La Fonera 2.0N", - fonera20n_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-freestation5.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-freestation5.c deleted file mode 100644 index b868244cca..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-freestation5.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * ARC FreeStation2/5 board support - * - * Copyright (C) 2009 John Crispin - * Copyright (C) 2010 Gabor Juhos - * Copyright (C) 2012 Pau Escrich - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include - -#include -#include -#include - -#include "devices.h" - -static void __init freestation5_init(void) -{ - rt305x_register_flash(0); - - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL; - rt305x_register_ethernet(); - rt305x_register_wifi(); - rt305x_register_wdt(); - rt305x_register_usb(); -} - -MIPS_MACHINE(RAMIPS_MACH_FREESTATION5, "FREESTATION5", "ARC FreeStation5", - freestation5_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-hw550-3g.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-hw550-3g.c deleted file mode 100644 index b274b917da..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-hw550-3g.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Aztech HW550-3G board support - * - * Copyright (C) 2011 Layne Edwards - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define HW550_3G_GPIO_LED_USB 8 -#define HW550_3G_GPIO_LED_3G 11 -#define HW550_3G_GPIO_LED_STATUS 12 -#define HW550_3G_GPIO_LED_WPS 14 - -#define HW550_3G_GPIO_BUTTON_RESET 10 -#define HW550_3G_GPIO_BUTTON_CONNECT 7 -#define HW550_3G_GPIO_BUTTON_WPS 0 - -#define HW550_3G_KEYS_POLL_INTERVAL 20 -#define HW550_3G_KEYS_DEBOUNCE_INTERVAL (3 * HW550_3G_KEYS_POLL_INTERVAL) - -static struct gpio_led hw550_3g_leds_gpio[] __initdata = { - { - .name = "hw550-3g:green:usb", - .gpio = HW550_3G_GPIO_LED_USB, - .active_low = 1, - }, { - .name = "hw550-3g:green:3g", - .gpio = HW550_3G_GPIO_LED_3G, - .active_low = 1, - }, { - .name = "hw550-3g:green:status", - .gpio = HW550_3G_GPIO_LED_STATUS, - .active_low = 1, - }, { - .name = "hw550-3g:green:wps", - .gpio = HW550_3G_GPIO_LED_WPS, - .active_low = 1, - } -}; - -static struct gpio_keys_button hw550_3g_gpio_buttons[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = HW550_3G_KEYS_DEBOUNCE_INTERVAL, - .gpio = HW550_3G_GPIO_BUTTON_RESET, - .active_low = 1, - }, { - .desc = "connect", - .type = EV_KEY, - .code = KEY_CONNECT, - .debounce_interval = HW550_3G_KEYS_DEBOUNCE_INTERVAL, - .gpio = HW550_3G_GPIO_BUTTON_CONNECT, - .active_low = 1, - }, { - .desc = "wps", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = HW550_3G_KEYS_DEBOUNCE_INTERVAL, - .gpio = HW550_3G_GPIO_BUTTON_WPS, - .active_low = 1, - } -}; - -#define HW550_3G_GPIO_MODE \ - ((RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT) | \ - RT305X_GPIO_MODE_MDIO) - -static void __init hw550_3g_init(void) -{ - rt305x_gpio_init(HW550_3G_GPIO_MODE); - - rt305x_register_flash(0); - - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL; - rt305x_register_ethernet(); - ramips_register_gpio_leds(-1, ARRAY_SIZE(hw550_3g_leds_gpio), - hw550_3g_leds_gpio); - ramips_register_gpio_buttons(-1, HW550_3G_KEYS_POLL_INTERVAL, - ARRAY_SIZE(hw550_3g_gpio_buttons), - hw550_3g_gpio_buttons); - rt305x_register_wifi(); - rt305x_register_wdt(); - rt305x_register_usb(); -} - -MIPS_MACHINE(RAMIPS_MACH_HW550_3G, "HW550-3G", "Aztech HW550-3G", - hw550_3g_init); - -MIPS_MACHINE(RAMIPS_MACH_ALL0239_3G, "ALL0239-3G", "Allnet ALL0239-3G", - hw550_3g_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-mofi3500-3gn.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-mofi3500-3gn.c deleted file mode 100644 index 38d217a4ff..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-mofi3500-3gn.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * MoFi Network MOFI3500-3GN board support - * - * Copyright (C) 2011 Layne Edwards - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define MOFI3500_3GN_GPIO_LED_USB 8 -#define MOFI3500_3GN_GPIO_LED_3G 11 -#define MOFI3500_3GN_GPIO_LED_STATUS 12 -#define MOFI3500_3GN_GPIO_LED_WPS 14 - -#define MOFI3500_3GN_GPIO_BUTTON_RESET 10 -#define MOFI3500_3GN_GPIO_BUTTON_CONNECT 7 -#define MOFI3500_3GN_GPIO_BUTTON_WPS 0 - -#define MOFI3500_3GN_KEYS_POLL_INTERVAL 20 -#define MOFI3500_3GN_KEYS_DEBOUNCE_INTERVAL (3 * MOFI3500_3GN_KEYS_POLL_INTERVAL) - -static struct gpio_led mofi3500_3gn_leds_gpio[] __initdata = { - { - .name = "mofi3500-3gn:green:usb", - .gpio = MOFI3500_3GN_GPIO_LED_USB, - .active_low = 1, - }, { - .name = "mofi3500-3gn:green:3g", - .gpio = MOFI3500_3GN_GPIO_LED_3G, - .active_low = 1, - }, { - .name = "mofi3500-3gn:green:status", - .gpio = MOFI3500_3GN_GPIO_LED_STATUS, - .active_low = 1, - }, { - .name = "mofi3500-3gn:green:wps", - .gpio = MOFI3500_3GN_GPIO_LED_WPS, - .active_low = 1, - } -}; - -static struct gpio_keys_button mofi3500_3gn_gpio_buttons[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = MOFI3500_3GN_KEYS_DEBOUNCE_INTERVAL, - .gpio = MOFI3500_3GN_GPIO_BUTTON_RESET, - .active_low = 1, - }, { - .desc = "connect", - .type = EV_KEY, - .code = KEY_CONNECT, - .debounce_interval = MOFI3500_3GN_KEYS_DEBOUNCE_INTERVAL, - .gpio = MOFI3500_3GN_GPIO_BUTTON_CONNECT, - .active_low = 1, - }, { - .desc = "wps", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = MOFI3500_3GN_KEYS_DEBOUNCE_INTERVAL, - .gpio = MOFI3500_3GN_GPIO_BUTTON_WPS, - .active_low = 1, - } -}; - -#define MOFI3500_3GN_GPIO_MODE \ - ((RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT) | \ - RT305X_GPIO_MODE_MDIO) - -static void __init mofi3500_3gn_init(void) -{ - rt305x_gpio_init(MOFI3500_3GN_GPIO_MODE); - - rt305x_register_flash(0); - - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; - rt305x_register_ethernet(); - ramips_register_gpio_leds(-1, ARRAY_SIZE(mofi3500_3gn_leds_gpio), - mofi3500_3gn_leds_gpio); - ramips_register_gpio_buttons(-1, MOFI3500_3GN_KEYS_POLL_INTERVAL, - ARRAY_SIZE(mofi3500_3gn_gpio_buttons), - mofi3500_3gn_gpio_buttons); - rt305x_register_wifi(); - rt305x_register_wdt(); - rt305x_register_usb(); -} - -MIPS_MACHINE(RAMIPS_MACH_MOFI3500_3GN, "MOFI3500-3GN", "MoFi Network MOFI3500-3GN", - mofi3500_3gn_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-mzk-w300nh2.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-mzk-w300nh2.c deleted file mode 100644 index 01cabbc0bf..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-mzk-w300nh2.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Planex MZK-W300NH2 board support - * - * Copyright (C) 2012 Samir Ibradžić - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define MZKW300NH2_GPIO_BUTTON_RESET 0 /* active low */ -#define MZKW300NH2_GPIO_BUTTON_WPS 12 /* active low */ -#define MZKW300NH2_GPIO_SWITCH_MODE_RT 13 /* active low */ - -#define MZKW300NH2_GPIO_LED_POWER 9 -#define MZKW300NH2_GPIO_LED_WLAN 14 -#define MZKW300NH2_GPIO_LED_WPS 11 - -#define MZKW300NH2_KEYS_POLL_INTERVAL 20 -#define MZKW300NH2_KEYS_DEBOUNCE_INTERVAL (3 * MZKW300NH2_KEYS_POLL_INTERVAL) - -static struct gpio_led mzkw300nh2_leds_gpio[] __initdata = { - { - .name = "mzkw300nh2:green:power", - .gpio = MZKW300NH2_GPIO_LED_POWER, - .active_low = 1, - }, { - .name = "mzkw300nh2:amber:wlan", - .gpio = MZKW300NH2_GPIO_LED_WLAN, - .active_low = 1, - }, { - .name = "mzkw300nh2:amber:wps", - .gpio = MZKW300NH2_GPIO_LED_WPS, - .active_low = 1, - } -}; - -static struct gpio_keys_button mzkw300nh2_gpio_buttons[] __initdata = { - { - .desc = "wps", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = MZKW300NH2_KEYS_DEBOUNCE_INTERVAL, - .gpio = MZKW300NH2_GPIO_BUTTON_WPS, - .active_low = 1, - }, { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = MZKW300NH2_KEYS_DEBOUNCE_INTERVAL, - .gpio = MZKW300NH2_GPIO_BUTTON_RESET, - .active_low = 1, - }, { - .desc = "rt", - .type = EV_KEY, - .code = BTN_0, - .debounce_interval = MZKW300NH2_KEYS_DEBOUNCE_INTERVAL, - .gpio = MZKW300NH2_GPIO_SWITCH_MODE_RT, - .active_low = 1, - } -}; - -static void __init mzkw300nh2_init(void) -{ - rt305x_gpio_init(RT305X_GPIO_MODE_UART0(RT305X_GPIO_MODE_GPIO) | - RT305X_GPIO_MODE_I2C | - RT305X_GPIO_MODE_SPI | - RT305X_GPIO_MODE_JTAG); - - rt305x_register_flash(0); - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; - rt305x_register_ethernet(); - ramips_register_gpio_leds(-1, ARRAY_SIZE(mzkw300nh2_leds_gpio), - mzkw300nh2_leds_gpio); - ramips_register_gpio_buttons(-1, MZKW300NH2_KEYS_POLL_INTERVAL, - ARRAY_SIZE(mzkw300nh2_gpio_buttons), - mzkw300nh2_gpio_buttons); - rt305x_register_wifi(); - rt305x_register_wdt(); -} - -MIPS_MACHINE(RAMIPS_MACH_MZKW300NH2, "MZK-W300NH2", "Planex MZK-W300NH2", - mzkw300nh2_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-nbg-419n.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-nbg-419n.c deleted file mode 100644 index 856520368f..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-nbg-419n.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * ZyXEL NBG-419N board support - * - * Copyright (C) 2011 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define NBG_419N_GPIO_LED_POWER 9 -#define NBG_419N_GPIO_LED_WPS 14 - -#define NBG_419N_GPIO_BUTTON_WPS 0 /* active low */ -#define NBG_419N_GPIO_BUTTON_RESET 10 /* active low */ - -#define NBG_419N_KEYS_POLL_INTERVAL 20 -#define NBG_419N_KEYS_DEBOUNCE_INTERVAL (3 * NBG_419N_KEYS_POLL_INTERVAL) - -static struct gpio_led nbg_419n_leds_gpio[] __initdata = { - { - .name = "nbg-419n:green:power", - .gpio = NBG_419N_GPIO_LED_POWER, - .active_low = 1, - }, { - .name = "nbg-419n:green:wps", - .gpio = NBG_419N_GPIO_LED_WPS, - .active_low = 1, - } -}; - -static struct gpio_keys_button nbg_419n_gpio_buttons[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = NBG_419N_KEYS_DEBOUNCE_INTERVAL, - .gpio = NBG_419N_GPIO_BUTTON_RESET, - .active_low = 1, - }, { - .desc = "wps", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = NBG_419N_KEYS_DEBOUNCE_INTERVAL, - .gpio = NBG_419N_GPIO_BUTTON_WPS, - .active_low = 1, - } -}; - -static void __init nbg_419n_init(void) -{ - rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); - - rt305x_register_flash(0); - - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; - rt305x_register_ethernet(); - ramips_register_gpio_leds(-1, ARRAY_SIZE(nbg_419n_leds_gpio), - nbg_419n_leds_gpio); - ramips_register_gpio_buttons(-1, NBG_419N_KEYS_POLL_INTERVAL, - ARRAY_SIZE(nbg_419n_gpio_buttons), - nbg_419n_gpio_buttons); - rt305x_register_wifi(); - rt305x_register_wdt(); -} - -MIPS_MACHINE(RAMIPS_MACH_NBG_419N, "NBG-419N", "ZyXEL NBG-419N", nbg_419n_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-nw718.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-nw718.c deleted file mode 100644 index 3c9d047908..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-nw718.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Netcore NW718 board support - * - * Copyright (C) 2011 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define NW718_GPIO_LED_USB 8 -#define NW718_GPIO_LED_CPU 13 -#define NW718_GPIO_LED_WPS 14 - -#define NW718_GPIO_BUTTON_WPS 0 -#define NW718_GPIO_BUTTON_RESET 10 - -#define NW718_GPIO_SPI_CS0 3 - -#define NW718_KEYS_POLL_INTERVAL 20 -#define NW718_KEYS_DEBOUNCE_INTERVAL (3 * NW718_KEYS_POLL_INTERVAL) - -static struct gpio_led nw718_leds_gpio[] __initdata = { - { - .name = "nw718:amber:cpu", - .gpio = NW718_GPIO_LED_CPU, - .active_low = 1, - }, { - .name = "nw718:amber:usb", - .gpio = NW718_GPIO_LED_USB, - .active_low = 1, - }, { - .name = "nw718:amber:wps", - .gpio = NW718_GPIO_LED_WPS, - .active_low = 1, - } -}; - -static struct gpio_keys_button nw718_gpio_buttons[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = NW718_KEYS_DEBOUNCE_INTERVAL, - .gpio = NW718_GPIO_BUTTON_RESET, - .active_low = 1, - }, { - .desc = "wps", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = NW718_KEYS_DEBOUNCE_INTERVAL, - .gpio = NW718_GPIO_BUTTON_WPS, - .active_low = 1, - } -}; - -static struct spi_board_info nw718_spi_info[] = { - { - .bus_num = 0, - .chip_select = 0, - .max_speed_hz = 25000000, - .modalias = "m25p80", - } -}; - -static void __init nw718_init(void) -{ - rt305x_gpio_init(RT305X_GPIO_MODE_I2C | - RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); - - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; - rt305x_register_ethernet(); - ramips_register_gpio_leds(-1, ARRAY_SIZE(nw718_leds_gpio), - nw718_leds_gpio); - ramips_register_gpio_buttons(-1, NW718_KEYS_POLL_INTERVAL, - ARRAY_SIZE(nw718_gpio_buttons), - nw718_gpio_buttons); - rt305x_register_wifi(); - rt305x_register_wdt(); - rt305x_register_spi(nw718_spi_info, ARRAY_SIZE(nw718_spi_info)); - rt305x_register_usb(); -} - -MIPS_MACHINE(RAMIPS_MACH_WHR_G300N, "NW718", "Netcore NW718", nw718_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-omni-emb.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-omni-emb.c deleted file mode 100644 index 930ac3028f..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-omni-emb.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Omnima MiniEMBWiFi board support - * - * Copyright (C) 2011 Johnathan Boyce - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define OMNI_EMB_GPIO_BUTTON_RESET 12 /* active low */ - -#define OMNI_EMB_KEYS_POLL_INTERVAL 20 -#define OMNI_EMB_KEYS_DEBOUNCE_INTERVAL (3 * OMNI_EMB_KEYS_POLL_INTERVAL) - -#define OMNI_EMB_GPIO_LED_STATUS 9 -#define OMNI_EMB_GPIO_LED_WLAN 14 - -static struct gpio_led omni_emb_leds_gpio[] __initdata = { - { - .name = "emb:green:status", - .gpio = OMNI_EMB_GPIO_LED_STATUS, - .active_low = 1, - }, { - .name = "emb:green:wlan", - .gpio = OMNI_EMB_GPIO_LED_WLAN, - .active_low = 1, - } -}; - -static struct gpio_keys_button omni_emb_gpio_buttons[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = OMNI_EMB_KEYS_DEBOUNCE_INTERVAL, - .gpio = OMNI_EMB_GPIO_BUTTON_RESET, - .active_low = 1, - } -}; - -static void __init omni_emb_init(void) -{ - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; - - rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); - - ramips_register_gpio_leds(-1, ARRAY_SIZE(omni_emb_leds_gpio), - omni_emb_leds_gpio); - ramips_register_gpio_buttons(-1, OMNI_EMB_KEYS_POLL_INTERVAL, - ARRAY_SIZE(omni_emb_gpio_buttons), - omni_emb_gpio_buttons); - - rt305x_register_flash(0); - rt305x_register_ethernet(); - rt305x_register_wifi(); - rt305x_register_wdt(); - rt305x_register_usb(); -} - -MIPS_MACHINE(RAMIPS_MACH_OMNI_EMB, "OMNI-EMB", "Omnima MiniEMBWiFi", - omni_emb_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-psr-680w.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-psr-680w.c deleted file mode 100644 index a6d10f7cbe..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-psr-680w.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Petatel PSR-680W Wireless 3G Router support - * - * Copyright (C) 2012 Dmitry Shmygov - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define PSR_680W_GPIO_BUTTON_RESET 0 /* active low */ - -#define PSR_680W_GPIO_LED_STATUS 19 - -#define PSR_680W_KEYS_POLL_INTERVAL 20 -#define PSR_680W_KEYS_DEBOUNCE_INTERVAL (3 * PSR_680W_KEYS_POLL_INTERVAL) - - -static struct gpio_led psr_680w_leds_gpio[] __initdata = { - { - .name = "psr-680w:red:wan", - .gpio = PSR_680W_GPIO_LED_STATUS, - .active_low = 1, - } -}; - -static struct gpio_keys_button psr_680w_gpio_buttons[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = PSR_680W_KEYS_DEBOUNCE_INTERVAL, - .gpio = PSR_680W_GPIO_BUTTON_RESET, - .active_low = 1, - } -}; - -static void __init psr_680w_init(void) -{ - rt305x_gpio_init((RT305X_GPIO_MODE_I2S_UARTF << RT305X_GPIO_MODE_UART0_SHIFT) | - RT305X_GPIO_MODE_SPI | - RT305X_GPIO_MODE_JTAG | - RT305X_GPIO_MODE_MDIO | - RT305X_GPIO_MODE_RGMII); - - rt305x_register_flash(0); - - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL; - rt305x_register_ethernet(); - ramips_register_gpio_leds(-1, ARRAY_SIZE(psr_680w_leds_gpio), - psr_680w_leds_gpio); - ramips_register_gpio_buttons(-1, PSR_680W_KEYS_POLL_INTERVAL, - ARRAY_SIZE(psr_680w_gpio_buttons), - psr_680w_gpio_buttons); - rt305x_register_wifi(); - rt305x_register_wdt(); - rt305x_register_usb(); -} - -MIPS_MACHINE(RAMIPS_MACH_PSR_680W, "PSR-680W", - "Petatel PSR-680W Wireless 3G Router", - psr_680w_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-pwh2004.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-pwh2004.c deleted file mode 100644 index 5baf32a49a..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-pwh2004.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Prolink PWH2004 support (or Abocom WR5205) - * - * Copyright (C) 2010 Esa Hyytia - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define PWH2004_GPIO_BUTTON_WPS 12 -#define PWH2004_GPIO_LED_POWER 9 -#define PWH2004_GPIO_LED_WIFI 14 -#define PWH2004_KEYS_POLL_INTERVAL 20 -#define PWH2004_KEYS_DEBOUNCE_INTERVAL (3 * PWH2004_KEYS_POLL_INTERVAL) - -static struct gpio_led pwh2004_leds_gpio[] __initdata = { - { - .name = "pwh2004:red:wifi", - .gpio = PWH2004_GPIO_LED_WIFI, - .active_low = 1, - }, { - .name = "pwh2004:green:power", - .gpio = PWH2004_GPIO_LED_POWER, - .active_low = 1, - } -}; - -static struct gpio_keys_button pwh2004_gpio_buttons[] __initdata = { - { - .desc = "wps", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = PWH2004_KEYS_DEBOUNCE_INTERVAL, - .gpio = PWH2004_GPIO_BUTTON_WPS, - .active_low = 1, - } -}; - -static void __init pwh2004_init(void) -{ - rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); - - rt305x_register_flash(0); - - ramips_register_gpio_leds(-1, ARRAY_SIZE(pwh2004_leds_gpio), - pwh2004_leds_gpio); - ramips_register_gpio_buttons(-1, PWH2004_KEYS_POLL_INTERVAL, - ARRAY_SIZE(pwh2004_gpio_buttons), - pwh2004_gpio_buttons); - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; - rt305x_register_ethernet(); - rt305x_register_wifi(); - rt305x_register_wdt(); -} - -MIPS_MACHINE(RAMIPS_MACH_PWH2004, "PWH2004", "Prolink PWH2004", - pwh2004_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-rt-g32-revb.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-rt-g32-revb.c deleted file mode 100644 index 2f0f710874..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-rt-g32-revb.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Asus RT-G32 rev B board support - * - * Copyright (C) 2011 Sergiy - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "devices.h" - -#define RT_G32B_GPIO_BUTTON_WPS 0 /* active low */ -#define RT_G32B_GPIO_BUTTON_RESET 10 /* active low */ - -#define RT_G32B_KEYS_POLL_INTERVAL 20 -#define RT_G32B_KEYS_DEBOUNCE_INTERVAL (3 * RT_G32B_KEYS_POLL_INTERVAL) - -const struct flash_platform_data rt_g32b_flash = { - .type = "mx25l3205d", -}; - -struct spi_board_info __initdata rt_g32b_spi_slave_info[] = { - { - .modalias = "m25p80", - .platform_data = &rt_g32b_flash, - .irq = -1, - .max_speed_hz = 10000000, - .bus_num = 0, - .chip_select = 0, - }, -}; - -static struct gpio_keys_button rt_g32b_gpio_buttons[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = RT_G32B_KEYS_DEBOUNCE_INTERVAL, - .gpio = RT_G32B_GPIO_BUTTON_RESET, - .active_low = 1, - }, { - .desc = "wps", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = RT_G32B_KEYS_DEBOUNCE_INTERVAL, - .gpio = RT_G32B_GPIO_BUTTON_WPS, - .active_low = 1, - } -}; - -static void __init rt_g32b_init(void) -{ - rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); - rt305x_register_spi(rt_g32b_spi_slave_info, - ARRAY_SIZE(rt_g32b_spi_slave_info)); - - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; - rt305x_register_ethernet(); - ramips_register_gpio_buttons(-1, RT_G32B_KEYS_POLL_INTERVAL, - ARRAY_SIZE(rt_g32b_gpio_buttons), - rt_g32b_gpio_buttons); - rt305x_register_wifi(); - rt305x_register_wdt(); -} - -MIPS_MACHINE(RAMIPS_MACH_RT_G32_B1, "RT-G32-B1", "Asus RT-G32 B1", - rt_g32b_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-rt-n10-plus.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-rt-n10-plus.c deleted file mode 100644 index 5b496d4eac..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-rt-n10-plus.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * ASUS RT-N10+ board support - * - * Copyright (C) 2009-2012 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define RT_N10_PLUS_GPIO_LED_WPS 14 - -#define RT_N10_PLUS_GPIO_BUTTON_WPS 0 /* active low */ -#define RT_N10_PLUS_GPIO_BUTTON_RESET 10 /* active low */ - -#define RT_N10_PLUS_KEYS_POLL_INTERVAL 20 -#define RT_N10_PLUS_KEYS_DEBOUNCE_INTERVAL (3 * RT_N10_PLUS_KEYS_POLL_INTERVAL) - -static struct gpio_led rt_n10_plus_leds_gpio[] __initdata = { - { - .name = "asus:green:wps", - .gpio = RT_N10_PLUS_GPIO_LED_WPS, - .active_low = 1, - } -}; - -static struct gpio_keys_button rt_n10_plus_gpio_buttons[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = RT_N10_PLUS_KEYS_DEBOUNCE_INTERVAL, - .gpio = RT_N10_PLUS_GPIO_BUTTON_RESET, - .active_low = 1, - }, { - .desc = "wps", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = RT_N10_PLUS_KEYS_DEBOUNCE_INTERVAL, - .gpio = RT_N10_PLUS_GPIO_BUTTON_WPS, - .active_low = 1, - } -}; - -static void __init rt_n10_plus_init(void) -{ - rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); - - rt305x_register_flash(0); - - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL; - rt305x_register_ethernet(); - ramips_register_gpio_leds(-1, ARRAY_SIZE(rt_n10_plus_leds_gpio), - rt_n10_plus_leds_gpio); - ramips_register_gpio_buttons(-1, RT_N10_PLUS_KEYS_POLL_INTERVAL, - ARRAY_SIZE(rt_n10_plus_gpio_buttons), - rt_n10_plus_gpio_buttons); - rt305x_register_wifi(); - rt305x_register_wdt(); -} - -MIPS_MACHINE(RAMIPS_MACH_RT_N10_PLUS, "RT-N10-PLUS", "Asus RT-N10+", - rt_n10_plus_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-rt-n13u.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-rt-n13u.c deleted file mode 100644 index cae857abd4..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-rt-n13u.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * ASUS RT-N13U board support - * - * Copyright (C) 2012 lintel - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define RT_N13U_GPIO_BUTTON_RESET 10 -#define RT_N13U_GPIO_BUTTON_WPS 0 - -#define RT_N13U_GPIO_LED_POWER 7 -#define RT_N13U_GPIO_LED_WIFI 8 - - -#define RT_N13U_BUTTONS_POLL_INTERVAL 10 -#define RT_N13U_BUTTONS_DEBOUNCE_INTERVAL (3 * RT_N13U_BUTTONS_POLL_INTERVAL) - -static struct gpio_led rt_n13u_leds_gpio[] __initdata = { - { - .name = "rt-n13u:power", - .gpio = RT_N13U_GPIO_LED_POWER, - .active_low = 1, - }, { - .name = "rt-n13u:wifi", - .gpio = RT_N13U_GPIO_LED_WIFI, - .active_low = 1, - } -}; - -static struct gpio_keys_button rt_n13u_gpio_buttons[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = RT_N13U_BUTTONS_DEBOUNCE_INTERVAL, - .gpio = RT_N13U_GPIO_BUTTON_RESET, - .active_low = 1, - }, { - .desc = "wps", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = RT_N13U_BUTTONS_DEBOUNCE_INTERVAL, - .gpio = RT_N13U_GPIO_BUTTON_WPS, - .active_low = 1, - }, -}; - -static void __init rt_n13u_init(void) -{ - rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); - - rt305x_register_flash(0); - - ramips_register_gpio_leds(-1, ARRAY_SIZE(rt_n13u_leds_gpio), - rt_n13u_leds_gpio); - - ramips_register_gpio_buttons(-1, RT_N13U_BUTTONS_POLL_INTERVAL, - ARRAY_SIZE(rt_n13u_gpio_buttons), - rt_n13u_gpio_buttons); - - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; - rt305x_register_ethernet(); - rt305x_register_wifi(); - rt305x_register_wdt(); - rt305x_register_usb(); -} - -MIPS_MACHINE(RAMIPS_MACH_RT_N13U, "RT-N13U", "Asus RT-N13U", - rt_n13u_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-sl-r7205.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-sl-r7205.c deleted file mode 100644 index 31f002c9aa..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-sl-r7205.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Skyline SL-R7205 Wireless 3G Router support - * - * Copyright (C) 2012 Haipoh Teoh - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define SL_R7205_GPIO_BUTTON_WPS 0 -#define SL_R7205_GPIO_BUTTON_RESET 10 /* active low */ - -#define SL_R7205_GPIO_LED_WIFI 7 - -#define SL_R7205_KEYS_POLL_INTERVAL 20 -#define SL_R7205_KEYS_DEBOUNCE_INTERVAL (3 * SL_R7205_KEYS_POLL_INTERVAL) - -static struct gpio_led sl_r7205_leds_gpio[] __initdata = { - { - .name = "sl-r7205:green:wifi", - .gpio = SL_R7205_GPIO_LED_WIFI, - .active_low = 1, - } -}; - -static struct gpio_keys_button sl_r7205_gpio_buttons[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = SL_R7205_KEYS_DEBOUNCE_INTERVAL, - .gpio = SL_R7205_GPIO_BUTTON_RESET, - .active_low = 1, - }, { - .desc = "wps", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = SL_R7205_KEYS_DEBOUNCE_INTERVAL, - .gpio = SL_R7205_GPIO_BUTTON_WPS, - .active_low = 1, - } -}; - -static void __init sl_r7205_init(void) -{ - rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); - - rt305x_register_flash(0); - - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL; - rt305x_register_ethernet(); - ramips_register_gpio_leds(-1, ARRAY_SIZE(sl_r7205_leds_gpio), - sl_r7205_leds_gpio); - ramips_register_gpio_buttons(-1, SL_R7205_KEYS_POLL_INTERVAL, - ARRAY_SIZE(sl_r7205_gpio_buttons), - sl_r7205_gpio_buttons); - rt305x_register_wifi(); - rt305x_register_wdt(); - rt305x_register_usb(); -} - -MIPS_MACHINE(RAMIPS_MACH_SL_R7205, "SL-R7205", - "Skyline SL-R7205 Wireless 3G Router", - sl_r7205_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-ur-326n4g.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-ur-326n4g.c deleted file mode 100644 index a5296941a1..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-ur-326n4g.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * UR-326N4G board support - * - * Copyright (C) 2013 Dmitry Lebedev - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - - -#define UR_326N4G_GPIO_LED_3G 9 -#define UR_326N4G_GPIO_LED_GATEWAY 11 -#define UR_326N4G_GPIO_LED_AP 12 -#define UR_326N4G_GPIO_LED_STATION 13 -#define UR_326N4G_GPIO_LED_WPS 14 - -#define UR_326N4G_GPIO_BUTTON_RESET 10 -#define UR_326N4G_GPIO_BUTTON_CONNECT 7 -#define UR_326N4G_GPIO_BUTTON_WPS 0 -#define UR_326N4G_GPIO_BUTTON_WPS2 8 - -#define UR_326N4G_KEYS_POLL_INTERVAL 20 -#define UR_326N4G_KEYS_DEBOUNCE_INTERVAL (3 * UR_326N4G_KEYS_POLL_INTERVAL) - -static struct gpio_led UR_326N4G_leds_gpio[] __initdata = { - { - .name = "ur326:green:3g", - .gpio = UR_326N4G_GPIO_LED_3G, - .active_low = 1, - }, { - .name = "ur326:green:gateway", - .gpio = UR_326N4G_GPIO_LED_GATEWAY, - .active_low = 1, - }, { - .name = "ur326:green:ap", - .gpio = UR_326N4G_GPIO_LED_AP, - .active_low = 1, - }, { - .name = "ur326:green:wps", - .gpio = UR_326N4G_GPIO_LED_WPS, - .active_low = 1, - }, { - .name = "ur326:green:station", - .gpio = UR_326N4G_GPIO_LED_STATION, - .active_low = 1, - } -}; - -static struct gpio_keys_button UR_326N4G_gpio_buttons[] __initdata = { - { - .desc = "reset_wps", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = UR_326N4G_KEYS_DEBOUNCE_INTERVAL, - .gpio = UR_326N4G_GPIO_BUTTON_RESET, - .active_low = 1, - }, { - .desc = "mode", - .type = EV_KEY, - .code = KEY_M, - .debounce_interval = UR_326N4G_KEYS_DEBOUNCE_INTERVAL, - .gpio = UR_326N4G_GPIO_BUTTON_CONNECT, - .active_low = 1, - } -}; - -#define UR_326N4G_GPIO_MODE \ - ((RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT) | \ - RT305X_GPIO_MODE_MDIO) - -static void __init UR_326N4G_init(void) -{ - rt305x_gpio_init(UR_326N4G_GPIO_MODE); - - rt305x_register_flash(0); - - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; - rt305x_register_ethernet(); - ramips_register_gpio_leds(-1, ARRAY_SIZE(UR_326N4G_leds_gpio), - UR_326N4G_leds_gpio); - ramips_register_gpio_buttons(-1, UR_326N4G_KEYS_POLL_INTERVAL, - ARRAY_SIZE(UR_326N4G_gpio_buttons), - UR_326N4G_gpio_buttons); - rt305x_register_wifi(); - rt305x_register_wdt(); - rt305x_register_usb(); -} - -MIPS_MACHINE(RAMIPS_MACH_UR_326N4G, "UR-326N4G", "UR-326N4G Wireless N router", - UR_326N4G_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-ur-336un.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-ur-336un.c deleted file mode 100644 index 0ff264957a..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-ur-336un.c +++ /dev/null @@ -1,92 +0,0 @@ -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - - -#define UR_336UN_GPIO_LED_3G 9 -#define UR_336UN_GPIO_LED_GATEWAY 11 -#define UR_336UN_GPIO_LED_AP 12 -#define UR_336UN_GPIO_LED_STATION 13 -#define UR_336UN_GPIO_LED_WPS 14 - -#define UR_336UN_GPIO_BUTTON_RESET 10 -#define UR_336UN_GPIO_BUTTON_CONNECT 7 -#define UR_336UN_GPIO_BUTTON_WPS 0 -#define UR_336UN_GPIO_BUTTON_WPS2 8 - -#define UR_336UN_KEYS_POLL_INTERVAL 20 -#define UR_336UN_KEYS_DEBOUNCE_INTERVAL (3 * UR_336UN_KEYS_POLL_INTERVAL) - -static struct gpio_led UR_336UN_leds_gpio[] __initdata = { - { - .name = "ur336:green:3g", - .gpio = UR_336UN_GPIO_LED_3G, - .active_low = 1, - }, { - .name = "ur336:green:gateway", - .gpio = UR_336UN_GPIO_LED_GATEWAY, - .active_low = 1, - }, { - .name = "ur336:green:ap", - .gpio = UR_336UN_GPIO_LED_AP, - .active_low = 1, - }, { - .name = "ur336:green:wps", - .gpio = UR_336UN_GPIO_LED_WPS, - .active_low = 1, - }, { - .name = "ur336:green:station", - .gpio = UR_336UN_GPIO_LED_STATION, - .active_low = 1, - } -}; - -static struct gpio_keys_button UR_336UN_gpio_buttons[] __initdata = { - { - .desc = "reset_wps", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = UR_336UN_KEYS_DEBOUNCE_INTERVAL, - .gpio = UR_336UN_GPIO_BUTTON_RESET, - .active_low = 1, - }, { - .desc = "mode", - .type = EV_KEY, - .code = KEY_M, - .debounce_interval = UR_336UN_KEYS_DEBOUNCE_INTERVAL, - .gpio = UR_336UN_GPIO_BUTTON_CONNECT, - .active_low = 1, - } -}; - -#define UR_336UN_GPIO_MODE \ - ((RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT) | \ - RT305X_GPIO_MODE_MDIO) - -static void __init UR_336UN_init(void) -{ - rt305x_gpio_init(UR_336UN_GPIO_MODE); - - rt305x_register_flash(0); - - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; - rt305x_register_ethernet(); - ramips_register_gpio_leds(-1, ARRAY_SIZE(UR_336UN_leds_gpio), - UR_336UN_leds_gpio); - ramips_register_gpio_buttons(-1, UR_336UN_KEYS_POLL_INTERVAL, - ARRAY_SIZE(UR_336UN_gpio_buttons), - UR_336UN_gpio_buttons); - rt305x_register_wifi(); - rt305x_register_wdt(); - rt305x_register_usb(); -} - -MIPS_MACHINE(RAMIPS_MACH_UR_336UN, "UR-336UN", "UR-336UN Wireless N router", - UR_336UN_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-v22rw-2x2.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-v22rw-2x2.c deleted file mode 100644 index 7f43dabdc4..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-v22rw-2x2.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Ralink AP-RT3052-V22RW-2X2 board support - * - * Copyright (C) 2009-2010 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define V22RW_2X2_GPIO_BUTTON_WPS 0 -#define V22RW_2X2_GPIO_BUTTON_SWRST 10 -#define V22RW_2X2_GPIO_LED_SECURITY 13 -#define V22RW_2X2_GPIO_LED_WPS 14 - -#define V22RW_2X2_KEYS_POLL_INTERVAL 20 -#define V22RW_2X2_KEYS_DEBOUNCE_INTERVAL (3 * V22RW_2X2_KEYS_POLL_INTERVAL) - -static struct gpio_led v22rw_2x2_leds_gpio[] __initdata = { - { - .name = "v22rw-2x2:green:security", - .gpio = V22RW_2X2_GPIO_LED_SECURITY, - .active_low = 1, - }, { - .name = "v22rw-2x2:red:wps", - .gpio = V22RW_2X2_GPIO_LED_WPS, - .active_low = 1, - } -}; - -static struct gpio_keys_button v22rw_2x2_gpio_buttons[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = V22RW_2X2_KEYS_DEBOUNCE_INTERVAL, - .gpio = V22RW_2X2_GPIO_BUTTON_SWRST, - .active_low = 1, - }, { - .desc = "wps", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = V22RW_2X2_KEYS_DEBOUNCE_INTERVAL, - .gpio = V22RW_2X2_GPIO_BUTTON_WPS, - .active_low = 1, - } -}; - -static void __init v22rw_2x2_init(void) -{ - rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); - - rt305x_register_flash(0); - - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; - rt305x_register_ethernet(); - ramips_register_gpio_leds(-1, ARRAY_SIZE(v22rw_2x2_leds_gpio), - v22rw_2x2_leds_gpio); - ramips_register_gpio_buttons(-1, V22RW_2X2_KEYS_POLL_INTERVAL, - ARRAY_SIZE(v22rw_2x2_gpio_buttons), - v22rw_2x2_gpio_buttons); - rt305x_register_wifi(); - rt305x_register_wdt(); - rt305x_register_usb(); -} - -MIPS_MACHINE(RAMIPS_MACH_V22RW_2X2, "V22RW-2X2", "Ralink AP-RT3052-V22RW-2X2", - v22rw_2x2_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-w306r-v20.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-w306r-v20.c deleted file mode 100644 index 7c8eb867cd..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-w306r-v20.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Tenda W306R V2.0 board support - * - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "devices.h" - -#define W306R_V20_GPIO_LED_SYS 9 -#define W306R_V20_GPIO_LED_WPS 13 - -#define W306R_V20_GPIO_BUTTON_RESET 10 - -#define W306R_V20_KEYS_POLL_INTERVAL 20 -#define W306R_V20_KEYS_DEBOUNCE_INTERVAL (3 * W306R_V20_KEYS_POLL_INTERVAL) - -static struct gpio_led w306r_v20_leds_gpio[] __initdata = { - { - .name = "w306r-v20:green:sys", - .gpio = W306R_V20_GPIO_LED_SYS, - .active_low = 1, - }, { - .name = "w306r-v20:green:wps", - .gpio = W306R_V20_GPIO_LED_WPS, - .active_low = 1, - } -}; - -static struct gpio_keys_button w306r_v20_gpio_buttons[] __initdata = { - { - .desc = "RESET/WPS", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = W306R_V20_KEYS_DEBOUNCE_INTERVAL, - .gpio = W306R_V20_GPIO_BUTTON_RESET, - .active_low = 1, - } -}; - -static void __init w306r_v20_init(void) -{ - rt305x_register_flash(0); - - rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); - - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL; - rt305x_register_ethernet(); - ramips_register_gpio_leds(-1, ARRAY_SIZE(w306r_v20_leds_gpio), - w306r_v20_leds_gpio); - ramips_register_gpio_buttons(-1, W306R_V20_KEYS_POLL_INTERVAL, - ARRAY_SIZE(w306r_v20_gpio_buttons), - w306r_v20_gpio_buttons); - rt305x_register_wifi(); - rt305x_register_wdt(); -} - -MIPS_MACHINE(RAMIPS_MACH_W306R_V20, "W306R_V20", "Tenda W306R V2.0", - w306r_v20_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-w502u.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-w502u.c deleted file mode 100644 index 6633ca0288..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-w502u.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * ALFA Networks W502U board support - * - * Copyright (C) 2011 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define W502U_GPIO_LED_USB 13 -#define W502U_GPIO_LED_WPS 14 - -#define W502U_GPIO_BUTTON_WPS 0 -#define W502U_GPIO_BUTTON_RESET 10 - -#define W502U_KEYS_POLL_INTERVAL 20 -#define W502U_KEYS_DEBOUNCE_INTERVAL (3 * W502U_KEYS_POLL_INTERVAL) - -static struct gpio_led w502u_leds_gpio[] __initdata = { - { - .name = "alfa:blue:usb", - .gpio = W502U_GPIO_LED_USB, - .active_low = 1, - }, - { - .name = "alfa:blue:wps", - .gpio = W502U_GPIO_LED_WPS, - .active_low = 1, - }, -}; - -static struct gpio_keys_button w502u_gpio_buttons[] __initdata = { - { - .desc = "Reset button", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = W502U_KEYS_DEBOUNCE_INTERVAL, - .gpio = W502U_GPIO_BUTTON_RESET, - .active_low = 1, - }, - { - .desc = "WPS button", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = W502U_KEYS_DEBOUNCE_INTERVAL, - .gpio = W502U_GPIO_BUTTON_WPS, - .active_low = 1, - }, -}; - -static void __init w502u_init(void) -{ - rt305x_gpio_init((RT305X_GPIO_MODE_GPIO << - RT305X_GPIO_MODE_UART0_SHIFT)); - - rt305x_register_flash(0); - - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL; - rt305x_register_ethernet(); - ramips_register_gpio_leds(-1, ARRAY_SIZE(w502u_leds_gpio), - w502u_leds_gpio); - ramips_register_gpio_buttons(-1, W502U_KEYS_POLL_INTERVAL, - ARRAY_SIZE(w502u_gpio_buttons), - w502u_gpio_buttons); - rt305x_register_wifi(); - rt305x_register_wdt(); - rt305x_register_usb(); -} - -MIPS_MACHINE(RAMIPS_MACH_W502U, "W502U", "ALFA Networks W502U", - w502u_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-wcr150gn.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-wcr150gn.c deleted file mode 100644 index dec1a7bb5b..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-wcr150gn.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Sparklan WCR-150GN board support - * - * Copyright (C) 2010 Roman Yeryomin - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define WCR150GN_GPIO_LED_USER 12 -#define WCR150GN_GPIO_LED_POWER 8 -#define WCR150GN_GPIO_BUTTON_WPS 10 -#define WCR150GN_GPIO_BUTTON_RESET 0 -#define WCR150GN_KEYS_POLL_INTERVAL 20 -#define WCR150GN_KEYS_DEBOUNCE_INTERVAL (3 * WCR150GN_KEYS_POLL_INTERVAL) - -static struct gpio_led wcr150gn_leds_gpio[] __initdata = { - { - .name = "wcr150gn:amber:user", - .gpio = WCR150GN_GPIO_LED_USER, - .active_low = 1, - }, - { - .name = "wcr150gn:amber:power", - .gpio = WCR150GN_GPIO_LED_POWER, - .active_low = 1, - } -}; - -static struct gpio_keys_button wcr150gn_gpio_buttons[] __initdata = { - { - .desc = "wps", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = WCR150GN_KEYS_DEBOUNCE_INTERVAL, - .gpio = WCR150GN_GPIO_BUTTON_WPS, - .active_low = 1, - }, - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = WCR150GN_KEYS_DEBOUNCE_INTERVAL, - .gpio = WCR150GN_GPIO_BUTTON_RESET, - .active_low = 1, - } -}; - -static void __init wcr150gn_init(void) -{ - rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); - - rt305x_register_flash(0); - - ramips_register_gpio_leds(-1, ARRAY_SIZE(wcr150gn_leds_gpio), - wcr150gn_leds_gpio); - ramips_register_gpio_buttons(-1, WCR150GN_KEYS_POLL_INTERVAL, - ARRAY_SIZE(wcr150gn_gpio_buttons), - wcr150gn_gpio_buttons); - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; - rt305x_register_ethernet(); - rt305x_register_wifi(); - rt305x_register_wdt(); - rt305x_register_usb(); -} - -MIPS_MACHINE(RAMIPS_MACH_WCR150GN, "WCR150GN", "Sparklan WCR-150GN", - wcr150gn_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-whr-g300n.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-whr-g300n.c deleted file mode 100644 index e5adb1909f..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-whr-g300n.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Buffalo WHR-G300N board support - * - * Copyright (C) 2009-2010 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define WHR_G300N_GPIO_LED_DIAG 7 -#define WHR_G300N_GPIO_LED_ROUTER 9 -#define WHR_G300N_GPIO_LED_SECURITY 14 - -#define WHR_G300N_GPIO_BUTTON_AOSS 0 /* active low */ -#define WHR_G300N_GPIO_BUTTON_RESET 10 /* active low */ -#define WHR_G300N_GPIO_BUTTON_ROUTER_ON 8 /* active low */ -#define WHR_G300N_GPIO_BUTTON_ROUTER_OFF 11 /* active low */ - -#define WHR_G300N_KEYS_POLL_INTERVAL 20 -#define WHR_G300N_KEYS_DEBOUNCE_INTERVAL (3 * WHR_G300N_KEYS_POLL_INTERVAL) - -static struct gpio_led whr_g300n_leds_gpio[] __initdata = { - { - .name = "whr-g300n:red:diag", - .gpio = WHR_G300N_GPIO_LED_DIAG, - .active_low = 1, - }, { - .name = "whr-g300n:green:router", - .gpio = WHR_G300N_GPIO_LED_ROUTER, - .active_low = 1, - }, { - .name = "whr-g300n:amber:security", - .gpio = WHR_G300N_GPIO_LED_SECURITY, - .active_low = 1, - } -}; - -static struct gpio_keys_button whr_g300n_gpio_buttons[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = WHR_G300N_KEYS_DEBOUNCE_INTERVAL, - .gpio = WHR_G300N_GPIO_BUTTON_RESET, - .active_low = 1, - }, { - .desc = "aoss", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = WHR_G300N_KEYS_DEBOUNCE_INTERVAL, - .gpio = WHR_G300N_GPIO_BUTTON_AOSS, - .active_low = 1, - }, { - .desc = "router-off", - .type = EV_KEY, - .code = BTN_2, - .debounce_interval = WHR_G300N_KEYS_DEBOUNCE_INTERVAL, - .gpio = WHR_G300N_GPIO_BUTTON_ROUTER_OFF, - .active_low = 1, - }, { - .desc = "router-on", - .type = EV_KEY, - .code = BTN_3, - .debounce_interval = WHR_G300N_KEYS_DEBOUNCE_INTERVAL, - .gpio = WHR_G300N_GPIO_BUTTON_ROUTER_ON, - .active_low = 1, - } -}; - -static void __init whr_g300n_init(void) -{ - rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); - - rt305x_register_flash(0); - - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; - rt305x_register_ethernet(); - ramips_register_gpio_leds(-1, ARRAY_SIZE(whr_g300n_leds_gpio), - whr_g300n_leds_gpio); - ramips_register_gpio_buttons(-1, WHR_G300N_KEYS_POLL_INTERVAL, - ARRAY_SIZE(whr_g300n_gpio_buttons), - whr_g300n_gpio_buttons); - rt305x_register_wifi(); - rt305x_register_wdt(); -} - -MIPS_MACHINE(RAMIPS_MACH_WHR_G300N, "WHR-G300N", "Buffalo WHR-G300N", - whr_g300n_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-wl-330n.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-wl-330n.c deleted file mode 100644 index b548dfee1d..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-wl-330n.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Asus WL_330N board support - * - * Copyright (C) 2012 Frederic Leroy - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define WL_330N_GPIO_BUTTON_RESET 10 -#define WL_330N_GPIO_BUTTON_WPS 0 -#define WL_330N_GPIO_LED_LINK 9 -#define WL_330N_GPIO_LED_POWER 11 -#define WL_330N_KEYS_POLL_INTERVAL 20 -#define WL_330N_KEYS_DEBOUNCE_INTERVAL (3 * WL_330N_KEYS_POLL_INTERVAL) - -const struct flash_platform_data wl_330n_flash = { - .type = "mx25l3205d", -}; - -struct spi_board_info wl_330n_spi_slave_info[] __initdata = { - { - .modalias = "m25p80", - .platform_data = &wl_330n_flash, - .irq = -1, - .max_speed_hz = 10000000, - .bus_num = 0, - .chip_select = 0, - }, -}; - -static struct gpio_keys_button wl_330n_gpio_buttons[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = WL_330N_KEYS_DEBOUNCE_INTERVAL, - .gpio = WL_330N_GPIO_BUTTON_RESET, - .active_low = 1, - }, - { - .desc = "wps", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = WL_330N_KEYS_DEBOUNCE_INTERVAL, - .gpio = WL_330N_GPIO_BUTTON_WPS, - .active_low = 1, - } -}; - -static struct gpio_led wl_330n_leds_gpio[] __initdata = { - { - .name = "asus:blue:link", - .gpio = WL_330N_GPIO_LED_LINK, - .active_low = 1, - }, { - .name = "asus:blue:power", - .gpio = WL_330N_GPIO_LED_POWER, - .active_low = 1, - } -}; - -static void __init wl_330n_init(void) -{ - rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); - rt305x_register_spi(wl_330n_spi_slave_info, - ARRAY_SIZE(wl_330n_spi_slave_info)); - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL; - rt305x_register_ethernet(); - ramips_register_gpio_leds(-1, ARRAY_SIZE(wl_330n_leds_gpio), - wl_330n_leds_gpio); - ramips_register_gpio_buttons(-1, WL_330N_KEYS_POLL_INTERVAL, - ARRAY_SIZE(wl_330n_gpio_buttons), - wl_330n_gpio_buttons); - rt305x_register_wifi(); - rt305x_register_wdt(); -} - -MIPS_MACHINE(RAMIPS_MACH_WL_330N, "WL_330N", "Asus WL-330N", - wl_330n_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-wl-330n3g.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-wl-330n3g.c deleted file mode 100644 index 599b9a9adb..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-wl-330n3g.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Asus WL_330N3G board support - * - * Copyright (C) 2012 Frederic Leroy - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define WL_330N3G_GPIO_BUTTON_RESET 10 -#define WL_330N3G_GPIO_BUTTON_WPS 0 -#define WL_330N3G_GPIO_LED_3G_BLUE 9 -#define WL_330N3G_GPIO_LED_3G_RED 13 -#define WL_330N3G_GPIO_LED_POWER 11 -#define WL_330N3G_KEYS_POLL_INTERVAL 20 -#define WL_330N3G_KEYS_DEBOUNCE_INTERVAL (3 * WL_330N3G_KEYS_POLL_INTERVAL) - -const struct flash_platform_data wl_330n3g_flash = { - .type = "mx25l3205d", -}; - -struct spi_board_info wl_330n3g_spi_slave_info[] __initdata = { - { - .modalias = "m25p80", - .platform_data = &wl_330n3g_flash, - .irq = -1, - .max_speed_hz = 10000000, - .bus_num = 0, - .chip_select = 0, - }, -}; - -static struct gpio_keys_button wl_330n3g_gpio_buttons[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = WL_330N3G_KEYS_DEBOUNCE_INTERVAL, - .gpio = WL_330N3G_GPIO_BUTTON_RESET, - .active_low = 1, - }, - { - .desc = "wps", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = WL_330N3G_KEYS_DEBOUNCE_INTERVAL, - .gpio = WL_330N3G_GPIO_BUTTON_WPS, - .active_low = 1, - } -}; - -static struct gpio_led wl_330n3g_leds_gpio[] __initdata = { - { - .name = "asus:blue:3g", - .gpio = WL_330N3G_GPIO_LED_3G_BLUE, - .active_low = 1, - }, { - .name = "asus:red:3g", - .gpio = WL_330N3G_GPIO_LED_3G_RED, - .active_low = 1, - }, { - .name = "asus:blue:power", - .gpio = WL_330N3G_GPIO_LED_POWER, - .active_low = 1, - } -}; - -static void __init wl_330n3g_init(void) -{ - rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); - rt305x_register_spi(wl_330n3g_spi_slave_info, - ARRAY_SIZE(wl_330n3g_spi_slave_info)); - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL; - rt305x_register_ethernet(); - ramips_register_gpio_leds(-1, ARRAY_SIZE(wl_330n3g_leds_gpio), - wl_330n3g_leds_gpio); - ramips_register_gpio_buttons(-1, WL_330N3G_KEYS_POLL_INTERVAL, - ARRAY_SIZE(wl_330n3g_gpio_buttons), - wl_330n3g_gpio_buttons); - rt305x_register_wifi(); - rt305x_register_usb(); - rt305x_register_wdt(); -} - -MIPS_MACHINE(RAMIPS_MACH_WL_330N3G, "WL_330N3G", "Asus WL-330N3G", - wl_330n3g_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-wl341v3.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-wl341v3.c deleted file mode 100644 index 2cd1d5e47a..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-wl341v3.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Sitecom WL341v3 board support - * - * Copyright (C) 2012 Marco Antonio Mauro - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define WL341V3_GPIO_LED_FIRST_AMBER 9 -#define WL341V3_GPIO_LED_FIRST_BLUE 13 -#define WL341V3_GPIO_LED_THIRD_AMBER 11 -#define WL341V3_GPIO_LED_THIRD_BLUE 14 -#define WL341V3_GPIO_LED_FOURTH_BLUE 10 -#define WL341V3_GPIO_LED_FIFTH_AMBER 12 -#define WL341V3_GPIO_LED_FIFTH_BLUE 8 - -#define WL341V3_GPIO_BUTTON_WPS 5 /* active low */ -#define WL341V3_GPIO_BUTTON_RESET 7 /* active low */ - -#define WL341V3_KEYS_POLL_INTERVAL 20 -#define WL341V3_KEYS_DEBOUNCE_INTERVAL (3 * WL341V3_KEYS_POLL_INTERVAL) - -static struct gpio_led wl341v3_leds_gpio[] __initdata = { - { - .name = "wl341v3:amber:first", - .gpio = WL341V3_GPIO_LED_FIRST_AMBER, - .active_low = 1, - }, { - .name = "wl341v3:blue:first", - .gpio = WL341V3_GPIO_LED_FIRST_BLUE, - .active_low = 1, - }, { - .name = "wl341v3:amber:third", - .gpio = WL341V3_GPIO_LED_THIRD_AMBER, - .active_low = 1, - }, { - .name = "wl341v3:blue:third", - .gpio = WL341V3_GPIO_LED_THIRD_BLUE, - .active_low = 1, - }, { - .name = "wl341v3:blue:fourth", - .gpio = WL341V3_GPIO_LED_FOURTH_BLUE, - .active_low = 1, - }, { - .name = "wl341v3:amber:fifth", - .gpio = WL341V3_GPIO_LED_FIFTH_AMBER, - .active_low = 1, - }, { - .name = "wl341v3:blue:fifth", - .gpio = WL341V3_GPIO_LED_FIFTH_BLUE, - .active_low = 1, - } -}; - -static struct gpio_keys_button wl341v3_gpio_buttons[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = WL341V3_KEYS_DEBOUNCE_INTERVAL, - .gpio = WL341V3_GPIO_BUTTON_RESET, - .active_low = 1, - }, { - .desc = "wps", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = WL341V3_KEYS_DEBOUNCE_INTERVAL, - .gpio = WL341V3_GPIO_BUTTON_WPS, - .active_low = 1, - } -}; - -static void __init wl341v3_init(void) -{ - rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); - - rt305x_register_flash(0); - - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL; - rt305x_register_ethernet(); - ramips_register_gpio_leds(-1, ARRAY_SIZE(wl341v3_leds_gpio), - wl341v3_leds_gpio); - ramips_register_gpio_buttons(-1, WL341V3_KEYS_POLL_INTERVAL, - ARRAY_SIZE(wl341v3_gpio_buttons), - wl341v3_gpio_buttons); - rt305x_register_wifi(); - rt305x_register_wdt(); - rt305x_register_usb(); -} - -MIPS_MACHINE(RAMIPS_MACH_WL341V3, "WL341V3", "Sitecom WL-341 v3", - wl341v3_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-wl351.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-wl351.c deleted file mode 100644 index 8c0caadb1a..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-wl351.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Sitecom WL-351 v1 002 board support - * - * Copyright (C) 2011 Tobias Diedrich - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define WL351_GPIO_LED_POWER_AMBER 8 -#define WL351_GPIO_LED_UNPOPULATED_AMBER 12 -#define WL351_GPIO_LED_UNPOPULATED_BLUE 13 - -#define WL351_GPIO_BUTTON_RESET 10 -#define WL351_GPIO_BUTTON_WPS 0 - -#define WL351_KEYS_POLL_INTERVAL 20 -#define WL351_KEYS_DEBOUNCE_INTERVAL (3 * WL351_KEYS_POLL_INTERVAL) - -static struct gpio_led wl351_leds_gpio[] __initdata = { - { - .name = "wl-351:amber:power", - .gpio = WL351_GPIO_LED_POWER_AMBER, - .active_low = 1, - }, { - .name = "wl-351:amber:unpopulated", - .gpio = WL351_GPIO_LED_UNPOPULATED_AMBER, - .active_low = 1, - }, { - .name = "wl-351:blue:unpopulated", - .gpio = WL351_GPIO_LED_UNPOPULATED_BLUE, - .active_low = 1, - } -}; - - -static struct gpio_keys_button wl351_gpio_buttons[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = WL351_KEYS_DEBOUNCE_INTERVAL, - .gpio = WL351_GPIO_BUTTON_RESET, - .active_low = 1, - }, { - .desc = "wps", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = WL351_KEYS_DEBOUNCE_INTERVAL, - .gpio = WL351_GPIO_BUTTON_WPS, - .active_low = 1, - } -}; - -static struct rtl8366_platform_data wl351_switch_data = { - .gpio_sda = RT305X_GPIO_I2C_SD, - .gpio_sck = RT305X_GPIO_I2C_SCLK, -}; - -static struct platform_device wl351_switch = { - .name = RTL8366RB_DRIVER_NAME, - .id = -1, - .dev = { - .platform_data = &wl351_switch_data, - } -}; - -static void __init wl351_init(void) -{ - rt305x_gpio_init((RT305X_GPIO_MODE_GPIO << - RT305X_GPIO_MODE_UART0_SHIFT) | - RT305X_GPIO_MODE_I2C | - RT305X_GPIO_MODE_SPI | - RT305X_GPIO_MODE_MDIO); - - rt305x_register_flash(0); - - ramips_register_gpio_leds(-1, ARRAY_SIZE(wl351_leds_gpio), - wl351_leds_gpio); - ramips_register_gpio_buttons(-1, WL351_KEYS_POLL_INTERVAL, - ARRAY_SIZE(wl351_gpio_buttons), - wl351_gpio_buttons); - /* External RTL8366RB. */ - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_NONE; - rt305x_esw_data.reg_initval_fct2 = 0x0002500c; - /* - * ext phy base addr 31, rx/tx clock skew 0, - * turbo mii off, rgmi 3.3v off, port 5 polling off - * port5: enabled, gige, full-duplex, rx/tx-flow-control - * port6: enabled, gige, full-duplex, rx/tx-flow-control - */ - rt305x_esw_data.reg_initval_fpa2 = 0x1f003fff; - rt305x_register_ethernet(); - platform_device_register(&wl351_switch); - rt305x_register_wifi(); - rt305x_register_wdt(); - rt305x_register_usb(); -} - -MIPS_MACHINE(RAMIPS_MACH_WL351, "WL-351", "Sitecom WL-351 v1 002", - wl351_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-wr512-3gn.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-wr512-3gn.c deleted file mode 100644 index eed752353d..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-wr512-3gn.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Unbranded router from DX board support - * Also known as *WR512*-3GN by local vendors - * e.g. WS-WR512N1, Sin Hon SH-WR512NU, and etc - * (http://www.dealextreme.com/p/portable-wireless-n-3g-router-cdma2000-evdo-td-scdma-hspa-wcdma-45639) - * This router is also known to be rebranded and sold by a number of local - * vendors in several countries. - * - * Copyright (C) 2011 Andrew Andrianov - * Based on MOFI3500-3N code by - * Copyright (C) 2011 Layne Edwards - * - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - - -#define WR512_3GN_GPIO_LED_3G 9 -#define WR512_3GN_GPIO_LED_GATEWAY 11 -#define WR512_3GN_GPIO_LED_AP 12 -#define WR512_3GN_GPIO_LED_STATION 13 -#define WR512_3GN_GPIO_LED_WPS 14 - -#define WR512_3GN_GPIO_BUTTON_RESET 10 -#define WR512_3GN_GPIO_BUTTON_CONNECT 7 -#define WR512_3GN_GPIO_BUTTON_WPS 0 -#define WR512_3GN_GPIO_BUTTON_WPS2 8 - -#define WR512_3GN_KEYS_POLL_INTERVAL 20 -#define WR512_3GN_KEYS_DEBOUNCE_INTERVAL (3 * WR512_3GN_KEYS_POLL_INTERVAL) - -static struct gpio_led wr512_3gn_leds_gpio[] __initdata = { - { - .name = "wr512:green:3g", - .gpio = WR512_3GN_GPIO_LED_3G, - .active_low = 1, - }, { - .name = "wr512:green:gateway", - .gpio = WR512_3GN_GPIO_LED_GATEWAY, - .active_low = 1, - }, { - .name = "wr512:green:ap", - .gpio = WR512_3GN_GPIO_LED_AP, - .active_low = 1, - }, { - .name = "wr512:green:wps", - .gpio = WR512_3GN_GPIO_LED_WPS, - .active_low = 1, - }, { - .name = "wr512:green:station", - .gpio = WR512_3GN_GPIO_LED_STATION, - .active_low = 1, - } -}; - -static struct gpio_keys_button wr512_3gn_gpio_buttons[] __initdata = { - { - .desc = "reset_wps", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = WR512_3GN_KEYS_DEBOUNCE_INTERVAL, - .gpio = WR512_3GN_GPIO_BUTTON_RESET, - .active_low = 1, - }, { - .desc = "mode", - .type = EV_KEY, - .code = KEY_M, - .debounce_interval = WR512_3GN_KEYS_DEBOUNCE_INTERVAL, - .gpio = WR512_3GN_GPIO_BUTTON_CONNECT, - .active_low = 1, - } -}; - -#define WR512_3GN_GPIO_MODE \ - ((RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT) | \ - RT305X_GPIO_MODE_MDIO) - -static void __init wr512_3gn_init(void) -{ - rt305x_gpio_init(WR512_3GN_GPIO_MODE); - - rt305x_register_flash(0); - - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW; - rt305x_register_ethernet(); - ramips_register_gpio_leds(-1, ARRAY_SIZE(wr512_3gn_leds_gpio), - wr512_3gn_leds_gpio); - ramips_register_gpio_buttons(-1, WR512_3GN_KEYS_POLL_INTERVAL, - ARRAY_SIZE(wr512_3gn_gpio_buttons), - wr512_3gn_gpio_buttons); - rt305x_register_wifi(); - rt305x_register_wdt(); - rt305x_register_usb(); -} - -MIPS_MACHINE(RAMIPS_MACH_WR512_3GN, "WR512-3GN", "WR512-3GN-like router", - wr512_3gn_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-wr6202.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-wr6202.c deleted file mode 100644 index 591d9ceb59..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-wr6202.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * AWB WR6202 board support - * - * Copyright (C) 2012 Johnathan Boyce - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define WR6202_GPIO_BUTTON_RESET 10 /* active low */ -#define WR6202_GPIO_BUTTON_WPS 0 /* active low */ - -#define WR6202_KEYS_POLL_INTERVAL 20 -#define WR6202_KEYS_DEBOUNCE_INTERVAL (3 * WR6202_KEYS_POLL_INTERVAL) - -#define WR6202_GPIO_USB_POWER 11 - -#define WR6202_GPIO_LED_3G 13 -#define WR6202_GPIO_LED_WPS 14 - -static struct gpio_led wr6202_leds_gpio[] __initdata = { - { - .name = "wr6202:blue:wps", - .gpio = WR6202_GPIO_LED_WPS, - .active_low = 1, - }, { - .name = "wr6202:blue:3g", - .gpio = WR6202_GPIO_LED_3G, - .active_low = 1, - } -}; - -static struct gpio_keys_button wr6202_gpio_buttons[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = WR6202_KEYS_DEBOUNCE_INTERVAL, - .gpio = WR6202_GPIO_BUTTON_RESET, - .active_low = 1, - }, { - .desc = "wps", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = WR6202_KEYS_DEBOUNCE_INTERVAL, - .gpio = WR6202_GPIO_BUTTON_WPS, - .active_low = 1, - } -}; - -static void __init wr6202_init(void) -{ - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL; - - rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT); - - ramips_register_gpio_leds(-1, ARRAY_SIZE(wr6202_leds_gpio), - wr6202_leds_gpio); - ramips_register_gpio_buttons(-1, WR6202_KEYS_POLL_INTERVAL, - ARRAY_SIZE(wr6202_gpio_buttons), - wr6202_gpio_buttons); - - /* Power to the USB port is controlled by GPIO line */ - gpio_request(WR6202_GPIO_USB_POWER, "WR6202_GPIO_USB_POWER"); - gpio_direction_output(WR6202_GPIO_USB_POWER, 0); - gpio_free(WR6202_GPIO_USB_POWER); - - rt305x_register_flash(0); - - rt305x_register_ethernet(); - rt305x_register_wifi(); - rt305x_register_wdt(); - rt305x_register_usb(); -} - -MIPS_MACHINE(RAMIPS_MACH_WR6202, "WR6202", "AWB WR6202", - wr6202_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-xdx-rn502j.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-xdx-rn502j.c deleted file mode 100644 index f7ef353262..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/mach-xdx-rn502j.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Unknown router name/model, PCB marked with XDX-RN502J - * - * Copyright (C) 2011 Bruno Schwander bruno@tinkerbox.org - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include - -#include -#include -#include -#include -#include - -#include "devices.h" - -#define XDXRN502J_GPIO_BUTTON_RESET 12 -#define XDXRN502J_GPIO_LED_WIFI 7 -#define XDXRN502J_GPIO_LED_POWER 9 - -#define XDXRN502J_BUTTONS_POLL_INTERVAL 20 -#define XDXRN502J_BUTTONS_DEBOUNCE_INTERVAL (3 * XDXRN502J_BUTTONS_POLL_INTERVAL) - - -static struct gpio_led xdxrn502j_leds_gpio[] __initdata = { - { - .name = "xdxrn502j:green:wifi", - .gpio = XDXRN502J_GPIO_LED_WIFI, - .active_low = 1, - }, { - .name = "xdxrn502j:green:power", - .gpio = XDXRN502J_GPIO_LED_POWER, - .active_low = 1, - } -}; - -static struct gpio_keys_button xdxrn502j_gpio_buttons[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = XDXRN502J_BUTTONS_DEBOUNCE_INTERVAL, - .gpio = XDXRN502J_GPIO_BUTTON_RESET, - .active_low = 1, - } -}; - -#define XDXRN502J_GPIO_MODE \ - ((RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT) | \ - RT305X_GPIO_MODE_MDIO) - -static void __init xdxrn502j_init(void) -{ - rt305x_gpio_init(XDXRN502J_GPIO_MODE); - - rt305x_register_flash(0); - - rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL; - rt305x_register_ethernet(); - - ramips_register_gpio_leds(-1, ARRAY_SIZE(xdxrn502j_leds_gpio), - xdxrn502j_leds_gpio); - - ramips_register_gpio_buttons(-1, XDXRN502J_BUTTONS_POLL_INTERVAL, - ARRAY_SIZE(xdxrn502j_gpio_buttons), - xdxrn502j_gpio_buttons); - - rt305x_register_wifi(); - rt305x_register_wdt(); - rt305x_register_usb(); -} - -MIPS_MACHINE(RAMIPS_MACH_XDXRN502J, "XDXRN502J", "XDX RN502J", - xdxrn502j_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/rt305x.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/rt305x.c deleted file mode 100644 index 8a7a58b7d5..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/rt305x.c +++ /dev/null @@ -1,247 +0,0 @@ -/* - * Ralink RT305x SoC specific setup - * - * Copyright (C) 2008-2011 Gabor Juhos - * Copyright (C) 2008 Imre Kaloz - * - * Parts of this file are based on Ralink's 2.6.21 BSP - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include - -#include - -#include -#include -#include -#include - -void __iomem * rt305x_sysc_base; -void __iomem * rt305x_memc_base; -enum rt305x_soc_type rt305x_soc; - -static unsigned long rt5350_get_mem_size(void) -{ - void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE); - unsigned long ret; - u32 t; - - t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG); - t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) & - RT5350_SYSCFG0_DRAM_SIZE_MASK; - - switch (t) { - case RT5350_SYSCFG0_DRAM_SIZE_2M: - ret = 2 * 1024 * 1024; - break; - case RT5350_SYSCFG0_DRAM_SIZE_8M: - ret = 8 * 1024 * 1024; - break; - case RT5350_SYSCFG0_DRAM_SIZE_16M: - ret = 16 * 1024 * 1024; - break; - case RT5350_SYSCFG0_DRAM_SIZE_32M: - ret = 32 * 1024 * 1024; - break; - case RT5350_SYSCFG0_DRAM_SIZE_64M: - ret = 64 * 1024 * 1024; - break; - default: - panic("rt5350: invalid DRAM size: %u", t); - break; - } - - return ret; -} - -void __init ramips_soc_prom_init(void) -{ - void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE); - const char *name = "unknown"; - u32 n0; - u32 n1; - u32 id; - - n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); - n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); - - if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) { - unsigned long icache_sets; - - icache_sets = (read_c0_config1() >> 22) & 7; - if (icache_sets == 1) { - rt305x_soc = RT305X_SOC_RT3050; - name = "RT3050"; - } else { - rt305x_soc = RT305X_SOC_RT3052; - name = "RT3052"; - } - } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) { - rt305x_soc = RT305X_SOC_RT3350; - name = "RT3350"; - } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) { - rt305x_soc = RT305X_SOC_RT3352; - name = "RT3352"; - } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) { - rt305x_soc = RT305X_SOC_RT5350; - name = "RT5350"; - } else { - panic("rt305x: unknown SoC, n0:%08x n1:%08x\n", n0, n1); - } - - id = __raw_readl(sysc + SYSC_REG_CHIP_ID); - - snprintf(ramips_sys_type, RAMIPS_SYS_TYPE_LEN, - "Ralink %s id:%u rev:%u", - name, - (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK, - (id & CHIP_ID_REV_MASK)); - - ramips_mem_base = RT305X_SDRAM_BASE; - - if (soc_is_rt5350()) { - ramips_get_mem_size = rt5350_get_mem_size; - } else if (soc_is_rt305x() || soc_is_rt3350() ) { - ramips_mem_size_min = RT305X_MEM_SIZE_MIN; - ramips_mem_size_max = RT305X_MEM_SIZE_MAX; - } else if (soc_is_rt3352()) { - ramips_mem_size_min = RT3352_MEM_SIZE_MIN; - ramips_mem_size_max = RT3352_MEM_SIZE_MAX; - } else { - BUG(); - } -} - -static struct ramips_gpio_chip rt305x_gpio_chips[] = { - { - .chip = { - .label = "RT305X-GPIO0", - .base = 0, - .ngpio = 24, - }, - .regs = { - [RAMIPS_GPIO_REG_INT] = 0x00, - [RAMIPS_GPIO_REG_EDGE] = 0x04, - [RAMIPS_GPIO_REG_RENA] = 0x08, - [RAMIPS_GPIO_REG_FENA] = 0x0c, - [RAMIPS_GPIO_REG_DATA] = 0x20, - [RAMIPS_GPIO_REG_DIR] = 0x24, - [RAMIPS_GPIO_REG_POL] = 0x28, - [RAMIPS_GPIO_REG_SET] = 0x2c, - [RAMIPS_GPIO_REG_RESET] = 0x30, - [RAMIPS_GPIO_REG_TOGGLE] = 0x34, - }, - .map_base = RT305X_PIO_BASE, - .map_size = RT305X_PIO_SIZE, - }, - { - .chip = { - .label = "RT305X-GPIO1", - .base = 24, - .ngpio = 16, - }, - .regs = { - [RAMIPS_GPIO_REG_INT] = 0x38, - [RAMIPS_GPIO_REG_EDGE] = 0x3c, - [RAMIPS_GPIO_REG_RENA] = 0x40, - [RAMIPS_GPIO_REG_FENA] = 0x44, - [RAMIPS_GPIO_REG_DATA] = 0x48, - [RAMIPS_GPIO_REG_DIR] = 0x4c, - [RAMIPS_GPIO_REG_POL] = 0x50, - [RAMIPS_GPIO_REG_SET] = 0x54, - [RAMIPS_GPIO_REG_RESET] = 0x58, - [RAMIPS_GPIO_REG_TOGGLE] = 0x5c, - }, - .map_base = RT305X_PIO_BASE, - .map_size = RT305X_PIO_SIZE, - }, - { - .chip = { - .label = "RT305X-GPIO2", - .base = 40, - .ngpio = 12, - }, - .regs = { - [RAMIPS_GPIO_REG_INT] = 0x60, - [RAMIPS_GPIO_REG_EDGE] = 0x64, - [RAMIPS_GPIO_REG_RENA] = 0x68, - [RAMIPS_GPIO_REG_FENA] = 0x6c, - [RAMIPS_GPIO_REG_DATA] = 0x70, - [RAMIPS_GPIO_REG_DIR] = 0x74, - [RAMIPS_GPIO_REG_POL] = 0x78, - [RAMIPS_GPIO_REG_SET] = 0x7c, - [RAMIPS_GPIO_REG_RESET] = 0x80, - [RAMIPS_GPIO_REG_TOGGLE] = 0x84, - }, - .map_base = RT305X_PIO_BASE, - .map_size = RT305X_PIO_SIZE, - }, -}; - -static struct ramips_gpio_data rt305x_gpio_data = { - .chips = rt305x_gpio_chips, - .num_chips = ARRAY_SIZE(rt305x_gpio_chips), -}; - -static void rt305x_gpio_reserve(int first, int last) -{ - for (; first <= last; first++) - gpio_request(first, "reserved"); -} - -void __init rt305x_gpio_init(u32 mode) -{ - u32 t; - - rt305x_sysc_wr(mode, SYSC_REG_GPIO_MODE); - - ramips_gpio_init(&rt305x_gpio_data); - if ((mode & RT305X_GPIO_MODE_I2C) == 0) - rt305x_gpio_reserve(RT305X_GPIO_I2C_SD, RT305X_GPIO_I2C_SCLK); - - if ((mode & RT305X_GPIO_MODE_SPI) == 0) - rt305x_gpio_reserve(RT305X_GPIO_SPI_EN, RT305X_GPIO_SPI_CLK); - - t = mode >> RT305X_GPIO_MODE_UART0_SHIFT; - t &= RT305X_GPIO_MODE_UART0_MASK; - switch (t) { - case RT305X_GPIO_MODE_UARTF: - case RT305X_GPIO_MODE_PCM_UARTF: - case RT305X_GPIO_MODE_PCM_I2S: - case RT305X_GPIO_MODE_I2S_UARTF: - rt305x_gpio_reserve(RT305X_GPIO_7, RT305X_GPIO_14); - break; - case RT305X_GPIO_MODE_PCM_GPIO: - rt305x_gpio_reserve(RT305X_GPIO_10, RT305X_GPIO_14); - break; - case RT305X_GPIO_MODE_GPIO_UARTF: - case RT305X_GPIO_MODE_GPIO_I2S: - rt305x_gpio_reserve(RT305X_GPIO_7, RT305X_GPIO_10); - break; - } - - if ((mode & RT305X_GPIO_MODE_UART1) == 0) - rt305x_gpio_reserve(RT305X_GPIO_UART1_TXD, - RT305X_GPIO_UART1_RXD); - - if ((mode & RT305X_GPIO_MODE_JTAG) == 0) - rt305x_gpio_reserve(RT305X_GPIO_JTAG_TDO, RT305X_GPIO_JTAG_TDI); - - if ((mode & RT305X_GPIO_MODE_MDIO) == 0) - rt305x_gpio_reserve(RT305X_GPIO_MDIO_MDC, - RT305X_GPIO_MDIO_MDIO); - - if ((mode & RT305X_GPIO_MODE_SDRAM) == 0) - rt305x_gpio_reserve(RT305X_GPIO_SDRAM_MD16, - RT305X_GPIO_SDRAM_MD31); - - if ((mode & RT305X_GPIO_MODE_RGMII) == 0) - rt305x_gpio_reserve(RT305X_GPIO_GE0_TXD0, - RT305X_GPIO_GE0_RXCLK); -} diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/setup.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/setup.c deleted file mode 100644 index 5a069db454..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/setup.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Ralink RT305x SoC specific setup - * - * Copyright (C) 2008-2011 Gabor Juhos - * - * Parts of this file are based on Ralink's 2.6.21 BSP - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include "common.h" - -static void rt305x_restart(char *command) -{ - rt305x_sysc_wr(RT305X_RESET_SYSTEM, SYSC_REG_RESET_CTRL); - while (1) - if (cpu_wait) - cpu_wait(); -} - -static void rt305x_halt(void) -{ - while (1) - if (cpu_wait) - cpu_wait(); -} - -unsigned int __cpuinit get_c0_compare_irq(void) -{ - return CP0_LEGACY_COMPARE_IRQ; -} - -void __init ramips_soc_setup(void) -{ - struct clk *clk; - - rt305x_sysc_base = ioremap_nocache(RT305X_SYSC_BASE, PAGE_SIZE); - rt305x_memc_base = ioremap_nocache(RT305X_MEMC_BASE, PAGE_SIZE); - - rt305x_clocks_init(); - - clk = clk_get(NULL, "cpu"); - if (IS_ERR(clk)) - panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); - - printk(KERN_INFO "%s running at %lu.%02lu MHz\n", ramips_sys_type, - clk_get_rate(clk) / 1000000, - (clk_get_rate(clk) % 1000000) * 100 / 1000000); - - _machine_restart = rt305x_restart; - _machine_halt = rt305x_halt; - pm_power_off = rt305x_halt; - - clk = clk_get(NULL, "uart"); - if (IS_ERR(clk)) - panic("unable to get UART clock, err=%ld", PTR_ERR(clk)); - - ramips_early_serial_setup(0, RT305X_UART0_BASE, clk_get_rate(clk), - RT305X_INTC_IRQ_UART0); - ramips_early_serial_setup(1, RT305X_UART1_BASE, clk_get_rate(clk), - RT305X_INTC_IRQ_UART1); -} - -void __init plat_time_init(void) -{ - struct clk *clk; - - clk = clk_get(NULL, "cpu"); - if (IS_ERR(clk)) - panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); - - mips_hpt_frequency = clk_get_rate(clk) / 2; -} diff --git a/target/linux/ramips/files/arch/mips/ralink/rt3883/Kconfig b/target/linux/ramips/files/arch/mips/ralink/rt3883/Kconfig deleted file mode 100644 index 57823f0c67..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt3883/Kconfig +++ /dev/null @@ -1,34 +0,0 @@ -if RALINK_RT3883 - -menu "Ralink RT3662/RT3883 machine selection" - -config RT3883_MACH_RT_N56U - bool "Asus RT-N56U support" - select HW_HAS_PCI - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT3883_MACH_DIR_645 - bool "D-Link DIR-645 support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT3883_MACH_OMNI_EMB_HPM - bool "Omnima EMB HPM board support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT3883_MACH_TEW_691GR - bool "TRENDnet TEW-691GR support" - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -config RT3883_MACH_TEW_692GR - bool "TRENDnet TEW-692GR support" - select HW_HAS_PCI - select RALINK_DEV_GPIO_BUTTONS - select RALINK_DEV_GPIO_LEDS - -endmenu - -endif diff --git a/target/linux/ramips/files/arch/mips/ralink/rt3883/Makefile b/target/linux/ramips/files/arch/mips/ralink/rt3883/Makefile deleted file mode 100644 index e1ab61e814..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt3883/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# Makefile for the Ralink RT3662/RT3883 SoC specific parts of the kernel -# -# Copyright (C) 2011-2012 Gabor Juhos -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of the GNU General Public License version 2 as published -# by the Free Software Foundation. - -obj-y := irq.o setup.o devices.o rt3883.o clock.o - -obj-$(CONFIG_EARLY_PRINTK) += early_printk.o - -obj-$(CONFIG_RT3883_MACH_DIR_645) += mach-dir-645.o -obj-$(CONFIG_RT3883_MACH_OMNI_EMB_HPM) += mach-omni-emb-hpm.o -obj-$(CONFIG_RT3883_MACH_RT_N56U) += mach-rt-n56u.o -obj-$(CONFIG_RT3883_MACH_TEW_691GR) += mach-tew-691gr.o -obj-$(CONFIG_RT3883_MACH_TEW_692GR) += mach-tew-692gr.o diff --git a/target/linux/ramips/files/arch/mips/ralink/rt3883/clock.c b/target/linux/ramips/files/arch/mips/ralink/rt3883/clock.c deleted file mode 100644 index bf70259cae..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt3883/clock.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Ralink RT3662/RT3883 clock API - * - * Copyright (C) 2011-2012 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include "common.h" - -struct clk { - unsigned long rate; -}; - -static struct clk rt3883_cpu_clk; -static struct clk rt3883_sys_clk; -static struct clk rt3883_wdt_clk; -static struct clk rt3883_uart_clk; - -void __init rt3883_clocks_init(void) -{ - u32 syscfg0; - u32 clksel; - u32 ddr2; - - syscfg0 = rt3883_sysc_rr(RT3883_SYSC_REG_SYSCFG0); - clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) & - RT3883_SYSCFG0_CPUCLK_MASK); - ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2; - - switch (clksel) { - case RT3883_SYSCFG0_CPUCLK_250: - rt3883_cpu_clk.rate = 250000000; - rt3883_sys_clk.rate = (ddr2) ? 125000000 : 83000000; - break; - case RT3883_SYSCFG0_CPUCLK_384: - rt3883_cpu_clk.rate = 384000000; - rt3883_sys_clk.rate = (ddr2) ? 128000000 : 96000000; - break; - case RT3883_SYSCFG0_CPUCLK_480: - rt3883_cpu_clk.rate = 480000000; - rt3883_sys_clk.rate = (ddr2) ? 160000000 : 120000000; - break; - case RT3883_SYSCFG0_CPUCLK_500: - rt3883_cpu_clk.rate = 500000000; - rt3883_sys_clk.rate = (ddr2) ? 166000000 : 125000000; - break; - } - - rt3883_wdt_clk.rate = rt3883_sys_clk.rate; - rt3883_uart_clk.rate = 40000000; -} - -struct clk *clk_get(struct device *dev, const char *id) -{ - if (!strcmp(id, "sys")) - return &rt3883_sys_clk; - - if (!strcmp(id, "cpu")) - return &rt3883_cpu_clk; - - if (!strcmp(id, "wdt")) - return &rt3883_wdt_clk; - - if (!strcmp(id, "uart")) - return &rt3883_uart_clk; - - return ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(clk_get); - -int clk_enable(struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - return clk->rate; -} -EXPORT_SYMBOL(clk_get_rate); - -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt3883/common.h b/target/linux/ramips/files/arch/mips/ralink/rt3883/common.h deleted file mode 100644 index a389dccce0..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt3883/common.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Ralink RT3662/RT3883 SoC common defines - * - * Copyright (C) 2011-2012 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef _RT3883_COMMON_H -#define _RT3883_COMMON_H - -void rt3883_clocks_init(void); - -#endif /* _RT3883_COMMON_H */ \ No newline at end of file diff --git a/target/linux/ramips/files/arch/mips/ralink/rt3883/devices.c b/target/linux/ramips/files/arch/mips/ralink/rt3883/devices.c deleted file mode 100644 index 6077e97dda..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt3883/devices.c +++ /dev/null @@ -1,398 +0,0 @@ -/* - * Ralink RT3662/RT3883 SoC platform device registration - * - * Copyright (C) 2011-2012 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include "devices.h" - -#include - -static struct resource rt3883_flash0_resources[] = { - { - .flags = IORESOURCE_MEM, - .start = RT3883_BOOT_BASE, - .end = RT3883_BOOT_BASE + RT3883_BOOT_SIZE - 1, - }, -}; - -struct physmap_flash_data rt3883_flash0_data; -static struct platform_device rt3883_flash0_device = { - .name = "physmap-flash", - .resource = rt3883_flash0_resources, - .num_resources = ARRAY_SIZE(rt3883_flash0_resources), - .dev = { - .platform_data = &rt3883_flash0_data, - }, -}; - -static struct resource rt3883_flash1_resources[] = { - { - .flags = IORESOURCE_MEM, - .start = RT3883_SRAM_BASE, - .end = RT3883_SRAM_BASE + RT3883_SRAM_SIZE - 1, - }, -}; - -struct physmap_flash_data rt3883_flash1_data; -static struct platform_device rt3883_flash1_device = { - .name = "physmap-flash", - .resource = rt3883_flash1_resources, - .num_resources = ARRAY_SIZE(rt3883_flash1_resources), - .dev = { - .platform_data = &rt3883_flash1_data, - }, -}; - -static int rt3883_flash_instance __initdata; -void __init rt3883_register_pflash(unsigned int id) -{ - struct platform_device *pdev; - struct physmap_flash_data *pdata; - void __iomem *fscc_base; - u32 t; - int reg; - - switch (id) { - case 0: - pdev = &rt3883_flash0_device; - reg = RT3883_FSCC_REG_FLASH_CFG0; - break; - case 1: - pdev = &rt3883_flash1_device; - reg = RT3883_FSCC_REG_FLASH_CFG1; - break; - default: - return; - } - - pdata = pdev->dev.platform_data; - - fscc_base = ioremap(RT3883_FSCC_BASE, RT3883_FSCC_SIZE); - if (!fscc_base) - panic("RT3883: ioremap failed for FSCC"); - - t = __raw_readl(fscc_base + reg); - iounmap(fscc_base); - - t = (t >> RT3883_FLASH_CFG_WIDTH_SHIFT) & RT3883_FLASH_CFG_WIDTH_MASK; - switch (t) { - case RT3883_FLASH_CFG_WIDTH_8BIT: - pdata->width = 1; - break; - case RT3883_FLASH_CFG_WIDTH_16BIT: - pdata->width = 2; - break; - case RT3883_FLASH_CFG_WIDTH_32BIT: - if (id == 1) { - pdata->width = 4; - break; - } - /* fallthrough */ - default: - pr_warn("RT3883: flash bank%d: invalid width detected\n", id); - return; - } - - pdev->id = rt3883_flash_instance; - - platform_device_register(pdev); - rt3883_flash_instance++; -} - -static atomic_t rt3883_usb_pwr_ref = ATOMIC_INIT(0); - -static int rt3883_usb_power_on(struct platform_device *pdev) -{ - - if (atomic_inc_return(&rt3883_usb_pwr_ref) == 1) { - u32 t; - - t = rt3883_sysc_rr(RT3883_SYSC_REG_USB_PS); - - /* enable clock for port0's and port1's phys */ - t = rt3883_sysc_rr(RT3883_SYSC_REG_CLKCFG1); - t |= RT3883_CLKCFG1_UPHY0_CLK_EN | RT3883_CLKCFG1_UPHY1_CLK_EN; - rt3883_sysc_wr(t, RT3883_SYSC_REG_CLKCFG1); - mdelay(500); - - /* pull USBHOST and USBDEV out from reset */ - t = rt3883_sysc_rr(RT3883_SYSC_REG_RSTCTRL); - t &= ~(RT3883_RSTCTRL_UHST | RT3883_RSTCTRL_UDEV); - rt3883_sysc_wr(t, RT3883_SYSC_REG_RSTCTRL); - mdelay(500); - - /* enable host mode */ - t = rt3883_sysc_rr(RT3883_SYSC_REG_SYSCFG1); - t |= RT3883_SYSCFG1_USB0_HOST_MODE; - rt3883_sysc_wr(t, RT3883_SYSC_REG_SYSCFG1); - - t = rt3883_sysc_rr(RT3883_SYSC_REG_USB_PS); - } - - return 0; -} - -static void rt3883_usb_power_off(struct platform_device *pdev) -{ - if (atomic_dec_return(&rt3883_usb_pwr_ref) == 0) { - u32 t; - - /* put USBHOST and USBDEV into reset */ - t = rt3883_sysc_rr(RT3883_SYSC_REG_RSTCTRL); - t |= RT3883_RSTCTRL_UHST | RT3883_RSTCTRL_UDEV; - rt3883_sysc_wr(t, RT3883_SYSC_REG_RSTCTRL); - udelay(10000); - - /* disable clock for port0's and port1's phys*/ - t = rt3883_sysc_rr(RT3883_SYSC_REG_CLKCFG1); - t &= ~(RT3883_CLKCFG1_UPHY0_CLK_EN | - RT3883_CLKCFG1_UPHY1_CLK_EN); - rt3883_sysc_wr(t, RT3883_SYSC_REG_CLKCFG1); - udelay(10000); - } -} - -static struct usb_ehci_pdata rt3883_ehci_data = { - .power_on = rt3883_usb_power_on, - .power_off = rt3883_usb_power_off, -}; - -static struct resource rt3883_ehci_resources[] = { - { - .start = RT3883_EHCI_BASE, - .end = RT3883_EHCI_BASE + PAGE_SIZE - 1, - .flags = IORESOURCE_MEM, - }, { - .start = RT3883_INTC_IRQ_UHST, - .end = RT3883_INTC_IRQ_UHST, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 rt3883_ehci_dmamask = DMA_BIT_MASK(32); -static struct platform_device rt3883_ehci_device = { - .name = "ehci-platform", - .id = -1, - .resource = rt3883_ehci_resources, - .num_resources = ARRAY_SIZE(rt3883_ehci_resources), - .dev = { - .dma_mask = &rt3883_ehci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &rt3883_ehci_data, - }, -}; - -static struct resource rt3883_ohci_resources[] = { - { - .start = RT3883_OHCI_BASE, - .end = RT3883_OHCI_BASE + PAGE_SIZE - 1, - .flags = IORESOURCE_MEM, - }, { - .start = RT3883_INTC_IRQ_UHST, - .end = RT3883_INTC_IRQ_UHST, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct usb_ohci_pdata rt3883_ohci_data = { - .power_on = rt3883_usb_power_on, - .power_off = rt3883_usb_power_off, -}; - -static u64 rt3883_ohci_dmamask = DMA_BIT_MASK(32); -static struct platform_device rt3883_ohci_device = { - .name = "ohci-platform", - .id = -1, - .resource = rt3883_ohci_resources, - .num_resources = ARRAY_SIZE(rt3883_ohci_resources), - .dev = { - .dma_mask = &rt3883_ohci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &rt3883_ohci_data, - }, -}; - -void __init rt3883_register_usbhost(void) -{ - platform_device_register(&rt3883_ehci_device); - platform_device_register(&rt3883_ohci_device); -} - -static void rt3883_fe_reset(void) -{ - u32 t; - - t = rt3883_sysc_rr(RT3883_SYSC_REG_RSTCTRL); - t |= RT3883_RSTCTRL_FE; - rt3883_sysc_wr(t , RT3883_SYSC_REG_RSTCTRL); - - t &= ~RT3883_RSTCTRL_FE; - rt3883_sysc_wr(t, RT3883_SYSC_REG_RSTCTRL); -} - -static struct resource rt3883_eth_resources[] = { - { - .start = RT3883_FE_BASE, - .end = RT3883_FE_BASE + PAGE_SIZE - 1, - .flags = IORESOURCE_MEM, - }, { - .start = RT3883_CPU_IRQ_FE, - .end = RT3883_CPU_IRQ_FE, - .flags = IORESOURCE_IRQ, - }, -}; - -struct ramips_eth_platform_data rt3883_eth_data = { - .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 }, - .reset_fe = rt3883_fe_reset, - .min_pkt_len = 64, -}; - -static struct platform_device rt3883_eth_device = { - .name = "ramips_eth", - .resource = rt3883_eth_resources, - .num_resources = ARRAY_SIZE(rt3883_eth_resources), - .dev = { - .platform_data = &rt3883_eth_data, - } -}; - -void __init rt3883_register_ethernet(void) -{ - struct clk *clk; - - clk = clk_get(NULL, "sys"); - if (IS_ERR(clk)) - panic("unable to get SYS clock, err=%ld", PTR_ERR(clk)); - - rt3883_eth_data.sys_freq = clk_get_rate(clk); - - platform_device_register(&rt3883_eth_device); -} - -static struct resource rt3883_wlan_resources[] = { - { - .start = RT3883_WLAN_BASE, - .end = RT3883_WLAN_BASE + 0x3FFFF, - .flags = IORESOURCE_MEM, - }, { - .start = RT3883_CPU_IRQ_WLAN, - .end = RT3883_CPU_IRQ_WLAN, - .flags = IORESOURCE_IRQ, - }, -}; - -struct rt2x00_platform_data rt3883_wlan_data; -static struct platform_device rt3883_wlan_device = { - .name = "rt2800_wmac", - .resource = rt3883_wlan_resources, - .num_resources = ARRAY_SIZE(rt3883_wlan_resources), - .dev = { - .platform_data = &rt3883_wlan_data, - } -}; - -void __init rt3883_register_wlan(void) -{ - rt3883_wlan_data.eeprom_file_name = "soc_wmac.eeprom", - platform_device_register(&rt3883_wlan_device); -} - -static struct resource rt3883_wdt_resources[] = { - { - .start = RT3883_TIMER_BASE, - .end = RT3883_TIMER_BASE + RT3883_TIMER_SIZE - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device rt3883_wdt_device = { - .name = "ramips-wdt", - .id = -1, - .resource = rt3883_wdt_resources, - .num_resources = ARRAY_SIZE(rt3883_wdt_resources), -}; - -void __init rt3883_register_wdt(bool enable_reset) -{ - if (enable_reset) { - u32 t; - - /* enable WDT reset output on GPIO 2 */ - t = rt3883_sysc_rr(RT3883_SYSC_REG_SYSCFG1); - t |= RT3883_SYSCFG1_GPIO2_AS_WDT_OUT; - rt3883_sysc_wr(t, RT3883_SYSC_REG_SYSCFG1); - } - - platform_device_register(&rt3883_wdt_device); -} - -static struct resource rt3883_nand_resources[] = { - { - .flags = IORESOURCE_MEM, - .start = RT3883_NANDC_BASE, - .end = RT3883_NANDC_BASE + RT3883_NANDC_SIZE - 1, - }, -}; - -struct ramips_nand_platform_data rt3883_nand_data; -static struct platform_device rt3883_nand_device = { - .name = RAMIPS_NAND_DRIVER_NAME, - .id = -1, - .resource = rt3883_nand_resources, - .num_resources = ARRAY_SIZE(rt3883_nand_resources), - .dev = { - .platform_data = &rt3883_nand_data, - }, -}; - -void __init rt3883_register_nand(void) -{ - platform_device_register(&rt3883_nand_device); -} - -static struct resource rt3883_spi_resources[] = { - { - .flags = IORESOURCE_MEM, - .start = RT3883_SPI_BASE, - .end = RT3883_SPI_BASE + RT3883_SPI_SIZE - 1, - }, -}; - -static struct platform_device rt3883_spi_device = { - .name = "ramips-spi", - .id = 0, - .resource = rt3883_spi_resources, - .num_resources = ARRAY_SIZE(rt3883_spi_resources), -}; - -void __init rt3883_register_spi(struct spi_board_info *info, int n) -{ - spi_register_board_info(info, n); - platform_device_register(&rt3883_spi_device); -} - diff --git a/target/linux/ramips/files/arch/mips/ralink/rt3883/devices.h b/target/linux/ramips/files/arch/mips/ralink/rt3883/devices.h deleted file mode 100644 index 808bcb2d36..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt3883/devices.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Ralink RT3662/3883 SoC specific platform device definitions - * - * Copyright (C) 2011-2012 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef _RT3883_DEVICES_H -#define _RT3883_DEVICES_H - -struct physmap_flash_data; -struct spi_board_info; - -extern struct physmap_flash_data rt3883_flash0_data; -extern struct physmap_flash_data rt3883_flash1_data; -void rt3883_register_pflash(unsigned int id); - -extern struct ramips_nand_platform_data rt3883_nand_data; -void rt3883_register_nand(void); - -extern struct ramips_eth_platform_data rt3883_eth_data; -void rt3883_register_ethernet(void); -void rt3883_register_usbhost(void); - -extern struct rt2x00_platform_data rt3883_wlan_data; -void rt3883_register_wlan(void); -void rt3883_register_wdt(bool enable_reset); - -void rt3883_register_spi(struct spi_board_info *info, int n); - -#endif /* _RT3883_DEVICES_H */ diff --git a/target/linux/ramips/files/arch/mips/ralink/rt3883/early_printk.c b/target/linux/ramips/files/arch/mips/ralink/rt3883/early_printk.c deleted file mode 100644 index e3bf7ba339..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt3883/early_printk.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Ralink RT3662/RT3883 SoC early printk support - * - * Copyright (C) 2011-2012 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include - -#include - -#include - -#define UART_READ(r) \ - __raw_readl((void __iomem *)(KSEG1ADDR(RT3883_UART1_BASE) + 4 * (r))) - -#define UART_WRITE(r, v) \ - __raw_writel((v), (void __iomem *)(KSEG1ADDR(RT3883_UART1_BASE) + 4 * (r))) - -void prom_putchar(unsigned char ch) -{ - while (((UART_READ(RT3883_UART_REG_LSR)) & UART_LSR_THRE) == 0); - UART_WRITE(RT3883_UART_REG_TX, ch); - while (((UART_READ(RT3883_UART_REG_LSR)) & UART_LSR_THRE) == 0); -} diff --git a/target/linux/ramips/files/arch/mips/ralink/rt3883/irq.c b/target/linux/ramips/files/arch/mips/ralink/rt3883/irq.c deleted file mode 100644 index b561fd38cd..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt3883/irq.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Ralink RT3662/RT3883 SoC specific interrupt handling - * - * Copyright (C) 2011-2012 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include - -#include -#include - -#include -#include -#include - -static void rt3883_intc_irq_dispatch(void) -{ - u32 pending; - - pending = ramips_intc_get_status(); - - if (pending & RT3883_INTC_INT_TIMER0) - do_IRQ(RT3883_INTC_IRQ_TIMER0); - - else if (pending & RT3883_INTC_INT_TIMER1) - do_IRQ(RT3883_INTC_IRQ_TIMER1); - - else if (pending & RT3883_INTC_INT_UART0) - do_IRQ(RT3883_INTC_IRQ_UART0); - - else if (pending & RT3883_INTC_INT_UART1) - do_IRQ(RT3883_INTC_IRQ_UART1); - - else if (pending & RT3883_INTC_INT_PERFC) - do_IRQ(RT3883_INTC_IRQ_PERFC); - - else if (pending & RT3883_INTC_INT_UHST) - do_IRQ(RT3883_INTC_IRQ_UHST); - - /* TODO: handle PIO interrupts as well */ - - else - spurious_interrupt(); -} - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned long pending; - - pending = read_c0_status() & read_c0_cause() & ST0_IM; - - if (pending & STATUSF_IP7) - do_IRQ(RT3883_CPU_IRQ_COUNTER); - - else if (pending & STATUSF_IP5) - do_IRQ(RT3883_CPU_IRQ_FE); - - else if (pending & STATUSF_IP6) - do_IRQ(RT3883_CPU_IRQ_WLAN); - - else if (pending & STATUSF_IP4) - do_IRQ(RT3883_CPU_IRQ_PCI); - - else if (pending & STATUSF_IP2) - rt3883_intc_irq_dispatch(); - - else - spurious_interrupt(); -} - -void __init arch_init_irq(void) -{ - mips_cpu_irq_init(); - ramips_intc_irq_init(RT3883_INTC_BASE, RT3883_CPU_IRQ_INTC, - RT3883_INTC_IRQ_BASE); - cp0_perfcount_irq = RT3883_INTC_IRQ_PERFC; -} diff --git a/target/linux/ramips/files/arch/mips/ralink/rt3883/mach-dir-645.c b/target/linux/ramips/files/arch/mips/ralink/rt3883/mach-dir-645.c deleted file mode 100644 index 825da27f77..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt3883/mach-dir-645.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * D-Link DIR-645 board support - * - * Copyright (C) 2012 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "devices.h" - -#define DIR_645_GPIO_LED_INET 0 -#define DIR_645_GPIO_LED_WPS 26 - -#define DIR_645_GPIO_BUTTON_RESET 9 -#define DIR_645_GPIO_BUTTON_WPS 14 - -#define DIR_645_GPIO_USB_POWER 30 - -#define DIR_645_GPIO_RTL8367_SCK 2 -#define DIR_645_GPIO_RTL8367_SDA 1 - -#define DIR_645_KEYS_POLL_INTERVAL 20 -#define DIR_645_KEYS_DEBOUNCE_INTERVAL (3 * DIR_645_KEYS_POLL_INTERVAL) - -static struct gpio_led dir_645_leds_gpio[] __initdata = { - { - .name = "d-link:green:inet", - .gpio = DIR_645_GPIO_LED_INET, - .active_low = 1, - }, - { - .name = "d-link:green:wps", - .gpio = DIR_645_GPIO_LED_WPS, - .active_low = 1, - }, -}; - -static struct gpio_keys_button dir_645_gpio_buttons[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = DIR_645_KEYS_DEBOUNCE_INTERVAL, - .gpio = DIR_645_GPIO_BUTTON_RESET, - .active_low = 1, - }, - { - .desc = "wps", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = DIR_645_KEYS_DEBOUNCE_INTERVAL, - .gpio = DIR_645_GPIO_BUTTON_WPS, - .active_low = 1, - } -}; - -static struct rtl8367_extif_config dir_645_rtl8367_extif1_cfg = { - .txdelay = 1, - .rxdelay = 0, - .mode = RTL8367_EXTIF_MODE_RGMII, - .ability = { - .force_mode = 1, - .txpause = 1, - .rxpause = 1, - .link = 1, - .duplex = 1, - .speed = RTL8367_PORT_SPEED_1000, - } -}; - -static struct rtl8367_platform_data dir_645_rtl8367_data = { - .gpio_sda = DIR_645_GPIO_RTL8367_SDA, - .gpio_sck = DIR_645_GPIO_RTL8367_SCK, - .extif1_cfg = &dir_645_rtl8367_extif1_cfg, -}; - -static struct platform_device dir_645_rtl8367_device = { - .name = RTL8367B_DRIVER_NAME, - .id = -1, - .dev = { - .platform_data = &dir_645_rtl8367_data, - } -}; - -static struct spi_board_info dir_645_spi_info[] = { - { - .bus_num = 0, - .chip_select = 0, - .max_speed_hz = 25000000, - .modalias = "m25p80", - } -}; - -static void __init dir_645_gpio_init(void) -{ - rt3883_gpio_init(RT3883_GPIO_MODE_I2C | - RT3883_GPIO_MODE_UART0(RT3883_GPIO_MODE_GPIO) | - RT3883_GPIO_MODE_JTAG | - RT3883_GPIO_MODE_PCI(RT3883_GPIO_MODE_PCI_FNC)); - - gpio_request_one(DIR_645_GPIO_USB_POWER, - GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, - "USB power"); -} - -static void __init dir_645_init(void) -{ - dir_645_gpio_init(); - - rt3883_register_spi(dir_645_spi_info, - ARRAY_SIZE(dir_645_spi_info)); - - ramips_register_gpio_leds(-1, ARRAY_SIZE(dir_645_leds_gpio), - dir_645_leds_gpio); - - ramips_register_gpio_buttons(-1, DIR_645_KEYS_POLL_INTERVAL, - ARRAY_SIZE(dir_645_gpio_buttons), - dir_645_gpio_buttons); - - platform_device_register(&dir_645_rtl8367_device); - - rt3883_wlan_data.disable_5ghz = 1; - rt3883_register_wlan(); - - rt3883_eth_data.speed = SPEED_1000; - rt3883_eth_data.duplex = DUPLEX_FULL; - rt3883_eth_data.tx_fc = 1; - rt3883_eth_data.rx_fc = 1; - rt3883_register_ethernet(); - - rt3883_register_wdt(false); - rt3883_register_usbhost(); -} - -MIPS_MACHINE(RAMIPS_MACH_DIR_645, "DIR-645", "D-Link DIR-645", dir_645_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt3883/mach-omni-emb-hpm.c b/target/linux/ramips/files/arch/mips/ralink/rt3883/mach-omni-emb-hpm.c deleted file mode 100644 index 77ccff624f..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt3883/mach-omni-emb-hpm.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Omnima EMB HPM board support - * - * Copyright (C) 2012 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "devices.h" - -#define OMNI_EMB_HPM_GPIO_LED_POWER 7 -#define OMNI_EMB_HPM_GPIO_LED_ETH_GREEN 20 -#define OMNI_EMB_HPM_GPIO_LED_ETH_RED 18 -#define OMNI_EMB_HPM_GPIO_LED_STATUS 21 -#define OMNI_EMB_HPM_GPIO_LED_WIFI_GREEN 17 -#define OMNI_EMB_HPM_GPIO_LED_WIFI_RED 19 - -#define OMNI_EMB_HPM_GPIO_BUTTON_RESET 14 - -#define OMNI_EMB_HPM_GPIO_USB0_ENABLE 2 -#define OMNI_EMB_HPM_GPIO_USB1_ENABLE 1 -#define OMNI_EMB_HPM_GPIO_USB0_OC 12 -#define OMNI_EMB_HPM_GPIO_USB1_OC 13 - -#define OMNI_EMB_HPM_KEYS_POLL_INTERVAL 20 -#define OMNI_EMB_HPM_KEYS_DEBOUNCE_INTERVAL (3 * OMNI_EMB_HPM_KEYS_POLL_INTERVAL) - -static struct gpio_led omni_emb_hpm_leds_gpio[] __initdata = { - { - .name = "emb:orange:power", - .gpio = OMNI_EMB_HPM_GPIO_LED_POWER, - .active_low = 1, - }, - { - .name = "emb:green:status", - .gpio = OMNI_EMB_HPM_GPIO_LED_STATUS, - }, - { - .name = "emb:green:eth", - .gpio = OMNI_EMB_HPM_GPIO_LED_ETH_GREEN, - .active_low = 1, - }, - { - .name = "emb:red:eth", - .gpio = OMNI_EMB_HPM_GPIO_LED_ETH_RED, - .active_low = 1, - }, - { - .name = "emb:green:wifi", - .gpio = OMNI_EMB_HPM_GPIO_LED_WIFI_GREEN, - .active_low = 1, - }, - { - .name = "emb:red:wifi", - .gpio = OMNI_EMB_HPM_GPIO_LED_WIFI_RED, - .active_low = 1, - }, -}; - -static struct gpio_keys_button omni_emb_hpm_gpio_buttons[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = OMNI_EMB_HPM_KEYS_DEBOUNCE_INTERVAL, - .gpio = OMNI_EMB_HPM_GPIO_BUTTON_RESET, - .active_low = 1, - }, -}; - -static struct spi_board_info omni_emb_hpm_spi_info[] = { - { - .bus_num = 0, - .chip_select = 0, - .max_speed_hz = 25000000, - .modalias = "m25p80", - } -}; - - -static void __init omni_emb_hpm_gpio_request(unsigned int gpio, - unsigned long flags, - const char *label, - bool free) -{ - int err; - - err = gpio_request_one(gpio, flags, label); - if (err) { - pr_err("EMB_HPM: can't setup GPIO%u (%s), err=%d\n", - gpio, label, err); - return; - } - - if (free) - gpio_free(gpio); -} - -static void __init omni_emb_hpm_gpio_init(void) -{ - rt3883_gpio_init(RT3883_GPIO_MODE_I2C | - RT3883_GPIO_MODE_UART0(RT3883_GPIO_MODE_GPIO) | - RT3883_GPIO_MODE_JTAG); - - omni_emb_hpm_gpio_request(OMNI_EMB_HPM_GPIO_USB0_ENABLE, - GPIOF_OUT_INIT_HIGH, - "USB0 power", true); - omni_emb_hpm_gpio_request(OMNI_EMB_HPM_GPIO_USB1_ENABLE, - GPIOF_OUT_INIT_HIGH, - "USB1 power", true); - omni_emb_hpm_gpio_request(OMNI_EMB_HPM_GPIO_USB0_OC, - GPIOF_IN, "USB0 OC", false); - omni_emb_hpm_gpio_request(OMNI_EMB_HPM_GPIO_USB1_OC, - GPIOF_IN, "USB1 OC", false); -} - -static void __init omni_emb_hpm_init(void) -{ - omni_emb_hpm_gpio_init(); - - ramips_register_gpio_leds(-1, ARRAY_SIZE(omni_emb_hpm_leds_gpio), - omni_emb_hpm_leds_gpio); - - ramips_register_gpio_buttons(-1, OMNI_EMB_HPM_KEYS_POLL_INTERVAL, - ARRAY_SIZE(omni_emb_hpm_gpio_buttons), - omni_emb_hpm_gpio_buttons); - - rt3883_register_spi(omni_emb_hpm_spi_info, - ARRAY_SIZE(omni_emb_hpm_spi_info)); - - rt3883_register_wlan(); - - rt3883_eth_data.phy_mask = BIT(4); - rt3883_register_ethernet(); - - rt3883_register_wdt(false); - rt3883_register_usbhost(); -} - -MIPS_MACHINE(RAMIPS_MACH_OMNI_EMB_HPM, "OMNI-EMB-HPM", "Omnima EMB HPM", - omni_emb_hpm_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt3883/mach-rt-n56u.c b/target/linux/ramips/files/arch/mips/ralink/rt3883/mach-rt-n56u.c deleted file mode 100644 index 99aa03fe9e..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt3883/mach-rt-n56u.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Asus RT-N56U board support - * - * Copyright (C) 2011-2012 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "devices.h" - -#define RT_N56U_GPIO_LED_POWER 0 -#define RT_N56U_GPIO_LED_LAN 19 -#define RT_N56U_GPIO_LED_USB 24 -#define RT_N56U_GPIO_LED_WAN 27 -#define RT_N56U_GPIO_BUTTON_RESET 13 -#define RT_N56U_GPIO_BUTTON_WPS 26 - -#define RT_N56U_GPIO_RTL8367_SCK 2 -#define RT_N56U_GPIO_RTL8367_SDA 1 - -#define RT_N56U_KEYS_POLL_INTERVAL 20 -#define RT_N56U_KEYS_DEBOUNCE_INTERVAL (3 * RT_N56U_KEYS_POLL_INTERVAL) - -static struct gpio_led rt_n56u_leds_gpio[] __initdata = { - { - .name = "asus:blue:power", - .gpio = RT_N56U_GPIO_LED_POWER, - .active_low = 1, - }, - { - .name = "asus:blue:lan", - .gpio = RT_N56U_GPIO_LED_LAN, - .active_low = 1, - }, - { - .name = "asus:blue:wan", - .gpio = RT_N56U_GPIO_LED_WAN, - .active_low = 1, - }, - { - .name = "asus:blue:usb", - .gpio = RT_N56U_GPIO_LED_USB, - .active_low = 1, - }, -}; - -static struct gpio_keys_button rt_n56u_gpio_buttons[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = RT_N56U_KEYS_DEBOUNCE_INTERVAL, - .gpio = RT_N56U_GPIO_BUTTON_RESET, - .active_low = 1, - }, - { - .desc = "wps", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = RT_N56U_KEYS_DEBOUNCE_INTERVAL, - .gpio = RT_N56U_GPIO_BUTTON_WPS, - .active_low = 1, - } -}; - -static struct rtl8367_extif_config rt_n56u_rtl8367_extif1_cfg = { - .txdelay = 1, - .rxdelay = 0, - .mode = RTL8367_EXTIF_MODE_RGMII, - .ability = { - .force_mode = 1, - .txpause = 1, - .rxpause = 1, - .link = 1, - .duplex = 1, - .speed = RTL8367_PORT_SPEED_1000, - } -}; - -static struct rtl8367_platform_data rt_n56u_rtl8367_data = { - .gpio_sda = RT_N56U_GPIO_RTL8367_SDA, - .gpio_sck = RT_N56U_GPIO_RTL8367_SCK, - .extif1_cfg = &rt_n56u_rtl8367_extif1_cfg, -}; - -static struct platform_device rt_n56u_rtl8367_device = { - .name = RTL8367_DRIVER_NAME, - .id = -1, - .dev = { - .platform_data = &rt_n56u_rtl8367_data, - } -}; - -static struct rt2x00_platform_data rt_n56u_pci_wlan_data = { - .eeprom_file_name = "rt2x00pci_1_0.eeprom", -}; - -static int rt_n56u_pci_plat_dev_init(struct pci_dev *dev) -{ - if (dev->bus->number == 1 && PCI_SLOT(dev->devfn) == 0) - dev->dev.platform_data = &rt_n56u_pci_wlan_data; - - return 0; -} - -static void __init rt_n56u_init(void) -{ - rt3883_gpio_init(RT3883_GPIO_MODE_I2C | - RT3883_GPIO_MODE_UART0(RT3883_GPIO_MODE_GPIO) | - RT3883_GPIO_MODE_JTAG | - RT3883_GPIO_MODE_PCI(RT3883_GPIO_MODE_PCI_FNC)); - - rt3883_register_pflash(0); - - ramips_register_gpio_leds(-1, ARRAY_SIZE(rt_n56u_leds_gpio), - rt_n56u_leds_gpio); - - ramips_register_gpio_buttons(-1, RT_N56U_KEYS_POLL_INTERVAL, - ARRAY_SIZE(rt_n56u_gpio_buttons), - rt_n56u_gpio_buttons); - - platform_device_register(&rt_n56u_rtl8367_device); - - rt3883_wlan_data.disable_2ghz = 1; - rt3883_register_wlan(); - - rt3883_eth_data.speed = SPEED_1000; - rt3883_eth_data.duplex = DUPLEX_FULL; - rt3883_eth_data.tx_fc = 1; - rt3883_eth_data.rx_fc = 1; - rt3883_register_ethernet(); - - rt3883_register_wdt(false); - rt3883_register_usbhost(); - rt3883_pci_set_plat_dev_init(rt_n56u_pci_plat_dev_init); - rt3883_pci_init(RT3883_PCI_MODE_PCIE); -} - -MIPS_MACHINE(RAMIPS_MACH_RT_N56U, "RT-N56U", "Asus RT-N56U", rt_n56u_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt3883/mach-tew-691gr.c b/target/linux/ramips/files/arch/mips/ralink/rt3883/mach-tew-691gr.c deleted file mode 100644 index 7b553ab6b2..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt3883/mach-tew-691gr.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * TRENDnet TEW-691GR board support - * - * Copyright (C) 2012 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "devices.h" - -#define TEW_691GR_GPIO_LED_WPS_GREEN 9 - -#define TEW_691GR_GPIO_BUTTON_RESET 10 -#define TEW_691GR_GPIO_BUTTON_WPS 26 - -#define TEW_691GR_GPIO_SWITCH_RFKILL 0 - -#define TEW_691GR_KEYS_POLL_INTERVAL 20 -#define TEW_691GR_KEYS_DEBOUNCE_INTERVAL (3 * TEW_691GR_KEYS_POLL_INTERVAL) - -static struct gpio_led tew_691gr_leds_gpio[] __initdata = { - { - .name = "trendnet:green:wps", - .gpio = TEW_691GR_GPIO_LED_WPS_GREEN, - .active_low = 1, - }, -}; - -static struct gpio_keys_button tew_691gr_gpio_buttons[] __initdata = { - { - .desc = "Reset button", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = TEW_691GR_KEYS_DEBOUNCE_INTERVAL, - .gpio = TEW_691GR_GPIO_BUTTON_RESET, - .active_low = 1, - }, - { - .desc = "WPS button", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = TEW_691GR_KEYS_DEBOUNCE_INTERVAL, - .gpio = TEW_691GR_GPIO_BUTTON_WPS, - .active_low = 1, - }, - { - .desc = "RFKILL switch", - .type = EV_SW, - .code = KEY_RFKILL, - .debounce_interval = TEW_691GR_KEYS_DEBOUNCE_INTERVAL, - .gpio = TEW_691GR_GPIO_SWITCH_RFKILL, - .active_low = 1, - }, -}; - -static void __init tew_691gr_init(void) -{ - rt3883_gpio_init(RT3883_GPIO_MODE_I2C | - RT3883_GPIO_MODE_SPI | - RT3883_GPIO_MODE_UART0(RT3883_GPIO_MODE_GPIO) | - RT3883_GPIO_MODE_JTAG | - RT3883_GPIO_MODE_PCI(RT3883_GPIO_MODE_PCI_FNC)); - - rt3883_register_pflash(0); - - ramips_register_gpio_leds(-1, ARRAY_SIZE(tew_691gr_leds_gpio), - tew_691gr_leds_gpio); - - ramips_register_gpio_buttons(-1, TEW_691GR_KEYS_POLL_INTERVAL, - ARRAY_SIZE(tew_691gr_gpio_buttons), - tew_691gr_gpio_buttons); - - rt3883_wlan_data.disable_5ghz = 1; - rt3883_register_wlan(); - - rt3883_eth_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; - rt3883_eth_data.phy_mask = BIT(0); - rt3883_eth_data.tx_fc = 1; - rt3883_eth_data.rx_fc = 1; - rt3883_register_ethernet(); - - rt3883_register_wdt(false); -} - -MIPS_MACHINE(RAMIPS_MACH_TEW_691GR, "TEW-691GR", "TRENDnet TEW-691GR", - tew_691gr_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt3883/mach-tew-692gr.c b/target/linux/ramips/files/arch/mips/ralink/rt3883/mach-tew-692gr.c deleted file mode 100644 index 59b520a371..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt3883/mach-tew-692gr.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - * TRENDnet TEW-692GR board support - * - * Copyright (C) 2012 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "devices.h" - -#define TEW_692GR_GPIO_LED_WPS_ORANGE 9 -#define TEW_692GR_GPIO_LED_WPS_GREEN 28 - -#define TEW_692GR_GPIO_BUTTON_RESET 10 -#define TEW_692GR_GPIO_BUTTON_WPS 26 - -#define TEW_692GR_KEYS_POLL_INTERVAL 20 -#define TEW_692GR_KEYS_DEBOUNCE_INTERVAL (3 * TEW_692GR_KEYS_POLL_INTERVAL) - -static struct gpio_led tew_692gr_leds_gpio[] __initdata = { - { - .name = "trendnet:orange:wps", - .gpio = TEW_692GR_GPIO_LED_WPS_ORANGE, - .active_low = 1, - }, - { - .name = "trendnet:green:wps", - .gpio = TEW_692GR_GPIO_LED_WPS_GREEN, - .active_low = 1, - }, -}; - -static struct gpio_keys_button tew_692gr_gpio_buttons[] __initdata = { - { - .desc = "Reset button", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = TEW_692GR_KEYS_DEBOUNCE_INTERVAL, - .gpio = TEW_692GR_GPIO_BUTTON_RESET, - .active_low = 1, - }, - { - .desc = "WPS button", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = TEW_692GR_KEYS_DEBOUNCE_INTERVAL, - .gpio = TEW_692GR_GPIO_BUTTON_WPS, - .active_low = 1, - }, -}; - -static struct ar8327_pad_cfg tew_692gr_ar8327_pad0_cfg = { - .mode = AR8327_PAD_MAC_RGMII, - .txclk_delay_en = true, - .rxclk_delay_en = true, - .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, - .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, -}; - -static struct ar8327_pad_cfg tew_692gr_ar8327_pad6_cfg = { - .mode = AR8327_PAD_MAC_RGMII, - .rxclk_delay_en = true, - .rxclk_delay_sel = AR8327_CLK_DELAY_SEL0, -}; - -static struct ar8327_led_cfg tew_692gr_ar8327_led_cfg = { - .led_ctrl0 = 0xc437c437, - .led_ctrl1 = 0xc337c337, - .led_ctrl2 = 0x00000000, - .led_ctrl3 = 0x03ffff00, - .open_drain = false, -}; - -static struct ar8327_platform_data tew_692gr_ar8327_data = { - .pad0_cfg = &tew_692gr_ar8327_pad0_cfg, - .pad6_cfg = &tew_692gr_ar8327_pad6_cfg, - .port0_cfg = { - .force_link = 1, - .speed = AR8327_PORT_SPEED_1000, - .duplex = 1, - .txpause = 1, - .rxpause = 1, - }, - .led_cfg = &tew_692gr_ar8327_led_cfg, -}; - -static struct mdio_board_info tew_692gr_mdio0_info[] = { - { - .bus_id = "ramips_mdio", - .phy_addr = 0, - .platform_data = &tew_692gr_ar8327_data, - }, -}; - -static void __init tew_692gr_init(void) -{ - rt3883_gpio_init(RT3883_GPIO_MODE_I2C | - RT3883_GPIO_MODE_SPI | - RT3883_GPIO_MODE_UART0(RT3883_GPIO_MODE_GPIO) | - RT3883_GPIO_MODE_JTAG | - RT3883_GPIO_MODE_PCI(RT3883_GPIO_MODE_PCI_FNC)); - - rt3883_register_pflash(0); - - ramips_register_gpio_leds(-1, ARRAY_SIZE(tew_692gr_leds_gpio), - tew_692gr_leds_gpio); - - ramips_register_gpio_buttons(-1, TEW_692GR_KEYS_POLL_INTERVAL, - ARRAY_SIZE(tew_692gr_gpio_buttons), - tew_692gr_gpio_buttons); - - rt3883_wlan_data.disable_5ghz = 1; - rt3883_register_wlan(); - - mdiobus_register_board_info(tew_692gr_mdio0_info, - ARRAY_SIZE(tew_692gr_mdio0_info)); - - rt3883_eth_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; - rt3883_eth_data.phy_mask = BIT(0); - rt3883_eth_data.tx_fc = 1; - rt3883_eth_data.rx_fc = 1; - rt3883_register_ethernet(); - - rt3883_register_wdt(false); - - rt3883_pci_init(RT3883_PCI_MODE_PCIE); -} - -MIPS_MACHINE(RAMIPS_MACH_TEW_692GR, "TEW-692GR", "TRENDnet TEW-692GR", - tew_692gr_init); diff --git a/target/linux/ramips/files/arch/mips/ralink/rt3883/rt3883.c b/target/linux/ramips/files/arch/mips/ralink/rt3883/rt3883.c deleted file mode 100644 index e397b854ea..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt3883/rt3883.c +++ /dev/null @@ -1,216 +0,0 @@ -/* - * Ralink RT3662/RT3883 SoC specific setup - * - * Copyright (C) 2011-2012 Gabor Juhos - * - * Parts of this file are based on Ralink's 2.6.21 BSP - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include - -#include -#include -#include -#include - -void __iomem * rt3883_sysc_base; -void __iomem * rt3883_memc_base; - -void __init ramips_soc_prom_init(void) -{ - void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE); - u32 n0; - u32 n1; - u32 id; - - n0 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID0_3); - n1 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID4_7); - id = __raw_readl(sysc + RT3883_SYSC_REG_REVID); - - snprintf(ramips_sys_type, RAMIPS_SYS_TYPE_LEN, - "Ralink %c%c%c%c%c%c%c%c ver:%u eco:%u", - (char) (n0 & 0xff), (char) ((n0 >> 8) & 0xff), - (char) ((n0 >> 16) & 0xff), (char) ((n0 >> 24) & 0xff), - (char) (n1 & 0xff), (char) ((n1 >> 8) & 0xff), - (char) ((n1 >> 16) & 0xff), (char) ((n1 >> 24) & 0xff), - (id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK, - (id & RT3883_REVID_ECO_ID_MASK)); - - ramips_mem_base = RT3883_SDRAM_BASE; - ramips_mem_size_min = RT3883_MEM_SIZE_MIN; - ramips_mem_size_max = RT3883_MEM_SIZE_MAX; -} - -static struct ramips_gpio_chip rt3883_gpio_chips[] = { - { - .chip = { - .label = "RT3883-GPIO0", - .base = 0, - .ngpio = 24, - }, - .regs = { - [RAMIPS_GPIO_REG_INT] = 0x00, - [RAMIPS_GPIO_REG_EDGE] = 0x04, - [RAMIPS_GPIO_REG_RENA] = 0x08, - [RAMIPS_GPIO_REG_FENA] = 0x0c, - [RAMIPS_GPIO_REG_DATA] = 0x20, - [RAMIPS_GPIO_REG_DIR] = 0x24, - [RAMIPS_GPIO_REG_POL] = 0x28, - [RAMIPS_GPIO_REG_SET] = 0x2c, - [RAMIPS_GPIO_REG_RESET] = 0x30, - [RAMIPS_GPIO_REG_TOGGLE] = 0x34, - }, - .map_base = RT3883_PIO_BASE, - .map_size = RT3883_PIO_SIZE, - }, - { - .chip = { - .label = "RT3883-GPIO1", - .base = 24, - .ngpio = 16, - }, - .regs = { - [RAMIPS_GPIO_REG_INT] = 0x38, - [RAMIPS_GPIO_REG_EDGE] = 0x3c, - [RAMIPS_GPIO_REG_RENA] = 0x40, - [RAMIPS_GPIO_REG_FENA] = 0x44, - [RAMIPS_GPIO_REG_DATA] = 0x48, - [RAMIPS_GPIO_REG_DIR] = 0x4c, - [RAMIPS_GPIO_REG_POL] = 0x50, - [RAMIPS_GPIO_REG_SET] = 0x54, - [RAMIPS_GPIO_REG_RESET] = 0x58, - [RAMIPS_GPIO_REG_TOGGLE] = 0x5c, - }, - .map_base = RT3883_PIO_BASE, - .map_size = RT3883_PIO_SIZE, - }, - { - .chip = { - .label = "RT3883-GPIO2", - .base = 40, - .ngpio = 32, - }, - .regs = { - [RAMIPS_GPIO_REG_INT] = 0x60, - [RAMIPS_GPIO_REG_EDGE] = 0x64, - [RAMIPS_GPIO_REG_RENA] = 0x68, - [RAMIPS_GPIO_REG_FENA] = 0x6c, - [RAMIPS_GPIO_REG_DATA] = 0x70, - [RAMIPS_GPIO_REG_DIR] = 0x74, - [RAMIPS_GPIO_REG_POL] = 0x78, - [RAMIPS_GPIO_REG_SET] = 0x7c, - [RAMIPS_GPIO_REG_RESET] = 0x80, - [RAMIPS_GPIO_REG_TOGGLE] = 0x84, - }, - .map_base = RT3883_PIO_BASE, - .map_size = RT3883_PIO_SIZE, - }, - { - .chip = { - .label = "RT3883-GPIO3", - .base = 72, - .ngpio = 24, - }, - .regs = { - [RAMIPS_GPIO_REG_INT] = 0x88, - [RAMIPS_GPIO_REG_EDGE] = 0x8c, - [RAMIPS_GPIO_REG_RENA] = 0x90, - [RAMIPS_GPIO_REG_FENA] = 0x94, - [RAMIPS_GPIO_REG_DATA] = 0x98, - [RAMIPS_GPIO_REG_DIR] = 0x9c, - [RAMIPS_GPIO_REG_POL] = 0xa0, - [RAMIPS_GPIO_REG_SET] = 0xa4, - [RAMIPS_GPIO_REG_RESET] = 0xa8, - [RAMIPS_GPIO_REG_TOGGLE] = 0xac, - }, - .map_base = RT3883_PIO_BASE, - .map_size = RT3883_PIO_SIZE, - }, -}; - -static struct ramips_gpio_data rt3883_gpio_data = { - .chips = rt3883_gpio_chips, - .num_chips = ARRAY_SIZE(rt3883_gpio_chips), -}; - -static void rt3883_gpio_reserve(int first, int last) -{ - for (; first <= last; first++) - gpio_request(first, "reserved"); -} - -void __init rt3883_gpio_init(u32 mode) -{ - u32 t; - - rt3883_sysc_wr(mode, RT3883_SYSC_REG_GPIO_MODE); - - ramips_gpio_init(&rt3883_gpio_data); - if ((mode & RT3883_GPIO_MODE_I2C) == 0) - rt3883_gpio_reserve(RT3883_GPIO_I2C_SD, RT3883_GPIO_I2C_SCLK); - - if ((mode & RT3883_GPIO_MODE_SPI) == 0) - rt3883_gpio_reserve(RT3883_GPIO_SPI_CS0, RT3883_GPIO_SPI_MISO); - - t = mode >> RT3883_GPIO_MODE_UART0_SHIFT; - t &= RT3883_GPIO_MODE_UART0_MASK; - switch (t) { - case RT3883_GPIO_MODE_UARTF: - case RT3883_GPIO_MODE_PCM_UARTF: - case RT3883_GPIO_MODE_PCM_I2S: - case RT3883_GPIO_MODE_I2S_UARTF: - rt3883_gpio_reserve(RT3883_GPIO_7, RT3883_GPIO_14); - break; - case RT3883_GPIO_MODE_PCM_GPIO: - rt3883_gpio_reserve(RT3883_GPIO_11, RT3883_GPIO_14); - break; - case RT3883_GPIO_MODE_GPIO_UARTF: - case RT3883_GPIO_MODE_GPIO_I2S: - rt3883_gpio_reserve(RT3883_GPIO_7, RT3883_GPIO_10); - break; - } - - if ((mode & RT3883_GPIO_MODE_UART1) == 0) - rt3883_gpio_reserve(RT3883_GPIO_UART1_TXD, - RT3883_GPIO_UART1_RXD); - - if ((mode & RT3883_GPIO_MODE_JTAG) == 0) - rt3883_gpio_reserve(RT3883_GPIO_JTAG_TDO, - RT3883_GPIO_JTAG_TCLK); - - if ((mode & RT3883_GPIO_MODE_MDIO) == 0) - rt3883_gpio_reserve(RT3883_GPIO_MDIO_MDC, - RT3883_GPIO_MDIO_MDIO); - - if ((mode & RT3883_GPIO_MODE_GE1) == 0) - rt3883_gpio_reserve(RT3883_GPIO_GE1_TXD0, - RT3883_GPIO_GE1_RXCLK); - - if ((mode & RT3883_GPIO_MODE_GE2) == 0) - rt3883_gpio_reserve(RT3883_GPIO_GE2_TXD0, - RT3883_GPIO_GE2_RXCLK); - - t = mode >> RT3883_GPIO_MODE_PCI_SHIFT; - t &= RT3883_GPIO_MODE_PCI_MASK; - if (t != RT3883_GPIO_MODE_PCI_GPIO) - rt3883_gpio_reserve(RT3883_GPIO_PCI_AD0, - RT3883_GPIO_PCI_AD31); - - t = mode >> RT3883_GPIO_MODE_LNA_A_SHIFT; - t &= RT3883_GPIO_MODE_LNA_A_MASK; - if (t != RT3883_GPIO_MODE_LNA_A_GPIO) - rt3883_gpio_reserve(RT3883_GPIO_LNA_PE_A0, - RT3883_GPIO_LNA_PE_A2); - - t = mode >> RT3883_GPIO_MODE_LNA_G_SHIFT; - t &= RT3883_GPIO_MODE_LNA_G_MASK; - if (t != RT3883_GPIO_MODE_LNA_G_GPIO) - rt3883_gpio_reserve(RT3883_GPIO_LNA_PE_G0, - RT3883_GPIO_LNA_PE_G2); -} diff --git a/target/linux/ramips/files/arch/mips/ralink/rt3883/setup.c b/target/linux/ramips/files/arch/mips/ralink/rt3883/setup.c deleted file mode 100644 index 6e037a7291..0000000000 --- a/target/linux/ramips/files/arch/mips/ralink/rt3883/setup.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Ralink RT3662/RT3883 SoC specific setup - * - * Copyright (C) 2011-2012 Gabor Juhos - * - * Parts of this file are based on Ralink's 2.6.21 BSP - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include "common.h" - -static void rt3883_restart(char *command) -{ - rt3883_sysc_wr(RT3883_RSTCTRL_SYS, RT3883_SYSC_REG_RSTCTRL); - while (1) - if (cpu_wait) - cpu_wait(); -} - -static void rt3883_halt(void) -{ - while (1) - if (cpu_wait) - cpu_wait(); -} - -unsigned int __cpuinit get_c0_compare_irq(void) -{ - return CP0_LEGACY_COMPARE_IRQ; -} - -void __init ramips_soc_setup(void) -{ - struct clk *clk; - - rt3883_sysc_base = ioremap_nocache(RT3883_SYSC_BASE, PAGE_SIZE); - rt3883_memc_base = ioremap_nocache(RT3883_MEMC_BASE, PAGE_SIZE); - - rt3883_clocks_init(); - - clk = clk_get(NULL, "cpu"); - if (IS_ERR(clk)) - panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); - - printk(KERN_INFO "%s running at %lu.%02lu MHz\n", ramips_sys_type, - clk_get_rate(clk) / 1000000, - (clk_get_rate(clk) % 1000000) * 100 / 1000000); - - _machine_restart = rt3883_restart; - _machine_halt = rt3883_halt; - pm_power_off = rt3883_halt; - - clk = clk_get(NULL, "uart"); - if (IS_ERR(clk)) - panic("unable to get UART clock, err=%ld", PTR_ERR(clk)); - - ramips_early_serial_setup(0, RT3883_UART0_BASE, clk_get_rate(clk), - RT3883_INTC_IRQ_UART0); - ramips_early_serial_setup(1, RT3883_UART1_BASE, clk_get_rate(clk), - RT3883_INTC_IRQ_UART1); -} - -void __init plat_time_init(void) -{ - struct clk *clk; - - clk = clk_get(NULL, "cpu"); - if (IS_ERR(clk)) - panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); - - mips_hpt_frequency = clk_get_rate(clk) / 2; -} diff --git a/target/linux/ramips/files/drivers/net/ethernet/ramips/Kconfig b/target/linux/ramips/files/drivers/net/ethernet/ramips/Kconfig deleted file mode 100644 index 1bc4c2bb08..0000000000 --- a/target/linux/ramips/files/drivers/net/ethernet/ramips/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -config NET_RAMIPS - tristate "Ralink RT288X/RT3X5X/RT3662/RT3883 ethernet driver" - depends on MIPS_RALINK - select PHYLIB if (SOC_RT288X || SOC_RT3883) - select SWCONFIG if SOC_RT305X - help - This driver supports the etehrnet mac inside the ralink wisocs - -if NET_RAMIPS - -config NET_RAMIPS_DEBUG - bool "Enable debug messages in the Ralink ethernet driver" - -config NET_RAMIPS_DEBUG_FS - bool "Enable debugfs support for the Ralink ethernet driver" - depends on DEBUG_FS - -endif diff --git a/target/linux/ramips/files/drivers/net/ethernet/ramips/Makefile b/target/linux/ramips/files/drivers/net/ethernet/ramips/Makefile deleted file mode 100644 index 22c460d4df..0000000000 --- a/target/linux/ramips/files/drivers/net/ethernet/ramips/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Makefile for the Ramips SoCs built-in ethernet macs -# - -ramips-y += ramips_main.o - -ramips-$(CONFIG_NET_RAMIPS_DEBUG_FS) += ramips_debugfs.o - -obj-$(CONFIG_NET_RAMIPS) += ramips.o diff --git a/target/linux/ramips/files/drivers/net/ethernet/ramips/ramips_debugfs.c b/target/linux/ramips/files/drivers/net/ethernet/ramips/ramips_debugfs.c deleted file mode 100644 index 20afcf5028..0000000000 --- a/target/linux/ramips/files/drivers/net/ethernet/ramips/ramips_debugfs.c +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Ralink SoC ethernet driver debugfs code - * - * Copyright (C) 2011-2012 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include - -#include "ramips_eth.h" - -static struct dentry *raeth_debugfs_root; - -static int raeth_debugfs_generic_open(struct inode *inode, struct file *file) -{ - file->private_data = inode->i_private; - return 0; -} - -void raeth_debugfs_update_int_stats(struct raeth_priv *re, u32 status) -{ - re->debug.int_stats.total += !!status; - - re->debug.int_stats.rx_delayed += !!(status & RAMIPS_RX_DLY_INT); - re->debug.int_stats.rx_done0 += !!(status & RAMIPS_RX_DONE_INT0); - re->debug.int_stats.rx_coherent += !!(status & RAMIPS_RX_COHERENT); - - re->debug.int_stats.tx_delayed += !!(status & RAMIPS_TX_DLY_INT); - re->debug.int_stats.tx_done0 += !!(status & RAMIPS_TX_DONE_INT0); - re->debug.int_stats.tx_done1 += !!(status & RAMIPS_TX_DONE_INT1); - re->debug.int_stats.tx_done2 += !!(status & RAMIPS_TX_DONE_INT2); - re->debug.int_stats.tx_done3 += !!(status & RAMIPS_TX_DONE_INT3); - re->debug.int_stats.tx_coherent += !!(status & RAMIPS_TX_COHERENT); - - re->debug.int_stats.pse_fq_empty += !!(status & RAMIPS_PSE_FQ_EMPTY); - re->debug.int_stats.pse_p0_fc += !!(status & RAMIPS_PSE_P0_FC); - re->debug.int_stats.pse_p1_fc += !!(status & RAMIPS_PSE_P1_FC); - re->debug.int_stats.pse_p2_fc += !!(status & RAMIPS_PSE_P2_FC); - re->debug.int_stats.pse_buf_drop += !!(status & RAMIPS_PSE_BUF_DROP); -} - -static ssize_t read_file_int_stats(struct file *file, char __user *user_buf, - size_t count, loff_t *ppos) -{ -#define PR_INT_STAT(_label, _field) \ - len += snprintf(buf + len, sizeof(buf) - len, \ - "%-18s: %10lu\n", _label, re->debug.int_stats._field); - - struct raeth_priv *re = file->private_data; - char buf[512]; - unsigned int len = 0; - unsigned long flags; - - spin_lock_irqsave(&re->page_lock, flags); - - PR_INT_STAT("RX Delayed", rx_delayed); - PR_INT_STAT("RX Done 0", rx_done0); - PR_INT_STAT("RX Coherent", rx_coherent); - - PR_INT_STAT("TX Delayed", tx_delayed); - PR_INT_STAT("TX Done 0", tx_done0); - PR_INT_STAT("TX Done 1", tx_done1); - PR_INT_STAT("TX Done 2", tx_done2); - PR_INT_STAT("TX Done 3", tx_done3); - PR_INT_STAT("TX Coherent", tx_coherent); - - PR_INT_STAT("PSE FQ empty", pse_fq_empty); - PR_INT_STAT("CDMA Flow control", pse_p0_fc); - PR_INT_STAT("GDMA1 Flow control", pse_p1_fc); - PR_INT_STAT("GDMA2 Flow control", pse_p2_fc); - PR_INT_STAT("PSE discard", pse_buf_drop); - - len += snprintf(buf + len, sizeof(buf) - len, "\n"); - PR_INT_STAT("Total", total); - - spin_unlock_irqrestore(&re->page_lock, flags); - - return simple_read_from_buffer(user_buf, count, ppos, buf, len); -#undef PR_INT_STAT -} - -static const struct file_operations raeth_fops_int_stats = { - .open = raeth_debugfs_generic_open, - .read = read_file_int_stats, - .owner = THIS_MODULE -}; - -void raeth_debugfs_exit(struct raeth_priv *re) -{ - debugfs_remove_recursive(re->debug.debugfs_dir); -} - -int raeth_debugfs_init(struct raeth_priv *re) -{ - re->debug.debugfs_dir = debugfs_create_dir(re->netdev->name, - raeth_debugfs_root); - if (!re->debug.debugfs_dir) - return -ENOMEM; - - debugfs_create_file("int_stats", S_IRUGO, re->debug.debugfs_dir, - re, &raeth_fops_int_stats); - - return 0; -} - -int raeth_debugfs_root_init(void) -{ - if (raeth_debugfs_root) - return -EBUSY; - - raeth_debugfs_root = debugfs_create_dir("raeth", NULL); - if (!raeth_debugfs_root) - return -ENOENT; - - return 0; -} - -void raeth_debugfs_root_exit(void) -{ - debugfs_remove(raeth_debugfs_root); - raeth_debugfs_root = NULL; -} diff --git a/target/linux/ramips/files/drivers/net/ethernet/ramips/ramips_esw.c b/target/linux/ramips/files/drivers/net/ethernet/ramips/ramips_esw.c deleted file mode 100644 index d3150d7a6f..0000000000 --- a/target/linux/ramips/files/drivers/net/ethernet/ramips/ramips_esw.c +++ /dev/null @@ -1,1132 +0,0 @@ -#include -#include -#include - -#include -#include - -/* - * HW limitations for this switch: - * - No large frame support (PKT_MAX_LEN at most 1536) - * - Can't have untagged vlan and tagged vlan on one port at the same time, - * though this might be possible using the undocumented PPE. - */ - -#define RT305X_ESW_REG_FCT0 0x08 -#define RT305X_ESW_REG_PFC1 0x14 -#define RT305X_ESW_REG_ATS 0x24 -#define RT305X_ESW_REG_ATS0 0x28 -#define RT305X_ESW_REG_ATS1 0x2c -#define RT305X_ESW_REG_ATS2 0x30 -#define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n)) -#define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n)) -#define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n)) -#define RT305X_ESW_REG_POA 0x80 -#define RT305X_ESW_REG_FPA 0x84 -#define RT305X_ESW_REG_SOCPC 0x8c -#define RT305X_ESW_REG_POC0 0x90 -#define RT305X_ESW_REG_POC1 0x94 -#define RT305X_ESW_REG_POC2 0x98 -#define RT305X_ESW_REG_SGC 0x9c -#define RT305X_ESW_REG_STRT 0xa0 -#define RT305X_ESW_REG_PCR0 0xc0 -#define RT305X_ESW_REG_PCR1 0xc4 -#define RT305X_ESW_REG_FPA2 0xc8 -#define RT305X_ESW_REG_FCT2 0xcc -#define RT305X_ESW_REG_SGC2 0xe4 -#define RT305X_ESW_REG_P0LED 0xa4 -#define RT305X_ESW_REG_P1LED 0xa8 -#define RT305X_ESW_REG_P2LED 0xac -#define RT305X_ESW_REG_P3LED 0xb0 -#define RT305X_ESW_REG_P4LED 0xb4 -#define RT305X_ESW_REG_P0PC 0xe8 -#define RT305X_ESW_REG_P1PC 0xec -#define RT305X_ESW_REG_P2PC 0xf0 -#define RT305X_ESW_REG_P3PC 0xf4 -#define RT305X_ESW_REG_P4PC 0xf8 -#define RT305X_ESW_REG_P5PC 0xfc - -#define RT305X_ESW_LED_LINK 0 -#define RT305X_ESW_LED_100M 1 -#define RT305X_ESW_LED_DUPLEX 2 -#define RT305X_ESW_LED_ACTIVITY 3 -#define RT305X_ESW_LED_COLLISION 4 -#define RT305X_ESW_LED_LINKACT 5 -#define RT305X_ESW_LED_DUPLCOLL 6 -#define RT305X_ESW_LED_10MACT 7 -#define RT305X_ESW_LED_100MACT 8 -/* Additional led states not in datasheet: */ -#define RT305X_ESW_LED_BLINK 10 -#define RT305X_ESW_LED_ON 12 - -#define RT305X_ESW_LINK_S 25 -#define RT305X_ESW_DUPLEX_S 9 -#define RT305X_ESW_SPD_S 0 - -#define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16 -#define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13) -#define RT305X_ESW_PCR0_CPU_PHY_REG_S 8 - -#define RT305X_ESW_PCR1_WT_DONE BIT(0) - -#define RT305X_ESW_ATS_TIMEOUT (5 * HZ) -#define RT305X_ESW_PHY_TIMEOUT (5 * HZ) - -#define RT305X_ESW_PVIDC_PVID_M 0xfff -#define RT305X_ESW_PVIDC_PVID_S 12 - -#define RT305X_ESW_VLANI_VID_M 0xfff -#define RT305X_ESW_VLANI_VID_S 12 - -#define RT305X_ESW_VMSC_MSC_M 0xff -#define RT305X_ESW_VMSC_MSC_S 8 - -#define RT305X_ESW_SOCPC_DISUN2CPU_S 0 -#define RT305X_ESW_SOCPC_DISMC2CPU_S 8 -#define RT305X_ESW_SOCPC_DISBC2CPU_S 16 -#define RT305X_ESW_SOCPC_CRC_PADDING BIT(25) - -#define RT305X_ESW_POC0_EN_BP_S 0 -#define RT305X_ESW_POC0_EN_FC_S 8 -#define RT305X_ESW_POC0_DIS_RMC2CPU_S 16 -#define RT305X_ESW_POC0_DIS_PORT_M 0x7f -#define RT305X_ESW_POC0_DIS_PORT_S 23 - -#define RT305X_ESW_POC2_UNTAG_EN_M 0xff -#define RT305X_ESW_POC2_UNTAG_EN_S 0 -#define RT305X_ESW_POC2_ENAGING_S 8 -#define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16 - -#define RT305X_ESW_SGC2_DOUBLE_TAG_M 0x7f -#define RT305X_ESW_SGC2_DOUBLE_TAG_S 0 -#define RT305X_ESW_SGC2_LAN_PMAP_M 0x3f -#define RT305X_ESW_SGC2_LAN_PMAP_S 24 - -#define RT305X_ESW_PFC1_EN_VLAN_M 0xff -#define RT305X_ESW_PFC1_EN_VLAN_S 16 -#define RT305X_ESW_PFC1_EN_TOS_S 24 - -#define RT305X_ESW_VLAN_NONE 0xfff - -#define RT305X_ESW_PORT0 0 -#define RT305X_ESW_PORT1 1 -#define RT305X_ESW_PORT2 2 -#define RT305X_ESW_PORT3 3 -#define RT305X_ESW_PORT4 4 -#define RT305X_ESW_PORT5 5 -#define RT305X_ESW_PORT6 6 - -#define RT305X_ESW_PORTS_NONE 0 - -#define RT305X_ESW_PMAP_LLLLLL 0x3f -#define RT305X_ESW_PMAP_LLLLWL 0x2f -#define RT305X_ESW_PMAP_WLLLLL 0x3e - -#define RT305X_ESW_PORTS_INTERNAL \ - (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \ - BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \ - BIT(RT305X_ESW_PORT4)) - -#define RT305X_ESW_PORTS_NOCPU \ - (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5)) - -#define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6) - -#define RT305X_ESW_PORTS_ALL \ - (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU) - -#define RT305X_ESW_NUM_VLANS 16 -#define RT305X_ESW_NUM_VIDS 4096 -#define RT305X_ESW_NUM_PORTS 7 -#define RT305X_ESW_NUM_LANWAN 6 -#define RT305X_ESW_NUM_LEDS 5 - -enum { - /* Global attributes. */ - RT305X_ESW_ATTR_ENABLE_VLAN, - RT305X_ESW_ATTR_ALT_VLAN_DISABLE, - /* Port attributes. */ - RT305X_ESW_ATTR_PORT_DISABLE, - RT305X_ESW_ATTR_PORT_DOUBLETAG, - RT305X_ESW_ATTR_PORT_UNTAG, - RT305X_ESW_ATTR_PORT_LED, - RT305X_ESW_ATTR_PORT_LAN, - RT305X_ESW_ATTR_PORT_RECV_BAD, - RT305X_ESW_ATTR_PORT_RECV_GOOD, -}; - -struct rt305x_esw_port { - bool disable; - bool doubletag; - bool untag; - u8 led; - u16 pvid; -}; - -struct rt305x_esw_vlan { - u8 ports; - u16 vid; -}; - -struct rt305x_esw { - void __iomem *base; - struct rt305x_esw_platform_data *pdata; - /* Protects against concurrent register rmw operations. */ - spinlock_t reg_rw_lock; - - struct switch_dev swdev; - bool global_vlan_enable; - bool alt_vlan_disable; - struct rt305x_esw_vlan vlans[RT305X_ESW_NUM_VLANS]; - struct rt305x_esw_port ports[RT305X_ESW_NUM_PORTS]; - -}; - -static inline void -rt305x_esw_wr(struct rt305x_esw *esw, u32 val, unsigned reg) -{ - __raw_writel(val, esw->base + reg); -} - -static inline u32 -rt305x_esw_rr(struct rt305x_esw *esw, unsigned reg) -{ - return __raw_readl(esw->base + reg); -} - -static inline void -rt305x_esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask, - unsigned long val) -{ - unsigned long t; - - t = __raw_readl(esw->base + reg) & ~mask; - __raw_writel(t | val, esw->base + reg); -} - -static void -rt305x_esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask, - unsigned long val) -{ - unsigned long flags; - - spin_lock_irqsave(&esw->reg_rw_lock, flags); - rt305x_esw_rmw_raw(esw, reg, mask, val); - spin_unlock_irqrestore(&esw->reg_rw_lock, flags); -} - -static u32 -rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register, - u32 write_data) -{ - unsigned long t_start = jiffies; - int ret = 0; - - while (1) { - if (!(rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) & - RT305X_ESW_PCR1_WT_DONE)) - break; - if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) { - ret = 1; - goto out; - } - } - - write_data &= 0xffff; - rt305x_esw_wr(esw, - (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) | - (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) | - (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD, - RT305X_ESW_REG_PCR0); - - t_start = jiffies; - while (1) { - if (rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) & - RT305X_ESW_PCR1_WT_DONE) - break; - - if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) { - ret = 1; - break; - } - } -out: - if (ret) - printk(KERN_ERR "ramips_eth: MDIO timeout\n"); - return ret; -} - -static unsigned -rt305x_esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan) -{ - unsigned s; - unsigned val; - - s = RT305X_ESW_VLANI_VID_S * (vlan % 2); - val = rt305x_esw_rr(esw, RT305X_ESW_REG_VLANI(vlan / 2)); - val = (val >> s) & RT305X_ESW_VLANI_VID_M; - - return val; -} - -static void -rt305x_esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid) -{ - unsigned s; - - s = RT305X_ESW_VLANI_VID_S * (vlan % 2); - rt305x_esw_rmw(esw, - RT305X_ESW_REG_VLANI(vlan / 2), - RT305X_ESW_VLANI_VID_M << s, - (vid & RT305X_ESW_VLANI_VID_M) << s); -} - -static unsigned -rt305x_esw_get_pvid(struct rt305x_esw *esw, unsigned port) -{ - unsigned s, val; - - s = RT305X_ESW_PVIDC_PVID_S * (port % 2); - val = rt305x_esw_rr(esw, RT305X_ESW_REG_PVIDC(port / 2)); - return (val >> s) & RT305X_ESW_PVIDC_PVID_M; -} - -static void -rt305x_esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid) -{ - unsigned s; - - s = RT305X_ESW_PVIDC_PVID_S * (port % 2); - rt305x_esw_rmw(esw, - RT305X_ESW_REG_PVIDC(port / 2), - RT305X_ESW_PVIDC_PVID_M << s, - (pvid & RT305X_ESW_PVIDC_PVID_M) << s); -} - -static unsigned -rt305x_esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan) -{ - unsigned s, val; - - s = RT305X_ESW_VMSC_MSC_S * (vlan % 4); - val = rt305x_esw_rr(esw, RT305X_ESW_REG_VMSC(vlan / 4)); - val = (val >> s) & RT305X_ESW_VMSC_MSC_M; - - return val; -} - -static void -rt305x_esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc) -{ - unsigned s; - - s = RT305X_ESW_VMSC_MSC_S * (vlan % 4); - rt305x_esw_rmw(esw, - RT305X_ESW_REG_VMSC(vlan / 4), - RT305X_ESW_VMSC_MSC_M << s, - (msc & RT305X_ESW_VMSC_MSC_M) << s); -} - -static unsigned -rt305x_esw_get_port_disable(struct rt305x_esw *esw) -{ - unsigned reg; - reg = rt305x_esw_rr(esw, RT305X_ESW_REG_POC0); - return (reg >> RT305X_ESW_POC0_DIS_PORT_S) & - RT305X_ESW_POC0_DIS_PORT_M; -} - -static void -rt305x_esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask) -{ - unsigned old_mask; - unsigned enable_mask; - unsigned changed; - int i; - - old_mask = rt305x_esw_get_port_disable(esw); - changed = old_mask ^ disable_mask; - enable_mask = old_mask & disable_mask; - - /* enable before writing to MII */ - rt305x_esw_rmw(esw, RT305X_ESW_REG_POC0, - (RT305X_ESW_POC0_DIS_PORT_M << - RT305X_ESW_POC0_DIS_PORT_S), - enable_mask << RT305X_ESW_POC0_DIS_PORT_S); - - for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) { - if (!(changed & (1 << i))) - continue; - if (disable_mask & (1 << i)) { - /* disable */ - rt305x_mii_write(esw, i, MII_BMCR, - BMCR_PDOWN); - } else { - /* enable */ - rt305x_mii_write(esw, i, MII_BMCR, - BMCR_FULLDPLX | - BMCR_ANENABLE | - BMCR_ANRESTART | - BMCR_SPEED100); - } - } - - /* disable after writing to MII */ - rt305x_esw_rmw(esw, RT305X_ESW_REG_POC0, - (RT305X_ESW_POC0_DIS_PORT_M << - RT305X_ESW_POC0_DIS_PORT_S), - disable_mask << RT305X_ESW_POC0_DIS_PORT_S); -} - -static int -rt305x_esw_apply_config(struct switch_dev *dev); - -static void -rt305x_esw_hw_init(struct rt305x_esw *esw) -{ - int i; - u8 port_disable = 0; - u8 port_map = RT305X_ESW_PMAP_LLLLLL; - - /* vodoo from original driver */ - rt305x_esw_wr(esw, 0xC8A07850, RT305X_ESW_REG_FCT0); - rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_SGC2); - /* Port priority 1 for all ports, vlan enabled. */ - rt305x_esw_wr(esw, 0x00005555 | - (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S), - RT305X_ESW_REG_PFC1); - - /* Enable Back Pressure, and Flow Control */ - rt305x_esw_wr(esw, - ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) | - (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)), - RT305X_ESW_REG_POC0); - - /* Enable Aging, and VLAN TAG removal */ - rt305x_esw_wr(esw, - ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) | - (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)), - RT305X_ESW_REG_POC2); - - rt305x_esw_wr(esw, esw->pdata->reg_initval_fct2, RT305X_ESW_REG_FCT2); - - /* - * 300s aging timer, max packet len 1536, broadcast storm prevention - * disabled, disable collision abort, mac xor48 hash, 10 packet back - * pressure jam, GMII disable was_transmit, back pressure disabled, - * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all - * ports. - */ - rt305x_esw_wr(esw, 0x0008a301, RT305X_ESW_REG_SGC); - - /* Setup SoC Port control register */ - rt305x_esw_wr(esw, - (RT305X_ESW_SOCPC_CRC_PADDING | - (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) | - (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) | - (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)), - RT305X_ESW_REG_SOCPC); - - rt305x_esw_wr(esw, esw->pdata->reg_initval_fpa2, RT305X_ESW_REG_FPA2); - rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_FPA); - - /* Force Link/Activity on ports */ - rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P0LED); - rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P1LED); - rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P2LED); - rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P3LED); - rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P4LED); - - /* Copy disabled port configuration from bootloader setup */ - port_disable = rt305x_esw_get_port_disable(esw); - for (i = 0; i < 6; i++) - esw->ports[i].disable = (port_disable & (1 << i)) != 0; - - rt305x_mii_write(esw, 0, 31, 0x8000); - for (i = 0; i < 5; i++) { - if (esw->ports[i].disable) { - rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN); - } else { - rt305x_mii_write(esw, i, MII_BMCR, - BMCR_FULLDPLX | - BMCR_ANENABLE | - BMCR_SPEED100); - } - /* TX10 waveform coefficient */ - rt305x_mii_write(esw, i, 26, 0x1601); - /* TX100/TX10 AD/DA current bias */ - rt305x_mii_write(esw, i, 29, 0x7058); - /* TX100 slew rate control */ - rt305x_mii_write(esw, i, 30, 0x0018); - } - - /* PHY IOT */ - /* select global register */ - rt305x_mii_write(esw, 0, 31, 0x0); - /* tune TP_IDL tail and head waveform */ - rt305x_mii_write(esw, 0, 22, 0x052f); - /* set TX10 signal amplitude threshold to minimum */ - rt305x_mii_write(esw, 0, 17, 0x0fe0); - /* set squelch amplitude to higher threshold */ - rt305x_mii_write(esw, 0, 18, 0x40ba); - /* longer TP_IDL tail length */ - rt305x_mii_write(esw, 0, 14, 0x65); - /* select local register */ - rt305x_mii_write(esw, 0, 31, 0x8000); - - switch (esw->pdata->vlan_config) { - case RT305X_ESW_VLAN_CONFIG_NONE: - port_map = RT305X_ESW_PMAP_LLLLLL; - break; - case RT305X_ESW_VLAN_CONFIG_LLLLW: - port_map = RT305X_ESW_PMAP_LLLLWL; - break; - case RT305X_ESW_VLAN_CONFIG_WLLLL: - port_map = RT305X_ESW_PMAP_WLLLLL; - break; - default: - BUG(); - } - - /* - * Unused HW feature, but still nice to be consistent here... - * This is also exported to userspace ('lan' attribute) so it's - * conveniently usable to decide which ports go into the wan vlan by - * default. - */ - rt305x_esw_rmw(esw, RT305X_ESW_REG_SGC2, - RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S, - port_map << RT305X_ESW_SGC2_LAN_PMAP_S); - - /* make the switch leds blink */ - for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) - esw->ports[i].led = 0x05; - - /* Apply the empty config. */ - rt305x_esw_apply_config(&esw->swdev); -} - -static int -rt305x_esw_apply_config(struct switch_dev *dev) -{ - struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); - int i; - u8 disable = 0; - u8 doubletag = 0; - u8 en_vlan = 0; - u8 untag = 0; - - for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) { - u32 vid, vmsc; - if (esw->global_vlan_enable) { - vid = esw->vlans[i].vid; - vmsc = esw->vlans[i].ports; - } else { - vid = RT305X_ESW_VLAN_NONE; - vmsc = RT305X_ESW_PORTS_NONE; - } - rt305x_esw_set_vlan_id(esw, i, vid); - rt305x_esw_set_vmsc(esw, i, vmsc); - } - - for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) { - u32 pvid; - disable |= esw->ports[i].disable << i; - if (esw->global_vlan_enable) { - doubletag |= esw->ports[i].doubletag << i; - en_vlan |= 1 << i; - untag |= esw->ports[i].untag << i; - pvid = esw->ports[i].pvid; - } else { - int x = esw->alt_vlan_disable ? 0 : 1; - doubletag |= x << i; - en_vlan |= x << i; - untag |= x << i; - pvid = 0; - } - rt305x_esw_set_pvid(esw, i, pvid); - if (i < RT305X_ESW_NUM_LEDS) - rt305x_esw_wr(esw, esw->ports[i].led, - RT305X_ESW_REG_P0LED + 4*i); - } - - rt305x_esw_set_port_disable(esw, disable); - rt305x_esw_rmw(esw, RT305X_ESW_REG_SGC2, - (RT305X_ESW_SGC2_DOUBLE_TAG_M << - RT305X_ESW_SGC2_DOUBLE_TAG_S), - doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S); - rt305x_esw_rmw(esw, RT305X_ESW_REG_PFC1, - RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S, - en_vlan << RT305X_ESW_PFC1_EN_VLAN_S); - rt305x_esw_rmw(esw, RT305X_ESW_REG_POC2, - RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S, - untag << RT305X_ESW_POC2_UNTAG_EN_S); - - if (!esw->global_vlan_enable) { - /* - * Still need to put all ports into vlan 0 or they'll be - * isolated. - * NOTE: vlan 0 is special, no vlan tag is prepended - */ - rt305x_esw_set_vlan_id(esw, 0, 0); - rt305x_esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL); - } - - return 0; -} - -static int -rt305x_esw_reset_switch(struct switch_dev *dev) -{ - struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); - esw->global_vlan_enable = 0; - memset(esw->ports, 0, sizeof(esw->ports)); - memset(esw->vlans, 0, sizeof(esw->vlans)); - rt305x_esw_hw_init(esw); - - return 0; -} - -static int -rt305x_esw_get_vlan_enable(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val) -{ - struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); - - val->value.i = esw->global_vlan_enable; - - return 0; -} - -static int -rt305x_esw_set_vlan_enable(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val) -{ - struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); - - esw->global_vlan_enable = val->value.i != 0; - - return 0; -} - -static int -rt305x_esw_get_alt_vlan_disable(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val) -{ - struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); - - val->value.i = esw->alt_vlan_disable; - - return 0; -} - -static int -rt305x_esw_set_alt_vlan_disable(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val) -{ - struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); - - esw->alt_vlan_disable = val->value.i != 0; - - return 0; -} - -static int -rt305x_esw_get_port_link(struct switch_dev *dev, - int port, - struct switch_port_link *link) -{ - struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); - u32 speed, poa; - - if (port < 0 || port >= RT305X_ESW_NUM_PORTS) - return -EINVAL; - - poa = rt305x_esw_rr(esw, RT305X_ESW_REG_POA) >> port; - - link->link = (poa >> RT305X_ESW_LINK_S) & 1; - link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1; - if (port < RT305X_ESW_NUM_LEDS) { - speed = (poa >> RT305X_ESW_SPD_S) & 1; - } else { - if (port == RT305X_ESW_NUM_PORTS - 1) - poa >>= 1; - speed = (poa >> RT305X_ESW_SPD_S) & 3; - } - switch (speed) { - case 0: - link->speed = SWITCH_PORT_SPEED_10; - break; - case 1: - link->speed = SWITCH_PORT_SPEED_100; - break; - case 2: - case 3: /* forced gige speed can be 2 or 3 */ - link->speed = SWITCH_PORT_SPEED_1000; - break; - default: - link->speed = SWITCH_PORT_SPEED_UNKNOWN; - break; - } - - return 0; -} - -static int -rt305x_esw_get_port_bool(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val) -{ - struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); - int idx = val->port_vlan; - u32 x, reg, shift; - - if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS) - return -EINVAL; - - switch (attr->id) { - case RT305X_ESW_ATTR_PORT_DISABLE: - reg = RT305X_ESW_REG_POC0; - shift = RT305X_ESW_POC0_DIS_PORT_S; - break; - case RT305X_ESW_ATTR_PORT_DOUBLETAG: - reg = RT305X_ESW_REG_SGC2; - shift = RT305X_ESW_SGC2_DOUBLE_TAG_S; - break; - case RT305X_ESW_ATTR_PORT_UNTAG: - reg = RT305X_ESW_REG_POC2; - shift = RT305X_ESW_POC2_UNTAG_EN_S; - break; - case RT305X_ESW_ATTR_PORT_LAN: - reg = RT305X_ESW_REG_SGC2; - shift = RT305X_ESW_SGC2_LAN_PMAP_S; - if (idx >= RT305X_ESW_NUM_LANWAN) - return -EINVAL; - break; - default: - return -EINVAL; - } - - x = rt305x_esw_rr(esw, reg); - val->value.i = (x >> (idx + shift)) & 1; - - return 0; -} - -static int -rt305x_esw_set_port_bool(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val) -{ - struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); - int idx = val->port_vlan; - - if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS || - val->value.i < 0 || val->value.i > 1) - return -EINVAL; - - switch (attr->id) { - case RT305X_ESW_ATTR_PORT_DISABLE: - esw->ports[idx].disable = val->value.i; - break; - case RT305X_ESW_ATTR_PORT_DOUBLETAG: - esw->ports[idx].doubletag = val->value.i; - break; - case RT305X_ESW_ATTR_PORT_UNTAG: - esw->ports[idx].untag = val->value.i; - break; - default: - return -EINVAL; - } - - return 0; -} - -static int -rt305x_esw_get_port_recv_badgood(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val) -{ - struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); - int idx = val->port_vlan; - int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16; - u32 reg; - - if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN) - return -EINVAL; - - reg = rt305x_esw_rr(esw, RT305X_ESW_REG_P0PC + 4*idx); - val->value.i = (reg >> shift) & 0xffff; - - return 0; -} - -static int -rt305x_esw_get_port_led(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val) -{ - struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); - int idx = val->port_vlan; - - if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS || - idx >= RT305X_ESW_NUM_LEDS) - return -EINVAL; - - val->value.i = rt305x_esw_rr(esw, RT305X_ESW_REG_P0LED + 4*idx); - - return 0; -} - -static int -rt305x_esw_set_port_led(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val) -{ - struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); - int idx = val->port_vlan; - - if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS) - return -EINVAL; - - esw->ports[idx].led = val->value.i; - - return 0; -} - -static int -rt305x_esw_get_port_pvid(struct switch_dev *dev, int port, int *val) -{ - struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); - - if (port >= RT305X_ESW_NUM_PORTS) - return -EINVAL; - - *val = rt305x_esw_get_pvid(esw, port); - - return 0; -} - -static int -rt305x_esw_set_port_pvid(struct switch_dev *dev, int port, int val) -{ - struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); - - if (port >= RT305X_ESW_NUM_PORTS) - return -EINVAL; - - esw->ports[port].pvid = val; - - return 0; -} - -static int -rt305x_esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val) -{ - struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); - u32 vmsc, poc2; - int vlan_idx = -1; - int i; - - val->len = 0; - - if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS) - return -EINVAL; - - /* valid vlan? */ - for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) { - if (rt305x_esw_get_vlan_id(esw, i) == val->port_vlan && - rt305x_esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) { - vlan_idx = i; - break; - } - } - - if (vlan_idx == -1) - return -EINVAL; - - vmsc = rt305x_esw_get_vmsc(esw, vlan_idx); - poc2 = rt305x_esw_rr(esw, RT305X_ESW_REG_POC2); - - for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) { - struct switch_port *p; - int port_mask = 1 << i; - - if (!(vmsc & port_mask)) - continue; - - p = &val->value.ports[val->len++]; - p->id = i; - if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S)) - p->flags = 0; - else - p->flags = 1 << SWITCH_PORT_FLAG_TAGGED; - } - - return 0; -} - -static int -rt305x_esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val) -{ - struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); - int ports; - int vlan_idx = -1; - int i; - - if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS || - val->len > RT305X_ESW_NUM_PORTS) - return -EINVAL; - - /* one of the already defined vlans? */ - for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) { - if (esw->vlans[i].vid == val->port_vlan && - esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) { - vlan_idx = i; - break; - } - } - - /* select a free slot */ - for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) { - if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE) - vlan_idx = i; - } - - /* bail if all slots are in use */ - if (vlan_idx == -1) - return -EINVAL; - - ports = RT305X_ESW_PORTS_NONE; - for (i = 0; i < val->len; i++) { - struct switch_port *p = &val->value.ports[i]; - int port_mask = 1 << p->id; - bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)); - - if (p->id >= RT305X_ESW_NUM_PORTS) - return -EINVAL; - - ports |= port_mask; - esw->ports[p->id].untag = untagged; - } - esw->vlans[vlan_idx].ports = ports; - if (ports == RT305X_ESW_PORTS_NONE) - esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE; - else - esw->vlans[vlan_idx].vid = val->port_vlan; - - return 0; -} - -static const struct switch_attr rt305x_esw_global[] = { - { - .type = SWITCH_TYPE_INT, - .name = "enable_vlan", - .description = "VLAN mode (1:enabled)", - .max = 1, - .id = RT305X_ESW_ATTR_ENABLE_VLAN, - .get = rt305x_esw_get_vlan_enable, - .set = rt305x_esw_set_vlan_enable, - }, - { - .type = SWITCH_TYPE_INT, - .name = "alternate_vlan_disable", - .description = "Use en_vlan instead of doubletag to disable" - " VLAN mode", - .max = 1, - .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE, - .get = rt305x_esw_get_alt_vlan_disable, - .set = rt305x_esw_set_alt_vlan_disable, - }, -}; - -static const struct switch_attr rt305x_esw_port[] = { - { - .type = SWITCH_TYPE_INT, - .name = "disable", - .description = "Port state (1:disabled)", - .max = 1, - .id = RT305X_ESW_ATTR_PORT_DISABLE, - .get = rt305x_esw_get_port_bool, - .set = rt305x_esw_set_port_bool, - }, - { - .type = SWITCH_TYPE_INT, - .name = "doubletag", - .description = "Double tagging for incoming vlan packets " - "(1:enabled)", - .max = 1, - .id = RT305X_ESW_ATTR_PORT_DOUBLETAG, - .get = rt305x_esw_get_port_bool, - .set = rt305x_esw_set_port_bool, - }, - { - .type = SWITCH_TYPE_INT, - .name = "untag", - .description = "Untag (1:strip outgoing vlan tag)", - .max = 1, - .id = RT305X_ESW_ATTR_PORT_UNTAG, - .get = rt305x_esw_get_port_bool, - .set = rt305x_esw_set_port_bool, - }, - { - .type = SWITCH_TYPE_INT, - .name = "led", - .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity," - " 4:collision, 5:linkact, 6:duplcoll, 7:10mact," - " 8:100mact, 10:blink, 12:on)", - .max = 15, - .id = RT305X_ESW_ATTR_PORT_LED, - .get = rt305x_esw_get_port_led, - .set = rt305x_esw_set_port_led, - }, - { - .type = SWITCH_TYPE_INT, - .name = "lan", - .description = "HW port group (0:wan, 1:lan)", - .max = 1, - .id = RT305X_ESW_ATTR_PORT_LAN, - .get = rt305x_esw_get_port_bool, - }, - { - .type = SWITCH_TYPE_INT, - .name = "recv_bad", - .description = "Receive bad packet counter", - .id = RT305X_ESW_ATTR_PORT_RECV_BAD, - .get = rt305x_esw_get_port_recv_badgood, - }, - { - .type = SWITCH_TYPE_INT, - .name = "recv_good", - .description = "Receive good packet counter", - .id = RT305X_ESW_ATTR_PORT_RECV_GOOD, - .get = rt305x_esw_get_port_recv_badgood, - }, -}; - -static const struct switch_attr rt305x_esw_vlan[] = { -}; - -static const struct switch_dev_ops rt305x_esw_ops = { - .attr_global = { - .attr = rt305x_esw_global, - .n_attr = ARRAY_SIZE(rt305x_esw_global), - }, - .attr_port = { - .attr = rt305x_esw_port, - .n_attr = ARRAY_SIZE(rt305x_esw_port), - }, - .attr_vlan = { - .attr = rt305x_esw_vlan, - .n_attr = ARRAY_SIZE(rt305x_esw_vlan), - }, - .get_vlan_ports = rt305x_esw_get_vlan_ports, - .set_vlan_ports = rt305x_esw_set_vlan_ports, - .get_port_pvid = rt305x_esw_get_port_pvid, - .set_port_pvid = rt305x_esw_set_port_pvid, - .get_port_link = rt305x_esw_get_port_link, - .apply_config = rt305x_esw_apply_config, - .reset_switch = rt305x_esw_reset_switch, -}; - -static int -rt305x_esw_probe(struct platform_device *pdev) -{ - struct rt305x_esw_platform_data *pdata; - struct rt305x_esw *esw; - struct switch_dev *swdev; - struct resource *res; - int err; - - pdata = pdev->dev.platform_data; - if (!pdata) - return -EINVAL; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(&pdev->dev, "no memory resource found\n"); - return -ENOMEM; - } - - esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL); - if (!esw) { - dev_err(&pdev->dev, "no memory for private data\n"); - return -ENOMEM; - } - - esw->base = ioremap(res->start, resource_size(res)); - if (!esw->base) { - dev_err(&pdev->dev, "ioremap failed\n"); - err = -ENOMEM; - goto free_esw; - } - - swdev = &esw->swdev; - swdev->name = "rt305x-esw"; - swdev->alias = "rt305x"; - swdev->cpu_port = RT305X_ESW_PORT6; - swdev->ports = RT305X_ESW_NUM_PORTS; - swdev->vlans = RT305X_ESW_NUM_VIDS; - swdev->ops = &rt305x_esw_ops; - - err = register_switch(swdev, NULL); - if (err < 0) { - dev_err(&pdev->dev, "register_switch failed\n"); - goto unmap_base; - } - - platform_set_drvdata(pdev, esw); - - esw->pdata = pdata; - spin_lock_init(&esw->reg_rw_lock); - rt305x_esw_hw_init(esw); - - return 0; - -unmap_base: - iounmap(esw->base); -free_esw: - kfree(esw); - return err; -} - -static int -rt305x_esw_remove(struct platform_device *pdev) -{ - struct rt305x_esw *esw; - - esw = platform_get_drvdata(pdev); - if (esw) { - unregister_switch(&esw->swdev); - platform_set_drvdata(pdev, NULL); - iounmap(esw->base); - kfree(esw); - } - - return 0; -} - -static struct platform_driver rt305x_esw_driver = { - .probe = rt305x_esw_probe, - .remove = rt305x_esw_remove, - .driver = { - .name = "rt305x-esw", - .owner = THIS_MODULE, - }, -}; - -static int __init -rt305x_esw_init(void) -{ - return platform_driver_register(&rt305x_esw_driver); -} - -static void -rt305x_esw_exit(void) -{ - platform_driver_unregister(&rt305x_esw_driver); -} diff --git a/target/linux/ramips/files/drivers/net/ethernet/ramips/ramips_eth.h b/target/linux/ramips/files/drivers/net/ethernet/ramips/ramips_eth.h deleted file mode 100644 index 66187030b9..0000000000 --- a/target/linux/ramips/files/drivers/net/ethernet/ramips/ramips_eth.h +++ /dev/null @@ -1,358 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * based on Ralink SDK3.3 - * Copyright (C) 2009 John Crispin - */ - -#ifndef RAMIPS_ETH_H -#define RAMIPS_ETH_H - -#include -#include -#include -#include - -#define NUM_RX_DESC 256 -#define NUM_TX_DESC 256 - -#define RAMIPS_DELAY_EN_INT 0x80 -#define RAMIPS_DELAY_MAX_INT 0x04 -#define RAMIPS_DELAY_MAX_TOUT 0x04 -#define RAMIPS_DELAY_CHAN (((RAMIPS_DELAY_EN_INT | RAMIPS_DELAY_MAX_INT) << 8) | RAMIPS_DELAY_MAX_TOUT) -#define RAMIPS_DELAY_INIT ((RAMIPS_DELAY_CHAN << 16) | RAMIPS_DELAY_CHAN) -#define RAMIPS_PSE_FQFC_CFG_INIT 0x80504000 - -/* interrupt bits */ -#define RAMIPS_CNT_PPE_AF BIT(31) -#define RAMIPS_CNT_GDM_AF BIT(29) -#define RAMIPS_PSE_P2_FC BIT(26) -#define RAMIPS_PSE_BUF_DROP BIT(24) -#define RAMIPS_GDM_OTHER_DROP BIT(23) -#define RAMIPS_PSE_P1_FC BIT(22) -#define RAMIPS_PSE_P0_FC BIT(21) -#define RAMIPS_PSE_FQ_EMPTY BIT(20) -#define RAMIPS_GE1_STA_CHG BIT(18) -#define RAMIPS_TX_COHERENT BIT(17) -#define RAMIPS_RX_COHERENT BIT(16) -#define RAMIPS_TX_DONE_INT3 BIT(11) -#define RAMIPS_TX_DONE_INT2 BIT(10) -#define RAMIPS_TX_DONE_INT1 BIT(9) -#define RAMIPS_TX_DONE_INT0 BIT(8) -#define RAMIPS_RX_DONE_INT0 BIT(2) -#define RAMIPS_TX_DLY_INT BIT(1) -#define RAMIPS_RX_DLY_INT BIT(0) - -#define RT5350_RX_DLY_INT BIT(30) -#define RT5350_TX_DLY_INT BIT(28) - -/* registers */ -#define RAMIPS_FE_OFFSET 0x0000 -#define RAMIPS_GDMA_OFFSET 0x0020 -#define RAMIPS_PSE_OFFSET 0x0040 -#define RAMIPS_GDMA2_OFFSET 0x0060 -#define RAMIPS_CDMA_OFFSET 0x0080 -#define RAMIPS_PDMA_OFFSET 0x0100 -#define RAMIPS_PPE_OFFSET 0x0200 -#define RAMIPS_CMTABLE_OFFSET 0x0400 -#define RAMIPS_POLICYTABLE_OFFSET 0x1000 - -#define RT5350_PDMA_OFFSET 0x0800 -#define RT5350_SDM_OFFSET 0x0c00 - -#define RAMIPS_MDIO_ACCESS (RAMIPS_FE_OFFSET + 0x00) -#define RAMIPS_MDIO_CFG (RAMIPS_FE_OFFSET + 0x04) -#define RAMIPS_FE_GLO_CFG (RAMIPS_FE_OFFSET + 0x08) -#define RAMIPS_FE_RST_GL (RAMIPS_FE_OFFSET + 0x0C) -#define RAMIPS_FE_INT_STATUS (RAMIPS_FE_OFFSET + 0x10) -#define RAMIPS_FE_INT_ENABLE (RAMIPS_FE_OFFSET + 0x14) -#define RAMIPS_MDIO_CFG2 (RAMIPS_FE_OFFSET + 0x18) -#define RAMIPS_FOC_TS_T (RAMIPS_FE_OFFSET + 0x1C) - -#define RAMIPS_GDMA1_FWD_CFG (RAMIPS_GDMA_OFFSET + 0x00) -#define RAMIPS_GDMA1_SCH_CFG (RAMIPS_GDMA_OFFSET + 0x04) -#define RAMIPS_GDMA1_SHPR_CFG (RAMIPS_GDMA_OFFSET + 0x08) -#define RAMIPS_GDMA1_MAC_ADRL (RAMIPS_GDMA_OFFSET + 0x0C) -#define RAMIPS_GDMA1_MAC_ADRH (RAMIPS_GDMA_OFFSET + 0x10) - -#define RAMIPS_GDMA2_FWD_CFG (RAMIPS_GDMA2_OFFSET + 0x00) -#define RAMIPS_GDMA2_SCH_CFG (RAMIPS_GDMA2_OFFSET + 0x04) -#define RAMIPS_GDMA2_SHPR_CFG (RAMIPS_GDMA2_OFFSET + 0x08) -#define RAMIPS_GDMA2_MAC_ADRL (RAMIPS_GDMA2_OFFSET + 0x0C) -#define RAMIPS_GDMA2_MAC_ADRH (RAMIPS_GDMA2_OFFSET + 0x10) - -#define RAMIPS_PSE_FQ_CFG (RAMIPS_PSE_OFFSET + 0x00) -#define RAMIPS_CDMA_FC_CFG (RAMIPS_PSE_OFFSET + 0x04) -#define RAMIPS_GDMA1_FC_CFG (RAMIPS_PSE_OFFSET + 0x08) -#define RAMIPS_GDMA2_FC_CFG (RAMIPS_PSE_OFFSET + 0x0C) - -#define RAMIPS_CDMA_CSG_CFG (RAMIPS_CDMA_OFFSET + 0x00) -#define RAMIPS_CDMA_SCH_CFG (RAMIPS_CDMA_OFFSET + 0x04) - -#define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00) -#define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04) -#define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08) -#define RT5350_TX_DTX_IDX0 (RT5350_PDMA_OFFSET + 0x0C) -#define RT5350_TX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x10) -#define RT5350_TX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x14) -#define RT5350_TX_CTX_IDX1 (RT5350_PDMA_OFFSET + 0x18) -#define RT5350_TX_DTX_IDX1 (RT5350_PDMA_OFFSET + 0x1C) -#define RT5350_TX_BASE_PTR2 (RT5350_PDMA_OFFSET + 0x20) -#define RT5350_TX_MAX_CNT2 (RT5350_PDMA_OFFSET + 0x24) -#define RT5350_TX_CTX_IDX2 (RT5350_PDMA_OFFSET + 0x28) -#define RT5350_TX_DTX_IDX2 (RT5350_PDMA_OFFSET + 0x2C) -#define RT5350_TX_BASE_PTR3 (RT5350_PDMA_OFFSET + 0x30) -#define RT5350_TX_MAX_CNT3 (RT5350_PDMA_OFFSET + 0x34) -#define RT5350_TX_CTX_IDX3 (RT5350_PDMA_OFFSET + 0x38) -#define RT5350_TX_DTX_IDX3 (RT5350_PDMA_OFFSET + 0x3C) -#define RT5350_RX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x100) -#define RT5350_RX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x104) -#define RT5350_RX_CALC_IDX0 (RT5350_PDMA_OFFSET + 0x108) -#define RT5350_RX_DRX_IDX0 (RT5350_PDMA_OFFSET + 0x10C) -#define RT5350_RX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x110) -#define RT5350_RX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x114) -#define RT5350_RX_CALC_IDX1 (RT5350_PDMA_OFFSET + 0x118) -#define RT5350_RX_DRX_IDX1 (RT5350_PDMA_OFFSET + 0x11C) -#define RT5350_PDMA_GLO_CFG (RT5350_PDMA_OFFSET + 0x204) -#define RT5350_PDMA_RST_CFG (RT5350_PDMA_OFFSET + 0x208) -#define RT5350_DLY_INT_CFG (RT5350_PDMA_OFFSET + 0x20c) -#define RT5350_FE_INT_STATUS (RT5350_PDMA_OFFSET + 0x220) -#define RT5350_FE_INT_ENABLE (RT5350_PDMA_OFFSET + 0x228) -#define RT5350_PDMA_SCH_CFG (RT5350_PDMA_OFFSET + 0x280) - - -#define RAMIPS_PDMA_GLO_CFG (RAMIPS_PDMA_OFFSET + 0x00) -#define RAMIPS_PDMA_RST_CFG (RAMIPS_PDMA_OFFSET + 0x04) -#define RAMIPS_PDMA_SCH_CFG (RAMIPS_PDMA_OFFSET + 0x08) -#define RAMIPS_DLY_INT_CFG (RAMIPS_PDMA_OFFSET + 0x0C) -#define RAMIPS_TX_BASE_PTR0 (RAMIPS_PDMA_OFFSET + 0x10) -#define RAMIPS_TX_MAX_CNT0 (RAMIPS_PDMA_OFFSET + 0x14) -#define RAMIPS_TX_CTX_IDX0 (RAMIPS_PDMA_OFFSET + 0x18) -#define RAMIPS_TX_DTX_IDX0 (RAMIPS_PDMA_OFFSET + 0x1C) -#define RAMIPS_TX_BASE_PTR1 (RAMIPS_PDMA_OFFSET + 0x20) -#define RAMIPS_TX_MAX_CNT1 (RAMIPS_PDMA_OFFSET + 0x24) -#define RAMIPS_TX_CTX_IDX1 (RAMIPS_PDMA_OFFSET + 0x28) -#define RAMIPS_TX_DTX_IDX1 (RAMIPS_PDMA_OFFSET + 0x2C) -#define RAMIPS_RX_BASE_PTR0 (RAMIPS_PDMA_OFFSET + 0x30) -#define RAMIPS_RX_MAX_CNT0 (RAMIPS_PDMA_OFFSET + 0x34) -#define RAMIPS_RX_CALC_IDX0 (RAMIPS_PDMA_OFFSET + 0x38) -#define RAMIPS_RX_DRX_IDX0 (RAMIPS_PDMA_OFFSET + 0x3C) -#define RAMIPS_TX_BASE_PTR2 (RAMIPS_PDMA_OFFSET + 0x40) -#define RAMIPS_TX_MAX_CNT2 (RAMIPS_PDMA_OFFSET + 0x44) -#define RAMIPS_TX_CTX_IDX2 (RAMIPS_PDMA_OFFSET + 0x48) -#define RAMIPS_TX_DTX_IDX2 (RAMIPS_PDMA_OFFSET + 0x4C) -#define RAMIPS_TX_BASE_PTR3 (RAMIPS_PDMA_OFFSET + 0x50) -#define RAMIPS_TX_MAX_CNT3 (RAMIPS_PDMA_OFFSET + 0x54) -#define RAMIPS_TX_CTX_IDX3 (RAMIPS_PDMA_OFFSET + 0x58) -#define RAMIPS_TX_DTX_IDX3 (RAMIPS_PDMA_OFFSET + 0x5C) -#define RAMIPS_RX_BASE_PTR1 (RAMIPS_PDMA_OFFSET + 0x60) -#define RAMIPS_RX_MAX_CNT1 (RAMIPS_PDMA_OFFSET + 0x64) -#define RAMIPS_RX_CALC_IDX1 (RAMIPS_PDMA_OFFSET + 0x68) -#define RAMIPS_RX_DRX_IDX1 (RAMIPS_PDMA_OFFSET + 0x6C) - -#define RT5350_SDM_CFG (RT5350_SDM_OFFSET + 0x00) //Switch DMA configuration -#define RT5350_SDM_RRING (RT5350_SDM_OFFSET + 0x04) //Switch DMA Rx Ring -#define RT5350_SDM_TRING (RT5350_SDM_OFFSET + 0x08) //Switch DMA Tx Ring -#define RT5350_SDM_MAC_ADRL (RT5350_SDM_OFFSET + 0x0C) //Switch MAC address LSB -#define RT5350_SDM_MAC_ADRH (RT5350_SDM_OFFSET + 0x10) //Switch MAC Address MSB -#define RT5350_SDM_TPCNT (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count -#define RT5350_SDM_TBCNT (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count -#define RT5350_SDM_RPCNT (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count -#define RT5350_SDM_RBCNT (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count -#define RT5350_SDM_CS_ERR (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count - -#define RT5350_SDM_ICS_EN BIT(16) -#define RT5350_SDM_TCS_EN BIT(17) -#define RT5350_SDM_UCS_EN BIT(18) - - -/* MDIO_CFG register bits */ -#define RAMIPS_MDIO_CFG_AUTO_POLL_EN BIT(29) -#define RAMIPS_MDIO_CFG_GP1_BP_EN BIT(16) -#define RAMIPS_MDIO_CFG_GP1_FRC_EN BIT(15) -#define RAMIPS_MDIO_CFG_GP1_SPEED_10 (0 << 13) -#define RAMIPS_MDIO_CFG_GP1_SPEED_100 (1 << 13) -#define RAMIPS_MDIO_CFG_GP1_SPEED_1000 (2 << 13) -#define RAMIPS_MDIO_CFG_GP1_DUPLEX BIT(12) -#define RAMIPS_MDIO_CFG_GP1_FC_TX BIT(11) -#define RAMIPS_MDIO_CFG_GP1_FC_RX BIT(10) -#define RAMIPS_MDIO_CFG_GP1_LNK_DWN BIT(9) -#define RAMIPS_MDIO_CFG_GP1_AN_FAIL BIT(8) -#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6) -#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6) -#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6) -#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6) -#define RAMIPS_MDIO_CFG_TURBO_MII_FREQ BIT(5) -#define RAMIPS_MDIO_CFG_TURBO_MII_MODE BIT(4) -#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2) -#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2) -#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2) -#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2) -#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_0 0 -#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_200 1 -#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_400 2 -#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_INV 3 - -/* uni-cast port */ -#define RAMIPS_GDM1_ICS_EN BIT(22) -#define RAMIPS_GDM1_TCS_EN BIT(21) -#define RAMIPS_GDM1_UCS_EN BIT(20) -#define RAMIPS_GDM1_JMB_EN BIT(19) -#define RAMIPS_GDM1_STRPCRC BIT(16) -#define RAMIPS_GDM1_UFRC_P_CPU (0 << 12) -#define RAMIPS_GDM1_UFRC_P_GDMA1 (1 << 12) -#define RAMIPS_GDM1_UFRC_P_PPE (6 << 12) - -/* checksums */ -#define RAMIPS_ICS_GEN_EN BIT(2) -#define RAMIPS_UCS_GEN_EN BIT(1) -#define RAMIPS_TCS_GEN_EN BIT(0) - -/* dma ring */ -#define RAMIPS_PST_DRX_IDX0 BIT(16) -#define RAMIPS_PST_DTX_IDX3 BIT(3) -#define RAMIPS_PST_DTX_IDX2 BIT(2) -#define RAMIPS_PST_DTX_IDX1 BIT(1) -#define RAMIPS_PST_DTX_IDX0 BIT(0) - -#define RAMIPS_TX_WB_DDONE BIT(6) -#define RAMIPS_RX_DMA_BUSY BIT(3) -#define RAMIPS_TX_DMA_BUSY BIT(1) -#define RAMIPS_RX_DMA_EN BIT(2) -#define RAMIPS_TX_DMA_EN BIT(0) - -#define RAMIPS_PDMA_SIZE_4DWORDS (0 << 4) -#define RAMIPS_PDMA_SIZE_8DWORDS (1 << 4) -#define RAMIPS_PDMA_SIZE_16DWORDS (2 << 4) - -#define RAMIPS_US_CYC_CNT_MASK 0xff -#define RAMIPS_US_CYC_CNT_SHIFT 0x8 -#define RAMIPS_US_CYC_CNT_DIVISOR 1000000 - -#define RX_DMA_PLEN0(_x) (((_x) >> 16) & 0x3fff) -#define RX_DMA_LSO BIT(30) -#define RX_DMA_DONE BIT(31) - -struct ramips_rx_dma { - unsigned int rxd1; - unsigned int rxd2; - unsigned int rxd3; - unsigned int rxd4; -} __packed __aligned(4); - -#define TX_DMA_PLEN0_MASK ((0x3fff) << 16) -#define TX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) -#define TX_DMA_LSO BIT(30) -#define TX_DMA_DONE BIT(31) -#define TX_DMA_QN(_x) ((_x) << 16) -#define TX_DMA_PN(_x) ((_x) << 24) -#define TX_DMA_QN_MASK TX_DMA_QN(0x7) -#define TX_DMA_PN_MASK TX_DMA_PN(0x7) - -struct ramips_tx_dma { - unsigned int txd1; - unsigned int txd2; - unsigned int txd3; - unsigned int txd4; -} __packed __aligned(4); - -struct raeth_tx_info { - struct ramips_tx_dma *tx_desc; - struct sk_buff *tx_skb; -}; - -struct raeth_rx_info { - struct ramips_rx_dma *rx_desc; - struct sk_buff *rx_skb; - dma_addr_t rx_dma; - unsigned int pad; -}; - -struct raeth_int_stats { - unsigned long rx_delayed; - unsigned long tx_delayed; - unsigned long rx_done0; - unsigned long tx_done0; - unsigned long tx_done1; - unsigned long tx_done2; - unsigned long tx_done3; - unsigned long rx_coherent; - unsigned long tx_coherent; - - unsigned long pse_fq_empty; - unsigned long pse_p0_fc; - unsigned long pse_p1_fc; - unsigned long pse_p2_fc; - unsigned long pse_buf_drop; - - unsigned long total; -}; - -struct raeth_debug { - struct dentry *debugfs_dir; - - struct raeth_int_stats int_stats; -}; - -struct raeth_priv -{ - struct raeth_rx_info *rx_info; - dma_addr_t rx_desc_dma; - struct tasklet_struct rx_tasklet; - struct ramips_rx_dma *rx; - - struct raeth_tx_info *tx_info; - dma_addr_t tx_desc_dma; - struct tasklet_struct tx_housekeeping_tasklet; - struct ramips_tx_dma *tx; - - unsigned int skb_free_idx; - - spinlock_t page_lock; - struct net_device *netdev; - struct device *parent; - struct ramips_eth_platform_data *plat; - - int link; - int speed; - int duplex; - int tx_fc; - int rx_fc; - - struct mii_bus *mii_bus; - int mii_irq[PHY_MAX_ADDR]; - struct phy_device *phy_dev; - spinlock_t phy_lock; - -#ifdef CONFIG_NET_RAMIPS_DEBUG_FS - struct raeth_debug debug; -#endif -}; - -#ifdef CONFIG_NET_RAMIPS_DEBUG_FS -int raeth_debugfs_root_init(void); -void raeth_debugfs_root_exit(void); -int raeth_debugfs_init(struct raeth_priv *re); -void raeth_debugfs_exit(struct raeth_priv *re); -void raeth_debugfs_update_int_stats(struct raeth_priv *re, u32 status); -#else -static inline int raeth_debugfs_root_init(void) { return 0; } -static inline void raeth_debugfs_root_exit(void) {} -static inline int raeth_debugfs_init(struct raeth_priv *re) { return 0; } -static inline void raeth_debugfs_exit(struct raeth_priv *re) {} -static inline void raeth_debugfs_update_int_stats(struct raeth_priv *re, - u32 status) {} -#endif /* CONFIG_NET_RAMIPS_DEBUG_FS */ - -#endif /* RAMIPS_ETH_H */ diff --git a/target/linux/ramips/files/drivers/net/ethernet/ramips/ramips_main.c b/target/linux/ramips/files/drivers/net/ethernet/ramips/ramips_main.c deleted file mode 100644 index 267860ff0f..0000000000 --- a/target/linux/ramips/files/drivers/net/ethernet/ramips/ramips_main.c +++ /dev/null @@ -1,1212 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2009 John Crispin - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include "ramips_eth.h" - -#define TX_TIMEOUT (20 * HZ / 100) -#define MAX_RX_LENGTH 1600 - -#ifdef CONFIG_RALINK_RT305X -#include -#include "ramips_esw.c" -#else -static inline int rt305x_esw_init(void) { return 0; } -static inline void rt305x_esw_exit(void) { } -static inline int soc_is_rt5350(void) { return 0; } -#endif - -#define phys_to_bus(a) (a & 0x1FFFFFFF) - -#ifdef CONFIG_NET_RAMIPS_DEBUG -#define RADEBUG(fmt, args...) printk(KERN_DEBUG fmt, ## args) -#else -#define RADEBUG(fmt, args...) do {} while (0) -#endif - -#define RX_DLY_INT ((soc_is_rt5350())?(RT5350_RX_DLY_INT):(RAMIPS_RX_DLY_INT)) -#define TX_DLY_INT ((soc_is_rt5350())?(RT5350_TX_DLY_INT):(RAMIPS_TX_DLY_INT)) - -enum raeth_reg { - RAETH_REG_PDMA_GLO_CFG = 0, - RAETH_REG_PDMA_RST_CFG, - RAETH_REG_DLY_INT_CFG, - RAETH_REG_TX_BASE_PTR0, - RAETH_REG_TX_MAX_CNT0, - RAETH_REG_TX_CTX_IDX0, - RAETH_REG_RX_BASE_PTR0, - RAETH_REG_RX_MAX_CNT0, - RAETH_REG_RX_CALC_IDX0, - RAETH_REG_FE_INT_ENABLE, - RAETH_REG_FE_INT_STATUS, - RAETH_REG_COUNT -}; - -static const u32 ramips_reg_table[RAETH_REG_COUNT] = { - [RAETH_REG_PDMA_GLO_CFG] = RAMIPS_PDMA_GLO_CFG, - [RAETH_REG_PDMA_RST_CFG] = RAMIPS_PDMA_RST_CFG, - [RAETH_REG_DLY_INT_CFG] = RAMIPS_DLY_INT_CFG, - [RAETH_REG_TX_BASE_PTR0] = RAMIPS_TX_BASE_PTR0, - [RAETH_REG_TX_MAX_CNT0] = RAMIPS_TX_MAX_CNT0, - [RAETH_REG_TX_CTX_IDX0] = RAMIPS_TX_CTX_IDX0, - [RAETH_REG_RX_BASE_PTR0] = RAMIPS_RX_BASE_PTR0, - [RAETH_REG_RX_MAX_CNT0] = RAMIPS_RX_MAX_CNT0, - [RAETH_REG_RX_CALC_IDX0] = RAMIPS_RX_CALC_IDX0, - [RAETH_REG_FE_INT_ENABLE] = RAMIPS_FE_INT_ENABLE, - [RAETH_REG_FE_INT_STATUS] = RAMIPS_FE_INT_STATUS, -}; - -static const u32 rt5350_reg_table[RAETH_REG_COUNT] = { - [RAETH_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG, - [RAETH_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG, - [RAETH_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG, - [RAETH_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0, - [RAETH_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0, - [RAETH_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0, - [RAETH_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0, - [RAETH_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0, - [RAETH_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0, - [RAETH_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE, - [RAETH_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS, -}; - -static struct net_device * ramips_dev; -static void __iomem *ramips_fe_base = 0; - -static inline u32 get_reg_offset(enum raeth_reg reg) -{ - const u32 *table; - - if (soc_is_rt5350()) - table = rt5350_reg_table; - else - table = ramips_reg_table; - - return table[reg]; -} - -static inline void -ramips_fe_wr(u32 val, unsigned reg) -{ - __raw_writel(val, ramips_fe_base + reg); -} - -static inline u32 -ramips_fe_rr(unsigned reg) -{ - return __raw_readl(ramips_fe_base + reg); -} - -static inline void -ramips_fe_twr(u32 val, enum raeth_reg reg) -{ - ramips_fe_wr(val, get_reg_offset(reg)); -} - -static inline u32 -ramips_fe_trr(enum raeth_reg reg) -{ - return ramips_fe_rr(get_reg_offset(reg)); -} - -static inline void -ramips_fe_int_disable(u32 mask) -{ - ramips_fe_twr(ramips_fe_trr(RAETH_REG_FE_INT_ENABLE) & ~mask, - RAETH_REG_FE_INT_ENABLE); - /* flush write */ - ramips_fe_trr(RAETH_REG_FE_INT_ENABLE); -} - -static inline void -ramips_fe_int_enable(u32 mask) -{ - ramips_fe_twr(ramips_fe_trr(RAETH_REG_FE_INT_ENABLE) | mask, - RAETH_REG_FE_INT_ENABLE); - /* flush write */ - ramips_fe_trr(RAETH_REG_FE_INT_ENABLE); -} - -static inline void -ramips_hw_set_macaddr(unsigned char *mac) -{ - if (soc_is_rt5350()) { - ramips_fe_wr((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH); - ramips_fe_wr((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], - RT5350_SDM_MAC_ADRL); - } else { - ramips_fe_wr((mac[0] << 8) | mac[1], RAMIPS_GDMA1_MAC_ADRH); - ramips_fe_wr((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], - RAMIPS_GDMA1_MAC_ADRL); - } -} - -static struct sk_buff * -ramips_alloc_skb(struct raeth_priv *re) -{ - struct sk_buff *skb; - - skb = netdev_alloc_skb(re->netdev, MAX_RX_LENGTH + NET_IP_ALIGN); - if (!skb) - return NULL; - - skb_reserve(skb, NET_IP_ALIGN); - - return skb; -} - -static void -ramips_ring_setup(struct raeth_priv *re) -{ - int len; - int i; - - memset(re->tx_info, 0, NUM_TX_DESC * sizeof(struct raeth_tx_info)); - - len = NUM_TX_DESC * sizeof(struct ramips_tx_dma); - memset(re->tx, 0, len); - - for (i = 0; i < NUM_TX_DESC; i++) { - struct raeth_tx_info *txi; - struct ramips_tx_dma *txd; - - txd = &re->tx[i]; - txd->txd4 = TX_DMA_QN(3) | TX_DMA_PN(1); - txd->txd2 = TX_DMA_LSO | TX_DMA_DONE; - - txi = &re->tx_info[i]; - txi->tx_desc = txd; - if (txi->tx_skb != NULL) { - netdev_warn(re->netdev, - "dirty skb for TX desc %d\n", i); - txi->tx_skb = NULL; - } - } - - len = NUM_RX_DESC * sizeof(struct ramips_rx_dma); - memset(re->rx, 0, len); - - for (i = 0; i < NUM_RX_DESC; i++) { - struct raeth_rx_info *rxi; - struct ramips_rx_dma *rxd; - dma_addr_t dma_addr; - - rxd = &re->rx[i]; - rxi = &re->rx_info[i]; - BUG_ON(rxi->rx_skb == NULL); - dma_addr = dma_map_single(&re->netdev->dev, rxi->rx_skb->data, - MAX_RX_LENGTH, DMA_FROM_DEVICE); - rxi->rx_dma = dma_addr; - rxi->rx_desc = rxd; - - rxd->rxd1 = (unsigned int) dma_addr; - rxd->rxd2 = RX_DMA_LSO; - } - - /* flush descriptors */ - wmb(); -} - -static void -ramips_ring_cleanup(struct raeth_priv *re) -{ - int i; - - for (i = 0; i < NUM_RX_DESC; i++) { - struct raeth_rx_info *rxi; - - rxi = &re->rx_info[i]; - if (rxi->rx_skb) - dma_unmap_single(&re->netdev->dev, rxi->rx_dma, - MAX_RX_LENGTH, DMA_FROM_DEVICE); - } - - for (i = 0; i < NUM_TX_DESC; i++) { - struct raeth_tx_info *txi; - - txi = &re->tx_info[i]; - if (txi->tx_skb) { - dev_kfree_skb_any(txi->tx_skb); - txi->tx_skb = NULL; - } - } - - netdev_reset_queue(re->netdev); -} - -#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT3883) - -#define RAMIPS_MDIO_RETRY 1000 - -static unsigned char *ramips_speed_str(struct raeth_priv *re) -{ - switch (re->speed) { - case SPEED_1000: - return "1000"; - case SPEED_100: - return "100"; - case SPEED_10: - return "10"; - } - - return "?"; -} - -static void ramips_link_adjust(struct raeth_priv *re) -{ - struct ramips_eth_platform_data *pdata; - u32 mdio_cfg; - - pdata = re->parent->platform_data; - if (!re->link) { - netif_carrier_off(re->netdev); - netdev_info(re->netdev, "link down\n"); - return; - } - - mdio_cfg = RAMIPS_MDIO_CFG_TX_CLK_SKEW_200 | - RAMIPS_MDIO_CFG_TX_CLK_SKEW_200 | - RAMIPS_MDIO_CFG_GP1_FRC_EN; - - if (re->duplex == DUPLEX_FULL) - mdio_cfg |= RAMIPS_MDIO_CFG_GP1_DUPLEX; - - if (re->tx_fc) - mdio_cfg |= RAMIPS_MDIO_CFG_GP1_FC_TX; - - if (re->rx_fc) - mdio_cfg |= RAMIPS_MDIO_CFG_GP1_FC_RX; - - switch (re->speed) { - case SPEED_10: - mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_10; - break; - case SPEED_100: - mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_100; - break; - case SPEED_1000: - mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_1000; - break; - default: - BUG(); - } - - ramips_fe_wr(mdio_cfg, RAMIPS_MDIO_CFG); - - netif_carrier_on(re->netdev); - netdev_info(re->netdev, "link up (%sMbps/%s duplex)\n", - ramips_speed_str(re), - (DUPLEX_FULL == re->duplex) ? "Full" : "Half"); -} - -static int -ramips_mdio_wait_ready(struct raeth_priv *re) -{ - int retries; - - retries = RAMIPS_MDIO_RETRY; - while (1) { - u32 t; - - t = ramips_fe_rr(RAMIPS_MDIO_ACCESS); - if ((t & (0x1 << 31)) == 0) - return 0; - - if (retries-- == 0) - break; - - udelay(1); - } - - dev_err(re->parent, "MDIO operation timed out\n"); - return -ETIMEDOUT; -} - -static int -ramips_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) -{ - struct raeth_priv *re = bus->priv; - int err; - u32 t; - - err = ramips_mdio_wait_ready(re); - if (err) - return 0xffff; - - t = (phy_addr << 24) | (phy_reg << 16); - ramips_fe_wr(t, RAMIPS_MDIO_ACCESS); - t |= (1 << 31); - ramips_fe_wr(t, RAMIPS_MDIO_ACCESS); - - err = ramips_mdio_wait_ready(re); - if (err) - return 0xffff; - - RADEBUG("%s: addr=%04x, reg=%04x, value=%04x\n", __func__, - phy_addr, phy_reg, ramips_fe_rr(RAMIPS_MDIO_ACCESS) & 0xffff); - - return ramips_fe_rr(RAMIPS_MDIO_ACCESS) & 0xffff; -} - -static int -ramips_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val) -{ - struct raeth_priv *re = bus->priv; - int err; - u32 t; - - RADEBUG("%s: addr=%04x, reg=%04x, value=%04x\n", __func__, - phy_addr, phy_reg, ramips_fe_rr(RAMIPS_MDIO_ACCESS) & 0xffff); - - err = ramips_mdio_wait_ready(re); - if (err) - return err; - - t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val; - ramips_fe_wr(t, RAMIPS_MDIO_ACCESS); - t |= (1 << 31); - ramips_fe_wr(t, RAMIPS_MDIO_ACCESS); - - return ramips_mdio_wait_ready(re); -} - -static int -ramips_mdio_reset(struct mii_bus *bus) -{ - /* TODO */ - return 0; -} - -static int -ramips_mdio_init(struct raeth_priv *re) -{ - int err; - int i; - - re->mii_bus = mdiobus_alloc(); - if (re->mii_bus == NULL) - return -ENOMEM; - - re->mii_bus->name = "ramips_mdio"; - re->mii_bus->read = ramips_mdio_read; - re->mii_bus->write = ramips_mdio_write; - re->mii_bus->reset = ramips_mdio_reset; - re->mii_bus->irq = re->mii_irq; - re->mii_bus->priv = re; - re->mii_bus->parent = re->parent; - - snprintf(re->mii_bus->id, MII_BUS_ID_SIZE, "%s", "ramips_mdio"); - re->mii_bus->phy_mask = 0; - - for (i = 0; i < PHY_MAX_ADDR; i++) - re->mii_irq[i] = PHY_POLL; - - err = mdiobus_register(re->mii_bus); - if (err) - goto err_free_bus; - - return 0; - -err_free_bus: - kfree(re->mii_bus); - return err; -} - -static void -ramips_mdio_cleanup(struct raeth_priv *re) -{ - mdiobus_unregister(re->mii_bus); - kfree(re->mii_bus); -} - -static void -ramips_phy_link_adjust(struct net_device *dev) -{ - struct raeth_priv *re = netdev_priv(dev); - struct phy_device *phydev = re->phy_dev; - unsigned long flags; - int status_change = 0; - - spin_lock_irqsave(&re->phy_lock, flags); - - if (phydev->link) - if (re->duplex != phydev->duplex || - re->speed != phydev->speed) - status_change = 1; - - if (phydev->link != re->link) - status_change = 1; - - re->link = phydev->link; - re->duplex = phydev->duplex; - re->speed = phydev->speed; - - if (status_change) - ramips_link_adjust(re); - - spin_unlock_irqrestore(&re->phy_lock, flags); -} - -static int -ramips_phy_connect_multi(struct raeth_priv *re) -{ - struct net_device *netdev = re->netdev; - struct ramips_eth_platform_data *pdata; - struct phy_device *phydev = NULL; - int phy_addr; - int ret = 0; - - pdata = re->parent->platform_data; - for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { - if (!(pdata->phy_mask & (1 << phy_addr))) - continue; - - if (re->mii_bus->phy_map[phy_addr] == NULL) - continue; - - RADEBUG("%s: PHY found at %s, uid=%08x\n", - netdev->name, - dev_name(&re->mii_bus->phy_map[phy_addr]->dev), - re->mii_bus->phy_map[phy_addr]->phy_id); - - if (phydev == NULL) - phydev = re->mii_bus->phy_map[phy_addr]; - } - - if (!phydev) { - netdev_err(netdev, "no PHY found with phy_mask=%08x\n", - pdata->phy_mask); - return -ENODEV; - } - - re->phy_dev = phy_connect(netdev, dev_name(&phydev->dev), - ramips_phy_link_adjust, 0, - pdata->phy_if_mode); - - if (IS_ERR(re->phy_dev)) { - netdev_err(netdev, "could not connect to PHY at %s\n", - dev_name(&phydev->dev)); - return PTR_ERR(re->phy_dev); - } - - phydev->supported &= PHY_GBIT_FEATURES; - phydev->advertising = phydev->supported; - - RADEBUG("%s: connected to PHY at %s [uid=%08x, driver=%s]\n", - netdev->name, dev_name(&phydev->dev), - phydev->phy_id, phydev->drv->name); - - re->link = 0; - re->speed = 0; - re->duplex = -1; - re->rx_fc = 0; - re->tx_fc = 0; - - return ret; -} - -static int -ramips_phy_connect_fixed(struct raeth_priv *re) -{ - struct ramips_eth_platform_data *pdata; - - pdata = re->parent->platform_data; - switch (pdata->speed) { - case SPEED_10: - case SPEED_100: - case SPEED_1000: - break; - default: - netdev_err(re->netdev, "invalid speed specified\n"); - return -EINVAL; - } - - RADEBUG("%s: using fixed link parameters\n", re->netdev->name); - - re->speed = pdata->speed; - re->duplex = pdata->duplex; - re->tx_fc = pdata->tx_fc; - re->rx_fc = pdata->tx_fc; - - return 0; -} - -static int -ramips_phy_connect(struct raeth_priv *re) -{ - struct ramips_eth_platform_data *pdata; - - pdata = re->parent->platform_data; - if (pdata->phy_mask) - return ramips_phy_connect_multi(re); - - return ramips_phy_connect_fixed(re); -} - -static void -ramips_phy_disconnect(struct raeth_priv *re) -{ - if (re->phy_dev) - phy_disconnect(re->phy_dev); -} - -static void -ramips_phy_start(struct raeth_priv *re) -{ - unsigned long flags; - - if (re->phy_dev) { - phy_start(re->phy_dev); - } else { - spin_lock_irqsave(&re->phy_lock, flags); - re->link = 1; - ramips_link_adjust(re); - spin_unlock_irqrestore(&re->phy_lock, flags); - } -} - -static void -ramips_phy_stop(struct raeth_priv *re) -{ - unsigned long flags; - - if (re->phy_dev) - phy_stop(re->phy_dev); - - spin_lock_irqsave(&re->phy_lock, flags); - re->link = 0; - ramips_link_adjust(re); - spin_unlock_irqrestore(&re->phy_lock, flags); -} -#else -static inline int -ramips_mdio_init(struct raeth_priv *re) -{ - return 0; -} - -static inline void -ramips_mdio_cleanup(struct raeth_priv *re) -{ -} - -static inline int -ramips_phy_connect(struct raeth_priv *re) -{ - return 0; -} - -static inline void -ramips_phy_disconnect(struct raeth_priv *re) -{ -} - -static inline void -ramips_phy_start(struct raeth_priv *re) -{ -} - -static inline void -ramips_phy_stop(struct raeth_priv *re) -{ -} -#endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT3883 */ - -static void -ramips_ring_free(struct raeth_priv *re) -{ - int len; - int i; - - if (re->rx_info) { - for (i = 0; i < NUM_RX_DESC; i++) { - struct raeth_rx_info *rxi; - - rxi = &re->rx_info[i]; - if (rxi->rx_skb) - dev_kfree_skb_any(rxi->rx_skb); - } - kfree(re->rx_info); - } - - if (re->rx) { - len = NUM_RX_DESC * sizeof(struct ramips_rx_dma); - dma_free_coherent(&re->netdev->dev, len, re->rx, - re->rx_desc_dma); - } - - if (re->tx) { - len = NUM_TX_DESC * sizeof(struct ramips_tx_dma); - dma_free_coherent(&re->netdev->dev, len, re->tx, - re->tx_desc_dma); - } - - kfree(re->tx_info); -} - -static int -ramips_ring_alloc(struct raeth_priv *re) -{ - int len; - int err = -ENOMEM; - int i; - - re->tx_info = kzalloc(NUM_TX_DESC * sizeof(struct raeth_tx_info), - GFP_ATOMIC); - if (!re->tx_info) - goto err_cleanup; - - re->rx_info = kzalloc(NUM_RX_DESC * sizeof(struct raeth_rx_info), - GFP_ATOMIC); - if (!re->rx_info) - goto err_cleanup; - - /* allocate tx ring */ - len = NUM_TX_DESC * sizeof(struct ramips_tx_dma); - re->tx = dma_alloc_coherent(&re->netdev->dev, len, - &re->tx_desc_dma, GFP_ATOMIC); - if (!re->tx) - goto err_cleanup; - - /* allocate rx ring */ - len = NUM_RX_DESC * sizeof(struct ramips_rx_dma); - re->rx = dma_alloc_coherent(&re->netdev->dev, len, - &re->rx_desc_dma, GFP_ATOMIC); - if (!re->rx) - goto err_cleanup; - - for (i = 0; i < NUM_RX_DESC; i++) { - struct sk_buff *skb; - - skb = ramips_alloc_skb(re); - if (!skb) - goto err_cleanup; - - re->rx_info[i].rx_skb = skb; - } - - return 0; - -err_cleanup: - ramips_ring_free(re); - return err; -} - -static void -ramips_setup_dma(struct raeth_priv *re) -{ - ramips_fe_twr(re->tx_desc_dma, RAETH_REG_TX_BASE_PTR0); - ramips_fe_twr(NUM_TX_DESC, RAETH_REG_TX_MAX_CNT0); - ramips_fe_twr(0, RAETH_REG_TX_CTX_IDX0); - ramips_fe_twr(RAMIPS_PST_DTX_IDX0, RAETH_REG_PDMA_RST_CFG); - - ramips_fe_twr(re->rx_desc_dma, RAETH_REG_RX_BASE_PTR0); - ramips_fe_twr(NUM_RX_DESC, RAETH_REG_RX_MAX_CNT0); - ramips_fe_twr((NUM_RX_DESC - 1), RAETH_REG_RX_CALC_IDX0); - ramips_fe_twr(RAMIPS_PST_DRX_IDX0, RAETH_REG_PDMA_RST_CFG); -} - -static int -ramips_eth_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) -{ - struct raeth_priv *re = netdev_priv(dev); - struct raeth_tx_info *txi, *txi_next; - struct ramips_tx_dma *txd, *txd_next; - unsigned long tx; - unsigned int tx_next; - dma_addr_t mapped_addr; - - if (re->plat->min_pkt_len) { - if (skb->len < re->plat->min_pkt_len) { - if (skb_padto(skb, re->plat->min_pkt_len)) { - printk(KERN_ERR - "ramips_eth: skb_padto failed\n"); - kfree_skb(skb); - return 0; - } - skb_put(skb, re->plat->min_pkt_len - skb->len); - } - } - - dev->trans_start = jiffies; - mapped_addr = dma_map_single(&re->netdev->dev, skb->data, skb->len, - DMA_TO_DEVICE); - - spin_lock(&re->page_lock); - tx = ramips_fe_trr(RAETH_REG_TX_CTX_IDX0); - tx_next = (tx + 1) % NUM_TX_DESC; - - txi = &re->tx_info[tx]; - txd = txi->tx_desc; - txi_next = &re->tx_info[tx_next]; - txd_next = txi_next->tx_desc; - - if ((txi->tx_skb) || (txi_next->tx_skb) || - !(txd->txd2 & TX_DMA_DONE) || - !(txd_next->txd2 & TX_DMA_DONE)) - goto out; - - txi->tx_skb = skb; - - txd->txd1 = (unsigned int) mapped_addr; - wmb(); - txd->txd2 = TX_DMA_LSO | TX_DMA_PLEN0(skb->len); - dev->stats.tx_packets++; - dev->stats.tx_bytes += skb->len; - ramips_fe_twr(tx_next, RAETH_REG_TX_CTX_IDX0); - netdev_sent_queue(dev, skb->len); - spin_unlock(&re->page_lock); - return NETDEV_TX_OK; - - out: - spin_unlock(&re->page_lock); - dev->stats.tx_dropped++; - kfree_skb(skb); - return NETDEV_TX_OK; -} - -static void -ramips_eth_rx_hw(unsigned long ptr) -{ - struct net_device *dev = (struct net_device *) ptr; - struct raeth_priv *re = netdev_priv(dev); - int rx; - int max_rx = 16; - - rx = ramips_fe_trr(RAETH_REG_RX_CALC_IDX0); - - while (max_rx) { - struct raeth_rx_info *rxi; - struct ramips_rx_dma *rxd; - struct sk_buff *rx_skb, *new_skb; - int pktlen; - - rx = (rx + 1) % NUM_RX_DESC; - - rxi = &re->rx_info[rx]; - rxd = rxi->rx_desc; - if (!(rxd->rxd2 & RX_DMA_DONE)) - break; - - rx_skb = rxi->rx_skb; - pktlen = RX_DMA_PLEN0(rxd->rxd2); - - new_skb = ramips_alloc_skb(re); - /* Reuse the buffer on allocation failures */ - if (new_skb) { - dma_addr_t dma_addr; - - dma_unmap_single(&re->netdev->dev, rxi->rx_dma, - MAX_RX_LENGTH, DMA_FROM_DEVICE); - - skb_put(rx_skb, pktlen); - rx_skb->dev = dev; - rx_skb->protocol = eth_type_trans(rx_skb, dev); - rx_skb->ip_summed = CHECKSUM_NONE; - dev->stats.rx_packets++; - dev->stats.rx_bytes += pktlen; - netif_rx(rx_skb); - - rxi->rx_skb = new_skb; - - dma_addr = dma_map_single(&re->netdev->dev, - new_skb->data, - MAX_RX_LENGTH, - DMA_FROM_DEVICE); - rxi->rx_dma = dma_addr; - rxd->rxd1 = (unsigned int) dma_addr; - wmb(); - } else { - dev->stats.rx_dropped++; - } - - rxd->rxd2 = RX_DMA_LSO; - ramips_fe_twr(rx, RAETH_REG_RX_CALC_IDX0); - max_rx--; - } - - if (max_rx == 0) - tasklet_schedule(&re->rx_tasklet); - else - ramips_fe_int_enable(RX_DLY_INT); -} - -static void -ramips_eth_tx_housekeeping(unsigned long ptr) -{ - struct net_device *dev = (struct net_device*)ptr; - struct raeth_priv *re = netdev_priv(dev); - unsigned int bytes_compl = 0, pkts_compl = 0; - - spin_lock(&re->page_lock); - while (1) { - struct raeth_tx_info *txi; - struct ramips_tx_dma *txd; - - txi = &re->tx_info[re->skb_free_idx]; - txd = txi->tx_desc; - - if (!(txd->txd2 & TX_DMA_DONE) || !(txi->tx_skb)) - break; - - pkts_compl++; - bytes_compl += txi->tx_skb->len; - - dev_kfree_skb_irq(txi->tx_skb); - txi->tx_skb = NULL; - re->skb_free_idx++; - if (re->skb_free_idx >= NUM_TX_DESC) - re->skb_free_idx = 0; - } - netdev_completed_queue(dev, pkts_compl, bytes_compl); - spin_unlock(&re->page_lock); - - ramips_fe_int_enable(TX_DLY_INT); -} - -static void -ramips_eth_timeout(struct net_device *dev) -{ - struct raeth_priv *re = netdev_priv(dev); - - tasklet_schedule(&re->tx_housekeeping_tasklet); -} - -static irqreturn_t -ramips_eth_irq(int irq, void *dev) -{ - struct raeth_priv *re = netdev_priv(dev); - unsigned int status; - - status = ramips_fe_trr(RAETH_REG_FE_INT_STATUS); - status &= ramips_fe_trr(RAETH_REG_FE_INT_ENABLE); - - if (!status) - return IRQ_NONE; - - ramips_fe_twr(status, RAETH_REG_FE_INT_STATUS); - - if (status & RX_DLY_INT) { - ramips_fe_int_disable(RX_DLY_INT); - tasklet_schedule(&re->rx_tasklet); - } - - if (status & TX_DLY_INT) { - ramips_fe_int_disable(TX_DLY_INT); - tasklet_schedule(&re->tx_housekeeping_tasklet); - } - - raeth_debugfs_update_int_stats(re, status); - - return IRQ_HANDLED; -} - -static int -ramips_eth_hw_init(struct net_device *dev) -{ - struct raeth_priv *re = netdev_priv(dev); - int err; - - err = request_irq(dev->irq, ramips_eth_irq, IRQF_DISABLED, - dev->name, dev); - if (err) - return err; - - err = ramips_ring_alloc(re); - if (err) - goto err_free_irq; - - ramips_ring_setup(re); - ramips_hw_set_macaddr(dev->dev_addr); - - ramips_setup_dma(re); - ramips_fe_wr((ramips_fe_rr(RAMIPS_FE_GLO_CFG) & - ~(RAMIPS_US_CYC_CNT_MASK << RAMIPS_US_CYC_CNT_SHIFT)) | - ((re->plat->sys_freq / RAMIPS_US_CYC_CNT_DIVISOR) << RAMIPS_US_CYC_CNT_SHIFT), - RAMIPS_FE_GLO_CFG); - - tasklet_init(&re->tx_housekeeping_tasklet, ramips_eth_tx_housekeeping, - (unsigned long)dev); - tasklet_init(&re->rx_tasklet, ramips_eth_rx_hw, (unsigned long)dev); - - - ramips_fe_twr(RAMIPS_DELAY_INIT, RAETH_REG_DLY_INT_CFG); - ramips_fe_twr(TX_DLY_INT | RX_DLY_INT, RAETH_REG_FE_INT_ENABLE); - if (soc_is_rt5350()) { - ramips_fe_wr(ramips_fe_rr(RT5350_SDM_CFG) & - ~(RT5350_SDM_ICS_EN | RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN | 0xffff), - RT5350_SDM_CFG); - } else { - ramips_fe_wr(ramips_fe_rr(RAMIPS_GDMA1_FWD_CFG) & - ~(RAMIPS_GDM1_ICS_EN | RAMIPS_GDM1_TCS_EN | RAMIPS_GDM1_UCS_EN | 0xffff), - RAMIPS_GDMA1_FWD_CFG); - ramips_fe_wr(ramips_fe_rr(RAMIPS_CDMA_CSG_CFG) & - ~(RAMIPS_ICS_GEN_EN | RAMIPS_TCS_GEN_EN | RAMIPS_UCS_GEN_EN), - RAMIPS_CDMA_CSG_CFG); - ramips_fe_wr(RAMIPS_PSE_FQFC_CFG_INIT, RAMIPS_PSE_FQ_CFG); - } - ramips_fe_wr(1, RAMIPS_FE_RST_GL); - ramips_fe_wr(0, RAMIPS_FE_RST_GL); - - return 0; - -err_free_irq: - free_irq(dev->irq, dev); - return err; -} - -static int -ramips_eth_open(struct net_device *dev) -{ - struct raeth_priv *re = netdev_priv(dev); - - ramips_fe_twr((ramips_fe_trr(RAETH_REG_PDMA_GLO_CFG) & 0xff) | - (RAMIPS_TX_WB_DDONE | RAMIPS_RX_DMA_EN | - RAMIPS_TX_DMA_EN | RAMIPS_PDMA_SIZE_4DWORDS), - RAETH_REG_PDMA_GLO_CFG); - ramips_phy_start(re); - netif_start_queue(dev); - return 0; -} - -static int -ramips_eth_stop(struct net_device *dev) -{ - struct raeth_priv *re = netdev_priv(dev); - - ramips_fe_twr(ramips_fe_trr(RAETH_REG_PDMA_GLO_CFG) & - ~(RAMIPS_TX_WB_DDONE | RAMIPS_RX_DMA_EN | RAMIPS_TX_DMA_EN), - RAETH_REG_PDMA_GLO_CFG); - - netif_stop_queue(dev); - ramips_phy_stop(re); - RADEBUG("ramips_eth: stopped\n"); - return 0; -} - -static int __init -ramips_eth_probe(struct net_device *dev) -{ - struct raeth_priv *re = netdev_priv(dev); - int err; - - BUG_ON(!re->plat->reset_fe); - re->plat->reset_fe(); - net_srandom(jiffies); - memcpy(dev->dev_addr, re->plat->mac, ETH_ALEN); - - ether_setup(dev); - dev->mtu = 1500; - dev->watchdog_timeo = TX_TIMEOUT; - spin_lock_init(&re->page_lock); - spin_lock_init(&re->phy_lock); - - err = ramips_mdio_init(re); - if (err) - return err; - - err = ramips_phy_connect(re); - if (err) - goto err_mdio_cleanup; - - err = raeth_debugfs_init(re); - if (err) - goto err_phy_disconnect; - - err = ramips_eth_hw_init(dev); - if (err) - goto err_debugfs; - - return 0; - -err_debugfs: - raeth_debugfs_exit(re); -err_phy_disconnect: - ramips_phy_disconnect(re); -err_mdio_cleanup: - ramips_mdio_cleanup(re); - return err; -} - -static void -ramips_eth_uninit(struct net_device *dev) -{ - struct raeth_priv *re = netdev_priv(dev); - - raeth_debugfs_exit(re); - ramips_phy_disconnect(re); - ramips_mdio_cleanup(re); - ramips_fe_twr(0, RAETH_REG_FE_INT_ENABLE); - free_irq(dev->irq, dev); - tasklet_kill(&re->tx_housekeeping_tasklet); - tasklet_kill(&re->rx_tasklet); - ramips_ring_cleanup(re); - ramips_ring_free(re); -} - -static const struct net_device_ops ramips_eth_netdev_ops = { - .ndo_init = ramips_eth_probe, - .ndo_uninit = ramips_eth_uninit, - .ndo_open = ramips_eth_open, - .ndo_stop = ramips_eth_stop, - .ndo_start_xmit = ramips_eth_hard_start_xmit, - .ndo_tx_timeout = ramips_eth_timeout, - .ndo_change_mtu = eth_change_mtu, - .ndo_set_mac_address = eth_mac_addr, - .ndo_validate_addr = eth_validate_addr, -}; - -static int -ramips_eth_plat_probe(struct platform_device *plat) -{ - struct raeth_priv *re; - struct ramips_eth_platform_data *data = plat->dev.platform_data; - struct resource *res; - int err; - - if (!data) { - dev_err(&plat->dev, "no platform data specified\n"); - return -EINVAL; - } - - res = platform_get_resource(plat, IORESOURCE_MEM, 0); - if (!res) { - dev_err(&plat->dev, "no memory resource found\n"); - return -ENXIO; - } - - ramips_fe_base = ioremap_nocache(res->start, res->end - res->start + 1); - if (!ramips_fe_base) - return -ENOMEM; - - ramips_dev = alloc_etherdev(sizeof(struct raeth_priv)); - if (!ramips_dev) { - dev_err(&plat->dev, "alloc_etherdev failed\n"); - err = -ENOMEM; - goto err_unmap; - } - - strcpy(ramips_dev->name, "eth%d"); - ramips_dev->irq = platform_get_irq(plat, 0); - if (ramips_dev->irq < 0) { - dev_err(&plat->dev, "no IRQ resource found\n"); - err = -ENXIO; - goto err_free_dev; - } - ramips_dev->addr_len = ETH_ALEN; - ramips_dev->base_addr = (unsigned long)ramips_fe_base; - ramips_dev->netdev_ops = &ramips_eth_netdev_ops; - - re = netdev_priv(ramips_dev); - - re->netdev = ramips_dev; - re->parent = &plat->dev; - re->speed = data->speed; - re->duplex = data->duplex; - re->rx_fc = data->rx_fc; - re->tx_fc = data->tx_fc; - re->plat = data; - - err = register_netdev(ramips_dev); - if (err) { - dev_err(&plat->dev, "error bringing up device\n"); - goto err_free_dev; - } - - RADEBUG("ramips_eth: loaded\n"); - return 0; - - err_free_dev: - kfree(ramips_dev); - err_unmap: - iounmap(ramips_fe_base); - return err; -} - -static int -ramips_eth_plat_remove(struct platform_device *plat) -{ - unregister_netdev(ramips_dev); - free_netdev(ramips_dev); - RADEBUG("ramips_eth: unloaded\n"); - return 0; -} - -static struct platform_driver ramips_eth_driver = { - .probe = ramips_eth_plat_probe, - .remove = ramips_eth_plat_remove, - .driver = { - .name = "ramips_eth", - .owner = THIS_MODULE, - }, -}; - -static int __init -ramips_eth_init(void) -{ - int ret; - - ret = raeth_debugfs_root_init(); - if (ret) - goto err_out; - - ret = rt305x_esw_init(); - if (ret) - goto err_debugfs_exit; - - ret = platform_driver_register(&ramips_eth_driver); - if (ret) { - printk(KERN_ERR - "ramips_eth: Error registering platfom driver!\n"); - goto esw_cleanup; - } - - return 0; - -esw_cleanup: - rt305x_esw_exit(); -err_debugfs_exit: - raeth_debugfs_root_exit(); -err_out: - return ret; -} - -static void __exit -ramips_eth_cleanup(void) -{ - platform_driver_unregister(&ramips_eth_driver); - rt305x_esw_exit(); - raeth_debugfs_root_exit(); -} - -module_init(ramips_eth_init); -module_exit(ramips_eth_cleanup); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("John Crispin "); -MODULE_DESCRIPTION("ethernet driver for ramips boards"); diff --git a/target/linux/ramips/files/drivers/spi/spi-ramips.c b/target/linux/ramips/files/drivers/spi/spi-ramips.c deleted file mode 100644 index d2ceaf3b8d..0000000000 --- a/target/linux/ramips/files/drivers/spi/spi-ramips.c +++ /dev/null @@ -1,559 +0,0 @@ -/* - * ramips_spi.c -- Ralink RT288x/RT305x SPI controller driver - * - * Copyright (C) 2011 Sergiy - * Copyright (C) 2011 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define DRIVER_NAME "ramips-spi" -#define RALINK_NUM_CHIPSELECTS 1 /* only one slave is supported*/ -#define RALINK_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */ - -#define RAMIPS_SPI_STAT 0x00 -#define RAMIPS_SPI_CFG 0x10 -#define RAMIPS_SPI_CTL 0x14 -#define RAMIPS_SPI_DATA 0x20 - -/* SPISTAT register bit field */ -#define SPISTAT_BUSY BIT(0) - -/* SPICFG register bit field */ -#define SPICFG_LSBFIRST 0 -#define SPICFG_MSBFIRST BIT(8) -#define SPICFG_SPICLKPOL BIT(6) -#define SPICFG_RXCLKEDGE_FALLING BIT(5) -#define SPICFG_TXCLKEDGE_FALLING BIT(4) -#define SPICFG_SPICLK_PRESCALE_MASK 0x7 -#define SPICFG_SPICLK_DIV2 0 -#define SPICFG_SPICLK_DIV4 1 -#define SPICFG_SPICLK_DIV8 2 -#define SPICFG_SPICLK_DIV16 3 -#define SPICFG_SPICLK_DIV32 4 -#define SPICFG_SPICLK_DIV64 5 -#define SPICFG_SPICLK_DIV128 6 -#define SPICFG_SPICLK_DISABLE 7 - -/* SPICTL register bit field */ -#define SPICTL_HIZSDO BIT(3) -#define SPICTL_STARTWR BIT(2) -#define SPICTL_STARTRD BIT(1) -#define SPICTL_SPIENA BIT(0) - -#ifdef DEBUG -#define spi_debug(args...) printk(args) -#else -#define spi_debug(args...) -#endif - -struct ramips_spi { - struct work_struct work; - - /* Lock access to transfer list.*/ - spinlock_t lock; - - struct list_head msg_queue; - struct spi_master *master; - void __iomem *base; - unsigned int sys_freq; - unsigned int speed; - - struct clk *clk; -}; - -static struct workqueue_struct *ramips_spi_wq; - -static inline struct ramips_spi *ramips_spidev_to_rs(struct spi_device *spi) -{ - return spi_master_get_devdata(spi->master); -} - -static inline u32 ramips_spi_read(struct ramips_spi *rs, u32 reg) -{ - return ioread32(rs->base + reg); -} - -static inline void ramips_spi_write(struct ramips_spi *rs, u32 reg, u32 val) -{ - iowrite32(val, rs->base + reg); -} - -static inline void ramips_spi_setbits(struct ramips_spi *rs, u32 reg, u32 mask) -{ - void __iomem *addr = rs->base + reg; - u32 val; - - val = ioread32(addr); - val |= mask; - iowrite32(val, addr); -} - -static inline void ramips_spi_clrbits(struct ramips_spi *rs, u32 reg, u32 mask) -{ - void __iomem *addr = rs->base + reg; - u32 val; - - val = ioread32(addr); - val &= ~mask; - iowrite32(val, addr); -} - -static int ramips_spi_baudrate_set(struct spi_device *spi, unsigned int speed) -{ - struct ramips_spi *rs = ramips_spidev_to_rs(spi); - u32 rate; - u32 prescale; - u32 reg; - - spi_debug("%s: speed:%u\n", __func__, speed); - - /* - * the supported rates are: 2,4,8...128 - * round up as we look for equal or less speed - */ - rate = DIV_ROUND_UP(rs->sys_freq, speed); - spi_debug("%s: rate-1:%u\n", __func__, rate); - rate = roundup_pow_of_two(rate); - spi_debug("%s: rate-2:%u\n", __func__, rate); - - /* check if requested speed is too small */ - if (rate > 128) - return -EINVAL; - - if (rate < 2) - rate = 2; - - /* Convert the rate to SPI clock divisor value. */ - prescale = ilog2(rate/2); - spi_debug("%s: prescale:%u\n", __func__, prescale); - - reg = ramips_spi_read(rs, RAMIPS_SPI_CFG); - reg = ((reg & ~SPICFG_SPICLK_PRESCALE_MASK) | prescale); - ramips_spi_write(rs, RAMIPS_SPI_CFG, reg); - rs->speed = speed; - return 0; -} - -/* - * called only when no transfer is active on the bus - */ -static int -ramips_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) -{ - struct ramips_spi *rs = ramips_spidev_to_rs(spi); - unsigned int speed = spi->max_speed_hz; - int rc; - unsigned int bits_per_word = 8; - - if ((t != NULL) && t->speed_hz) - speed = t->speed_hz; - - if ((t != NULL) && t->bits_per_word) - bits_per_word = t->bits_per_word; - - if (rs->speed != speed) { - spi_debug("%s: speed_hz:%u\n", __func__, speed); - rc = ramips_spi_baudrate_set(spi, speed); - if (rc) - return rc; - } - - if (bits_per_word != 8) { - spi_debug("%s: bad bits_per_word: %u\n", __func__, - bits_per_word); - return -EINVAL; - } - - return 0; -} - -static void ramips_spi_set_cs(struct ramips_spi *rs, int enable) -{ - if (enable) - ramips_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA); - else - ramips_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA); -} - -static inline int ramips_spi_wait_till_ready(struct ramips_spi *rs) -{ - int i; - - for (i = 0; i < RALINK_SPI_WAIT_RDY_MAX_LOOP; i++) { - u32 status; - - status = ramips_spi_read(rs, RAMIPS_SPI_STAT); - if ((status & SPISTAT_BUSY) == 0) - return 0; - - udelay(1); - } - - return -ETIMEDOUT; -} - -static unsigned int -ramips_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer) -{ - struct ramips_spi *rs = ramips_spidev_to_rs(spi); - unsigned count = 0; - u8 *rx = xfer->rx_buf; - const u8 *tx = xfer->tx_buf; - int err; - - spi_debug("%s(%d): %s %s\n", __func__, xfer->len, - (tx != NULL) ? "tx" : " ", - (rx != NULL) ? "rx" : " "); - - if (tx) { - for (count = 0; count < xfer->len; count++) { - ramips_spi_write(rs, RAMIPS_SPI_DATA, tx[count]); - ramips_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR); - err = ramips_spi_wait_till_ready(rs); - if (err) { - dev_err(&spi->dev, "TX failed, err=%d\n", err); - goto out; - } - } - } - - if (rx) { - for (count = 0; count < xfer->len; count++) { - ramips_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD); - err = ramips_spi_wait_till_ready(rs); - if (err) { - dev_err(&spi->dev, "RX failed, err=%d\n", err); - goto out; - } - rx[count] = (u8) ramips_spi_read(rs, RAMIPS_SPI_DATA); - } - } - -out: - return count; -} - -static void ramips_spi_work(struct work_struct *work) -{ - struct ramips_spi *rs = - container_of(work, struct ramips_spi, work); - - spin_lock_irq(&rs->lock); - while (!list_empty(&rs->msg_queue)) { - struct spi_message *m; - struct spi_device *spi; - struct spi_transfer *t = NULL; - int par_override = 0; - int status = 0; - int cs_active = 0; - - m = container_of(rs->msg_queue.next, struct spi_message, - queue); - - list_del_init(&m->queue); - spin_unlock_irq(&rs->lock); - - spi = m->spi; - - /* Load defaults */ - status = ramips_spi_setup_transfer(spi, NULL); - - if (status < 0) - goto msg_done; - - list_for_each_entry(t, &m->transfers, transfer_list) { - if (par_override || t->speed_hz || t->bits_per_word) { - par_override = 1; - status = ramips_spi_setup_transfer(spi, t); - if (status < 0) - break; - if (!t->speed_hz && !t->bits_per_word) - par_override = 0; - } - - if (!cs_active) { - ramips_spi_set_cs(rs, 1); - cs_active = 1; - } - - if (t->len) - m->actual_length += - ramips_spi_write_read(spi, t); - - if (t->delay_usecs) - udelay(t->delay_usecs); - - if (t->cs_change) { - ramips_spi_set_cs(rs, 0); - cs_active = 0; - } - } - -msg_done: - if (cs_active) - ramips_spi_set_cs(rs, 0); - - m->status = status; - m->complete(m->context); - - spin_lock_irq(&rs->lock); - } - - spin_unlock_irq(&rs->lock); -} - -static int ramips_spi_setup(struct spi_device *spi) -{ - struct ramips_spi *rs = ramips_spidev_to_rs(spi); - - if ((spi->max_speed_hz == 0) || - (spi->max_speed_hz > (rs->sys_freq / 2))) - spi->max_speed_hz = (rs->sys_freq / 2); - - if (spi->max_speed_hz < (rs->sys_freq/128)) { - dev_err(&spi->dev, "setup: requested speed too low %d Hz\n", - spi->max_speed_hz); - return -EINVAL; - } - - if (spi->bits_per_word != 0 && spi->bits_per_word != 8) { - dev_err(&spi->dev, - "setup: requested bits per words - os wrong %d bpw\n", - spi->bits_per_word); - return -EINVAL; - } - - if (spi->bits_per_word == 0) - spi->bits_per_word = 8; - - /* - * baudrate & width will be set ramips_spi_setup_transfer - */ - return 0; -} - -static int ramips_spi_transfer(struct spi_device *spi, struct spi_message *m) -{ - struct ramips_spi *rs; - struct spi_transfer *t = NULL; - unsigned long flags; - - m->actual_length = 0; - m->status = 0; - - /* reject invalid messages and transfers */ - if (list_empty(&m->transfers) || !m->complete) - return -EINVAL; - - rs = ramips_spidev_to_rs(spi); - - list_for_each_entry(t, &m->transfers, transfer_list) { - unsigned int bits_per_word = spi->bits_per_word; - - if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) { - dev_err(&spi->dev, - "message rejected : " - "invalid transfer data buffers\n"); - goto msg_rejected; - } - - if (t->bits_per_word) - bits_per_word = t->bits_per_word; - - if (bits_per_word != 8) { - dev_err(&spi->dev, - "message rejected : " - "invalid transfer bits_per_word (%d bits)\n", - bits_per_word); - goto msg_rejected; - } - - if (t->speed_hz && t->speed_hz < (rs->sys_freq/128)) { - dev_err(&spi->dev, - "message rejected : " - "device min speed (%d Hz) exceeds " - "required transfer speed (%d Hz)\n", - (rs->sys_freq/128), t->speed_hz); - goto msg_rejected; - } - } - - - spin_lock_irqsave(&rs->lock, flags); - list_add_tail(&m->queue, &rs->msg_queue); - queue_work(ramips_spi_wq, &rs->work); - spin_unlock_irqrestore(&rs->lock, flags); - - return 0; -msg_rejected: - /* Message rejected and not queued */ - m->status = -EINVAL; - if (m->complete) - m->complete(m->context); - return -EINVAL; -} - -static void __init ramips_spi_reset(struct ramips_spi *rs) -{ - ramips_spi_write(rs, RAMIPS_SPI_CFG, - SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING | - SPICFG_SPICLK_DIV16 | SPICFG_SPICLKPOL); - ramips_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA); -} - -static int __init ramips_spi_probe(struct platform_device *pdev) -{ - struct spi_master *master; - struct ramips_spi *rs; - struct resource *r; - int status = 0; - - master = spi_alloc_master(&pdev->dev, sizeof(*rs)); - if (master == NULL) { - dev_dbg(&pdev->dev, "master allocation failed\n"); - return -ENOMEM; - } - - if (pdev->id != -1) - master->bus_num = pdev->id; - - /* we support only mode 0, and no options */ - master->mode_bits = 0; - - master->setup = ramips_spi_setup; - master->transfer = ramips_spi_transfer; - master->num_chipselect = RALINK_NUM_CHIPSELECTS; - - dev_set_drvdata(&pdev->dev, master); - - rs = spi_master_get_devdata(master); - rs->master = master; - - rs->clk = clk_get(NULL, "sys"); - if (IS_ERR(rs->clk)) { - status = PTR_ERR(rs->clk); - dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n", - status); - goto out_put_master; - } - - status = clk_enable(rs->clk); - if (status) - goto out_put_clk; - - rs->sys_freq = clk_get_rate(rs->clk); - spi_debug("%s: sys_freq: %ld\n", __func__, rs->sys_freq); - - r = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (r == NULL) { - status = -ENODEV; - goto out_disable_clk; - } - - if (!request_mem_region(r->start, (r->end - r->start) + 1, - dev_name(&pdev->dev))) { - status = -EBUSY; - goto out_disable_clk; - } - - rs->base = ioremap(r->start, resource_size(r)); - if (rs->base == NULL) { - dev_err(&pdev->dev, "ioremap failed\n"); - status = -ENOMEM; - goto out_rel_mem; - } - - INIT_WORK(&rs->work, ramips_spi_work); - - spin_lock_init(&rs->lock); - INIT_LIST_HEAD(&rs->msg_queue); - - ramips_spi_reset(rs); - - status = spi_register_master(master); - if (status) - goto out_unmap_base; - - return 0; - -out_unmap_base: - iounmap(rs->base); -out_rel_mem: - release_mem_region(r->start, (r->end - r->start) + 1); -out_disable_clk: - clk_disable(rs->clk); -out_put_clk: - clk_put(rs->clk); -out_put_master: - spi_master_put(master); - return status; -} - -static int ramips_spi_remove(struct platform_device *pdev) -{ - struct spi_master *master; - struct ramips_spi *rs; - struct resource *r; - - master = dev_get_drvdata(&pdev->dev); - rs = spi_master_get_devdata(master); - - cancel_work_sync(&rs->work); - - iounmap(rs->base); - r = platform_get_resource(pdev, IORESOURCE_MEM, 0); - release_mem_region(r->start, (r->end - r->start) + 1); - - clk_disable(rs->clk); - clk_put(rs->clk); - spi_unregister_master(master); - - return 0; -} - -MODULE_ALIAS("platform:" DRIVER_NAME); - -static struct platform_driver ramips_spi_driver = { - .driver = { - .name = DRIVER_NAME, - .owner = THIS_MODULE, - }, - .remove = ramips_spi_remove, -}; - -static int __init ramips_spi_init(void) -{ - ramips_spi_wq = create_singlethread_workqueue( - ramips_spi_driver.driver.name); - if (ramips_spi_wq == NULL) - return -ENOMEM; - - return platform_driver_probe(&ramips_spi_driver, ramips_spi_probe); -} -module_init(ramips_spi_init); - -static void __exit ramips_spi_exit(void) -{ - flush_workqueue(ramips_spi_wq); - platform_driver_unregister(&ramips_spi_driver); - - destroy_workqueue(ramips_spi_wq); -} -module_exit(ramips_spi_exit); - -MODULE_DESCRIPTION("Ralink SPI driver"); -MODULE_AUTHOR("Sergiy "); -MODULE_AUTHOR("Gabor Juhos "); -MODULE_LICENSE("GPL"); diff --git a/target/linux/ramips/files/drivers/usb/dwc_otg/Kconfig b/target/linux/ramips/files/drivers/usb/dwc_otg/Kconfig deleted file mode 100644 index 6dd75f14a3..0000000000 --- a/target/linux/ramips/files/drivers/usb/dwc_otg/Kconfig +++ /dev/null @@ -1,24 +0,0 @@ -config DWC_OTG - tristate "Ralink RT305X DWC_OTG support" - depends on SOC_RT305X - ---help--- - This driver supports Ralink DWC_OTG - -choice - prompt "USB Operation Mode" - depends on DWC_OTG - default DWC_OTG_HOST_ONLY - -config DWC_OTG_HOST_ONLY - bool "HOST ONLY MODE" - depends on DWC_OTG - -config DWC_OTG_DEVICE_ONLY - bool "DEVICE ONLY MODE" - depends on DWC_OTG - -endchoice - -config DWC_OTG_DEBUG - bool "Enable debug mode" - depends on DWC_OTG diff --git a/target/linux/ramips/files/drivers/usb/dwc_otg/Makefile b/target/linux/ramips/files/drivers/usb/dwc_otg/Makefile deleted file mode 100644 index 95c5b66fea..0000000000 --- a/target/linux/ramips/files/drivers/usb/dwc_otg/Makefile +++ /dev/null @@ -1,25 +0,0 @@ -# -# Makefile for DWC_otg Highspeed USB controller driver -# - -ifeq ($(CONFIG_DWC_OTG_DEBUG),y) -EXTRA_CFLAGS += -DDEBUG -endif - -# Use one of the following flags to compile the software in host-only or -# device-only mode. -ifeq ($(CONFIG_DWC_OTG_HOST_ONLY),y) -EXTRA_CFLAGS += -DDWC_HOST_ONLY -EXTRA_CFLAGS += -DDWC_EN_ISOC -endif - -ifeq ($(CONFIG_DWC_OTG_DEVICE_ONLY),y) -EXTRA_CFLAGS += -DDWC_DEVICE_ONLY -endif - -obj-$(CONFIG_DWC_OTG) := dwc_otg.o - -dwc_otg-objs := dwc_otg_driver.o dwc_otg_attr.o -dwc_otg-objs += dwc_otg_cil.o dwc_otg_cil_intr.o -dwc_otg-objs += dwc_otg_pcd.o dwc_otg_pcd_intr.o -dwc_otg-objs += dwc_otg_hcd.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o diff --git a/target/linux/ramips/files/drivers/usb/dwc_otg/dummy_audio.c b/target/linux/ramips/files/drivers/usb/dwc_otg/dummy_audio.c deleted file mode 100644 index 225decf765..0000000000 --- a/target/linux/ramips/files/drivers/usb/dwc_otg/dummy_audio.c +++ /dev/null @@ -1,1575 +0,0 @@ -/* - * zero.c -- Gadget Zero, for USB development - * - * Copyright (C) 2003-2004 David Brownell - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions, and the following disclaimer, - * without modification. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The names of the above-listed copyright holders may not be used - * to endorse or promote products derived from this software without - * specific prior written permission. - * - * ALTERNATIVELY, this software may be distributed under the terms of the - * GNU General Public License ("GPL") as published by the Free Software - * Foundation, either version 2 of that License or (at your option) any - * later version. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS - * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - - -/* - * Gadget Zero only needs two bulk endpoints, and is an example of how you - * can write a hardware-agnostic gadget driver running inside a USB device. - * - * Hardware details are visible (see CONFIG_USB_ZERO_* below) but don't - * affect most of the driver. - * - * Use it with the Linux host/master side "usbtest" driver to get a basic - * functional test of your device-side usb stack, or with "usb-skeleton". - * - * It supports two similar configurations. One sinks whatever the usb host - * writes, and in return sources zeroes. The other loops whatever the host - * writes back, so the host can read it. Module options include: - * - * buflen=N default N=4096, buffer size used - * qlen=N default N=32, how many buffers in the loopback queue - * loopdefault default false, list loopback config first - * - * Many drivers will only have one configuration, letting them be much - * simpler if they also don't support high speed operation (like this - * driver does). - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21) -# include -#else -# include -#endif - -#include - - -/*-------------------------------------------------------------------------*/ -/*-------------------------------------------------------------------------*/ - - -static int utf8_to_utf16le(const char *s, u16 *cp, unsigned len) -{ - int count = 0; - u8 c; - u16 uchar; - - /* this insists on correct encodings, though not minimal ones. - * BUT it currently rejects legit 4-byte UTF-8 code points, - * which need surrogate pairs. (Unicode 3.1 can use them.) - */ - while (len != 0 && (c = (u8) *s++) != 0) { - if (unlikely(c & 0x80)) { - // 2-byte sequence: - // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx - if ((c & 0xe0) == 0xc0) { - uchar = (c & 0x1f) << 6; - - c = (u8) *s++; - if ((c & 0xc0) != 0xc0) - goto fail; - c &= 0x3f; - uchar |= c; - - // 3-byte sequence (most CJKV characters): - // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx - } else if ((c & 0xf0) == 0xe0) { - uchar = (c & 0x0f) << 12; - - c = (u8) *s++; - if ((c & 0xc0) != 0xc0) - goto fail; - c &= 0x3f; - uchar |= c << 6; - - c = (u8) *s++; - if ((c & 0xc0) != 0xc0) - goto fail; - c &= 0x3f; - uchar |= c; - - /* no bogus surrogates */ - if (0xd800 <= uchar && uchar <= 0xdfff) - goto fail; - - // 4-byte sequence (surrogate pairs, currently rare): - // 11101110wwwwzzzzyy + 110111yyyyxxxxxx - // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx - // (uuuuu = wwww + 1) - // FIXME accept the surrogate code points (only) - - } else - goto fail; - } else - uchar = c; - put_unaligned (cpu_to_le16 (uchar), cp++); - count++; - len--; - } - return count; -fail: - return -1; -} - - -/** - * usb_gadget_get_string - fill out a string descriptor - * @table: of c strings encoded using UTF-8 - * @id: string id, from low byte of wValue in get string descriptor - * @buf: at least 256 bytes - * - * Finds the UTF-8 string matching the ID, and converts it into a - * string descriptor in utf16-le. - * Returns length of descriptor (always even) or negative errno - * - * If your driver needs stings in multiple languages, you'll probably - * "switch (wIndex) { ... }" in your ep0 string descriptor logic, - * using this routine after choosing which set of UTF-8 strings to use. - * Note that US-ASCII is a strict subset of UTF-8; any string bytes with - * the eighth bit set will be multibyte UTF-8 characters, not ISO-8859/1 - * characters (which are also widely used in C strings). - */ -int -usb_gadget_get_string (struct usb_gadget_strings *table, int id, u8 *buf) -{ - struct usb_string *s; - int len; - - /* descriptor 0 has the language id */ - if (id == 0) { - buf [0] = 4; - buf [1] = USB_DT_STRING; - buf [2] = (u8) table->language; - buf [3] = (u8) (table->language >> 8); - return 4; - } - for (s = table->strings; s && s->s; s++) - if (s->id == id) - break; - - /* unrecognized: stall. */ - if (!s || !s->s) - return -EINVAL; - - /* string descriptors have length, tag, then UTF16-LE text */ - len = min ((size_t) 126, strlen (s->s)); - memset (buf + 2, 0, 2 * len); /* zero all the bytes */ - len = utf8_to_utf16le(s->s, (u16 *)&buf[2], len); - if (len < 0) - return -EINVAL; - buf [0] = (len + 1) * 2; - buf [1] = USB_DT_STRING; - return buf [0]; -} - - -/*-------------------------------------------------------------------------*/ -/*-------------------------------------------------------------------------*/ - - -/** - * usb_descriptor_fillbuf - fill buffer with descriptors - * @buf: Buffer to be filled - * @buflen: Size of buf - * @src: Array of descriptor pointers, terminated by null pointer. - * - * Copies descriptors into the buffer, returning the length or a - * negative error code if they can't all be copied. Useful when - * assembling descriptors for an associated set of interfaces used - * as part of configuring a composite device; or in other cases where - * sets of descriptors need to be marshaled. - */ -int -usb_descriptor_fillbuf(void *buf, unsigned buflen, - const struct usb_descriptor_header **src) -{ - u8 *dest = buf; - - if (!src) - return -EINVAL; - - /* fill buffer from src[] until null descriptor ptr */ - for (; 0 != *src; src++) { - unsigned len = (*src)->bLength; - - if (len > buflen) - return -EINVAL; - memcpy(dest, *src, len); - buflen -= len; - dest += len; - } - return dest - (u8 *)buf; -} - - -/** - * usb_gadget_config_buf - builts a complete configuration descriptor - * @config: Header for the descriptor, including characteristics such - * as power requirements and number of interfaces. - * @desc: Null-terminated vector of pointers to the descriptors (interface, - * endpoint, etc) defining all functions in this device configuration. - * @buf: Buffer for the resulting configuration descriptor. - * @length: Length of buffer. If this is not big enough to hold the - * entire configuration descriptor, an error code will be returned. - * - * This copies descriptors into the response buffer, building a descriptor - * for that configuration. It returns the buffer length or a negative - * status code. The config.wTotalLength field is set to match the length - * of the result, but other descriptor fields (including power usage and - * interface count) must be set by the caller. - * - * Gadget drivers could use this when constructing a config descriptor - * in response to USB_REQ_GET_DESCRIPTOR. They will need to patch the - * resulting bDescriptorType value if USB_DT_OTHER_SPEED_CONFIG is needed. - */ -int usb_gadget_config_buf( - const struct usb_config_descriptor *config, - void *buf, - unsigned length, - const struct usb_descriptor_header **desc -) -{ - struct usb_config_descriptor *cp = buf; - int len; - - /* config descriptor first */ - if (length < USB_DT_CONFIG_SIZE || !desc) - return -EINVAL; - *cp = *config; - - /* then interface/endpoint/class/vendor/... */ - len = usb_descriptor_fillbuf(USB_DT_CONFIG_SIZE + (u8*)buf, - length - USB_DT_CONFIG_SIZE, desc); - if (len < 0) - return len; - len += USB_DT_CONFIG_SIZE; - if (len > 0xffff) - return -EINVAL; - - /* patch up the config descriptor */ - cp->bLength = USB_DT_CONFIG_SIZE; - cp->bDescriptorType = USB_DT_CONFIG; - cp->wTotalLength = cpu_to_le16(len); - cp->bmAttributes |= USB_CONFIG_ATT_ONE; - return len; -} - -/*-------------------------------------------------------------------------*/ -/*-------------------------------------------------------------------------*/ - - -#define RBUF_LEN (1024*1024) -static int rbuf_start; -static int rbuf_len; -static __u8 rbuf[RBUF_LEN]; - -/*-------------------------------------------------------------------------*/ - -#define DRIVER_VERSION "St Patrick's Day 2004" - -static const char shortname [] = "zero"; -static const char longname [] = "YAMAHA YST-MS35D USB Speaker "; - -static const char source_sink [] = "source and sink data"; -static const char loopback [] = "loop input to output"; - -/*-------------------------------------------------------------------------*/ - -/* - * driver assumes self-powered hardware, and - * has no way for users to trigger remote wakeup. - * - * this version autoconfigures as much as possible, - * which is reasonable for most "bulk-only" drivers. - */ -static const char *EP_IN_NAME; /* source */ -static const char *EP_OUT_NAME; /* sink */ - -/*-------------------------------------------------------------------------*/ - -/* big enough to hold our biggest descriptor */ -#define USB_BUFSIZ 512 - -struct zero_dev { - spinlock_t lock; - struct usb_gadget *gadget; - struct usb_request *req; /* for control responses */ - - /* when configured, we have one of two configs: - * - source data (in to host) and sink it (out from host) - * - or loop it back (out from host back in to host) - */ - u8 config; - struct usb_ep *in_ep, *out_ep; - - /* autoresume timer */ - struct timer_list resume; -}; - -#define xprintk(d,level,fmt,args...) \ - dev_printk(level , &(d)->gadget->dev , fmt , ## args) - -#ifdef DEBUG -#define DBG(dev,fmt,args...) \ - xprintk(dev , KERN_DEBUG , fmt , ## args) -#else -#define DBG(dev,fmt,args...) \ - do { } while (0) -#endif /* DEBUG */ - -#ifdef VERBOSE -#define VDBG DBG -#else -#define VDBG(dev,fmt,args...) \ - do { } while (0) -#endif /* VERBOSE */ - -#define ERROR(dev,fmt,args...) \ - xprintk(dev , KERN_ERR , fmt , ## args) -#define WARN(dev,fmt,args...) \ - xprintk(dev , KERN_WARNING , fmt , ## args) -#define INFO(dev,fmt,args...) \ - xprintk(dev , KERN_INFO , fmt , ## args) - -/*-------------------------------------------------------------------------*/ - -static unsigned buflen = 4096; -static unsigned qlen = 32; -static unsigned pattern = 0; - -module_param (buflen, uint, S_IRUGO|S_IWUSR); -module_param (qlen, uint, S_IRUGO|S_IWUSR); -module_param (pattern, uint, S_IRUGO|S_IWUSR); - -/* - * if it's nonzero, autoresume says how many seconds to wait - * before trying to wake up the host after suspend. - */ -static unsigned autoresume = 0; -module_param (autoresume, uint, 0); - -/* - * Normally the "loopback" configuration is second (index 1) so - * it's not the default. Here's where to change that order, to - * work better with hosts where config changes are problematic. - * Or controllers (like superh) that only support one config. - */ -static int loopdefault = 0; - -module_param (loopdefault, bool, S_IRUGO|S_IWUSR); - -/*-------------------------------------------------------------------------*/ - -/* Thanks to NetChip Technologies for donating this product ID. - * - * DO NOT REUSE THESE IDs with a protocol-incompatible driver!! Ever!! - * Instead: allocate your own, using normal USB-IF procedures. - */ -#ifndef CONFIG_USB_ZERO_HNPTEST -#define DRIVER_VENDOR_NUM 0x0525 /* NetChip */ -#define DRIVER_PRODUCT_NUM 0xa4a0 /* Linux-USB "Gadget Zero" */ -#else -#define DRIVER_VENDOR_NUM 0x1a0a /* OTG test device IDs */ -#define DRIVER_PRODUCT_NUM 0xbadd -#endif - -/*-------------------------------------------------------------------------*/ - -/* - * DESCRIPTORS ... most are static, but strings and (full) - * configuration descriptors are built on demand. - */ - -/* -#define STRING_MANUFACTURER 25 -#define STRING_PRODUCT 42 -#define STRING_SERIAL 101 -*/ -#define STRING_MANUFACTURER 1 -#define STRING_PRODUCT 2 -#define STRING_SERIAL 3 - -#define STRING_SOURCE_SINK 250 -#define STRING_LOOPBACK 251 - -/* - * This device advertises two configurations; these numbers work - * on a pxa250 as well as more flexible hardware. - */ -#define CONFIG_SOURCE_SINK 3 -#define CONFIG_LOOPBACK 2 - -/* -static struct usb_device_descriptor -device_desc = { - .bLength = sizeof device_desc, - .bDescriptorType = USB_DT_DEVICE, - - .bcdUSB = __constant_cpu_to_le16 (0x0200), - .bDeviceClass = USB_CLASS_VENDOR_SPEC, - - .idVendor = __constant_cpu_to_le16 (DRIVER_VENDOR_NUM), - .idProduct = __constant_cpu_to_le16 (DRIVER_PRODUCT_NUM), - .iManufacturer = STRING_MANUFACTURER, - .iProduct = STRING_PRODUCT, - .iSerialNumber = STRING_SERIAL, - .bNumConfigurations = 2, -}; -*/ -static struct usb_device_descriptor -device_desc = { - .bLength = sizeof device_desc, - .bDescriptorType = USB_DT_DEVICE, - .bcdUSB = __constant_cpu_to_le16 (0x0100), - .bDeviceClass = USB_CLASS_PER_INTERFACE, - .bDeviceSubClass = 0, - .bDeviceProtocol = 0, - .bMaxPacketSize0 = 64, - .bcdDevice = __constant_cpu_to_le16 (0x0100), - .idVendor = __constant_cpu_to_le16 (0x0499), - .idProduct = __constant_cpu_to_le16 (0x3002), - .iManufacturer = STRING_MANUFACTURER, - .iProduct = STRING_PRODUCT, - .iSerialNumber = STRING_SERIAL, - .bNumConfigurations = 1, -}; - -static struct usb_config_descriptor -z_config = { - .bLength = sizeof z_config, - .bDescriptorType = USB_DT_CONFIG, - - /* compute wTotalLength on the fly */ - .bNumInterfaces = 2, - .bConfigurationValue = 1, - .iConfiguration = 0, - .bmAttributes = 0x40, - .bMaxPower = 0, /* self-powered */ -}; - - -static struct usb_otg_descriptor -otg_descriptor = { - .bLength = sizeof otg_descriptor, - .bDescriptorType = USB_DT_OTG, - - .bmAttributes = USB_OTG_SRP, -}; - -/* one interface in each configuration */ -#ifdef CONFIG_USB_GADGET_DUALSPEED - -/* - * usb 2.0 devices need to expose both high speed and full speed - * descriptors, unless they only run at full speed. - * - * that means alternate endpoint descriptors (bigger packets) - * and a "device qualifier" ... plus more construction options - * for the config descriptor. - */ - -static struct usb_qualifier_descriptor -dev_qualifier = { - .bLength = sizeof dev_qualifier, - .bDescriptorType = USB_DT_DEVICE_QUALIFIER, - - .bcdUSB = __constant_cpu_to_le16 (0x0200), - .bDeviceClass = USB_CLASS_VENDOR_SPEC, - - .bNumConfigurations = 2, -}; - - -struct usb_cs_as_general_descriptor { - __u8 bLength; - __u8 bDescriptorType; - - __u8 bDescriptorSubType; - __u8 bTerminalLink; - __u8 bDelay; - __u16 wFormatTag; -} __attribute__ ((packed)); - -struct usb_cs_as_format_descriptor { - __u8 bLength; - __u8 bDescriptorType; - - __u8 bDescriptorSubType; - __u8 bFormatType; - __u8 bNrChannels; - __u8 bSubframeSize; - __u8 bBitResolution; - __u8 bSamfreqType; - __u8 tLowerSamFreq[3]; - __u8 tUpperSamFreq[3]; -} __attribute__ ((packed)); - -static const struct usb_interface_descriptor -z_audio_control_if_desc = { - .bLength = sizeof z_audio_control_if_desc, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = 0, - .bAlternateSetting = 0, - .bNumEndpoints = 0, - .bInterfaceClass = USB_CLASS_AUDIO, - .bInterfaceSubClass = 0x1, - .bInterfaceProtocol = 0, - .iInterface = 0, -}; - -static const struct usb_interface_descriptor -z_audio_if_desc = { - .bLength = sizeof z_audio_if_desc, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = 1, - .bAlternateSetting = 0, - .bNumEndpoints = 0, - .bInterfaceClass = USB_CLASS_AUDIO, - .bInterfaceSubClass = 0x2, - .bInterfaceProtocol = 0, - .iInterface = 0, -}; - -static const struct usb_interface_descriptor -z_audio_if_desc2 = { - .bLength = sizeof z_audio_if_desc, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = 1, - .bAlternateSetting = 1, - .bNumEndpoints = 1, - .bInterfaceClass = USB_CLASS_AUDIO, - .bInterfaceSubClass = 0x2, - .bInterfaceProtocol = 0, - .iInterface = 0, -}; - -static const struct usb_cs_as_general_descriptor -z_audio_cs_as_if_desc = { - .bLength = 7, - .bDescriptorType = 0x24, - - .bDescriptorSubType = 0x01, - .bTerminalLink = 0x01, - .bDelay = 0x0, - .wFormatTag = __constant_cpu_to_le16 (0x0001) -}; - - -static const struct usb_cs_as_format_descriptor -z_audio_cs_as_format_desc = { - .bLength = 0xe, - .bDescriptorType = 0x24, - - .bDescriptorSubType = 2, - .bFormatType = 1, - .bNrChannels = 1, - .bSubframeSize = 1, - .bBitResolution = 8, - .bSamfreqType = 0, - .tLowerSamFreq = {0x7e, 0x13, 0x00}, - .tUpperSamFreq = {0xe2, 0xd6, 0x00}, -}; - -static const struct usb_endpoint_descriptor -z_iso_ep = { - .bLength = 0x09, - .bDescriptorType = 0x05, - .bEndpointAddress = 0x04, - .bmAttributes = 0x09, - .wMaxPacketSize = 0x0038, - .bInterval = 0x01, - .bRefresh = 0x00, - .bSynchAddress = 0x00, -}; - -static char z_iso_ep2[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; - -// 9 bytes -static char z_ac_interface_header_desc[] = -{ 0x09, 0x24, 0x01, 0x00, 0x01, 0x2b, 0x00, 0x01, 0x01 }; - -// 12 bytes -static char z_0[] = {0x0c, 0x24, 0x02, 0x01, 0x01, 0x01, 0x00, 0x02, - 0x03, 0x00, 0x00, 0x00}; -// 13 bytes -static char z_1[] = {0x0d, 0x24, 0x06, 0x02, 0x01, 0x02, 0x15, 0x00, - 0x02, 0x00, 0x02, 0x00, 0x00}; -// 9 bytes -static char z_2[] = {0x09, 0x24, 0x03, 0x03, 0x01, 0x03, 0x00, 0x02, - 0x00}; - -static char za_0[] = {0x09, 0x04, 0x01, 0x02, 0x01, 0x01, 0x02, 0x00, - 0x00}; - -static char za_1[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00}; - -static char za_2[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x01, 0x08, 0x00, - 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00}; - -static char za_3[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00, - 0x00}; - -static char za_4[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; - -static char za_5[] = {0x09, 0x04, 0x01, 0x03, 0x01, 0x01, 0x02, 0x00, - 0x00}; - -static char za_6[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00}; - -static char za_7[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x02, 0x10, 0x00, - 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00}; - -static char za_8[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00, - 0x00}; - -static char za_9[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; - -static char za_10[] = {0x09, 0x04, 0x01, 0x04, 0x01, 0x01, 0x02, 0x00, - 0x00}; - -static char za_11[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00}; - -static char za_12[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x02, 0x10, 0x00, - 0x73, 0x13, 0x00, 0xe2, 0xd6, 0x00}; - -static char za_13[] = {0x09, 0x05, 0x04, 0x09, 0xe0, 0x00, 0x01, 0x00, - 0x00}; - -static char za_14[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; - -static char za_15[] = {0x09, 0x04, 0x01, 0x05, 0x01, 0x01, 0x02, 0x00, - 0x00}; - -static char za_16[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00}; - -static char za_17[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x03, 0x14, 0x00, - 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00}; - -static char za_18[] = {0x09, 0x05, 0x04, 0x09, 0xa8, 0x00, 0x01, 0x00, - 0x00}; - -static char za_19[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; - -static char za_20[] = {0x09, 0x04, 0x01, 0x06, 0x01, 0x01, 0x02, 0x00, - 0x00}; - -static char za_21[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00}; - -static char za_22[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x03, 0x14, 0x00, - 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00}; - -static char za_23[] = {0x09, 0x05, 0x04, 0x09, 0x50, 0x01, 0x01, 0x00, - 0x00}; - -static char za_24[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; - - - -static const struct usb_descriptor_header *z_function [] = { - (struct usb_descriptor_header *) &z_audio_control_if_desc, - (struct usb_descriptor_header *) &z_ac_interface_header_desc, - (struct usb_descriptor_header *) &z_0, - (struct usb_descriptor_header *) &z_1, - (struct usb_descriptor_header *) &z_2, - (struct usb_descriptor_header *) &z_audio_if_desc, - (struct usb_descriptor_header *) &z_audio_if_desc2, - (struct usb_descriptor_header *) &z_audio_cs_as_if_desc, - (struct usb_descriptor_header *) &z_audio_cs_as_format_desc, - (struct usb_descriptor_header *) &z_iso_ep, - (struct usb_descriptor_header *) &z_iso_ep2, - (struct usb_descriptor_header *) &za_0, - (struct usb_descriptor_header *) &za_1, - (struct usb_descriptor_header *) &za_2, - (struct usb_descriptor_header *) &za_3, - (struct usb_descriptor_header *) &za_4, - (struct usb_descriptor_header *) &za_5, - (struct usb_descriptor_header *) &za_6, - (struct usb_descriptor_header *) &za_7, - (struct usb_descriptor_header *) &za_8, - (struct usb_descriptor_header *) &za_9, - (struct usb_descriptor_header *) &za_10, - (struct usb_descriptor_header *) &za_11, - (struct usb_descriptor_header *) &za_12, - (struct usb_descriptor_header *) &za_13, - (struct usb_descriptor_header *) &za_14, - (struct usb_descriptor_header *) &za_15, - (struct usb_descriptor_header *) &za_16, - (struct usb_descriptor_header *) &za_17, - (struct usb_descriptor_header *) &za_18, - (struct usb_descriptor_header *) &za_19, - (struct usb_descriptor_header *) &za_20, - (struct usb_descriptor_header *) &za_21, - (struct usb_descriptor_header *) &za_22, - (struct usb_descriptor_header *) &za_23, - (struct usb_descriptor_header *) &za_24, - NULL, -}; - -/* maxpacket and other transfer characteristics vary by speed. */ -#define ep_desc(g,hs,fs) (((g)->speed==USB_SPEED_HIGH)?(hs):(fs)) - -#else - -/* if there's no high speed support, maxpacket doesn't change. */ -#define ep_desc(g,hs,fs) fs - -#endif /* !CONFIG_USB_GADGET_DUALSPEED */ - -static char manufacturer [40]; -//static char serial [40]; -static char serial [] = "Ser 00 em"; - -/* static strings, in UTF-8 */ -static struct usb_string strings [] = { - { STRING_MANUFACTURER, manufacturer, }, - { STRING_PRODUCT, longname, }, - { STRING_SERIAL, serial, }, - { STRING_LOOPBACK, loopback, }, - { STRING_SOURCE_SINK, source_sink, }, - { } /* end of list */ -}; - -static struct usb_gadget_strings stringtab = { - .language = 0x0409, /* en-us */ - .strings = strings, -}; - -/* - * config descriptors are also handcrafted. these must agree with code - * that sets configurations, and with code managing interfaces and their - * altsettings. other complexity may come from: - * - * - high speed support, including "other speed config" rules - * - multiple configurations - * - interfaces with alternate settings - * - embedded class or vendor-specific descriptors - * - * this handles high speed, and has a second config that could as easily - * have been an alternate interface setting (on most hardware). - * - * NOTE: to demonstrate (and test) more USB capabilities, this driver - * should include an altsetting to test interrupt transfers, including - * high bandwidth modes at high speed. (Maybe work like Intel's test - * device?) - */ -static int -config_buf (struct usb_gadget *gadget, u8 *buf, u8 type, unsigned index) -{ - int len; - const struct usb_descriptor_header **function; - - function = z_function; - len = usb_gadget_config_buf (&z_config, buf, USB_BUFSIZ, function); - if (len < 0) - return len; - ((struct usb_config_descriptor *) buf)->bDescriptorType = type; - return len; -} - -/*-------------------------------------------------------------------------*/ - -static struct usb_request * -alloc_ep_req (struct usb_ep *ep, unsigned length) -{ - struct usb_request *req; - - req = usb_ep_alloc_request (ep, GFP_ATOMIC); - if (req) { - req->length = length; - req->buf = usb_ep_alloc_buffer (ep, length, - &req->dma, GFP_ATOMIC); - if (!req->buf) { - usb_ep_free_request (ep, req); - req = NULL; - } - } - return req; -} - -static void free_ep_req (struct usb_ep *ep, struct usb_request *req) -{ - if (req->buf) - usb_ep_free_buffer (ep, req->buf, req->dma, req->length); - usb_ep_free_request (ep, req); -} - -/*-------------------------------------------------------------------------*/ - -/* optionally require specific source/sink data patterns */ - -static int -check_read_data ( - struct zero_dev *dev, - struct usb_ep *ep, - struct usb_request *req -) -{ - unsigned i; - u8 *buf = req->buf; - - for (i = 0; i < req->actual; i++, buf++) { - switch (pattern) { - /* all-zeroes has no synchronization issues */ - case 0: - if (*buf == 0) - continue; - break; - /* mod63 stays in sync with short-terminated transfers, - * or otherwise when host and gadget agree on how large - * each usb transfer request should be. resync is done - * with set_interface or set_config. - */ - case 1: - if (*buf == (u8)(i % 63)) - continue; - break; - } - ERROR (dev, "bad OUT byte, buf [%d] = %d\n", i, *buf); - usb_ep_set_halt (ep); - return -EINVAL; - } - return 0; -} - -/*-------------------------------------------------------------------------*/ - -static void zero_reset_config (struct zero_dev *dev) -{ - if (dev->config == 0) - return; - - DBG (dev, "reset config\n"); - - /* just disable endpoints, forcing completion of pending i/o. - * all our completion handlers free their requests in this case. - */ - if (dev->in_ep) { - usb_ep_disable (dev->in_ep); - dev->in_ep = NULL; - } - if (dev->out_ep) { - usb_ep_disable (dev->out_ep); - dev->out_ep = NULL; - } - dev->config = 0; - del_timer (&dev->resume); -} - -#define _write(f, buf, sz) (f->f_op->write(f, buf, sz, &f->f_pos)) - -static void -zero_isoc_complete (struct usb_ep *ep, struct usb_request *req) -{ - struct zero_dev *dev = ep->driver_data; - int status = req->status; - int i, j; - - switch (status) { - - case 0: /* normal completion? */ - //printk ("\nzero ---------------> isoc normal completion %d bytes\n", req->actual); - for (i=0, j=rbuf_start; iactual; i++) { - //printk ("%02x ", ((__u8*)req->buf)[i]); - rbuf[j] = ((__u8*)req->buf)[i]; - j++; - if (j >= RBUF_LEN) j=0; - } - rbuf_start = j; - //printk ("\n\n"); - - if (rbuf_len < RBUF_LEN) { - rbuf_len += req->actual; - if (rbuf_len > RBUF_LEN) { - rbuf_len = RBUF_LEN; - } - } - - break; - - /* this endpoint is normally active while we're configured */ - case -ECONNABORTED: /* hardware forced ep reset */ - case -ECONNRESET: /* request dequeued */ - case -ESHUTDOWN: /* disconnect from host */ - VDBG (dev, "%s gone (%d), %d/%d\n", ep->name, status, - req->actual, req->length); - if (ep == dev->out_ep) - check_read_data (dev, ep, req); - free_ep_req (ep, req); - return; - - case -EOVERFLOW: /* buffer overrun on read means that - * we didn't provide a big enough - * buffer. - */ - default: -#if 1 - DBG (dev, "%s complete --> %d, %d/%d\n", ep->name, - status, req->actual, req->length); -#endif - case -EREMOTEIO: /* short read */ - break; - } - - status = usb_ep_queue (ep, req, GFP_ATOMIC); - if (status) { - ERROR (dev, "kill %s: resubmit %d bytes --> %d\n", - ep->name, req->length, status); - usb_ep_set_halt (ep); - /* FIXME recover later ... somehow */ - } -} - -static struct usb_request * -zero_start_isoc_ep (struct usb_ep *ep, int gfp_flags) -{ - struct usb_request *req; - int status; - - req = alloc_ep_req (ep, 512); - if (!req) - return NULL; - - req->complete = zero_isoc_complete; - - status = usb_ep_queue (ep, req, gfp_flags); - if (status) { - struct zero_dev *dev = ep->driver_data; - - ERROR (dev, "start %s --> %d\n", ep->name, status); - free_ep_req (ep, req); - req = NULL; - } - - return req; -} - -/* change our operational config. this code must agree with the code - * that returns config descriptors, and altsetting code. - * - * it's also responsible for power management interactions. some - * configurations might not work with our current power sources. - * - * note that some device controller hardware will constrain what this - * code can do, perhaps by disallowing more than one configuration or - * by limiting configuration choices (like the pxa2xx). - */ -static int -zero_set_config (struct zero_dev *dev, unsigned number, int gfp_flags) -{ - int result = 0; - struct usb_gadget *gadget = dev->gadget; - const struct usb_endpoint_descriptor *d; - struct usb_ep *ep; - - if (number == dev->config) - return 0; - - zero_reset_config (dev); - - gadget_for_each_ep (ep, gadget) { - - if (strcmp (ep->name, "ep4") == 0) { - - d = (struct usb_endpoint_descripter *)&za_23; // isoc ep desc for audio i/f alt setting 6 - result = usb_ep_enable (ep, d); - - if (result == 0) { - ep->driver_data = dev; - dev->in_ep = ep; - - if (zero_start_isoc_ep (ep, gfp_flags) != 0) { - - dev->in_ep = ep; - continue; - } - - usb_ep_disable (ep); - result = -EIO; - } - } - - } - - dev->config = number; - return result; -} - -/*-------------------------------------------------------------------------*/ - -static void zero_setup_complete (struct usb_ep *ep, struct usb_request *req) -{ - if (req->status || req->actual != req->length) - DBG ((struct zero_dev *) ep->driver_data, - "setup complete --> %d, %d/%d\n", - req->status, req->actual, req->length); -} - -/* - * The setup() callback implements all the ep0 functionality that's - * not handled lower down, in hardware or the hardware driver (like - * device and endpoint feature flags, and their status). It's all - * housekeeping for the gadget function we're implementing. Most of - * the work is in config-specific setup. - */ -static int -zero_setup (struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl) -{ - struct zero_dev *dev = get_gadget_data (gadget); - struct usb_request *req = dev->req; - int value = -EOPNOTSUPP; - - /* usually this stores reply data in the pre-allocated ep0 buffer, - * but config change events will reconfigure hardware. - */ - req->zero = 0; - switch (ctrl->bRequest) { - - case USB_REQ_GET_DESCRIPTOR: - - switch (ctrl->wValue >> 8) { - - case USB_DT_DEVICE: - value = min (ctrl->wLength, (u16) sizeof device_desc); - memcpy (req->buf, &device_desc, value); - break; -#ifdef CONFIG_USB_GADGET_DUALSPEED - case USB_DT_DEVICE_QUALIFIER: - if (!gadget->is_dualspeed) - break; - value = min (ctrl->wLength, (u16) sizeof dev_qualifier); - memcpy (req->buf, &dev_qualifier, value); - break; - - case USB_DT_OTHER_SPEED_CONFIG: - if (!gadget->is_dualspeed) - break; - // FALLTHROUGH -#endif /* CONFIG_USB_GADGET_DUALSPEED */ - case USB_DT_CONFIG: - value = config_buf (gadget, req->buf, - ctrl->wValue >> 8, - ctrl->wValue & 0xff); - if (value >= 0) - value = min (ctrl->wLength, (u16) value); - break; - - case USB_DT_STRING: - /* wIndex == language code. - * this driver only handles one language, you can - * add string tables for other languages, using - * any UTF-8 characters - */ - value = usb_gadget_get_string (&stringtab, - ctrl->wValue & 0xff, req->buf); - if (value >= 0) { - value = min (ctrl->wLength, (u16) value); - } - break; - } - break; - - /* currently two configs, two speeds */ - case USB_REQ_SET_CONFIGURATION: - if (ctrl->bRequestType != 0) - goto unknown; - - spin_lock (&dev->lock); - value = zero_set_config (dev, ctrl->wValue, GFP_ATOMIC); - spin_unlock (&dev->lock); - break; - case USB_REQ_GET_CONFIGURATION: - if (ctrl->bRequestType != USB_DIR_IN) - goto unknown; - *(u8 *)req->buf = dev->config; - value = min (ctrl->wLength, (u16) 1); - break; - - /* until we add altsetting support, or other interfaces, - * only 0/0 are possible. pxa2xx only supports 0/0 (poorly) - * and already killed pending endpoint I/O. - */ - case USB_REQ_SET_INTERFACE: - - if (ctrl->bRequestType != USB_RECIP_INTERFACE) - goto unknown; - spin_lock (&dev->lock); - if (dev->config) { - u8 config = dev->config; - - /* resets interface configuration, forgets about - * previous transaction state (queued bufs, etc) - * and re-inits endpoint state (toggle etc) - * no response queued, just zero status == success. - * if we had more than one interface we couldn't - * use this "reset the config" shortcut. - */ - zero_reset_config (dev); - zero_set_config (dev, config, GFP_ATOMIC); - value = 0; - } - spin_unlock (&dev->lock); - break; - case USB_REQ_GET_INTERFACE: - if ((ctrl->bRequestType == 0x21) && (ctrl->wIndex == 0x02)) { - value = ctrl->wLength; - break; - } - else { - if (ctrl->bRequestType != (USB_DIR_IN|USB_RECIP_INTERFACE)) - goto unknown; - if (!dev->config) - break; - if (ctrl->wIndex != 0) { - value = -EDOM; - break; - } - *(u8 *)req->buf = 0; - value = min (ctrl->wLength, (u16) 1); - } - break; - - /* - * These are the same vendor-specific requests supported by - * Intel's USB 2.0 compliance test devices. We exceed that - * device spec by allowing multiple-packet requests. - */ - case 0x5b: /* control WRITE test -- fill the buffer */ - if (ctrl->bRequestType != (USB_DIR_OUT|USB_TYPE_VENDOR)) - goto unknown; - if (ctrl->wValue || ctrl->wIndex) - break; - /* just read that many bytes into the buffer */ - if (ctrl->wLength > USB_BUFSIZ) - break; - value = ctrl->wLength; - break; - case 0x5c: /* control READ test -- return the buffer */ - if (ctrl->bRequestType != (USB_DIR_IN|USB_TYPE_VENDOR)) - goto unknown; - if (ctrl->wValue || ctrl->wIndex) - break; - /* expect those bytes are still in the buffer; send back */ - if (ctrl->wLength > USB_BUFSIZ - || ctrl->wLength != req->length) - break; - value = ctrl->wLength; - break; - - case 0x01: // SET_CUR - case 0x02: - case 0x03: - case 0x04: - case 0x05: - value = ctrl->wLength; - break; - case 0x81: - switch (ctrl->wValue) { - case 0x0201: - case 0x0202: - ((u8*)req->buf)[0] = 0x00; - ((u8*)req->buf)[1] = 0xe3; - break; - case 0x0300: - case 0x0500: - ((u8*)req->buf)[0] = 0x00; - break; - } - //((u8*)req->buf)[0] = 0x81; - //((u8*)req->buf)[1] = 0x81; - value = ctrl->wLength; - break; - case 0x82: - switch (ctrl->wValue) { - case 0x0201: - case 0x0202: - ((u8*)req->buf)[0] = 0x00; - ((u8*)req->buf)[1] = 0xc3; - break; - case 0x0300: - case 0x0500: - ((u8*)req->buf)[0] = 0x00; - break; - } - //((u8*)req->buf)[0] = 0x82; - //((u8*)req->buf)[1] = 0x82; - value = ctrl->wLength; - break; - case 0x83: - switch (ctrl->wValue) { - case 0x0201: - case 0x0202: - ((u8*)req->buf)[0] = 0x00; - ((u8*)req->buf)[1] = 0x00; - break; - case 0x0300: - ((u8*)req->buf)[0] = 0x60; - break; - case 0x0500: - ((u8*)req->buf)[0] = 0x18; - break; - } - //((u8*)req->buf)[0] = 0x83; - //((u8*)req->buf)[1] = 0x83; - value = ctrl->wLength; - break; - case 0x84: - switch (ctrl->wValue) { - case 0x0201: - case 0x0202: - ((u8*)req->buf)[0] = 0x00; - ((u8*)req->buf)[1] = 0x01; - break; - case 0x0300: - case 0x0500: - ((u8*)req->buf)[0] = 0x08; - break; - } - //((u8*)req->buf)[0] = 0x84; - //((u8*)req->buf)[1] = 0x84; - value = ctrl->wLength; - break; - case 0x85: - ((u8*)req->buf)[0] = 0x85; - ((u8*)req->buf)[1] = 0x85; - value = ctrl->wLength; - break; - - - default: -unknown: - printk("unknown control req%02x.%02x v%04x i%04x l%d\n", - ctrl->bRequestType, ctrl->bRequest, - ctrl->wValue, ctrl->wIndex, ctrl->wLength); - } - - /* respond with data transfer before status phase? */ - if (value >= 0) { - req->length = value; - req->zero = value < ctrl->wLength - && (value % gadget->ep0->maxpacket) == 0; - value = usb_ep_queue (gadget->ep0, req, GFP_ATOMIC); - if (value < 0) { - DBG (dev, "ep_queue < 0 --> %d\n", value); - req->status = 0; - zero_setup_complete (gadget->ep0, req); - } - } - - /* device either stalls (value < 0) or reports success */ - return value; -} - -static void -zero_disconnect (struct usb_gadget *gadget) -{ - struct zero_dev *dev = get_gadget_data (gadget); - unsigned long flags; - - spin_lock_irqsave (&dev->lock, flags); - zero_reset_config (dev); - - /* a more significant application might have some non-usb - * activities to quiesce here, saving resources like power - * or pushing the notification up a network stack. - */ - spin_unlock_irqrestore (&dev->lock, flags); - - /* next we may get setup() calls to enumerate new connections; - * or an unbind() during shutdown (including removing module). - */ -} - -static void -zero_autoresume (unsigned long _dev) -{ - struct zero_dev *dev = (struct zero_dev *) _dev; - int status; - - /* normally the host would be woken up for something - * more significant than just a timer firing... - */ - if (dev->gadget->speed != USB_SPEED_UNKNOWN) { - status = usb_gadget_wakeup (dev->gadget); - DBG (dev, "wakeup --> %d\n", status); - } -} - -/*-------------------------------------------------------------------------*/ - -static void -zero_unbind (struct usb_gadget *gadget) -{ - struct zero_dev *dev = get_gadget_data (gadget); - - DBG (dev, "unbind\n"); - - /* we've already been disconnected ... no i/o is active */ - if (dev->req) - free_ep_req (gadget->ep0, dev->req); - del_timer_sync (&dev->resume); - kfree (dev); - set_gadget_data (gadget, NULL); -} - -static int -zero_bind (struct usb_gadget *gadget) -{ - struct zero_dev *dev; - //struct usb_ep *ep; - - printk("binding\n"); - /* - * DRIVER POLICY CHOICE: you may want to do this differently. - * One thing to avoid is reusing a bcdDevice revision code - * with different host-visible configurations or behavior - * restrictions -- using ep1in/ep2out vs ep1out/ep3in, etc - */ - //device_desc.bcdDevice = __constant_cpu_to_le16 (0x0201); - - - /* ok, we made sense of the hardware ... */ - dev = kmalloc (sizeof *dev, SLAB_KERNEL); - if (!dev) - return -ENOMEM; - memset (dev, 0, sizeof *dev); - spin_lock_init (&dev->lock); - dev->gadget = gadget; - set_gadget_data (gadget, dev); - - /* preallocate control response and buffer */ - dev->req = usb_ep_alloc_request (gadget->ep0, GFP_KERNEL); - if (!dev->req) - goto enomem; - dev->req->buf = usb_ep_alloc_buffer (gadget->ep0, USB_BUFSIZ, - &dev->req->dma, GFP_KERNEL); - if (!dev->req->buf) - goto enomem; - - dev->req->complete = zero_setup_complete; - - device_desc.bMaxPacketSize0 = gadget->ep0->maxpacket; - -#ifdef CONFIG_USB_GADGET_DUALSPEED - /* assume ep0 uses the same value for both speeds ... */ - dev_qualifier.bMaxPacketSize0 = device_desc.bMaxPacketSize0; - - /* and that all endpoints are dual-speed */ - //hs_source_desc.bEndpointAddress = fs_source_desc.bEndpointAddress; - //hs_sink_desc.bEndpointAddress = fs_sink_desc.bEndpointAddress; -#endif - - usb_gadget_set_selfpowered (gadget); - - init_timer (&dev->resume); - dev->resume.function = zero_autoresume; - dev->resume.data = (unsigned long) dev; - - gadget->ep0->driver_data = dev; - - INFO (dev, "%s, version: " DRIVER_VERSION "\n", longname); - INFO (dev, "using %s, OUT %s IN %s\n", gadget->name, - EP_OUT_NAME, EP_IN_NAME); - - snprintf (manufacturer, sizeof manufacturer, - UTS_SYSNAME " " UTS_RELEASE " with %s", - gadget->name); - - return 0; - -enomem: - zero_unbind (gadget); - return -ENOMEM; -} - -/*-------------------------------------------------------------------------*/ - -static void -zero_suspend (struct usb_gadget *gadget) -{ - struct zero_dev *dev = get_gadget_data (gadget); - - if (gadget->speed == USB_SPEED_UNKNOWN) - return; - - if (autoresume) { - mod_timer (&dev->resume, jiffies + (HZ * autoresume)); - DBG (dev, "suspend, wakeup in %d seconds\n", autoresume); - } else - DBG (dev, "suspend\n"); -} - -static void -zero_resume (struct usb_gadget *gadget) -{ - struct zero_dev *dev = get_gadget_data (gadget); - - DBG (dev, "resume\n"); - del_timer (&dev->resume); -} - - -/*-------------------------------------------------------------------------*/ - -static struct usb_gadget_driver zero_driver = { -#ifdef CONFIG_USB_GADGET_DUALSPEED - .speed = USB_SPEED_HIGH, -#else - .speed = USB_SPEED_FULL, -#endif - .function = (char *) longname, - .bind = zero_bind, - .unbind = zero_unbind, - - .setup = zero_setup, - .disconnect = zero_disconnect, - - .suspend = zero_suspend, - .resume = zero_resume, - - .driver = { - .name = (char *) shortname, - // .shutdown = ... - // .suspend = ... - // .resume = ... - }, -}; - -MODULE_AUTHOR ("David Brownell"); -MODULE_LICENSE ("Dual BSD/GPL"); - -static struct proc_dir_entry *pdir, *pfile; - -static int isoc_read_data (char *page, char **start, - off_t off, int count, - int *eof, void *data) -{ - int i; - static int c = 0; - static int done = 0; - static int s = 0; - -/* - printk ("\ncount: %d\n", count); - printk ("rbuf_start: %d\n", rbuf_start); - printk ("rbuf_len: %d\n", rbuf_len); - printk ("off: %d\n", off); - printk ("start: %p\n\n", *start); -*/ - if (done) { - c = 0; - done = 0; - *eof = 1; - return 0; - } - - if (c == 0) { - if (rbuf_len == RBUF_LEN) - s = rbuf_start; - else s = 0; - } - - for (i=0; i= rbuf_len) { - *eof = 1; - done = 1; - } - - - return i; -} - -static int __init init (void) -{ - - int retval = 0; - - pdir = proc_mkdir("isoc_test", NULL); - if(pdir == NULL) { - retval = -ENOMEM; - printk("Error creating dir\n"); - goto done; - } - pdir->owner = THIS_MODULE; - - pfile = create_proc_read_entry("isoc_data", - 0444, pdir, - isoc_read_data, - NULL); - if (pfile == NULL) { - retval = -ENOMEM; - printk("Error creating file\n"); - goto no_file; - } - pfile->owner = THIS_MODULE; - - return usb_gadget_register_driver (&zero_driver); - - no_file: - remove_proc_entry("isoc_data", NULL); - done: - return retval; -} -module_init (init); - -static void __exit cleanup (void) -{ - - usb_gadget_unregister_driver (&zero_driver); - - remove_proc_entry("isoc_data", pdir); - remove_proc_entry("isoc_test", NULL); -} -module_exit (cleanup); diff --git a/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_attr.c b/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_attr.c deleted file mode 100644 index 85435379d0..0000000000 --- a/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_attr.c +++ /dev/null @@ -1,966 +0,0 @@ -/* ========================================================================== - * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.c $ - * $Revision: 1.2 $ - * $Date: 2008-11-21 05:39:15 $ - * $Change: 1064918 $ - * - * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, - * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless - * otherwise expressly agreed to in writing between Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ - -/** @file - * - * The diagnostic interface will provide access to the controller for - * bringing up the hardware and testing. The Linux driver attributes - * feature will be used to provide the Linux Diagnostic - * Interface. These attributes are accessed through sysfs. - */ - -/** @page "Linux Module Attributes" - * - * The Linux module attributes feature is used to provide the Linux - * Diagnostic Interface. These attributes are accessed through sysfs. - * The diagnostic interface will provide access to the controller for - * bringing up the hardware and testing. - - - The following table shows the attributes. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Name Description Access
mode Returns the current mode: 0 for device mode, 1 for host mode Read
hnpcapable Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register. - Read returns the current value. Read/Write
srpcapable Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register. - Read returns the current value. Read/Write
hnp Initiates the Host Negotiation Protocol. Read returns the status. Read/Write
srp Initiates the Session Request Protocol. Read returns the status. Read/Write
buspower Gets or sets the Power State of the bus (0 - Off or 1 - On) Read/Write
bussuspend Suspends the USB bus. Read/Write
busconnected Gets the connection status of the bus Read
gotgctl Gets or sets the Core Control Status Register. Read/Write
gusbcfg Gets or sets the Core USB Configuration Register Read/Write
grxfsiz Gets or sets the Receive FIFO Size Register Read/Write
gnptxfsiz Gets or sets the non-periodic Transmit Size Register Read/Write
gpvndctl Gets or sets the PHY Vendor Control Register Read/Write
ggpio Gets the value in the lower 16-bits of the General Purpose IO Register - or sets the upper 16 bits. Read/Write
guid Gets or sets the value of the User ID Register Read/Write
gsnpsid Gets the value of the Synopsys ID Regester Read
devspeed Gets or sets the device speed setting in the DCFG register Read/Write
enumspeed Gets the device enumeration Speed. Read
hptxfsiz Gets the value of the Host Periodic Transmit FIFO Read
hprt0 Gets or sets the value in the Host Port Control and Status Register Read/Write
regoffset Sets the register offset for the next Register Access Read/Write
regvalue Gets or sets the value of the register at the offset in the regoffset attribute. Read/Write
remote_wakeup On read, shows the status of Remote Wakeup. On write, initiates a remote - wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote - Wakeup signalling bit in the Device Control Register is set for 1 - milli-second. Read/Write
regdump Dumps the contents of core registers. Read
spramdump Dumps the contents of core registers. Read
hcddump Dumps the current HCD state. Read
hcd_frrem Shows the average value of the Frame Remaining - field in the Host Frame Number/Frame Remaining register when an SOF interrupt - occurs. This can be used to determine the average interrupt latency. Also - shows the average Frame Remaining value for start_transfer and the "a" and - "b" sample points. The "a" and "b" sample points may be used during debugging - bto determine how long it takes to execute a section of the HCD code. Read
rd_reg_test Displays the time required to read the GNPTXFSIZ register many times - (the output shows the number of times the register is read). - Read
wr_reg_test Displays the time required to write the GNPTXFSIZ register many times - (the output shows the number of times the register is written). - Read
- - Example usage: - To get the current mode: - cat /sys/devices/lm0/mode - - To power down the USB: - echo 0 > /sys/devices/lm0/buspower - */ - -#include -#include -#include -#include -#include -#include -#include -#include /* permission constants */ -#include - -#include - -#include "linux/dwc_otg_plat.h" -#include "dwc_otg_attr.h" -#include "dwc_otg_driver.h" -#include "dwc_otg_pcd.h" -#include "dwc_otg_hcd.h" - -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -/* - * MACROs for defining sysfs attribute - */ -#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ -static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ -{ \ - dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \ - uint32_t val; \ - val = dwc_read_reg32 (_addr_); \ - val = (val & (_mask_)) >> _shift_; \ - return sprintf (buf, "%s = 0x%x\n", _string_, val); \ -} -#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ -static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \ - const char *buf, size_t count) \ -{ \ - dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \ - uint32_t set = simple_strtoul(buf, NULL, 16); \ - uint32_t clear = set; \ - clear = ((~clear) << _shift_) & _mask_; \ - set = (set << _shift_) & _mask_; \ - dev_dbg(_dev, "Storing Address=0x%08x Set=0x%08x Clear=0x%08x\n", (uint32_t)_addr_, set, clear); \ - dwc_modify_reg32(_addr_, clear, set); \ - return count; \ -} - -/* - * MACROs for defining sysfs attribute for 32-bit registers - */ -#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \ -static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ -{ \ - dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \ - uint32_t val; \ - val = dwc_read_reg32 (_addr_); \ - return sprintf (buf, "%s = 0x%08x\n", _string_, val); \ -} -#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \ -static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \ - const char *buf, size_t count) \ -{ \ - dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \ - uint32_t val = simple_strtoul(buf, NULL, 16); \ - dev_dbg(_dev, "Storing Address=0x%08x Val=0x%08x\n", (uint32_t)_addr_, val); \ - dwc_write_reg32(_addr_, val); \ - return count; \ -} - -#else - -/* - * MACROs for defining sysfs attribute - */ -#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ -static ssize_t _otg_attr_name_##_show (struct device *_dev, char *buf) \ -{ \ - dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\ - uint32_t val; \ - val = dwc_read_reg32 (_addr_); \ - val = (val & (_mask_)) >> _shift_; \ - return sprintf (buf, "%s = 0x%x\n", _string_, val); \ -} -#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ -static ssize_t _otg_attr_name_##_store (struct device *_dev, const char *buf, size_t count) \ -{ \ - dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\ - uint32_t set = simple_strtoul(buf, NULL, 16); \ - uint32_t clear = set; \ - clear = ((~clear) << _shift_) & _mask_; \ - set = (set << _shift_) & _mask_; \ - dev_dbg(_dev, "Storing Address=0x%08x Set=0x%08x Clear=0x%08x\n", (uint32_t)_addr_, set, clear); \ - dwc_modify_reg32(_addr_, clear, set); \ - return count; \ -} - -/* - * MACROs for defining sysfs attribute for 32-bit registers - */ -#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \ -static ssize_t _otg_attr_name_##_show (struct device *_dev, char *buf) \ -{ \ - dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\ - uint32_t val; \ - val = dwc_read_reg32 (_addr_); \ - return sprintf (buf, "%s = 0x%08x\n", _string_, val); \ -} -#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \ -static ssize_t _otg_attr_name_##_store (struct device *_dev, const char *buf, size_t count) \ -{ \ - dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\ - uint32_t val = simple_strtoul(buf, NULL, 16); \ - dev_dbg(_dev, "Storing Address=0x%08x Val=0x%08x\n", (uint32_t)_addr_, val); \ - dwc_write_reg32(_addr_, val); \ - return count; \ -} - -#endif - -#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ -DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ -DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ -DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store); - -#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ -DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ -DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL); - -#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \ -DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \ -DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \ -DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store); - -#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \ -DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \ -DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL); - - -/** @name Functions for Show/Store of Attributes */ -/**@{*/ - -/** - * Show the register offset of the Register Access. - */ -static ssize_t regoffset_show( struct device *_dev, -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) - struct device_attribute *attr, -#endif - char *buf) -{ - dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); - return snprintf(buf, sizeof("0xFFFFFFFF\n")+1,"0x%08x\n", otg_dev->reg_offset); -} - -/** - * Set the register offset for the next Register Access Read/Write - */ -static ssize_t regoffset_store( struct device *_dev, -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) - struct device_attribute *attr, -#endif - const char *buf, - size_t count ) -{ - dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); - - uint32_t offset = simple_strtoul(buf, NULL, 16); - //dev_dbg(_dev, "Offset=0x%08x\n", offset); - if (offset < 0x00040000 ) { - otg_dev->reg_offset = offset; - } - else { - dev_err( _dev, "invalid offset\n" ); - } - - return count; -} -DEVICE_ATTR(regoffset, S_IRUGO|S_IWUSR, (void *)regoffset_show, regoffset_store); - - -/** - * Show the value of the register at the offset in the reg_offset - * attribute. - */ -static ssize_t regvalue_show( struct device *_dev, -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) - struct device_attribute *attr, -#endif - char *buf) -{ - dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); - - uint32_t val; - volatile uint32_t *addr; - - if (otg_dev->reg_offset != 0xFFFFFFFF && - 0 != otg_dev->base) { - /* Calculate the address */ - addr = (uint32_t*)(otg_dev->reg_offset + - (uint8_t*)otg_dev->base); - //dev_dbg(_dev, "@0x%08x\n", (unsigned)addr); - val = dwc_read_reg32( addr ); - return snprintf(buf, sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n")+1, - "Reg@0x%06x = 0x%08x\n", - otg_dev->reg_offset, val); - } - else { - dev_err(_dev, "Invalid offset (0x%0x)\n", - otg_dev->reg_offset); - return sprintf(buf, "invalid offset\n" ); - } -} - -/** - * Store the value in the register at the offset in the reg_offset - * attribute. - * - */ -static ssize_t regvalue_store( struct device *_dev, -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) - struct device_attribute *attr, -#endif - const char *buf, - size_t count ) -{ - dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); - - volatile uint32_t * addr; - uint32_t val = simple_strtoul(buf, NULL, 16); - //dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val); - if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) { - /* Calculate the address */ - addr = (uint32_t*)(otg_dev->reg_offset + - (uint8_t*)otg_dev->base); - //dev_dbg(_dev, "@0x%08x\n", (unsigned)addr); - dwc_write_reg32( addr, val ); - } - else { - dev_err(_dev, "Invalid Register Offset (0x%08x)\n", - otg_dev->reg_offset); - } - return count; -} -DEVICE_ATTR(regvalue, S_IRUGO|S_IWUSR, regvalue_show, regvalue_store); - -/* - * Attributes - */ -DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<20),20,"Mode"); -DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<9),9,"Mode"); -DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<8),8,"Mode"); - -//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode"); -//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode"); -DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected,otg_dev->core_if->host_if->hprt0,0x01,0,"Bus Connected"); - -DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl,&(otg_dev->core_if->core_global_regs->gotgctl),"GOTGCTL"); -DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,&(otg_dev->core_if->core_global_regs->gusbcfg),"GUSBCFG"); -DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,&(otg_dev->core_if->core_global_regs->grxfsiz),"GRXFSIZ"); -DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,&(otg_dev->core_if->core_global_regs->gnptxfsiz),"GNPTXFSIZ"); -DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,&(otg_dev->core_if->core_global_regs->gpvndctl),"GPVNDCTL"); -DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,&(otg_dev->core_if->core_global_regs->ggpio),"GGPIO"); -DWC_OTG_DEVICE_ATTR_REG32_RW(guid,&(otg_dev->core_if->core_global_regs->guid),"GUID"); -DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,&(otg_dev->core_if->core_global_regs->gsnpsid),"GSNPSID"); -DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dcfg),0x3,0,"Device Speed"); -DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dsts),0x6,1,"Device Enumeration Speed"); - -DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,&(otg_dev->core_if->core_global_regs->hptxfsiz),"HPTXFSIZ"); -DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0,otg_dev->core_if->host_if->hprt0,"HPRT0"); - - -/** - * @todo Add code to initiate the HNP. - */ -/** - * Show the HNP status bit - */ -static ssize_t hnp_show( struct device *_dev, -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) - struct device_attribute *attr, -#endif - char *buf) -{ - dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); - - gotgctl_data_t val; - val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl)); - return sprintf (buf, "HstNegScs = 0x%x\n", val.b.hstnegscs); -} - -/** - * Set the HNP Request bit - */ -static ssize_t hnp_store( struct device *_dev, -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) - struct device_attribute *attr, -#endif - const char *buf, - size_t count ) -{ - dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); - - uint32_t in = simple_strtoul(buf, NULL, 16); - uint32_t *addr = (uint32_t *)&(otg_dev->core_if->core_global_regs->gotgctl); - gotgctl_data_t mem; - mem.d32 = dwc_read_reg32(addr); - mem.b.hnpreq = in; - dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32); - dwc_write_reg32(addr, mem.d32); - return count; -} -DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store); - -/** - * @todo Add code to initiate the SRP. - */ -/** - * Show the SRP status bit - */ -static ssize_t srp_show( struct device *_dev, -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) - struct device_attribute *attr, -#endif - char *buf) -{ -#ifndef DWC_HOST_ONLY - dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); - - gotgctl_data_t val; - val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl)); - return sprintf (buf, "SesReqScs = 0x%x\n", val.b.sesreqscs); -#else - return sprintf(buf, "Host Only Mode!\n"); -#endif -} - - - -/** - * Set the SRP Request bit - */ -static ssize_t srp_store( struct device *_dev, -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) - struct device_attribute *attr, -#endif - const char *buf, - size_t count ) -{ -#ifndef DWC_HOST_ONLY - dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); - - dwc_otg_pcd_initiate_srp(otg_dev->pcd); -#endif - return count; -} -DEVICE_ATTR(srp, 0644, srp_show, srp_store); - -/** - * @todo Need to do more for power on/off? - */ -/** - * Show the Bus Power status - */ -static ssize_t buspower_show( struct device *_dev, -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) - struct device_attribute *attr, -#endif - char *buf) -{ - dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); - - hprt0_data_t val; - val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0); - return sprintf (buf, "Bus Power = 0x%x\n", val.b.prtpwr); -} - - -/** - * Set the Bus Power status - */ -static ssize_t buspower_store( struct device *_dev, -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) - struct device_attribute *attr, -#endif - const char *buf, - size_t count ) -{ - dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); - - uint32_t on = simple_strtoul(buf, NULL, 16); - uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0; - hprt0_data_t mem; - - mem.d32 = dwc_read_reg32(addr); - mem.b.prtpwr = on; - - //dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32); - dwc_write_reg32(addr, mem.d32); - - return count; -} -DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store); - -/** - * @todo Need to do more for suspend? - */ -/** - * Show the Bus Suspend status - */ -static ssize_t bussuspend_show( struct device *_dev, -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) - struct device_attribute *attr, -#endif - char *buf) -{ - dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); - - hprt0_data_t val; - val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0); - return sprintf (buf, "Bus Suspend = 0x%x\n", val.b.prtsusp); -} - -/** - * Set the Bus Suspend status - */ -static ssize_t bussuspend_store( struct device *_dev, -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) - struct device_attribute *attr, -#endif - const char *buf, - size_t count ) -{ - dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); - - uint32_t in = simple_strtoul(buf, NULL, 16); - uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0; - hprt0_data_t mem; - mem.d32 = dwc_read_reg32(addr); - mem.b.prtsusp = in; - dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32); - dwc_write_reg32(addr, mem.d32); - return count; -} -DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store); - -/** - * Show the status of Remote Wakeup. - */ -static ssize_t remote_wakeup_show( struct device *_dev, -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) - struct device_attribute *attr, -#endif - char *buf) -{ -#ifndef DWC_HOST_ONLY - dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); - - dctl_data_t val; - val.d32 = - dwc_read_reg32( &otg_dev->core_if->dev_if->dev_global_regs->dctl); - return sprintf( buf, "Remote Wakeup = %d Enabled = %d\n", - val.b.rmtwkupsig, otg_dev->pcd->remote_wakeup_enable); -#else - return sprintf(buf, "Host Only Mode!\n"); -#endif -} -/** - * Initiate a remote wakeup of the host. The Device control register - * Remote Wakeup Signal bit is written if the PCD Remote wakeup enable - * flag is set. - * - */ -static ssize_t remote_wakeup_store( struct device *_dev, -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) - struct device_attribute *attr, -#endif - const char *buf, - size_t count ) -{ -#ifndef DWC_HOST_ONLY - dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); - - uint32_t val = simple_strtoul(buf, NULL, 16); - if (val&1) { - dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1); - } - else { - dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0); - } -#endif - return count; -} -DEVICE_ATTR(remote_wakeup, S_IRUGO|S_IWUSR, remote_wakeup_show, - remote_wakeup_store); - -/** - * Dump global registers and either host or device registers (depending on the - * current mode of the core). - */ -static ssize_t regdump_show( struct device *_dev, -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) - struct device_attribute *attr, -#endif - char *buf) -{ - dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); - - dwc_otg_dump_global_registers( otg_dev->core_if); - if (dwc_otg_is_host_mode(otg_dev->core_if)) { - dwc_otg_dump_host_registers( otg_dev->core_if); - } else { - dwc_otg_dump_dev_registers( otg_dev->core_if); - - } - return sprintf( buf, "Register Dump\n" ); -} - -DEVICE_ATTR(regdump, S_IRUGO|S_IWUSR, regdump_show, 0); - -/** - * Dump global registers and either host or device registers (depending on the - * current mode of the core). - */ -static ssize_t spramdump_show( struct device *_dev, -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) - struct device_attribute *attr, -#endif - char *buf) -{ - dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); - - dwc_otg_dump_spram( otg_dev->core_if); - - return sprintf( buf, "SPRAM Dump\n" ); -} - -DEVICE_ATTR(spramdump, S_IRUGO|S_IWUSR, spramdump_show, 0); - -/** - * Dump the current hcd state. - */ -static ssize_t hcddump_show( struct device *_dev, -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) - struct device_attribute *attr, -#endif - char *buf) -{ -#ifndef DWC_DEVICE_ONLY - dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); - - dwc_otg_hcd_dump_state(otg_dev->hcd); -#endif - return sprintf( buf, "HCD Dump\n" ); -} - -DEVICE_ATTR(hcddump, S_IRUGO|S_IWUSR, hcddump_show, 0); - -/** - * Dump the average frame remaining at SOF. This can be used to - * determine average interrupt latency. Frame remaining is also shown for - * start transfer and two additional sample points. - */ -static ssize_t hcd_frrem_show( struct device *_dev, -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) - struct device_attribute *attr, -#endif - char *buf) -{ -#ifndef DWC_DEVICE_ONLY - dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); - - dwc_otg_hcd_dump_frrem(otg_dev->hcd); -#endif - return sprintf( buf, "HCD Dump Frame Remaining\n" ); -} - -DEVICE_ATTR(hcd_frrem, S_IRUGO|S_IWUSR, hcd_frrem_show, 0); - -/** - * Displays the time required to read the GNPTXFSIZ register many times (the - * output shows the number of times the register is read). - */ -#define RW_REG_COUNT 10000000 -#define MSEC_PER_JIFFIE 1000/HZ -static ssize_t rd_reg_test_show( struct device *_dev, -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) - struct device_attribute *attr, -#endif - char *buf) -{ - dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); - - int i; - int time; - int start_jiffies; - - printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n", - HZ, MSEC_PER_JIFFIE, loops_per_jiffy); - start_jiffies = jiffies; - for (i = 0; i < RW_REG_COUNT; i++) { - dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz); - } - time = jiffies - start_jiffies; - return sprintf( buf, "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n", - RW_REG_COUNT, time * MSEC_PER_JIFFIE, time ); -} - -DEVICE_ATTR(rd_reg_test, S_IRUGO|S_IWUSR, rd_reg_test_show, 0); - -/** - * Displays the time required to write the GNPTXFSIZ register many times (the - * output shows the number of times the register is written). - */ -static ssize_t wr_reg_test_show( struct device *_dev, -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) - struct device_attribute *attr, -#endif - char *buf) -{ - dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); - - uint32_t reg_val; - int i; - int time; - int start_jiffies; - - printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n", - HZ, MSEC_PER_JIFFIE, loops_per_jiffy); - reg_val = dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz); - start_jiffies = jiffies; - for (i = 0; i < RW_REG_COUNT; i++) { - dwc_write_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz, reg_val); - } - time = jiffies - start_jiffies; - return sprintf( buf, "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n", - RW_REG_COUNT, time * MSEC_PER_JIFFIE, time); -} - -DEVICE_ATTR(wr_reg_test, S_IRUGO|S_IWUSR, wr_reg_test_show, 0); -/**@}*/ - -/** - * Create the device files - */ -void dwc_otg_attr_create (struct device *dev) -{ - int error; - - error = device_create_file(dev, &dev_attr_regoffset); - error = device_create_file(dev, &dev_attr_regvalue); - error = device_create_file(dev, &dev_attr_mode); - error = device_create_file(dev, &dev_attr_hnpcapable); - error = device_create_file(dev, &dev_attr_srpcapable); - error = device_create_file(dev, &dev_attr_hnp); - error = device_create_file(dev, &dev_attr_srp); - error = device_create_file(dev, &dev_attr_buspower); - error = device_create_file(dev, &dev_attr_bussuspend); - error = device_create_file(dev, &dev_attr_busconnected); - error = device_create_file(dev, &dev_attr_gotgctl); - error = device_create_file(dev, &dev_attr_gusbcfg); - error = device_create_file(dev, &dev_attr_grxfsiz); - error = device_create_file(dev, &dev_attr_gnptxfsiz); - error = device_create_file(dev, &dev_attr_gpvndctl); - error = device_create_file(dev, &dev_attr_ggpio); - error = device_create_file(dev, &dev_attr_guid); - error = device_create_file(dev, &dev_attr_gsnpsid); - error = device_create_file(dev, &dev_attr_devspeed); - error = device_create_file(dev, &dev_attr_enumspeed); - error = device_create_file(dev, &dev_attr_hptxfsiz); - error = device_create_file(dev, &dev_attr_hprt0); - error = device_create_file(dev, &dev_attr_remote_wakeup); - error = device_create_file(dev, &dev_attr_regdump); - error = device_create_file(dev, &dev_attr_spramdump); - error = device_create_file(dev, &dev_attr_hcddump); - error = device_create_file(dev, &dev_attr_hcd_frrem); - error = device_create_file(dev, &dev_attr_rd_reg_test); - error = device_create_file(dev, &dev_attr_wr_reg_test); -} - -/** - * Remove the device files - */ -void dwc_otg_attr_remove (struct device *dev) -{ - device_remove_file(dev, &dev_attr_regoffset); - device_remove_file(dev, &dev_attr_regvalue); - device_remove_file(dev, &dev_attr_mode); - device_remove_file(dev, &dev_attr_hnpcapable); - device_remove_file(dev, &dev_attr_srpcapable); - device_remove_file(dev, &dev_attr_hnp); - device_remove_file(dev, &dev_attr_srp); - device_remove_file(dev, &dev_attr_buspower); - device_remove_file(dev, &dev_attr_bussuspend); - device_remove_file(dev, &dev_attr_busconnected); - device_remove_file(dev, &dev_attr_gotgctl); - device_remove_file(dev, &dev_attr_gusbcfg); - device_remove_file(dev, &dev_attr_grxfsiz); - device_remove_file(dev, &dev_attr_gnptxfsiz); - device_remove_file(dev, &dev_attr_gpvndctl); - device_remove_file(dev, &dev_attr_ggpio); - device_remove_file(dev, &dev_attr_guid); - device_remove_file(dev, &dev_attr_gsnpsid); - device_remove_file(dev, &dev_attr_devspeed); - device_remove_file(dev, &dev_attr_enumspeed); - device_remove_file(dev, &dev_attr_hptxfsiz); - device_remove_file(dev, &dev_attr_hprt0); - device_remove_file(dev, &dev_attr_remote_wakeup); - device_remove_file(dev, &dev_attr_regdump); - device_remove_file(dev, &dev_attr_spramdump); - device_remove_file(dev, &dev_attr_hcddump); - device_remove_file(dev, &dev_attr_hcd_frrem); - device_remove_file(dev, &dev_attr_rd_reg_test); - device_remove_file(dev, &dev_attr_wr_reg_test); -} diff --git a/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_attr.h b/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_attr.h deleted file mode 100644 index 0862b2711b..0000000000 --- a/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_attr.h +++ /dev/null @@ -1,67 +0,0 @@ -/* ========================================================================== - * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.h $ - * $Revision: 1.2 $ - * $Date: 2008-11-21 05:39:15 $ - * $Change: 477051 $ - * - * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, - * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless - * otherwise expressly agreed to in writing between Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ - -#if !defined(__DWC_OTG_ATTR_H__) -#define __DWC_OTG_ATTR_H__ - -/** @file - * This file contains the interface to the Linux device attributes. - */ -extern struct device_attribute dev_attr_regoffset; -extern struct device_attribute dev_attr_regvalue; - -extern struct device_attribute dev_attr_mode; -extern struct device_attribute dev_attr_hnpcapable; -extern struct device_attribute dev_attr_srpcapable; -extern struct device_attribute dev_attr_hnp; -extern struct device_attribute dev_attr_srp; -extern struct device_attribute dev_attr_buspower; -extern struct device_attribute dev_attr_bussuspend; -extern struct device_attribute dev_attr_busconnected; -extern struct device_attribute dev_attr_gotgctl; -extern struct device_attribute dev_attr_gusbcfg; -extern struct device_attribute dev_attr_grxfsiz; -extern struct device_attribute dev_attr_gnptxfsiz; -extern struct device_attribute dev_attr_gpvndctl; -extern struct device_attribute dev_attr_ggpio; -extern struct device_attribute dev_attr_guid; -extern struct device_attribute dev_attr_gsnpsid; -extern struct device_attribute dev_attr_devspeed; -extern struct device_attribute dev_attr_enumspeed; -extern struct device_attribute dev_attr_hptxfsiz; -extern struct device_attribute dev_attr_hprt0; - -void dwc_otg_attr_create (struct device *dev); -void dwc_otg_attr_remove (struct device *dev); - -#endif diff --git a/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_cil.c b/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_cil.c deleted file mode 100644 index 89aa83ec90..0000000000 --- a/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_cil.c +++ /dev/null @@ -1,3692 +0,0 @@ -/* ========================================================================== - * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.c $ - * $Revision: 1.7 $ - * $Date: 2008-12-22 11:43:05 $ - * $Change: 1117667 $ - * - * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, - * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless - * otherwise expressly agreed to in writing between Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ - -/** @file - * - * The Core Interface Layer provides basic services for accessing and - * managing the DWC_otg hardware. These services are used by both the - * Host Controller Driver and the Peripheral Controller Driver. - * - * The CIL manages the memory map for the core so that the HCD and PCD - * don't have to do this separately. It also handles basic tasks like - * reading/writing the registers and data FIFOs in the controller. - * Some of the data access functions provide encapsulation of several - * operations required to perform a task, such as writing multiple - * registers to start a transfer. Finally, the CIL performs basic - * services that are not specific to either the host or device modes - * of operation. These services include management of the OTG Host - * Negotiation Protocol (HNP) and Session Request Protocol (SRP). A - * Diagnostic API is also provided to allow testing of the controller - * hardware. - * - * The Core Interface Layer has the following requirements: - * - Provides basic controller operations. - * - Minimal use of OS services. - * - The OS services used will be abstracted by using inline functions - * or macros. - * - */ -#include -#include -#ifdef DEBUG -#include -#endif - -#include "linux/dwc_otg_plat.h" -#include "dwc_otg_regs.h" -#include "dwc_otg_cil.h" - -/* Included only to access hc->qh for non-dword buffer handling - * TODO: account it - */ -#include "dwc_otg_hcd.h" - -/** - * This function is called to initialize the DWC_otg CSR data - * structures. The register addresses in the device and host - * structures are initialized from the base address supplied by the - * caller. The calling function must make the OS calls to get the - * base address of the DWC_otg controller registers. The core_params - * argument holds the parameters that specify how the core should be - * configured. - * - * @param[in] reg_base_addr Base address of DWC_otg core registers - * @param[in] core_params Pointer to the core configuration parameters - * - */ -dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *reg_base_addr, - dwc_otg_core_params_t *core_params) -{ - dwc_otg_core_if_t *core_if = 0; - dwc_otg_dev_if_t *dev_if = 0; - dwc_otg_host_if_t *host_if = 0; - uint8_t *reg_base = (uint8_t *)reg_base_addr; - int i = 0; - - DWC_DEBUGPL(DBG_CILV, "%s(%p,%p)\n", __func__, reg_base_addr, core_params); - - core_if = kmalloc(sizeof(dwc_otg_core_if_t), GFP_KERNEL); - - if (core_if == 0) { - DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_core_if_t failed\n"); - return 0; - } - - memset(core_if, 0, sizeof(dwc_otg_core_if_t)); - - core_if->core_params = core_params; - core_if->core_global_regs = (dwc_otg_core_global_regs_t *)reg_base; - - /* - * Allocate the Device Mode structures. - */ - dev_if = kmalloc(sizeof(dwc_otg_dev_if_t), GFP_KERNEL); - - if (dev_if == 0) { - DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n"); - kfree(core_if); - return 0; - } - - dev_if->dev_global_regs = - (dwc_otg_device_global_regs_t *)(reg_base + DWC_DEV_GLOBAL_REG_OFFSET); - - for (i=0; iin_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *) - (reg_base + DWC_DEV_IN_EP_REG_OFFSET + - (i * DWC_EP_REG_OFFSET)); - - dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *) - (reg_base + DWC_DEV_OUT_EP_REG_OFFSET + - (i * DWC_EP_REG_OFFSET)); - DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n", - i, &dev_if->in_ep_regs[i]->diepctl); - DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n", - i, &dev_if->out_ep_regs[i]->doepctl); - } - - dev_if->speed = 0; // unknown - - core_if->dev_if = dev_if; - - /* - * Allocate the Host Mode structures. - */ - host_if = kmalloc(sizeof(dwc_otg_host_if_t), GFP_KERNEL); - - if (host_if == 0) { - DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_host_if_t failed\n"); - kfree(dev_if); - kfree(core_if); - return 0; - } - - host_if->host_global_regs = (dwc_otg_host_global_regs_t *) - (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET); - - host_if->hprt0 = (uint32_t*)(reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET); - - for (i=0; ihc_regs[i] = (dwc_otg_hc_regs_t *) - (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET + - (i * DWC_OTG_CHAN_REGS_OFFSET)); - DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n", - i, &host_if->hc_regs[i]->hcchar); - } - - host_if->num_host_channels = MAX_EPS_CHANNELS; - core_if->host_if = host_if; - - for (i=0; idata_fifo[i] = - (uint32_t *)(reg_base + DWC_OTG_DATA_FIFO_OFFSET + - (i * DWC_OTG_DATA_FIFO_SIZE)); - DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08x\n", - i, (unsigned)core_if->data_fifo[i]); - } - - core_if->pcgcctl = (uint32_t*)(reg_base + DWC_OTG_PCGCCTL_OFFSET); - - /* - * Store the contents of the hardware configuration registers here for - * easy access later. - */ - core_if->hwcfg1.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg1); - core_if->hwcfg2.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg2); - core_if->hwcfg3.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg3); - core_if->hwcfg4.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg4); - - DWC_DEBUGPL(DBG_CILV,"hwcfg1=%08x\n",core_if->hwcfg1.d32); - DWC_DEBUGPL(DBG_CILV,"hwcfg2=%08x\n",core_if->hwcfg2.d32); - DWC_DEBUGPL(DBG_CILV,"hwcfg3=%08x\n",core_if->hwcfg3.d32); - DWC_DEBUGPL(DBG_CILV,"hwcfg4=%08x\n",core_if->hwcfg4.d32); - - core_if->hcfg.d32 = dwc_read_reg32(&core_if->host_if->host_global_regs->hcfg); - core_if->dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg); - - DWC_DEBUGPL(DBG_CILV,"hcfg=%08x\n",core_if->hcfg.d32); - DWC_DEBUGPL(DBG_CILV,"dcfg=%08x\n",core_if->dcfg.d32); - - DWC_DEBUGPL(DBG_CILV,"op_mode=%0x\n",core_if->hwcfg2.b.op_mode); - DWC_DEBUGPL(DBG_CILV,"arch=%0x\n",core_if->hwcfg2.b.architecture); - DWC_DEBUGPL(DBG_CILV,"num_dev_ep=%d\n",core_if->hwcfg2.b.num_dev_ep); - DWC_DEBUGPL(DBG_CILV,"num_host_chan=%d\n",core_if->hwcfg2.b.num_host_chan); - DWC_DEBUGPL(DBG_CILV,"nonperio_tx_q_depth=0x%0x\n",core_if->hwcfg2.b.nonperio_tx_q_depth); - DWC_DEBUGPL(DBG_CILV,"host_perio_tx_q_depth=0x%0x\n",core_if->hwcfg2.b.host_perio_tx_q_depth); - DWC_DEBUGPL(DBG_CILV,"dev_token_q_depth=0x%0x\n",core_if->hwcfg2.b.dev_token_q_depth); - - DWC_DEBUGPL(DBG_CILV,"Total FIFO SZ=%d\n", core_if->hwcfg3.b.dfifo_depth); - DWC_DEBUGPL(DBG_CILV,"xfer_size_cntr_width=%0x\n", core_if->hwcfg3.b.xfer_size_cntr_width); - - /* - * Set the SRP sucess bit for FS-I2c - */ - core_if->srp_success = 0; - core_if->srp_timer_started = 0; - - - /* - * Create new workqueue and init works - */ - core_if->wq_otg = create_singlethread_workqueue("dwc_otg"); - if(core_if->wq_otg == 0) { - DWC_DEBUGPL(DBG_CIL, "Creation of wq_otg failed\n"); - kfree(host_if); - kfree(dev_if); - kfree(core_if); - return 0 * HZ; - } - - - -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) - - INIT_WORK(&core_if->w_conn_id, w_conn_id_status_change, core_if); - INIT_WORK(&core_if->w_wkp, w_wakeup_detected, core_if); - -#else - - INIT_WORK(&core_if->w_conn_id, w_conn_id_status_change); - INIT_DELAYED_WORK(&core_if->w_wkp, w_wakeup_detected); - -#endif - return core_if; -} - -/** - * This function frees the structures allocated by dwc_otg_cil_init(). - * - * @param[in] core_if The core interface pointer returned from - * dwc_otg_cil_init(). - * - */ -void dwc_otg_cil_remove(dwc_otg_core_if_t *core_if) -{ - /* Disable all interrupts */ - dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, 1, 0); - dwc_write_reg32(&core_if->core_global_regs->gintmsk, 0); - - if (core_if->wq_otg) { - destroy_workqueue(core_if->wq_otg); - } - if (core_if->dev_if) { - kfree(core_if->dev_if); - } - if (core_if->host_if) { - kfree(core_if->host_if); - } - kfree(core_if); -} - -/** - * This function enables the controller's Global Interrupt in the AHB Config - * register. - * - * @param[in] core_if Programming view of DWC_otg controller. - */ -void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t *core_if) -{ - gahbcfg_data_t ahbcfg = { .d32 = 0}; - ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ - dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32); -} - -/** - * This function disables the controller's Global Interrupt in the AHB Config - * register. - * - * @param[in] core_if Programming view of DWC_otg controller. - */ -void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t *core_if) -{ - gahbcfg_data_t ahbcfg = { .d32 = 0}; - ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ - dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0); -} - -/** - * This function initializes the commmon interrupts, used in both - * device and host modes. - * - * @param[in] core_if Programming view of the DWC_otg controller - * - */ -static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t *core_if) -{ - dwc_otg_core_global_regs_t *global_regs = - core_if->core_global_regs; - gintmsk_data_t intr_mask = { .d32 = 0}; - - /* Clear any pending OTG Interrupts */ - dwc_write_reg32(&global_regs->gotgint, 0xFFFFFFFF); - - /* Clear any pending interrupts */ - dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF); - - /* - * Enable the interrupts in the GINTMSK. - */ - intr_mask.b.modemismatch = 1; - intr_mask.b.otgintr = 1; - - if (!core_if->dma_enable) { - intr_mask.b.rxstsqlvl = 1; - } - - intr_mask.b.conidstschng = 1; - intr_mask.b.wkupintr = 1; - intr_mask.b.disconnect = 1; - intr_mask.b.usbsuspend = 1; - intr_mask.b.sessreqintr = 1; - dwc_write_reg32(&global_regs->gintmsk, intr_mask.d32); -} - -/** - * Initializes the FSLSPClkSel field of the HCFG register depending on the PHY - * type. - */ -static void init_fslspclksel(dwc_otg_core_if_t *core_if) -{ - uint32_t val; - hcfg_data_t hcfg; - - if (((core_if->hwcfg2.b.hs_phy_type == 2) && - (core_if->hwcfg2.b.fs_phy_type == 1) && - (core_if->core_params->ulpi_fs_ls)) || - (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) { - /* Full speed PHY */ - val = DWC_HCFG_48_MHZ; - } - else { - /* High speed PHY running at full speed or high speed */ - val = DWC_HCFG_30_60_MHZ; - } - - DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val); - hcfg.d32 = dwc_read_reg32(&core_if->host_if->host_global_regs->hcfg); - hcfg.b.fslspclksel = val; - dwc_write_reg32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32); -} - -/** - * Initializes the DevSpd field of the DCFG register depending on the PHY type - * and the enumeration speed of the device. - */ -static void init_devspd(dwc_otg_core_if_t *core_if) -{ - uint32_t val; - dcfg_data_t dcfg; - - if (((core_if->hwcfg2.b.hs_phy_type == 2) && - (core_if->hwcfg2.b.fs_phy_type == 1) && - (core_if->core_params->ulpi_fs_ls)) || - (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) { - /* Full speed PHY */ - val = 0x3; - } - else if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) { - /* High speed PHY running at full speed */ - val = 0x1; - } - else { - /* High speed PHY running at high speed */ - val = 0x0; - } - - DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val); - - dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg); - dcfg.b.devspd = val; - dwc_write_reg32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32); -} - -/** - * This function calculates the number of IN EPS - * using GHWCFG1 and GHWCFG2 registers values - * - * @param core_if Programming view of the DWC_otg controller - */ -static uint32_t calc_num_in_eps(dwc_otg_core_if_t *core_if) -{ - uint32_t num_in_eps = 0; - uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep; - uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 3; - uint32_t num_tx_fifos = core_if->hwcfg4.b.num_in_eps; - int i; - - - for(i = 0; i < num_eps; ++i) - { - if(!(hwcfg1 & 0x1)) - num_in_eps++; - - hwcfg1 >>= 2; - } - - if(core_if->hwcfg4.b.ded_fifo_en) { - num_in_eps = (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps; - } - - return num_in_eps; -} - - -/** - * This function calculates the number of OUT EPS - * using GHWCFG1 and GHWCFG2 registers values - * - * @param core_if Programming view of the DWC_otg controller - */ -static uint32_t calc_num_out_eps(dwc_otg_core_if_t *core_if) -{ - uint32_t num_out_eps = 0; - uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep; - uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 2; - int i; - - for(i = 0; i < num_eps; ++i) - { - if(!(hwcfg1 & 0x2)) - num_out_eps++; - - hwcfg1 >>= 2; - } - return num_out_eps; -} -/** - * This function initializes the DWC_otg controller registers and - * prepares the core for device mode or host mode operation. - * - * @param core_if Programming view of the DWC_otg controller - * - */ -void dwc_otg_core_init(dwc_otg_core_if_t *core_if) -{ - int i = 0; - dwc_otg_core_global_regs_t *global_regs = - core_if->core_global_regs; - dwc_otg_dev_if_t *dev_if = core_if->dev_if; - gahbcfg_data_t ahbcfg = { .d32 = 0 }; - gusbcfg_data_t usbcfg = { .d32 = 0 }; - gi2cctl_data_t i2cctl = { .d32 = 0 }; - - DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p)\n", core_if); - - /* Common Initialization */ - - usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); - -// usbcfg.b.tx_end_delay = 1; - /* Program the ULPI External VBUS bit if needed */ - usbcfg.b.ulpi_ext_vbus_drv = - (core_if->core_params->phy_ulpi_ext_vbus == DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0; - - /* Set external TS Dline pulsing */ - usbcfg.b.term_sel_dl_pulse = (core_if->core_params->ts_dline == 1) ? 1 : 0; - dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32); - - - /* Reset the Controller */ - dwc_otg_core_reset(core_if); - - /* Initialize parameters from Hardware configuration registers. */ - dev_if->num_in_eps = calc_num_in_eps(core_if); - dev_if->num_out_eps = calc_num_out_eps(core_if); - - - DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n", core_if->hwcfg4.b.num_dev_perio_in_ep); - - for (i=0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) - { - dev_if->perio_tx_fifo_size[i] = - dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16; - DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n", - i, dev_if->perio_tx_fifo_size[i]); - } - - for (i=0; i < core_if->hwcfg4.b.num_in_eps; i++) - { - dev_if->tx_fifo_size[i] = - dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16; - DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n", - i, dev_if->perio_tx_fifo_size[i]); - } - - core_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth; - core_if->rx_fifo_size = - dwc_read_reg32(&global_regs->grxfsiz); - core_if->nperio_tx_fifo_size = - dwc_read_reg32(&global_regs->gnptxfsiz) >> 16; - - DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", core_if->total_fifo_size); - DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", core_if->rx_fifo_size); - DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n", core_if->nperio_tx_fifo_size); - - /* This programming sequence needs to happen in FS mode before any other - * programming occurs */ - if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) && - (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) { - /* If FS mode with FS PHY */ - - /* core_init() is now called on every switch so only call the - * following for the first time through. */ - if (!core_if->phy_init_done) { - core_if->phy_init_done = 1; - DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n"); - usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); - usbcfg.b.physel = 1; - dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32); - - /* Reset after a PHY select */ - dwc_otg_core_reset(core_if); - } - - /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also - * do this on HNP Dev/Host mode switches (done in dev_init and - * host_init). */ - if (dwc_otg_is_host_mode(core_if)) { - init_fslspclksel(core_if); - } - else { - init_devspd(core_if); - } - - if (core_if->core_params->i2c_enable) { - DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n"); - /* Program GUSBCFG.OtgUtmifsSel to I2C */ - usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); - usbcfg.b.otgutmifssel = 1; - dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32); - - /* Program GI2CCTL.I2CEn */ - i2cctl.d32 = dwc_read_reg32(&global_regs->gi2cctl); - i2cctl.b.i2cdevaddr = 1; - i2cctl.b.i2cen = 0; - dwc_write_reg32 (&global_regs->gi2cctl, i2cctl.d32); - i2cctl.b.i2cen = 1; - dwc_write_reg32 (&global_regs->gi2cctl, i2cctl.d32); - } - - } /* endif speed == DWC_SPEED_PARAM_FULL */ - - else { - /* High speed PHY. */ - if (!core_if->phy_init_done) { - core_if->phy_init_done = 1; - /* HS PHY parameters. These parameters are preserved - * during soft reset so only program the first time. Do - * a soft reset immediately after setting phyif. */ - usbcfg.b.ulpi_utmi_sel = core_if->core_params->phy_type; - if (usbcfg.b.ulpi_utmi_sel == 1) { - /* ULPI interface */ - usbcfg.b.phyif = 0; - usbcfg.b.ddrsel = core_if->core_params->phy_ulpi_ddr; - } - else { - /* UTMI+ interface */ - if (core_if->core_params->phy_utmi_width == 16) { - usbcfg.b.phyif = 1; - } - else { - usbcfg.b.phyif = 0; - } - } - - dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); - - /* Reset after setting the PHY parameters */ - dwc_otg_core_reset(core_if); - } - } - - if ((core_if->hwcfg2.b.hs_phy_type == 2) && - (core_if->hwcfg2.b.fs_phy_type == 1) && - (core_if->core_params->ulpi_fs_ls)) { - DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n"); - usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); - usbcfg.b.ulpi_fsls = 1; - usbcfg.b.ulpi_clk_sus_m = 1; - dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); - } - else { - usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); - usbcfg.b.ulpi_fsls = 0; - usbcfg.b.ulpi_clk_sus_m = 0; - dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); - } - - /* Program the GAHBCFG Register.*/ - switch (core_if->hwcfg2.b.architecture) { - - case DWC_SLAVE_ONLY_ARCH: - DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n"); - ahbcfg.b.nptxfemplvl_txfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY; - ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY; - core_if->dma_enable = 0; - core_if->dma_desc_enable = 0; - break; - - case DWC_EXT_DMA_ARCH: - DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n"); - ahbcfg.b.hburstlen = core_if->core_params->dma_burst_size; - core_if->dma_enable = (core_if->core_params->dma_enable != 0); - core_if->dma_desc_enable = (core_if->core_params->dma_desc_enable != 0); - break; - - case DWC_INT_DMA_ARCH: - DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n"); - ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR; - core_if->dma_enable = (core_if->core_params->dma_enable != 0); - core_if->dma_desc_enable = (core_if->core_params->dma_desc_enable != 0); - break; - - } - ahbcfg.b.dmaenable = core_if->dma_enable; - dwc_write_reg32(&global_regs->gahbcfg, ahbcfg.d32); - - core_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en; - - core_if->pti_enh_enable = core_if->core_params->pti_enable != 0; - core_if->multiproc_int_enable = core_if->core_params->mpi_enable; - DWC_PRINT("Periodic Transfer Interrupt Enhancement - %s\n", ((core_if->pti_enh_enable) ? "enabled": "disabled")); - DWC_PRINT("Multiprocessor Interrupt Enhancement - %s\n", ((core_if->multiproc_int_enable) ? "enabled": "disabled")); - - /* - * Program the GUSBCFG register. - */ - usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); - - switch (core_if->hwcfg2.b.op_mode) { - case DWC_MODE_HNP_SRP_CAPABLE: - usbcfg.b.hnpcap = (core_if->core_params->otg_cap == - DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE); - usbcfg.b.srpcap = (core_if->core_params->otg_cap != - DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); - break; - - case DWC_MODE_SRP_ONLY_CAPABLE: - usbcfg.b.hnpcap = 0; - usbcfg.b.srpcap = (core_if->core_params->otg_cap != - DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); - break; - - case DWC_MODE_NO_HNP_SRP_CAPABLE: - usbcfg.b.hnpcap = 0; - usbcfg.b.srpcap = 0; - break; - - case DWC_MODE_SRP_CAPABLE_DEVICE: - usbcfg.b.hnpcap = 0; - usbcfg.b.srpcap = (core_if->core_params->otg_cap != - DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); - break; - - case DWC_MODE_NO_SRP_CAPABLE_DEVICE: - usbcfg.b.hnpcap = 0; - usbcfg.b.srpcap = 0; - break; - - case DWC_MODE_SRP_CAPABLE_HOST: - usbcfg.b.hnpcap = 0; - usbcfg.b.srpcap = (core_if->core_params->otg_cap != - DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); - break; - - case DWC_MODE_NO_SRP_CAPABLE_HOST: - usbcfg.b.hnpcap = 0; - usbcfg.b.srpcap = 0; - break; - } - - dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); - - /* Enable common interrupts */ - dwc_otg_enable_common_interrupts(core_if); - - /* Do device or host intialization based on mode during PCD - * and HCD initialization */ - if (dwc_otg_is_host_mode(core_if)) { - DWC_DEBUGPL(DBG_ANY, "Host Mode\n"); - core_if->op_state = A_HOST; - } - else { - DWC_DEBUGPL(DBG_ANY, "Device Mode\n"); - core_if->op_state = B_PERIPHERAL; -#ifdef DWC_DEVICE_ONLY - dwc_otg_core_dev_init(core_if); -#endif - } -} - - -/** - * This function enables the Device mode interrupts. - * - * @param core_if Programming view of DWC_otg controller - */ -void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *core_if) -{ - gintmsk_data_t intr_mask = { .d32 = 0}; - dwc_otg_core_global_regs_t *global_regs = - core_if->core_global_regs; - - DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__); - - /* Disable all interrupts. */ - dwc_write_reg32(&global_regs->gintmsk, 0); - - /* Clear any pending interrupts */ - dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF); - - /* Enable the common interrupts */ - dwc_otg_enable_common_interrupts(core_if); - - /* Enable interrupts */ - intr_mask.b.usbreset = 1; - intr_mask.b.enumdone = 1; - - if(!core_if->multiproc_int_enable) { - intr_mask.b.inepintr = 1; - intr_mask.b.outepintr = 1; - } - - intr_mask.b.erlysuspend = 1; - - if(core_if->en_multiple_tx_fifo == 0) { - intr_mask.b.epmismatch = 1; - } - - -#ifdef DWC_EN_ISOC - if(core_if->dma_enable) { - if(core_if->dma_desc_enable == 0) { - if(core_if->pti_enh_enable) { - dctl_data_t dctl = { .d32 = 0 }; - dctl.b.ifrmnum = 1; - dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32); - } else { - intr_mask.b.incomplisoin = 1; - intr_mask.b.incomplisoout = 1; - } - } - } else { - intr_mask.b.incomplisoin = 1; - intr_mask.b.incomplisoout = 1; - } -#endif // DWC_EN_ISOC - -/** @todo NGS: Should this be a module parameter? */ -#ifdef USE_PERIODIC_EP - intr_mask.b.isooutdrop = 1; - intr_mask.b.eopframe = 1; - intr_mask.b.incomplisoin = 1; - intr_mask.b.incomplisoout = 1; -#endif - - dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32); - - DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__, - dwc_read_reg32(&global_regs->gintmsk)); -} - -/** - * This function initializes the DWC_otg controller registers for - * device mode. - * - * @param core_if Programming view of DWC_otg controller - * - */ -void dwc_otg_core_dev_init(dwc_otg_core_if_t *core_if) -{ - int i; - dwc_otg_core_global_regs_t *global_regs = - core_if->core_global_regs; - dwc_otg_dev_if_t *dev_if = core_if->dev_if; - dwc_otg_core_params_t *params = core_if->core_params; - dcfg_data_t dcfg = { .d32 = 0}; - grstctl_t resetctl = { .d32 = 0 }; - uint32_t rx_fifo_size; - fifosize_data_t nptxfifosize; - fifosize_data_t txfifosize; - dthrctl_data_t dthrctl; - fifosize_data_t ptxfifosize; - - /* Restart the Phy Clock */ - dwc_write_reg32(core_if->pcgcctl, 0); - - /* Device configuration register */ - init_devspd(core_if); - dcfg.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dcfg); - dcfg.b.descdma = (core_if->dma_desc_enable) ? 1 : 0; - dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80; - - dwc_write_reg32(&dev_if->dev_global_regs->dcfg, dcfg.d32); - - /* Configure data FIFO sizes */ - if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) { - DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n", core_if->total_fifo_size); - DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n", params->dev_rx_fifo_size); - DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n", params->dev_nperio_tx_fifo_size); - - /* Rx FIFO */ - DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n", - dwc_read_reg32(&global_regs->grxfsiz)); - - rx_fifo_size = params->dev_rx_fifo_size; - dwc_write_reg32(&global_regs->grxfsiz, rx_fifo_size); - - DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n", - dwc_read_reg32(&global_regs->grxfsiz)); - - /** Set Periodic Tx FIFO Mask all bits 0 */ - core_if->p_tx_msk = 0; - - /** Set Tx FIFO Mask all bits 0 */ - core_if->tx_msk = 0; - - if(core_if->en_multiple_tx_fifo == 0) { - /* Non-periodic Tx FIFO */ - DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n", - dwc_read_reg32(&global_regs->gnptxfsiz)); - - nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size; - nptxfifosize.b.startaddr = params->dev_rx_fifo_size; - - dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32); - - DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n", - dwc_read_reg32(&global_regs->gnptxfsiz)); - - /**@todo NGS: Fix Periodic FIFO Sizing! */ - /* - * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15. - * Indexes of the FIFO size module parameters in the - * dev_perio_tx_fifo_size array and the FIFO size registers in - * the dptxfsiz array run from 0 to 14. - */ - /** @todo Finish debug of this */ - ptxfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth; - for (i=0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) - { - ptxfifosize.b.depth = params->dev_perio_tx_fifo_size[i]; - DWC_DEBUGPL(DBG_CIL, "initial dptxfsiz_dieptxf[%d]=%08x\n", i, - dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i])); - dwc_write_reg32(&global_regs->dptxfsiz_dieptxf[i], - ptxfifosize.d32); - DWC_DEBUGPL(DBG_CIL, "new dptxfsiz_dieptxf[%d]=%08x\n", i, - dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i])); - ptxfifosize.b.startaddr += ptxfifosize.b.depth; - } - } - else { - /* - * Tx FIFOs These FIFOs are numbered from 1 to 15. - * Indexes of the FIFO size module parameters in the - * dev_tx_fifo_size array and the FIFO size registers in - * the dptxfsiz_dieptxf array run from 0 to 14. - */ - - - /* Non-periodic Tx FIFO */ - DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n", - dwc_read_reg32(&global_regs->gnptxfsiz)); - - nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size; - nptxfifosize.b.startaddr = params->dev_rx_fifo_size; - - dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32); - - DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n", - dwc_read_reg32(&global_regs->gnptxfsiz)); - - txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth; - /* - Modify by kaiker ,for RT3052 device mode config - - In RT3052,Since the _core_if->hwcfg4.b.num_dev_perio_in_ep is - configed to 0 so these TX_FIF0 not config.IN EP will can't - more than 1 if not modify it. - - */ -#if 1 - for (i=1 ; i <= dev_if->num_in_eps; i++) -#else - for (i=1; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++) -#endif - { - - txfifosize.b.depth = params->dev_tx_fifo_size[i]; - - DWC_DEBUGPL(DBG_CIL, "initial dptxfsiz_dieptxf[%d]=%08x\n", i, - dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i])); - - dwc_write_reg32(&global_regs->dptxfsiz_dieptxf[i-1], - txfifosize.d32); - - DWC_DEBUGPL(DBG_CIL, "new dptxfsiz_dieptxf[%d]=%08x\n", i, - dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i-1])); - - txfifosize.b.startaddr += txfifosize.b.depth; - } - } - } - /* Flush the FIFOs */ - dwc_otg_flush_tx_fifo(core_if, 0x10); /* all Tx FIFOs */ - dwc_otg_flush_rx_fifo(core_if); - - /* Flush the Learning Queue. */ - resetctl.b.intknqflsh = 1; - dwc_write_reg32(&core_if->core_global_regs->grstctl, resetctl.d32); - - /* Clear all pending Device Interrupts */ - - if(core_if->multiproc_int_enable) { - } - - /** @todo - if the condition needed to be checked - * or in any case all pending interrutps should be cleared? - */ - if(core_if->multiproc_int_enable) { - for(i = 0; i < core_if->dev_if->num_in_eps; ++i) { - dwc_write_reg32(&dev_if->dev_global_regs->diepeachintmsk[i], 0); - } - - for(i = 0; i < core_if->dev_if->num_out_eps; ++i) { - dwc_write_reg32(&dev_if->dev_global_regs->doepeachintmsk[i], 0); - } - - dwc_write_reg32(&dev_if->dev_global_regs->deachint, 0xFFFFFFFF); - dwc_write_reg32(&dev_if->dev_global_regs->deachintmsk, 0); - } else { - dwc_write_reg32(&dev_if->dev_global_regs->diepmsk, 0); - dwc_write_reg32(&dev_if->dev_global_regs->doepmsk, 0); - dwc_write_reg32(&dev_if->dev_global_regs->daint, 0xFFFFFFFF); - dwc_write_reg32(&dev_if->dev_global_regs->daintmsk, 0); - } - - for (i=0; i <= dev_if->num_in_eps; i++) - { - depctl_data_t depctl; - depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl); - if (depctl.b.epena) { - depctl.d32 = 0; - depctl.b.epdis = 1; - depctl.b.snak = 1; - } - else { - depctl.d32 = 0; - } - - dwc_write_reg32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32); - - - dwc_write_reg32(&dev_if->in_ep_regs[i]->dieptsiz, 0); - dwc_write_reg32(&dev_if->in_ep_regs[i]->diepdma, 0); - dwc_write_reg32(&dev_if->in_ep_regs[i]->diepint, 0xFF); - } - - for (i=0; i <= dev_if->num_out_eps; i++) - { - depctl_data_t depctl; - depctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[i]->doepctl); - if (depctl.b.epena) { - depctl.d32 = 0; - depctl.b.epdis = 1; - depctl.b.snak = 1; - } - else { - depctl.d32 = 0; - } - - dwc_write_reg32(&dev_if->out_ep_regs[i]->doepctl, depctl.d32); - - dwc_write_reg32(&dev_if->out_ep_regs[i]->doeptsiz, 0); - dwc_write_reg32(&dev_if->out_ep_regs[i]->doepdma, 0); - dwc_write_reg32(&dev_if->out_ep_regs[i]->doepint, 0xFF); - } - - if(core_if->en_multiple_tx_fifo && core_if->dma_enable) { - dev_if->non_iso_tx_thr_en = params->thr_ctl & 0x1; - dev_if->iso_tx_thr_en = (params->thr_ctl >> 1) & 0x1; - dev_if->rx_thr_en = (params->thr_ctl >> 2) & 0x1; - - dev_if->rx_thr_length = params->rx_thr_length; - dev_if->tx_thr_length = params->tx_thr_length; - - dev_if->setup_desc_index = 0; - - dthrctl.d32 = 0; - dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en; - dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en; - dthrctl.b.tx_thr_len = dev_if->tx_thr_length; - dthrctl.b.rx_thr_en = dev_if->rx_thr_en; - dthrctl.b.rx_thr_len = dev_if->rx_thr_length; - - dwc_write_reg32(&dev_if->dev_global_regs->dtknqr3_dthrctl, dthrctl.d32); - - DWC_DEBUGPL(DBG_CIL, "Non ISO Tx Thr - %d\nISO Tx Thr - %d\nRx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n", - dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en, dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len, dthrctl.b.rx_thr_len); - - } - - dwc_otg_enable_device_interrupts(core_if); - - { - diepmsk_data_t msk = { .d32 = 0 }; - msk.b.txfifoundrn = 1; - if(core_if->multiproc_int_enable) { - dwc_modify_reg32(&dev_if->dev_global_regs->diepeachintmsk[0], msk.d32, msk.d32); - } else { - dwc_modify_reg32(&dev_if->dev_global_regs->diepmsk, msk.d32, msk.d32); - } - } - - - if(core_if->multiproc_int_enable) { - /* Set NAK on Babble */ - dctl_data_t dctl = { .d32 = 0}; - dctl.b.nakonbble = 1; - dwc_modify_reg32(&dev_if->dev_global_regs->dctl, 0, dctl.d32); - } -} - -/** - * This function enables the Host mode interrupts. - * - * @param core_if Programming view of DWC_otg controller - */ -void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *core_if) -{ - dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; - gintmsk_data_t intr_mask = { .d32 = 0 }; - - DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__); - - /* Disable all interrupts. */ - dwc_write_reg32(&global_regs->gintmsk, 0); - - /* Clear any pending interrupts. */ - dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF); - - /* Enable the common interrupts */ - dwc_otg_enable_common_interrupts(core_if); - - /* - * Enable host mode interrupts without disturbing common - * interrupts. - */ - intr_mask.b.sofintr = 1; - intr_mask.b.portintr = 1; - intr_mask.b.hcintr = 1; - - dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32); -} - -/** - * This function disables the Host Mode interrupts. - * - * @param core_if Programming view of DWC_otg controller - */ -void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *core_if) -{ - dwc_otg_core_global_regs_t *global_regs = - core_if->core_global_regs; - gintmsk_data_t intr_mask = { .d32 = 0 }; - - DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__); - - /* - * Disable host mode interrupts without disturbing common - * interrupts. - */ - intr_mask.b.sofintr = 1; - intr_mask.b.portintr = 1; - intr_mask.b.hcintr = 1; - intr_mask.b.ptxfempty = 1; - intr_mask.b.nptxfempty = 1; - - dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0); -} - -/** - * This function initializes the DWC_otg controller registers for - * host mode. - * - * This function flushes the Tx and Rx FIFOs and it flushes any entries in the - * request queues. Host channels are reset to ensure that they are ready for - * performing transfers. - * - * @param core_if Programming view of DWC_otg controller - * - */ -void dwc_otg_core_host_init(dwc_otg_core_if_t *core_if) -{ - dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; - dwc_otg_host_if_t *host_if = core_if->host_if; - dwc_otg_core_params_t *params = core_if->core_params; - hprt0_data_t hprt0 = { .d32 = 0 }; - fifosize_data_t nptxfifosize; - fifosize_data_t ptxfifosize; - int i; - hcchar_data_t hcchar; - hcfg_data_t hcfg; - dwc_otg_hc_regs_t *hc_regs; - int num_channels; - gotgctl_data_t gotgctl = { .d32 = 0 }; - - DWC_DEBUGPL(DBG_CILV,"%s(%p)\n", __func__, core_if); - - /* Restart the Phy Clock */ - dwc_write_reg32(core_if->pcgcctl, 0); - - /* Initialize Host Configuration Register */ - init_fslspclksel(core_if); - if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) - { - hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg); - hcfg.b.fslssupp = 1; - dwc_write_reg32(&host_if->host_global_regs->hcfg, hcfg.d32); - } - - /* Configure data FIFO sizes */ - if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) { - DWC_DEBUGPL(DBG_CIL,"Total FIFO Size=%d\n", core_if->total_fifo_size); - DWC_DEBUGPL(DBG_CIL,"Rx FIFO Size=%d\n", params->host_rx_fifo_size); - DWC_DEBUGPL(DBG_CIL,"NP Tx FIFO Size=%d\n", params->host_nperio_tx_fifo_size); - DWC_DEBUGPL(DBG_CIL,"P Tx FIFO Size=%d\n", params->host_perio_tx_fifo_size); - - /* Rx FIFO */ - DWC_DEBUGPL(DBG_CIL,"initial grxfsiz=%08x\n", dwc_read_reg32(&global_regs->grxfsiz)); - dwc_write_reg32(&global_regs->grxfsiz, params->host_rx_fifo_size); - DWC_DEBUGPL(DBG_CIL,"new grxfsiz=%08x\n", dwc_read_reg32(&global_regs->grxfsiz)); - - /* Non-periodic Tx FIFO */ - DWC_DEBUGPL(DBG_CIL,"initial gnptxfsiz=%08x\n", dwc_read_reg32(&global_regs->gnptxfsiz)); - nptxfifosize.b.depth = params->host_nperio_tx_fifo_size; - nptxfifosize.b.startaddr = params->host_rx_fifo_size; - dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32); - DWC_DEBUGPL(DBG_CIL,"new gnptxfsiz=%08x\n", dwc_read_reg32(&global_regs->gnptxfsiz)); - - /* Periodic Tx FIFO */ - DWC_DEBUGPL(DBG_CIL,"initial hptxfsiz=%08x\n", dwc_read_reg32(&global_regs->hptxfsiz)); - ptxfifosize.b.depth = params->host_perio_tx_fifo_size; - ptxfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth; - dwc_write_reg32(&global_regs->hptxfsiz, ptxfifosize.d32); - DWC_DEBUGPL(DBG_CIL,"new hptxfsiz=%08x\n", dwc_read_reg32(&global_regs->hptxfsiz)); - } - - /* Clear Host Set HNP Enable in the OTG Control Register */ - gotgctl.b.hstsethnpen = 1; - dwc_modify_reg32(&global_regs->gotgctl, gotgctl.d32, 0); - - /* Make sure the FIFOs are flushed. */ - dwc_otg_flush_tx_fifo(core_if, 0x10 /* all Tx FIFOs */); - dwc_otg_flush_rx_fifo(core_if); - - /* Flush out any leftover queued requests. */ - num_channels = core_if->core_params->host_channels; - for (i = 0; i < num_channels; i++) - { - hc_regs = core_if->host_if->hc_regs[i]; - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - hcchar.b.chen = 0; - hcchar.b.chdis = 1; - hcchar.b.epdir = 0; - dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); - } - - /* Halt all channels to put them into a known state. */ - for (i = 0; i < num_channels; i++) - { - int count = 0; - hc_regs = core_if->host_if->hc_regs[i]; - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - hcchar.b.chen = 1; - hcchar.b.chdis = 1; - hcchar.b.epdir = 0; - dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); - DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d\n", __func__, i); - do { - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - if (++count > 1000) - { - DWC_ERROR("%s: Unable to clear halt on channel %d\n", - __func__, i); - break; - } - } - while (hcchar.b.chen); - } - - /* Turn on the vbus power. */ - DWC_PRINT("Init: Port Power? op_state=%d\n", core_if->op_state); - if (core_if->op_state == A_HOST) { - hprt0.d32 = dwc_otg_read_hprt0(core_if); - DWC_PRINT("Init: Power Port (%d)\n", hprt0.b.prtpwr); - if (hprt0.b.prtpwr == 0) { - hprt0.b.prtpwr = 1; - dwc_write_reg32(host_if->hprt0, hprt0.d32); - } - } - - dwc_otg_enable_host_interrupts(core_if); -} - -/** - * Prepares a host channel for transferring packets to/from a specific - * endpoint. The HCCHARn register is set up with the characteristics specified - * in _hc. Host channel interrupts that may need to be serviced while this - * transfer is in progress are enabled. - * - * @param core_if Programming view of DWC_otg controller - * @param hc Information needed to initialize the host channel - */ -void dwc_otg_hc_init(dwc_otg_core_if_t *core_if, dwc_hc_t *hc) -{ - uint32_t intr_enable; - hcintmsk_data_t hc_intr_mask; - gintmsk_data_t gintmsk = { .d32 = 0 }; - hcchar_data_t hcchar; - hcsplt_data_t hcsplt; - - uint8_t hc_num = hc->hc_num; - dwc_otg_host_if_t *host_if = core_if->host_if; - dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num]; - - /* Clear old interrupt conditions for this host channel. */ - hc_intr_mask.d32 = 0xFFFFFFFF; - hc_intr_mask.b.reserved = 0; - dwc_write_reg32(&hc_regs->hcint, hc_intr_mask.d32); - - /* Enable channel interrupts required for this transfer. */ - hc_intr_mask.d32 = 0; - hc_intr_mask.b.chhltd = 1; - if (core_if->dma_enable) { - hc_intr_mask.b.ahberr = 1; - if (hc->error_state && !hc->do_split && - hc->ep_type != DWC_OTG_EP_TYPE_ISOC) { - hc_intr_mask.b.ack = 1; - if (hc->ep_is_in) { - hc_intr_mask.b.datatglerr = 1; - if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) { - hc_intr_mask.b.nak = 1; - } - } - } - } - else { - switch (hc->ep_type) { - case DWC_OTG_EP_TYPE_CONTROL: - case DWC_OTG_EP_TYPE_BULK: - hc_intr_mask.b.xfercompl = 1; - hc_intr_mask.b.stall = 1; - hc_intr_mask.b.xacterr = 1; - hc_intr_mask.b.datatglerr = 1; - if (hc->ep_is_in) { - hc_intr_mask.b.bblerr = 1; - } - else { - hc_intr_mask.b.nak = 1; - hc_intr_mask.b.nyet = 1; - if (hc->do_ping) { - hc_intr_mask.b.ack = 1; - } - } - - if (hc->do_split) { - hc_intr_mask.b.nak = 1; - if (hc->complete_split) { - hc_intr_mask.b.nyet = 1; - } - else { - hc_intr_mask.b.ack = 1; - } - } - - if (hc->error_state) { - hc_intr_mask.b.ack = 1; - } - break; - case DWC_OTG_EP_TYPE_INTR: - hc_intr_mask.b.xfercompl = 1; - hc_intr_mask.b.nak = 1; - hc_intr_mask.b.stall = 1; - hc_intr_mask.b.xacterr = 1; - hc_intr_mask.b.datatglerr = 1; - hc_intr_mask.b.frmovrun = 1; - - if (hc->ep_is_in) { - hc_intr_mask.b.bblerr = 1; - } - if (hc->error_state) { - hc_intr_mask.b.ack = 1; - } - if (hc->do_split) { - if (hc->complete_split) { - hc_intr_mask.b.nyet = 1; - } - else { - hc_intr_mask.b.ack = 1; - } - } - break; - case DWC_OTG_EP_TYPE_ISOC: - hc_intr_mask.b.xfercompl = 1; - hc_intr_mask.b.frmovrun = 1; - hc_intr_mask.b.ack = 1; - - if (hc->ep_is_in) { - hc_intr_mask.b.xacterr = 1; - hc_intr_mask.b.bblerr = 1; - } - break; - } - } - dwc_write_reg32(&hc_regs->hcintmsk, hc_intr_mask.d32); - -// if(hc->ep_type == DWC_OTG_EP_TYPE_BULK && !hc->ep_is_in) -// hc->max_packet = 512; - /* Enable the top level host channel interrupt. */ - intr_enable = (1 << hc_num); - dwc_modify_reg32(&host_if->host_global_regs->haintmsk, 0, intr_enable); - - /* Make sure host channel interrupts are enabled. */ - gintmsk.b.hcintr = 1; - dwc_modify_reg32(&core_if->core_global_regs->gintmsk, 0, gintmsk.d32); - - /* - * Program the HCCHARn register with the endpoint characteristics for - * the current transfer. - */ - hcchar.d32 = 0; - hcchar.b.devaddr = hc->dev_addr; - hcchar.b.epnum = hc->ep_num; - hcchar.b.epdir = hc->ep_is_in; - hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW); - hcchar.b.eptype = hc->ep_type; - hcchar.b.mps = hc->max_packet; - - dwc_write_reg32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32); - - DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); - DWC_DEBUGPL(DBG_HCDV, " Dev Addr: %d\n", hcchar.b.devaddr); - DWC_DEBUGPL(DBG_HCDV, " Ep Num: %d\n", hcchar.b.epnum); - DWC_DEBUGPL(DBG_HCDV, " Is In: %d\n", hcchar.b.epdir); - DWC_DEBUGPL(DBG_HCDV, " Is Low Speed: %d\n", hcchar.b.lspddev); - DWC_DEBUGPL(DBG_HCDV, " Ep Type: %d\n", hcchar.b.eptype); - DWC_DEBUGPL(DBG_HCDV, " Max Pkt: %d\n", hcchar.b.mps); - DWC_DEBUGPL(DBG_HCDV, " Multi Cnt: %d\n", hcchar.b.multicnt); - - /* - * Program the HCSPLIT register for SPLITs - */ - hcsplt.d32 = 0; - if (hc->do_split) { - DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n", hc->hc_num, - hc->complete_split ? "CSPLIT" : "SSPLIT"); - hcsplt.b.compsplt = hc->complete_split; - hcsplt.b.xactpos = hc->xact_pos; - hcsplt.b.hubaddr = hc->hub_addr; - hcsplt.b.prtaddr = hc->port_addr; - DWC_DEBUGPL(DBG_HCDV, " comp split %d\n", hc->complete_split); - DWC_DEBUGPL(DBG_HCDV, " xact pos %d\n", hc->xact_pos); - DWC_DEBUGPL(DBG_HCDV, " hub addr %d\n", hc->hub_addr); - DWC_DEBUGPL(DBG_HCDV, " port addr %d\n", hc->port_addr); - DWC_DEBUGPL(DBG_HCDV, " is_in %d\n", hc->ep_is_in); - DWC_DEBUGPL(DBG_HCDV, " Max Pkt: %d\n", hcchar.b.mps); - DWC_DEBUGPL(DBG_HCDV, " xferlen: %d\n", hc->xfer_len); - } - dwc_write_reg32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32); - -} - -/** - * Attempts to halt a host channel. This function should only be called in - * Slave mode or to abort a transfer in either Slave mode or DMA mode. Under - * normal circumstances in DMA mode, the controller halts the channel when the - * transfer is complete or a condition occurs that requires application - * intervention. - * - * In slave mode, checks for a free request queue entry, then sets the Channel - * Enable and Channel Disable bits of the Host Channel Characteristics - * register of the specified channel to intiate the halt. If there is no free - * request queue entry, sets only the Channel Disable bit of the HCCHARn - * register to flush requests for this channel. In the latter case, sets a - * flag to indicate that the host channel needs to be halted when a request - * queue slot is open. - * - * In DMA mode, always sets the Channel Enable and Channel Disable bits of the - * HCCHARn register. The controller ensures there is space in the request - * queue before submitting the halt request. - * - * Some time may elapse before the core flushes any posted requests for this - * host channel and halts. The Channel Halted interrupt handler completes the - * deactivation of the host channel. - * - * @param core_if Controller register interface. - * @param hc Host channel to halt. - * @param halt_status Reason for halting the channel. - */ -void dwc_otg_hc_halt(dwc_otg_core_if_t *core_if, - dwc_hc_t *hc, - dwc_otg_halt_status_e halt_status) -{ - gnptxsts_data_t nptxsts; - hptxsts_data_t hptxsts; - hcchar_data_t hcchar; - dwc_otg_hc_regs_t *hc_regs; - dwc_otg_core_global_regs_t *global_regs; - dwc_otg_host_global_regs_t *host_global_regs; - - hc_regs = core_if->host_if->hc_regs[hc->hc_num]; - global_regs = core_if->core_global_regs; - host_global_regs = core_if->host_if->host_global_regs; - - WARN_ON(halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS); - - if (halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE || - halt_status == DWC_OTG_HC_XFER_AHB_ERR) { - /* - * Disable all channel interrupts except Ch Halted. The QTD - * and QH state associated with this transfer has been cleared - * (in the case of URB_DEQUEUE), so the channel needs to be - * shut down carefully to prevent crashes. - */ - hcintmsk_data_t hcintmsk; - hcintmsk.d32 = 0; - hcintmsk.b.chhltd = 1; - dwc_write_reg32(&hc_regs->hcintmsk, hcintmsk.d32); - - /* - * Make sure no other interrupts besides halt are currently - * pending. Handling another interrupt could cause a crash due - * to the QTD and QH state. - */ - dwc_write_reg32(&hc_regs->hcint, ~hcintmsk.d32); - - /* - * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR - * even if the channel was already halted for some other - * reason. - */ - hc->halt_status = halt_status; - - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - if (hcchar.b.chen == 0) { - /* - * The channel is either already halted or it hasn't - * started yet. In DMA mode, the transfer may halt if - * it finishes normally or a condition occurs that - * requires driver intervention. Don't want to halt - * the channel again. In either Slave or DMA mode, - * it's possible that the transfer has been assigned - * to a channel, but not started yet when an URB is - * dequeued. Don't want to halt a channel that hasn't - * started yet. - */ - return; - } - } - - if (hc->halt_pending) { - /* - * A halt has already been issued for this channel. This might - * happen when a transfer is aborted by a higher level in - * the stack. - */ -#ifdef DEBUG - DWC_PRINT("*** %s: Channel %d, _hc->halt_pending already set ***\n", - __func__, hc->hc_num); - -/* dwc_otg_dump_global_registers(core_if); */ -/* dwc_otg_dump_host_registers(core_if); */ -#endif - return; - } - - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - hcchar.b.chen = 1; - hcchar.b.chdis = 1; - - if (!core_if->dma_enable) { - /* Check for space in the request queue to issue the halt. */ - if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL || - hc->ep_type == DWC_OTG_EP_TYPE_BULK) { - nptxsts.d32 = dwc_read_reg32(&global_regs->gnptxsts); - if (nptxsts.b.nptxqspcavail == 0) { - hcchar.b.chen = 0; - } - } - else { - hptxsts.d32 = dwc_read_reg32(&host_global_regs->hptxsts); - if ((hptxsts.b.ptxqspcavail == 0) || (core_if->queuing_high_bandwidth)) { - hcchar.b.chen = 0; - } - } - } - - dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); - - hc->halt_status = halt_status; - - if (hcchar.b.chen) { - hc->halt_pending = 1; - hc->halt_on_queue = 0; - } - else { - hc->halt_on_queue = 1; - } - - DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); - DWC_DEBUGPL(DBG_HCDV, " hcchar: 0x%08x\n", hcchar.d32); - DWC_DEBUGPL(DBG_HCDV, " halt_pending: %d\n", hc->halt_pending); - DWC_DEBUGPL(DBG_HCDV, " halt_on_queue: %d\n", hc->halt_on_queue); - DWC_DEBUGPL(DBG_HCDV, " halt_status: %d\n", hc->halt_status); - - return; -} - -/** - * Clears the transfer state for a host channel. This function is normally - * called after a transfer is done and the host channel is being released. - * - * @param core_if Programming view of DWC_otg controller. - * @param hc Identifies the host channel to clean up. - */ -void dwc_otg_hc_cleanup(dwc_otg_core_if_t *core_if, dwc_hc_t *hc) -{ - dwc_otg_hc_regs_t *hc_regs; - - hc->xfer_started = 0; - - /* - * Clear channel interrupt enables and any unhandled channel interrupt - * conditions. - */ - hc_regs = core_if->host_if->hc_regs[hc->hc_num]; - dwc_write_reg32(&hc_regs->hcintmsk, 0); - dwc_write_reg32(&hc_regs->hcint, 0xFFFFFFFF); - -#ifdef DEBUG - del_timer(&core_if->hc_xfer_timer[hc->hc_num]); - { - hcchar_data_t hcchar; - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - if (hcchar.b.chdis) { - DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n", - __func__, hc->hc_num, hcchar.d32); - } - } -#endif -} - -/** - * Sets the channel property that indicates in which frame a periodic transfer - * should occur. This is always set to the _next_ frame. This function has no - * effect on non-periodic transfers. - * - * @param core_if Programming view of DWC_otg controller. - * @param hc Identifies the host channel to set up and its properties. - * @param hcchar Current value of the HCCHAR register for the specified host - * channel. - */ -static inline void hc_set_even_odd_frame(dwc_otg_core_if_t *core_if, - dwc_hc_t *hc, - hcchar_data_t *hcchar) -{ - if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || - hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { - hfnum_data_t hfnum; - hfnum.d32 = dwc_read_reg32(&core_if->host_if->host_global_regs->hfnum); - - /* 1 if _next_ frame is odd, 0 if it's even */ - hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1; -#ifdef DEBUG - if (hc->ep_type == DWC_OTG_EP_TYPE_INTR && hc->do_split && !hc->complete_split) { - switch (hfnum.b.frnum & 0x7) { - case 7: - core_if->hfnum_7_samples++; - core_if->hfnum_7_frrem_accum += hfnum.b.frrem; - break; - case 0: - core_if->hfnum_0_samples++; - core_if->hfnum_0_frrem_accum += hfnum.b.frrem; - break; - default: - core_if->hfnum_other_samples++; - core_if->hfnum_other_frrem_accum += hfnum.b.frrem; - break; - } - } -#endif - } -} - -#ifdef DEBUG -static void hc_xfer_timeout(unsigned long ptr) -{ - hc_xfer_info_t *xfer_info = (hc_xfer_info_t *)ptr; - int hc_num = xfer_info->hc->hc_num; - DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num); - DWC_WARN(" start_hcchar_val 0x%08x\n", xfer_info->core_if->start_hcchar_val[hc_num]); -} -#endif - -/* - * This function does the setup for a data transfer for a host channel and - * starts the transfer. May be called in either Slave mode or DMA mode. In - * Slave mode, the caller must ensure that there is sufficient space in the - * request queue and Tx Data FIFO. - * - * For an OUT transfer in Slave mode, it loads a data packet into the - * appropriate FIFO. If necessary, additional data packets will be loaded in - * the Host ISR. - * - * For an IN transfer in Slave mode, a data packet is requested. The data - * packets are unloaded from the Rx FIFO in the Host ISR. If necessary, - * additional data packets are requested in the Host ISR. - * - * For a PING transfer in Slave mode, the Do Ping bit is set in the egards, - * - * Steven - * - * register along with a packet count of 1 and the channel is enabled. This - * causes a single PING transaction to occur. Other fields in HCTSIZ are - * simply set to 0 since no data transfer occurs in this case. - * - * For a PING transfer in DMA mode, the HCTSIZ register is initialized with - * all the information required to perform the subsequent data transfer. In - * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the - * controller performs the entire PING protocol, then starts the data - * transfer. - * - * @param core_if Programming view of DWC_otg controller. - * @param hc Information needed to initialize the host channel. The xfer_len - * value may be reduced to accommodate the max widths of the XferSize and - * PktCnt fields in the HCTSIZn register. The multi_count value may be changed - * to reflect the final xfer_len value. - */ -void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *core_if, dwc_hc_t *hc) -{ - hcchar_data_t hcchar; - hctsiz_data_t hctsiz; - uint16_t num_packets; - uint32_t max_hc_xfer_size = core_if->core_params->max_transfer_size; - uint16_t max_hc_pkt_count = core_if->core_params->max_packet_count; - dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num]; - - hctsiz.d32 = 0; - - if (hc->do_ping) { - if (!core_if->dma_enable) { - dwc_otg_hc_do_ping(core_if, hc); - hc->xfer_started = 1; - return; - } - else { - hctsiz.b.dopng = 1; - } - } - - if (hc->do_split) { - num_packets = 1; - - if (hc->complete_split && !hc->ep_is_in) { - /* For CSPLIT OUT Transfer, set the size to 0 so the - * core doesn't expect any data written to the FIFO */ - hc->xfer_len = 0; - } - else if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) { - hc->xfer_len = hc->max_packet; - } - else if (!hc->ep_is_in && (hc->xfer_len > 188)) { - hc->xfer_len = 188; - } - - hctsiz.b.xfersize = hc->xfer_len; - } - else { - /* - * Ensure that the transfer length and packet count will fit - * in the widths allocated for them in the HCTSIZn register. - */ - if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || - hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { - /* - * Make sure the transfer size is no larger than one - * (micro)frame's worth of data. (A check was done - * when the periodic transfer was accepted to ensure - * that a (micro)frame's worth of data can be - * programmed into a channel.) - */ - uint32_t max_periodic_len = hc->multi_count * hc->max_packet; - if (hc->xfer_len > max_periodic_len) { - hc->xfer_len = max_periodic_len; - } - else { - } - - } - else if (hc->xfer_len > max_hc_xfer_size) { - /* Make sure that xfer_len is a multiple of max packet size. */ - hc->xfer_len = max_hc_xfer_size - hc->max_packet + 1; - } - - if (hc->xfer_len > 0) { - num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet; - if (num_packets > max_hc_pkt_count) { - num_packets = max_hc_pkt_count; - hc->xfer_len = num_packets * hc->max_packet; - } - } - else { - /* Need 1 packet for transfer length of 0. */ - num_packets = 1; - } - - if (hc->ep_is_in) { - /* Always program an integral # of max packets for IN transfers. */ - hc->xfer_len = num_packets * hc->max_packet; - } - - if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || - hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { - /* - * Make sure that the multi_count field matches the - * actual transfer length. - */ - hc->multi_count = num_packets; - } - - if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { - /* Set up the initial PID for the transfer. */ - if (hc->speed == DWC_OTG_EP_SPEED_HIGH) { - if (hc->ep_is_in) { - if (hc->multi_count == 1) { - hc->data_pid_start = DWC_OTG_HC_PID_DATA0; - } - else if (hc->multi_count == 2) { - hc->data_pid_start = DWC_OTG_HC_PID_DATA1; - } - else { - hc->data_pid_start = DWC_OTG_HC_PID_DATA2; - } - } - else { - if (hc->multi_count == 1) { - hc->data_pid_start = DWC_OTG_HC_PID_DATA0; - } - else { - hc->data_pid_start = DWC_OTG_HC_PID_MDATA; - } - } - } - else { - hc->data_pid_start = DWC_OTG_HC_PID_DATA0; - } - } - - hctsiz.b.xfersize = hc->xfer_len; - } - - hc->start_pkt_count = num_packets; - hctsiz.b.pktcnt = num_packets; - hctsiz.b.pid = hc->data_pid_start; - dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); - - DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); - DWC_DEBUGPL(DBG_HCDV, " Xfer Size: %d\n", hctsiz.b.xfersize); - DWC_DEBUGPL(DBG_HCDV, " Num Pkts: %d\n", hctsiz.b.pktcnt); - DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid); - - if (core_if->dma_enable) { -#if defined (CONFIG_DWC_OTG_HOST_ONLY) - if ((uint32_t)hc->xfer_buff & 0x3) { - /* non DWORD-aligned buffer case*/ - if(!hc->qh->dw_align_buf) { - hc->qh->dw_align_buf = - dma_alloc_coherent(NULL, - core_if->core_params->max_transfer_size, - &hc->qh->dw_align_buf_dma, - GFP_ATOMIC | GFP_DMA); - if (!hc->qh->dw_align_buf) { - - DWC_ERROR("%s: Failed to allocate memory to handle " - "non-dword aligned buffer case\n", __func__); - return; - } - - } - if (!hc->ep_is_in) { - memcpy(hc->qh->dw_align_buf, phys_to_virt((uint32_t)hc->xfer_buff), hc->xfer_len); - } - - dwc_write_reg32(&hc_regs->hcdma, hc->qh->dw_align_buf_dma); - } - else -#endif - dwc_write_reg32(&hc_regs->hcdma, (uint32_t)hc->xfer_buff); - } - - /* Start the split */ - if (hc->do_split) { - hcsplt_data_t hcsplt; - hcsplt.d32 = dwc_read_reg32 (&hc_regs->hcsplt); - hcsplt.b.spltena = 1; - dwc_write_reg32(&hc_regs->hcsplt, hcsplt.d32); - } - - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - hcchar.b.multicnt = hc->multi_count; - hc_set_even_odd_frame(core_if, hc, &hcchar); -#ifdef DEBUG - core_if->start_hcchar_val[hc->hc_num] = hcchar.d32; - if (hcchar.b.chdis) { - DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n", - __func__, hc->hc_num, hcchar.d32); - } -#endif - - /* Set host channel enable after all other setup is complete. */ - hcchar.b.chen = 1; - hcchar.b.chdis = 0; - dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); - - hc->xfer_started = 1; - hc->requests++; - - if (!core_if->dma_enable && - !hc->ep_is_in && hc->xfer_len > 0) { - /* Load OUT packet into the appropriate Tx FIFO. */ - dwc_otg_hc_write_packet(core_if, hc); - } - -#ifdef DEBUG - /* Start a timer for this transfer. */ - core_if->hc_xfer_timer[hc->hc_num].function = hc_xfer_timeout; - core_if->hc_xfer_info[hc->hc_num].core_if = core_if; - core_if->hc_xfer_info[hc->hc_num].hc = hc; - core_if->hc_xfer_timer[hc->hc_num].data = (unsigned long)(&core_if->hc_xfer_info[hc->hc_num]); - core_if->hc_xfer_timer[hc->hc_num].expires = jiffies + (HZ*10); - add_timer(&core_if->hc_xfer_timer[hc->hc_num]); -#endif -} - -/** - * This function continues a data transfer that was started by previous call - * to dwc_otg_hc_start_transfer. The caller must ensure there is - * sufficient space in the request queue and Tx Data FIFO. This function - * should only be called in Slave mode. In DMA mode, the controller acts - * autonomously to complete transfers programmed to a host channel. - * - * For an OUT transfer, a new data packet is loaded into the appropriate FIFO - * if there is any data remaining to be queued. For an IN transfer, another - * data packet is always requested. For the SETUP phase of a control transfer, - * this function does nothing. - * - * @return 1 if a new request is queued, 0 if no more requests are required - * for this transfer. - */ -int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *core_if, dwc_hc_t *hc) -{ - DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); - - if (hc->do_split) { - /* SPLITs always queue just once per channel */ - return 0; - } - else if (hc->data_pid_start == DWC_OTG_HC_PID_SETUP) { - /* SETUPs are queued only once since they can't be NAKed. */ - return 0; - } - else if (hc->ep_is_in) { - /* - * Always queue another request for other IN transfers. If - * back-to-back INs are issued and NAKs are received for both, - * the driver may still be processing the first NAK when the - * second NAK is received. When the interrupt handler clears - * the NAK interrupt for the first NAK, the second NAK will - * not be seen. So we can't depend on the NAK interrupt - * handler to requeue a NAKed request. Instead, IN requests - * are issued each time this function is called. When the - * transfer completes, the extra requests for the channel will - * be flushed. - */ - hcchar_data_t hcchar; - dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num]; - - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - hc_set_even_odd_frame(core_if, hc, &hcchar); - hcchar.b.chen = 1; - hcchar.b.chdis = 0; - DWC_DEBUGPL(DBG_HCDV, " IN xfer: hcchar = 0x%08x\n", hcchar.d32); - dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); - hc->requests++; - return 1; - } - else { - /* OUT transfers. */ - if (hc->xfer_count < hc->xfer_len) { - if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || - hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { - hcchar_data_t hcchar; - dwc_otg_hc_regs_t *hc_regs; - hc_regs = core_if->host_if->hc_regs[hc->hc_num]; - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - hc_set_even_odd_frame(core_if, hc, &hcchar); - } - - /* Load OUT packet into the appropriate Tx FIFO. */ - dwc_otg_hc_write_packet(core_if, hc); - hc->requests++; - return 1; - } - else { - return 0; - } - } -} - -/** - * Starts a PING transfer. This function should only be called in Slave mode. - * The Do Ping bit is set in the HCTSIZ register, then the channel is enabled. - */ -void dwc_otg_hc_do_ping(dwc_otg_core_if_t *core_if, dwc_hc_t *hc) -{ - hcchar_data_t hcchar; - hctsiz_data_t hctsiz; - dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num]; - - DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); - - hctsiz.d32 = 0; - hctsiz.b.dopng = 1; - hctsiz.b.pktcnt = 1; - dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); - - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - hcchar.b.chen = 1; - hcchar.b.chdis = 0; - dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); -} - -/* - * This function writes a packet into the Tx FIFO associated with the Host - * Channel. For a channel associated with a non-periodic EP, the non-periodic - * Tx FIFO is written. For a channel associated with a periodic EP, the - * periodic Tx FIFO is written. This function should only be called in Slave - * mode. - * - * Upon return the xfer_buff and xfer_count fields in _hc are incremented by - * then number of bytes written to the Tx FIFO. - */ -void dwc_otg_hc_write_packet(dwc_otg_core_if_t *core_if, dwc_hc_t *hc) -{ - uint32_t i; - uint32_t remaining_count; - uint32_t byte_count; - uint32_t dword_count; - - uint32_t *data_buff = (uint32_t *)(hc->xfer_buff); - uint32_t *data_fifo = core_if->data_fifo[hc->hc_num]; - - remaining_count = hc->xfer_len - hc->xfer_count; - if (remaining_count > hc->max_packet) { - byte_count = hc->max_packet; - } - else { - byte_count = remaining_count; - } - - dword_count = (byte_count + 3) / 4; - - if ((((unsigned long)data_buff) & 0x3) == 0) { - /* xfer_buff is DWORD aligned. */ - for (i = 0; i < dword_count; i++, data_buff++) - { - dwc_write_reg32(data_fifo, *data_buff); - } - } - else { - /* xfer_buff is not DWORD aligned. */ - for (i = 0; i < dword_count; i++, data_buff++) - { - dwc_write_reg32(data_fifo, get_unaligned(data_buff)); - } - } - - hc->xfer_count += byte_count; - hc->xfer_buff += byte_count; -} - -/** - * Gets the current USB frame number. This is the frame number from the last - * SOF packet. - */ -uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *core_if) -{ - dsts_data_t dsts; - dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); - - /* read current frame/microframe number from DSTS register */ - return dsts.b.soffn; -} - -/** - * This function reads a setup packet from the Rx FIFO into the destination - * buffer. This function is called from the Rx Status Queue Level (RxStsQLvl) - * Interrupt routine when a SETUP packet has been received in Slave mode. - * - * @param core_if Programming view of DWC_otg controller. - * @param dest Destination buffer for packet data. - */ -void dwc_otg_read_setup_packet(dwc_otg_core_if_t *core_if, uint32_t *dest) -{ - /* Get the 8 bytes of a setup transaction data */ - - /* Pop 2 DWORDS off the receive data FIFO into memory */ - dest[0] = dwc_read_reg32(core_if->data_fifo[0]); - dest[1] = dwc_read_reg32(core_if->data_fifo[0]); -} - - -/** - * This function enables EP0 OUT to receive SETUP packets and configures EP0 - * IN for transmitting packets. It is normally called when the - * "Enumeration Done" interrupt occurs. - * - * @param core_if Programming view of DWC_otg controller. - * @param ep The EP0 data. - */ -void dwc_otg_ep0_activate(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) -{ - dwc_otg_dev_if_t *dev_if = core_if->dev_if; - dsts_data_t dsts; - depctl_data_t diepctl; - depctl_data_t doepctl; - dctl_data_t dctl = { .d32 = 0 }; - - /* Read the Device Status and Endpoint 0 Control registers */ - dsts.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dsts); - diepctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl); - doepctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl); - - /* Set the MPS of the IN EP based on the enumeration speed */ - switch (dsts.b.enumspd) { - case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: - case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: - case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ: - diepctl.b.mps = DWC_DEP0CTL_MPS_64; - break; - case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ: - diepctl.b.mps = DWC_DEP0CTL_MPS_8; - break; - } - - dwc_write_reg32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32); - - /* Enable OUT EP for receive */ - doepctl.b.epena = 1; - dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32); - -#ifdef VERBOSE - DWC_DEBUGPL(DBG_PCDV,"doepctl0=%0x\n", - dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl)); - DWC_DEBUGPL(DBG_PCDV,"diepctl0=%0x\n", - dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl)); -#endif - dctl.b.cgnpinnak = 1; - - dwc_modify_reg32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); - DWC_DEBUGPL(DBG_PCDV,"dctl=%0x\n", - dwc_read_reg32(&dev_if->dev_global_regs->dctl)); -} - -/** - * This function activates an EP. The Device EP control register for - * the EP is configured as defined in the ep structure. Note: This - * function is not used for EP0. - * - * @param core_if Programming view of DWC_otg controller. - * @param ep The EP to activate. - */ -void dwc_otg_ep_activate(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) -{ - dwc_otg_dev_if_t *dev_if = core_if->dev_if; - depctl_data_t depctl; - volatile uint32_t *addr; - daint_data_t daintmsk = { .d32 = 0 }; - - DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, ep->num, - (ep->is_in?"IN":"OUT")); - - /* Read DEPCTLn register */ - if (ep->is_in == 1) { - addr = &dev_if->in_ep_regs[ep->num]->diepctl; - daintmsk.ep.in = 1<num; - } - else { - addr = &dev_if->out_ep_regs[ep->num]->doepctl; - daintmsk.ep.out = 1<num; - } - - /* If the EP is already active don't change the EP Control - * register. */ - depctl.d32 = dwc_read_reg32(addr); - if (!depctl.b.usbactep) { - depctl.b.mps = ep->maxpacket; - depctl.b.eptype = ep->type; - depctl.b.txfnum = ep->tx_fifo_num; - - if (ep->type == DWC_OTG_EP_TYPE_ISOC) { - depctl.b.setd0pid = 1; // ??? - } - else { - depctl.b.setd0pid = 1; - } - depctl.b.usbactep = 1; - - dwc_write_reg32(addr, depctl.d32); - DWC_DEBUGPL(DBG_PCDV,"DEPCTL=%08x\n", dwc_read_reg32(addr)); - } - - /* Enable the Interrupt for this EP */ - if(core_if->multiproc_int_enable) { - if (ep->is_in == 1) { - diepmsk_data_t diepmsk = { .d32 = 0}; - diepmsk.b.xfercompl = 1; - diepmsk.b.timeout = 1; - diepmsk.b.epdisabled = 1; - diepmsk.b.ahberr = 1; - diepmsk.b.intknepmis = 1; - diepmsk.b.txfifoundrn = 1; //????? - - - if(core_if->dma_desc_enable) { - diepmsk.b.bna = 1; - } -/* - if(core_if->dma_enable) { - doepmsk.b.nak = 1; - } -*/ - dwc_write_reg32(&dev_if->dev_global_regs->diepeachintmsk[ep->num], diepmsk.d32); - - } else { - doepmsk_data_t doepmsk = { .d32 = 0}; - doepmsk.b.xfercompl = 1; - doepmsk.b.ahberr = 1; - doepmsk.b.epdisabled = 1; - - - if(core_if->dma_desc_enable) { - doepmsk.b.bna = 1; - } -/* - doepmsk.b.babble = 1; - doepmsk.b.nyet = 1; - doepmsk.b.nak = 1; -*/ - dwc_write_reg32(&dev_if->dev_global_regs->doepeachintmsk[ep->num], doepmsk.d32); - } - dwc_modify_reg32(&dev_if->dev_global_regs->deachintmsk, - 0, daintmsk.d32); - } else { - dwc_modify_reg32(&dev_if->dev_global_regs->daintmsk, - 0, daintmsk.d32); - } - - DWC_DEBUGPL(DBG_PCDV,"DAINTMSK=%0x\n", - dwc_read_reg32(&dev_if->dev_global_regs->daintmsk)); - - ep->stall_clear_flag = 0; - return; -} - -/** - * This function deactivates an EP. This is done by clearing the USB Active - * EP bit in the Device EP control register. Note: This function is not used - * for EP0. EP0 cannot be deactivated. - * - * @param core_if Programming view of DWC_otg controller. - * @param ep The EP to deactivate. - */ -void dwc_otg_ep_deactivate(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) -{ - depctl_data_t depctl = { .d32 = 0 }; - volatile uint32_t *addr; - daint_data_t daintmsk = { .d32 = 0}; - - /* Read DEPCTLn register */ - if (ep->is_in == 1) { - addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl; - daintmsk.ep.in = 1<num; - } - else { - addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl; - daintmsk.ep.out = 1<num; - } - - depctl.b.usbactep = 0; - - if(core_if->dma_desc_enable) - depctl.b.epdis = 1; - - dwc_write_reg32(addr, depctl.d32); - - /* Disable the Interrupt for this EP */ - if(core_if->multiproc_int_enable) { - dwc_modify_reg32(&core_if->dev_if->dev_global_regs->deachintmsk, - daintmsk.d32, 0); - - if (ep->is_in == 1) { - dwc_write_reg32(&core_if->dev_if->dev_global_regs->diepeachintmsk[ep->num], 0); - } else { - dwc_write_reg32(&core_if->dev_if->dev_global_regs->doepeachintmsk[ep->num], 0); - } - } else { - dwc_modify_reg32(&core_if->dev_if->dev_global_regs->daintmsk, - daintmsk.d32, 0); - } -} - -/** - * This function does the setup for a data transfer for an EP and - * starts the transfer. For an IN transfer, the packets will be - * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, - * the packets are unloaded from the Rx FIFO in the ISR. the ISR. - * - * @param core_if Programming view of DWC_otg controller. - * @param ep The EP to start the transfer on. - */ -static void init_dma_desc_chain(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) -{ - dwc_otg_dma_desc_t* dma_desc; - uint32_t offset; - uint32_t xfer_est; - int i; - - ep->desc_cnt = ( ep->total_len / ep->maxxfer) + - ((ep->total_len % ep->maxxfer) ? 1 : 0); - if(!ep->desc_cnt) - ep->desc_cnt = 1; - - dma_desc = ep->desc_addr; - xfer_est = ep->total_len; - offset = 0; - for( i = 0; i < ep->desc_cnt; ++i) { - /** DMA Descriptor Setup */ - if(xfer_est > ep->maxxfer) { - dma_desc->status.b.bs = BS_HOST_BUSY; - dma_desc->status.b.l = 0; - dma_desc->status.b.ioc = 0; - dma_desc->status.b.sp = 0; - dma_desc->status.b.bytes = ep->maxxfer; - dma_desc->buf = ep->dma_addr + offset; - dma_desc->status.b.bs = BS_HOST_READY; - - xfer_est -= ep->maxxfer; - offset += ep->maxxfer; - } else { - dma_desc->status.b.bs = BS_HOST_BUSY; - dma_desc->status.b.l = 1; - dma_desc->status.b.ioc = 1; - if(ep->is_in) { - dma_desc->status.b.sp = (xfer_est % ep->maxpacket) ? - 1 : ((ep->sent_zlp) ? 1 : 0); - dma_desc->status.b.bytes = xfer_est; - } else { - dma_desc->status.b.bytes = xfer_est + ((4 - (xfer_est & 0x3)) & 0x3) ; - } - - dma_desc->buf = ep->dma_addr + offset; - dma_desc->status.b.bs = BS_HOST_READY; - } - dma_desc ++; - } -} - -/** - * This function does the setup for a data transfer for an EP and - * starts the transfer. For an IN transfer, the packets will be - * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, - * the packets are unloaded from the Rx FIFO in the ISR. the ISR. - * - * @param core_if Programming view of DWC_otg controller. - * @param ep The EP to start the transfer on. - */ - -void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) -{ - depctl_data_t depctl; - deptsiz_data_t deptsiz; - gintmsk_data_t intr_mask = { .d32 = 0}; - - DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__); - - DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d " - "xfer_buff=%p start_xfer_buff=%p\n", - ep->num, (ep->is_in?"IN":"OUT"), ep->xfer_len, - ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff); - - /* IN endpoint */ - if (ep->is_in == 1) { - dwc_otg_dev_in_ep_regs_t *in_regs = - core_if->dev_if->in_ep_regs[ep->num]; - - gnptxsts_data_t gtxstatus; - - gtxstatus.d32 = - dwc_read_reg32(&core_if->core_global_regs->gnptxsts); - - if(core_if->en_multiple_tx_fifo == 0 && gtxstatus.b.nptxqspcavail == 0) { -#ifdef DEBUG - DWC_PRINT("TX Queue Full (0x%0x)\n", gtxstatus.d32); -#endif - return; - } - - depctl.d32 = dwc_read_reg32(&(in_regs->diepctl)); - deptsiz.d32 = dwc_read_reg32(&(in_regs->dieptsiz)); - - ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ? - ep->maxxfer : (ep->total_len - ep->xfer_len); - - /* Zero Length Packet? */ - if ((ep->xfer_len - ep->xfer_count) == 0) { - deptsiz.b.xfersize = 0; - deptsiz.b.pktcnt = 1; - } - else { - /* Program the transfer size and packet count - * as follows: xfersize = N * maxpacket + - * short_packet pktcnt = N + (short_packet - * exist ? 1 : 0) - */ - deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count; - deptsiz.b.pktcnt = - (ep->xfer_len - ep->xfer_count - 1 + ep->maxpacket) / - ep->maxpacket; - } - - - /* Write the DMA register */ - if (core_if->dma_enable) { - if (core_if->dma_desc_enable == 0) { - dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); - dwc_write_reg32 (&(in_regs->diepdma), - (uint32_t)ep->dma_addr); - } - else { - init_dma_desc_chain(core_if, ep); - /** DIEPDMAn Register write */ - dwc_write_reg32(&in_regs->diepdma, ep->dma_desc_addr); - } - } - else { - dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); - if(ep->type != DWC_OTG_EP_TYPE_ISOC) { - /** - * Enable the Non-Periodic Tx FIFO empty interrupt, - * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, - * the data will be written into the fifo by the ISR. - */ - if(core_if->en_multiple_tx_fifo == 0) { - intr_mask.b.nptxfempty = 1; - dwc_modify_reg32(&core_if->core_global_regs->gintmsk, - intr_mask.d32, intr_mask.d32); - } - else { - /* Enable the Tx FIFO Empty Interrupt for this EP */ - if(ep->xfer_len > 0) { - uint32_t fifoemptymsk = 0; - fifoemptymsk = 1 << ep->num; - dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk, - 0, fifoemptymsk); - - } - } - } - } - - /* EP enable, IN data in FIFO */ - depctl.b.cnak = 1; - depctl.b.epena = 1; - dwc_write_reg32(&in_regs->diepctl, depctl.d32); - - depctl.d32 = dwc_read_reg32 (&core_if->dev_if->in_ep_regs[0]->diepctl); - depctl.b.nextep = ep->num; - dwc_write_reg32 (&core_if->dev_if->in_ep_regs[0]->diepctl, depctl.d32); - - } - else { - /* OUT endpoint */ - dwc_otg_dev_out_ep_regs_t *out_regs = - core_if->dev_if->out_ep_regs[ep->num]; - - depctl.d32 = dwc_read_reg32(&(out_regs->doepctl)); - deptsiz.d32 = dwc_read_reg32(&(out_regs->doeptsiz)); - - ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ? - ep->maxxfer : (ep->total_len - ep->xfer_len); - - /* Program the transfer size and packet count as follows: - * - * pktcnt = N - * xfersize = N * maxpacket - */ - if ((ep->xfer_len - ep->xfer_count) == 0) { - /* Zero Length Packet */ - deptsiz.b.xfersize = ep->maxpacket; - deptsiz.b.pktcnt = 1; - } - else { - deptsiz.b.pktcnt = - (ep->xfer_len - ep->xfer_count + (ep->maxpacket - 1)) / - ep->maxpacket; - ep->xfer_len = deptsiz.b.pktcnt * ep->maxpacket + ep->xfer_count; - deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count; - } - - DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n", - ep->num, - deptsiz.b.xfersize, deptsiz.b.pktcnt); - - if (core_if->dma_enable) { - if (!core_if->dma_desc_enable) { - dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32); - - dwc_write_reg32 (&(out_regs->doepdma), - (uint32_t)ep->dma_addr); - } - else { - init_dma_desc_chain(core_if, ep); - - /** DOEPDMAn Register write */ - dwc_write_reg32(&out_regs->doepdma, ep->dma_desc_addr); - } - } - else { - dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32); - } - - /* EP enable */ - depctl.b.cnak = 1; - depctl.b.epena = 1; - - dwc_write_reg32(&out_regs->doepctl, depctl.d32); - - DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n", - dwc_read_reg32(&out_regs->doepctl), - dwc_read_reg32(&out_regs->doeptsiz)); - DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n", - dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk), - dwc_read_reg32(&core_if->core_global_regs->gintmsk)); - } -} - -/** - * This function setup a zero length transfer in Buffer DMA and - * Slave modes for usb requests with zero field set - * - * @param core_if Programming view of DWC_otg controller. - * @param ep The EP to start the transfer on. - * - */ -void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) -{ - - depctl_data_t depctl; - deptsiz_data_t deptsiz; - gintmsk_data_t intr_mask = { .d32 = 0}; - - DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__); - - /* IN endpoint */ - if (ep->is_in == 1) { - dwc_otg_dev_in_ep_regs_t *in_regs = - core_if->dev_if->in_ep_regs[ep->num]; - - depctl.d32 = dwc_read_reg32(&(in_regs->diepctl)); - deptsiz.d32 = dwc_read_reg32(&(in_regs->dieptsiz)); - - deptsiz.b.xfersize = 0; - deptsiz.b.pktcnt = 1; - - - /* Write the DMA register */ - if (core_if->dma_enable) { - if (core_if->dma_desc_enable == 0) { - dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); - dwc_write_reg32 (&(in_regs->diepdma), - (uint32_t)ep->dma_addr); - } - } - else { - dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); - /** - * Enable the Non-Periodic Tx FIFO empty interrupt, - * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, - * the data will be written into the fifo by the ISR. - */ - if(core_if->en_multiple_tx_fifo == 0) { - intr_mask.b.nptxfempty = 1; - dwc_modify_reg32(&core_if->core_global_regs->gintmsk, - intr_mask.d32, intr_mask.d32); - } - else { - /* Enable the Tx FIFO Empty Interrupt for this EP */ - if(ep->xfer_len > 0) { - uint32_t fifoemptymsk = 0; - fifoemptymsk = 1 << ep->num; - dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk, - 0, fifoemptymsk); - } - } - } - - /* EP enable, IN data in FIFO */ - depctl.b.cnak = 1; - depctl.b.epena = 1; - dwc_write_reg32(&in_regs->diepctl, depctl.d32); - - depctl.d32 = dwc_read_reg32 (&core_if->dev_if->in_ep_regs[0]->diepctl); - depctl.b.nextep = ep->num; - dwc_write_reg32 (&core_if->dev_if->in_ep_regs[0]->diepctl, depctl.d32); - - } - else { - /* OUT endpoint */ - dwc_otg_dev_out_ep_regs_t *out_regs = - core_if->dev_if->out_ep_regs[ep->num]; - - depctl.d32 = dwc_read_reg32(&(out_regs->doepctl)); - deptsiz.d32 = dwc_read_reg32(&(out_regs->doeptsiz)); - - /* Zero Length Packet */ - deptsiz.b.xfersize = ep->maxpacket; - deptsiz.b.pktcnt = 1; - - if (core_if->dma_enable) { - if (!core_if->dma_desc_enable) { - dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32); - - dwc_write_reg32 (&(out_regs->doepdma), - (uint32_t)ep->dma_addr); - } - } - else { - dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32); - } - - /* EP enable */ - depctl.b.cnak = 1; - depctl.b.epena = 1; - - dwc_write_reg32(&out_regs->doepctl, depctl.d32); - - } -} - -/** - * This function does the setup for a data transfer for EP0 and starts - * the transfer. For an IN transfer, the packets will be loaded into - * the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are - * unloaded from the Rx FIFO in the ISR. - * - * @param core_if Programming view of DWC_otg controller. - * @param ep The EP0 data. - */ -void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) -{ - depctl_data_t depctl; - deptsiz0_data_t deptsiz; - gintmsk_data_t intr_mask = { .d32 = 0}; - dwc_otg_dma_desc_t* dma_desc; - - DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d " - "xfer_buff=%p start_xfer_buff=%p \n", - ep->num, (ep->is_in?"IN":"OUT"), ep->xfer_len, - ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff); - - ep->total_len = ep->xfer_len; - - /* IN endpoint */ - if (ep->is_in == 1) { - dwc_otg_dev_in_ep_regs_t *in_regs = - core_if->dev_if->in_ep_regs[0]; - - gnptxsts_data_t gtxstatus; - - gtxstatus.d32 = - dwc_read_reg32(&core_if->core_global_regs->gnptxsts); - - if(core_if->en_multiple_tx_fifo == 0 && gtxstatus.b.nptxqspcavail == 0) { -#ifdef DEBUG - deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz); - DWC_DEBUGPL(DBG_PCD,"DIEPCTL0=%0x\n", - dwc_read_reg32(&in_regs->diepctl)); - DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n", - deptsiz.d32, - deptsiz.b.xfersize, deptsiz.b.pktcnt); - DWC_PRINT("TX Queue or FIFO Full (0x%0x)\n", - gtxstatus.d32); -#endif - return; - } - - - depctl.d32 = dwc_read_reg32(&in_regs->diepctl); - deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz); - - /* Zero Length Packet? */ - if (ep->xfer_len == 0) { - deptsiz.b.xfersize = 0; - deptsiz.b.pktcnt = 1; - } - else { - /* Program the transfer size and packet count - * as follows: xfersize = N * maxpacket + - * short_packet pktcnt = N + (short_packet - * exist ? 1 : 0) - */ - if (ep->xfer_len > ep->maxpacket) { - ep->xfer_len = ep->maxpacket; - deptsiz.b.xfersize = ep->maxpacket; - } - else { - deptsiz.b.xfersize = ep->xfer_len; - } - deptsiz.b.pktcnt = 1; - - } - DWC_DEBUGPL(DBG_PCDV, "IN len=%d xfersize=%d pktcnt=%d [%08x]\n", - ep->xfer_len, - deptsiz.b.xfersize, deptsiz.b.pktcnt, deptsiz.d32); - - /* Write the DMA register */ - if (core_if->dma_enable) { - if(core_if->dma_desc_enable == 0) { - dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); - - dwc_write_reg32 (&(in_regs->diepdma), - (uint32_t)ep->dma_addr); - } - else { - dma_desc = core_if->dev_if->in_desc_addr; - - /** DMA Descriptor Setup */ - dma_desc->status.b.bs = BS_HOST_BUSY; - dma_desc->status.b.l = 1; - dma_desc->status.b.ioc = 1; - dma_desc->status.b.sp = (ep->xfer_len == ep->maxpacket) ? 0 : 1; - dma_desc->status.b.bytes = ep->xfer_len; - dma_desc->buf = ep->dma_addr; - dma_desc->status.b.bs = BS_HOST_READY; - - /** DIEPDMA0 Register write */ - dwc_write_reg32(&in_regs->diepdma, core_if->dev_if->dma_in_desc_addr); - } - } - else { - dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); - } - - /* EP enable, IN data in FIFO */ - depctl.b.cnak = 1; - depctl.b.epena = 1; - dwc_write_reg32(&in_regs->diepctl, depctl.d32); - - /** - * Enable the Non-Periodic Tx FIFO empty interrupt, the - * data will be written into the fifo by the ISR. - */ - if (!core_if->dma_enable) { - if(core_if->en_multiple_tx_fifo == 0) { - intr_mask.b.nptxfempty = 1; - dwc_modify_reg32(&core_if->core_global_regs->gintmsk, - intr_mask.d32, intr_mask.d32); - } - else { - /* Enable the Tx FIFO Empty Interrupt for this EP */ - if(ep->xfer_len > 0) { - uint32_t fifoemptymsk = 0; - fifoemptymsk |= 1 << ep->num; - dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk, - 0, fifoemptymsk); - } - } - } - } - else { - /* OUT endpoint */ - dwc_otg_dev_out_ep_regs_t *out_regs = - core_if->dev_if->out_ep_regs[0]; - - depctl.d32 = dwc_read_reg32(&out_regs->doepctl); - deptsiz.d32 = dwc_read_reg32(&out_regs->doeptsiz); - - /* Program the transfer size and packet count as follows: - * xfersize = N * (maxpacket + 4 - (maxpacket % 4)) - * pktcnt = N */ - /* Zero Length Packet */ - deptsiz.b.xfersize = ep->maxpacket; - deptsiz.b.pktcnt = 1; - - DWC_DEBUGPL(DBG_PCDV, "len=%d xfersize=%d pktcnt=%d\n", - ep->xfer_len, - deptsiz.b.xfersize, deptsiz.b.pktcnt); - - if (core_if->dma_enable) { - if(!core_if->dma_desc_enable) { - dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32); - - dwc_write_reg32 (&(out_regs->doepdma), - (uint32_t)ep->dma_addr); - } - else { - dma_desc = core_if->dev_if->out_desc_addr; - - /** DMA Descriptor Setup */ - dma_desc->status.b.bs = BS_HOST_BUSY; - dma_desc->status.b.l = 1; - dma_desc->status.b.ioc = 1; - dma_desc->status.b.bytes = ep->maxpacket; - dma_desc->buf = ep->dma_addr; - dma_desc->status.b.bs = BS_HOST_READY; - - /** DOEPDMA0 Register write */ - dwc_write_reg32(&out_regs->doepdma, core_if->dev_if->dma_out_desc_addr); - } - } - else { - dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32); - } - - /* EP enable */ - depctl.b.cnak = 1; - depctl.b.epena = 1; - dwc_write_reg32 (&(out_regs->doepctl), depctl.d32); - } -} - -/** - * This function continues control IN transfers started by - * dwc_otg_ep0_start_transfer, when the transfer does not fit in a - * single packet. NOTE: The DIEPCTL0/DOEPCTL0 registers only have one - * bit for the packet count. - * - * @param core_if Programming view of DWC_otg controller. - * @param ep The EP0 data. - */ -void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) -{ - depctl_data_t depctl; - deptsiz0_data_t deptsiz; - gintmsk_data_t intr_mask = { .d32 = 0}; - dwc_otg_dma_desc_t* dma_desc; - - if (ep->is_in == 1) { - dwc_otg_dev_in_ep_regs_t *in_regs = - core_if->dev_if->in_ep_regs[0]; - gnptxsts_data_t tx_status = { .d32 = 0 }; - - tx_status.d32 = dwc_read_reg32(&core_if->core_global_regs->gnptxsts); - /** @todo Should there be check for room in the Tx - * Status Queue. If not remove the code above this comment. */ - - depctl.d32 = dwc_read_reg32(&in_regs->diepctl); - deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz); - - /* Program the transfer size and packet count - * as follows: xfersize = N * maxpacket + - * short_packet pktcnt = N + (short_packet - * exist ? 1 : 0) - */ - - - if(core_if->dma_desc_enable == 0) { - deptsiz.b.xfersize = (ep->total_len - ep->xfer_count) > ep->maxpacket ? ep->maxpacket : - (ep->total_len - ep->xfer_count); - deptsiz.b.pktcnt = 1; - if(core_if->dma_enable == 0) { - ep->xfer_len += deptsiz.b.xfersize; - } else { - ep->xfer_len = deptsiz.b.xfersize; - } - dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); - } - else { - ep->xfer_len = (ep->total_len - ep->xfer_count) > ep->maxpacket ? ep->maxpacket : - (ep->total_len - ep->xfer_count); - - dma_desc = core_if->dev_if->in_desc_addr; - - /** DMA Descriptor Setup */ - dma_desc->status.b.bs = BS_HOST_BUSY; - dma_desc->status.b.l = 1; - dma_desc->status.b.ioc = 1; - dma_desc->status.b.sp = (ep->xfer_len == ep->maxpacket) ? 0 : 1; - dma_desc->status.b.bytes = ep->xfer_len; - dma_desc->buf = ep->dma_addr; - dma_desc->status.b.bs = BS_HOST_READY; - - /** DIEPDMA0 Register write */ - dwc_write_reg32(&in_regs->diepdma, core_if->dev_if->dma_in_desc_addr); - } - - - DWC_DEBUGPL(DBG_PCDV, "IN len=%d xfersize=%d pktcnt=%d [%08x]\n", - ep->xfer_len, - deptsiz.b.xfersize, deptsiz.b.pktcnt, deptsiz.d32); - - /* Write the DMA register */ - if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) { - if(core_if->dma_desc_enable == 0) - dwc_write_reg32 (&(in_regs->diepdma), (uint32_t)ep->dma_addr); - } - - /* EP enable, IN data in FIFO */ - depctl.b.cnak = 1; - depctl.b.epena = 1; - dwc_write_reg32(&in_regs->diepctl, depctl.d32); - - /** - * Enable the Non-Periodic Tx FIFO empty interrupt, the - * data will be written into the fifo by the ISR. - */ - if (!core_if->dma_enable) { - if(core_if->en_multiple_tx_fifo == 0) { - /* First clear it from GINTSTS */ - intr_mask.b.nptxfempty = 1; - dwc_modify_reg32(&core_if->core_global_regs->gintmsk, - intr_mask.d32, intr_mask.d32); - - } - else { - /* Enable the Tx FIFO Empty Interrupt for this EP */ - if(ep->xfer_len > 0) { - uint32_t fifoemptymsk = 0; - fifoemptymsk |= 1 << ep->num; - dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk, - 0, fifoemptymsk); - } - } - } - } - else { - dwc_otg_dev_out_ep_regs_t *out_regs = - core_if->dev_if->out_ep_regs[0]; - - - depctl.d32 = dwc_read_reg32(&out_regs->doepctl); - deptsiz.d32 = dwc_read_reg32(&out_regs->doeptsiz); - - /* Program the transfer size and packet count - * as follows: xfersize = N * maxpacket + - * short_packet pktcnt = N + (short_packet - * exist ? 1 : 0) - */ - deptsiz.b.xfersize = ep->maxpacket; - deptsiz.b.pktcnt = 1; - - - if(core_if->dma_desc_enable == 0) { - dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32); - } - else { - dma_desc = core_if->dev_if->out_desc_addr; - - /** DMA Descriptor Setup */ - dma_desc->status.b.bs = BS_HOST_BUSY; - dma_desc->status.b.l = 1; - dma_desc->status.b.ioc = 1; - dma_desc->status.b.bytes = ep->maxpacket; - dma_desc->buf = ep->dma_addr; - dma_desc->status.b.bs = BS_HOST_READY; - - /** DOEPDMA0 Register write */ - dwc_write_reg32(&out_regs->doepdma, core_if->dev_if->dma_out_desc_addr); - } - - - DWC_DEBUGPL(DBG_PCDV, "IN len=%d xfersize=%d pktcnt=%d [%08x]\n", - ep->xfer_len, - deptsiz.b.xfersize, deptsiz.b.pktcnt, deptsiz.d32); - - /* Write the DMA register */ - if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) { - if(core_if->dma_desc_enable == 0) - dwc_write_reg32 (&(out_regs->doepdma), (uint32_t)ep->dma_addr); - } - - /* EP enable, IN data in FIFO */ - depctl.b.cnak = 1; - depctl.b.epena = 1; - dwc_write_reg32(&out_regs->doepctl, depctl.d32); - - } -} - -#ifdef DEBUG -void dump_msg(const u8 *buf, unsigned int length) -{ - unsigned int start, num, i; - char line[52], *p; - - if (length >= 512) - return; - start = 0; - while (length > 0) { - num = min(length, 16u); - p = line; - for (i = 0; i < num; ++i) - { - if (i == 8) - *p++ = ' '; - sprintf(p, " %02x", buf[i]); - p += 3; - } - *p = 0; - DWC_PRINT("%6x: %s\n", start, line); - buf += num; - start += num; - length -= num; - } -} -#else -static inline void dump_msg(const u8 *buf, unsigned int length) -{ -} -#endif - -/** - * This function writes a packet into the Tx FIFO associated with the - * EP. For non-periodic EPs the non-periodic Tx FIFO is written. For - * periodic EPs the periodic Tx FIFO associated with the EP is written - * with all packets for the next micro-frame. - * - * @param core_if Programming view of DWC_otg controller. - * @param ep The EP to write packet for. - * @param dma Indicates if DMA is being used. - */ -void dwc_otg_ep_write_packet(dwc_otg_core_if_t *core_if, dwc_ep_t *ep, int dma) -{ - /** - * The buffer is padded to DWORD on a per packet basis in - * slave/dma mode if the MPS is not DWORD aligned. The last - * packet, if short, is also padded to a multiple of DWORD. - * - * ep->xfer_buff always starts DWORD aligned in memory and is a - * multiple of DWORD in length - * - * ep->xfer_len can be any number of bytes - * - * ep->xfer_count is a multiple of ep->maxpacket until the last - * packet - * - * FIFO access is DWORD */ - - uint32_t i; - uint32_t byte_count; - uint32_t dword_count; - uint32_t *fifo; - uint32_t *data_buff = (uint32_t *)ep->xfer_buff; - - DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, core_if, ep); - if (ep->xfer_count >= ep->xfer_len) { - DWC_WARN("%s() No data for EP%d!!!\n", __func__, ep->num); - return; - } - - /* Find the byte length of the packet either short packet or MPS */ - if ((ep->xfer_len - ep->xfer_count) < ep->maxpacket) { - byte_count = ep->xfer_len - ep->xfer_count; - } - else { - byte_count = ep->maxpacket; - } - - /* Find the DWORD length, padded by extra bytes as neccessary if MPS - * is not a multiple of DWORD */ - dword_count = (byte_count + 3) / 4; - -#ifdef VERBOSE - dump_msg(ep->xfer_buff, byte_count); -#endif - - /**@todo NGS Where are the Periodic Tx FIFO addresses - * intialized? What should this be? */ - - fifo = core_if->data_fifo[ep->num]; - - - DWC_DEBUGPL((DBG_PCDV|DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n", fifo, data_buff, *data_buff, byte_count); - - if (!dma) { - for (i=0; ixfer_count += byte_count; - ep->xfer_buff += byte_count; - ep->dma_addr += byte_count; -} - -/** - * Set the EP STALL. - * - * @param core_if Programming view of DWC_otg controller. - * @param ep The EP to set the stall on. - */ -void dwc_otg_ep_set_stall(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) -{ - depctl_data_t depctl; - volatile uint32_t *depctl_addr; - - DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num, - (ep->is_in?"IN":"OUT")); - - DWC_PRINT("%s ep%d-%s\n", __func__, ep->num, - (ep->is_in?"in":"out")); - - if (ep->is_in == 1) { - depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl); - depctl.d32 = dwc_read_reg32(depctl_addr); - - /* set the disable and stall bits */ - if (depctl.b.epena) { - depctl.b.epdis = 1; - } - depctl.b.stall = 1; - dwc_write_reg32(depctl_addr, depctl.d32); - } - else { - depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl); - depctl.d32 = dwc_read_reg32(depctl_addr); - - /* set the stall bit */ - depctl.b.stall = 1; - dwc_write_reg32(depctl_addr, depctl.d32); - } - - DWC_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",dwc_read_reg32(depctl_addr)); - - return; -} - -/** - * Clear the EP STALL. - * - * @param core_if Programming view of DWC_otg controller. - * @param ep The EP to clear stall from. - */ -void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) -{ - depctl_data_t depctl; - volatile uint32_t *depctl_addr; - - DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num, - (ep->is_in?"IN":"OUT")); - - if (ep->is_in == 1) { - depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl); - } - else { - depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl); - } - - depctl.d32 = dwc_read_reg32(depctl_addr); - - /* clear the stall bits */ - depctl.b.stall = 0; - - /* - * USB Spec 9.4.5: For endpoints using data toggle, regardless - * of whether an endpoint has the Halt feature set, a - * ClearFeature(ENDPOINT_HALT) request always results in the - * data toggle being reinitialized to DATA0. - */ - if (ep->type == DWC_OTG_EP_TYPE_INTR || - ep->type == DWC_OTG_EP_TYPE_BULK) { - depctl.b.setd0pid = 1; /* DATA0 */ - } - - dwc_write_reg32(depctl_addr, depctl.d32); - DWC_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",dwc_read_reg32(depctl_addr)); - return; -} - -/** - * This function reads a packet from the Rx FIFO into the destination - * buffer. To read SETUP data use dwc_otg_read_setup_packet. - * - * @param core_if Programming view of DWC_otg controller. - * @param dest Destination buffer for the packet. - * @param bytes Number of bytes to copy to the destination. - */ -void dwc_otg_read_packet(dwc_otg_core_if_t *core_if, - uint8_t *dest, - uint16_t bytes) -{ - int i; - int word_count = (bytes + 3) / 4; - - volatile uint32_t *fifo = core_if->data_fifo[0]; - uint32_t *data_buff = (uint32_t *)dest; - - /** - * @todo Account for the case where _dest is not dword aligned. This - * requires reading data from the FIFO into a uint32_t temp buffer, - * then moving it into the data buffer. - */ - - DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__, - core_if, dest, bytes); - - for (i=0; idev_if->dev_global_regs->dcfg; - DWC_PRINT("DCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->dev_if->dev_global_regs->dctl; - DWC_PRINT("DCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->dev_if->dev_global_regs->dsts; - DWC_PRINT("DSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->dev_if->dev_global_regs->diepmsk; - DWC_PRINT("DIEPMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->dev_if->dev_global_regs->doepmsk; - DWC_PRINT("DOEPMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->dev_if->dev_global_regs->daint; - DWC_PRINT("DAINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->dev_if->dev_global_regs->daintmsk; - DWC_PRINT("DAINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->dev_if->dev_global_regs->dtknqr1; - DWC_PRINT("DTKNQR1 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - if (core_if->hwcfg2.b.dev_token_q_depth > 6) { - addr=&core_if->dev_if->dev_global_regs->dtknqr2; - DWC_PRINT("DTKNQR2 @0x%08X : 0x%08X\n", - (uint32_t)addr,dwc_read_reg32(addr)); - } - - addr=&core_if->dev_if->dev_global_regs->dvbusdis; - DWC_PRINT("DVBUSID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - - addr=&core_if->dev_if->dev_global_regs->dvbuspulse; - DWC_PRINT("DVBUSPULSE @0x%08X : 0x%08X\n", - (uint32_t)addr,dwc_read_reg32(addr)); - - if (core_if->hwcfg2.b.dev_token_q_depth > 14) { - addr=&core_if->dev_if->dev_global_regs->dtknqr3_dthrctl; - DWC_PRINT("DTKNQR3_DTHRCTL @0x%08X : 0x%08X\n", - (uint32_t)addr, dwc_read_reg32(addr)); - } -/* - if (core_if->hwcfg2.b.dev_token_q_depth > 22) { - addr=&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk; - DWC_PRINT("DTKNQR4 @0x%08X : 0x%08X\n", - (uint32_t)addr, dwc_read_reg32(addr)); - } -*/ - addr=&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk; - DWC_PRINT("FIFOEMPMSK @0x%08X : 0x%08X\n", (uint32_t)addr, dwc_read_reg32(addr)); - - addr=&core_if->dev_if->dev_global_regs->deachint; - DWC_PRINT("DEACHINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->dev_if->dev_global_regs->deachintmsk; - DWC_PRINT("DEACHINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - - for (i=0; i<= core_if->dev_if->num_in_eps; i++) { - addr=&core_if->dev_if->dev_global_regs->diepeachintmsk[i]; - DWC_PRINT("DIEPEACHINTMSK[%d] @0x%08X : 0x%08X\n", i, (uint32_t)addr, dwc_read_reg32(addr)); - } - - - for (i=0; i<= core_if->dev_if->num_out_eps; i++) { - addr=&core_if->dev_if->dev_global_regs->doepeachintmsk[i]; - DWC_PRINT("DOEPEACHINTMSK[%d] @0x%08X : 0x%08X\n", i, (uint32_t)addr, dwc_read_reg32(addr)); - } - - for (i=0; i<= core_if->dev_if->num_in_eps; i++) { - DWC_PRINT("Device IN EP %d Registers\n", i); - addr=&core_if->dev_if->in_ep_regs[i]->diepctl; - DWC_PRINT("DIEPCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->dev_if->in_ep_regs[i]->diepint; - DWC_PRINT("DIEPINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->dev_if->in_ep_regs[i]->dieptsiz; - DWC_PRINT("DIETSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->dev_if->in_ep_regs[i]->diepdma; - DWC_PRINT("DIEPDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->dev_if->in_ep_regs[i]->dtxfsts; - DWC_PRINT("DTXFSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->dev_if->in_ep_regs[i]->diepdmab; - DWC_PRINT("DIEPDMAB @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - } - - - for (i=0; i<= core_if->dev_if->num_out_eps; i++) { - DWC_PRINT("Device OUT EP %d Registers\n", i); - addr=&core_if->dev_if->out_ep_regs[i]->doepctl; - DWC_PRINT("DOEPCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->dev_if->out_ep_regs[i]->doepfn; - DWC_PRINT("DOEPFN @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->dev_if->out_ep_regs[i]->doepint; - DWC_PRINT("DOEPINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->dev_if->out_ep_regs[i]->doeptsiz; - DWC_PRINT("DOETSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->dev_if->out_ep_regs[i]->doepdma; - DWC_PRINT("DOEPDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->dev_if->out_ep_regs[i]->doepdmab; - DWC_PRINT("DOEPDMAB @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - - } - - - - return; -} - -/** - * This functions reads the SPRAM and prints its content - * - * @param core_if Programming view of DWC_otg controller. - */ -void dwc_otg_dump_spram(dwc_otg_core_if_t *core_if) -{ - volatile uint8_t *addr, *start_addr, *end_addr; - - DWC_PRINT("SPRAM Data:\n"); - start_addr = (void*)core_if->core_global_regs; - DWC_PRINT("Base Address: 0x%8X\n", (uint32_t)start_addr); - start_addr += 0x00028000; - end_addr=(void*)core_if->core_global_regs; - end_addr += 0x000280e0; - - for(addr = start_addr; addr < end_addr; addr+=16) - { - DWC_PRINT("0x%8X:\t%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\n", (uint32_t)addr, - addr[0], - addr[1], - addr[2], - addr[3], - addr[4], - addr[5], - addr[6], - addr[7], - addr[8], - addr[9], - addr[10], - addr[11], - addr[12], - addr[13], - addr[14], - addr[15] - ); - } - - return; -} -/** - * This function reads the host registers and prints them - * - * @param core_if Programming view of DWC_otg controller. - */ -void dwc_otg_dump_host_registers(dwc_otg_core_if_t *core_if) -{ - int i; - volatile uint32_t *addr; - - DWC_PRINT("Host Global Registers\n"); - addr=&core_if->host_if->host_global_regs->hcfg; - DWC_PRINT("HCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->host_if->host_global_regs->hfir; - DWC_PRINT("HFIR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->host_if->host_global_regs->hfnum; - DWC_PRINT("HFNUM @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->host_if->host_global_regs->hptxsts; - DWC_PRINT("HPTXSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->host_if->host_global_regs->haint; - DWC_PRINT("HAINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->host_if->host_global_regs->haintmsk; - DWC_PRINT("HAINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=core_if->host_if->hprt0; - DWC_PRINT("HPRT0 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - - for (i=0; icore_params->host_channels; i++) - { - DWC_PRINT("Host Channel %d Specific Registers\n", i); - addr=&core_if->host_if->hc_regs[i]->hcchar; - DWC_PRINT("HCCHAR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->host_if->hc_regs[i]->hcsplt; - DWC_PRINT("HCSPLT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->host_if->hc_regs[i]->hcint; - DWC_PRINT("HCINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->host_if->hc_regs[i]->hcintmsk; - DWC_PRINT("HCINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->host_if->hc_regs[i]->hctsiz; - DWC_PRINT("HCTSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->host_if->hc_regs[i]->hcdma; - DWC_PRINT("HCDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - } - return; -} - -/** - * This function reads the core global registers and prints them - * - * @param core_if Programming view of DWC_otg controller. - */ -void dwc_otg_dump_global_registers(dwc_otg_core_if_t *core_if) -{ - int i; - volatile uint32_t *addr; - - DWC_PRINT("Core Global Registers\n"); - addr=&core_if->core_global_regs->gotgctl; - DWC_PRINT("GOTGCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->core_global_regs->gotgint; - DWC_PRINT("GOTGINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->core_global_regs->gahbcfg; - DWC_PRINT("GAHBCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->core_global_regs->gusbcfg; - DWC_PRINT("GUSBCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->core_global_regs->grstctl; - DWC_PRINT("GRSTCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->core_global_regs->gintsts; - DWC_PRINT("GINTSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->core_global_regs->gintmsk; - DWC_PRINT("GINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->core_global_regs->grxstsr; - DWC_PRINT("GRXSTSR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - //addr=&core_if->core_global_regs->grxstsp; - //DWC_PRINT("GRXSTSP @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->core_global_regs->grxfsiz; - DWC_PRINT("GRXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->core_global_regs->gnptxfsiz; - DWC_PRINT("GNPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->core_global_regs->gnptxsts; - DWC_PRINT("GNPTXSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->core_global_regs->gi2cctl; - DWC_PRINT("GI2CCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->core_global_regs->gpvndctl; - DWC_PRINT("GPVNDCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->core_global_regs->ggpio; - DWC_PRINT("GGPIO @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->core_global_regs->guid; - DWC_PRINT("GUID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->core_global_regs->gsnpsid; - DWC_PRINT("GSNPSID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->core_global_regs->ghwcfg1; - DWC_PRINT("GHWCFG1 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->core_global_regs->ghwcfg2; - DWC_PRINT("GHWCFG2 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->core_global_regs->ghwcfg3; - DWC_PRINT("GHWCFG3 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->core_global_regs->ghwcfg4; - DWC_PRINT("GHWCFG4 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - addr=&core_if->core_global_regs->hptxfsiz; - DWC_PRINT("HPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); - - for (i=0; ihwcfg4.b.num_dev_perio_in_ep; i++) - { - addr=&core_if->core_global_regs->dptxfsiz_dieptxf[i]; - DWC_PRINT("DPTXFSIZ[%d] @0x%08X : 0x%08X\n",i,(uint32_t)addr,dwc_read_reg32(addr)); - } -} - -/** - * Flush a Tx FIFO. - * - * @param core_if Programming view of DWC_otg controller. - * @param num Tx FIFO to flush. - */ -void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t *core_if, - const int num) -{ - dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; - volatile grstctl_t greset = { .d32 = 0}; - int count = 0; - - DWC_DEBUGPL((DBG_CIL|DBG_PCDV), "Flush Tx FIFO %d\n", num); - - greset.b.txfflsh = 1; - greset.b.txfnum = num; - dwc_write_reg32(&global_regs->grstctl, greset.d32); - - do { - greset.d32 = dwc_read_reg32(&global_regs->grstctl); - if (++count > 10000) { - DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n", - __func__, greset.d32, - dwc_read_reg32(&global_regs->gnptxsts)); - break; - } - } - while (greset.b.txfflsh == 1); - - /* Wait for 3 PHY Clocks*/ - UDELAY(1); -} - -/** - * Flush Rx FIFO. - * - * @param core_if Programming view of DWC_otg controller. - */ -void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t *core_if) -{ - dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; - volatile grstctl_t greset = { .d32 = 0}; - int count = 0; - - DWC_DEBUGPL((DBG_CIL|DBG_PCDV), "%s\n", __func__); - /* - * - */ - greset.b.rxfflsh = 1; - dwc_write_reg32(&global_regs->grstctl, greset.d32); - - do { - greset.d32 = dwc_read_reg32(&global_regs->grstctl); - if (++count > 10000) { - DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__, - greset.d32); - break; - } - } - while (greset.b.rxfflsh == 1); - - /* Wait for 3 PHY Clocks*/ - UDELAY(1); -} - -/** - * Do core a soft reset of the core. Be careful with this because it - * resets all the internal state machines of the core. - */ -void dwc_otg_core_reset(dwc_otg_core_if_t *core_if) -{ - dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; - volatile grstctl_t greset = { .d32 = 0}; - int count = 0; - - DWC_DEBUGPL(DBG_CILV, "%s\n", __func__); - /* Wait for AHB master IDLE state. */ - do { - UDELAY(10); - greset.d32 = dwc_read_reg32(&global_regs->grstctl); - if (++count > 100000) { - DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x\n", __func__, - greset.d32); - return; - } - } - while (greset.b.ahbidle == 0); - - /* Core Soft Reset */ - count = 0; - greset.b.csftrst = 1; - dwc_write_reg32(&global_regs->grstctl, greset.d32); - do { - greset.d32 = dwc_read_reg32(&global_regs->grstctl); - if (++count > 10000) { - DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n", __func__, - greset.d32); - break; - } - } - while (greset.b.csftrst == 1); - - /* Wait for 3 PHY Clocks*/ - MDELAY(100); -} - - - -/** - * Register HCD callbacks. The callbacks are used to start and stop - * the HCD for interrupt processing. - * - * @param core_if Programming view of DWC_otg controller. - * @param cb the HCD callback structure. - * @param p pointer to be passed to callback function (usb_hcd*). - */ -void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t *core_if, - dwc_otg_cil_callbacks_t *cb, - void *p) -{ - core_if->hcd_cb = cb; - cb->p = p; -} - -/** - * Register PCD callbacks. The callbacks are used to start and stop - * the PCD for interrupt processing. - * - * @param core_if Programming view of DWC_otg controller. - * @param cb the PCD callback structure. - * @param p pointer to be passed to callback function (pcd*). - */ -void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t *core_if, - dwc_otg_cil_callbacks_t *cb, - void *p) -{ - core_if->pcd_cb = cb; - cb->p = p; -} - -#ifdef DWC_EN_ISOC - -/** - * This function writes isoc data per 1 (micro)frame into tx fifo - * - * @param core_if Programming view of DWC_otg controller. - * @param ep The EP to start the transfer on. - * - */ -void write_isoc_frame_data(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) -{ - dwc_otg_dev_in_ep_regs_t *ep_regs; - dtxfsts_data_t txstatus = {.d32 = 0}; - uint32_t len = 0; - uint32_t dwords; - - ep->xfer_len = ep->data_per_frame; - ep->xfer_count = 0; - - ep_regs = core_if->dev_if->in_ep_regs[ep->num]; - - len = ep->xfer_len - ep->xfer_count; - - if (len > ep->maxpacket) { - len = ep->maxpacket; - } - - dwords = (len + 3)/4; - - /* While there is space in the queue and space in the FIFO and - * More data to tranfer, Write packets to the Tx FIFO */ - txstatus.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts); - DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n",ep->num,txstatus.d32); - - while (txstatus.b.txfspcavail > dwords && - ep->xfer_count < ep->xfer_len && - ep->xfer_len != 0) { - /* Write the FIFO */ - dwc_otg_ep_write_packet(core_if, ep, 0); - - len = ep->xfer_len - ep->xfer_count; - if (len > ep->maxpacket) { - len = ep->maxpacket; - } - - dwords = (len + 3)/4; - txstatus.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts); - DWC_DEBUGPL(DBG_PCDV,"dtxfsts[%d]=0x%08x\n", ep->num, txstatus.d32); - } -} - - -/** - * This function initializes a descriptor chain for Isochronous transfer - * - * @param core_if Programming view of DWC_otg controller. - * @param ep The EP to start the transfer on. - * - */ -void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) -{ - deptsiz_data_t deptsiz = { .d32 = 0 }; - depctl_data_t depctl = { .d32 = 0 }; - dsts_data_t dsts = { .d32 = 0 }; - volatile uint32_t *addr; - - if(ep->is_in) { - addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl; - } else { - addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl; - } - - ep->xfer_len = ep->data_per_frame; - ep->xfer_count = 0; - ep->xfer_buff = ep->cur_pkt_addr; - ep->dma_addr = ep->cur_pkt_dma_addr; - - if(ep->is_in) { - /* Program the transfer size and packet count - * as follows: xfersize = N * maxpacket + - * short_packet pktcnt = N + (short_packet - * exist ? 1 : 0) - */ - deptsiz.b.xfersize = ep->xfer_len; - deptsiz.b.pktcnt = - (ep->xfer_len - 1 + ep->maxpacket) / - ep->maxpacket; - deptsiz.b.mc = deptsiz.b.pktcnt; - dwc_write_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz, deptsiz.d32); - - /* Write the DMA register */ - if (core_if->dma_enable) { - dwc_write_reg32 (&(core_if->dev_if->in_ep_regs[ep->num]->diepdma), (uint32_t)ep->dma_addr); - } - } else { - deptsiz.b.pktcnt = - (ep->xfer_len + (ep->maxpacket - 1)) / - ep->maxpacket; - deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket; - - dwc_write_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doeptsiz, deptsiz.d32); - - if (core_if->dma_enable) { - dwc_write_reg32 (&(core_if->dev_if->out_ep_regs[ep->num]->doepdma), - (uint32_t)ep->dma_addr); - } - } - - - /** Enable endpoint, clear nak */ - - depctl.d32 = 0; - if(ep->bInterval == 1) { - dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); - ep->next_frame = dsts.b.soffn + ep->bInterval; - - if(ep->next_frame & 0x1) { - depctl.b.setd1pid = 1; - } else { - depctl.b.setd0pid = 1; - } - } else { - ep->next_frame += ep->bInterval; - - if(ep->next_frame & 0x1) { - depctl.b.setd1pid = 1; - } else { - depctl.b.setd0pid = 1; - } - } - depctl.b.epena = 1; - depctl.b.cnak = 1; - - dwc_modify_reg32(addr, 0, depctl.d32); - depctl.d32 = dwc_read_reg32(addr); - - if(ep->is_in && core_if->dma_enable == 0) { - write_isoc_frame_data(core_if, ep); - } - -} - -#endif //DWC_EN_ISOC diff --git a/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_cil.h b/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_cil.h deleted file mode 100644 index 95079920a9..0000000000 --- a/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_cil.h +++ /dev/null @@ -1,1098 +0,0 @@ -/* ========================================================================== - * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $ - * $Revision: 1.2 $ - * $Date: 2008-11-21 05:39:15 $ - * $Change: 1099526 $ - * - * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, - * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless - * otherwise expressly agreed to in writing between Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ - -#if !defined(__DWC_CIL_H__) -#define __DWC_CIL_H__ - -#include -#include -#include - -#include "linux/dwc_otg_plat.h" -#include "dwc_otg_regs.h" -#ifdef DEBUG -#include "linux/timer.h" -#endif - -/** - * @file - * This file contains the interface to the Core Interface Layer. - */ - - -/** Macros defined for DWC OTG HW Release verison */ -#define OTG_CORE_REV_2_00 0x4F542000 -#define OTG_CORE_REV_2_60a 0x4F54260A -#define OTG_CORE_REV_2_71a 0x4F54271A -#define OTG_CORE_REV_2_72a 0x4F54272A - -/** -*/ -typedef struct iso_pkt_info -{ - uint32_t offset; - uint32_t length; - int32_t status; -} iso_pkt_info_t; -/** - * The dwc_ep structure represents the state of a single - * endpoint when acting in device mode. It contains the data items - * needed for an endpoint to be activated and transfer packets. - */ -typedef struct dwc_ep -{ - /** EP number used for register address lookup */ - uint8_t num; - /** EP direction 0 = OUT */ - unsigned is_in : 1; - /** EP active. */ - unsigned active : 1; - - /** Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic Tx FIFO - If dedicated Tx FIFOs are enabled for all IN Eps - Tx FIFO # FOR IN EPs*/ - unsigned tx_fifo_num : 4; - /** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */ - unsigned type : 2; -#define DWC_OTG_EP_TYPE_CONTROL 0 -#define DWC_OTG_EP_TYPE_ISOC 1 -#define DWC_OTG_EP_TYPE_BULK 2 -#define DWC_OTG_EP_TYPE_INTR 3 - - /** DATA start PID for INTR and BULK EP */ - unsigned data_pid_start : 1; - /** Frame (even/odd) for ISOC EP */ - unsigned even_odd_frame : 1; - /** Max Packet bytes */ - unsigned maxpacket : 11; - - /** Max Transfer size */ - unsigned maxxfer : 16; - - /** @name Transfer state */ - /** @{ */ - - /** - * Pointer to the beginning of the transfer buffer -- do not modify - * during transfer. - */ - - uint32_t dma_addr; - - uint32_t dma_desc_addr; - dwc_otg_dma_desc_t* desc_addr; - - - uint8_t *start_xfer_buff; - /** pointer to the transfer buffer */ - uint8_t *xfer_buff; - /** Number of bytes to transfer */ - unsigned xfer_len : 19; - /** Number of bytes transferred. */ - unsigned xfer_count : 19; - /** Sent ZLP */ - unsigned sent_zlp : 1; - /** Total len for control transfer */ - unsigned total_len : 19; - - /** stall clear flag */ - unsigned stall_clear_flag : 1; - - /** Allocated DMA Desc count */ - uint32_t desc_cnt; - -#ifdef DWC_EN_ISOC - /** - * Variables specific for ISOC EPs - * - */ - /** DMA addresses of ISOC buffers */ - uint32_t dma_addr0; - uint32_t dma_addr1; - - uint32_t iso_dma_desc_addr; - dwc_otg_dma_desc_t* iso_desc_addr; - - /** pointer to the transfer buffers */ - uint8_t *xfer_buff0; - uint8_t *xfer_buff1; - - /** number of ISOC Buffer is processing */ - uint32_t proc_buf_num; - /** Interval of ISOC Buffer processing */ - uint32_t buf_proc_intrvl; - /** Data size for regular frame */ - uint32_t data_per_frame; - - /* todo - pattern data support is to be implemented in the future */ - /** Data size for pattern frame */ - uint32_t data_pattern_frame; - /** Frame number of pattern data */ - uint32_t sync_frame; - - /** bInterval */ - uint32_t bInterval; - /** ISO Packet number per frame */ - uint32_t pkt_per_frm; - /** Next frame num for which will be setup DMA Desc */ - uint32_t next_frame; - /** Number of packets per buffer processing */ - uint32_t pkt_cnt; - /** Info for all isoc packets */ - iso_pkt_info_t *pkt_info; - /** current pkt number */ - uint32_t cur_pkt; - /** current pkt number */ - uint8_t *cur_pkt_addr; - /** current pkt number */ - uint32_t cur_pkt_dma_addr; -#endif //DWC_EN_ISOC -/** @} */ -} dwc_ep_t; - -/* - * Reasons for halting a host channel. - */ -typedef enum dwc_otg_halt_status -{ - DWC_OTG_HC_XFER_NO_HALT_STATUS, - DWC_OTG_HC_XFER_COMPLETE, - DWC_OTG_HC_XFER_URB_COMPLETE, - DWC_OTG_HC_XFER_ACK, - DWC_OTG_HC_XFER_NAK, - DWC_OTG_HC_XFER_NYET, - DWC_OTG_HC_XFER_STALL, - DWC_OTG_HC_XFER_XACT_ERR, - DWC_OTG_HC_XFER_FRAME_OVERRUN, - DWC_OTG_HC_XFER_BABBLE_ERR, - DWC_OTG_HC_XFER_DATA_TOGGLE_ERR, - DWC_OTG_HC_XFER_AHB_ERR, - DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE, - DWC_OTG_HC_XFER_URB_DEQUEUE -} dwc_otg_halt_status_e; - -/** - * Host channel descriptor. This structure represents the state of a single - * host channel when acting in host mode. It contains the data items needed to - * transfer packets to an endpoint via a host channel. - */ -typedef struct dwc_hc -{ - /** Host channel number used for register address lookup */ - uint8_t hc_num; - - /** Device to access */ - unsigned dev_addr : 7; - - /** EP to access */ - unsigned ep_num : 4; - - /** EP direction. 0: OUT, 1: IN */ - unsigned ep_is_in : 1; - - /** - * EP speed. - * One of the following values: - * - DWC_OTG_EP_SPEED_LOW - * - DWC_OTG_EP_SPEED_FULL - * - DWC_OTG_EP_SPEED_HIGH - */ - unsigned speed : 2; -#define DWC_OTG_EP_SPEED_LOW 0 -#define DWC_OTG_EP_SPEED_FULL 1 -#define DWC_OTG_EP_SPEED_HIGH 2 - - /** - * Endpoint type. - * One of the following values: - * - DWC_OTG_EP_TYPE_CONTROL: 0 - * - DWC_OTG_EP_TYPE_ISOC: 1 - * - DWC_OTG_EP_TYPE_BULK: 2 - * - DWC_OTG_EP_TYPE_INTR: 3 - */ - unsigned ep_type : 2; - - /** Max packet size in bytes */ - unsigned max_packet : 11; - - /** - * PID for initial transaction. - * 0: DATA0,
- * 1: DATA2,
- * 2: DATA1,
- * 3: MDATA (non-Control EP), - * SETUP (Control EP) - */ - unsigned data_pid_start : 2; -#define DWC_OTG_HC_PID_DATA0 0 -#define DWC_OTG_HC_PID_DATA2 1 -#define DWC_OTG_HC_PID_DATA1 2 -#define DWC_OTG_HC_PID_MDATA 3 -#define DWC_OTG_HC_PID_SETUP 3 - - /** Number of periodic transactions per (micro)frame */ - unsigned multi_count: 2; - - /** @name Transfer State */ - /** @{ */ - - /** Pointer to the current transfer buffer position. */ - uint8_t *xfer_buff; - /** Total number of bytes to transfer. */ - uint32_t xfer_len; - /** Number of bytes transferred so far. */ - uint32_t xfer_count; - /** Packet count at start of transfer.*/ - uint16_t start_pkt_count; - - /** - * Flag to indicate whether the transfer has been started. Set to 1 if - * it has been started, 0 otherwise. - */ - uint8_t xfer_started; - - /** - * Set to 1 to indicate that a PING request should be issued on this - * channel. If 0, process normally. - */ - uint8_t do_ping; - - /** - * Set to 1 to indicate that the error count for this transaction is - * non-zero. Set to 0 if the error count is 0. - */ - uint8_t error_state; - - /** - * Set to 1 to indicate that this channel should be halted the next - * time a request is queued for the channel. This is necessary in - * slave mode if no request queue space is available when an attempt - * is made to halt the channel. - */ - uint8_t halt_on_queue; - - /** - * Set to 1 if the host channel has been halted, but the core is not - * finished flushing queued requests. Otherwise 0. - */ - uint8_t halt_pending; - - /** - * Reason for halting the host channel. - */ - dwc_otg_halt_status_e halt_status; - - /* - * Split settings for the host channel - */ - uint8_t do_split; /**< Enable split for the channel */ - uint8_t complete_split; /**< Enable complete split */ - uint8_t hub_addr; /**< Address of high speed hub */ - - uint8_t port_addr; /**< Port of the low/full speed device */ - /** Split transaction position - * One of the following values: - * - DWC_HCSPLIT_XACTPOS_MID - * - DWC_HCSPLIT_XACTPOS_BEGIN - * - DWC_HCSPLIT_XACTPOS_END - * - DWC_HCSPLIT_XACTPOS_ALL */ - uint8_t xact_pos; - - /** Set when the host channel does a short read. */ - uint8_t short_read; - - /** - * Number of requests issued for this channel since it was assigned to - * the current transfer (not counting PINGs). - */ - uint8_t requests; - - /** - * Queue Head for the transfer being processed by this channel. - */ - struct dwc_otg_qh *qh; - - /** @} */ - - /** Entry in list of host channels. */ - struct list_head hc_list_entry; -} dwc_hc_t; - -/** - * The following parameters may be specified when starting the module. These - * parameters define how the DWC_otg controller should be configured. - * Parameter values are passed to the CIL initialization function - * dwc_otg_cil_init. - */ -typedef struct dwc_otg_core_params -{ - int32_t opt; -#define dwc_param_opt_default 1 - - /** - * Specifies the OTG capabilities. The driver will automatically - * detect the value for this parameter if none is specified. - * 0 - HNP and SRP capable (default) - * 1 - SRP Only capable - * 2 - No HNP/SRP capable - */ - int32_t otg_cap; -#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0 -#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1 -#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 -#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE - - /** - * Specifies whether to use slave or DMA mode for accessing the data - * FIFOs. The driver will automatically detect the value for this - * parameter if none is specified. - * 0 - Slave - * 1 - DMA (default, if available) - */ - int32_t dma_enable; -#define dwc_param_dma_enable_default 1 - - /** - * When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data - * FIFOs in device mode. The driver will automatically detect the value for this - * parameter if none is specified. - * 0 - address DMA - * 1 - DMA Descriptor(default, if available) - */ - int32_t dma_desc_enable; -#define dwc_param_dma_desc_enable_default 0 - /** The DMA Burst size (applicable only for External DMA - * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32) - */ - int32_t dma_burst_size; /* Translate this to GAHBCFG values */ -#define dwc_param_dma_burst_size_default 32 - - /** - * Specifies the maximum speed of operation in host and device mode. - * The actual speed depends on the speed of the attached device and - * the value of phy_type. The actual speed depends on the speed of the - * attached device. - * 0 - High Speed (default) - * 1 - Full Speed - */ - int32_t speed; -#define dwc_param_speed_default 0 -#define DWC_SPEED_PARAM_HIGH 0 -#define DWC_SPEED_PARAM_FULL 1 - - /** Specifies whether low power mode is supported when attached - * to a Full Speed or Low Speed device in host mode. - * 0 - Don't support low power mode (default) - * 1 - Support low power mode - */ - int32_t host_support_fs_ls_low_power; -#define dwc_param_host_support_fs_ls_low_power_default 0 - - /** Specifies the PHY clock rate in low power mode when connected to a - * Low Speed device in host mode. This parameter is applicable only if - * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS - * then defaults to 6 MHZ otherwise 48 MHZ. - * - * 0 - 48 MHz - * 1 - 6 MHz - */ - int32_t host_ls_low_power_phy_clk; -#define dwc_param_host_ls_low_power_phy_clk_default 0 -#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 -#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 - - /** - * 0 - Use cC FIFO size parameters - * 1 - Allow dynamic FIFO sizing (default) - */ - int32_t enable_dynamic_fifo; -#define dwc_param_enable_dynamic_fifo_default 1 - - /** Total number of 4-byte words in the data FIFO memory. This - * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic - * Tx FIFOs. - * 32 to 32768 (default 8192) - * Note: The total FIFO memory depth in the FPGA configuration is 8192. - */ - int32_t data_fifo_size; -#define dwc_param_data_fifo_size_default 8192 - - /** Number of 4-byte words in the Rx FIFO in device mode when dynamic - * FIFO sizing is enabled. - * 16 to 32768 (default 1064) - */ - int32_t dev_rx_fifo_size; -#define dwc_param_dev_rx_fifo_size_default 1064 - - /** Number of 4-byte words in the non-periodic Tx FIFO in device mode - * when dynamic FIFO sizing is enabled. - * 16 to 32768 (default 1024) - */ - int32_t dev_nperio_tx_fifo_size; -#define dwc_param_dev_nperio_tx_fifo_size_default 1024 - - /** Number of 4-byte words in each of the periodic Tx FIFOs in device - * mode when dynamic FIFO sizing is enabled. - * 4 to 768 (default 256) - */ - uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS]; -#define dwc_param_dev_perio_tx_fifo_size_default 256 - - /** Number of 4-byte words in the Rx FIFO in host mode when dynamic - * FIFO sizing is enabled. - * 16 to 32768 (default 1024) - */ - int32_t host_rx_fifo_size; -#define dwc_param_host_rx_fifo_size_default 1024 - - /** Number of 4-byte words in the non-periodic Tx FIFO in host mode - * when Dynamic FIFO sizing is enabled in the core. - * 16 to 32768 (default 1024) - */ - int32_t host_nperio_tx_fifo_size; -#define dwc_param_host_nperio_tx_fifo_size_default 1024 - - /** Number of 4-byte words in the host periodic Tx FIFO when dynamic - * FIFO sizing is enabled. - * 16 to 32768 (default 1024) - */ - int32_t host_perio_tx_fifo_size; -#define dwc_param_host_perio_tx_fifo_size_default 1024 - - /** The maximum transfer size supported in bytes. - * 2047 to 65,535 (default 65,535) - */ - int32_t max_transfer_size; -#define dwc_param_max_transfer_size_default 65535 - - /** The maximum number of packets in a transfer. - * 15 to 511 (default 511) - */ - int32_t max_packet_count; -#define dwc_param_max_packet_count_default 511 - - /** The number of host channel registers to use. - * 1 to 16 (default 12) - * Note: The FPGA configuration supports a maximum of 12 host channels. - */ - int32_t host_channels; -#define dwc_param_host_channels_default 12 - - /** The number of endpoints in addition to EP0 available for device - * mode operations. - * 1 to 15 (default 6 IN and OUT) - * Note: The FPGA configuration supports a maximum of 6 IN and OUT - * endpoints in addition to EP0. - */ - int32_t dev_endpoints; -#define dwc_param_dev_endpoints_default 6 - - /** - * Specifies the type of PHY interface to use. By default, the driver - * will automatically detect the phy_type. - * - * 0 - Full Speed PHY - * 1 - UTMI+ (default) - * 2 - ULPI - */ - int32_t phy_type; -#define DWC_PHY_TYPE_PARAM_FS 0 -#define DWC_PHY_TYPE_PARAM_UTMI 1 -#define DWC_PHY_TYPE_PARAM_ULPI 2 -#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI - - /** - * Specifies the UTMI+ Data Width. This parameter is - * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI - * PHY_TYPE, this parameter indicates the data width between - * the MAC and the ULPI Wrapper.) Also, this parameter is - * applicable only if the OTG_HSPHY_WIDTH cC parameter was set - * to "8 and 16 bits", meaning that the core has been - * configured to work at either data path width. - * - * 8 or 16 bits (default 16) - */ - int32_t phy_utmi_width; -#define dwc_param_phy_utmi_width_default 16 - - /** - * Specifies whether the ULPI operates at double or single - * data rate. This parameter is only applicable if PHY_TYPE is - * ULPI. - * - * 0 - single data rate ULPI interface with 8 bit wide data - * bus (default) - * 1 - double data rate ULPI interface with 4 bit wide data - * bus - */ - int32_t phy_ulpi_ddr; -#define dwc_param_phy_ulpi_ddr_default 0 - - /** - * Specifies whether to use the internal or external supply to - * drive the vbus with a ULPI phy. - */ - int32_t phy_ulpi_ext_vbus; -#define DWC_PHY_ULPI_INTERNAL_VBUS 0 -#define DWC_PHY_ULPI_EXTERNAL_VBUS 1 -#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS - - /** - * Specifies whether to use the I2Cinterface for full speed PHY. This - * parameter is only applicable if PHY_TYPE is FS. - * 0 - No (default) - * 1 - Yes - */ - int32_t i2c_enable; -#define dwc_param_i2c_enable_default 0 - - int32_t ulpi_fs_ls; -#define dwc_param_ulpi_fs_ls_default 0 - - int32_t ts_dline; -#define dwc_param_ts_dline_default 0 - - /** - * Specifies whether dedicated transmit FIFOs are - * enabled for non periodic IN endpoints in device mode - * 0 - No - * 1 - Yes - */ - int32_t en_multiple_tx_fifo; -#define dwc_param_en_multiple_tx_fifo_default 1 - - /** Number of 4-byte words in each of the Tx FIFOs in device - * mode when dynamic FIFO sizing is enabled. - * 4 to 768 (default 256) - */ - uint32_t dev_tx_fifo_size[MAX_TX_FIFOS]; -#define dwc_param_dev_tx_fifo_size_default 256 - - /** Thresholding enable flag- - * bit 0 - enable non-ISO Tx thresholding - * bit 1 - enable ISO Tx thresholding - * bit 2 - enable Rx thresholding - */ - uint32_t thr_ctl; -#define dwc_param_thr_ctl_default 0 - - /** Thresholding length for Tx - * FIFOs in 32 bit DWORDs - */ - uint32_t tx_thr_length; -#define dwc_param_tx_thr_length_default 64 - - /** Thresholding length for Rx - * FIFOs in 32 bit DWORDs - */ - uint32_t rx_thr_length; -#define dwc_param_rx_thr_length_default 64 - - /** Per Transfer Interrupt - * mode enable flag - * 1 - Enabled - * 0 - Disabled - */ - uint32_t pti_enable; -#define dwc_param_pti_enable_default 0 - - /** Molti Processor Interrupt - * mode enable flag - * 1 - Enabled - * 0 - Disabled - */ - uint32_t mpi_enable; -#define dwc_param_mpi_enable_default 0 - -} dwc_otg_core_params_t; - -#ifdef DEBUG -struct dwc_otg_core_if; -typedef struct hc_xfer_info -{ - struct dwc_otg_core_if *core_if; - dwc_hc_t *hc; -} hc_xfer_info_t; -#endif - -/** - * The dwc_otg_core_if structure contains information needed to manage - * the DWC_otg controller acting in either host or device mode. It - * represents the programming view of the controller as a whole. - */ -typedef struct dwc_otg_core_if -{ - /** Parameters that define how the core should be configured.*/ - dwc_otg_core_params_t *core_params; - - /** Core Global registers starting at offset 000h. */ - dwc_otg_core_global_regs_t *core_global_regs; - - /** Device-specific information */ - dwc_otg_dev_if_t *dev_if; - /** Host-specific information */ - dwc_otg_host_if_t *host_if; - - /** Value from SNPSID register */ - uint32_t snpsid; - - /* - * Set to 1 if the core PHY interface bits in USBCFG have been - * initialized. - */ - uint8_t phy_init_done; - - /* - * SRP Success flag, set by srp success interrupt in FS I2C mode - */ - uint8_t srp_success; - uint8_t srp_timer_started; - - /* Common configuration information */ - /** Power and Clock Gating Control Register */ - volatile uint32_t *pcgcctl; -#define DWC_OTG_PCGCCTL_OFFSET 0xE00 - - /** Push/pop addresses for endpoints or host channels.*/ - uint32_t *data_fifo[MAX_EPS_CHANNELS]; -#define DWC_OTG_DATA_FIFO_OFFSET 0x1000 -#define DWC_OTG_DATA_FIFO_SIZE 0x1000 - - /** Total RAM for FIFOs (Bytes) */ - uint16_t total_fifo_size; - /** Size of Rx FIFO (Bytes) */ - uint16_t rx_fifo_size; - /** Size of Non-periodic Tx FIFO (Bytes) */ - uint16_t nperio_tx_fifo_size; - - - /** 1 if DMA is enabled, 0 otherwise. */ - uint8_t dma_enable; - - /** 1 if Descriptor DMA mode is enabled, 0 otherwise. */ - uint8_t dma_desc_enable; - - /** 1 if PTI Enhancement mode is enabled, 0 otherwise. */ - uint8_t pti_enh_enable; - - /** 1 if MPI Enhancement mode is enabled, 0 otherwise. */ - uint8_t multiproc_int_enable; - - /** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */ - uint8_t en_multiple_tx_fifo; - - /** Set to 1 if multiple packets of a high-bandwidth transfer is in - * process of being queued */ - uint8_t queuing_high_bandwidth; - - /** Hardware Configuration -- stored here for convenience.*/ - hwcfg1_data_t hwcfg1; - hwcfg2_data_t hwcfg2; - hwcfg3_data_t hwcfg3; - hwcfg4_data_t hwcfg4; - - /** Host and Device Configuration -- stored here for convenience.*/ - hcfg_data_t hcfg; - dcfg_data_t dcfg; - - /** The operational State, during transations - * (a_host>>a_peripherial and b_device=>b_host) this may not - * match the core but allows the software to determine - * transitions. - */ - uint8_t op_state; - - /** - * Set to 1 if the HCD needs to be restarted on a session request - * interrupt. This is required if no connector ID status change has - * occurred since the HCD was last disconnected. - */ - uint8_t restart_hcd_on_session_req; - - /** HCD callbacks */ - /** A-Device is a_host */ -#define A_HOST (1) - /** A-Device is a_suspend */ -#define A_SUSPEND (2) - /** A-Device is a_peripherial */ -#define A_PERIPHERAL (3) - /** B-Device is operating as a Peripheral. */ -#define B_PERIPHERAL (4) - /** B-Device is operating as a Host. */ -#define B_HOST (5) - - /** HCD callbacks */ - struct dwc_otg_cil_callbacks *hcd_cb; - /** PCD callbacks */ - struct dwc_otg_cil_callbacks *pcd_cb; - - /** Device mode Periodic Tx FIFO Mask */ - uint32_t p_tx_msk; - /** Device mode Periodic Tx FIFO Mask */ - uint32_t tx_msk; - - /** Workqueue object used for handling several interrupts */ - struct workqueue_struct *wq_otg; - - /** Work object used for handling "Connector ID Status Change" Interrupt */ - struct work_struct w_conn_id; - - /** Work object used for handling "Wakeup Detected" Interrupt */ -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) - struct work_struct w_wkp; -#else - struct delayed_work w_wkp; -#endif - -#ifdef DEBUG - uint32_t start_hcchar_val[MAX_EPS_CHANNELS]; - - hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS]; - struct timer_list hc_xfer_timer[MAX_EPS_CHANNELS]; - - uint32_t hfnum_7_samples; - uint64_t hfnum_7_frrem_accum; - uint32_t hfnum_0_samples; - uint64_t hfnum_0_frrem_accum; - uint32_t hfnum_other_samples; - uint64_t hfnum_other_frrem_accum; -#endif - - -} dwc_otg_core_if_t; - -/*We must clear S3C24XX_EINTPEND external interrupt register - * because after clearing in this register trigerred IRQ from - * H/W core in kernel interrupt can be occured again before OTG - * handlers clear all IRQ sources of Core registers because of - * timing latencies and Low Level IRQ Type. - */ - -#ifdef CONFIG_MACH_IPMATE -#define S3C2410X_CLEAR_EINTPEND() \ -do { \ - if (!dwc_otg_read_core_intr(core_if)) { \ - __raw_writel(1UL << 11,S3C24XX_EINTPEND); \ - } \ -} while (0) -#else -#define S3C2410X_CLEAR_EINTPEND() do { } while (0) -#endif - -/* - * The following functions are functions for works - * using during handling some interrupts - */ -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) - -extern void w_conn_id_status_change(void *p); -extern void w_wakeup_detected(void *p); - -#else - -extern void w_conn_id_status_change(struct work_struct *p); -extern void w_wakeup_detected(struct work_struct *p); - -#endif - - -/* - * The following functions support initialization of the CIL driver component - * and the DWC_otg controller. - */ -extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *_reg_base_addr, - dwc_otg_core_params_t *_core_params); -extern void dwc_otg_cil_remove(dwc_otg_core_if_t *_core_if); -extern void dwc_otg_core_init(dwc_otg_core_if_t *_core_if); -extern void dwc_otg_core_host_init(dwc_otg_core_if_t *_core_if); -extern void dwc_otg_core_dev_init(dwc_otg_core_if_t *_core_if); -extern void dwc_otg_enable_global_interrupts( dwc_otg_core_if_t *_core_if ); -extern void dwc_otg_disable_global_interrupts( dwc_otg_core_if_t *_core_if ); - -/** @name Device CIL Functions - * The following functions support managing the DWC_otg controller in device - * mode. - */ -/**@{*/ -extern void dwc_otg_wakeup(dwc_otg_core_if_t *_core_if); -extern void dwc_otg_read_setup_packet (dwc_otg_core_if_t *_core_if, uint32_t *_dest); -extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *_core_if); -extern void dwc_otg_ep0_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); -extern void dwc_otg_ep_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); -extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); -extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); -extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); -extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); -extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); -extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep, int _dma); -extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); -extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); -extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *_core_if); -extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t *_core_if); -extern void dwc_otg_dump_spram(dwc_otg_core_if_t *_core_if); -#ifdef DWC_EN_ISOC -extern void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep); -extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep); -#endif //DWC_EN_ISOC -/**@}*/ - -/** @name Host CIL Functions - * The following functions support managing the DWC_otg controller in host - * mode. - */ -/**@{*/ -extern void dwc_otg_hc_init(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc); -extern void dwc_otg_hc_halt(dwc_otg_core_if_t *_core_if, - dwc_hc_t *_hc, - dwc_otg_halt_status_e _halt_status); -extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc); -extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc); -extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc); -extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc); -extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc); -extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *_core_if); -extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *_core_if); - -/** - * This function Reads HPRT0 in preparation to modify. It keeps the - * WC bits 0 so that if they are read as 1, they won't clear when you - * write it back - */ -static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t *_core_if) -{ - hprt0_data_t hprt0; - hprt0.d32 = dwc_read_reg32(_core_if->host_if->hprt0); - hprt0.b.prtena = 0; - hprt0.b.prtconndet = 0; - hprt0.b.prtenchng = 0; - hprt0.b.prtovrcurrchng = 0; - return hprt0.d32; -} - -extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t *_core_if); -/**@}*/ - -/** @name Common CIL Functions - * The following functions support managing the DWC_otg controller in either - * device or host mode. - */ -/**@{*/ - -extern void dwc_otg_read_packet(dwc_otg_core_if_t *core_if, - uint8_t *dest, - uint16_t bytes); - -extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t *_core_if); - -extern void dwc_otg_flush_tx_fifo( dwc_otg_core_if_t *_core_if, - const int _num ); -extern void dwc_otg_flush_rx_fifo( dwc_otg_core_if_t *_core_if ); -extern void dwc_otg_core_reset( dwc_otg_core_if_t *_core_if ); - -extern dwc_otg_dma_desc_t* dwc_otg_ep_alloc_desc_chain(uint32_t * dma_desc_addr, uint32_t count); -extern void dwc_otg_ep_free_desc_chain(dwc_otg_dma_desc_t* desc_addr, uint32_t dma_desc_addr, uint32_t count); - -/** - * This function returns the Core Interrupt register. - */ -static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t *_core_if) -{ - return (dwc_read_reg32(&_core_if->core_global_regs->gintsts) & - dwc_read_reg32(&_core_if->core_global_regs->gintmsk)); -} - -/** - * This function returns the OTG Interrupt register. - */ -static inline uint32_t dwc_otg_read_otg_intr (dwc_otg_core_if_t *_core_if) -{ - return (dwc_read_reg32 (&_core_if->core_global_regs->gotgint)); -} - -/** - * This function reads the Device All Endpoints Interrupt register and - * returns the IN endpoint interrupt bits. - */ -static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *core_if) -{ - uint32_t v; - - if(core_if->multiproc_int_enable) { - v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachint) & - dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachintmsk); - } else { - v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->daint) & - dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk); - } - return (v & 0xffff); - -} - -/** - * This function reads the Device All Endpoints Interrupt register and - * returns the OUT endpoint interrupt bits. - */ -static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *core_if) -{ - uint32_t v; - - if(core_if->multiproc_int_enable) { - v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachint) & - dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachintmsk); - } else { - v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->daint) & - dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk); - } - - return ((v & 0xffff0000) >> 16); -} - -/** - * This function returns the Device IN EP Interrupt register - */ -static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t *core_if, - dwc_ep_t *ep) -{ - dwc_otg_dev_if_t *dev_if = core_if->dev_if; - uint32_t v, msk, emp; - - if(core_if->multiproc_int_enable) { - msk = dwc_read_reg32(&dev_if->dev_global_regs->diepeachintmsk[ep->num]); - emp = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk); - msk |= ((emp >> ep->num) & 0x1) << 7; - v = dwc_read_reg32(&dev_if->in_ep_regs[ep->num]->diepint) & msk; - } else { - msk = dwc_read_reg32(&dev_if->dev_global_regs->diepmsk); - emp = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk); - msk |= ((emp >> ep->num) & 0x1) << 7; - v = dwc_read_reg32(&dev_if->in_ep_regs[ep->num]->diepint) & msk; - } - - - return v; -} -/** - * This function returns the Device OUT EP Interrupt register - */ -static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *_core_if, - dwc_ep_t *_ep) -{ - dwc_otg_dev_if_t *dev_if = _core_if->dev_if; - uint32_t v; - doepmsk_data_t msk = { .d32 = 0 }; - - if(_core_if->multiproc_int_enable) { - msk.d32 = dwc_read_reg32(&dev_if->dev_global_regs->doepeachintmsk[_ep->num]); - if(_core_if->pti_enh_enable) { - msk.b.pktdrpsts = 1; - } - v = dwc_read_reg32( &dev_if->out_ep_regs[_ep->num]->doepint) & msk.d32; - } else { - msk.d32 = dwc_read_reg32(&dev_if->dev_global_regs->doepmsk); - if(_core_if->pti_enh_enable) { - msk.b.pktdrpsts = 1; - } - v = dwc_read_reg32( &dev_if->out_ep_regs[_ep->num]->doepint) & msk.d32; - } - return v; -} - -/** - * This function returns the Host All Channel Interrupt register - */ -static inline uint32_t dwc_otg_read_host_all_channels_intr (dwc_otg_core_if_t *_core_if) -{ - return (dwc_read_reg32 (&_core_if->host_if->host_global_regs->haint)); -} - -static inline uint32_t dwc_otg_read_host_channel_intr (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc) -{ - return (dwc_read_reg32 (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint)); -} - - -/** - * This function returns the mode of the operation, host or device. - * - * @return 0 - Device Mode, 1 - Host Mode - */ -static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t *_core_if) -{ - return (dwc_read_reg32( &_core_if->core_global_regs->gintsts ) & 0x1); -} - -static inline uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t *_core_if) -{ - return (dwc_otg_mode(_core_if) != DWC_HOST_MODE); -} -static inline uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t *_core_if) -{ - return (dwc_otg_mode(_core_if) == DWC_HOST_MODE); -} - -extern int32_t dwc_otg_handle_common_intr( dwc_otg_core_if_t *_core_if ); - - -/**@}*/ - -/** - * DWC_otg CIL callback structure. This structure allows the HCD and - * PCD to register functions used for starting and stopping the PCD - * and HCD for role change on for a DRD. - */ -typedef struct dwc_otg_cil_callbacks -{ - /** Start function for role change */ - int (*start) (void *_p); - /** Stop Function for role change */ - int (*stop) (void *_p); - /** Disconnect Function for role change */ - int (*disconnect) (void *_p); - /** Resume/Remote wakeup Function */ - int (*resume_wakeup) (void *_p); - /** Suspend function */ - int (*suspend) (void *_p); - /** Session Start (SRP) */ - int (*session_start) (void *_p); - /** Pointer passed to start() and stop() */ - void *p; -} dwc_otg_cil_callbacks_t; - -extern void dwc_otg_cil_register_pcd_callbacks( dwc_otg_core_if_t *_core_if, - dwc_otg_cil_callbacks_t *_cb, - void *_p); -extern void dwc_otg_cil_register_hcd_callbacks( dwc_otg_core_if_t *_core_if, - dwc_otg_cil_callbacks_t *_cb, - void *_p); - -#endif - diff --git a/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_cil_intr.c b/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_cil_intr.c deleted file mode 100644 index 61b17b35dc..0000000000 --- a/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_cil_intr.c +++ /dev/null @@ -1,750 +0,0 @@ -/* ========================================================================== - * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $ - * $Revision: 1.2 $ - * $Date: 2008-11-21 05:39:15 $ - * $Change: 1065567 $ - * - * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, - * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless - * otherwise expressly agreed to in writing between Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ - -/** @file - * - * The Core Interface Layer provides basic services for accessing and - * managing the DWC_otg hardware. These services are used by both the - * Host Controller Driver and the Peripheral Controller Driver. - * - * This file contains the Common Interrupt handlers. - */ -#include "linux/dwc_otg_plat.h" -#include "dwc_otg_regs.h" -#include "dwc_otg_cil.h" - -#ifdef DEBUG -inline const char *op_state_str(dwc_otg_core_if_t *core_if) -{ - return (core_if->op_state==A_HOST?"a_host": - (core_if->op_state==A_SUSPEND?"a_suspend": - (core_if->op_state==A_PERIPHERAL?"a_peripheral": - (core_if->op_state==B_PERIPHERAL?"b_peripheral": - (core_if->op_state==B_HOST?"b_host": - "unknown"))))); -} -#endif - -/** This function will log a debug message - * - * @param core_if Programming view of DWC_otg controller. - */ -int32_t dwc_otg_handle_mode_mismatch_intr (dwc_otg_core_if_t *core_if) -{ - gintsts_data_t gintsts; - DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n", - dwc_otg_mode(core_if) ? "Host" : "Device"); - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.modemismatch = 1; - dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32); - return 1; -} - -/** Start the HCD. Helper function for using the HCD callbacks. - * - * @param core_if Programming view of DWC_otg controller. - */ -static inline void hcd_start(dwc_otg_core_if_t *core_if) -{ - if (core_if->hcd_cb && core_if->hcd_cb->start) { - core_if->hcd_cb->start(core_if->hcd_cb->p); - } -} -/** Stop the HCD. Helper function for using the HCD callbacks. - * - * @param core_if Programming view of DWC_otg controller. - */ -static inline void hcd_stop(dwc_otg_core_if_t *core_if) -{ - if (core_if->hcd_cb && core_if->hcd_cb->stop) { - core_if->hcd_cb->stop(core_if->hcd_cb->p); - } -} -/** Disconnect the HCD. Helper function for using the HCD callbacks. - * - * @param core_if Programming view of DWC_otg controller. - */ -static inline void hcd_disconnect(dwc_otg_core_if_t *core_if) -{ - if (core_if->hcd_cb && core_if->hcd_cb->disconnect) { - core_if->hcd_cb->disconnect(core_if->hcd_cb->p); - } -} -/** Inform the HCD the a New Session has begun. Helper function for - * using the HCD callbacks. - * - * @param core_if Programming view of DWC_otg controller. - */ -static inline void hcd_session_start(dwc_otg_core_if_t *core_if) -{ - if (core_if->hcd_cb && core_if->hcd_cb->session_start) { - core_if->hcd_cb->session_start(core_if->hcd_cb->p); - } -} - -/** Start the PCD. Helper function for using the PCD callbacks. - * - * @param core_if Programming view of DWC_otg controller. - */ -static inline void pcd_start(dwc_otg_core_if_t *core_if) -{ - if (core_if->pcd_cb && core_if->pcd_cb->start) { - core_if->pcd_cb->start(core_if->pcd_cb->p); - } -} -/** Stop the PCD. Helper function for using the PCD callbacks. - * - * @param core_if Programming view of DWC_otg controller. - */ -static inline void pcd_stop(dwc_otg_core_if_t *core_if) -{ - if (core_if->pcd_cb && core_if->pcd_cb->stop) { - core_if->pcd_cb->stop(core_if->pcd_cb->p); - } -} -/** Suspend the PCD. Helper function for using the PCD callbacks. - * - * @param core_if Programming view of DWC_otg controller. - */ -static inline void pcd_suspend(dwc_otg_core_if_t *core_if) -{ - if (core_if->pcd_cb && core_if->pcd_cb->suspend) { - core_if->pcd_cb->suspend(core_if->pcd_cb->p); - } -} -/** Resume the PCD. Helper function for using the PCD callbacks. - * - * @param core_if Programming view of DWC_otg controller. - */ -static inline void pcd_resume(dwc_otg_core_if_t *core_if) -{ - if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) { - core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p); - } -} - -/** - * This function handles the OTG Interrupts. It reads the OTG - * Interrupt Register (GOTGINT) to determine what interrupt has - * occurred. - * - * @param core_if Programming view of DWC_otg controller. - */ -int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t *core_if) -{ - dwc_otg_core_global_regs_t *global_regs = - core_if->core_global_regs; - gotgint_data_t gotgint; - gotgctl_data_t gotgctl; - gintmsk_data_t gintmsk; - - gotgint.d32 = dwc_read_reg32(&global_regs->gotgint); - gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl); - DWC_DEBUGPL(DBG_CIL, "gotgctl=%08x\n", gotgctl.d32); - - if (gotgint.b.sesenddet) { - DWC_DEBUGPL(DBG_ANY, "OTG Interrupt: " - "Session End Detected++ (%s)\n", - op_state_str(core_if)); - gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl); - - if (core_if->op_state == B_HOST) { - pcd_start(core_if); - core_if->op_state = B_PERIPHERAL; - } else { - /* If not B_HOST and Device HNP still set. HNP - * Did not succeed!*/ - if (gotgctl.b.devhnpen) { - DWC_DEBUGPL(DBG_ANY, "Session End Detected\n"); - DWC_ERROR("Device Not Connected/Responding!\n"); - } - - /* If Session End Detected the B-Cable has - * been disconnected. */ - /* Reset PCD and Gadget driver to a - * clean state. */ - pcd_stop(core_if); - } - gotgctl.d32 = 0; - gotgctl.b.devhnpen = 1; - dwc_modify_reg32(&global_regs->gotgctl, - gotgctl.d32, 0); - } - if (gotgint.b.sesreqsucstschng) { - DWC_DEBUGPL(DBG_ANY, " OTG Interrupt: " - "Session Reqeust Success Status Change++\n"); - gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl); - if (gotgctl.b.sesreqscs) { - if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) && - (core_if->core_params->i2c_enable)) { - core_if->srp_success = 1; - } - else { - pcd_resume(core_if); - /* Clear Session Request */ - gotgctl.d32 = 0; - gotgctl.b.sesreq = 1; - dwc_modify_reg32(&global_regs->gotgctl, - gotgctl.d32, 0); - } - } - } - if (gotgint.b.hstnegsucstschng) { - /* Print statements during the HNP interrupt handling - * can cause it to fail.*/ - gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl); - if (gotgctl.b.hstnegscs) { - if (dwc_otg_is_host_mode(core_if)) { - core_if->op_state = B_HOST; - /* - * Need to disable SOF interrupt immediately. - * When switching from device to host, the PCD - * interrupt handler won't handle the - * interrupt if host mode is already set. The - * HCD interrupt handler won't get called if - * the HCD state is HALT. This means that the - * interrupt does not get handled and Linux - * complains loudly. - */ - gintmsk.d32 = 0; - gintmsk.b.sofintr = 1; - dwc_modify_reg32(&global_regs->gintmsk, - gintmsk.d32, 0); - pcd_stop(core_if); - /* - * Initialize the Core for Host mode. - */ - hcd_start(core_if); - core_if->op_state = B_HOST; - } - } else { - gotgctl.d32 = 0; - gotgctl.b.hnpreq = 1; - gotgctl.b.devhnpen = 1; - dwc_modify_reg32(&global_regs->gotgctl, - gotgctl.d32, 0); - DWC_DEBUGPL(DBG_ANY, "HNP Failed\n"); - DWC_ERROR("Device Not Connected/Responding\n"); - } - } - if (gotgint.b.hstnegdet) { - /* The disconnect interrupt is set at the same time as - * Host Negotiation Detected. During the mode - * switch all interrupts are cleared so the disconnect - * interrupt handler will not get executed. - */ - DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " - "Host Negotiation Detected++ (%s)\n", - (dwc_otg_is_host_mode(core_if)?"Host":"Device")); - if (dwc_otg_is_device_mode(core_if)){ - DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n", core_if->op_state); - hcd_disconnect(core_if); - pcd_start(core_if); - core_if->op_state = A_PERIPHERAL; - } else { - /* - * Need to disable SOF interrupt immediately. When - * switching from device to host, the PCD interrupt - * handler won't handle the interrupt if host mode is - * already set. The HCD interrupt handler won't get - * called if the HCD state is HALT. This means that - * the interrupt does not get handled and Linux - * complains loudly. - */ - gintmsk.d32 = 0; - gintmsk.b.sofintr = 1; - dwc_modify_reg32(&global_regs->gintmsk, - gintmsk.d32, 0); - pcd_stop(core_if); - hcd_start(core_if); - core_if->op_state = A_HOST; - } - } - if (gotgint.b.adevtoutchng) { - DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " - "A-Device Timeout Change++\n"); - } - if (gotgint.b.debdone) { - DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " - "Debounce Done++\n"); - } - - /* Clear GOTGINT */ - dwc_write_reg32 (&core_if->core_global_regs->gotgint, gotgint.d32); - - return 1; -} - - -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) - -void w_conn_id_status_change(void *p) -{ - dwc_otg_core_if_t *core_if = p; - -#else - -void w_conn_id_status_change(struct work_struct *p) -{ - dwc_otg_core_if_t *core_if = container_of(p, dwc_otg_core_if_t, w_conn_id); - -#endif - - - uint32_t count = 0; - gotgctl_data_t gotgctl = { .d32 = 0 }; - - gotgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl); - DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32); - DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts); - - /* B-Device connector (Device Mode) */ - if (gotgctl.b.conidsts) { - /* Wait for switch to device mode. */ - while (!dwc_otg_is_device_mode(core_if)){ - DWC_PRINT("Waiting for Peripheral Mode, Mode=%s\n", - (dwc_otg_is_host_mode(core_if)?"Host":"Peripheral")); - MDELAY(100); - if (++count > 10000) *(uint32_t*)NULL=0; - } - core_if->op_state = B_PERIPHERAL; - dwc_otg_core_init(core_if); - dwc_otg_enable_global_interrupts(core_if); - pcd_start(core_if); - } else { - /* A-Device connector (Host Mode) */ - while (!dwc_otg_is_host_mode(core_if)) { - DWC_PRINT("Waiting for Host Mode, Mode=%s\n", - (dwc_otg_is_host_mode(core_if)?"Host":"Peripheral")); - MDELAY(100); - if (++count > 10000) *(uint32_t*)NULL=0; - } - core_if->op_state = A_HOST; - /* - * Initialize the Core for Host mode. - */ - dwc_otg_core_init(core_if); - dwc_otg_enable_global_interrupts(core_if); - hcd_start(core_if); - } -} - - -/** - * This function handles the Connector ID Status Change Interrupt. It - * reads the OTG Interrupt Register (GOTCTL) to determine whether this - * is a Device to Host Mode transition or a Host Mode to Device - * Transition. - * - * This only occurs when the cable is connected/removed from the PHY - * connector. - * - * @param core_if Programming view of DWC_otg controller. - */ -int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t *core_if) -{ - - /* - * Need to disable SOF interrupt immediately. If switching from device - * to host, the PCD interrupt handler won't handle the interrupt if - * host mode is already set. The HCD interrupt handler won't get - * called if the HCD state is HALT. This means that the interrupt does - * not get handled and Linux complains loudly. - */ - gintmsk_data_t gintmsk = { .d32 = 0 }; - gintsts_data_t gintsts = { .d32 = 0 }; - - gintmsk.b.sofintr = 1; - dwc_modify_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0); - - DWC_DEBUGPL(DBG_CIL, " ++Connector ID Status Change Interrupt++ (%s)\n", - (dwc_otg_is_host_mode(core_if)?"Host":"Device")); - - /* - * Need to schedule a work, as there are possible DELAY function calls - */ - queue_work(core_if->wq_otg, &core_if->w_conn_id); - - /* Set flag and clear interrupt */ - gintsts.b.conidstschng = 1; - dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32); - - return 1; -} - -/** - * This interrupt indicates that a device is initiating the Session - * Request Protocol to request the host to turn on bus power so a new - * session can begin. The handler responds by turning on bus power. If - * the DWC_otg controller is in low power mode, the handler brings the - * controller out of low power mode before turning on bus power. - * - * @param core_if Programming view of DWC_otg controller. - */ -int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t *core_if) -{ - gintsts_data_t gintsts; - -#ifndef DWC_HOST_ONLY - hprt0_data_t hprt0; - DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n"); - - if (dwc_otg_is_device_mode(core_if)) { - DWC_PRINT("SRP: Device mode\n"); - } else { - DWC_PRINT("SRP: Host mode\n"); - - /* Turn on the port power bit. */ - hprt0.d32 = dwc_otg_read_hprt0(core_if); - hprt0.b.prtpwr = 1; - dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); - - /* Start the Connection timer. So a message can be displayed - * if connect does not occur within 10 seconds. */ - hcd_session_start(core_if); - } -#endif - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.sessreqintr = 1; - dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32); - - return 1; -} - - -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -void w_wakeup_detected(void *p) -{ - dwc_otg_core_if_t* core_if = p; - -#else - -void w_wakeup_detected(struct work_struct *p) -{ - struct delayed_work *dw = container_of(p, struct delayed_work, work); - dwc_otg_core_if_t *core_if = container_of(dw, dwc_otg_core_if_t, w_wkp); - -#endif - /* - * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms - * so that OPT tests pass with all PHYs). - */ - hprt0_data_t hprt0 = {.d32=0}; -#if 0 - pcgcctl_data_t pcgcctl = {.d32=0}; - /* Restart the Phy Clock */ - pcgcctl.b.stoppclk = 1; - dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, 0); - UDELAY(10); -#endif //0 - hprt0.d32 = dwc_otg_read_hprt0(core_if); - DWC_DEBUGPL(DBG_ANY,"Resume: HPRT0=%0x\n", hprt0.d32); -// MDELAY(70); - hprt0.b.prtres = 0; /* Resume */ - dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); - DWC_DEBUGPL(DBG_ANY,"Clear Resume: HPRT0=%0x\n", dwc_read_reg32(core_if->host_if->hprt0)); -} -/** - * This interrupt indicates that the DWC_otg controller has detected a - * resume or remote wakeup sequence. If the DWC_otg controller is in - * low power mode, the handler must brings the controller out of low - * power mode. The controller automatically begins resume - * signaling. The handler schedules a time to stop resume signaling. - */ -int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t *core_if) -{ - gintsts_data_t gintsts; - - DWC_DEBUGPL(DBG_ANY, "++Resume and Remote Wakeup Detected Interrupt++\n"); - - if (dwc_otg_is_device_mode(core_if)) { - dctl_data_t dctl = {.d32=0}; - DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", - dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts)); -#ifdef PARTIAL_POWER_DOWN - if (core_if->hwcfg4.b.power_optimiz) { - pcgcctl_data_t power = {.d32=0}; - - power.d32 = dwc_read_reg32(core_if->pcgcctl); - DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n", power.d32); - - power.b.stoppclk = 0; - dwc_write_reg32(core_if->pcgcctl, power.d32); - - power.b.pwrclmp = 0; - dwc_write_reg32(core_if->pcgcctl, power.d32); - - power.b.rstpdwnmodule = 0; - dwc_write_reg32(core_if->pcgcctl, power.d32); - } -#endif - /* Clear the Remote Wakeup Signalling */ - dctl.b.rmtwkupsig = 1; - dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl, - dctl.d32, 0); - - if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) { - core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p); - } - - } else { - pcgcctl_data_t pcgcctl = {.d32=0}; - - /* Restart the Phy Clock */ - pcgcctl.b.stoppclk = 1; - dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, 0); - - queue_delayed_work(core_if->wq_otg, &core_if->w_wkp, ((70 * HZ / 1000) + 1)); - } - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.wkupintr = 1; - dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32); - - return 1; -} - -/** - * This interrupt indicates that a device has been disconnected from - * the root port. - */ -int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t *core_if) -{ - gintsts_data_t gintsts; - - DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n", - (dwc_otg_is_host_mode(core_if)?"Host":"Device"), - op_state_str(core_if)); - -/** @todo Consolidate this if statement. */ -#ifndef DWC_HOST_ONLY - if (core_if->op_state == B_HOST) { - /* If in device mode Disconnect and stop the HCD, then - * start the PCD. */ - hcd_disconnect(core_if); - pcd_start(core_if); - core_if->op_state = B_PERIPHERAL; - } else if (dwc_otg_is_device_mode(core_if)) { - gotgctl_data_t gotgctl = { .d32 = 0 }; - gotgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl); - if (gotgctl.b.hstsethnpen==1) { - /* Do nothing, if HNP in process the OTG - * interrupt "Host Negotiation Detected" - * interrupt will do the mode switch. - */ - } else if (gotgctl.b.devhnpen == 0) { - /* If in device mode Disconnect and stop the HCD, then - * start the PCD. */ - hcd_disconnect(core_if); - pcd_start(core_if); - core_if->op_state = B_PERIPHERAL; - } else { - DWC_DEBUGPL(DBG_ANY,"!a_peripheral && !devhnpen\n"); - } - } else { - if (core_if->op_state == A_HOST) { - /* A-Cable still connected but device disconnected. */ - hcd_disconnect(core_if); - } - } -#endif - - gintsts.d32 = 0; - gintsts.b.disconnect = 1; - dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32); - return 1; -} -/** - * This interrupt indicates that SUSPEND state has been detected on - * the USB. - * - * For HNP the USB Suspend interrupt signals the change from - * "a_peripheral" to "a_host". - * - * When power management is enabled the core will be put in low power - * mode. - */ -int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t *core_if) -{ - dsts_data_t dsts; - gintsts_data_t gintsts; - - DWC_DEBUGPL(DBG_ANY,"USB SUSPEND\n"); - - if (dwc_otg_is_device_mode(core_if)) { - /* Check the Device status register to determine if the Suspend - * state is active. */ - dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); - DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32); - DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d " - "HWCFG4.power Optimize=%d\n", - dsts.b.suspsts, core_if->hwcfg4.b.power_optimiz); - - -#ifdef PARTIAL_POWER_DOWN -/** @todo Add a module parameter for power management. */ - - if (dsts.b.suspsts && core_if->hwcfg4.b.power_optimiz) { - pcgcctl_data_t power = {.d32=0}; - DWC_DEBUGPL(DBG_CIL, "suspend\n"); - - power.b.pwrclmp = 1; - dwc_write_reg32(core_if->pcgcctl, power.d32); - - power.b.rstpdwnmodule = 1; - dwc_modify_reg32(core_if->pcgcctl, 0, power.d32); - - power.b.stoppclk = 1; - dwc_modify_reg32(core_if->pcgcctl, 0, power.d32); - - } else { - DWC_DEBUGPL(DBG_ANY,"disconnect?\n"); - } -#endif - /* PCD callback for suspend. */ - pcd_suspend(core_if); - } else { - if (core_if->op_state == A_PERIPHERAL) { - DWC_DEBUGPL(DBG_ANY,"a_peripheral->a_host\n"); - /* Clear the a_peripheral flag, back to a_host. */ - pcd_stop(core_if); - hcd_start(core_if); - core_if->op_state = A_HOST; - } - } - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.usbsuspend = 1; - dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32); - - return 1; -} - - -/** - * This function returns the Core Interrupt register. - */ -static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t *core_if) -{ - gintsts_data_t gintsts; - gintmsk_data_t gintmsk; - gintmsk_data_t gintmsk_common = {.d32=0}; - gintmsk_common.b.wkupintr = 1; - gintmsk_common.b.sessreqintr = 1; - gintmsk_common.b.conidstschng = 1; - gintmsk_common.b.otgintr = 1; - gintmsk_common.b.modemismatch = 1; - gintmsk_common.b.disconnect = 1; - gintmsk_common.b.usbsuspend = 1; - /** @todo: The port interrupt occurs while in device - * mode. Added code to CIL to clear the interrupt for now! - */ - gintmsk_common.b.portintr = 1; - - gintsts.d32 = dwc_read_reg32(&core_if->core_global_regs->gintsts); - gintmsk.d32 = dwc_read_reg32(&core_if->core_global_regs->gintmsk); -#ifdef DEBUG - /* if any common interrupts set */ - if (gintsts.d32 & gintmsk_common.d32) { - DWC_DEBUGPL(DBG_ANY, "gintsts=%08x gintmsk=%08x\n", - gintsts.d32, gintmsk.d32); - } -#endif - - return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32); - -} - -/** - * Common interrupt handler. - * - * The common interrupts are those that occur in both Host and Device mode. - * This handler handles the following interrupts: - * - Mode Mismatch Interrupt - * - Disconnect Interrupt - * - OTG Interrupt - * - Connector ID Status Change Interrupt - * - Session Request Interrupt. - * - Resume / Remote Wakeup Detected Interrupt. - * - */ -int32_t dwc_otg_handle_common_intr(dwc_otg_core_if_t *core_if) -{ - int retval = 0; - gintsts_data_t gintsts; - - gintsts.d32 = dwc_otg_read_common_intr(core_if); - - if (gintsts.b.modemismatch) { - retval |= dwc_otg_handle_mode_mismatch_intr(core_if); - } - if (gintsts.b.otgintr) { - retval |= dwc_otg_handle_otg_intr(core_if); - } - if (gintsts.b.conidstschng) { - retval |= dwc_otg_handle_conn_id_status_change_intr(core_if); - } - if (gintsts.b.disconnect) { - retval |= dwc_otg_handle_disconnect_intr(core_if); - } - if (gintsts.b.sessreqintr) { - retval |= dwc_otg_handle_session_req_intr(core_if); - } - if (gintsts.b.wkupintr) { - retval |= dwc_otg_handle_wakeup_detected_intr(core_if); - } - if (gintsts.b.usbsuspend) { - retval |= dwc_otg_handle_usb_suspend_intr(core_if); - } - if (gintsts.b.portintr && dwc_otg_is_device_mode(core_if)) { - /* The port interrupt occurs while in device mode with HPRT0 - * Port Enable/Disable. - */ - gintsts.d32 = 0; - gintsts.b.portintr = 1; - dwc_write_reg32(&core_if->core_global_regs->gintsts, - gintsts.d32); - retval |= 1; - - } - - S3C2410X_CLEAR_EINTPEND(); - - return retval; -} diff --git a/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_driver.c b/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_driver.c deleted file mode 100644 index 87d3fbbbc2..0000000000 --- a/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_driver.c +++ /dev/null @@ -1,1265 +0,0 @@ -/* ========================================================================== - * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_driver.c $ - * $Revision: 1.7 $ - * $Date: 2008-11-21 05:39:15 $ - * $Change: 791271 $ - * - * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, - * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless - * otherwise expressly agreed to in writing between Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ - -/** @file - * The dwc_otg_driver module provides the initialization and cleanup entry - * points for the DWC_otg driver. This module will be dynamically installed - * after Linux is booted using the insmod command. When the module is - * installed, the dwc_otg_driver_init function is called. When the module is - * removed (using rmmod), the dwc_otg_driver_cleanup function is called. - * - * This module also defines a data structure for the dwc_otg_driver, which is - * used in conjunction with the standard ARM platform_device structure. These - * structures allow the OTG driver to comply with the standard Linux driver - * model in which devices and drivers are registered with a bus driver. This - * has the benefit that Linux can expose attributes of the driver and device - * in its special sysfs file system. Users can then read or write files in - * this file system to perform diagnostics on the driver components or the - * device. - */ - -#include -#include -#include -#include -#include -#include -#include -#include /* permission constants */ -#include -#include - -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -# include -#endif - -#include - -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -# include -#endif - -#include "linux/dwc_otg_plat.h" -#include "dwc_otg_attr.h" -#include "dwc_otg_driver.h" -#include "dwc_otg_cil.h" -#include "dwc_otg_pcd.h" -#include "dwc_otg_hcd.h" - -#define DWC_DRIVER_VERSION "2.72a 24-JUN-2008" -#define DWC_DRIVER_DESC "HS OTG USB Controller driver" - -static const char dwc_driver_name[] = "dwc_otg"; - -/*-------------------------------------------------------------------------*/ -/* Encapsulate the module parameter settings */ - -static dwc_otg_core_params_t dwc_otg_module_params = { - .opt = -1, - .otg_cap = -1, - .dma_enable = -1, - .dma_desc_enable = -1, - .dma_burst_size = -1, - .speed = -1, - .host_support_fs_ls_low_power = -1, - .host_ls_low_power_phy_clk = -1, - .enable_dynamic_fifo = -1, - .data_fifo_size = -1, - .dev_rx_fifo_size = -1, - .dev_nperio_tx_fifo_size = -1, - .dev_perio_tx_fifo_size = { - /* dev_perio_tx_fifo_size_1 */ - -1, - -1, - -1, - -1, - -1, - -1, - -1, - -1, - -1, - -1, - -1, - -1, - -1, - -1, - -1 - /* 15 */ - }, - .host_rx_fifo_size = -1, - .host_nperio_tx_fifo_size = -1, - .host_perio_tx_fifo_size = -1, - .max_transfer_size = -1, - .max_packet_count = -1, - .host_channels = -1, - .dev_endpoints = -1, - .phy_type = -1, - .phy_utmi_width = -1, - .phy_ulpi_ddr = -1, - .phy_ulpi_ext_vbus = -1, - .i2c_enable = -1, - .ulpi_fs_ls = -1, - .ts_dline = -1, - .en_multiple_tx_fifo = -1, - .dev_tx_fifo_size = { - /* dev_tx_fifo_size */ - -1, - -1, - -1, - -1, - -1, - -1, - -1, - -1, - -1, - -1, - -1, - -1, - -1, - -1, - -1 - /* 15 */ - }, - .thr_ctl = -1, - .tx_thr_length = -1, - .rx_thr_length = -1, - .pti_enable = -1, - .mpi_enable = -1, -}; - -/** - * This function shows the Driver Version. - */ -static ssize_t version_show(struct device_driver *dev, char *buf) -{ - return snprintf(buf, sizeof(DWC_DRIVER_VERSION)+2, "%s\n", - DWC_DRIVER_VERSION); -} -static DRIVER_ATTR(version, S_IRUGO, version_show, NULL); - -/** - * Global Debug Level Mask. - */ -uint32_t g_dbg_lvl = 0; /* OFF */ - -/** - * This function shows the driver Debug Level. - */ -static ssize_t dbg_level_show(struct device_driver *drv, char *buf) -{ - return sprintf(buf, "0x%0x\n", g_dbg_lvl); -} - -/** - * This function stores the driver Debug Level. - */ -static ssize_t dbg_level_store(struct device_driver *drv, const char *buf, - size_t count) -{ - g_dbg_lvl = simple_strtoul(buf, NULL, 16); - return count; -} -static DRIVER_ATTR(debuglevel, S_IRUGO|S_IWUSR, dbg_level_show, dbg_level_store); - -/** - * This function is called during module intialization to verify that - * the module parameters are in a valid state. - */ -static int check_parameters(dwc_otg_core_if_t *core_if) -{ - int i; - int retval = 0; - -/* Checks if the parameter is outside of its valid range of values */ -#define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \ - ((dwc_otg_module_params._param_ < (_low_)) || \ - (dwc_otg_module_params._param_ > (_high_))) - -/* If the parameter has been set by the user, check that the parameter value is - * within the value range of values. If not, report a module error. */ -#define DWC_OTG_PARAM_ERR(_param_, _low_, _high_, _string_) \ - do { \ - if (dwc_otg_module_params._param_ != -1) { \ - if (DWC_OTG_PARAM_TEST(_param_, (_low_), (_high_))) { \ - DWC_ERROR("`%d' invalid for parameter `%s'\n", \ - dwc_otg_module_params._param_, _string_); \ - dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \ - retval++; \ - } \ - } \ - } while (0) - - DWC_OTG_PARAM_ERR(opt,0,1,"opt"); - DWC_OTG_PARAM_ERR(otg_cap,0,2,"otg_cap"); - DWC_OTG_PARAM_ERR(dma_enable,0,1,"dma_enable"); - DWC_OTG_PARAM_ERR(dma_desc_enable,0,1,"dma_desc_enable"); - DWC_OTG_PARAM_ERR(speed,0,1,"speed"); - DWC_OTG_PARAM_ERR(host_support_fs_ls_low_power,0,1,"host_support_fs_ls_low_power"); - DWC_OTG_PARAM_ERR(host_ls_low_power_phy_clk,0,1,"host_ls_low_power_phy_clk"); - DWC_OTG_PARAM_ERR(enable_dynamic_fifo,0,1,"enable_dynamic_fifo"); - DWC_OTG_PARAM_ERR(data_fifo_size,32,32768,"data_fifo_size"); - DWC_OTG_PARAM_ERR(dev_rx_fifo_size,16,32768,"dev_rx_fifo_size"); - DWC_OTG_PARAM_ERR(dev_nperio_tx_fifo_size,16,32768,"dev_nperio_tx_fifo_size"); - DWC_OTG_PARAM_ERR(host_rx_fifo_size,16,32768,"host_rx_fifo_size"); - DWC_OTG_PARAM_ERR(host_nperio_tx_fifo_size,16,32768,"host_nperio_tx_fifo_size"); - DWC_OTG_PARAM_ERR(host_perio_tx_fifo_size,16,32768,"host_perio_tx_fifo_size"); - DWC_OTG_PARAM_ERR(max_transfer_size,2047,524288,"max_transfer_size"); - DWC_OTG_PARAM_ERR(max_packet_count,15,511,"max_packet_count"); - DWC_OTG_PARAM_ERR(host_channels,1,16,"host_channels"); - DWC_OTG_PARAM_ERR(dev_endpoints,1,15,"dev_endpoints"); - DWC_OTG_PARAM_ERR(phy_type,0,2,"phy_type"); - DWC_OTG_PARAM_ERR(phy_ulpi_ddr,0,1,"phy_ulpi_ddr"); - DWC_OTG_PARAM_ERR(phy_ulpi_ext_vbus,0,1,"phy_ulpi_ext_vbus"); - DWC_OTG_PARAM_ERR(i2c_enable,0,1,"i2c_enable"); - DWC_OTG_PARAM_ERR(ulpi_fs_ls,0,1,"ulpi_fs_ls"); - DWC_OTG_PARAM_ERR(ts_dline,0,1,"ts_dline"); - - if (dwc_otg_module_params.dma_burst_size != -1) { - if (DWC_OTG_PARAM_TEST(dma_burst_size,1,1) && - DWC_OTG_PARAM_TEST(dma_burst_size,4,4) && - DWC_OTG_PARAM_TEST(dma_burst_size,8,8) && - DWC_OTG_PARAM_TEST(dma_burst_size,16,16) && - DWC_OTG_PARAM_TEST(dma_burst_size,32,32) && - DWC_OTG_PARAM_TEST(dma_burst_size,64,64) && - DWC_OTG_PARAM_TEST(dma_burst_size,128,128) && - DWC_OTG_PARAM_TEST(dma_burst_size,256,256)) { - DWC_ERROR("`%d' invalid for parameter `dma_burst_size'\n", - dwc_otg_module_params.dma_burst_size); - dwc_otg_module_params.dma_burst_size = 32; - retval++; - } - - { - uint8_t brst_sz = 0; - while(dwc_otg_module_params.dma_burst_size > 1) { - brst_sz ++; - dwc_otg_module_params.dma_burst_size >>= 1; - } - dwc_otg_module_params.dma_burst_size = brst_sz; - } - } - - if (dwc_otg_module_params.phy_utmi_width != -1) { - if (DWC_OTG_PARAM_TEST(phy_utmi_width, 8, 8) && - DWC_OTG_PARAM_TEST(phy_utmi_width, 16, 16)) { - DWC_ERROR("`%d' invalid for parameter `phy_utmi_width'\n", - dwc_otg_module_params.phy_utmi_width); - dwc_otg_module_params.phy_utmi_width = 16; - retval++; - } - } - - for (i = 0; i < 15; i++) { - /** @todo should be like above */ - //DWC_OTG_PARAM_ERR(dev_perio_tx_fifo_size[i], 4, 768, "dev_perio_tx_fifo_size"); - if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) { - if (DWC_OTG_PARAM_TEST(dev_perio_tx_fifo_size[i], 4, 768)) { - DWC_ERROR("`%d' invalid for parameter `%s_%d'\n", - dwc_otg_module_params.dev_perio_tx_fifo_size[i], "dev_perio_tx_fifo_size", i); - dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default; - retval++; - } - } - } - - DWC_OTG_PARAM_ERR(en_multiple_tx_fifo, 0, 1, "en_multiple_tx_fifo"); - - for (i = 0; i < 15; i++) { - /** @todo should be like above */ - //DWC_OTG_PARAM_ERR(dev_tx_fifo_size[i], 4, 768, "dev_tx_fifo_size"); - if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) { - if (DWC_OTG_PARAM_TEST(dev_tx_fifo_size[i], 4, 768)) { - DWC_ERROR("`%d' invalid for parameter `%s_%d'\n", - dwc_otg_module_params.dev_tx_fifo_size[i], "dev_tx_fifo_size", i); - dwc_otg_module_params.dev_tx_fifo_size[i] = dwc_param_dev_tx_fifo_size_default; - retval++; - } - } - } - - DWC_OTG_PARAM_ERR(thr_ctl, 0, 7, "thr_ctl"); - DWC_OTG_PARAM_ERR(tx_thr_length, 8, 128, "tx_thr_length"); - DWC_OTG_PARAM_ERR(rx_thr_length, 8, 128, "rx_thr_length"); - - DWC_OTG_PARAM_ERR(pti_enable,0,1,"pti_enable"); - DWC_OTG_PARAM_ERR(mpi_enable,0,1,"mpi_enable"); - - /* At this point, all module parameters that have been set by the user - * are valid, and those that have not are left unset. Now set their - * default values and/or check the parameters against the hardware - * configurations of the OTG core. */ - -/* This sets the parameter to the default value if it has not been set by the - * user */ -#define DWC_OTG_PARAM_SET_DEFAULT(_param_) \ - ({ \ - int changed = 1; \ - if (dwc_otg_module_params._param_ == -1) { \ - changed = 0; \ - dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \ - } \ - changed; \ - }) - -/* This checks the macro agains the hardware configuration to see if it is - * valid. It is possible that the default value could be invalid. In this - * case, it will report a module error if the user touched the parameter. - * Otherwise it will adjust the value without any error. */ -#define DWC_OTG_PARAM_CHECK_VALID(_param_, _str_, _is_valid_, _set_valid_) \ - ({ \ - int changed = DWC_OTG_PARAM_SET_DEFAULT(_param_); \ - int error = 0; \ - if (!(_is_valid_)) { \ - if (changed) { \ - DWC_ERROR("`%d' invalid for parameter `%s'. Check HW configuration.\n", dwc_otg_module_params._param_, _str_); \ - error = 1; \ - } \ - dwc_otg_module_params._param_ = (_set_valid_); \ - } \ - error; \ - }) - - /* OTG Cap */ - retval += DWC_OTG_PARAM_CHECK_VALID(otg_cap, "otg_cap", - ({ - int valid; - valid = 1; - switch (dwc_otg_module_params.otg_cap) { - case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE: - if (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) - valid = 0; - break; - case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE: - if ((core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) && - (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) && - (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) && - (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) { - valid = 0; - } - break; - case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE: - /* always valid */ - break; - } - valid; - }), - (((core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) || - (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) || - (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) || - (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ? - DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE : - DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE)); - - retval += DWC_OTG_PARAM_CHECK_VALID(dma_enable, "dma_enable", - ((dwc_otg_module_params.dma_enable == 1) && (core_if->hwcfg2.b.architecture == 0)) ? 0 : 1, - 0); - - retval += DWC_OTG_PARAM_CHECK_VALID(dma_desc_enable, "dma_desc_enable", - ((dwc_otg_module_params.dma_desc_enable == 1) && - ((dwc_otg_module_params.dma_enable == 0) || (core_if->hwcfg4.b.desc_dma == 0))) ? 0 : 1, - 0); - - retval += DWC_OTG_PARAM_CHECK_VALID(opt, "opt", 1, 0); - - DWC_OTG_PARAM_SET_DEFAULT(dma_burst_size); - - retval += DWC_OTG_PARAM_CHECK_VALID(host_support_fs_ls_low_power, - "host_support_fs_ls_low_power", - 1, 0); - - retval += DWC_OTG_PARAM_CHECK_VALID(enable_dynamic_fifo, - "enable_dynamic_fifo", - ((dwc_otg_module_params.enable_dynamic_fifo == 0) || - (core_if->hwcfg2.b.dynamic_fifo == 1)), 0); - - retval += DWC_OTG_PARAM_CHECK_VALID(data_fifo_size, - "data_fifo_size", - (dwc_otg_module_params.data_fifo_size <= core_if->hwcfg3.b.dfifo_depth), - core_if->hwcfg3.b.dfifo_depth); - - retval += DWC_OTG_PARAM_CHECK_VALID(dev_rx_fifo_size, - "dev_rx_fifo_size", - (dwc_otg_module_params.dev_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)), - dwc_read_reg32(&core_if->core_global_regs->grxfsiz)); - - retval += DWC_OTG_PARAM_CHECK_VALID(dev_nperio_tx_fifo_size, - "dev_nperio_tx_fifo_size", - (dwc_otg_module_params.dev_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)), - (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)); - - retval += DWC_OTG_PARAM_CHECK_VALID(host_rx_fifo_size, - "host_rx_fifo_size", - (dwc_otg_module_params.host_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)), - dwc_read_reg32(&core_if->core_global_regs->grxfsiz)); - - retval += DWC_OTG_PARAM_CHECK_VALID(host_nperio_tx_fifo_size, - "host_nperio_tx_fifo_size", - (dwc_otg_module_params.host_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)), - (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)); - - retval += DWC_OTG_PARAM_CHECK_VALID(host_perio_tx_fifo_size, - "host_perio_tx_fifo_size", - (dwc_otg_module_params.host_perio_tx_fifo_size <= ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16))), - ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16))); - - retval += DWC_OTG_PARAM_CHECK_VALID(max_transfer_size, - "max_transfer_size", - (dwc_otg_module_params.max_transfer_size < (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))), - ((1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1)); - - retval += DWC_OTG_PARAM_CHECK_VALID(max_packet_count, - "max_packet_count", - (dwc_otg_module_params.max_packet_count < (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))), - ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1)); - - retval += DWC_OTG_PARAM_CHECK_VALID(host_channels, - "host_channels", - (dwc_otg_module_params.host_channels <= (core_if->hwcfg2.b.num_host_chan + 1)), - (core_if->hwcfg2.b.num_host_chan + 1)); - - retval += DWC_OTG_PARAM_CHECK_VALID(dev_endpoints, - "dev_endpoints", - (dwc_otg_module_params.dev_endpoints <= (core_if->hwcfg2.b.num_dev_ep)), - core_if->hwcfg2.b.num_dev_ep); - -/* - * Define the following to disable the FS PHY Hardware checking. This is for - * internal testing only. - * - * #define NO_FS_PHY_HW_CHECKS - */ - -#ifdef NO_FS_PHY_HW_CHECKS - retval += DWC_OTG_PARAM_CHECK_VALID(phy_type, - "phy_type", 1, 0); -#else - retval += DWC_OTG_PARAM_CHECK_VALID(phy_type, - "phy_type", - ({ - int valid = 0; - if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_UTMI) && - ((core_if->hwcfg2.b.hs_phy_type == 1) || - (core_if->hwcfg2.b.hs_phy_type == 3))) { - valid = 1; - } - else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_ULPI) && - ((core_if->hwcfg2.b.hs_phy_type == 2) || - (core_if->hwcfg2.b.hs_phy_type == 3))) { - valid = 1; - } - else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) && - (core_if->hwcfg2.b.fs_phy_type == 1)) { - valid = 1; - } - valid; - }), - ({ - int set = DWC_PHY_TYPE_PARAM_FS; - if (core_if->hwcfg2.b.hs_phy_type) { - if ((core_if->hwcfg2.b.hs_phy_type == 3) || - (core_if->hwcfg2.b.hs_phy_type == 1)) { - set = DWC_PHY_TYPE_PARAM_UTMI; - } - else { - set = DWC_PHY_TYPE_PARAM_ULPI; - } - } - set; - })); -#endif - - retval += DWC_OTG_PARAM_CHECK_VALID(speed, "speed", - (dwc_otg_module_params.speed == 0) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1, - dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS ? 1 : 0); - - retval += DWC_OTG_PARAM_CHECK_VALID(host_ls_low_power_phy_clk, - "host_ls_low_power_phy_clk", - ((dwc_otg_module_params.host_ls_low_power_phy_clk == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1), - ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ : DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ)); - - DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ddr); - DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ext_vbus); - DWC_OTG_PARAM_SET_DEFAULT(phy_utmi_width); - DWC_OTG_PARAM_SET_DEFAULT(ulpi_fs_ls); - DWC_OTG_PARAM_SET_DEFAULT(ts_dline); - -#ifdef NO_FS_PHY_HW_CHECKS - retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable, "i2c_enable", 1, 0); -#else - retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable, - "i2c_enable", - (dwc_otg_module_params.i2c_enable == 1) && (core_if->hwcfg3.b.i2c == 0) ? 0 : 1, - 0); -#endif - - for (i = 0; i < 15; i++) { - int changed = 1; - int error = 0; - - if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] == -1) { - changed = 0; - dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default; - } - if (!(dwc_otg_module_params.dev_perio_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) { - if (changed) { - DWC_ERROR("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", dwc_otg_module_params.dev_perio_tx_fifo_size[i], i); - error = 1; - } - dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]); - } - retval += error; - } - - retval += DWC_OTG_PARAM_CHECK_VALID(en_multiple_tx_fifo, "en_multiple_tx_fifo", - ((dwc_otg_module_params.en_multiple_tx_fifo == 1) && (core_if->hwcfg4.b.ded_fifo_en == 0)) ? 0 : 1, - 0); - - for (i = 0; i < 15; i++) { - int changed = 1; - int error = 0; - - if (dwc_otg_module_params.dev_tx_fifo_size[i] == -1) { - changed = 0; - dwc_otg_module_params.dev_tx_fifo_size[i] = dwc_param_dev_tx_fifo_size_default; - } - if (!(dwc_otg_module_params.dev_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) { - if (changed) { - DWC_ERROR("%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", dwc_otg_module_params.dev_tx_fifo_size[i], i); - error = 1; - } - dwc_otg_module_params.dev_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]); - } - retval += error; - } - - retval += DWC_OTG_PARAM_CHECK_VALID(thr_ctl, "thr_ctl", - ((dwc_otg_module_params.thr_ctl != 0) && ((dwc_otg_module_params.dma_enable == 0) || (core_if->hwcfg4.b.ded_fifo_en == 0))) ? 0 : 1, - 0); - - DWC_OTG_PARAM_SET_DEFAULT(tx_thr_length); - DWC_OTG_PARAM_SET_DEFAULT(rx_thr_length); - - retval += DWC_OTG_PARAM_CHECK_VALID(pti_enable, "pti_enable", - ((dwc_otg_module_params.pti_enable == 0) || ((dwc_otg_module_params.pti_enable == 1) && (core_if->snpsid >= 0x4F54272A))) ? 1 : 0, - 0); - - retval += DWC_OTG_PARAM_CHECK_VALID(mpi_enable, "mpi_enable", - ((dwc_otg_module_params.mpi_enable == 0) || ((dwc_otg_module_params.mpi_enable == 1) && (core_if->hwcfg2.b.multi_proc_int == 1))) ? 1 : 0, - 0); - return retval; -} - -/** - * This function is the top level interrupt handler for the Common - * (Device and host modes) interrupts. - */ -static irqreturn_t dwc_otg_common_irq(int irq, void *dev -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) - , struct pt_regs *r -#endif - ) -{ - dwc_otg_device_t *otg_dev = dev; - int32_t retval = IRQ_NONE; - - retval = dwc_otg_handle_common_intr(otg_dev->core_if); - return IRQ_RETVAL(retval); -} - -/** - * This function is called when a platform_device is unregistered with the - * dwc_otg_driver. This happens, for example, when the rmmod command is - * executed. The device may or may not be electrically present. If it is - * present, the driver stops device processing. Any resources used on behalf - * of this device are freed. - * - * @param[in] pdev - */ -static int dwc_otg_driver_remove(struct platform_device *pdev) -{ - dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); - DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, pdev); - - if (!otg_dev) { - /* Memory allocation for the dwc_otg_device failed. */ - DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__); - return 0; - } - - /* - * Free the IRQ - */ - if (otg_dev->common_irq_installed) { - free_irq(otg_dev->irq, otg_dev); - } - -#ifndef DWC_DEVICE_ONLY - if (otg_dev->hcd) { - dwc_otg_hcd_remove(&pdev->dev); - } else { - DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__); - return 0; - } -#endif - -#ifndef DWC_HOST_ONLY - if (otg_dev->pcd) { - dwc_otg_pcd_remove(&pdev->dev); - } -#endif - if (otg_dev->core_if) { - dwc_otg_cil_remove(otg_dev->core_if); - } - - /* - * Remove the device attributes - */ - dwc_otg_attr_remove(otg_dev->parent); - - /* Disable USB port */ - dwc_write_reg32((uint32_t *)((uint8_t *)otg_dev->base + 0xe00), 0xf); - - /* - * Return the memory. - */ - if (otg_dev->base) { - iounmap(otg_dev->base); - } - - if (otg_dev->phys_addr != 0) { - release_mem_region(otg_dev->phys_addr, otg_dev->base_len); - } - - kfree(otg_dev); - - /* - * Clear the drvdata pointer. - */ - platform_set_drvdata(pdev, NULL); - - return 0; -} - -/** - * This function is called when an platform_device is bound to a - * dwc_otg_driver. It creates the driver components required to - * control the device (CIL, HCD, and PCD) and it initializes the - * device. The driver components are stored in a dwc_otg_device - * structure. A reference to the dwc_otg_device is saved in the - * platform_device. This allows the driver to access the dwc_otg_device - * structure on subsequent calls to driver methods for this device. - * - * @param[in] pdev platform_device definition - */ -static int dwc_otg_driver_probe(struct platform_device *pdev) -{ - int retval = 0; - uint32_t snpsid; - dwc_otg_device_t *otg_dev; - struct resource *res; - - dev_dbg(&pdev->dev, "dwc_otg_driver_probe(%p)\n", pdev); - - otg_dev= kzalloc(sizeof(dwc_otg_device_t), GFP_KERNEL); - if (!otg_dev) { - dev_err(&pdev->dev, "kmalloc of dwc_otg_device failed\n"); - retval = -ENOMEM; - goto fail; - } - - otg_dev->reg_offset = 0xFFFFFFFF; - - /* - * Retrieve the memory and IRQ resources. - */ - otg_dev->irq = platform_get_irq(pdev, 0); - if (otg_dev->irq <= 0) { - dev_err(&pdev->dev, "no device irq\n"); - retval = -EINVAL; - goto fail; - } - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (res == NULL) { - dev_err(&pdev->dev, "no CSR address\n"); - retval = -EINVAL; - goto fail; - } - - otg_dev->parent = &pdev->dev; - otg_dev->phys_addr = res->start; - otg_dev->base_len = res->end - res->start + 1; - if (request_mem_region(otg_dev->phys_addr, - otg_dev->base_len, - dwc_driver_name) == NULL) { - dev_err(&pdev->dev, "request_mem_region failed\n"); - retval = -EBUSY; - goto fail; - } - - /* - * Map the DWC_otg Core memory into virtual address space. - */ - otg_dev->base = ioremap(otg_dev->phys_addr, otg_dev->base_len); - if (!otg_dev->base) { - dev_err(&pdev->dev, "ioremap() failed\n"); - retval = -ENOMEM; - goto fail; - } - dev_dbg(&pdev->dev, "mapped base=0x%08x\n", (unsigned) otg_dev->base); - - /* Enable USB Port */ - dwc_write_reg32((uint32_t *)((uint8_t *)otg_dev->base + 0xe00), 0); - - /* - * Attempt to ensure this device is really a DWC_otg Controller. - * Read and verify the SNPSID register contents. The value should be - * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX". - */ - snpsid = dwc_read_reg32((uint32_t *)((uint8_t *)otg_dev->base + 0x40)); - - if ((snpsid & 0xFFFFF000) != OTG_CORE_REV_2_00) { - dev_err(&pdev->dev, "Bad value for SNPSID: 0x%08x\n", snpsid); - retval = -EINVAL; - goto fail; - } - - DWC_PRINT("Core Release: %x.%x%x%x\n", - (snpsid >> 12 & 0xF), - (snpsid >> 8 & 0xF), - (snpsid >> 4 & 0xF), - (snpsid & 0xF)); - - /* - * Initialize driver data to point to the global DWC_otg - * Device structure. - */ - platform_set_drvdata(pdev, otg_dev); - dev_dbg(&pdev->dev, "dwc_otg_device=0x%p\n", otg_dev); - - - otg_dev->core_if = dwc_otg_cil_init(otg_dev->base, - &dwc_otg_module_params); - - otg_dev->core_if->snpsid = snpsid; - - if (!otg_dev->core_if) { - dev_err(&pdev->dev, "CIL initialization failed!\n"); - retval = -ENOMEM; - goto fail; - } - - /* - * Validate parameter values. - */ - if (check_parameters(otg_dev->core_if)) { - retval = -EINVAL; - goto fail; - } - - /* - * Create Device Attributes in sysfs - */ - dwc_otg_attr_create(&pdev->dev); - - /* - * Disable the global interrupt until all the interrupt - * handlers are installed. - */ - dwc_otg_disable_global_interrupts(otg_dev->core_if); - - /* - * Install the interrupt handler for the common interrupts before - * enabling common interrupts in core_init below. - */ - DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", - otg_dev->irq); - retval = request_irq(otg_dev->irq, dwc_otg_common_irq, - IRQF_SHARED, "dwc_otg", otg_dev); - if (retval) { - DWC_ERROR("request of irq%d failed\n", otg_dev->irq); - retval = -EBUSY; - goto fail; - } else { - otg_dev->common_irq_installed = 1; - } - - /* - * Initialize the DWC_otg core. - */ - dwc_otg_core_init(otg_dev->core_if); - -#ifndef DWC_HOST_ONLY - /* - * Initialize the PCD - */ - retval = dwc_otg_pcd_init(&pdev->dev); - if (retval != 0) { - DWC_ERROR("dwc_otg_pcd_init failed\n"); - otg_dev->pcd = NULL; - goto fail; - } -#endif -#ifndef DWC_DEVICE_ONLY - /* - * Initialize the HCD - */ - retval = dwc_otg_hcd_init(&pdev->dev); - if (retval != 0) { - DWC_ERROR("dwc_otg_hcd_init failed\n"); - otg_dev->hcd = NULL; - goto fail; - } -#endif - - /* - * Enable the global interrupt after all the interrupt - * handlers are installed. - */ - dwc_otg_enable_global_interrupts(otg_dev->core_if); - - return 0; - - fail: - dwc_otg_driver_remove(pdev); - return retval; -} - -/** - * This structure defines the methods to be called by a bus driver - * during the lifecycle of a device on that bus. Both drivers and - * devices are registered with a bus driver. The bus driver matches - * devices to drivers based on information in the device and driver - * structures. - * - * The probe function is called when the bus driver matches a device - * to this driver. The remove function is called when a device is - * unregistered with the bus driver. - */ -static struct platform_driver dwc_otg_driver = { - .driver = { - .name = (char *)dwc_driver_name, - }, - .probe = dwc_otg_driver_probe, - .remove = dwc_otg_driver_remove, -}; - -/** - * This function is called when the dwc_otg_driver is installed with the - * insmod command. It registers the dwc_otg_driver structure with the - * appropriate bus driver. This will cause the dwc_otg_driver_probe function - * to be called. In addition, the bus driver will automatically expose - * attributes defined for the device and driver in the special sysfs file - * system. - * - * @return - */ -static int __init dwc_otg_driver_init(void) -{ - int retval = 0; - int error; - - printk(KERN_INFO "%s: version %s\n", dwc_driver_name, DWC_DRIVER_VERSION); - - retval = platform_driver_register(&dwc_otg_driver); - if (retval) { - printk(KERN_ERR "%s retval=%d\n", __func__, retval); - return retval; - } - - error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_version); - error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel); - - return retval; -} -module_init(dwc_otg_driver_init); - -/** - * This function is called when the driver is removed from the kernel - * with the rmmod command. The driver unregisters itself with its bus - * driver. - * - */ -static void __exit dwc_otg_driver_cleanup(void) -{ - printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n"); - - driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel); - driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version); - - platform_driver_unregister(&dwc_otg_driver); - - printk(KERN_INFO "%s module removed\n", dwc_driver_name); -} -module_exit(dwc_otg_driver_cleanup); - -MODULE_DESCRIPTION(DWC_DRIVER_DESC); -MODULE_AUTHOR("Synopsys Inc."); -MODULE_LICENSE("GPL"); - -module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444); -MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None"); -module_param_named(opt, dwc_otg_module_params.opt, int, 0444); -MODULE_PARM_DESC(opt, "OPT Mode"); -module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444); -MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled"); - -module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int, 0444); -MODULE_PARM_DESC(dma_desc_enable, "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled"); - -module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int, 0444); -MODULE_PARM_DESC(dma_burst_size, "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256"); -module_param_named(speed, dwc_otg_module_params.speed, int, 0444); -MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed"); -module_param_named(host_support_fs_ls_low_power, dwc_otg_module_params.host_support_fs_ls_low_power, int, 0444); -MODULE_PARM_DESC(host_support_fs_ls_low_power, "Support Low Power w/FS or LS 0=Support 1=Don't Support"); -module_param_named(host_ls_low_power_phy_clk, dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444); -MODULE_PARM_DESC(host_ls_low_power_phy_clk, "Low Speed Low Power Clock 0=48Mhz 1=6Mhz"); -module_param_named(enable_dynamic_fifo, dwc_otg_module_params.enable_dynamic_fifo, int, 0444); -MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing"); -module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int, 0444); -MODULE_PARM_DESC(data_fifo_size, "Total number of words in the data FIFO memory 32-32768"); -module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size, int, 0444); -MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768"); -module_param_named(dev_nperio_tx_fifo_size, dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444); -MODULE_PARM_DESC(dev_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768"); -module_param_named(dev_perio_tx_fifo_size_1, dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444); -MODULE_PARM_DESC(dev_perio_tx_fifo_size_1, "Number of words in the periodic Tx FIFO 4-768"); -module_param_named(dev_perio_tx_fifo_size_2, dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444); -MODULE_PARM_DESC(dev_perio_tx_fifo_size_2, "Number of words in the periodic Tx FIFO 4-768"); -module_param_named(dev_perio_tx_fifo_size_3, dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444); -MODULE_PARM_DESC(dev_perio_tx_fifo_size_3, "Number of words in the periodic Tx FIFO 4-768"); -module_param_named(dev_perio_tx_fifo_size_4, dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444); -MODULE_PARM_DESC(dev_perio_tx_fifo_size_4, "Number of words in the periodic Tx FIFO 4-768"); -module_param_named(dev_perio_tx_fifo_size_5, dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444); -MODULE_PARM_DESC(dev_perio_tx_fifo_size_5, "Number of words in the periodic Tx FIFO 4-768"); -module_param_named(dev_perio_tx_fifo_size_6, dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444); -MODULE_PARM_DESC(dev_perio_tx_fifo_size_6, "Number of words in the periodic Tx FIFO 4-768"); -module_param_named(dev_perio_tx_fifo_size_7, dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444); -MODULE_PARM_DESC(dev_perio_tx_fifo_size_7, "Number of words in the periodic Tx FIFO 4-768"); -module_param_named(dev_perio_tx_fifo_size_8, dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444); -MODULE_PARM_DESC(dev_perio_tx_fifo_size_8, "Number of words in the periodic Tx FIFO 4-768"); -module_param_named(dev_perio_tx_fifo_size_9, dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444); -MODULE_PARM_DESC(dev_perio_tx_fifo_size_9, "Number of words in the periodic Tx FIFO 4-768"); -module_param_named(dev_perio_tx_fifo_size_10, dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444); -MODULE_PARM_DESC(dev_perio_tx_fifo_size_10, "Number of words in the periodic Tx FIFO 4-768"); -module_param_named(dev_perio_tx_fifo_size_11, dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444); -MODULE_PARM_DESC(dev_perio_tx_fifo_size_11, "Number of words in the periodic Tx FIFO 4-768"); -module_param_named(dev_perio_tx_fifo_size_12, dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444); -MODULE_PARM_DESC(dev_perio_tx_fifo_size_12, "Number of words in the periodic Tx FIFO 4-768"); -module_param_named(dev_perio_tx_fifo_size_13, dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444); -MODULE_PARM_DESC(dev_perio_tx_fifo_size_13, "Number of words in the periodic Tx FIFO 4-768"); -module_param_named(dev_perio_tx_fifo_size_14, dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444); -MODULE_PARM_DESC(dev_perio_tx_fifo_size_14, "Number of words in the periodic Tx FIFO 4-768"); -module_param_named(dev_perio_tx_fifo_size_15, dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444); -MODULE_PARM_DESC(dev_perio_tx_fifo_size_15, "Number of words in the periodic Tx FIFO 4-768"); -module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size, int, 0444); -MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768"); -module_param_named(host_nperio_tx_fifo_size, dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444); -MODULE_PARM_DESC(host_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768"); -module_param_named(host_perio_tx_fifo_size, dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444); -MODULE_PARM_DESC(host_perio_tx_fifo_size, "Number of words in the host periodic Tx FIFO 16-32768"); -module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size, int, 0444); -/** @todo Set the max to 512K, modify checks */ -MODULE_PARM_DESC(max_transfer_size, "The maximum transfer size supported in bytes 2047-65535"); -module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count, int, 0444); -MODULE_PARM_DESC(max_packet_count, "The maximum number of packets in a transfer 15-511"); -module_param_named(host_channels, dwc_otg_module_params.host_channels, int, 0444); -MODULE_PARM_DESC(host_channels, "The number of host channel registers to use 1-16"); -module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int, 0444); -MODULE_PARM_DESC(dev_endpoints, "The number of endpoints in addition to EP0 available for device mode 1-15"); -module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444); -MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI"); -module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int, 0444); -MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits"); -module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444); -MODULE_PARM_DESC(phy_ulpi_ddr, "ULPI at double or single data rate 0=Single 1=Double"); -module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus, int, 0444); -MODULE_PARM_DESC(phy_ulpi_ext_vbus, "ULPI PHY using internal or external vbus 0=Internal"); -module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444); -MODULE_PARM_DESC(i2c_enable, "FS PHY Interface"); -module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444); -MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only"); -module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444); -MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs"); -module_param_named(debug, g_dbg_lvl, int, 0444); -MODULE_PARM_DESC(debug, ""); - -module_param_named(en_multiple_tx_fifo, dwc_otg_module_params.en_multiple_tx_fifo, int, 0444); -MODULE_PARM_DESC(en_multiple_tx_fifo, "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled"); -module_param_named(dev_tx_fifo_size_1, dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444); -MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768"); -module_param_named(dev_tx_fifo_size_2, dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444); -MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768"); -module_param_named(dev_tx_fifo_size_3, dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444); -MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768"); -module_param_named(dev_tx_fifo_size_4, dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444); -MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768"); -module_param_named(dev_tx_fifo_size_5, dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444); -MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768"); -module_param_named(dev_tx_fifo_size_6, dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444); -MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768"); -module_param_named(dev_tx_fifo_size_7, dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444); -MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768"); -module_param_named(dev_tx_fifo_size_8, dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444); -MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768"); -module_param_named(dev_tx_fifo_size_9, dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444); -MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768"); -module_param_named(dev_tx_fifo_size_10, dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444); -MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768"); -module_param_named(dev_tx_fifo_size_11, dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444); -MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768"); -module_param_named(dev_tx_fifo_size_12, dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444); -MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768"); -module_param_named(dev_tx_fifo_size_13, dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444); -MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768"); -module_param_named(dev_tx_fifo_size_14, dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444); -MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768"); -module_param_named(dev_tx_fifo_size_15, dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444); -MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768"); - -module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444); -MODULE_PARM_DESC(thr_ctl, "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled"); -module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int, 0444); -MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs"); -module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int, 0444); -MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs"); - -module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444); -MODULE_PARM_DESC(pti_enable, "Per Transfer Interrupt mode 0=disabled 1=enabled"); - -module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444); -MODULE_PARM_DESC(mpi_enable, "Multiprocessor Interrupt mode 0=disabled 1=enabled"); - -/** @page "Module Parameters" - * - * The following parameters may be specified when starting the module. - * These parameters define how the DWC_otg controller should be - * configured. Parameter values are passed to the CIL initialization - * function dwc_otg_cil_init - * - * Example: modprobe dwc_otg speed=1 otg_cap=1 - * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/ diff --git a/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_driver.h b/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_driver.h deleted file mode 100644 index fd7f0a4b9d..0000000000 --- a/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_driver.h +++ /dev/null @@ -1,83 +0,0 @@ -/* ========================================================================== - * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.h $ - * $Revision: 1.2 $ - * $Date: 2008-11-21 05:39:15 $ - * $Change: 1064918 $ - * - * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, - * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless - * otherwise expressly agreed to in writing between Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ - -#ifndef __DWC_OTG_DRIVER_H__ -#define __DWC_OTG_DRIVER_H__ - -/** @file - * This file contains the interface to the Linux driver. - */ -#include "dwc_otg_cil.h" - -/* Type declarations */ -struct dwc_otg_pcd; -struct dwc_otg_hcd; - -/** - * This structure is a wrapper that encapsulates the driver components used to - * manage a single DWC_otg controller. - */ -typedef struct dwc_otg_device { - /** Base address returned from ioremap() */ - void *base; - - struct device *parent; - - /** Pointer to the core interface structure. */ - dwc_otg_core_if_t *core_if; - - /** Register offset for Diagnostic API. */ - uint32_t reg_offset; - - /** Pointer to the PCD structure. */ - struct dwc_otg_pcd *pcd; - - /** Pointer to the HCD structure. */ - struct dwc_otg_hcd *hcd; - - /** Flag to indicate whether the common IRQ handler is installed. */ - uint8_t common_irq_installed; - - /* Interrupt request number. */ - unsigned int irq; - - /* Physical address of Control and Status registers, used by - * release_mem_region(). - */ - resource_size_t phys_addr; - - /* Length of memory region, used by release_mem_region(). */ - unsigned long base_len; -} dwc_otg_device_t; - -#endif diff --git a/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_hcd.c b/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_hcd.c deleted file mode 100644 index fe643b6460..0000000000 --- a/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_hcd.c +++ /dev/null @@ -1,2852 +0,0 @@ -/* ========================================================================== - * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $ - * $Revision: 1.4 $ - * $Date: 2008-11-21 05:39:15 $ - * $Change: 1064940 $ - * - * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, - * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless - * otherwise expressly agreed to in writing between Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ -#ifndef DWC_DEVICE_ONLY - -/** - * @file - * - * This file contains the implementation of the HCD. In Linux, the HCD - * implements the hc_driver API. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "dwc_otg_driver.h" -#include "dwc_otg_hcd.h" -#include "dwc_otg_regs.h" - -static const char dwc_otg_hcd_name[] = "dwc_otg"; - -static const struct hc_driver dwc_otg_hc_driver = { - - .description = dwc_otg_hcd_name, - .product_desc = "DWC OTG Controller", - .hcd_priv_size = sizeof(dwc_otg_hcd_t), - - .irq = dwc_otg_hcd_irq, - - .flags = HCD_MEMORY | HCD_USB2, - - //.reset = - .start = dwc_otg_hcd_start, - //.suspend = - //.resume = - .stop = dwc_otg_hcd_stop, - - .urb_enqueue = dwc_otg_hcd_urb_enqueue, - .urb_dequeue = dwc_otg_hcd_urb_dequeue, - .endpoint_disable = dwc_otg_hcd_endpoint_disable, - - .get_frame_number = dwc_otg_hcd_get_frame_number, - - .hub_status_data = dwc_otg_hcd_hub_status_data, - .hub_control = dwc_otg_hcd_hub_control, - //.hub_suspend = - //.hub_resume = -}; - -/** - * Work queue function for starting the HCD when A-Cable is connected. - * The dwc_otg_hcd_start() must be called in a process context. - */ -static void hcd_start_func( -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) - void *_vp -#else - struct work_struct *_work -#endif - ) -{ -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) - struct usb_hcd *usb_hcd = (struct usb_hcd *)_vp; -#else - struct delayed_work *dw = container_of(_work, struct delayed_work, work); - struct dwc_otg_hcd *otg_hcd = container_of(dw, struct dwc_otg_hcd, start_work); - struct usb_hcd *usb_hcd = container_of((void *)otg_hcd, struct usb_hcd, hcd_priv); -#endif - DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, usb_hcd); - if (usb_hcd) { - dwc_otg_hcd_start(usb_hcd); - } -} - -/** - * HCD Callback function for starting the HCD when A-Cable is - * connected. - * - * @param p void pointer to the struct usb_hcd - */ -static int32_t dwc_otg_hcd_start_cb(void *p) -{ - dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(p); - dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; - hprt0_data_t hprt0; - - if (core_if->op_state == B_HOST) { - /* - * Reset the port. During a HNP mode switch the reset - * needs to occur within 1ms and have a duration of at - * least 50ms. - */ - hprt0.d32 = dwc_otg_read_hprt0(core_if); - hprt0.b.prtrst = 1; - dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); - ((struct usb_hcd *)p)->self.is_b_host = 1; - } else { - ((struct usb_hcd *)p)->self.is_b_host = 0; - } - - /* Need to start the HCD in a non-interrupt context. */ -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) - INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func, p); -// INIT_DELAYED_WORK(&dwc_otg_hcd->start_work, hcd_start_func, p); -#else -// INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func); - INIT_DELAYED_WORK(&dwc_otg_hcd->start_work, hcd_start_func); -#endif -// schedule_work(&dwc_otg_hcd->start_work); - queue_delayed_work(core_if->wq_otg, &dwc_otg_hcd->start_work, 50 * HZ / 1000); - - return 1; -} - -/** - * HCD Callback function for stopping the HCD. - * - * @param p void pointer to the struct usb_hcd - */ -static int32_t dwc_otg_hcd_stop_cb(void *p) -{ - struct usb_hcd *usb_hcd = (struct usb_hcd *)p; - DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p); - dwc_otg_hcd_stop(usb_hcd); - return 1; -} - -static void del_xfer_timers(dwc_otg_hcd_t *hcd) -{ -#ifdef DEBUG - int i; - int num_channels = hcd->core_if->core_params->host_channels; - for (i = 0; i < num_channels; i++) { - del_timer(&hcd->core_if->hc_xfer_timer[i]); - } -#endif -} - -static void del_timers(dwc_otg_hcd_t *hcd) -{ - del_xfer_timers(hcd); - del_timer(&hcd->conn_timer); -} - -/** - * Processes all the URBs in a single list of QHs. Completes them with - * -ETIMEDOUT and frees the QTD. - */ -static void kill_urbs_in_qh_list(dwc_otg_hcd_t *hcd, struct list_head *qh_list) -{ - struct list_head *qh_item; - dwc_otg_qh_t *qh; - struct list_head *qtd_item; - dwc_otg_qtd_t *qtd; - - list_for_each(qh_item, qh_list) { - qh = list_entry(qh_item, dwc_otg_qh_t, qh_list_entry); - for (qtd_item = qh->qtd_list.next; - qtd_item != &qh->qtd_list; - qtd_item = qh->qtd_list.next) { - qtd = list_entry(qtd_item, dwc_otg_qtd_t, qtd_list_entry); - if (qtd->urb != NULL) { - dwc_otg_hcd_complete_urb(hcd, qtd->urb, - -ETIMEDOUT); - } - dwc_otg_hcd_qtd_remove_and_free(hcd, qtd); - } - } -} - -/** - * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic - * and periodic schedules. The QTD associated with each URB is removed from - * the schedule and freed. This function may be called when a disconnect is - * detected or when the HCD is being stopped. - */ -static void kill_all_urbs(dwc_otg_hcd_t *hcd) -{ - kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive); - kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active); - kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive); - kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready); - kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned); - kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued); -} - -/** - * HCD Callback function for disconnect of the HCD. - * - * @param p void pointer to the struct usb_hcd - */ -static int32_t dwc_otg_hcd_disconnect_cb(void *p) -{ - gintsts_data_t intr; - dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(p); - - //DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p); - - /* - * Set status flags for the hub driver. - */ - dwc_otg_hcd->flags.b.port_connect_status_change = 1; - dwc_otg_hcd->flags.b.port_connect_status = 0; - - /* - * Shutdown any transfers in process by clearing the Tx FIFO Empty - * interrupt mask and status bits and disabling subsequent host - * channel interrupts. - */ - intr.d32 = 0; - intr.b.nptxfempty = 1; - intr.b.ptxfempty = 1; - intr.b.hcintr = 1; - dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, intr.d32, 0); - dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintsts, intr.d32, 0); - - del_timers(dwc_otg_hcd); - - /* - * Turn off the vbus power only if the core has transitioned to device - * mode. If still in host mode, need to keep power on to detect a - * reconnection. - */ - if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) { - if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) { - hprt0_data_t hprt0 = { .d32=0 }; - DWC_PRINT("Disconnect: PortPower off\n"); - hprt0.b.prtpwr = 0; - dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32); - } - - dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if); - } - - /* Respond with an error status to all URBs in the schedule. */ - kill_all_urbs(dwc_otg_hcd); - - if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) { - /* Clean up any host channels that were in use. */ - int num_channels; - int i; - dwc_hc_t *channel; - dwc_otg_hc_regs_t *hc_regs; - hcchar_data_t hcchar; - - num_channels = dwc_otg_hcd->core_if->core_params->host_channels; - - if (!dwc_otg_hcd->core_if->dma_enable) { - /* Flush out any channel requests in slave mode. */ - for (i = 0; i < num_channels; i++) { - channel = dwc_otg_hcd->hc_ptr_array[i]; - if (list_empty(&channel->hc_list_entry)) { - hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i]; - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - if (hcchar.b.chen) { - hcchar.b.chen = 0; - hcchar.b.chdis = 1; - hcchar.b.epdir = 0; - dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); - } - } - } - } - - for (i = 0; i < num_channels; i++) { - channel = dwc_otg_hcd->hc_ptr_array[i]; - if (list_empty(&channel->hc_list_entry)) { - hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i]; - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - if (hcchar.b.chen) { - /* Halt the channel. */ - hcchar.b.chdis = 1; - dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); - } - - dwc_otg_hc_cleanup(dwc_otg_hcd->core_if, channel); - list_add_tail(&channel->hc_list_entry, - &dwc_otg_hcd->free_hc_list); - } - } - } - - /* A disconnect will end the session so the B-Device is no - * longer a B-host. */ - ((struct usb_hcd *)p)->self.is_b_host = 0; - return 1; -} - -/** - * Connection timeout function. An OTG host is required to display a - * message if the device does not connect within 10 seconds. - */ -void dwc_otg_hcd_connect_timeout(unsigned long ptr) -{ - DWC_DEBUGPL(DBG_HCDV, "%s(%x)\n", __func__, (int)ptr); - DWC_PRINT("Connect Timeout\n"); - DWC_ERROR("Device Not Connected/Responding\n"); -} - -/** - * Start the connection timer. An OTG host is required to display a - * message if the device does not connect within 10 seconds. The - * timer is deleted if a port connect interrupt occurs before the - * timer expires. - */ -static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t *hcd) -{ - init_timer(&hcd->conn_timer); - hcd->conn_timer.function = dwc_otg_hcd_connect_timeout; - hcd->conn_timer.data = 0; - hcd->conn_timer.expires = jiffies + (HZ * 10); - add_timer(&hcd->conn_timer); -} - -/** - * HCD Callback function for disconnect of the HCD. - * - * @param p void pointer to the struct usb_hcd - */ -static int32_t dwc_otg_hcd_session_start_cb(void *p) -{ - dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(p); - DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p); - dwc_otg_hcd_start_connect_timer(dwc_otg_hcd); - return 1; -} - -/** - * HCD Callback structure for handling mode switching. - */ -static dwc_otg_cil_callbacks_t hcd_cil_callbacks = { - .start = dwc_otg_hcd_start_cb, - .stop = dwc_otg_hcd_stop_cb, - .disconnect = dwc_otg_hcd_disconnect_cb, - .session_start = dwc_otg_hcd_session_start_cb, - .p = 0, -}; - -/** - * Reset tasklet function - */ -static void reset_tasklet_func(unsigned long data) -{ - dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *)data; - dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; - hprt0_data_t hprt0; - - DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n"); - - hprt0.d32 = dwc_otg_read_hprt0(core_if); - hprt0.b.prtrst = 1; - dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); - mdelay(60); - - hprt0.b.prtrst = 0; - dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); - dwc_otg_hcd->flags.b.port_reset_change = 1; -} - -static struct tasklet_struct reset_tasklet = { - .next = NULL, - .state = 0, - .count = ATOMIC_INIT(0), - .func = reset_tasklet_func, - .data = 0, -}; - -/** - * Initializes the HCD. This function allocates memory for and initializes the - * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the - * USB bus with the core and calls the hc_driver->start() function. It returns - * a negative error on failure. - */ -int dwc_otg_hcd_init(struct device *dev) -{ - dwc_otg_device_t *otg_dev = dev_get_drvdata(dev); - struct usb_hcd *hcd = NULL; - dwc_otg_hcd_t *dwc_otg_hcd = NULL; - - int num_channels; - int i; - dwc_hc_t *channel; - - int retval = 0; - - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n"); - -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) - /* 2.6.20+ requires dev.dma_mask to be set prior to calling usb_create_hcd() */ - - /* Set device flags indicating whether the HCD supports DMA. */ - if (otg_dev->core_if->dma_enable) { - DWC_PRINT("Using DMA mode\n"); - dev->dma_mask = (void *)~0; - dev->coherent_dma_mask = ~0; - - if (otg_dev->core_if->dma_desc_enable) { - DWC_PRINT("Device using Descriptor DMA mode\n"); - } else { - DWC_PRINT("Device using Buffer DMA mode\n"); - } - } else { - DWC_PRINT("Using Slave mode\n"); - dev->dma_mask = (void *)0; - dev->coherent_dma_mask = 0; - } -#endif - /* - * Allocate memory for the base HCD plus the DWC OTG HCD. - * Initialize the base HCD. - */ - hcd = usb_create_hcd(&dwc_otg_hc_driver, dev, dev_name(dev)); - if (!hcd) { - retval = -ENOMEM; - goto error1; - } - - dev_set_drvdata(dev, otg_dev); - hcd->regs = otg_dev->base; - hcd->rsrc_start = otg_dev->phys_addr; - hcd->rsrc_len = otg_dev->base_len; - hcd->self.otg_port = 1; - hcd->has_tt = 1; - - /* Initialize the DWC OTG HCD. */ - dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); - dwc_otg_hcd->core_if = otg_dev->core_if; - otg_dev->hcd = dwc_otg_hcd; - - /* */ - spin_lock_init(&dwc_otg_hcd->lock); - - /* Register the HCD CIL Callbacks */ - dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if, - &hcd_cil_callbacks, hcd); - - /* Initialize the non-periodic schedule. */ - INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive); - INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active); - - /* Initialize the periodic schedule. */ - INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive); - INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready); - INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned); - INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued); - - /* - * Create a host channel descriptor for each host channel implemented - * in the controller. Initialize the channel descriptor array. - */ - INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list); - num_channels = dwc_otg_hcd->core_if->core_params->host_channels; - memset(dwc_otg_hcd->hc_ptr_array, 0, sizeof(dwc_otg_hcd->hc_ptr_array)); - for (i = 0; i < num_channels; i++) { - channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL); - if (channel == NULL) { - retval = -ENOMEM; - DWC_ERROR("%s: host channel allocation failed\n", __func__); - goto error2; - } - memset(channel, 0, sizeof(dwc_hc_t)); - channel->hc_num = i; - dwc_otg_hcd->hc_ptr_array[i] = channel; -#ifdef DEBUG - init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]); -#endif - DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel); - } - - /* Initialize the Connection timeout timer. */ - init_timer(&dwc_otg_hcd->conn_timer); - - /* Initialize reset tasklet. */ - reset_tasklet.data = (unsigned long) dwc_otg_hcd; - dwc_otg_hcd->reset_tasklet = &reset_tasklet; - -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) - /* Set device flags indicating whether the HCD supports DMA. */ - if (otg_dev->core_if->dma_enable) { - DWC_PRINT("Using DMA mode\n"); - dev->dma_mask = (void *)~0; - dev->coherent_dma_mask = ~0; - - if (otg_dev->core_if->dma_desc_enable){ - DWC_PRINT("Device using Descriptor DMA mode\n"); - } else { - DWC_PRINT("Device using Buffer DMA mode\n"); - } - } else { - DWC_PRINT("Using Slave mode\n"); - dev->dma_mask = (void *)0; - dev->dev.coherent_dma_mask = 0; - } -#endif - /* - * Finish generic HCD initialization and start the HCD. This function - * allocates the DMA buffer pool, registers the USB bus, requests the - * IRQ line, and calls dwc_otg_hcd_start method. - */ - retval = usb_add_hcd(hcd, otg_dev->irq, IRQF_SHARED); - if (retval < 0) { - goto error2; - } - - /* - * Allocate space for storing data on status transactions. Normally no - * data is sent, but this space acts as a bit bucket. This must be - * done after usb_add_hcd since that function allocates the DMA buffer - * pool. - */ - if (otg_dev->core_if->dma_enable) { - dwc_otg_hcd->status_buf = - dma_alloc_coherent(dev, - DWC_OTG_HCD_STATUS_BUF_SIZE, - &dwc_otg_hcd->status_buf_dma, - GFP_KERNEL | GFP_DMA); - } else { - dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE, - GFP_KERNEL); - } - if (!dwc_otg_hcd->status_buf) { - retval = -ENOMEM; - DWC_ERROR("%s: status_buf allocation failed\n", __func__); - goto error3; - } - - dwc_otg_hcd->otg_dev = otg_dev; - - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n", - dev_name(dev), hcd->self.busnum); - - return 0; - - /* Error conditions */ - error3: - usb_remove_hcd(hcd); - error2: - dwc_otg_hcd_free(hcd); - usb_put_hcd(hcd); - - /* FIXME: 2008/05/03 by Steven - * write back to device: - * dwc_otg_hcd has already been released by dwc_otg_hcd_free() - */ - dev_set_drvdata(dev, otg_dev); - - error1: - return retval; -} - -/** - * Removes the HCD. - * Frees memory and resources associated with the HCD and deregisters the bus. - */ -void dwc_otg_hcd_remove(struct device *dev) -{ - dwc_otg_device_t *otg_dev = dev_get_drvdata(dev); - dwc_otg_hcd_t *dwc_otg_hcd; - struct usb_hcd *hcd; - - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE\n"); - - if (!otg_dev) { - DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__); - return; - } - - dwc_otg_hcd = otg_dev->hcd; - - if (!dwc_otg_hcd) { - DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__); - return; - } - - hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd); - - if (!hcd) { - DWC_DEBUGPL(DBG_ANY, "%s: dwc_otg_hcd_to_hcd(dwc_otg_hcd) NULL!\n", __func__); - return; - } - - /* Turn off all interrupts */ - dwc_write_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0); - dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gahbcfg, 1, 0); - - usb_remove_hcd(hcd); - dwc_otg_hcd_free(hcd); - usb_put_hcd(hcd); -} - -/* ========================================================================= - * Linux HC Driver Functions - * ========================================================================= */ - -/** - * Initializes dynamic portions of the DWC_otg HCD state. - */ -static void hcd_reinit(dwc_otg_hcd_t *hcd) -{ - struct list_head *item; - int num_channels; - int i; - dwc_hc_t *channel; - - hcd->flags.d32 = 0; - - hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active; - hcd->non_periodic_channels = 0; - hcd->periodic_channels = 0; - - /* - * Put all channels in the free channel list and clean up channel - * states. - */ - item = hcd->free_hc_list.next; - while (item != &hcd->free_hc_list) { - list_del(item); - item = hcd->free_hc_list.next; - } - num_channels = hcd->core_if->core_params->host_channels; - for (i = 0; i < num_channels; i++) { - channel = hcd->hc_ptr_array[i]; - list_add_tail(&channel->hc_list_entry, &hcd->free_hc_list); - dwc_otg_hc_cleanup(hcd->core_if, channel); - } - - /* Initialize the DWC core for host mode operation. */ - dwc_otg_core_host_init(hcd->core_if); -} - -/** Initializes the DWC_otg controller and its root hub and prepares it for host - * mode operation. Activates the root port. Returns 0 on success and a negative - * error code on failure. */ -int dwc_otg_hcd_start(struct usb_hcd *hcd) -{ - dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); - dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; - struct usb_bus *bus; - -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) - struct usb_device *udev; - int retval; -#endif - - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n"); - - bus = hcd_to_bus(hcd); - - /* Initialize the bus state. If the core is in Device Mode - * HALT the USB bus and return. */ - if (dwc_otg_is_device_mode(core_if)) { -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) - hcd->state = HC_STATE_HALT; -#else - hcd->state = HC_STATE_RUNNING; -#endif - return 0; - } - hcd->state = HC_STATE_RUNNING; - - /* Initialize and connect root hub if one is not already attached */ - if (bus->root_hub) { - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n"); - /* Inform the HUB driver to resume. */ - usb_hcd_resume_root_hub(hcd); - } - else { - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Does Not Have Root Hub\n"); - -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) - udev = usb_alloc_dev(NULL, bus, 0); - udev->speed = USB_SPEED_HIGH; - if (!udev) { - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error udev alloc\n"); - return -ENODEV; - } - if ((retval = usb_hcd_register_root_hub(udev, hcd)) != 0) { - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error registering %d\n", retval); - return -ENODEV; - } -#endif - } - - hcd_reinit(dwc_otg_hcd); - - return 0; -} - -static void qh_list_free(dwc_otg_hcd_t *hcd, struct list_head *qh_list) -{ - struct list_head *item; - dwc_otg_qh_t *qh; - - if (!qh_list->next) { - /* The list hasn't been initialized yet. */ - return; - } - - /* Ensure there are no QTDs or URBs left. */ - kill_urbs_in_qh_list(hcd, qh_list); - - for (item = qh_list->next; item != qh_list; item = qh_list->next) { - qh = list_entry(item, dwc_otg_qh_t, qh_list_entry); - dwc_otg_hcd_qh_remove_and_free(hcd, qh); - } -} - -/** - * Halts the DWC_otg host mode operations in a clean manner. USB transfers are - * stopped. - */ -void dwc_otg_hcd_stop(struct usb_hcd *hcd) -{ - dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); - hprt0_data_t hprt0 = { .d32=0 }; - - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n"); - - /* Turn off all host-specific interrupts. */ - dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if); - - /* - * The root hub should be disconnected before this function is called. - * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) - * and the QH lists (via ..._hcd_endpoint_disable). - */ - - /* Turn off the vbus power */ - DWC_PRINT("PortPower off\n"); - hprt0.b.prtpwr = 0; - dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32); -} - -/** Returns the current frame number. */ -int dwc_otg_hcd_get_frame_number(struct usb_hcd *hcd) -{ - dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); - hfnum_data_t hfnum; - - hfnum.d32 = dwc_read_reg32(&dwc_otg_hcd->core_if-> - host_if->host_global_regs->hfnum); - -#ifdef DEBUG_SOF - DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n", hfnum.b.frnum); -#endif - return hfnum.b.frnum; -} - -/** - * Frees secondary storage associated with the dwc_otg_hcd structure contained - * in the struct usb_hcd field. - */ -void dwc_otg_hcd_free(struct usb_hcd *hcd) -{ - dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); - int i; - - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n"); - - del_timers(dwc_otg_hcd); - - /* Free memory for QH/QTD lists */ - qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive); - qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active); - qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive); - qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready); - qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned); - qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued); - - /* Free memory for the host channels. */ - for (i = 0; i < MAX_EPS_CHANNELS; i++) { - dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i]; - if (hc != NULL) { - DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n", i, hc); - kfree(hc); - } - } - - if (dwc_otg_hcd->core_if->dma_enable) { - if (dwc_otg_hcd->status_buf_dma) { - dma_free_coherent(hcd->self.controller, - DWC_OTG_HCD_STATUS_BUF_SIZE, - dwc_otg_hcd->status_buf, - dwc_otg_hcd->status_buf_dma); - } - } else if (dwc_otg_hcd->status_buf != NULL) { - kfree(dwc_otg_hcd->status_buf); - } -} - -#ifdef DEBUG -static void dump_urb_info(struct urb *urb, char* fn_name) -{ - DWC_PRINT("%s, urb %p\n", fn_name, urb); - DWC_PRINT(" Device address: %d\n", usb_pipedevice(urb->pipe)); - DWC_PRINT(" Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe), - (usb_pipein(urb->pipe) ? "IN" : "OUT")); - DWC_PRINT(" Endpoint type: %s\n", - ({char *pipetype; - switch (usb_pipetype(urb->pipe)) { - case PIPE_CONTROL: pipetype = "CONTROL"; break; - case PIPE_BULK: pipetype = "BULK"; break; - case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break; - case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break; - default: pipetype = "UNKNOWN"; break; - }; pipetype;})); - DWC_PRINT(" Speed: %s\n", - ({char *speed; - switch (urb->dev->speed) { - case USB_SPEED_HIGH: speed = "HIGH"; break; - case USB_SPEED_FULL: speed = "FULL"; break; - case USB_SPEED_LOW: speed = "LOW"; break; - default: speed = "UNKNOWN"; break; - }; speed;})); - DWC_PRINT(" Max packet size: %d\n", - usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); - DWC_PRINT(" Data buffer length: %d\n", urb->transfer_buffer_length); - DWC_PRINT(" Transfer buffer: %p, Transfer DMA: %p\n", - urb->transfer_buffer, (void *)urb->transfer_dma); - DWC_PRINT(" Setup buffer: %p, Setup DMA: %p\n", - urb->setup_packet, (void *)urb->setup_dma); - DWC_PRINT(" Interval: %d\n", urb->interval); - if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { - int i; - for (i = 0; i < urb->number_of_packets; i++) { - DWC_PRINT(" ISO Desc %d:\n", i); - DWC_PRINT(" offset: %d, length %d\n", - urb->iso_frame_desc[i].offset, - urb->iso_frame_desc[i].length); - } - } -} - -static void dump_channel_info(dwc_otg_hcd_t *hcd, - dwc_otg_qh_t *qh) -{ - if (qh->channel != NULL) { - dwc_hc_t *hc = qh->channel; - struct list_head *item; - dwc_otg_qh_t *qh_item; - int num_channels = hcd->core_if->core_params->host_channels; - int i; - - dwc_otg_hc_regs_t *hc_regs; - hcchar_data_t hcchar; - hcsplt_data_t hcsplt; - hctsiz_data_t hctsiz; - uint32_t hcdma; - - hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num]; - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt); - hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); - hcdma = dwc_read_reg32(&hc_regs->hcdma); - - DWC_PRINT(" Assigned to channel %p:\n", hc); - DWC_PRINT(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32); - DWC_PRINT(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma); - DWC_PRINT(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n", - hc->dev_addr, hc->ep_num, hc->ep_is_in); - DWC_PRINT(" ep_type: %d\n", hc->ep_type); - DWC_PRINT(" max_packet: %d\n", hc->max_packet); - DWC_PRINT(" data_pid_start: %d\n", hc->data_pid_start); - DWC_PRINT(" xfer_started: %d\n", hc->xfer_started); - DWC_PRINT(" halt_status: %d\n", hc->halt_status); - DWC_PRINT(" xfer_buff: %p\n", hc->xfer_buff); - DWC_PRINT(" xfer_len: %d\n", hc->xfer_len); - DWC_PRINT(" qh: %p\n", hc->qh); - DWC_PRINT(" NP inactive sched:\n"); - list_for_each(item, &hcd->non_periodic_sched_inactive) { - qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry); - DWC_PRINT(" %p\n", qh_item); - } - DWC_PRINT(" NP active sched:\n"); - list_for_each(item, &hcd->non_periodic_sched_active) { - qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry); - DWC_PRINT(" %p\n", qh_item); - } - DWC_PRINT(" Channels: \n"); - for (i = 0; i < num_channels; i++) { - dwc_hc_t *hc = hcd->hc_ptr_array[i]; - DWC_PRINT(" %2d: %p\n", i, hc); - } - } -} -#endif - -/** Starts processing a USB transfer request specified by a USB Request Block - * (URB). mem_flags indicates the type of memory allocation to use while - * processing this URB. */ -int dwc_otg_hcd_urb_enqueue(struct usb_hcd *hcd, - struct urb *urb, -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) - int mem_flags -#else - gfp_t mem_flags -#endif - ) -{ - int retval = 0; - dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); - dwc_otg_qtd_t *qtd; - -#ifdef DEBUG - if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { - dump_urb_info(urb, "dwc_otg_hcd_urb_enqueue"); - } -#endif - if (!dwc_otg_hcd->flags.b.port_connect_status) { - /* No longer connected. */ - return -ENODEV; - } - - qtd = dwc_otg_hcd_qtd_create(urb); - if (qtd == NULL) { - DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n"); - return -ENOMEM; - } - - retval = dwc_otg_hcd_qtd_add(qtd, dwc_otg_hcd); - if (retval < 0) { - DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. " - "Error status %d\n", retval); - dwc_otg_hcd_qtd_free(qtd); - } - - return retval; -} - -/** Aborts/cancels a USB transfer request. Always returns 0 to indicate - * success. */ -int dwc_otg_hcd_urb_dequeue(struct usb_hcd *hcd, - struct urb *urb, - int status) -{ - unsigned long flags; - dwc_otg_hcd_t *dwc_otg_hcd; - dwc_otg_qtd_t *urb_qtd; - dwc_otg_qh_t *qh; -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) - struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb); -#endif - - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n"); - - dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); - - SPIN_LOCK_IRQSAVE(&dwc_otg_hcd->lock, flags); - - urb_qtd = (dwc_otg_qtd_t *)urb->hcpriv; - qh = (dwc_otg_qh_t *)ep->hcpriv; - -#ifdef DEBUG - if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { - dump_urb_info(urb, "dwc_otg_hcd_urb_dequeue"); - if (urb_qtd == qh->qtd_in_process) { - dump_channel_info(dwc_otg_hcd, qh); - } - } -#endif - - if (urb_qtd == qh->qtd_in_process) { - /* The QTD is in process (it has been assigned to a channel). */ - - if (dwc_otg_hcd->flags.b.port_connect_status) { - /* - * If still connected (i.e. in host mode), halt the - * channel so it can be used for other transfers. If - * no longer connected, the host registers can't be - * written to halt the channel since the core is in - * device mode. - */ - dwc_otg_hc_halt(dwc_otg_hcd->core_if, qh->channel, - DWC_OTG_HC_XFER_URB_DEQUEUE); - } - } - - /* - * Free the QTD and clean up the associated QH. Leave the QH in the - * schedule if it has any remaining QTDs. - */ - dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd, urb_qtd); - if (urb_qtd == qh->qtd_in_process) { - dwc_otg_hcd_qh_deactivate(dwc_otg_hcd, qh, 0); - qh->channel = NULL; - qh->qtd_in_process = NULL; - } else if (list_empty(&qh->qtd_list)) { - dwc_otg_hcd_qh_remove(dwc_otg_hcd, qh); - } - - SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags); - - urb->hcpriv = NULL; - - /* Higher layer software sets URB status. */ -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) - usb_hcd_giveback_urb(hcd, urb, status); -#else - usb_hcd_giveback_urb(hcd, urb, NULL); -#endif - if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { - DWC_PRINT("Called usb_hcd_giveback_urb()\n"); - DWC_PRINT(" urb->status = %d\n", urb->status); - } - - return 0; -} - -/** Frees resources in the DWC_otg controller related to a given endpoint. Also - * clears state in the HCD related to the endpoint. Any URBs for the endpoint - * must already be dequeued. */ -void dwc_otg_hcd_endpoint_disable(struct usb_hcd *hcd, - struct usb_host_endpoint *ep) -{ - dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); - dwc_otg_qh_t *qh; - -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) - unsigned long flags; - int retry = 0; -#endif - - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, " - "endpoint=%d\n", ep->desc.bEndpointAddress, - dwc_ep_addr_to_endpoint(ep->desc.bEndpointAddress)); - -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -rescan: - SPIN_LOCK_IRQSAVE(&dwc_otg_hcd->lock, flags); - qh = (dwc_otg_qh_t *)(ep->hcpriv); - if (!qh) - goto done; - - /** Check that the QTD list is really empty */ - if (!list_empty(&qh->qtd_list)) { - if (retry++ < 250) { - SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags); - schedule_timeout_uninterruptible(1); - goto rescan; - } - - DWC_WARN("DWC OTG HCD EP DISABLE:" - " QTD List for this endpoint is not empty\n"); - } - - dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd, qh); - ep->hcpriv = NULL; -done: - SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags); - -#else // LINUX_VERSION_CODE - - qh = (dwc_otg_qh_t *)(ep->hcpriv); - if (qh != NULL) { -#ifdef DEBUG - /** Check that the QTD list is really empty */ - if (!list_empty(&qh->qtd_list)) { - DWC_WARN("DWC OTG HCD EP DISABLE:" - " QTD List for this endpoint is not empty\n"); - } -#endif - dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd, qh); - ep->hcpriv = NULL; - } -#endif // LINUX_VERSION_CODE -} - -/** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if - * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid - * interrupt. - * - * This function is called by the USB core when an interrupt occurs */ -irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) - , struct pt_regs *regs -#endif - ) -{ - dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); - return IRQ_RETVAL(dwc_otg_hcd_handle_intr(dwc_otg_hcd)); -} - -/** Creates Status Change bitmap for the root hub and root port. The bitmap is - * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 - * is the status change indicator for the single root port. Returns 1 if either - * change indicator is 1, otherwise returns 0. */ -int dwc_otg_hcd_hub_status_data(struct usb_hcd *hcd, char *buf) -{ - dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); - - buf[0] = 0; - buf[0] |= (dwc_otg_hcd->flags.b.port_connect_status_change || - dwc_otg_hcd->flags.b.port_reset_change || - dwc_otg_hcd->flags.b.port_enable_change || - dwc_otg_hcd->flags.b.port_suspend_change || - dwc_otg_hcd->flags.b.port_over_current_change) << 1; - -#ifdef DEBUG - if (buf[0]) { - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:" - " Root port status changed\n"); - DWC_DEBUGPL(DBG_HCDV, " port_connect_status_change: %d\n", - dwc_otg_hcd->flags.b.port_connect_status_change); - DWC_DEBUGPL(DBG_HCDV, " port_reset_change: %d\n", - dwc_otg_hcd->flags.b.port_reset_change); - DWC_DEBUGPL(DBG_HCDV, " port_enable_change: %d\n", - dwc_otg_hcd->flags.b.port_enable_change); - DWC_DEBUGPL(DBG_HCDV, " port_suspend_change: %d\n", - dwc_otg_hcd->flags.b.port_suspend_change); - DWC_DEBUGPL(DBG_HCDV, " port_over_current_change: %d\n", - dwc_otg_hcd->flags.b.port_over_current_change); - } -#endif - return (buf[0] != 0); -} - -#ifdef DWC_HS_ELECT_TST -/* - * Quick and dirty hack to implement the HS Electrical Test - * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature. - * - * This code was copied from our userspace app "hset". It sends a - * Get Device Descriptor control sequence in two parts, first the - * Setup packet by itself, followed some time later by the In and - * Ack packets. Rather than trying to figure out how to add this - * functionality to the normal driver code, we just hijack the - * hardware, using these two function to drive the hardware - * directly. - */ - -dwc_otg_core_global_regs_t *global_regs; -dwc_otg_host_global_regs_t *hc_global_regs; -dwc_otg_hc_regs_t *hc_regs; -uint32_t *data_fifo; - -static void do_setup(void) -{ - gintsts_data_t gintsts; - hctsiz_data_t hctsiz; - hcchar_data_t hcchar; - haint_data_t haint; - hcint_data_t hcint; - - /* Enable HAINTs */ - dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001); - - /* Enable HCINTs */ - dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3); - - /* Read GINTSTS */ - gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); - //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); - - /* Read HAINT */ - haint.d32 = dwc_read_reg32(&hc_global_regs->haint); - //fprintf(stderr, "HAINT: %08x\n", haint.d32); - - /* Read HCINT */ - hcint.d32 = dwc_read_reg32(&hc_regs->hcint); - //fprintf(stderr, "HCINT: %08x\n", hcint.d32); - - /* Read HCCHAR */ - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); - - /* Clear HCINT */ - dwc_write_reg32(&hc_regs->hcint, hcint.d32); - - /* Clear HAINT */ - dwc_write_reg32(&hc_global_regs->haint, haint.d32); - - /* Clear GINTSTS */ - dwc_write_reg32(&global_regs->gintsts, gintsts.d32); - - /* Read GINTSTS */ - gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); - //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); - - /* - * Send Setup packet (Get Device Descriptor) - */ - - /* Make sure channel is disabled */ - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - if (hcchar.b.chen) { - //fprintf(stderr, "Channel already enabled 1, HCCHAR = %08x\n", hcchar.d32); - hcchar.b.chdis = 1; -// hcchar.b.chen = 1; - dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); - //sleep(1); - mdelay(1000); - - /* Read GINTSTS */ - gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); - //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); - - /* Read HAINT */ - haint.d32 = dwc_read_reg32(&hc_global_regs->haint); - //fprintf(stderr, "HAINT: %08x\n", haint.d32); - - /* Read HCINT */ - hcint.d32 = dwc_read_reg32(&hc_regs->hcint); - //fprintf(stderr, "HCINT: %08x\n", hcint.d32); - - /* Read HCCHAR */ - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); - - /* Clear HCINT */ - dwc_write_reg32(&hc_regs->hcint, hcint.d32); - - /* Clear HAINT */ - dwc_write_reg32(&hc_global_regs->haint, haint.d32); - - /* Clear GINTSTS */ - dwc_write_reg32(&global_regs->gintsts, gintsts.d32); - - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - //if (hcchar.b.chen) { - // fprintf(stderr, "** Channel _still_ enabled 1, HCCHAR = %08x **\n", hcchar.d32); - //} - } - - /* Set HCTSIZ */ - hctsiz.d32 = 0; - hctsiz.b.xfersize = 8; - hctsiz.b.pktcnt = 1; - hctsiz.b.pid = DWC_OTG_HC_PID_SETUP; - dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); - - /* Set HCCHAR */ - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; - hcchar.b.epdir = 0; - hcchar.b.epnum = 0; - hcchar.b.mps = 8; - hcchar.b.chen = 1; - dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); - - /* Fill FIFO with Setup data for Get Device Descriptor */ - data_fifo = (uint32_t *)((char *)global_regs + 0x1000); - dwc_write_reg32(data_fifo++, 0x01000680); - dwc_write_reg32(data_fifo++, 0x00080000); - - gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); - //fprintf(stderr, "Waiting for HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32); - - /* Wait for host channel interrupt */ - do { - gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); - } while (gintsts.b.hcintr == 0); - - //fprintf(stderr, "Got HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32); - - /* Disable HCINTs */ - dwc_write_reg32(&hc_regs->hcintmsk, 0x0000); - - /* Disable HAINTs */ - dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000); - - /* Read HAINT */ - haint.d32 = dwc_read_reg32(&hc_global_regs->haint); - //fprintf(stderr, "HAINT: %08x\n", haint.d32); - - /* Read HCINT */ - hcint.d32 = dwc_read_reg32(&hc_regs->hcint); - //fprintf(stderr, "HCINT: %08x\n", hcint.d32); - - /* Read HCCHAR */ - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); - - /* Clear HCINT */ - dwc_write_reg32(&hc_regs->hcint, hcint.d32); - - /* Clear HAINT */ - dwc_write_reg32(&hc_global_regs->haint, haint.d32); - - /* Clear GINTSTS */ - dwc_write_reg32(&global_regs->gintsts, gintsts.d32); - - /* Read GINTSTS */ - gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); - //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); -} - -static void do_in_ack(void) -{ - gintsts_data_t gintsts; - hctsiz_data_t hctsiz; - hcchar_data_t hcchar; - haint_data_t haint; - hcint_data_t hcint; - host_grxsts_data_t grxsts; - - /* Enable HAINTs */ - dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001); - - /* Enable HCINTs */ - dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3); - - /* Read GINTSTS */ - gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); - //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); - - /* Read HAINT */ - haint.d32 = dwc_read_reg32(&hc_global_regs->haint); - //fprintf(stderr, "HAINT: %08x\n", haint.d32); - - /* Read HCINT */ - hcint.d32 = dwc_read_reg32(&hc_regs->hcint); - //fprintf(stderr, "HCINT: %08x\n", hcint.d32); - - /* Read HCCHAR */ - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); - - /* Clear HCINT */ - dwc_write_reg32(&hc_regs->hcint, hcint.d32); - - /* Clear HAINT */ - dwc_write_reg32(&hc_global_regs->haint, haint.d32); - - /* Clear GINTSTS */ - dwc_write_reg32(&global_regs->gintsts, gintsts.d32); - - /* Read GINTSTS */ - gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); - //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); - - /* - * Receive Control In packet - */ - - /* Make sure channel is disabled */ - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - if (hcchar.b.chen) { - //fprintf(stderr, "Channel already enabled 2, HCCHAR = %08x\n", hcchar.d32); - hcchar.b.chdis = 1; - hcchar.b.chen = 1; - dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); - //sleep(1); - mdelay(1000); - - /* Read GINTSTS */ - gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); - //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); - - /* Read HAINT */ - haint.d32 = dwc_read_reg32(&hc_global_regs->haint); - //fprintf(stderr, "HAINT: %08x\n", haint.d32); - - /* Read HCINT */ - hcint.d32 = dwc_read_reg32(&hc_regs->hcint); - //fprintf(stderr, "HCINT: %08x\n", hcint.d32); - - /* Read HCCHAR */ - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); - - /* Clear HCINT */ - dwc_write_reg32(&hc_regs->hcint, hcint.d32); - - /* Clear HAINT */ - dwc_write_reg32(&hc_global_regs->haint, haint.d32); - - /* Clear GINTSTS */ - dwc_write_reg32(&global_regs->gintsts, gintsts.d32); - - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - //if (hcchar.b.chen) { - // fprintf(stderr, "** Channel _still_ enabled 2, HCCHAR = %08x **\n", hcchar.d32); - //} - } - - /* Set HCTSIZ */ - hctsiz.d32 = 0; - hctsiz.b.xfersize = 8; - hctsiz.b.pktcnt = 1; - hctsiz.b.pid = DWC_OTG_HC_PID_DATA1; - dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); - - /* Set HCCHAR */ - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; - hcchar.b.epdir = 1; - hcchar.b.epnum = 0; - hcchar.b.mps = 8; - hcchar.b.chen = 1; - dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); - - gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); - //fprintf(stderr, "Waiting for RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32); - - /* Wait for receive status queue interrupt */ - do { - gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); - } while (gintsts.b.rxstsqlvl == 0); - - //fprintf(stderr, "Got RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32); - - /* Read RXSTS */ - grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp); - //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32); - - /* Clear RXSTSQLVL in GINTSTS */ - gintsts.d32 = 0; - gintsts.b.rxstsqlvl = 1; - dwc_write_reg32(&global_regs->gintsts, gintsts.d32); - - switch (grxsts.b.pktsts) { - case DWC_GRXSTS_PKTSTS_IN: - /* Read the data into the host buffer */ - if (grxsts.b.bcnt > 0) { - int i; - int word_count = (grxsts.b.bcnt + 3) / 4; - - data_fifo = (uint32_t *)((char *)global_regs + 0x1000); - - for (i = 0; i < word_count; i++) { - (void)dwc_read_reg32(data_fifo++); - } - } - - //fprintf(stderr, "Received %u bytes\n", (unsigned)grxsts.b.bcnt); - break; - - default: - //fprintf(stderr, "** Unexpected GRXSTS packet status 1 **\n"); - break; - } - - gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); - //fprintf(stderr, "Waiting for RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32); - - /* Wait for receive status queue interrupt */ - do { - gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); - } while (gintsts.b.rxstsqlvl == 0); - - //fprintf(stderr, "Got RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32); - - /* Read RXSTS */ - grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp); - //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32); - - /* Clear RXSTSQLVL in GINTSTS */ - gintsts.d32 = 0; - gintsts.b.rxstsqlvl = 1; - dwc_write_reg32(&global_regs->gintsts, gintsts.d32); - - switch (grxsts.b.pktsts) { - case DWC_GRXSTS_PKTSTS_IN_XFER_COMP: - break; - - default: - //fprintf(stderr, "** Unexpected GRXSTS packet status 2 **\n"); - break; - } - - gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); - //fprintf(stderr, "Waiting for HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32); - - /* Wait for host channel interrupt */ - do { - gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); - } while (gintsts.b.hcintr == 0); - - //fprintf(stderr, "Got HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32); - - /* Read HAINT */ - haint.d32 = dwc_read_reg32(&hc_global_regs->haint); - //fprintf(stderr, "HAINT: %08x\n", haint.d32); - - /* Read HCINT */ - hcint.d32 = dwc_read_reg32(&hc_regs->hcint); - //fprintf(stderr, "HCINT: %08x\n", hcint.d32); - - /* Read HCCHAR */ - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); - - /* Clear HCINT */ - dwc_write_reg32(&hc_regs->hcint, hcint.d32); - - /* Clear HAINT */ - dwc_write_reg32(&hc_global_regs->haint, haint.d32); - - /* Clear GINTSTS */ - dwc_write_reg32(&global_regs->gintsts, gintsts.d32); - - /* Read GINTSTS */ - gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); - //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); - -// usleep(100000); -// mdelay(100); - mdelay(1); - - /* - * Send handshake packet - */ - - /* Read HAINT */ - haint.d32 = dwc_read_reg32(&hc_global_regs->haint); - //fprintf(stderr, "HAINT: %08x\n", haint.d32); - - /* Read HCINT */ - hcint.d32 = dwc_read_reg32(&hc_regs->hcint); - //fprintf(stderr, "HCINT: %08x\n", hcint.d32); - - /* Read HCCHAR */ - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); - - /* Clear HCINT */ - dwc_write_reg32(&hc_regs->hcint, hcint.d32); - - /* Clear HAINT */ - dwc_write_reg32(&hc_global_regs->haint, haint.d32); - - /* Clear GINTSTS */ - dwc_write_reg32(&global_regs->gintsts, gintsts.d32); - - /* Read GINTSTS */ - gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); - //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); - - /* Make sure channel is disabled */ - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - if (hcchar.b.chen) { - //fprintf(stderr, "Channel already enabled 3, HCCHAR = %08x\n", hcchar.d32); - hcchar.b.chdis = 1; - hcchar.b.chen = 1; - dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); - //sleep(1); - mdelay(1000); - - /* Read GINTSTS */ - gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); - //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); - - /* Read HAINT */ - haint.d32 = dwc_read_reg32(&hc_global_regs->haint); - //fprintf(stderr, "HAINT: %08x\n", haint.d32); - - /* Read HCINT */ - hcint.d32 = dwc_read_reg32(&hc_regs->hcint); - //fprintf(stderr, "HCINT: %08x\n", hcint.d32); - - /* Read HCCHAR */ - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); - - /* Clear HCINT */ - dwc_write_reg32(&hc_regs->hcint, hcint.d32); - - /* Clear HAINT */ - dwc_write_reg32(&hc_global_regs->haint, haint.d32); - - /* Clear GINTSTS */ - dwc_write_reg32(&global_regs->gintsts, gintsts.d32); - - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - //if (hcchar.b.chen) { - // fprintf(stderr, "** Channel _still_ enabled 3, HCCHAR = %08x **\n", hcchar.d32); - //} - } - - /* Set HCTSIZ */ - hctsiz.d32 = 0; - hctsiz.b.xfersize = 0; - hctsiz.b.pktcnt = 1; - hctsiz.b.pid = DWC_OTG_HC_PID_DATA1; - dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); - - /* Set HCCHAR */ - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; - hcchar.b.epdir = 0; - hcchar.b.epnum = 0; - hcchar.b.mps = 8; - hcchar.b.chen = 1; - dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); - - gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); - //fprintf(stderr, "Waiting for HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32); - - /* Wait for host channel interrupt */ - do { - gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); - } while (gintsts.b.hcintr == 0); - - //fprintf(stderr, "Got HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32); - - /* Disable HCINTs */ - dwc_write_reg32(&hc_regs->hcintmsk, 0x0000); - - /* Disable HAINTs */ - dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000); - - /* Read HAINT */ - haint.d32 = dwc_read_reg32(&hc_global_regs->haint); - //fprintf(stderr, "HAINT: %08x\n", haint.d32); - - /* Read HCINT */ - hcint.d32 = dwc_read_reg32(&hc_regs->hcint); - //fprintf(stderr, "HCINT: %08x\n", hcint.d32); - - /* Read HCCHAR */ - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); - - /* Clear HCINT */ - dwc_write_reg32(&hc_regs->hcint, hcint.d32); - - /* Clear HAINT */ - dwc_write_reg32(&hc_global_regs->haint, haint.d32); - - /* Clear GINTSTS */ - dwc_write_reg32(&global_regs->gintsts, gintsts.d32); - - /* Read GINTSTS */ - gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); - //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); -} -#endif /* DWC_HS_ELECT_TST */ - -/** Handles hub class-specific requests. */ -int dwc_otg_hcd_hub_control(struct usb_hcd *hcd, - u16 typeReq, - u16 wValue, - u16 wIndex, - char *buf, - u16 wLength) -{ - int retval = 0; - - dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); - dwc_otg_core_if_t *core_if = hcd_to_dwc_otg_hcd(hcd)->core_if; - struct usb_hub_descriptor *desc; - hprt0_data_t hprt0 = {.d32 = 0}; - - uint32_t port_status; - - switch (typeReq) { - case ClearHubFeature: - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " - "ClearHubFeature 0x%x\n", wValue); - switch (wValue) { - case C_HUB_LOCAL_POWER: - case C_HUB_OVER_CURRENT: - /* Nothing required here */ - break; - default: - retval = -EINVAL; - DWC_ERROR("DWC OTG HCD - " - "ClearHubFeature request %xh unknown\n", wValue); - } - break; - case ClearPortFeature: - if (!wIndex || wIndex > 1) - goto error; - - switch (wValue) { - case USB_PORT_FEAT_ENABLE: - DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - " - "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); - hprt0.d32 = dwc_otg_read_hprt0(core_if); - hprt0.b.prtena = 1; - dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); - break; - case USB_PORT_FEAT_SUSPEND: - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " - "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); - hprt0.d32 = dwc_otg_read_hprt0(core_if); - hprt0.b.prtres = 1; - dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); - /* Clear Resume bit */ - mdelay(100); - hprt0.b.prtres = 0; - dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); - break; - case USB_PORT_FEAT_POWER: - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " - "ClearPortFeature USB_PORT_FEAT_POWER\n"); - hprt0.d32 = dwc_otg_read_hprt0(core_if); - hprt0.b.prtpwr = 0; - dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); - break; - case USB_PORT_FEAT_INDICATOR: - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " - "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); - /* Port inidicator not supported */ - break; - case USB_PORT_FEAT_C_CONNECTION: - /* Clears drivers internal connect status change - * flag */ - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " - "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); - dwc_otg_hcd->flags.b.port_connect_status_change = 0; - break; - case USB_PORT_FEAT_C_RESET: - /* Clears the driver's internal Port Reset Change - * flag */ - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " - "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); - dwc_otg_hcd->flags.b.port_reset_change = 0; - break; - case USB_PORT_FEAT_C_ENABLE: - /* Clears the driver's internal Port - * Enable/Disable Change flag */ - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " - "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); - dwc_otg_hcd->flags.b.port_enable_change = 0; - break; - case USB_PORT_FEAT_C_SUSPEND: - /* Clears the driver's internal Port Suspend - * Change flag, which is set when resume signaling on - * the host port is complete */ - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " - "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); - dwc_otg_hcd->flags.b.port_suspend_change = 0; - break; - case USB_PORT_FEAT_C_OVER_CURRENT: - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " - "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); - dwc_otg_hcd->flags.b.port_over_current_change = 0; - break; - default: - retval = -EINVAL; - DWC_ERROR("DWC OTG HCD - " - "ClearPortFeature request %xh " - "unknown or unsupported\n", wValue); - } - break; - case GetHubDescriptor: - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " - "GetHubDescriptor\n"); - desc = (struct usb_hub_descriptor *)buf; - desc->bDescLength = 9; - desc->bDescriptorType = 0x29; - desc->bNbrPorts = 1; - desc->wHubCharacteristics = 0x08; - desc->bPwrOn2PwrGood = 1; - desc->bHubContrCurrent = 0; -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,39) - desc->u.hs.DeviceRemovable[0] = 0; - desc->u.hs.DeviceRemovable[1] = 0xff; -#endif - break; - case GetHubStatus: - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " - "GetHubStatus\n"); - memset(buf, 0, 4); - break; - case GetPortStatus: - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " - "GetPortStatus\n"); - - if (!wIndex || wIndex > 1) - goto error; - - port_status = 0; - - if (dwc_otg_hcd->flags.b.port_connect_status_change) - port_status |= (1 << USB_PORT_FEAT_C_CONNECTION); - - if (dwc_otg_hcd->flags.b.port_enable_change) - port_status |= (1 << USB_PORT_FEAT_C_ENABLE); - - if (dwc_otg_hcd->flags.b.port_suspend_change) - port_status |= (1 << USB_PORT_FEAT_C_SUSPEND); - - if (dwc_otg_hcd->flags.b.port_reset_change) - port_status |= (1 << USB_PORT_FEAT_C_RESET); - - if (dwc_otg_hcd->flags.b.port_over_current_change) { - DWC_ERROR("Device Not Supported\n"); - port_status |= (1 << USB_PORT_FEAT_C_OVER_CURRENT); - } - - if (!dwc_otg_hcd->flags.b.port_connect_status) { - /* - * The port is disconnected, which means the core is - * either in device mode or it soon will be. Just - * return 0's for the remainder of the port status - * since the port register can't be read if the core - * is in device mode. - */ - *((__le32 *) buf) = cpu_to_le32(port_status); - break; - } - - hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0); - DWC_DEBUGPL(DBG_HCDV, " HPRT0: 0x%08x\n", hprt0.d32); - - if (hprt0.b.prtconnsts) - port_status |= (1 << USB_PORT_FEAT_CONNECTION); - - if (hprt0.b.prtena) - port_status |= (1 << USB_PORT_FEAT_ENABLE); - - if (hprt0.b.prtsusp) - port_status |= (1 << USB_PORT_FEAT_SUSPEND); - - if (hprt0.b.prtovrcurract) - port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT); - - if (hprt0.b.prtrst) - port_status |= (1 << USB_PORT_FEAT_RESET); - - if (hprt0.b.prtpwr) - port_status |= (1 << USB_PORT_FEAT_POWER); - - if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) - port_status |= USB_PORT_STAT_HIGH_SPEED; - else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED) - port_status |= USB_PORT_STAT_LOW_SPEED; - - if (hprt0.b.prttstctl) - port_status |= (1 << USB_PORT_FEAT_TEST); - - /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ - - *((__le32 *) buf) = cpu_to_le32(port_status); - - break; - case SetHubFeature: - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " - "SetHubFeature\n"); - /* No HUB features supported */ - break; - case SetPortFeature: - if (wValue != USB_PORT_FEAT_TEST && (!wIndex || wIndex > 1)) - goto error; - - if (!dwc_otg_hcd->flags.b.port_connect_status) { - /* - * The port is disconnected, which means the core is - * either in device mode or it soon will be. Just - * return without doing anything since the port - * register can't be written if the core is in device - * mode. - */ - break; - } - - switch (wValue) { - case USB_PORT_FEAT_SUSPEND: - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " - "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); - if (hcd->self.otg_port == wIndex && - hcd->self.b_hnp_enable) { - gotgctl_data_t gotgctl = {.d32=0}; - gotgctl.b.hstsethnpen = 1; - dwc_modify_reg32(&core_if->core_global_regs->gotgctl, - 0, gotgctl.d32); - core_if->op_state = A_SUSPEND; - } - hprt0.d32 = dwc_otg_read_hprt0(core_if); - hprt0.b.prtsusp = 1; - dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); - //DWC_PRINT("SUSPEND: HPRT0=%0x\n", hprt0.d32); - /* Suspend the Phy Clock */ - { - pcgcctl_data_t pcgcctl = {.d32=0}; - pcgcctl.b.stoppclk = 1; - dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32); - } - - /* For HNP the bus must be suspended for at least 200ms. */ - if (hcd->self.b_hnp_enable) { - mdelay(200); - //DWC_PRINT("SUSPEND: wait complete! (%d)\n", _hcd->state); - } - break; - case USB_PORT_FEAT_POWER: - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " - "SetPortFeature - USB_PORT_FEAT_POWER\n"); - hprt0.d32 = dwc_otg_read_hprt0(core_if); - hprt0.b.prtpwr = 1; - dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); - break; - case USB_PORT_FEAT_RESET: - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " - "SetPortFeature - USB_PORT_FEAT_RESET\n"); - hprt0.d32 = dwc_otg_read_hprt0(core_if); - /* When B-Host the Port reset bit is set in - * the Start HCD Callback function, so that - * the reset is started within 1ms of the HNP - * success interrupt. */ - if (!hcd->self.is_b_host) { - hprt0.b.prtrst = 1; - dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); - } - /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ - MDELAY(60); - hprt0.b.prtrst = 0; - dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); - break; - -#ifdef DWC_HS_ELECT_TST - case USB_PORT_FEAT_TEST: - { - uint32_t t; - gintmsk_data_t gintmsk; - - t = (wIndex >> 8); /* MSB wIndex USB */ - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " - "SetPortFeature - USB_PORT_FEAT_TEST %d\n", t); - warn("USB_PORT_FEAT_TEST %d\n", t); - if (t < 6) { - hprt0.d32 = dwc_otg_read_hprt0(core_if); - hprt0.b.prttstctl = t; - dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); - } else { - /* Setup global vars with reg addresses (quick and - * dirty hack, should be cleaned up) - */ - global_regs = core_if->core_global_regs; - hc_global_regs = core_if->host_if->host_global_regs; - hc_regs = (dwc_otg_hc_regs_t *)((char *)global_regs + 0x500); - data_fifo = (uint32_t *)((char *)global_regs + 0x1000); - - if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */ - /* Save current interrupt mask */ - gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk); - - /* Disable all interrupts while we muck with - * the hardware directly - */ - dwc_write_reg32(&global_regs->gintmsk, 0); - - /* 15 second delay per the test spec */ - mdelay(15000); - - /* Drive suspend on the root port */ - hprt0.d32 = dwc_otg_read_hprt0(core_if); - hprt0.b.prtsusp = 1; - hprt0.b.prtres = 0; - dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); - - /* 15 second delay per the test spec */ - mdelay(15000); - - /* Drive resume on the root port */ - hprt0.d32 = dwc_otg_read_hprt0(core_if); - hprt0.b.prtsusp = 0; - hprt0.b.prtres = 1; - dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); - mdelay(100); - - /* Clear the resume bit */ - hprt0.b.prtres = 0; - dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); - - /* Restore interrupts */ - dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32); - } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */ - /* Save current interrupt mask */ - gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk); - - /* Disable all interrupts while we muck with - * the hardware directly - */ - dwc_write_reg32(&global_regs->gintmsk, 0); - - /* 15 second delay per the test spec */ - mdelay(15000); - - /* Send the Setup packet */ - do_setup(); - - /* 15 second delay so nothing else happens for awhile */ - mdelay(15000); - - /* Restore interrupts */ - dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32); - } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */ - /* Save current interrupt mask */ - gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk); - - /* Disable all interrupts while we muck with - * the hardware directly - */ - dwc_write_reg32(&global_regs->gintmsk, 0); - - /* Send the Setup packet */ - do_setup(); - - /* 15 second delay so nothing else happens for awhile */ - mdelay(15000); - - /* Send the In and Ack packets */ - do_in_ack(); - - /* 15 second delay so nothing else happens for awhile */ - mdelay(15000); - - /* Restore interrupts */ - dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32); - } - } - break; - } -#endif /* DWC_HS_ELECT_TST */ - - case USB_PORT_FEAT_INDICATOR: - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " - "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); - /* Not supported */ - break; - default: - retval = -EINVAL; - DWC_ERROR("DWC OTG HCD - " - "SetPortFeature request %xh " - "unknown or unsupported\n", wValue); - break; - } - break; - default: - error: - retval = -EINVAL; - DWC_WARN("DWC OTG HCD - " - "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n", - typeReq, wIndex, wValue); - break; - } - - return retval; -} - -/** - * Assigns transactions from a QTD to a free host channel and initializes the - * host channel to perform the transactions. The host channel is removed from - * the free list. - * - * @param hcd The HCD state structure. - * @param qh Transactions from the first QTD for this QH are selected and - * assigned to a free host channel. - */ -static void assign_and_init_hc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) -{ - dwc_hc_t *hc; - dwc_otg_qtd_t *qtd; - struct urb *urb; - - DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, hcd, qh); - - hc = list_entry(hcd->free_hc_list.next, dwc_hc_t, hc_list_entry); - - /* Remove the host channel from the free list. */ - list_del_init(&hc->hc_list_entry); - - qtd = list_entry(qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); - urb = qtd->urb; - qh->channel = hc; - qh->qtd_in_process = qtd; - - /* - * Use usb_pipedevice to determine device address. This address is - * 0 before the SET_ADDRESS command and the correct address afterward. - */ - hc->dev_addr = usb_pipedevice(urb->pipe); - hc->ep_num = usb_pipeendpoint(urb->pipe); - - if (urb->dev->speed == USB_SPEED_LOW) { - hc->speed = DWC_OTG_EP_SPEED_LOW; - } else if (urb->dev->speed == USB_SPEED_FULL) { - hc->speed = DWC_OTG_EP_SPEED_FULL; - } else { - hc->speed = DWC_OTG_EP_SPEED_HIGH; - } - - hc->max_packet = dwc_max_packet(qh->maxp); - - hc->xfer_started = 0; - hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS; - hc->error_state = (qtd->error_count > 0); - hc->halt_on_queue = 0; - hc->halt_pending = 0; - hc->requests = 0; - - /* - * The following values may be modified in the transfer type section - * below. The xfer_len value may be reduced when the transfer is - * started to accommodate the max widths of the XferSize and PktCnt - * fields in the HCTSIZn register. - */ - hc->do_ping = qh->ping_state; - hc->ep_is_in = (usb_pipein(urb->pipe) != 0); - hc->data_pid_start = qh->data_toggle; - hc->multi_count = 1; - - if (hcd->core_if->dma_enable) { - hc->xfer_buff = (uint8_t *)urb->transfer_dma + urb->actual_length; - } else { - hc->xfer_buff = (uint8_t *)urb->transfer_buffer + urb->actual_length; - } - hc->xfer_len = urb->transfer_buffer_length - urb->actual_length; - hc->xfer_count = 0; - - /* - * Set the split attributes - */ - hc->do_split = 0; - if (qh->do_split) { - hc->do_split = 1; - hc->xact_pos = qtd->isoc_split_pos; - hc->complete_split = qtd->complete_split; - hc->hub_addr = urb->dev->tt->hub->devnum; - hc->port_addr = urb->dev->ttport; - } - - switch (usb_pipetype(urb->pipe)) { - case PIPE_CONTROL: - hc->ep_type = DWC_OTG_EP_TYPE_CONTROL; - switch (qtd->control_phase) { - case DWC_OTG_CONTROL_SETUP: - DWC_DEBUGPL(DBG_HCDV, " Control setup transaction\n"); - hc->do_ping = 0; - hc->ep_is_in = 0; - hc->data_pid_start = DWC_OTG_HC_PID_SETUP; - if (hcd->core_if->dma_enable) { - hc->xfer_buff = (uint8_t *)urb->setup_dma; - } else { - hc->xfer_buff = (uint8_t *)urb->setup_packet; - } - hc->xfer_len = 8; - break; - case DWC_OTG_CONTROL_DATA: - DWC_DEBUGPL(DBG_HCDV, " Control data transaction\n"); - hc->data_pid_start = qtd->data_toggle; - break; - case DWC_OTG_CONTROL_STATUS: - /* - * Direction is opposite of data direction or IN if no - * data. - */ - DWC_DEBUGPL(DBG_HCDV, " Control status transaction\n"); - if (urb->transfer_buffer_length == 0) { - hc->ep_is_in = 1; - } else { - hc->ep_is_in = (usb_pipein(urb->pipe) != USB_DIR_IN); - } - if (hc->ep_is_in) { - hc->do_ping = 0; - } - hc->data_pid_start = DWC_OTG_HC_PID_DATA1; - hc->xfer_len = 0; - if (hcd->core_if->dma_enable) { - hc->xfer_buff = (uint8_t *)hcd->status_buf_dma; - } else { - hc->xfer_buff = (uint8_t *)hcd->status_buf; - } - break; - } - break; - case PIPE_BULK: - hc->ep_type = DWC_OTG_EP_TYPE_BULK; - break; - case PIPE_INTERRUPT: - hc->ep_type = DWC_OTG_EP_TYPE_INTR; - break; - case PIPE_ISOCHRONOUS: - { - struct usb_iso_packet_descriptor *frame_desc; - frame_desc = &urb->iso_frame_desc[qtd->isoc_frame_index]; - hc->ep_type = DWC_OTG_EP_TYPE_ISOC; - if (hcd->core_if->dma_enable) { - hc->xfer_buff = (uint8_t *)urb->transfer_dma; - } else { - hc->xfer_buff = (uint8_t *)urb->transfer_buffer; - } - hc->xfer_buff += frame_desc->offset + qtd->isoc_split_offset; - hc->xfer_len = frame_desc->length - qtd->isoc_split_offset; - - if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) { - if (hc->xfer_len <= 188) { - hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL; - } - else { - hc->xact_pos = DWC_HCSPLIT_XACTPOS_BEGIN; - } - } - } - break; - } - - if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || - hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { - /* - * This value may be modified when the transfer is started to - * reflect the actual transfer length. - */ - hc->multi_count = dwc_hb_mult(qh->maxp); - } - - dwc_otg_hc_init(hcd->core_if, hc); - hc->qh = qh; -} - -/** - * This function selects transactions from the HCD transfer schedule and - * assigns them to available host channels. It is called from HCD interrupt - * handler functions. - * - * @param hcd The HCD state structure. - * - * @return The types of new transactions that were assigned to host channels. - */ -dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *hcd) -{ - struct list_head *qh_ptr; - dwc_otg_qh_t *qh; - int num_channels; - dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE; - -#ifdef DEBUG_SOF - DWC_DEBUGPL(DBG_HCD, " Select Transactions\n"); -#endif - - /* Process entries in the periodic ready list. */ - qh_ptr = hcd->periodic_sched_ready.next; - while (qh_ptr != &hcd->periodic_sched_ready && - !list_empty(&hcd->free_hc_list)) { - - qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry); - assign_and_init_hc(hcd, qh); - - /* - * Move the QH from the periodic ready schedule to the - * periodic assigned schedule. - */ - qh_ptr = qh_ptr->next; - list_move(&qh->qh_list_entry, &hcd->periodic_sched_assigned); - - ret_val = DWC_OTG_TRANSACTION_PERIODIC; - } - - /* - * Process entries in the inactive portion of the non-periodic - * schedule. Some free host channels may not be used if they are - * reserved for periodic transfers. - */ - qh_ptr = hcd->non_periodic_sched_inactive.next; - num_channels = hcd->core_if->core_params->host_channels; - while (qh_ptr != &hcd->non_periodic_sched_inactive && - (hcd->non_periodic_channels < - num_channels - hcd->periodic_channels) && - !list_empty(&hcd->free_hc_list)) { - - qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry); - assign_and_init_hc(hcd, qh); - - /* - * Move the QH from the non-periodic inactive schedule to the - * non-periodic active schedule. - */ - qh_ptr = qh_ptr->next; - list_move(&qh->qh_list_entry, &hcd->non_periodic_sched_active); - - if (ret_val == DWC_OTG_TRANSACTION_NONE) { - ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC; - } else { - ret_val = DWC_OTG_TRANSACTION_ALL; - } - - hcd->non_periodic_channels++; - } - - return ret_val; -} - -/** - * Attempts to queue a single transaction request for a host channel - * associated with either a periodic or non-periodic transfer. This function - * assumes that there is space available in the appropriate request queue. For - * an OUT transfer or SETUP transaction in Slave mode, it checks whether space - * is available in the appropriate Tx FIFO. - * - * @param hcd The HCD state structure. - * @param hc Host channel descriptor associated with either a periodic or - * non-periodic transfer. - * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx - * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic - * transfers. - * - * @return 1 if a request is queued and more requests may be needed to - * complete the transfer, 0 if no more requests are required for this - * transfer, -1 if there is insufficient space in the Tx FIFO. - */ -static int queue_transaction(dwc_otg_hcd_t *hcd, - dwc_hc_t *hc, - uint16_t fifo_dwords_avail) -{ - int retval; - - if (hcd->core_if->dma_enable) { - if (!hc->xfer_started) { - dwc_otg_hc_start_transfer(hcd->core_if, hc); - hc->qh->ping_state = 0; - } - retval = 0; - } else if (hc->halt_pending) { - /* Don't queue a request if the channel has been halted. */ - retval = 0; - } else if (hc->halt_on_queue) { - dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status); - retval = 0; - } else if (hc->do_ping) { - if (!hc->xfer_started) { - dwc_otg_hc_start_transfer(hcd->core_if, hc); - } - retval = 0; - } else if (!hc->ep_is_in || - hc->data_pid_start == DWC_OTG_HC_PID_SETUP) { - if ((fifo_dwords_avail * 4) >= hc->max_packet) { - if (!hc->xfer_started) { - dwc_otg_hc_start_transfer(hcd->core_if, hc); - retval = 1; - } else { - retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc); - } - } else { - retval = -1; - } - } else { - if (!hc->xfer_started) { - dwc_otg_hc_start_transfer(hcd->core_if, hc); - retval = 1; - } else { - retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc); - } - } - - return retval; -} - -/** - * Processes active non-periodic channels and queues transactions for these - * channels to the DWC_otg controller. After queueing transactions, the NP Tx - * FIFO Empty interrupt is enabled if there are more transactions to queue as - * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx - * FIFO Empty interrupt is disabled. - */ -static void process_non_periodic_channels(dwc_otg_hcd_t *hcd) -{ - gnptxsts_data_t tx_status; - struct list_head *orig_qh_ptr; - dwc_otg_qh_t *qh; - int status; - int no_queue_space = 0; - int no_fifo_space = 0; - int more_to_do = 0; - - dwc_otg_core_global_regs_t *global_regs = hcd->core_if->core_global_regs; - - DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n"); -#ifdef DEBUG - tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts); - DWC_DEBUGPL(DBG_HCDV, " NP Tx Req Queue Space Avail (before queue): %d\n", - tx_status.b.nptxqspcavail); - DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (before queue): %d\n", - tx_status.b.nptxfspcavail); -#endif - /* - * Keep track of the starting point. Skip over the start-of-list - * entry. - */ - if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) { - hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next; - } - orig_qh_ptr = hcd->non_periodic_qh_ptr; - - /* - * Process once through the active list or until no more space is - * available in the request queue or the Tx FIFO. - */ - do { - tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts); - if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) { - no_queue_space = 1; - break; - } - - qh = list_entry(hcd->non_periodic_qh_ptr, dwc_otg_qh_t, qh_list_entry); - status = queue_transaction(hcd, qh->channel, tx_status.b.nptxfspcavail); - - if (status > 0) { - more_to_do = 1; - } else if (status < 0) { - no_fifo_space = 1; - break; - } - - /* Advance to next QH, skipping start-of-list entry. */ - hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next; - if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) { - hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next; - } - - } while (hcd->non_periodic_qh_ptr != orig_qh_ptr); - - if (!hcd->core_if->dma_enable) { - gintmsk_data_t intr_mask = {.d32 = 0}; - intr_mask.b.nptxfempty = 1; - -#ifdef DEBUG - tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts); - DWC_DEBUGPL(DBG_HCDV, " NP Tx Req Queue Space Avail (after queue): %d\n", - tx_status.b.nptxqspcavail); - DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (after queue): %d\n", - tx_status.b.nptxfspcavail); -#endif - if (more_to_do || no_queue_space || no_fifo_space) { - /* - * May need to queue more transactions as the request - * queue or Tx FIFO empties. Enable the non-periodic - * Tx FIFO empty interrupt. (Always use the half-empty - * level to ensure that new requests are loaded as - * soon as possible.) - */ - dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32); - } else { - /* - * Disable the Tx FIFO empty interrupt since there are - * no more transactions that need to be queued right - * now. This function is called from interrupt - * handlers to queue more transactions as transfer - * states change. - */ - dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0); - } - } -} - -/** - * Processes periodic channels for the next frame and queues transactions for - * these channels to the DWC_otg controller. After queueing transactions, the - * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions - * to queue as Periodic Tx FIFO or request queue space becomes available. - * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. - */ -static void process_periodic_channels(dwc_otg_hcd_t *hcd) -{ - hptxsts_data_t tx_status; - struct list_head *qh_ptr; - dwc_otg_qh_t *qh; - int status; - int no_queue_space = 0; - int no_fifo_space = 0; - - dwc_otg_host_global_regs_t *host_regs; - host_regs = hcd->core_if->host_if->host_global_regs; - - DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n"); -#ifdef DEBUG - tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts); - DWC_DEBUGPL(DBG_HCDV, " P Tx Req Queue Space Avail (before queue): %d\n", - tx_status.b.ptxqspcavail); - DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (before queue): %d\n", - tx_status.b.ptxfspcavail); -#endif - - qh_ptr = hcd->periodic_sched_assigned.next; - while (qh_ptr != &hcd->periodic_sched_assigned) { - tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts); - if (tx_status.b.ptxqspcavail == 0) { - no_queue_space = 1; - break; - } - - qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry); - - /* - * Set a flag if we're queuing high-bandwidth in slave mode. - * The flag prevents any halts to get into the request queue in - * the middle of multiple high-bandwidth packets getting queued. - */ - if (!hcd->core_if->dma_enable && - qh->channel->multi_count > 1) - { - hcd->core_if->queuing_high_bandwidth = 1; - } - - status = queue_transaction(hcd, qh->channel, tx_status.b.ptxfspcavail); - if (status < 0) { - no_fifo_space = 1; - break; - } - - /* - * In Slave mode, stay on the current transfer until there is - * nothing more to do or the high-bandwidth request count is - * reached. In DMA mode, only need to queue one request. The - * controller automatically handles multiple packets for - * high-bandwidth transfers. - */ - if (hcd->core_if->dma_enable || status == 0 || - qh->channel->requests == qh->channel->multi_count) { - qh_ptr = qh_ptr->next; - /* - * Move the QH from the periodic assigned schedule to - * the periodic queued schedule. - */ - list_move(&qh->qh_list_entry, &hcd->periodic_sched_queued); - - /* done queuing high bandwidth */ - hcd->core_if->queuing_high_bandwidth = 0; - } - } - - if (!hcd->core_if->dma_enable) { - dwc_otg_core_global_regs_t *global_regs; - gintmsk_data_t intr_mask = {.d32 = 0}; - - global_regs = hcd->core_if->core_global_regs; - intr_mask.b.ptxfempty = 1; -#ifdef DEBUG - tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts); - DWC_DEBUGPL(DBG_HCDV, " P Tx Req Queue Space Avail (after queue): %d\n", - tx_status.b.ptxqspcavail); - DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (after queue): %d\n", - tx_status.b.ptxfspcavail); -#endif - if (!list_empty(&hcd->periodic_sched_assigned) || - no_queue_space || no_fifo_space) { - /* - * May need to queue more transactions as the request - * queue or Tx FIFO empties. Enable the periodic Tx - * FIFO empty interrupt. (Always use the half-empty - * level to ensure that new requests are loaded as - * soon as possible.) - */ - dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32); - } else { - /* - * Disable the Tx FIFO empty interrupt since there are - * no more transactions that need to be queued right - * now. This function is called from interrupt - * handlers to queue more transactions as transfer - * states change. - */ - dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0); - } - } -} - -/** - * This function processes the currently active host channels and queues - * transactions for these channels to the DWC_otg controller. It is called - * from HCD interrupt handler functions. - * - * @param hcd The HCD state structure. - * @param tr_type The type(s) of transactions to queue (non-periodic, - * periodic, or both). - */ -void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *hcd, - dwc_otg_transaction_type_e tr_type) -{ -#ifdef DEBUG_SOF - DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n"); -#endif - /* Process host channels associated with periodic transfers. */ - if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC || - tr_type == DWC_OTG_TRANSACTION_ALL) && - !list_empty(&hcd->periodic_sched_assigned)) { - - process_periodic_channels(hcd); - } - - /* Process host channels associated with non-periodic transfers. */ - if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC || - tr_type == DWC_OTG_TRANSACTION_ALL) { - if (!list_empty(&hcd->non_periodic_sched_active)) { - process_non_periodic_channels(hcd); - } else { - /* - * Ensure NP Tx FIFO empty interrupt is disabled when - * there are no non-periodic transfers to process. - */ - gintmsk_data_t gintmsk = {.d32 = 0}; - gintmsk.b.nptxfempty = 1; - dwc_modify_reg32(&hcd->core_if->core_global_regs->gintmsk, - gintmsk.d32, 0); - } - } -} - -/** - * Sets the final status of an URB and returns it to the device driver. Any - * required cleanup of the URB is performed. - */ -void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t *hcd, struct urb *urb, int status) -{ -#ifdef DEBUG - if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { - DWC_PRINT("%s: urb %p, device %d, ep %d %s, status=%d\n", - __func__, urb, usb_pipedevice(urb->pipe), - usb_pipeendpoint(urb->pipe), - usb_pipein(urb->pipe) ? "IN" : "OUT", status); - if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { - int i; - for (i = 0; i < urb->number_of_packets; i++) { - DWC_PRINT(" ISO Desc %d status: %d\n", - i, urb->iso_frame_desc[i].status); - } - } - } -#endif - - urb->status = status; - urb->hcpriv = NULL; -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) - usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb, status); -#else - usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb, NULL); -#endif -} - -/* - * Returns the Queue Head for an URB. - */ -dwc_otg_qh_t *dwc_urb_to_qh(struct urb *urb) -{ - struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb); - return (dwc_otg_qh_t *)ep->hcpriv; -} - -#ifdef DEBUG -void dwc_print_setup_data(uint8_t *setup) -{ - int i; - if (CHK_DEBUG_LEVEL(DBG_HCD)){ - DWC_PRINT("Setup Data = MSB "); - for (i = 7; i >= 0; i--) DWC_PRINT("%02x ", setup[i]); - DWC_PRINT("\n"); - DWC_PRINT(" bmRequestType Tranfer = %s\n", (setup[0] & 0x80) ? "Device-to-Host" : "Host-to-Device"); - DWC_PRINT(" bmRequestType Type = "); - switch ((setup[0] & 0x60) >> 5) { - case 0: DWC_PRINT("Standard\n"); break; - case 1: DWC_PRINT("Class\n"); break; - case 2: DWC_PRINT("Vendor\n"); break; - case 3: DWC_PRINT("Reserved\n"); break; - } - DWC_PRINT(" bmRequestType Recipient = "); - switch (setup[0] & 0x1f) { - case 0: DWC_PRINT("Device\n"); break; - case 1: DWC_PRINT("Interface\n"); break; - case 2: DWC_PRINT("Endpoint\n"); break; - case 3: DWC_PRINT("Other\n"); break; - default: DWC_PRINT("Reserved\n"); break; - } - DWC_PRINT(" bRequest = 0x%0x\n", setup[1]); - DWC_PRINT(" wValue = 0x%0x\n", *((uint16_t *)&setup[2])); - DWC_PRINT(" wIndex = 0x%0x\n", *((uint16_t *)&setup[4])); - DWC_PRINT(" wLength = 0x%0x\n\n", *((uint16_t *)&setup[6])); - } -} -#endif - -void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *hcd) { -#if defined(DEBUG) && LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) - DWC_PRINT("Frame remaining at SOF:\n"); - DWC_PRINT(" samples %u, accum %llu, avg %llu\n", - hcd->frrem_samples, hcd->frrem_accum, - (hcd->frrem_samples > 0) ? - hcd->frrem_accum/hcd->frrem_samples : 0); - - DWC_PRINT("\n"); - DWC_PRINT("Frame remaining at start_transfer (uframe 7):\n"); - DWC_PRINT(" samples %u, accum %llu, avg %llu\n", - hcd->core_if->hfnum_7_samples, hcd->core_if->hfnum_7_frrem_accum, - (hcd->core_if->hfnum_7_samples > 0) ? - hcd->core_if->hfnum_7_frrem_accum/hcd->core_if->hfnum_7_samples : 0); - DWC_PRINT("Frame remaining at start_transfer (uframe 0):\n"); - DWC_PRINT(" samples %u, accum %llu, avg %llu\n", - hcd->core_if->hfnum_0_samples, hcd->core_if->hfnum_0_frrem_accum, - (hcd->core_if->hfnum_0_samples > 0) ? - hcd->core_if->hfnum_0_frrem_accum/hcd->core_if->hfnum_0_samples : 0); - DWC_PRINT("Frame remaining at start_transfer (uframe 1-6):\n"); - DWC_PRINT(" samples %u, accum %llu, avg %llu\n", - hcd->core_if->hfnum_other_samples, hcd->core_if->hfnum_other_frrem_accum, - (hcd->core_if->hfnum_other_samples > 0) ? - hcd->core_if->hfnum_other_frrem_accum/hcd->core_if->hfnum_other_samples : 0); - - DWC_PRINT("\n"); - DWC_PRINT("Frame remaining at sample point A (uframe 7):\n"); - DWC_PRINT(" samples %u, accum %llu, avg %llu\n", - hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a, - (hcd->hfnum_7_samples_a > 0) ? - hcd->hfnum_7_frrem_accum_a/hcd->hfnum_7_samples_a : 0); - DWC_PRINT("Frame remaining at sample point A (uframe 0):\n"); - DWC_PRINT(" samples %u, accum %llu, avg %llu\n", - hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a, - (hcd->hfnum_0_samples_a > 0) ? - hcd->hfnum_0_frrem_accum_a/hcd->hfnum_0_samples_a : 0); - DWC_PRINT("Frame remaining at sample point A (uframe 1-6):\n"); - DWC_PRINT(" samples %u, accum %llu, avg %llu\n", - hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a, - (hcd->hfnum_other_samples_a > 0) ? - hcd->hfnum_other_frrem_accum_a/hcd->hfnum_other_samples_a : 0); - - DWC_PRINT("\n"); - DWC_PRINT("Frame remaining at sample point B (uframe 7):\n"); - DWC_PRINT(" samples %u, accum %llu, avg %llu\n", - hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b, - (hcd->hfnum_7_samples_b > 0) ? - hcd->hfnum_7_frrem_accum_b/hcd->hfnum_7_samples_b : 0); - DWC_PRINT("Frame remaining at sample point B (uframe 0):\n"); - DWC_PRINT(" samples %u, accum %llu, avg %llu\n", - hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b, - (hcd->hfnum_0_samples_b > 0) ? - hcd->hfnum_0_frrem_accum_b/hcd->hfnum_0_samples_b : 0); - DWC_PRINT("Frame remaining at sample point B (uframe 1-6):\n"); - DWC_PRINT(" samples %u, accum %llu, avg %llu\n", - hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b, - (hcd->hfnum_other_samples_b > 0) ? - hcd->hfnum_other_frrem_accum_b/hcd->hfnum_other_samples_b : 0); -#endif -} - -void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *hcd) -{ -#ifdef DEBUG - int num_channels; - int i; - gnptxsts_data_t np_tx_status; - hptxsts_data_t p_tx_status; - - num_channels = hcd->core_if->core_params->host_channels; - DWC_PRINT("\n"); - DWC_PRINT("************************************************************\n"); - DWC_PRINT("HCD State:\n"); - DWC_PRINT(" Num channels: %d\n", num_channels); - for (i = 0; i < num_channels; i++) { - dwc_hc_t *hc = hcd->hc_ptr_array[i]; - DWC_PRINT(" Channel %d:\n", i); - DWC_PRINT(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n", - hc->dev_addr, hc->ep_num, hc->ep_is_in); - DWC_PRINT(" speed: %d\n", hc->speed); - DWC_PRINT(" ep_type: %d\n", hc->ep_type); - DWC_PRINT(" max_packet: %d\n", hc->max_packet); - DWC_PRINT(" data_pid_start: %d\n", hc->data_pid_start); - DWC_PRINT(" multi_count: %d\n", hc->multi_count); - DWC_PRINT(" xfer_started: %d\n", hc->xfer_started); - DWC_PRINT(" xfer_buff: %p\n", hc->xfer_buff); - DWC_PRINT(" xfer_len: %d\n", hc->xfer_len); - DWC_PRINT(" xfer_count: %d\n", hc->xfer_count); - DWC_PRINT(" halt_on_queue: %d\n", hc->halt_on_queue); - DWC_PRINT(" halt_pending: %d\n", hc->halt_pending); - DWC_PRINT(" halt_status: %d\n", hc->halt_status); - DWC_PRINT(" do_split: %d\n", hc->do_split); - DWC_PRINT(" complete_split: %d\n", hc->complete_split); - DWC_PRINT(" hub_addr: %d\n", hc->hub_addr); - DWC_PRINT(" port_addr: %d\n", hc->port_addr); - DWC_PRINT(" xact_pos: %d\n", hc->xact_pos); - DWC_PRINT(" requests: %d\n", hc->requests); - DWC_PRINT(" qh: %p\n", hc->qh); - if (hc->xfer_started) { - hfnum_data_t hfnum; - hcchar_data_t hcchar; - hctsiz_data_t hctsiz; - hcint_data_t hcint; - hcintmsk_data_t hcintmsk; - hfnum.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hfnum); - hcchar.d32 = dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->hcchar); - hctsiz.d32 = dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->hctsiz); - hcint.d32 = dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->hcint); - hcintmsk.d32 = dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->hcintmsk); - DWC_PRINT(" hfnum: 0x%08x\n", hfnum.d32); - DWC_PRINT(" hcchar: 0x%08x\n", hcchar.d32); - DWC_PRINT(" hctsiz: 0x%08x\n", hctsiz.d32); - DWC_PRINT(" hcint: 0x%08x\n", hcint.d32); - DWC_PRINT(" hcintmsk: 0x%08x\n", hcintmsk.d32); - } - if (hc->xfer_started && hc->qh && hc->qh->qtd_in_process) { - dwc_otg_qtd_t *qtd; - struct urb *urb; - qtd = hc->qh->qtd_in_process; - urb = qtd->urb; - DWC_PRINT(" URB Info:\n"); - DWC_PRINT(" qtd: %p, urb: %p\n", qtd, urb); - if (urb) { - DWC_PRINT(" Dev: %d, EP: %d %s\n", - usb_pipedevice(urb->pipe), usb_pipeendpoint(urb->pipe), - usb_pipein(urb->pipe) ? "IN" : "OUT"); - DWC_PRINT(" Max packet size: %d\n", - usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); - DWC_PRINT(" transfer_buffer: %p\n", urb->transfer_buffer); - DWC_PRINT(" transfer_dma: %p\n", (void *)urb->transfer_dma); - DWC_PRINT(" transfer_buffer_length: %d\n", urb->transfer_buffer_length); - DWC_PRINT(" actual_length: %d\n", urb->actual_length); - } - } - } - DWC_PRINT(" non_periodic_channels: %d\n", hcd->non_periodic_channels); - DWC_PRINT(" periodic_channels: %d\n", hcd->periodic_channels); - DWC_PRINT(" periodic_usecs: %d\n", hcd->periodic_usecs); - np_tx_status.d32 = dwc_read_reg32(&hcd->core_if->core_global_regs->gnptxsts); - DWC_PRINT(" NP Tx Req Queue Space Avail: %d\n", np_tx_status.b.nptxqspcavail); - DWC_PRINT(" NP Tx FIFO Space Avail: %d\n", np_tx_status.b.nptxfspcavail); - p_tx_status.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hptxsts); - DWC_PRINT(" P Tx Req Queue Space Avail: %d\n", p_tx_status.b.ptxqspcavail); - DWC_PRINT(" P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail); - dwc_otg_hcd_dump_frrem(hcd); - dwc_otg_dump_global_registers(hcd->core_if); - dwc_otg_dump_host_registers(hcd->core_if); - DWC_PRINT("************************************************************\n"); - DWC_PRINT("\n"); -#endif -} -#endif /* DWC_DEVICE_ONLY */ diff --git a/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_hcd.h b/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_hcd.h deleted file mode 100644 index ee41dc96f9..0000000000 --- a/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_hcd.h +++ /dev/null @@ -1,668 +0,0 @@ -/* ========================================================================== - * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $ - * $Revision: 1.3 $ - * $Date: 2008-12-15 06:51:32 $ - * $Change: 1064918 $ - * - * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, - * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless - * otherwise expressly agreed to in writing between Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ -#ifndef DWC_DEVICE_ONLY -#ifndef __DWC_HCD_H__ -#define __DWC_HCD_H__ - -#include -#include -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35) -#include -#else -#include <../drivers/usb/core/hcd.h> -#endif - -struct dwc_otg_device; - -#include "dwc_otg_cil.h" - -/** - * @file - * - * This file contains the structures, constants, and interfaces for - * the Host Contoller Driver (HCD). - * - * The Host Controller Driver (HCD) is responsible for translating requests - * from the USB Driver into the appropriate actions on the DWC_otg controller. - * It isolates the USBD from the specifics of the controller by providing an - * API to the USBD. - */ - -/** - * Phases for control transfers. - */ -typedef enum dwc_otg_control_phase { - DWC_OTG_CONTROL_SETUP, - DWC_OTG_CONTROL_DATA, - DWC_OTG_CONTROL_STATUS -} dwc_otg_control_phase_e; - -/** Transaction types. */ -typedef enum dwc_otg_transaction_type { - DWC_OTG_TRANSACTION_NONE, - DWC_OTG_TRANSACTION_PERIODIC, - DWC_OTG_TRANSACTION_NON_PERIODIC, - DWC_OTG_TRANSACTION_ALL -} dwc_otg_transaction_type_e; - -/** - * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, - * interrupt, or isochronous transfer. A single QTD is created for each URB - * (of one of these types) submitted to the HCD. The transfer associated with - * a QTD may require one or multiple transactions. - * - * A QTD is linked to a Queue Head, which is entered in either the - * non-periodic or periodic schedule for execution. When a QTD is chosen for - * execution, some or all of its transactions may be executed. After - * execution, the state of the QTD is updated. The QTD may be retired if all - * its transactions are complete or if an error occurred. Otherwise, it - * remains in the schedule so more transactions can be executed later. - */ -typedef struct dwc_otg_qtd { - /** - * Determines the PID of the next data packet for the data phase of - * control transfers. Ignored for other transfer types.
- * One of the following values: - * - DWC_OTG_HC_PID_DATA0 - * - DWC_OTG_HC_PID_DATA1 - */ - uint8_t data_toggle; - - /** Current phase for control transfers (Setup, Data, or Status). */ - dwc_otg_control_phase_e control_phase; - - /** Keep track of the current split type - * for FS/LS endpoints on a HS Hub */ - uint8_t complete_split; - - /** How many bytes transferred during SSPLIT OUT */ - uint32_t ssplit_out_xfer_count; - - /** - * Holds the number of bus errors that have occurred for a transaction - * within this transfer. - */ - uint8_t error_count; - - /** - * Index of the next frame descriptor for an isochronous transfer. A - * frame descriptor describes the buffer position and length of the - * data to be transferred in the next scheduled (micro)frame of an - * isochronous transfer. It also holds status for that transaction. - * The frame index starts at 0. - */ - int isoc_frame_index; - - /** Position of the ISOC split on full/low speed */ - uint8_t isoc_split_pos; - - /** Position of the ISOC split in the buffer for the current frame */ - uint16_t isoc_split_offset; - - /** URB for this transfer */ - struct urb *urb; - - /** This list of QTDs */ - struct list_head qtd_list_entry; - -} dwc_otg_qtd_t; - -/** - * A Queue Head (QH) holds the static characteristics of an endpoint and - * maintains a list of transfers (QTDs) for that endpoint. A QH structure may - * be entered in either the non-periodic or periodic schedule. - */ -typedef struct dwc_otg_qh { - /** - * Endpoint type. - * One of the following values: - * - USB_ENDPOINT_XFER_CONTROL - * - USB_ENDPOINT_XFER_ISOC - * - USB_ENDPOINT_XFER_BULK - * - USB_ENDPOINT_XFER_INT - */ - uint8_t ep_type; - uint8_t ep_is_in; - - /** wMaxPacketSize Field of Endpoint Descriptor. */ - uint16_t maxp; - - /** - * Determines the PID of the next data packet for non-control - * transfers. Ignored for control transfers.
- * One of the following values: - * - DWC_OTG_HC_PID_DATA0 - * - DWC_OTG_HC_PID_DATA1 - */ - uint8_t data_toggle; - - /** Ping state if 1. */ - uint8_t ping_state; - - /** - * List of QTDs for this QH. - */ - struct list_head qtd_list; - - /** Host channel currently processing transfers for this QH. */ - dwc_hc_t *channel; - - /** QTD currently assigned to a host channel for this QH. */ - dwc_otg_qtd_t *qtd_in_process; - - /** Full/low speed endpoint on high-speed hub requires split. */ - uint8_t do_split; - - /** @name Periodic schedule information */ - /** @{ */ - - /** Bandwidth in microseconds per (micro)frame. */ - uint8_t usecs; - - /** Interval between transfers in (micro)frames. */ - uint16_t interval; - - /** - * (micro)frame to initialize a periodic transfer. The transfer - * executes in the following (micro)frame. - */ - uint16_t sched_frame; - - /** (micro)frame at which last start split was initialized. */ - uint16_t start_split_frame; - - /** @} */ - - /** Entry for QH in either the periodic or non-periodic schedule. */ - struct list_head qh_list_entry; - - /* For non-dword aligned buffer support */ - uint8_t *dw_align_buf; - dma_addr_t dw_align_buf_dma; -} dwc_otg_qh_t; - -/** - * This structure holds the state of the HCD, including the non-periodic and - * periodic schedules. - */ -typedef struct dwc_otg_hcd { - /** The DWC otg device pointer */ - struct dwc_otg_device *otg_dev; - - /** DWC OTG Core Interface Layer */ - dwc_otg_core_if_t *core_if; - - /** Internal DWC HCD Flags */ - volatile union dwc_otg_hcd_internal_flags { - uint32_t d32; - struct { - unsigned port_connect_status_change : 1; - unsigned port_connect_status : 1; - unsigned port_reset_change : 1; - unsigned port_enable_change : 1; - unsigned port_suspend_change : 1; - unsigned port_over_current_change : 1; - unsigned reserved : 27; - } b; - } flags; - - /** - * Inactive items in the non-periodic schedule. This is a list of - * Queue Heads. Transfers associated with these Queue Heads are not - * currently assigned to a host channel. - */ - struct list_head non_periodic_sched_inactive; - - /** - * Active items in the non-periodic schedule. This is a list of - * Queue Heads. Transfers associated with these Queue Heads are - * currently assigned to a host channel. - */ - struct list_head non_periodic_sched_active; - - /** - * Pointer to the next Queue Head to process in the active - * non-periodic schedule. - */ - struct list_head *non_periodic_qh_ptr; - - /** - * Inactive items in the periodic schedule. This is a list of QHs for - * periodic transfers that are _not_ scheduled for the next frame. - * Each QH in the list has an interval counter that determines when it - * needs to be scheduled for execution. This scheduling mechanism - * allows only a simple calculation for periodic bandwidth used (i.e. - * must assume that all periodic transfers may need to execute in the - * same frame). However, it greatly simplifies scheduling and should - * be sufficient for the vast majority of OTG hosts, which need to - * connect to a small number of peripherals at one time. - * - * Items move from this list to periodic_sched_ready when the QH - * interval counter is 0 at SOF. - */ - struct list_head periodic_sched_inactive; - - /** - * List of periodic QHs that are ready for execution in the next - * frame, but have not yet been assigned to host channels. - * - * Items move from this list to periodic_sched_assigned as host - * channels become available during the current frame. - */ - struct list_head periodic_sched_ready; - - /** - * List of periodic QHs to be executed in the next frame that are - * assigned to host channels. - * - * Items move from this list to periodic_sched_queued as the - * transactions for the QH are queued to the DWC_otg controller. - */ - struct list_head periodic_sched_assigned; - - /** - * List of periodic QHs that have been queued for execution. - * - * Items move from this list to either periodic_sched_inactive or - * periodic_sched_ready when the channel associated with the transfer - * is released. If the interval for the QH is 1, the item moves to - * periodic_sched_ready because it must be rescheduled for the next - * frame. Otherwise, the item moves to periodic_sched_inactive. - */ - struct list_head periodic_sched_queued; - - /** - * Total bandwidth claimed so far for periodic transfers. This value - * is in microseconds per (micro)frame. The assumption is that all - * periodic transfers may occur in the same (micro)frame. - */ - uint16_t periodic_usecs; - - /** - * Frame number read from the core at SOF. The value ranges from 0 to - * DWC_HFNUM_MAX_FRNUM. - */ - uint16_t frame_number; - - /** - * Free host channels in the controller. This is a list of - * dwc_hc_t items. - */ - struct list_head free_hc_list; - - /** - * Number of host channels assigned to periodic transfers. Currently - * assuming that there is a dedicated host channel for each periodic - * transaction and at least one host channel available for - * non-periodic transactions. - */ - int periodic_channels; - - /** - * Number of host channels assigned to non-periodic transfers. - */ - int non_periodic_channels; - - /** - * Array of pointers to the host channel descriptors. Allows accessing - * a host channel descriptor given the host channel number. This is - * useful in interrupt handlers. - */ - dwc_hc_t *hc_ptr_array[MAX_EPS_CHANNELS]; - - /** - * Buffer to use for any data received during the status phase of a - * control transfer. Normally no data is transferred during the status - * phase. This buffer is used as a bit bucket. - */ - uint8_t *status_buf; - - /** - * DMA address for status_buf. - */ - dma_addr_t status_buf_dma; -#define DWC_OTG_HCD_STATUS_BUF_SIZE 64 - - /** - * Structure to allow starting the HCD in a non-interrupt context - * during an OTG role change. - */ -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) - struct work_struct start_work; -#else - struct delayed_work start_work; -#endif - - /** - * Connection timer. An OTG host must display a message if the device - * does not connect. Started when the VBus power is turned on via - * sysfs attribute "buspower". - */ - struct timer_list conn_timer; - - /* Tasket to do a reset */ - struct tasklet_struct *reset_tasklet; - - /* */ - spinlock_t lock; - -#ifdef DEBUG - uint32_t frrem_samples; - uint64_t frrem_accum; - - uint32_t hfnum_7_samples_a; - uint64_t hfnum_7_frrem_accum_a; - uint32_t hfnum_0_samples_a; - uint64_t hfnum_0_frrem_accum_a; - uint32_t hfnum_other_samples_a; - uint64_t hfnum_other_frrem_accum_a; - - uint32_t hfnum_7_samples_b; - uint64_t hfnum_7_frrem_accum_b; - uint32_t hfnum_0_samples_b; - uint64_t hfnum_0_frrem_accum_b; - uint32_t hfnum_other_samples_b; - uint64_t hfnum_other_frrem_accum_b; -#endif -} dwc_otg_hcd_t; - -/** Gets the dwc_otg_hcd from a struct usb_hcd */ -static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd) -{ - return (dwc_otg_hcd_t *)(hcd->hcd_priv); -} - -/** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */ -static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t *dwc_otg_hcd) -{ - return container_of((void *)dwc_otg_hcd, struct usb_hcd, hcd_priv); -} - -/** @name HCD Create/Destroy Functions */ -/** @{ */ -extern int dwc_otg_hcd_init(struct device *dev); -extern void dwc_otg_hcd_remove(struct device *dev); -/** @} */ - -/** @name Linux HC Driver API Functions */ -/** @{ */ - -extern int dwc_otg_hcd_start(struct usb_hcd *hcd); -extern void dwc_otg_hcd_stop(struct usb_hcd *hcd); -extern int dwc_otg_hcd_get_frame_number(struct usb_hcd *hcd); -extern void dwc_otg_hcd_free(struct usb_hcd *hcd); -extern int dwc_otg_hcd_urb_enqueue(struct usb_hcd *hcd, - struct urb *urb, -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) - int mem_flags -#else - gfp_t mem_flags -#endif - ); -extern int dwc_otg_hcd_urb_dequeue(struct usb_hcd *hcd, -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -#endif - struct urb *urb, int status); -extern void dwc_otg_hcd_endpoint_disable(struct usb_hcd *hcd, - struct usb_host_endpoint *ep); -extern irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) - , struct pt_regs *regs -#endif - ); -extern int dwc_otg_hcd_hub_status_data(struct usb_hcd *hcd, - char *buf); -extern int dwc_otg_hcd_hub_control(struct usb_hcd *hcd, - u16 typeReq, - u16 wValue, - u16 wIndex, - char *buf, - u16 wLength); - -/** @} */ - -/** @name Transaction Execution Functions */ -/** @{ */ -extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *hcd); -extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *hcd, - dwc_otg_transaction_type_e tr_type); -extern void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t *_hcd, struct urb *urb, - int status); -/** @} */ - -/** @name Interrupt Handler Functions */ -/** @{ */ -extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t *dwc_otg_hcd); -extern int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t *dwc_otg_hcd); -extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *dwc_otg_hcd); -extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd); -extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd); -extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *dwc_otg_hcd); -extern int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t *dwc_otg_hcd); -extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(dwc_otg_hcd_t *dwc_otg_hcd); -extern int32_t dwc_otg_hcd_handle_disconnect_intr(dwc_otg_hcd_t *dwc_otg_hcd); -extern int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t *dwc_otg_hcd); -extern int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t *dwc_otg_hcd, uint32_t num); -extern int32_t dwc_otg_hcd_handle_session_req_intr(dwc_otg_hcd_t *dwc_otg_hcd); -extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr(dwc_otg_hcd_t *dwc_otg_hcd); -/** @} */ - - -/** @name Schedule Queue Functions */ -/** @{ */ - -/* Implemented in dwc_otg_hcd_queue.c */ -extern dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t *hcd, struct urb *urb); -extern void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, struct urb *urb); -extern void dwc_otg_hcd_qh_free(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh); -extern int dwc_otg_hcd_qh_add(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh); -extern void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh); -extern void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int sched_csplit); - -/** Remove and free a QH */ -static inline void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t *hcd, - dwc_otg_qh_t *qh) -{ - dwc_otg_hcd_qh_remove(hcd, qh); - dwc_otg_hcd_qh_free(hcd, qh); -} - -/** Allocates memory for a QH structure. - * @return Returns the memory allocate or NULL on error. */ -static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(void) -{ - return (dwc_otg_qh_t *) kmalloc(sizeof(dwc_otg_qh_t), GFP_KERNEL); -} - -extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(struct urb *urb); -extern void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t *qtd, struct urb *urb); -extern int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t *qtd, dwc_otg_hcd_t *dwc_otg_hcd); - -/** Allocates memory for a QTD structure. - * @return Returns the memory allocate or NULL on error. */ -static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(void) -{ - return (dwc_otg_qtd_t *) kmalloc(sizeof(dwc_otg_qtd_t), GFP_KERNEL); -} - -/** Frees the memory for a QTD structure. QTD should already be removed from - * list. - * @param[in] qtd QTD to free.*/ -static inline void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t *qtd) -{ - kfree(qtd); -} - -/** Removes a QTD from list. - * @param[in] hcd HCD instance. - * @param[in] qtd QTD to remove from list. */ -static inline void dwc_otg_hcd_qtd_remove(dwc_otg_hcd_t *hcd, dwc_otg_qtd_t *qtd) -{ - unsigned long flags; - SPIN_LOCK_IRQSAVE(&hcd->lock, flags); - list_del(&qtd->qtd_list_entry); - SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags); -} - -/** Remove and free a QTD */ -static inline void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t *hcd, dwc_otg_qtd_t *qtd) -{ - dwc_otg_hcd_qtd_remove(hcd, qtd); - dwc_otg_hcd_qtd_free(qtd); -} - -/** @} */ - - -/** @name Internal Functions */ -/** @{ */ -dwc_otg_qh_t *dwc_urb_to_qh(struct urb *urb); -void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *hcd); -void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *hcd); -/** @} */ - -/** Gets the usb_host_endpoint associated with an URB. */ -static inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *urb) -{ - struct usb_device *dev = urb->dev; - int ep_num = usb_pipeendpoint(urb->pipe); - - if (usb_pipein(urb->pipe)) - return dev->ep_in[ep_num]; - else - return dev->ep_out[ep_num]; -} - -/** - * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is - * qualified with its direction (possible 32 endpoints per device). - */ -#define dwc_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \ - ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4) - -/** Gets the QH that contains the list_head */ -#define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry) - -/** Gets the QTD that contains the list_head */ -#define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry) - -/** Check if QH is non-periodic */ -#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == USB_ENDPOINT_XFER_BULK) || \ - (_qh_ptr_->ep_type == USB_ENDPOINT_XFER_CONTROL)) - -/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */ -#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03)) - -/** Packet size for any kind of endpoint descriptor */ -#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) - -/** - * Returns true if _frame1 is less than or equal to _frame2. The comparison is - * done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the - * frame number when the max frame number is reached. - */ -static inline int dwc_frame_num_le(uint16_t frame1, uint16_t frame2) -{ - return ((frame2 - frame1) & DWC_HFNUM_MAX_FRNUM) <= - (DWC_HFNUM_MAX_FRNUM >> 1); -} - -/** - * Returns true if _frame1 is greater than _frame2. The comparison is done - * modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame - * number when the max frame number is reached. - */ -static inline int dwc_frame_num_gt(uint16_t frame1, uint16_t frame2) -{ - return (frame1 != frame2) && - (((frame1 - frame2) & DWC_HFNUM_MAX_FRNUM) < - (DWC_HFNUM_MAX_FRNUM >> 1)); -} - -/** - * Increments _frame by the amount specified by _inc. The addition is done - * modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value. - */ -static inline uint16_t dwc_frame_num_inc(uint16_t frame, uint16_t inc) -{ - return (frame + inc) & DWC_HFNUM_MAX_FRNUM; -} - -static inline uint16_t dwc_full_frame_num(uint16_t frame) -{ - return (frame & DWC_HFNUM_MAX_FRNUM) >> 3; -} - -static inline uint16_t dwc_micro_frame_num(uint16_t frame) -{ - return frame & 0x7; -} - -#ifdef DEBUG -/** - * Macro to sample the remaining PHY clocks left in the current frame. This - * may be used during debugging to determine the average time it takes to - * execute sections of code. There are two possible sample points, "a" and - * "b", so the _letter argument must be one of these values. - * - * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For - * example, "cat /sys/devices/lm0/hcd_frrem". - */ -#define dwc_sample_frrem(_hcd, _qh, _letter) \ -{ \ - hfnum_data_t hfnum; \ - dwc_otg_qtd_t *qtd; \ - qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \ - if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \ - hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum); \ - switch (hfnum.b.frnum & 0x7) { \ - case 7: \ - _hcd->hfnum_7_samples_##_letter++; \ - _hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \ - break; \ - case 0: \ - _hcd->hfnum_0_samples_##_letter++; \ - _hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \ - break; \ - default: \ - _hcd->hfnum_other_samples_##_letter++; \ - _hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \ - break; \ - } \ - } \ -} -#else -#define dwc_sample_frrem(_hcd, _qh, _letter) -#endif -#endif -#endif /* DWC_DEVICE_ONLY */ diff --git a/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c b/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c deleted file mode 100644 index bdf2db99f3..0000000000 --- a/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c +++ /dev/null @@ -1,1873 +0,0 @@ -/* ========================================================================== - * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $ - * $Revision: 1.6.2.1 $ - * $Date: 2009-04-22 03:48:22 $ - * $Change: 1117667 $ - * - * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, - * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless - * otherwise expressly agreed to in writing between Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ -#ifndef DWC_DEVICE_ONLY - -#include - -#include "dwc_otg_driver.h" -#include "dwc_otg_hcd.h" -#include "dwc_otg_regs.h" - -/** @file - * This file contains the implementation of the HCD Interrupt handlers. - */ - -/** This function handles interrupts for the HCD. */ -int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t *dwc_otg_hcd) -{ - int retval = 0; - - dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; - gintsts_data_t gintsts; -#ifdef DEBUG - dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; -#endif - - /* Check if HOST Mode */ - if (dwc_otg_is_host_mode(core_if)) { - gintsts.d32 = dwc_otg_read_core_intr(core_if); - if (!gintsts.d32) { - return 0; - } - -#ifdef DEBUG - /* Don't print debug message in the interrupt handler on SOF */ -# ifndef DEBUG_SOF - if (gintsts.d32 != DWC_SOF_INTR_MASK) -# endif - DWC_DEBUGPL(DBG_HCD, "\n"); -#endif - -#ifdef DEBUG -# ifndef DEBUG_SOF - if (gintsts.d32 != DWC_SOF_INTR_MASK) -# endif - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n", gintsts.d32); -#endif - if (gintsts.b.usbreset) { - DWC_PRINT("Usb Reset In Host Mode\n"); - } - - - if (gintsts.b.sofintr) { - retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd); - } - if (gintsts.b.rxstsqlvl) { - retval |= dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd); - } - if (gintsts.b.nptxfempty) { - retval |= dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd); - } - if (gintsts.b.i2cintr) { - /** @todo Implement i2cintr handler. */ - } - if (gintsts.b.portintr) { - retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd); - } - if (gintsts.b.hcintr) { - retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd); - } - if (gintsts.b.ptxfempty) { - retval |= dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd); - } -#ifdef DEBUG -# ifndef DEBUG_SOF - if (gintsts.d32 != DWC_SOF_INTR_MASK) -# endif - { - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Finished Servicing Interrupts\n"); - DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n", - dwc_read_reg32(&global_regs->gintsts)); - DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n", - dwc_read_reg32(&global_regs->gintmsk)); - } -#endif - -#ifdef DEBUG -# ifndef DEBUG_SOF - if (gintsts.d32 != DWC_SOF_INTR_MASK) -# endif - DWC_DEBUGPL(DBG_HCD, "\n"); -#endif - - } - - S3C2410X_CLEAR_EINTPEND(); - - return retval; -} - -#ifdef DWC_TRACK_MISSED_SOFS -#warning Compiling code to track missed SOFs -#define FRAME_NUM_ARRAY_SIZE 1000 -/** - * This function is for debug only. - */ -static inline void track_missed_sofs(uint16_t curr_frame_number) -{ - static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE]; - static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE]; - static int frame_num_idx = 0; - static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM; - static int dumped_frame_num_array = 0; - - if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) { - if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) != curr_frame_number) { - frame_num_array[frame_num_idx] = curr_frame_number; - last_frame_num_array[frame_num_idx++] = last_frame_num; - } - } else if (!dumped_frame_num_array) { - int i; - printk(KERN_EMERG USB_DWC "Frame Last Frame\n"); - printk(KERN_EMERG USB_DWC "----- ----------\n"); - for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) { - printk(KERN_EMERG USB_DWC "0x%04x 0x%04x\n", - frame_num_array[i], last_frame_num_array[i]); - } - dumped_frame_num_array = 1; - } - last_frame_num = curr_frame_number; -} -#endif - -/** - * Handles the start-of-frame interrupt in host mode. Non-periodic - * transactions may be queued to the DWC_otg controller for the current - * (micro)frame. Periodic transactions may be queued to the controller for the - * next (micro)frame. - */ -int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t *hcd) -{ - hfnum_data_t hfnum; - struct list_head *qh_entry; - dwc_otg_qh_t *qh; - dwc_otg_transaction_type_e tr_type; - gintsts_data_t gintsts = {.d32 = 0}; - - hfnum.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hfnum); - -#ifdef DEBUG_SOF - DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n"); -#endif - hcd->frame_number = hfnum.b.frnum; - -#ifdef DEBUG - hcd->frrem_accum += hfnum.b.frrem; - hcd->frrem_samples++; -#endif - -#ifdef DWC_TRACK_MISSED_SOFS - track_missed_sofs(hcd->frame_number); -#endif - - /* Determine whether any periodic QHs should be executed. */ - qh_entry = hcd->periodic_sched_inactive.next; - while (qh_entry != &hcd->periodic_sched_inactive) { - qh = list_entry(qh_entry, dwc_otg_qh_t, qh_list_entry); - qh_entry = qh_entry->next; - if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) { - /* - * Move QH to the ready list to be executed next - * (micro)frame. - */ - list_move(&qh->qh_list_entry, &hcd->periodic_sched_ready); - } - } - - tr_type = dwc_otg_hcd_select_transactions(hcd); - if (tr_type != DWC_OTG_TRANSACTION_NONE) { - dwc_otg_hcd_queue_transactions(hcd, tr_type); - } - - /* Clear interrupt */ - gintsts.b.sofintr = 1; - dwc_write_reg32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32); - - return 1; -} - -/** Handles the Rx Status Queue Level Interrupt, which indicates that there is at - * least one packet in the Rx FIFO. The packets are moved from the FIFO to - * memory if the DWC_otg controller is operating in Slave mode. */ -int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *dwc_otg_hcd) -{ - host_grxsts_data_t grxsts; - dwc_hc_t *hc = NULL; - - DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n"); - - grxsts.d32 = dwc_read_reg32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp); - - hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum]; - - /* Packet Status */ - DWC_DEBUGPL(DBG_HCDV, " Ch num = %d\n", grxsts.b.chnum); - DWC_DEBUGPL(DBG_HCDV, " Count = %d\n", grxsts.b.bcnt); - DWC_DEBUGPL(DBG_HCDV, " DPID = %d, hc.dpid = %d\n", grxsts.b.dpid, hc->data_pid_start); - DWC_DEBUGPL(DBG_HCDV, " PStatus = %d\n", grxsts.b.pktsts); - - switch (grxsts.b.pktsts) { - case DWC_GRXSTS_PKTSTS_IN: - /* Read the data into the host buffer. */ - if (grxsts.b.bcnt > 0) { - dwc_otg_read_packet(dwc_otg_hcd->core_if, - hc->xfer_buff, - grxsts.b.bcnt); - - /* Update the HC fields for the next packet received. */ - hc->xfer_count += grxsts.b.bcnt; - hc->xfer_buff += grxsts.b.bcnt; - } - - case DWC_GRXSTS_PKTSTS_IN_XFER_COMP: - case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR: - case DWC_GRXSTS_PKTSTS_CH_HALTED: - /* Handled in interrupt, just ignore data */ - break; - default: - DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n", grxsts.b.pktsts); - break; - } - - return 1; -} - -/** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More - * data packets may be written to the FIFO for OUT transfers. More requests - * may be written to the non-periodic request queue for IN transfers. This - * interrupt is enabled only in Slave mode. */ -int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd) -{ - DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n"); - dwc_otg_hcd_queue_transactions(dwc_otg_hcd, - DWC_OTG_TRANSACTION_NON_PERIODIC); - return 1; -} - -/** This interrupt occurs when the periodic Tx FIFO is half-empty. More data - * packets may be written to the FIFO for OUT transfers. More requests may be - * written to the periodic request queue for IN transfers. This interrupt is - * enabled only in Slave mode. */ -int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd) -{ - DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n"); - dwc_otg_hcd_queue_transactions(dwc_otg_hcd, - DWC_OTG_TRANSACTION_PERIODIC); - return 1; -} - -/** There are multiple conditions that can cause a port interrupt. This function - * determines which interrupt conditions have occurred and handles them - * appropriately. */ -int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t *dwc_otg_hcd) -{ - int retval = 0; - hprt0_data_t hprt0; - hprt0_data_t hprt0_modify; - - hprt0.d32 = dwc_read_reg32(dwc_otg_hcd->core_if->host_if->hprt0); - hprt0_modify.d32 = dwc_read_reg32(dwc_otg_hcd->core_if->host_if->hprt0); - - /* Clear appropriate bits in HPRT0 to clear the interrupt bit in - * GINTSTS */ - - hprt0_modify.b.prtena = 0; - hprt0_modify.b.prtconndet = 0; - hprt0_modify.b.prtenchng = 0; - hprt0_modify.b.prtovrcurrchng = 0; - - /* Port Connect Detected - * Set flag and clear if detected */ - if (hprt0.b.prtconndet) { - DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x " - "Port Connect Detected--\n", hprt0.d32); - dwc_otg_hcd->flags.b.port_connect_status_change = 1; - dwc_otg_hcd->flags.b.port_connect_status = 1; - hprt0_modify.b.prtconndet = 1; - - /* B-Device has connected, Delete the connection timer. */ - del_timer( &dwc_otg_hcd->conn_timer ); - - /* The Hub driver asserts a reset when it sees port connect - * status change flag */ - retval |= 1; - } - - /* Port Enable Changed - * Clear if detected - Set internal flag if disabled */ - if (hprt0.b.prtenchng) { - DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x " - "Port Enable Changed--\n", hprt0.d32); - hprt0_modify.b.prtenchng = 1; - if (hprt0.b.prtena == 1) { - int do_reset = 0; - dwc_otg_core_params_t *params = dwc_otg_hcd->core_if->core_params; - dwc_otg_core_global_regs_t *global_regs = dwc_otg_hcd->core_if->core_global_regs; - dwc_otg_host_if_t *host_if = dwc_otg_hcd->core_if->host_if; - - /* Check if we need to adjust the PHY clock speed for - * low power and adjust it */ - if (params->host_support_fs_ls_low_power) { - gusbcfg_data_t usbcfg; - - usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); - - if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED || - hprt0.b.prtspd == DWC_HPRT0_PRTSPD_FULL_SPEED) { - /* - * Low power - */ - hcfg_data_t hcfg; - if (usbcfg.b.phylpwrclksel == 0) { - /* Set PHY low power clock select for FS/LS devices */ - usbcfg.b.phylpwrclksel = 1; - dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); - do_reset = 1; - } - - hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg); - - if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED && - params->host_ls_low_power_phy_clk == - DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) { - /* 6 MHZ */ - DWC_DEBUGPL(DBG_CIL, "FS_PHY programming HCFG to 6 MHz (Low Power)\n"); - if (hcfg.b.fslspclksel != DWC_HCFG_6_MHZ) { - hcfg.b.fslspclksel = DWC_HCFG_6_MHZ; - dwc_write_reg32(&host_if->host_global_regs->hcfg, - hcfg.d32); - do_reset = 1; - } - } else { - /* 48 MHZ */ - DWC_DEBUGPL(DBG_CIL, "FS_PHY programming HCFG to 48 MHz ()\n"); - if (hcfg.b.fslspclksel != DWC_HCFG_48_MHZ) { - hcfg.b.fslspclksel = DWC_HCFG_48_MHZ; - dwc_write_reg32(&host_if->host_global_regs->hcfg, - hcfg.d32); - do_reset = 1; - } - } - } else { - /* - * Not low power - */ - if (usbcfg.b.phylpwrclksel == 1) { - usbcfg.b.phylpwrclksel = 0; - dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); - do_reset = 1; - } - } - - if (do_reset) { - tasklet_schedule(dwc_otg_hcd->reset_tasklet); - } - } - - if (!do_reset) { - /* Port has been enabled set the reset change flag */ - dwc_otg_hcd->flags.b.port_reset_change = 1; - } - } else { - dwc_otg_hcd->flags.b.port_enable_change = 1; - } - retval |= 1; - } - - /** Overcurrent Change Interrupt */ - if (hprt0.b.prtovrcurrchng) { - DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x " - "Port Overcurrent Changed--\n", hprt0.d32); - dwc_otg_hcd->flags.b.port_over_current_change = 1; - hprt0_modify.b.prtovrcurrchng = 1; - retval |= 1; - } - - /* Clear Port Interrupts */ - dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32); - - return retval; -} - -/** This interrupt indicates that one or more host channels has a pending - * interrupt. There are multiple conditions that can cause each host channel - * interrupt. This function determines which conditions have occurred for each - * host channel interrupt and handles them appropriately. */ -int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t *dwc_otg_hcd) -{ - int i; - int retval = 0; - haint_data_t haint; - - /* Clear appropriate bits in HCINTn to clear the interrupt bit in - * GINTSTS */ - - haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if); - - for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) { - if (haint.b2.chint & (1 << i)) { - retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i); - } - } - - return retval; -} - -/* Macro used to clear one channel interrupt */ -#define clear_hc_int(_hc_regs_, _intr_) \ -do { \ - hcint_data_t hcint_clear = {.d32 = 0}; \ - hcint_clear.b._intr_ = 1; \ - dwc_write_reg32(&(_hc_regs_)->hcint, hcint_clear.d32); \ -} while (0) - -/* - * Macro used to disable one channel interrupt. Channel interrupts are - * disabled when the channel is halted or released by the interrupt handler. - * There is no need to handle further interrupts of that type until the - * channel is re-assigned. In fact, subsequent handling may cause crashes - * because the channel structures are cleaned up when the channel is released. - */ -#define disable_hc_int(_hc_regs_, _intr_) \ -do { \ - hcintmsk_data_t hcintmsk = {.d32 = 0}; \ - hcintmsk.b._intr_ = 1; \ - dwc_modify_reg32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \ -} while (0) - -/** - * Gets the actual length of a transfer after the transfer halts. _halt_status - * holds the reason for the halt. - * - * For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE, - * *short_read is set to 1 upon return if less than the requested - * number of bytes were transferred. Otherwise, *short_read is set to 0 upon - * return. short_read may also be NULL on entry, in which case it remains - * unchanged. - */ -static uint32_t get_actual_xfer_length(dwc_hc_t *hc, - dwc_otg_hc_regs_t *hc_regs, - dwc_otg_qtd_t *qtd, - dwc_otg_halt_status_e halt_status, - int *short_read) -{ - hctsiz_data_t hctsiz; - uint32_t length; - - if (short_read != NULL) { - *short_read = 0; - } - hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); - - if (halt_status == DWC_OTG_HC_XFER_COMPLETE) { - if (hc->ep_is_in) { - length = hc->xfer_len - hctsiz.b.xfersize; - if (short_read != NULL) { - *short_read = (hctsiz.b.xfersize != 0); - } - } else if (hc->qh->do_split) { - length = qtd->ssplit_out_xfer_count; - } else { - length = hc->xfer_len; - } - } else { - /* - * Must use the hctsiz.pktcnt field to determine how much data - * has been transferred. This field reflects the number of - * packets that have been transferred via the USB. This is - * always an integral number of packets if the transfer was - * halted before its normal completion. (Can't use the - * hctsiz.xfersize field because that reflects the number of - * bytes transferred via the AHB, not the USB). - */ - length = (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet; - } - - return length; -} - -/** - * Updates the state of the URB after a Transfer Complete interrupt on the - * host channel. Updates the actual_length field of the URB based on the - * number of bytes transferred via the host channel. Sets the URB status - * if the data transfer is finished. - * - * @return 1 if the data transfer specified by the URB is completely finished, - * 0 otherwise. - */ -static int update_urb_state_xfer_comp(dwc_hc_t *hc, - dwc_otg_hc_regs_t *hc_regs, - struct urb *urb, - dwc_otg_qtd_t *qtd) -{ - int xfer_done = 0; - int short_read = 0; - int overflow_read=0; - uint32_t len = 0; - int max_packet; - - len = get_actual_xfer_length(hc, hc_regs, qtd, - DWC_OTG_HC_XFER_COMPLETE, - &short_read); - - /* Data overflow case: by Steven */ - if (len > urb->transfer_buffer_length) { - len = urb->transfer_buffer_length; - overflow_read = 1; - } - - /* non DWORD-aligned buffer case handling. */ - if (((uint32_t)hc->xfer_buff & 0x3) && len && hc->qh->dw_align_buf && hc->ep_is_in) { - memcpy(urb->transfer_buffer + urb->actual_length, hc->qh->dw_align_buf, len); - } - urb->actual_length +=len; - - max_packet = usb_maxpacket(urb->dev, urb->pipe, !usb_pipein(urb->pipe)); - if((len) && usb_pipebulk(urb->pipe) && - (urb->transfer_flags & URB_ZERO_PACKET) && - (urb->actual_length == urb->transfer_buffer_length) && - (!(urb->transfer_buffer_length % max_packet))) { - } else if (short_read || urb->actual_length == urb->transfer_buffer_length) { - xfer_done = 1; - if (short_read && (urb->transfer_flags & URB_SHORT_NOT_OK)) { - urb->status = -EREMOTEIO; - } else if (overflow_read) { - urb->status = -EOVERFLOW; - } else { - urb->status = 0; - } - } - -#ifdef DEBUG - { - hctsiz_data_t hctsiz; - hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); - DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n", - __func__, (hc->ep_is_in ? "IN" : "OUT"), hc->hc_num); - DWC_DEBUGPL(DBG_HCDV, " hc->xfer_len %d\n", hc->xfer_len); - DWC_DEBUGPL(DBG_HCDV, " hctsiz.xfersize %d\n", hctsiz.b.xfersize); - DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n", - urb->transfer_buffer_length); - DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n", urb->actual_length); - DWC_DEBUGPL(DBG_HCDV, " short_read %d, xfer_done %d\n", - short_read, xfer_done); - } -#endif - - return xfer_done; -} - -/* - * Save the starting data toggle for the next transfer. The data toggle is - * saved in the QH for non-control transfers and it's saved in the QTD for - * control transfers. - */ -static void save_data_toggle(dwc_hc_t *hc, - dwc_otg_hc_regs_t *hc_regs, - dwc_otg_qtd_t *qtd) -{ - hctsiz_data_t hctsiz; - hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); - - if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) { - dwc_otg_qh_t *qh = hc->qh; - if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) { - qh->data_toggle = DWC_OTG_HC_PID_DATA0; - } else { - qh->data_toggle = DWC_OTG_HC_PID_DATA1; - } - } else { - if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) { - qtd->data_toggle = DWC_OTG_HC_PID_DATA0; - } else { - qtd->data_toggle = DWC_OTG_HC_PID_DATA1; - } - } -} - -/** - * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic - * QHs, removes the QH from the active non-periodic schedule. If any QTDs are - * still linked to the QH, the QH is added to the end of the inactive - * non-periodic schedule. For periodic QHs, removes the QH from the periodic - * schedule if no more QTDs are linked to the QH. - */ -static void deactivate_qh(dwc_otg_hcd_t *hcd, - dwc_otg_qh_t *qh, - int free_qtd) -{ - int continue_split = 0; - dwc_otg_qtd_t *qtd; - - DWC_DEBUGPL(DBG_HCDV, " %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd); - - qtd = list_entry(qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); - - if (qtd->complete_split) { - continue_split = 1; - } else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID || - qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) { - continue_split = 1; - } - - if (free_qtd) { - dwc_otg_hcd_qtd_remove_and_free(hcd, qtd); - continue_split = 0; - } - - qh->channel = NULL; - qh->qtd_in_process = NULL; - dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split); -} - -/** - * Updates the state of an Isochronous URB when the transfer is stopped for - * any reason. The fields of the current entry in the frame descriptor array - * are set based on the transfer state and the input _halt_status. Completes - * the Isochronous URB if all the URB frames have been completed. - * - * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be - * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE. - */ -static dwc_otg_halt_status_e -update_isoc_urb_state(dwc_otg_hcd_t *hcd, - dwc_hc_t *hc, - dwc_otg_hc_regs_t *hc_regs, - dwc_otg_qtd_t *qtd, - dwc_otg_halt_status_e halt_status) -{ - struct urb *urb = qtd->urb; - dwc_otg_halt_status_e ret_val = halt_status; - struct usb_iso_packet_descriptor *frame_desc; - - frame_desc = &urb->iso_frame_desc[qtd->isoc_frame_index]; - switch (halt_status) { - case DWC_OTG_HC_XFER_COMPLETE: - frame_desc->status = 0; - frame_desc->actual_length = - get_actual_xfer_length(hc, hc_regs, qtd, - halt_status, NULL); - - /* non DWORD-aligned buffer case handling. */ - if (frame_desc->actual_length && ((uint32_t)hc->xfer_buff & 0x3) && - hc->qh->dw_align_buf && hc->ep_is_in) { - memcpy(urb->transfer_buffer + frame_desc->offset + qtd->isoc_split_offset, - hc->qh->dw_align_buf, frame_desc->actual_length); - - } - - break; - case DWC_OTG_HC_XFER_FRAME_OVERRUN: - printk("DWC_OTG_HC_XFER_FRAME_OVERRUN: %d\n", halt_status); - urb->error_count++; - if (hc->ep_is_in) { - frame_desc->status = -ENOSR; - } else { - frame_desc->status = -ECOMM; - } - frame_desc->actual_length = 0; - break; - case DWC_OTG_HC_XFER_BABBLE_ERR: - printk("DWC_OTG_HC_XFER_BABBLE_ERR: %d\n", halt_status); - urb->error_count++; - frame_desc->status = -EOVERFLOW; - /* Don't need to update actual_length in this case. */ - break; - case DWC_OTG_HC_XFER_XACT_ERR: - printk("DWC_OTG_HC_XFER_XACT_ERR: %d\n", halt_status); - urb->error_count++; - frame_desc->status = -EPROTO; - frame_desc->actual_length = - get_actual_xfer_length(hc, hc_regs, qtd, - halt_status, NULL); - - /* non DWORD-aligned buffer case handling. */ - if (frame_desc->actual_length && ((uint32_t)hc->xfer_buff & 0x3) && - hc->qh->dw_align_buf && hc->ep_is_in) { - memcpy(urb->transfer_buffer + frame_desc->offset + qtd->isoc_split_offset, - hc->qh->dw_align_buf, frame_desc->actual_length); - - } - break; - default: - - DWC_ERROR("%s: Unhandled _halt_status (%d)\n", __func__, - halt_status); - BUG(); - break; - } - - if (++qtd->isoc_frame_index == urb->number_of_packets) { - /* - * urb->status is not used for isoc transfers. - * The individual frame_desc statuses are used instead. - */ - dwc_otg_hcd_complete_urb(hcd, urb, 0); - ret_val = DWC_OTG_HC_XFER_URB_COMPLETE; - } else { - ret_val = DWC_OTG_HC_XFER_COMPLETE; - } - - return ret_val; -} - -/** - * Releases a host channel for use by other transfers. Attempts to select and - * queue more transactions since at least one host channel is available. - * - * @param hcd The HCD state structure. - * @param hc The host channel to release. - * @param qtd The QTD associated with the host channel. This QTD may be freed - * if the transfer is complete or an error has occurred. - * @param halt_status Reason the channel is being released. This status - * determines the actions taken by this function. - */ -static void release_channel(dwc_otg_hcd_t *hcd, - dwc_hc_t *hc, - dwc_otg_qtd_t *qtd, - dwc_otg_halt_status_e halt_status) -{ - dwc_otg_transaction_type_e tr_type; - int free_qtd; - - DWC_DEBUGPL(DBG_HCDV, " %s: channel %d, halt_status %d\n", - __func__, hc->hc_num, halt_status); - - switch (halt_status) { - case DWC_OTG_HC_XFER_URB_COMPLETE: - free_qtd = 1; - break; - case DWC_OTG_HC_XFER_AHB_ERR: - case DWC_OTG_HC_XFER_STALL: - case DWC_OTG_HC_XFER_BABBLE_ERR: - free_qtd = 1; - break; - case DWC_OTG_HC_XFER_XACT_ERR: - if (qtd->error_count >= 3) { - DWC_DEBUGPL(DBG_HCDV, " Complete URB with transaction error\n"); - free_qtd = 1; - qtd->urb->status = -EPROTO; - dwc_otg_hcd_complete_urb(hcd, qtd->urb, -EPROTO); - } else { - free_qtd = 0; - } - break; - case DWC_OTG_HC_XFER_URB_DEQUEUE: - /* - * The QTD has already been removed and the QH has been - * deactivated. Don't want to do anything except release the - * host channel and try to queue more transfers. - */ - goto cleanup; - case DWC_OTG_HC_XFER_NO_HALT_STATUS: - DWC_ERROR("%s: No halt_status, channel %d\n", __func__, hc->hc_num); - free_qtd = 0; - break; - default: - free_qtd = 0; - break; - } - - deactivate_qh(hcd, hc->qh, free_qtd); - - cleanup: - /* - * Release the host channel for use by other transfers. The cleanup - * function clears the channel interrupt enables and conditions, so - * there's no need to clear the Channel Halted interrupt separately. - */ - dwc_otg_hc_cleanup(hcd->core_if, hc); - list_add_tail(&hc->hc_list_entry, &hcd->free_hc_list); - - switch (hc->ep_type) { - case DWC_OTG_EP_TYPE_CONTROL: - case DWC_OTG_EP_TYPE_BULK: - hcd->non_periodic_channels--; - break; - - default: - /* - * Don't release reservations for periodic channels here. - * That's done when a periodic transfer is descheduled (i.e. - * when the QH is removed from the periodic schedule). - */ - break; - } - - /* Try to queue more transfers now that there's a free channel. */ - tr_type = dwc_otg_hcd_select_transactions(hcd); - if (tr_type != DWC_OTG_TRANSACTION_NONE) { - dwc_otg_hcd_queue_transactions(hcd, tr_type); - } -} - -/** - * Halts a host channel. If the channel cannot be halted immediately because - * the request queue is full, this function ensures that the FIFO empty - * interrupt for the appropriate queue is enabled so that the halt request can - * be queued when there is space in the request queue. - * - * This function may also be called in DMA mode. In that case, the channel is - * simply released since the core always halts the channel automatically in - * DMA mode. - */ -static void halt_channel(dwc_otg_hcd_t *hcd, - dwc_hc_t *hc, - dwc_otg_qtd_t *qtd, - dwc_otg_halt_status_e halt_status) -{ - if (hcd->core_if->dma_enable) { - release_channel(hcd, hc, qtd, halt_status); - return; - } - - /* Slave mode processing... */ - dwc_otg_hc_halt(hcd->core_if, hc, halt_status); - - if (hc->halt_on_queue) { - gintmsk_data_t gintmsk = {.d32 = 0}; - dwc_otg_core_global_regs_t *global_regs; - global_regs = hcd->core_if->core_global_regs; - - if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL || - hc->ep_type == DWC_OTG_EP_TYPE_BULK) { - /* - * Make sure the Non-periodic Tx FIFO empty interrupt - * is enabled so that the non-periodic schedule will - * be processed. - */ - gintmsk.b.nptxfempty = 1; - dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32); - } else { - /* - * Move the QH from the periodic queued schedule to - * the periodic assigned schedule. This allows the - * halt to be queued when the periodic schedule is - * processed. - */ - list_move(&hc->qh->qh_list_entry, - &hcd->periodic_sched_assigned); - - /* - * Make sure the Periodic Tx FIFO Empty interrupt is - * enabled so that the periodic schedule will be - * processed. - */ - gintmsk.b.ptxfempty = 1; - dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32); - } - } -} - -/** - * Performs common cleanup for non-periodic transfers after a Transfer - * Complete interrupt. This function should be called after any endpoint type - * specific handling is finished to release the host channel. - */ -static void complete_non_periodic_xfer(dwc_otg_hcd_t *hcd, - dwc_hc_t *hc, - dwc_otg_hc_regs_t *hc_regs, - dwc_otg_qtd_t *qtd, - dwc_otg_halt_status_e halt_status) -{ - hcint_data_t hcint; - - qtd->error_count = 0; - - hcint.d32 = dwc_read_reg32(&hc_regs->hcint); - if (hcint.b.nyet) { - /* - * Got a NYET on the last transaction of the transfer. This - * means that the endpoint should be in the PING state at the - * beginning of the next transfer. - */ - hc->qh->ping_state = 1; - clear_hc_int(hc_regs, nyet); - } - - /* - * Always halt and release the host channel to make it available for - * more transfers. There may still be more phases for a control - * transfer or more data packets for a bulk transfer at this point, - * but the host channel is still halted. A channel will be reassigned - * to the transfer when the non-periodic schedule is processed after - * the channel is released. This allows transactions to be queued - * properly via dwc_otg_hcd_queue_transactions, which also enables the - * Tx FIFO Empty interrupt if necessary. - */ - if (hc->ep_is_in) { - /* - * IN transfers in Slave mode require an explicit disable to - * halt the channel. (In DMA mode, this call simply releases - * the channel.) - */ - halt_channel(hcd, hc, qtd, halt_status); - } else { - /* - * The channel is automatically disabled by the core for OUT - * transfers in Slave mode. - */ - release_channel(hcd, hc, qtd, halt_status); - } -} - -/** - * Performs common cleanup for periodic transfers after a Transfer Complete - * interrupt. This function should be called after any endpoint type specific - * handling is finished to release the host channel. - */ -static void complete_periodic_xfer(dwc_otg_hcd_t *hcd, - dwc_hc_t *hc, - dwc_otg_hc_regs_t *hc_regs, - dwc_otg_qtd_t *qtd, - dwc_otg_halt_status_e halt_status) -{ - hctsiz_data_t hctsiz; - qtd->error_count = 0; - - hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); - if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) { - /* Core halts channel in these cases. */ - release_channel(hcd, hc, qtd, halt_status); - } else { - /* Flush any outstanding requests from the Tx queue. */ - halt_channel(hcd, hc, qtd, halt_status); - } -} - -/** - * Handles a host channel Transfer Complete interrupt. This handler may be - * called in either DMA mode or Slave mode. - */ -static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t *hcd, - dwc_hc_t *hc, - dwc_otg_hc_regs_t *hc_regs, - dwc_otg_qtd_t *qtd) -{ - int urb_xfer_done; - dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE; - struct urb *urb = qtd->urb; - int pipe_type = usb_pipetype(urb->pipe); - - DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " - "Transfer Complete--\n", hc->hc_num); - - /* - * Handle xfer complete on CSPLIT. - */ - if (hc->qh->do_split) { - qtd->complete_split = 0; - } - - /* Update the QTD and URB states. */ - switch (pipe_type) { - case PIPE_CONTROL: - switch (qtd->control_phase) { - case DWC_OTG_CONTROL_SETUP: - if (urb->transfer_buffer_length > 0) { - qtd->control_phase = DWC_OTG_CONTROL_DATA; - } else { - qtd->control_phase = DWC_OTG_CONTROL_STATUS; - } - DWC_DEBUGPL(DBG_HCDV, " Control setup transaction done\n"); - halt_status = DWC_OTG_HC_XFER_COMPLETE; - break; - case DWC_OTG_CONTROL_DATA: { - urb_xfer_done = update_urb_state_xfer_comp(hc, hc_regs, urb, qtd); - if (urb_xfer_done) { - qtd->control_phase = DWC_OTG_CONTROL_STATUS; - DWC_DEBUGPL(DBG_HCDV, " Control data transfer done\n"); - } else { - save_data_toggle(hc, hc_regs, qtd); - } - halt_status = DWC_OTG_HC_XFER_COMPLETE; - break; - } - case DWC_OTG_CONTROL_STATUS: - DWC_DEBUGPL(DBG_HCDV, " Control transfer complete\n"); - if (urb->status == -EINPROGRESS) { - urb->status = 0; - } - dwc_otg_hcd_complete_urb(hcd, urb, urb->status); - halt_status = DWC_OTG_HC_XFER_URB_COMPLETE; - break; - } - - complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status); - break; - case PIPE_BULK: - DWC_DEBUGPL(DBG_HCDV, " Bulk transfer complete\n"); - urb_xfer_done = update_urb_state_xfer_comp(hc, hc_regs, urb, qtd); - if (urb_xfer_done) { - dwc_otg_hcd_complete_urb(hcd, urb, urb->status); - halt_status = DWC_OTG_HC_XFER_URB_COMPLETE; - } else { - halt_status = DWC_OTG_HC_XFER_COMPLETE; - } - - save_data_toggle(hc, hc_regs, qtd); - complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status); - break; - case PIPE_INTERRUPT: - DWC_DEBUGPL(DBG_HCDV, " Interrupt transfer complete\n"); - update_urb_state_xfer_comp(hc, hc_regs, urb, qtd); - - /* - * Interrupt URB is done on the first transfer complete - * interrupt. - */ - dwc_otg_hcd_complete_urb(hcd, urb, urb->status); - save_data_toggle(hc, hc_regs, qtd); - complete_periodic_xfer(hcd, hc, hc_regs, qtd, - DWC_OTG_HC_XFER_URB_COMPLETE); - break; - case PIPE_ISOCHRONOUS: - DWC_DEBUGPL(DBG_HCDV, " Isochronous transfer complete\n"); - if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) { - halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd, - DWC_OTG_HC_XFER_COMPLETE); - } - complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status); - break; - } - - disable_hc_int(hc_regs, xfercompl); - - return 1; -} - -/** - * Handles a host channel STALL interrupt. This handler may be called in - * either DMA mode or Slave mode. - */ -static int32_t handle_hc_stall_intr(dwc_otg_hcd_t *hcd, - dwc_hc_t *hc, - dwc_otg_hc_regs_t *hc_regs, - dwc_otg_qtd_t *qtd) -{ - struct urb *urb = qtd->urb; - int pipe_type = usb_pipetype(urb->pipe); - - DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " - "STALL Received--\n", hc->hc_num); - - if (pipe_type == PIPE_CONTROL) { - dwc_otg_hcd_complete_urb(hcd, urb, -EPIPE); - } - - if (pipe_type == PIPE_BULK || pipe_type == PIPE_INTERRUPT) { - dwc_otg_hcd_complete_urb(hcd, urb, -EPIPE); - /* - * USB protocol requires resetting the data toggle for bulk - * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT) - * setup command is issued to the endpoint. Anticipate the - * CLEAR_FEATURE command since a STALL has occurred and reset - * the data toggle now. - */ - hc->qh->data_toggle = 0; - } - - halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL); - - disable_hc_int(hc_regs, stall); - - return 1; -} - -/* - * Updates the state of the URB when a transfer has been stopped due to an - * abnormal condition before the transfer completes. Modifies the - * actual_length field of the URB to reflect the number of bytes that have - * actually been transferred via the host channel. - */ -static void update_urb_state_xfer_intr(dwc_hc_t *hc, - dwc_otg_hc_regs_t *hc_regs, - struct urb *urb, - dwc_otg_qtd_t *qtd, - dwc_otg_halt_status_e halt_status) -{ - uint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd, - halt_status, NULL); - urb->actual_length += bytes_transferred; - -#ifdef DEBUG - { - hctsiz_data_t hctsiz; - hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); - DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n", - __func__, (hc->ep_is_in ? "IN" : "OUT"), hc->hc_num); - DWC_DEBUGPL(DBG_HCDV, " hc->start_pkt_count %d\n", hc->start_pkt_count); - DWC_DEBUGPL(DBG_HCDV, " hctsiz.pktcnt %d\n", hctsiz.b.pktcnt); - DWC_DEBUGPL(DBG_HCDV, " hc->max_packet %d\n", hc->max_packet); - DWC_DEBUGPL(DBG_HCDV, " bytes_transferred %d\n", bytes_transferred); - DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n", urb->actual_length); - DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n", - urb->transfer_buffer_length); - } -#endif -} - -/** - * Handles a host channel NAK interrupt. This handler may be called in either - * DMA mode or Slave mode. - */ -static int32_t handle_hc_nak_intr(dwc_otg_hcd_t *hcd, - dwc_hc_t *hc, - dwc_otg_hc_regs_t *hc_regs, - dwc_otg_qtd_t *qtd) -{ - DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " - "NAK Received--\n", hc->hc_num); - - /* - * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and - * interrupt. Re-start the SSPLIT transfer. - */ - if (hc->do_split) { - if (hc->complete_split) { - qtd->error_count = 0; - } - qtd->complete_split = 0; - halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK); - goto handle_nak_done; - } - - switch (usb_pipetype(qtd->urb->pipe)) { - case PIPE_CONTROL: - case PIPE_BULK: - if (hcd->core_if->dma_enable && hc->ep_is_in) { - /* - * NAK interrupts are enabled on bulk/control IN - * transfers in DMA mode for the sole purpose of - * resetting the error count after a transaction error - * occurs. The core will continue transferring data. - */ - qtd->error_count = 0; - goto handle_nak_done; - } - - /* - * NAK interrupts normally occur during OUT transfers in DMA - * or Slave mode. For IN transfers, more requests will be - * queued as request queue space is available. - */ - qtd->error_count = 0; - - if (!hc->qh->ping_state) { - update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, - qtd, DWC_OTG_HC_XFER_NAK); - save_data_toggle(hc, hc_regs, qtd); - if (qtd->urb->dev->speed == USB_SPEED_HIGH) { - hc->qh->ping_state = 1; - } - } - - /* - * Halt the channel so the transfer can be re-started from - * the appropriate point or the PING protocol will - * start/continue. - */ - halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK); - break; - case PIPE_INTERRUPT: - qtd->error_count = 0; - halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK); - break; - case PIPE_ISOCHRONOUS: - /* Should never get called for isochronous transfers. */ - BUG(); - break; - } - - handle_nak_done: - disable_hc_int(hc_regs, nak); - - return 1; -} - -/** - * Handles a host channel ACK interrupt. This interrupt is enabled when - * performing the PING protocol in Slave mode, when errors occur during - * either Slave mode or DMA mode, and during Start Split transactions. - */ -static int32_t handle_hc_ack_intr(dwc_otg_hcd_t *hcd, - dwc_hc_t *hc, - dwc_otg_hc_regs_t *hc_regs, - dwc_otg_qtd_t *qtd) -{ - DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " - "ACK Received--\n", hc->hc_num); - - if (hc->do_split) { - /* - * Handle ACK on SSPLIT. - * ACK should not occur in CSPLIT. - */ - if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) { - qtd->ssplit_out_xfer_count = hc->xfer_len; - } - if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) { - /* Don't need complete for isochronous out transfers. */ - qtd->complete_split = 1; - } - - /* ISOC OUT */ - if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) { - switch (hc->xact_pos) { - case DWC_HCSPLIT_XACTPOS_ALL: - break; - case DWC_HCSPLIT_XACTPOS_END: - qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL; - qtd->isoc_split_offset = 0; - break; - case DWC_HCSPLIT_XACTPOS_BEGIN: - case DWC_HCSPLIT_XACTPOS_MID: - /* - * For BEGIN or MID, calculate the length for - * the next microframe to determine the correct - * SSPLIT token, either MID or END. - */ - { - struct usb_iso_packet_descriptor *frame_desc; - - frame_desc = &qtd->urb->iso_frame_desc[qtd->isoc_frame_index]; - qtd->isoc_split_offset += 188; - - if ((frame_desc->length - qtd->isoc_split_offset) <= 188) { - qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_END; - } else { - qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_MID; - } - - } - break; - } - } else { - halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK); - } - } else { - qtd->error_count = 0; - - if (hc->qh->ping_state) { - hc->qh->ping_state = 0; - /* - * Halt the channel so the transfer can be re-started - * from the appropriate point. This only happens in - * Slave mode. In DMA mode, the ping_state is cleared - * when the transfer is started because the core - * automatically executes the PING, then the transfer. - */ - halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK); - } - } - - /* - * If the ACK occurred when _not_ in the PING state, let the channel - * continue transferring data after clearing the error count. - */ - - disable_hc_int(hc_regs, ack); - - return 1; -} - -/** - * Handles a host channel NYET interrupt. This interrupt should only occur on - * Bulk and Control OUT endpoints and for complete split transactions. If a - * NYET occurs at the same time as a Transfer Complete interrupt, it is - * handled in the xfercomp interrupt handler, not here. This handler may be - * called in either DMA mode or Slave mode. - */ -static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t *hcd, - dwc_hc_t *hc, - dwc_otg_hc_regs_t *hc_regs, - dwc_otg_qtd_t *qtd) -{ - DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " - "NYET Received--\n", hc->hc_num); - - /* - * NYET on CSPLIT - * re-do the CSPLIT immediately on non-periodic - */ - if (hc->do_split && hc->complete_split) { - if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || - hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { - int frnum = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(hcd)); - - if (dwc_full_frame_num(frnum) != - dwc_full_frame_num(hc->qh->sched_frame)) { - /* - * No longer in the same full speed frame. - * Treat this as a transaction error. - */ -#if 0 - /** @todo Fix system performance so this can - * be treated as an error. Right now complete - * splits cannot be scheduled precisely enough - * due to other system activity, so this error - * occurs regularly in Slave mode. - */ - qtd->error_count++; -#endif - qtd->complete_split = 0; - halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR); - /** @todo add support for isoc release */ - goto handle_nyet_done; - } - } - - halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET); - goto handle_nyet_done; - } - - hc->qh->ping_state = 1; - qtd->error_count = 0; - - update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd, - DWC_OTG_HC_XFER_NYET); - save_data_toggle(hc, hc_regs, qtd); - - /* - * Halt the channel and re-start the transfer so the PING - * protocol will start. - */ - halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET); - -handle_nyet_done: - disable_hc_int(hc_regs, nyet); - return 1; -} - -/** - * Handles a host channel babble interrupt. This handler may be called in - * either DMA mode or Slave mode. - */ -static int32_t handle_hc_babble_intr(dwc_otg_hcd_t *hcd, - dwc_hc_t *hc, - dwc_otg_hc_regs_t *hc_regs, - dwc_otg_qtd_t *qtd) -{ - DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " - "Babble Error--\n", hc->hc_num); - if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) { - dwc_otg_hcd_complete_urb(hcd, qtd->urb, -EOVERFLOW); - halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR); - } else { - dwc_otg_halt_status_e halt_status; - halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd, - DWC_OTG_HC_XFER_BABBLE_ERR); - halt_channel(hcd, hc, qtd, halt_status); - } - disable_hc_int(hc_regs, bblerr); - return 1; -} - -/** - * Handles a host channel AHB error interrupt. This handler is only called in - * DMA mode. - */ -static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t *hcd, - dwc_hc_t *hc, - dwc_otg_hc_regs_t *hc_regs, - dwc_otg_qtd_t *qtd) -{ - hcchar_data_t hcchar; - hcsplt_data_t hcsplt; - hctsiz_data_t hctsiz; - uint32_t hcdma; - struct urb *urb = qtd->urb; - - DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " - "AHB Error--\n", hc->hc_num); - - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt); - hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); - hcdma = dwc_read_reg32(&hc_regs->hcdma); - - DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num); - DWC_ERROR(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32); - DWC_ERROR(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma); - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n"); - DWC_ERROR(" Device address: %d\n", usb_pipedevice(urb->pipe)); - DWC_ERROR(" Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe), - (usb_pipein(urb->pipe) ? "IN" : "OUT")); - DWC_ERROR(" Endpoint type: %s\n", - ({char *pipetype; - switch (usb_pipetype(urb->pipe)) { - case PIPE_CONTROL: pipetype = "CONTROL"; break; - case PIPE_BULK: pipetype = "BULK"; break; - case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break; - case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break; - default: pipetype = "UNKNOWN"; break; - }; pipetype;})); - DWC_ERROR(" Speed: %s\n", - ({char *speed; - switch (urb->dev->speed) { - case USB_SPEED_HIGH: speed = "HIGH"; break; - case USB_SPEED_FULL: speed = "FULL"; break; - case USB_SPEED_LOW: speed = "LOW"; break; - default: speed = "UNKNOWN"; break; - }; speed;})); - DWC_ERROR(" Max packet size: %d\n", - usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); - DWC_ERROR(" Data buffer length: %d\n", urb->transfer_buffer_length); - DWC_ERROR(" Transfer buffer: %p, Transfer DMA: %p\n", - urb->transfer_buffer, (void *)urb->transfer_dma); - DWC_ERROR(" Setup buffer: %p, Setup DMA: %p\n", - urb->setup_packet, (void *)urb->setup_dma); - DWC_ERROR(" Interval: %d\n", urb->interval); - - dwc_otg_hcd_complete_urb(hcd, urb, -EIO); - - /* - * Force a channel halt. Don't call halt_channel because that won't - * write to the HCCHARn register in DMA mode to force the halt. - */ - dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR); - - disable_hc_int(hc_regs, ahberr); - return 1; -} - -/** - * Handles a host channel transaction error interrupt. This handler may be - * called in either DMA mode or Slave mode. - */ -static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t *hcd, - dwc_hc_t *hc, - dwc_otg_hc_regs_t *hc_regs, - dwc_otg_qtd_t *qtd) -{ - DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " - "Transaction Error--\n", hc->hc_num); - - switch (usb_pipetype(qtd->urb->pipe)) { - case PIPE_CONTROL: - case PIPE_BULK: - qtd->error_count++; - if (!hc->qh->ping_state) { - update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, - qtd, DWC_OTG_HC_XFER_XACT_ERR); - save_data_toggle(hc, hc_regs, qtd); - if (!hc->ep_is_in && qtd->urb->dev->speed == USB_SPEED_HIGH) { - hc->qh->ping_state = 1; - } - } - - /* - * Halt the channel so the transfer can be re-started from - * the appropriate point or the PING protocol will start. - */ - halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR); - break; - case PIPE_INTERRUPT: - qtd->error_count++; - if (hc->do_split && hc->complete_split) { - qtd->complete_split = 0; - } - halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR); - break; - case PIPE_ISOCHRONOUS: - { - dwc_otg_halt_status_e halt_status; - halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd, - DWC_OTG_HC_XFER_XACT_ERR); - - halt_channel(hcd, hc, qtd, halt_status); - } - break; - } - - disable_hc_int(hc_regs, xacterr); - - return 1; -} - -/** - * Handles a host channel frame overrun interrupt. This handler may be called - * in either DMA mode or Slave mode. - */ -static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t *hcd, - dwc_hc_t *hc, - dwc_otg_hc_regs_t *hc_regs, - dwc_otg_qtd_t *qtd) -{ - DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " - "Frame Overrun--\n", hc->hc_num); - - switch (usb_pipetype(qtd->urb->pipe)) { - case PIPE_CONTROL: - case PIPE_BULK: - break; - case PIPE_INTERRUPT: - halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN); - break; - case PIPE_ISOCHRONOUS: - { - dwc_otg_halt_status_e halt_status; - halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd, - DWC_OTG_HC_XFER_FRAME_OVERRUN); - - halt_channel(hcd, hc, qtd, halt_status); - } - break; - } - - disable_hc_int(hc_regs, frmovrun); - - return 1; -} - -/** - * Handles a host channel data toggle error interrupt. This handler may be - * called in either DMA mode or Slave mode. - */ -static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t *hcd, - dwc_hc_t *hc, - dwc_otg_hc_regs_t *hc_regs, - dwc_otg_qtd_t *qtd) -{ - DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " - "Data Toggle Error--\n", hc->hc_num); - - if (hc->ep_is_in) { - qtd->error_count = 0; - } else { - DWC_ERROR("Data Toggle Error on OUT transfer," - "channel %d\n", hc->hc_num); - } - - disable_hc_int(hc_regs, datatglerr); - - return 1; -} - -#ifdef DEBUG -/** - * This function is for debug only. It checks that a valid halt status is set - * and that HCCHARn.chdis is clear. If there's a problem, corrective action is - * taken and a warning is issued. - * @return 1 if halt status is ok, 0 otherwise. - */ -static inline int halt_status_ok(dwc_otg_hcd_t *hcd, - dwc_hc_t *hc, - dwc_otg_hc_regs_t *hc_regs, - dwc_otg_qtd_t *qtd) -{ - hcchar_data_t hcchar; - hctsiz_data_t hctsiz; - hcint_data_t hcint; - hcintmsk_data_t hcintmsk; - hcsplt_data_t hcsplt; - - if (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) { - /* - * This code is here only as a check. This condition should - * never happen. Ignore the halt if it does occur. - */ - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); - hcint.d32 = dwc_read_reg32(&hc_regs->hcint); - hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk); - hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt); - DWC_WARN("%s: hc->halt_status == DWC_OTG" - "channel %d, hcchar 0x%08x, hctsiz 0x%08x, " - "hcint 0x%08x, hcintmsk 0x%08x, " - "hcsplt 0x%08x, qtd->complete_split %d\n", - __func__, hc->hc_num, hcchar.d32, hctsiz.d32, - hcint.d32, hcintmsk.d32, - hcsplt.d32, qtd->complete_split); - - DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n", - __func__, hc->hc_num); - DWC_WARN("\n"); - clear_hc_int(hc_regs, chhltd); - return 0; - } - - /* - * This code is here only as a check. hcchar.chdis should - * never be set when the halt interrupt occurs. Halt the - * channel again if it does occur. - */ - hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); - if (hcchar.b.chdis) { - DWC_WARN("%s: hcchar.chdis set unexpectedly, " - "hcchar 0x%08x, trying to halt again\n", - __func__, hcchar.d32); - clear_hc_int(hc_regs, chhltd); - hc->halt_pending = 0; - halt_channel(hcd, hc, qtd, hc->halt_status); - return 0; - } - - return 1; -} -#endif - -/** - * Handles a host Channel Halted interrupt in DMA mode. This handler - * determines the reason the channel halted and proceeds accordingly. - */ -static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t *hcd, - dwc_hc_t *hc, - dwc_otg_hc_regs_t *hc_regs, - dwc_otg_qtd_t *qtd) -{ - hcint_data_t hcint; - hcintmsk_data_t hcintmsk; - int out_nak_enh = 0; - - /* For core with OUT NAK enhancement, the flow for high- - * speed CONTROL/BULK OUT is handled a little differently. - */ - if (hcd->core_if->snpsid >= 0x4F54271A) { - if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in && - (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL || - hc->ep_type == DWC_OTG_EP_TYPE_BULK)) { - printk(KERN_DEBUG "OUT NAK enhancement enabled\n"); - out_nak_enh = 1; - } else { - printk(KERN_DEBUG "OUT NAK enhancement disabled, not HS Ctrl/Bulk OUT EP\n"); - } - } else { -// printk(KERN_DEBUG "OUT NAK enhancement disabled, no core support\n"); - } - - if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE || - hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR) { - /* - * Just release the channel. A dequeue can happen on a - * transfer timeout. In the case of an AHB Error, the channel - * was forced to halt because there's no way to gracefully - * recover. - */ - release_channel(hcd, hc, qtd, hc->halt_status); - return; - } - - /* Read the HCINTn register to determine the cause for the halt. */ - hcint.d32 = dwc_read_reg32(&hc_regs->hcint); - hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk); - - if (hcint.b.xfercomp) { - /** @todo This is here because of a possible hardware bug. Spec - * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT - * interrupt w/ACK bit set should occur, but I only see the - * XFERCOMP bit, even with it masked out. This is a workaround - * for that behavior. Should fix this when hardware is fixed. - */ - if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) { - handle_hc_ack_intr(hcd, hc, hc_regs, qtd); - } - handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd); - } else if (hcint.b.stall) { - handle_hc_stall_intr(hcd, hc, hc_regs, qtd); - } else if (hcint.b.xacterr) { - if (out_nak_enh) { - if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) { - printk(KERN_DEBUG "XactErr with NYET/NAK/ACK\n"); - qtd->error_count = 0; - } else { - printk(KERN_DEBUG "XactErr without NYET/NAK/ACK\n"); - } - } - - /* - * Must handle xacterr before nak or ack. Could get a xacterr - * at the same time as either of these on a BULK/CONTROL OUT - * that started with a PING. The xacterr takes precedence. - */ - handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd); - } else if (!out_nak_enh) { - if (hcint.b.nyet) { - /* - * Must handle nyet before nak or ack. Could get a nyet at the - * same time as either of those on a BULK/CONTROL OUT that - * started with a PING. The nyet takes precedence. - */ - handle_hc_nyet_intr(hcd, hc, hc_regs, qtd); - } else if (hcint.b.bblerr) { - handle_hc_babble_intr(hcd, hc, hc_regs, qtd); - } else if (hcint.b.frmovrun) { - handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd); - } else if (hcint.b.nak && !hcintmsk.b.nak) { - /* - * If nak is not masked, it's because a non-split IN transfer - * is in an error state. In that case, the nak is handled by - * the nak interrupt handler, not here. Handle nak here for - * BULK/CONTROL OUT transfers, which halt on a NAK to allow - * rewinding the buffer pointer. - */ - handle_hc_nak_intr(hcd, hc, hc_regs, qtd); - } else if (hcint.b.ack && !hcintmsk.b.ack) { - /* - * If ack is not masked, it's because a non-split IN transfer - * is in an error state. In that case, the ack is handled by - * the ack interrupt handler, not here. Handle ack here for - * split transfers. Start splits halt on ACK. - */ - handle_hc_ack_intr(hcd, hc, hc_regs, qtd); - } else { - if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || - hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { - /* - * A periodic transfer halted with no other channel - * interrupts set. Assume it was halted by the core - * because it could not be completed in its scheduled - * (micro)frame. - */ -#ifdef DEBUG - DWC_PRINT("%s: Halt channel %d (assume incomplete periodic transfer)\n", - __func__, hc->hc_num); -#endif - halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE); - } else { - DWC_ERROR("%s: Channel %d, DMA Mode -- ChHltd set, but reason " - "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n", - __func__, hc->hc_num, hcint.d32, - dwc_read_reg32(&hcd->core_if->core_global_regs->gintsts)); - } - } - } else { - printk(KERN_DEBUG "NYET/NAK/ACK/other in non-error case, 0x%08x\n", hcint.d32); - } -} - -/** - * Handles a host channel Channel Halted interrupt. - * - * In slave mode, this handler is called only when the driver specifically - * requests a halt. This occurs during handling other host channel interrupts - * (e.g. nak, xacterr, stall, nyet, etc.). - * - * In DMA mode, this is the interrupt that occurs when the core has finished - * processing a transfer on a channel. Other host channel interrupts (except - * ahberr) are disabled in DMA mode. - */ -static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t *hcd, - dwc_hc_t *hc, - dwc_otg_hc_regs_t *hc_regs, - dwc_otg_qtd_t *qtd) -{ - DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " - "Channel Halted--\n", hc->hc_num); - - if (hcd->core_if->dma_enable) { - handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd); - } else { -#ifdef DEBUG - if (!halt_status_ok(hcd, hc, hc_regs, qtd)) { - return 1; - } -#endif - release_channel(hcd, hc, qtd, hc->halt_status); - } - - return 1; -} - -/** Handles interrupt for a specific Host Channel */ -int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t *dwc_otg_hcd, uint32_t num) -{ - int retval = 0; - hcint_data_t hcint; - hcintmsk_data_t hcintmsk; - dwc_hc_t *hc; - dwc_otg_hc_regs_t *hc_regs; - dwc_otg_qtd_t *qtd; - - DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", num); - - hc = dwc_otg_hcd->hc_ptr_array[num]; - hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num]; - qtd = list_entry(hc->qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); - - hcint.d32 = dwc_read_reg32(&hc_regs->hcint); - hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk); - DWC_DEBUGPL(DBG_HCDV, " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n", - hcint.d32, hcintmsk.d32, (hcint.d32 & hcintmsk.d32)); - hcint.d32 = hcint.d32 & hcintmsk.d32; - - if (!dwc_otg_hcd->core_if->dma_enable) { - if (hcint.b.chhltd && hcint.d32 != 0x2) { - hcint.b.chhltd = 0; - } - } - - if (hcint.b.xfercomp) { - retval |= handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd); - /* - * If NYET occurred at same time as Xfer Complete, the NYET is - * handled by the Xfer Complete interrupt handler. Don't want - * to call the NYET interrupt handler in this case. - */ - hcint.b.nyet = 0; - } - if (hcint.b.chhltd) { - retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd); - } - if (hcint.b.ahberr) { - retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd); - } - if (hcint.b.stall) { - retval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd); - } - if (hcint.b.nak) { - retval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd); - } - if (hcint.b.ack) { - retval |= handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd); - } - if (hcint.b.nyet) { - retval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd); - } - if (hcint.b.xacterr) { - retval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd); - } - if (hcint.b.bblerr) { - retval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd); - } - if (hcint.b.frmovrun) { - retval |= handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd); - } - if (hcint.b.datatglerr) { - retval |= handle_hc_datatglerr_intr(dwc_otg_hcd, hc, hc_regs, qtd); - } - - return retval; -} - -#endif /* DWC_DEVICE_ONLY */ diff --git a/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c b/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c deleted file mode 100644 index cfb1f16410..0000000000 --- a/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c +++ /dev/null @@ -1,684 +0,0 @@ -/* ========================================================================== - * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd_queue.c $ - * $Revision: 1.5 $ - * $Date: 2008-12-15 06:51:32 $ - * $Change: 537387 $ - * - * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, - * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless - * otherwise expressly agreed to in writing between Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ -#ifndef DWC_DEVICE_ONLY - -/** - * @file - * - * This file contains the functions to manage Queue Heads and Queue - * Transfer Descriptors. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "dwc_otg_driver.h" -#include "dwc_otg_hcd.h" -#include "dwc_otg_regs.h" - -/** - * This function allocates and initializes a QH. - * - * @param hcd The HCD state structure for the DWC OTG controller. - * @param[in] urb Holds the information about the device/endpoint that we need - * to initialize the QH. - * - * @return Returns pointer to the newly allocated QH, or NULL on error. */ -dwc_otg_qh_t *dwc_otg_hcd_qh_create (dwc_otg_hcd_t *hcd, struct urb *urb) -{ - dwc_otg_qh_t *qh; - - /* Allocate memory */ - /** @todo add memflags argument */ - qh = dwc_otg_hcd_qh_alloc (); - if (qh == NULL) { - return NULL; - } - - dwc_otg_hcd_qh_init (hcd, qh, urb); - return qh; -} - -/** Free each QTD in the QH's QTD-list then free the QH. QH should already be - * removed from a list. QTD list should already be empty if called from URB - * Dequeue. - * - * @param[in] hcd HCD instance. - * @param[in] qh The QH to free. - */ -void dwc_otg_hcd_qh_free (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) -{ - dwc_otg_qtd_t *qtd; - struct list_head *pos; - unsigned long flags; - - /* Free each QTD in the QTD list */ - SPIN_LOCK_IRQSAVE(&hcd->lock, flags) - for (pos = qh->qtd_list.next; - pos != &qh->qtd_list; - pos = qh->qtd_list.next) - { - list_del (pos); - qtd = dwc_list_to_qtd (pos); - dwc_otg_hcd_qtd_free (qtd); - } - SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags) - - if (qh->dw_align_buf) { - dma_free_coherent((dwc_otg_hcd_to_hcd(hcd))->self.controller, - hcd->core_if->core_params->max_transfer_size, - qh->dw_align_buf, - qh->dw_align_buf_dma); - } - - kfree (qh); - return; -} - -/** Initializes a QH structure. - * - * @param[in] hcd The HCD state structure for the DWC OTG controller. - * @param[in] qh The QH to init. - * @param[in] urb Holds the information about the device/endpoint that we need - * to initialize the QH. */ -#define SCHEDULE_SLOP 10 -void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, struct urb *urb) -{ - char *speed, *type; - memset (qh, 0, sizeof (dwc_otg_qh_t)); - - /* Initialize QH */ - switch (usb_pipetype(urb->pipe)) { - case PIPE_CONTROL: - qh->ep_type = USB_ENDPOINT_XFER_CONTROL; - break; - case PIPE_BULK: - qh->ep_type = USB_ENDPOINT_XFER_BULK; - break; - case PIPE_ISOCHRONOUS: - qh->ep_type = USB_ENDPOINT_XFER_ISOC; - break; - case PIPE_INTERRUPT: - qh->ep_type = USB_ENDPOINT_XFER_INT; - break; - } - - qh->ep_is_in = usb_pipein(urb->pipe) ? 1 : 0; - - qh->data_toggle = DWC_OTG_HC_PID_DATA0; - qh->maxp = usb_maxpacket(urb->dev, urb->pipe, !(usb_pipein(urb->pipe))); - INIT_LIST_HEAD(&qh->qtd_list); - INIT_LIST_HEAD(&qh->qh_list_entry); - qh->channel = NULL; - - /* FS/LS Enpoint on HS Hub - * NOT virtual root hub */ - qh->do_split = 0; - if (((urb->dev->speed == USB_SPEED_LOW) || - (urb->dev->speed == USB_SPEED_FULL)) && - (urb->dev->tt) && (urb->dev->tt->hub) && (urb->dev->tt->hub->devnum != 1)) - { - DWC_DEBUGPL(DBG_HCD, "QH init: EP %d: TT found at hub addr %d, for port %d\n", - usb_pipeendpoint(urb->pipe), urb->dev->tt->hub->devnum, - urb->dev->ttport); - qh->do_split = 1; - } - - if (qh->ep_type == USB_ENDPOINT_XFER_INT || - qh->ep_type == USB_ENDPOINT_XFER_ISOC) { - /* Compute scheduling parameters once and save them. */ - hprt0_data_t hprt; - - /** @todo Account for split transfers in the bus time. */ - int bytecount = dwc_hb_mult(qh->maxp) * dwc_max_packet(qh->maxp); - - /* FIXME: work-around patch by Steven */ - qh->usecs = NS_TO_US(usb_calc_bus_time(urb->dev->speed, - usb_pipein(urb->pipe), - (qh->ep_type == USB_ENDPOINT_XFER_ISOC), - bytecount)); - - /* Start in a slightly future (micro)frame. */ - qh->sched_frame = dwc_frame_num_inc(hcd->frame_number, - SCHEDULE_SLOP); - qh->interval = urb->interval; -#if 0 - /* Increase interrupt polling rate for debugging. */ - if (qh->ep_type == USB_ENDPOINT_XFER_INT) { - qh->interval = 8; - } -#endif - hprt.d32 = dwc_read_reg32(hcd->core_if->host_if->hprt0); - if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) && - ((urb->dev->speed == USB_SPEED_LOW) || - (urb->dev->speed == USB_SPEED_FULL))) { - qh->interval *= 8; - qh->sched_frame |= 0x7; - qh->start_split_frame = qh->sched_frame; - } - - } - - DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n"); - DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", qh); - DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n", - urb->dev->devnum); - DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n", - usb_pipeendpoint(urb->pipe), - usb_pipein(urb->pipe) == USB_DIR_IN ? "IN" : "OUT"); - - switch(urb->dev->speed) { - case USB_SPEED_LOW: - speed = "low"; - break; - case USB_SPEED_FULL: - speed = "full"; - break; - case USB_SPEED_HIGH: - speed = "high"; - break; - default: - speed = "?"; - break; - } - DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n", speed); - - switch (qh->ep_type) { - case USB_ENDPOINT_XFER_ISOC: - type = "isochronous"; - break; - case USB_ENDPOINT_XFER_INT: - type = "interrupt"; - break; - case USB_ENDPOINT_XFER_CONTROL: - type = "control"; - break; - case USB_ENDPOINT_XFER_BULK: - type = "bulk"; - break; - default: - type = "?"; - break; - } - DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n",type); - -#ifdef DEBUG - if (qh->ep_type == USB_ENDPOINT_XFER_INT) { - DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n", - qh->usecs); - DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n", - qh->interval); - } -#endif - qh->dw_align_buf = NULL; - return; -} - -/** - * Checks that a channel is available for a periodic transfer. - * - * @return 0 if successful, negative error code otherise. - */ -static int periodic_channel_available(dwc_otg_hcd_t *hcd) -{ - /* - * Currently assuming that there is a dedicated host channnel for each - * periodic transaction plus at least one host channel for - * non-periodic transactions. - */ - int status; - int num_channels; - - num_channels = hcd->core_if->core_params->host_channels; - if ((hcd->periodic_channels + hcd->non_periodic_channels < num_channels) && - (hcd->periodic_channels < num_channels - 1)) { - status = 0; - } - else { - DWC_NOTICE("%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n", - __func__, num_channels, hcd->periodic_channels, - hcd->non_periodic_channels); - status = -ENOSPC; - } - - return status; -} - -/** - * Checks that there is sufficient bandwidth for the specified QH in the - * periodic schedule. For simplicity, this calculation assumes that all the - * transfers in the periodic schedule may occur in the same (micro)frame. - * - * @param hcd The HCD state structure for the DWC OTG controller. - * @param qh QH containing periodic bandwidth required. - * - * @return 0 if successful, negative error code otherwise. - */ -static int check_periodic_bandwidth(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) -{ - int status; - uint16_t max_claimed_usecs; - - status = 0; - - if (hcd->core_if->core_params->speed == DWC_SPEED_PARAM_HIGH) { - /* - * High speed mode. - * Max periodic usecs is 80% x 125 usec = 100 usec. - */ - max_claimed_usecs = 100 - qh->usecs; - } else { - /* - * Full speed mode. - * Max periodic usecs is 90% x 1000 usec = 900 usec. - */ - max_claimed_usecs = 900 - qh->usecs; - } - - if (hcd->periodic_usecs > max_claimed_usecs) { - DWC_NOTICE("%s: already claimed usecs %d, required usecs %d\n", - __func__, hcd->periodic_usecs, qh->usecs); - status = -ENOSPC; - } - - return status; -} - -/** - * Checks that the max transfer size allowed in a host channel is large enough - * to handle the maximum data transfer in a single (micro)frame for a periodic - * transfer. - * - * @param hcd The HCD state structure for the DWC OTG controller. - * @param qh QH for a periodic endpoint. - * - * @return 0 if successful, negative error code otherwise. - */ -static int check_max_xfer_size(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) -{ - int status; - uint32_t max_xfer_size; - uint32_t max_channel_xfer_size; - - status = 0; - - max_xfer_size = dwc_max_packet(qh->maxp) * dwc_hb_mult(qh->maxp); - max_channel_xfer_size = hcd->core_if->core_params->max_transfer_size; - - if (max_xfer_size > max_channel_xfer_size) { - DWC_NOTICE("%s: Periodic xfer length %d > " - "max xfer length for channel %d\n", - __func__, max_xfer_size, max_channel_xfer_size); - status = -ENOSPC; - } - - return status; -} - -/** - * Schedules an interrupt or isochronous transfer in the periodic schedule. - * - * @param hcd The HCD state structure for the DWC OTG controller. - * @param qh QH for the periodic transfer. The QH should already contain the - * scheduling information. - * - * @return 0 if successful, negative error code otherwise. - */ -static int schedule_periodic(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) -{ - int status = 0; - - status = periodic_channel_available(hcd); - if (status) { - DWC_NOTICE("%s: No host channel available for periodic " - "transfer.\n", __func__); - return status; - } - - status = check_periodic_bandwidth(hcd, qh); - if (status) { - DWC_NOTICE("%s: Insufficient periodic bandwidth for " - "periodic transfer.\n", __func__); - return status; - } - - status = check_max_xfer_size(hcd, qh); - if (status) { - DWC_NOTICE("%s: Channel max transfer size too small " - "for periodic transfer.\n", __func__); - return status; - } - - /* Always start in the inactive schedule. */ - list_add_tail(&qh->qh_list_entry, &hcd->periodic_sched_inactive); - - /* Reserve the periodic channel. */ - hcd->periodic_channels++; - - /* Update claimed usecs per (micro)frame. */ - hcd->periodic_usecs += qh->usecs; - - /* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */ - hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_allocated += qh->usecs / qh->interval; - if (qh->ep_type == USB_ENDPOINT_XFER_INT) { - hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_int_reqs++; - DWC_DEBUGPL(DBG_HCD, "Scheduled intr: qh %p, usecs %d, period %d\n", - qh, qh->usecs, qh->interval); - } else { - hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_isoc_reqs++; - DWC_DEBUGPL(DBG_HCD, "Scheduled isoc: qh %p, usecs %d, period %d\n", - qh, qh->usecs, qh->interval); - } - - return status; -} - -/** - * This function adds a QH to either the non periodic or periodic schedule if - * it is not already in the schedule. If the QH is already in the schedule, no - * action is taken. - * - * @return 0 if successful, negative error code otherwise. - */ -int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) -{ - unsigned long flags; - int status = 0; - - SPIN_LOCK_IRQSAVE(&hcd->lock, flags) - - if (!list_empty(&qh->qh_list_entry)) { - /* QH already in a schedule. */ - goto done; - } - - /* Add the new QH to the appropriate schedule */ - if (dwc_qh_is_non_per(qh)) { - /* Always start in the inactive schedule. */ - list_add_tail(&qh->qh_list_entry, &hcd->non_periodic_sched_inactive); - } else { - status = schedule_periodic(hcd, qh); - } - - done: - SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags) - - return status; -} - -/** - * Removes an interrupt or isochronous transfer from the periodic schedule. - * - * @param hcd The HCD state structure for the DWC OTG controller. - * @param qh QH for the periodic transfer. - */ -static void deschedule_periodic(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) -{ - list_del_init(&qh->qh_list_entry); - - /* Release the periodic channel reservation. */ - hcd->periodic_channels--; - - /* Update claimed usecs per (micro)frame. */ - hcd->periodic_usecs -= qh->usecs; - - /* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */ - hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_allocated -= qh->usecs / qh->interval; - - if (qh->ep_type == USB_ENDPOINT_XFER_INT) { - hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_int_reqs--; - DWC_DEBUGPL(DBG_HCD, "Descheduled intr: qh %p, usecs %d, period %d\n", - qh, qh->usecs, qh->interval); - } else { - hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_isoc_reqs--; - DWC_DEBUGPL(DBG_HCD, "Descheduled isoc: qh %p, usecs %d, period %d\n", - qh, qh->usecs, qh->interval); - } -} - -/** - * Removes a QH from either the non-periodic or periodic schedule. Memory is - * not freed. - * - * @param[in] hcd The HCD state structure. - * @param[in] qh QH to remove from schedule. */ -void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) -{ - unsigned long flags; - - SPIN_LOCK_IRQSAVE(&hcd->lock, flags); - - if (list_empty(&qh->qh_list_entry)) { - /* QH is not in a schedule. */ - goto done; - } - - if (dwc_qh_is_non_per(qh)) { - if (hcd->non_periodic_qh_ptr == &qh->qh_list_entry) { - hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next; - } - list_del_init(&qh->qh_list_entry); - } else { - deschedule_periodic(hcd, qh); - } - - done: - SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags) -} - -/** - * Deactivates a QH. For non-periodic QHs, removes the QH from the active - * non-periodic schedule. The QH is added to the inactive non-periodic - * schedule if any QTDs are still attached to the QH. - * - * For periodic QHs, the QH is removed from the periodic queued schedule. If - * there are any QTDs still attached to the QH, the QH is added to either the - * periodic inactive schedule or the periodic ready schedule and its next - * scheduled frame is calculated. The QH is placed in the ready schedule if - * the scheduled frame has been reached already. Otherwise it's placed in the - * inactive schedule. If there are no QTDs attached to the QH, the QH is - * completely removed from the periodic schedule. - */ -void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int sched_next_periodic_split) -{ - unsigned long flags; - SPIN_LOCK_IRQSAVE(&hcd->lock, flags); - - if (dwc_qh_is_non_per(qh)) { - dwc_otg_hcd_qh_remove(hcd, qh); - if (!list_empty(&qh->qtd_list)) { - /* Add back to inactive non-periodic schedule. */ - dwc_otg_hcd_qh_add(hcd, qh); - } - } else { - uint16_t frame_number = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(hcd)); - - if (qh->do_split) { - /* Schedule the next continuing periodic split transfer */ - if (sched_next_periodic_split) { - - qh->sched_frame = frame_number; - if (dwc_frame_num_le(frame_number, - dwc_frame_num_inc(qh->start_split_frame, 1))) { - /* - * Allow one frame to elapse after start - * split microframe before scheduling - * complete split, but DONT if we are - * doing the next start split in the - * same frame for an ISOC out. - */ - if ((qh->ep_type != USB_ENDPOINT_XFER_ISOC) || (qh->ep_is_in != 0)) { - qh->sched_frame = dwc_frame_num_inc(qh->sched_frame, 1); - } - } - } else { - qh->sched_frame = dwc_frame_num_inc(qh->start_split_frame, - qh->interval); - if (dwc_frame_num_le(qh->sched_frame, frame_number)) { - qh->sched_frame = frame_number; - } - qh->sched_frame |= 0x7; - qh->start_split_frame = qh->sched_frame; - } - } else { - qh->sched_frame = dwc_frame_num_inc(qh->sched_frame, qh->interval); - if (dwc_frame_num_le(qh->sched_frame, frame_number)) { - qh->sched_frame = frame_number; - } - } - - if (list_empty(&qh->qtd_list)) { - dwc_otg_hcd_qh_remove(hcd, qh); - } else { - /* - * Remove from periodic_sched_queued and move to - * appropriate queue. - */ - if (qh->sched_frame == frame_number) { - list_move(&qh->qh_list_entry, - &hcd->periodic_sched_ready); - } else { - list_move(&qh->qh_list_entry, - &hcd->periodic_sched_inactive); - } - } - } - - SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags); -} - -/** - * This function allocates and initializes a QTD. - * - * @param[in] urb The URB to create a QTD from. Each URB-QTD pair will end up - * pointing to each other so each pair should have a unique correlation. - * - * @return Returns pointer to the newly allocated QTD, or NULL on error. */ -dwc_otg_qtd_t *dwc_otg_hcd_qtd_create (struct urb *urb) -{ - dwc_otg_qtd_t *qtd; - - qtd = dwc_otg_hcd_qtd_alloc (); - if (qtd == NULL) { - return NULL; - } - - dwc_otg_hcd_qtd_init (qtd, urb); - return qtd; -} - -/** - * Initializes a QTD structure. - * - * @param[in] qtd The QTD to initialize. - * @param[in] urb The URB to use for initialization. */ -void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *qtd, struct urb *urb) -{ - memset (qtd, 0, sizeof (dwc_otg_qtd_t)); - qtd->urb = urb; - if (usb_pipecontrol(urb->pipe)) { - /* - * The only time the QTD data toggle is used is on the data - * phase of control transfers. This phase always starts with - * DATA1. - */ - qtd->data_toggle = DWC_OTG_HC_PID_DATA1; - qtd->control_phase = DWC_OTG_CONTROL_SETUP; - } - - /* start split */ - qtd->complete_split = 0; - qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL; - qtd->isoc_split_offset = 0; - - /* Store the qtd ptr in the urb to reference what QTD. */ - urb->hcpriv = qtd; - return; -} - -/** - * This function adds a QTD to the QTD-list of a QH. It will find the correct - * QH to place the QTD into. If it does not find a QH, then it will create a - * new QH. If the QH to which the QTD is added is not currently scheduled, it - * is placed into the proper schedule based on its EP type. - * - * @param[in] qtd The QTD to add - * @param[in] dwc_otg_hcd The DWC HCD structure - * - * @return 0 if successful, negative error code otherwise. - */ -int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *qtd, - dwc_otg_hcd_t *dwc_otg_hcd) -{ - struct usb_host_endpoint *ep; - dwc_otg_qh_t *qh; - unsigned long flags; - int retval = 0; - - struct urb *urb = qtd->urb; - - SPIN_LOCK_IRQSAVE(&dwc_otg_hcd->lock, flags); - - /* - * Get the QH which holds the QTD-list to insert to. Create QH if it - * doesn't exist. - */ - ep = dwc_urb_to_endpoint(urb); - qh = (dwc_otg_qh_t *)ep->hcpriv; - if (qh == NULL) { - qh = dwc_otg_hcd_qh_create (dwc_otg_hcd, urb); - if (qh == NULL) { - goto done; - } - ep->hcpriv = qh; - } - - retval = dwc_otg_hcd_qh_add(dwc_otg_hcd, qh); - if (retval == 0) { - list_add_tail(&qtd->qtd_list_entry, &qh->qtd_list); - } - - done: - SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags); - - return retval; -} - -#endif /* DWC_DEVICE_ONLY */ diff --git a/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_pcd.c b/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_pcd.c deleted file mode 100644 index 030a3f2856..0000000000 --- a/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_pcd.c +++ /dev/null @@ -1,2523 +0,0 @@ -/* ========================================================================== - * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.c $ - * $Revision: 1.5 $ - * $Date: 2008-11-27 09:21:25 $ - * $Change: 1115682 $ - * - * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, - * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless - * otherwise expressly agreed to in writing between Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ -#ifndef DWC_HOST_ONLY - -/** @file - * This file implements the Peripheral Controller Driver. - * - * The Peripheral Controller Driver (PCD) is responsible for - * translating requests from the Function Driver into the appropriate - * actions on the DWC_otg controller. It isolates the Function Driver - * from the specifics of the controller by providing an API to the - * Function Driver. - * - * The Peripheral Controller Driver for Linux will implement the - * Gadget API, so that the existing Gadget drivers can be used. - * (Gadget Driver is the Linux terminology for a Function Driver.) - * - * The Linux Gadget API is defined in the header file - * . The USB EP operations API is - * defined in the structure usb_ep_ops and the USB - * Controller API is defined in the structure - * usb_gadget_ops. - * - * An important function of the PCD is managing interrupts generated - * by the DWC_otg controller. The implementation of the DWC_otg device - * mode interrupt service routines is in dwc_otg_pcd_intr.c. - * - * @todo Add Device Mode test modes (Test J mode, Test K mode, etc). - * @todo Does it work when the request size is greater than DEPTSIZ - * transfer size - * - */ - - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21) -# include -#else -# include -#endif - -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) -#include -#else -#include -#endif - -#include "dwc_otg_driver.h" -#include "dwc_otg_pcd.h" - - -/** - * Static PCD pointer for use in usb_gadget_register_driver and - * usb_gadget_unregister_driver. Initialized in dwc_otg_pcd_init. - */ -static dwc_otg_pcd_t *s_pcd = 0; - - -/* Display the contents of the buffer */ -extern void dump_msg(const u8 *buf, unsigned int length); - - -/** - * This function completes a request. It call's the request call back. - */ -void dwc_otg_request_done(dwc_otg_pcd_ep_t *ep, dwc_otg_pcd_request_t *req, - int status) -{ - unsigned stopped = ep->stopped; - - DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, ep); - list_del_init(&req->queue); - - if (req->req.status == -EINPROGRESS) { - req->req.status = status; - } else { - status = req->req.status; - } - - /* don't modify queue heads during completion callback */ - ep->stopped = 1; - SPIN_UNLOCK(&ep->pcd->lock); - req->req.complete(&ep->ep, &req->req); - SPIN_LOCK(&ep->pcd->lock); - - if (ep->pcd->request_pending > 0) { - --ep->pcd->request_pending; - } - - ep->stopped = stopped; -} - -/** - * This function terminates all the requsts in the EP request queue. - */ -void dwc_otg_request_nuke(dwc_otg_pcd_ep_t *ep) -{ - dwc_otg_pcd_request_t *req; - - ep->stopped = 1; - - /* called with irqs blocked?? */ - while (!list_empty(&ep->queue)) { - req = list_entry(ep->queue.next, dwc_otg_pcd_request_t, - queue); - dwc_otg_request_done(ep, req, -ESHUTDOWN); - } -} - -/* USB Endpoint Operations */ -/* - * The following sections briefly describe the behavior of the Gadget - * API endpoint operations implemented in the DWC_otg driver - * software. Detailed descriptions of the generic behavior of each of - * these functions can be found in the Linux header file - * include/linux/usb_gadget.h. - * - * The Gadget API provides wrapper functions for each of the function - * pointers defined in usb_ep_ops. The Gadget Driver calls the wrapper - * function, which then calls the underlying PCD function. The - * following sections are named according to the wrapper - * functions. Within each section, the corresponding DWC_otg PCD - * function name is specified. - * - */ - -/** - * This function assigns periodic Tx FIFO to an periodic EP - * in shared Tx FIFO mode - */ -static uint32_t assign_perio_tx_fifo(dwc_otg_core_if_t *core_if) -{ - uint32_t PerTxMsk = 1; - int i; - for(i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; ++i) - { - if((PerTxMsk & core_if->p_tx_msk) == 0) { - core_if->p_tx_msk |= PerTxMsk; - return i + 1; - } - PerTxMsk <<= 1; - } - return 0; -} -/** - * This function releases periodic Tx FIFO - * in shared Tx FIFO mode - */ -static void release_perio_tx_fifo(dwc_otg_core_if_t *core_if, uint32_t fifo_num) -{ - core_if->p_tx_msk = (core_if->p_tx_msk & (1 << (fifo_num - 1))) ^ core_if->p_tx_msk; -} -/** - * This function assigns periodic Tx FIFO to an periodic EP - * in shared Tx FIFO mode - */ -static uint32_t assign_tx_fifo(dwc_otg_core_if_t *core_if) -{ - uint32_t TxMsk = 1; - int i; - - for(i = 0; i < core_if->hwcfg4.b.num_in_eps; ++i) - { - if((TxMsk & core_if->tx_msk) == 0) { - core_if->tx_msk |= TxMsk; - return i + 1; - } - TxMsk <<= 1; - } - return 0; -} -/** - * This function releases periodic Tx FIFO - * in shared Tx FIFO mode - */ -static void release_tx_fifo(dwc_otg_core_if_t *core_if, uint32_t fifo_num) -{ - core_if->tx_msk = (core_if->tx_msk & (1 << (fifo_num - 1))) ^ core_if->tx_msk; -} - -/** - * This function is called by the Gadget Driver for each EP to be - * configured for the current configuration (SET_CONFIGURATION). - * - * This function initializes the dwc_otg_ep_t data structure, and then - * calls dwc_otg_ep_activate. - */ -static int dwc_otg_pcd_ep_enable(struct usb_ep *usb_ep, - const struct usb_endpoint_descriptor *ep_desc) -{ - dwc_otg_pcd_ep_t *ep = 0; - dwc_otg_pcd_t *pcd = 0; - unsigned long flags; - - DWC_DEBUGPL(DBG_PCDV,"%s(%p,%p)\n", __func__, usb_ep, ep_desc); - - ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep); - if (!usb_ep || !ep_desc || ep->desc || - ep_desc->bDescriptorType != USB_DT_ENDPOINT) { - DWC_WARN("%s, bad ep or descriptor\n", __func__); - return -EINVAL; - } - if (ep == &ep->pcd->ep0) { - DWC_WARN("%s, bad ep(0)\n", __func__); - return -EINVAL; - } - - /* Check FIFO size? */ - if (!ep_desc->wMaxPacketSize) { - DWC_WARN("%s, bad %s maxpacket\n", __func__, usb_ep->name); - return -ERANGE; - } - - pcd = ep->pcd; - if (!pcd->driver || pcd->gadget.speed == USB_SPEED_UNKNOWN) { - DWC_WARN("%s, bogus device state\n", __func__); - return -ESHUTDOWN; - } - - SPIN_LOCK_IRQSAVE(&pcd->lock, flags); - - ep->desc = ep_desc; - ep->ep.maxpacket = le16_to_cpu (ep_desc->wMaxPacketSize); - - /* - * Activate the EP - */ - ep->stopped = 0; - - ep->dwc_ep.is_in = (USB_DIR_IN & ep_desc->bEndpointAddress) != 0; - ep->dwc_ep.maxpacket = ep->ep.maxpacket; - - ep->dwc_ep.type = ep_desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; - - if(ep->dwc_ep.is_in) { - if(!pcd->otg_dev->core_if->en_multiple_tx_fifo) { - ep->dwc_ep.tx_fifo_num = 0; - - if (ep->dwc_ep.type == USB_ENDPOINT_XFER_ISOC) { - /* - * if ISOC EP then assign a Periodic Tx FIFO. - */ - ep->dwc_ep.tx_fifo_num = assign_perio_tx_fifo(pcd->otg_dev->core_if); - } - } else { - /* - * if Dedicated FIFOs mode is on then assign a Tx FIFO. - */ - ep->dwc_ep.tx_fifo_num = assign_tx_fifo(pcd->otg_dev->core_if); - - } - } - /* Set initial data PID. */ - if (ep->dwc_ep.type == USB_ENDPOINT_XFER_BULK) { - ep->dwc_ep.data_pid_start = 0; - } - - DWC_DEBUGPL(DBG_PCD, "Activate %s-%s: type=%d, mps=%d desc=%p\n", - ep->ep.name, (ep->dwc_ep.is_in ?"IN":"OUT"), - ep->dwc_ep.type, ep->dwc_ep.maxpacket, ep->desc); - - if(ep->dwc_ep.type != USB_ENDPOINT_XFER_ISOC) { - ep->dwc_ep.desc_addr = dwc_otg_ep_alloc_desc_chain(&ep->dwc_ep.dma_desc_addr, MAX_DMA_DESC_CNT); - } - - dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep); - SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags); - - return 0; -} - -/** - * This function is called when an EP is disabled due to disconnect or - * change in configuration. Any pending requests will terminate with a - * status of -ESHUTDOWN. - * - * This function modifies the dwc_otg_ep_t data structure for this EP, - * and then calls dwc_otg_ep_deactivate. - */ -static int dwc_otg_pcd_ep_disable(struct usb_ep *usb_ep) -{ - dwc_otg_pcd_ep_t *ep; - dwc_otg_pcd_t *pcd = 0; - unsigned long flags; - - DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, usb_ep); - ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep); - if (!usb_ep || !ep->desc) { - DWC_DEBUGPL(DBG_PCD, "%s, %s not enabled\n", __func__, - usb_ep ? ep->ep.name : NULL); - return -EINVAL; - } - - SPIN_LOCK_IRQSAVE(&ep->pcd->lock, flags); - - dwc_otg_request_nuke(ep); - - dwc_otg_ep_deactivate(GET_CORE_IF(ep->pcd), &ep->dwc_ep); - ep->desc = 0; - ep->stopped = 1; - - if(ep->dwc_ep.is_in) { - dwc_otg_flush_tx_fifo(GET_CORE_IF(ep->pcd), ep->dwc_ep.tx_fifo_num); - release_perio_tx_fifo(GET_CORE_IF(ep->pcd), ep->dwc_ep.tx_fifo_num); - release_tx_fifo(GET_CORE_IF(ep->pcd), ep->dwc_ep.tx_fifo_num); - } - - /* Free DMA Descriptors */ - pcd = ep->pcd; - - SPIN_UNLOCK_IRQRESTORE(&ep->pcd->lock, flags); - - if(ep->dwc_ep.type != USB_ENDPOINT_XFER_ISOC && ep->dwc_ep.desc_addr) { - dwc_otg_ep_free_desc_chain(ep->dwc_ep.desc_addr, ep->dwc_ep.dma_desc_addr, MAX_DMA_DESC_CNT); - } - - DWC_DEBUGPL(DBG_PCD, "%s disabled\n", usb_ep->name); - return 0; -} - - -/** - * This function allocates a request object to use with the specified - * endpoint. - * - * @param ep The endpoint to be used with with the request - * @param gfp_flags the GFP_* flags to use. - */ -static struct usb_request *dwc_otg_pcd_alloc_request(struct usb_ep *ep, -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) - int gfp_flags -#else - gfp_t gfp_flags -#endif - ) -{ - dwc_otg_pcd_request_t *req; - - DWC_DEBUGPL(DBG_PCDV,"%s(%p,%d)\n", __func__, ep, gfp_flags); - if (0 == ep) { - DWC_WARN("%s() %s\n", __func__, "Invalid EP!\n"); - return 0; - } - req = kmalloc(sizeof(dwc_otg_pcd_request_t), gfp_flags); - if (0 == req) { - DWC_WARN("%s() %s\n", __func__, - "request allocation failed!\n"); - return 0; - } - memset(req, 0, sizeof(dwc_otg_pcd_request_t)); - req->req.dma = DMA_ADDR_INVALID; - INIT_LIST_HEAD(&req->queue); - return &req->req; -} - -/** - * This function frees a request object. - * - * @param ep The endpoint associated with the request - * @param req The request being freed - */ -static void dwc_otg_pcd_free_request(struct usb_ep *ep, - struct usb_request *req) -{ - dwc_otg_pcd_request_t *request; - DWC_DEBUGPL(DBG_PCDV,"%s(%p,%p)\n", __func__, ep, req); - - if (0 == ep || 0 == req) { - DWC_WARN("%s() %s\n", __func__, - "Invalid ep or req argument!\n"); - return; - } - - request = container_of(req, dwc_otg_pcd_request_t, req); - kfree(request); -} - -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) -/** - * This function allocates an I/O buffer to be used for a transfer - * to/from the specified endpoint. - * - * @param usb_ep The endpoint to be used with with the request - * @param bytes The desired number of bytes for the buffer - * @param dma Pointer to the buffer's DMA address; must be valid - * @param gfp_flags the GFP_* flags to use. - * @return address of a new buffer or null is buffer could not be allocated. - */ -static void *dwc_otg_pcd_alloc_buffer(struct usb_ep *usb_ep, unsigned bytes, - dma_addr_t *dma, -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) - int gfp_flags -#else - gfp_t gfp_flags -#endif - ) -{ - void *buf; - dwc_otg_pcd_ep_t *ep; - dwc_otg_pcd_t *pcd = 0; - - ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep); - pcd = ep->pcd; - - DWC_DEBUGPL(DBG_PCDV,"%s(%p,%d,%p,%0x)\n", __func__, usb_ep, bytes, - dma, gfp_flags); - - /* Check dword alignment */ - if ((bytes & 0x3UL) != 0) { - DWC_WARN("%s() Buffer size is not a multiple of" - "DWORD size (%d)",__func__, bytes); - } - - if (GET_CORE_IF(pcd)->dma_enable) { - buf = dma_alloc_coherent (NULL, bytes, dma, gfp_flags); - } - else { - buf = kmalloc(bytes, gfp_flags); - } - - /* Check dword alignment */ - if (((int)buf & 0x3UL) != 0) { - DWC_WARN("%s() Buffer is not DWORD aligned (%p)", - __func__, buf); - } - - return buf; -} - -/** - * This function frees an I/O buffer that was allocated by alloc_buffer. - * - * @param usb_ep the endpoint associated with the buffer - * @param buf address of the buffer - * @param dma The buffer's DMA address - * @param bytes The number of bytes of the buffer - */ -static void dwc_otg_pcd_free_buffer(struct usb_ep *usb_ep, void *buf, - dma_addr_t dma, unsigned bytes) -{ - dwc_otg_pcd_ep_t *ep; - dwc_otg_pcd_t *pcd = 0; - - ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep); - pcd = ep->pcd; - - DWC_DEBUGPL(DBG_PCDV,"%s(%p,%p,%0x,%d)\n", __func__, ep, buf, dma, bytes); - - if (GET_CORE_IF(pcd)->dma_enable) { - dma_free_coherent (NULL, bytes, buf, dma); - } - else { - kfree(buf); - } -} -#endif - - -/** - * This function is used to submit an I/O Request to an EP. - * - * - When the request completes the request's completion callback - * is called to return the request to the driver. - * - An EP, except control EPs, may have multiple requests - * pending. - * - Once submitted the request cannot be examined or modified. - * - Each request is turned into one or more packets. - * - A BULK EP can queue any amount of data; the transfer is - * packetized. - * - Zero length Packets are specified with the request 'zero' - * flag. - */ -static int dwc_otg_pcd_ep_queue(struct usb_ep *usb_ep, - struct usb_request *usb_req, -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) - int gfp_flags -#else - gfp_t gfp_flags -#endif - ) -{ - int prevented = 0; - dwc_otg_pcd_request_t *req; - dwc_otg_pcd_ep_t *ep; - dwc_otg_pcd_t *pcd; - unsigned long flags = 0; - dwc_otg_core_if_t *_core_if; - - DWC_DEBUGPL(DBG_PCDV,"%s(%p,%p,%d)\n", - __func__, usb_ep, usb_req, gfp_flags); - - req = container_of(usb_req, dwc_otg_pcd_request_t, req); - if (!usb_req || !usb_req->complete || !usb_req->buf || - !list_empty(&req->queue)) { - DWC_WARN("%s, bad params\n", __func__); - return -EINVAL; - } - - ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep); - if (!usb_ep || (!ep->desc && ep->dwc_ep.num != 0)/* || ep->stopped != 0*/) { - DWC_WARN("%s, bad ep\n", __func__); - return -EINVAL; - } - - pcd = ep->pcd; - if (!pcd->driver || pcd->gadget.speed == USB_SPEED_UNKNOWN) { - DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n", pcd->gadget.speed); - DWC_WARN("%s, bogus device state\n", __func__); - return -ESHUTDOWN; - } - - - DWC_DEBUGPL(DBG_PCD, "%s queue req %p, len %d buf %p\n", - usb_ep->name, usb_req, usb_req->length, usb_req->buf); - - if (!GET_CORE_IF(pcd)->core_params->opt) { - if (ep->dwc_ep.num != 0) { - DWC_ERROR("%s queue req %p, len %d buf %p\n", - usb_ep->name, usb_req, usb_req->length, usb_req->buf); - } - } - - SPIN_LOCK_IRQSAVE(&ep->pcd->lock, flags); - - - /************************************************** - New add by kaiker ,for DMA mode bug - ************************************************/ - //by kaiker ,for RT3052 USB OTG device mode - - _core_if = GET_CORE_IF(pcd); - - if (_core_if->dma_enable) - { - usb_req->dma = virt_to_phys((void *)usb_req->buf); - - if(ep->dwc_ep.is_in) - { -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) || defined(CONFIG_MIPS) - if(usb_req->length) - dma_cache_wback_inv((unsigned long)usb_req->buf, usb_req->length + 2); -#endif - } - } - - - -#if defined(DEBUG) & defined(VERBOSE) - dump_msg(usb_req->buf, usb_req->length); -#endif - - usb_req->status = -EINPROGRESS; - usb_req->actual = 0; - - /* - * For EP0 IN without premature status, zlp is required? - */ - if (ep->dwc_ep.num == 0 && ep->dwc_ep.is_in) { - DWC_DEBUGPL(DBG_PCDV, "%s-OUT ZLP\n", usb_ep->name); - //_req->zero = 1; - } - - /* Start the transfer */ - if (list_empty(&ep->queue) && !ep->stopped) { - /* EP0 Transfer? */ - if (ep->dwc_ep.num == 0) { - switch (pcd->ep0state) { - case EP0_IN_DATA_PHASE: - DWC_DEBUGPL(DBG_PCD, - "%s ep0: EP0_IN_DATA_PHASE\n", - __func__); - break; - - case EP0_OUT_DATA_PHASE: - DWC_DEBUGPL(DBG_PCD, - "%s ep0: EP0_OUT_DATA_PHASE\n", - __func__); - if (pcd->request_config) { - /* Complete STATUS PHASE */ - ep->dwc_ep.is_in = 1; - pcd->ep0state = EP0_IN_STATUS_PHASE; - } - break; - - case EP0_IN_STATUS_PHASE: - DWC_DEBUGPL(DBG_PCD, - "%s ep0: EP0_IN_STATUS_PHASE\n", - __func__); - break; - - default: - DWC_DEBUGPL(DBG_ANY, "ep0: odd state %d\n", - pcd->ep0state); - SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags); - return -EL2HLT; - } - ep->dwc_ep.dma_addr = usb_req->dma; - ep->dwc_ep.start_xfer_buff = usb_req->buf; - ep->dwc_ep.xfer_buff = usb_req->buf; - ep->dwc_ep.xfer_len = usb_req->length; - ep->dwc_ep.xfer_count = 0; - ep->dwc_ep.sent_zlp = 0; - ep->dwc_ep.total_len = ep->dwc_ep.xfer_len; - - if(usb_req->zero) { - if((ep->dwc_ep.xfer_len % ep->dwc_ep.maxpacket == 0) - && (ep->dwc_ep.xfer_len != 0)) { - ep->dwc_ep.sent_zlp = 1; - } - - } - - dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep->dwc_ep); - } - else { - - uint32_t max_transfer = GET_CORE_IF(ep->pcd)->core_params->max_transfer_size; - - /* Setup and start the Transfer */ - ep->dwc_ep.dma_addr = usb_req->dma; - ep->dwc_ep.start_xfer_buff = usb_req->buf; - ep->dwc_ep.xfer_buff = usb_req->buf; - ep->dwc_ep.sent_zlp = 0; - ep->dwc_ep.total_len = usb_req->length; - ep->dwc_ep.xfer_len = 0; - ep->dwc_ep.xfer_count = 0; - - if(max_transfer > MAX_TRANSFER_SIZE) { - ep->dwc_ep.maxxfer = max_transfer - (max_transfer % ep->dwc_ep.maxpacket); - } else { - ep->dwc_ep.maxxfer = max_transfer; - } - - if(usb_req->zero) { - if((ep->dwc_ep.total_len % ep->dwc_ep.maxpacket == 0) - && (ep->dwc_ep.total_len != 0)) { - ep->dwc_ep.sent_zlp = 1; - } - - } - dwc_otg_ep_start_transfer(GET_CORE_IF(pcd), &ep->dwc_ep); - } - } - - if ((req != 0) || prevented) { - ++pcd->request_pending; - list_add_tail(&req->queue, &ep->queue); - if (ep->dwc_ep.is_in && ep->stopped && !(GET_CORE_IF(pcd)->dma_enable)) { - /** @todo NGS Create a function for this. */ - diepmsk_data_t diepmsk = { .d32 = 0}; - diepmsk.b.intktxfemp = 1; - if(&GET_CORE_IF(pcd)->multiproc_int_enable) { - dwc_modify_reg32(&GET_CORE_IF(pcd)->dev_if->dev_global_regs->diepeachintmsk[ep->dwc_ep.num], - 0, diepmsk.d32); - } else { - dwc_modify_reg32(&GET_CORE_IF(pcd)->dev_if->dev_global_regs->diepmsk, 0, diepmsk.d32); - } - } - } - - SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags); - return 0; -} - -/** - * This function cancels an I/O request from an EP. - */ -static int dwc_otg_pcd_ep_dequeue(struct usb_ep *usb_ep, - struct usb_request *usb_req) -{ - dwc_otg_pcd_request_t *req; - dwc_otg_pcd_ep_t *ep; - dwc_otg_pcd_t *pcd; - unsigned long flags; - - DWC_DEBUGPL(DBG_PCDV,"%s(%p,%p)\n", __func__, usb_ep, usb_req); - - ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep); - if (!usb_ep || !usb_req || (!ep->desc && ep->dwc_ep.num != 0)) { - DWC_WARN("%s, bad argument\n", __func__); - return -EINVAL; - } - pcd = ep->pcd; - if (!pcd->driver || pcd->gadget.speed == USB_SPEED_UNKNOWN) { - DWC_WARN("%s, bogus device state\n", __func__); - return -ESHUTDOWN; - } - - SPIN_LOCK_IRQSAVE(&pcd->lock, flags); - DWC_DEBUGPL(DBG_PCDV, "%s %s %s %p\n", __func__, usb_ep->name, - ep->dwc_ep.is_in ? "IN" : "OUT", - usb_req); - - /* make sure it's actually queued on this endpoint */ - list_for_each_entry(req, &ep->queue, queue) - { - if (&req->req == usb_req) { - break; - } - } - - if (&req->req != usb_req) { - SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags); - return -EINVAL; - } - - if (!list_empty(&req->queue)) { - dwc_otg_request_done(ep, req, -ECONNRESET); - } - else { - req = 0; - } - - SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags); - - return req ? 0 : -EOPNOTSUPP; -} - -/** - * usb_ep_set_halt stalls an endpoint. - * - * usb_ep_clear_halt clears an endpoint halt and resets its data - * toggle. - * - * Both of these functions are implemented with the same underlying - * function. The behavior depends on the value argument. - * - * @param[in] usb_ep the Endpoint to halt or clear halt. - * @param[in] value - * - 0 means clear_halt. - * - 1 means set_halt, - * - 2 means clear stall lock flag. - * - 3 means set stall lock flag. - */ -static int dwc_otg_pcd_ep_set_halt(struct usb_ep *usb_ep, int value) -{ - int retval = 0; - unsigned long flags; - dwc_otg_pcd_ep_t *ep = 0; - - - DWC_DEBUGPL(DBG_PCD,"HALT %s %d\n", usb_ep->name, value); - - ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep); - - if (!usb_ep || (!ep->desc && ep != &ep->pcd->ep0) || - ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) { - DWC_WARN("%s, bad ep\n", __func__); - return -EINVAL; - } - - SPIN_LOCK_IRQSAVE(&ep->pcd->lock, flags); - if (!list_empty(&ep->queue)) { - DWC_WARN("%s() %s XFer In process\n", __func__, usb_ep->name); - retval = -EAGAIN; - } - else if (value == 0) { - dwc_otg_ep_clear_stall(ep->pcd->otg_dev->core_if, - &ep->dwc_ep); - } - else if(value == 1) { - if (ep->dwc_ep.is_in == 1 && ep->pcd->otg_dev->core_if->dma_desc_enable) { - dtxfsts_data_t txstatus; - fifosize_data_t txfifosize; - - txfifosize.d32 = dwc_read_reg32(&ep->pcd->otg_dev->core_if->core_global_regs->dptxfsiz_dieptxf[ep->dwc_ep.tx_fifo_num]); - txstatus.d32 = dwc_read_reg32(&ep->pcd->otg_dev->core_if->dev_if->in_ep_regs[ep->dwc_ep.num]->dtxfsts); - - if(txstatus.b.txfspcavail < txfifosize.b.depth) { - DWC_WARN("%s() %s Data In Tx Fifo\n", __func__, usb_ep->name); - retval = -EAGAIN; - } - else { - if (ep->dwc_ep.num == 0) { - ep->pcd->ep0state = EP0_STALL; - } - - ep->stopped = 1; - dwc_otg_ep_set_stall(ep->pcd->otg_dev->core_if, - &ep->dwc_ep); - } - } - else { - if (ep->dwc_ep.num == 0) { - ep->pcd->ep0state = EP0_STALL; - } - - ep->stopped = 1; - dwc_otg_ep_set_stall(ep->pcd->otg_dev->core_if, - &ep->dwc_ep); - } - } - else if (value == 2) { - ep->dwc_ep.stall_clear_flag = 0; - } - else if (value == 3) { - ep->dwc_ep.stall_clear_flag = 1; - } - - SPIN_UNLOCK_IRQRESTORE(&ep->pcd->lock, flags); - return retval; -} - -/** - * This function allocates a DMA Descriptor chain for the Endpoint - * buffer to be used for a transfer to/from the specified endpoint. - */ -dwc_otg_dma_desc_t* dwc_otg_ep_alloc_desc_chain(uint32_t * dma_desc_addr, uint32_t count) -{ - - return dma_alloc_coherent(NULL, count * sizeof(dwc_otg_dma_desc_t), dma_desc_addr, GFP_KERNEL); -} - -/** - * This function frees a DMA Descriptor chain that was allocated by ep_alloc_desc. - */ -void dwc_otg_ep_free_desc_chain(dwc_otg_dma_desc_t* desc_addr, uint32_t dma_desc_addr, uint32_t count) -{ - dma_free_coherent(NULL, count * sizeof(dwc_otg_dma_desc_t), desc_addr, dma_desc_addr); -} - -#ifdef DWC_EN_ISOC - -/** - * This function initializes a descriptor chain for Isochronous transfer - * - * @param core_if Programming view of DWC_otg controller. - * @param dwc_ep The EP to start the transfer on. - * - */ -void dwc_otg_iso_ep_start_ddma_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep) -{ - - dsts_data_t dsts = { .d32 = 0}; - depctl_data_t depctl = { .d32 = 0 }; - volatile uint32_t *addr; - int i, j; - - if(dwc_ep->is_in) - dwc_ep->desc_cnt = dwc_ep->buf_proc_intrvl / dwc_ep->bInterval; - else - dwc_ep->desc_cnt = dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm / dwc_ep->bInterval; - - - /** Allocate descriptors for double buffering */ - dwc_ep->iso_desc_addr = dwc_otg_ep_alloc_desc_chain(&dwc_ep->iso_dma_desc_addr,dwc_ep->desc_cnt*2); - if(dwc_ep->desc_addr) { - DWC_WARN("%s, can't allocate DMA descriptor chain\n", __func__); - return; - } - - dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); - - /** ISO OUT EP */ - if(dwc_ep->is_in == 0) { - desc_sts_data_t sts = { .d32 =0 }; - dwc_otg_dma_desc_t* dma_desc = dwc_ep->iso_desc_addr; - dma_addr_t dma_ad; - uint32_t data_per_desc; - dwc_otg_dev_out_ep_regs_t *out_regs = - core_if->dev_if->out_ep_regs[dwc_ep->num]; - int offset; - - addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl; - dma_ad = (dma_addr_t)dwc_read_reg32(&(out_regs->doepdma)); - - /** Buffer 0 descriptors setup */ - dma_ad = dwc_ep->dma_addr0; - - sts.b_iso_out.bs = BS_HOST_READY; - sts.b_iso_out.rxsts = 0; - sts.b_iso_out.l = 0; - sts.b_iso_out.sp = 0; - sts.b_iso_out.ioc = 0; - sts.b_iso_out.pid = 0; - sts.b_iso_out.framenum = 0; - - offset = 0; - for(i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; i+= dwc_ep->pkt_per_frm) - { - - for(j = 0; j < dwc_ep->pkt_per_frm; ++j) - { - data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ? - dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket; - - data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0; - sts.b_iso_out.rxbytes = data_per_desc; - writel((uint32_t)dma_ad, &dma_desc->buf); - writel(sts.d32, &dma_desc->status); - - offset += data_per_desc; - dma_desc ++; - (uint32_t)dma_ad += data_per_desc; - } - } - - for(j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) - { - data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ? - dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket; - data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0; - sts.b_iso_out.rxbytes = data_per_desc; - writel((uint32_t)dma_ad, &dma_desc->buf); - writel(sts.d32, &dma_desc->status); - - offset += data_per_desc; - dma_desc ++; - (uint32_t)dma_ad += data_per_desc; - } - - sts.b_iso_out.ioc = 1; - data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ? - dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket; - data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0; - sts.b_iso_out.rxbytes = data_per_desc; - - writel((uint32_t)dma_ad, &dma_desc->buf); - writel(sts.d32, &dma_desc->status); - dma_desc ++; - - /** Buffer 1 descriptors setup */ - sts.b_iso_out.ioc = 0; - dma_ad = dwc_ep->dma_addr1; - - offset = 0; - for(i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; i+= dwc_ep->pkt_per_frm) - { - for(j = 0; j < dwc_ep->pkt_per_frm; ++j) - { - data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ? - dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket; - data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0; - sts.b_iso_out.rxbytes = data_per_desc; - writel((uint32_t)dma_ad, &dma_desc->buf); - writel(sts.d32, &dma_desc->status); - - offset += data_per_desc; - dma_desc ++; - (uint32_t)dma_ad += data_per_desc; - } - } - for(j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) - { - data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ? - dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket; - data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0; - sts.b_iso_out.rxbytes = data_per_desc; - writel((uint32_t)dma_ad, &dma_desc->buf); - writel(sts.d32, &dma_desc->status); - - offset += data_per_desc; - dma_desc ++; - (uint32_t)dma_ad += data_per_desc; - } - - sts.b_iso_out.ioc = 1; - sts.b_iso_out.l = 1; - data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ? - dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket; - data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0; - sts.b_iso_out.rxbytes = data_per_desc; - - writel((uint32_t)dma_ad, &dma_desc->buf); - writel(sts.d32, &dma_desc->status); - - dwc_ep->next_frame = 0; - - /** Write dma_ad into DOEPDMA register */ - dwc_write_reg32(&(out_regs->doepdma),(uint32_t)dwc_ep->iso_dma_desc_addr); - - } - /** ISO IN EP */ - else { - desc_sts_data_t sts = { .d32 =0 }; - dwc_otg_dma_desc_t* dma_desc = dwc_ep->iso_desc_addr; - dma_addr_t dma_ad; - dwc_otg_dev_in_ep_regs_t *in_regs = - core_if->dev_if->in_ep_regs[dwc_ep->num]; - unsigned int frmnumber; - fifosize_data_t txfifosize,rxfifosize; - - txfifosize.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[dwc_ep->num]->dtxfsts); - rxfifosize.d32 = dwc_read_reg32(&core_if->core_global_regs->grxfsiz); - - - addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl; - - dma_ad = dwc_ep->dma_addr0; - - dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); - - sts.b_iso_in.bs = BS_HOST_READY; - sts.b_iso_in.txsts = 0; - sts.b_iso_in.sp = (dwc_ep->data_per_frame % dwc_ep->maxpacket)? 1 : 0; - sts.b_iso_in.ioc = 0; - sts.b_iso_in.pid = dwc_ep->pkt_per_frm; - - - frmnumber = dwc_ep->next_frame; - - sts.b_iso_in.framenum = frmnumber; - sts.b_iso_in.txbytes = dwc_ep->data_per_frame; - sts.b_iso_in.l = 0; - - /** Buffer 0 descriptors setup */ - for(i = 0; i < dwc_ep->desc_cnt - 1; i++) - { - writel((uint32_t)dma_ad, &dma_desc->buf); - writel(sts.d32, &dma_desc->status); - dma_desc ++; - - (uint32_t)dma_ad += dwc_ep->data_per_frame; - sts.b_iso_in.framenum += dwc_ep->bInterval; - } - - sts.b_iso_in.ioc = 1; - writel((uint32_t)dma_ad, &dma_desc->buf); - writel(sts.d32, &dma_desc->status); - ++dma_desc; - - /** Buffer 1 descriptors setup */ - sts.b_iso_in.ioc = 0; - dma_ad = dwc_ep->dma_addr1; - - for(i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; i+= dwc_ep->pkt_per_frm) - { - writel((uint32_t)dma_ad, &dma_desc->buf); - writel(sts.d32, &dma_desc->status); - dma_desc ++; - - (uint32_t)dma_ad += dwc_ep->data_per_frame; - sts.b_iso_in.framenum += dwc_ep->bInterval; - - sts.b_iso_in.ioc = 0; - } - sts.b_iso_in.ioc = 1; - sts.b_iso_in.l = 1; - - writel((uint32_t)dma_ad, &dma_desc->buf); - writel(sts.d32, &dma_desc->status); - - dwc_ep->next_frame = sts.b_iso_in.framenum + dwc_ep->bInterval; - - /** Write dma_ad into diepdma register */ - dwc_write_reg32(&(in_regs->diepdma),(uint32_t)dwc_ep->iso_dma_desc_addr); - } - /** Enable endpoint, clear nak */ - depctl.d32 = 0; - depctl.b.epena = 1; - depctl.b.usbactep = 1; - depctl.b.cnak = 1; - - dwc_modify_reg32(addr, depctl.d32,depctl.d32); - depctl.d32 = dwc_read_reg32(addr); -} - -/** - * This function initializes a descriptor chain for Isochronous transfer - * - * @param core_if Programming view of DWC_otg controller. - * @param ep The EP to start the transfer on. - * - */ - -void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) -{ - depctl_data_t depctl = { .d32 = 0 }; - volatile uint32_t *addr; - - - if(ep->is_in) { - addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl; - } else { - addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl; - } - - - if(core_if->dma_enable == 0 || core_if->dma_desc_enable!= 0) { - return; - } else { - deptsiz_data_t deptsiz = { .d32 = 0 }; - - ep->xfer_len = ep->data_per_frame * ep->buf_proc_intrvl / ep->bInterval; - ep->pkt_cnt = (ep->xfer_len - 1 + ep->maxpacket) / - ep->maxpacket; - ep->xfer_count = 0; - ep->xfer_buff = (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0; - ep->dma_addr = (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0; - - if(ep->is_in) { - /* Program the transfer size and packet count - * as follows: xfersize = N * maxpacket + - * short_packet pktcnt = N + (short_packet - * exist ? 1 : 0) - */ - deptsiz.b.mc = ep->pkt_per_frm; - deptsiz.b.xfersize = ep->xfer_len; - deptsiz.b.pktcnt = - (ep->xfer_len - 1 + ep->maxpacket) / - ep->maxpacket; - dwc_write_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz, deptsiz.d32); - - /* Write the DMA register */ - dwc_write_reg32 (&(core_if->dev_if->in_ep_regs[ep->num]->diepdma), (uint32_t)ep->dma_addr); - - } else { - deptsiz.b.pktcnt = - (ep->xfer_len + (ep->maxpacket - 1)) / - ep->maxpacket; - deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket; - - dwc_write_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doeptsiz, deptsiz.d32); - - /* Write the DMA register */ - dwc_write_reg32 (&(core_if->dev_if->out_ep_regs[ep->num]->doepdma), (uint32_t)ep->dma_addr); - - } - /** Enable endpoint, clear nak */ - depctl.d32 = 0; - dwc_modify_reg32(addr, depctl.d32,depctl.d32); - - depctl.b.epena = 1; - depctl.b.cnak = 1; - - dwc_modify_reg32(addr, depctl.d32,depctl.d32); - } -} - - -/** - * This function does the setup for a data transfer for an EP and - * starts the transfer. For an IN transfer, the packets will be - * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, - * the packets are unloaded from the Rx FIFO in the ISR. the ISR. - * - * @param core_if Programming view of DWC_otg controller. - * @param ep The EP to start the transfer on. - */ - -void dwc_otg_iso_ep_start_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) -{ - if(core_if->dma_enable) { - if(core_if->dma_desc_enable) { - if(ep->is_in) { - ep->desc_cnt = ep->pkt_cnt / ep->pkt_per_frm; - } else { - ep->desc_cnt = ep->pkt_cnt; - } - dwc_otg_iso_ep_start_ddma_transfer(core_if, ep); - } else { - if(core_if->pti_enh_enable) { - dwc_otg_iso_ep_start_buf_transfer(core_if, ep); - } else { - ep->cur_pkt_addr = (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0; - ep->cur_pkt_dma_addr = (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0; - dwc_otg_iso_ep_start_frm_transfer(core_if, ep); - } - } - } else { - ep->cur_pkt_addr = (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0; - ep->cur_pkt_dma_addr = (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0; - dwc_otg_iso_ep_start_frm_transfer(core_if, ep); - } -} - -/** - * This function does the setup for a data transfer for an EP and - * starts the transfer. For an IN transfer, the packets will be - * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, - * the packets are unloaded from the Rx FIFO in the ISR. the ISR. - * - * @param core_if Programming view of DWC_otg controller. - * @param ep The EP to start the transfer on. - */ - -void dwc_otg_iso_ep_stop_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) -{ - depctl_data_t depctl = { .d32 = 0 }; - volatile uint32_t *addr; - - if(ep->is_in == 1) { - addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl; - } - else { - addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl; - } - - /* disable the ep */ - depctl.d32 = dwc_read_reg32(addr); - - depctl.b.epdis = 1; - depctl.b.snak = 1; - - dwc_write_reg32(addr, depctl.d32); - - if(core_if->dma_desc_enable && - ep->iso_desc_addr && ep->iso_dma_desc_addr) { - dwc_otg_ep_free_desc_chain(ep->iso_desc_addr,ep->iso_dma_desc_addr,ep->desc_cnt * 2); - } - - /* reset varibales */ - ep->dma_addr0 = 0; - ep->dma_addr1 = 0; - ep->xfer_buff0 = 0; - ep->xfer_buff1 = 0; - ep->data_per_frame = 0; - ep->data_pattern_frame = 0; - ep->sync_frame = 0; - ep->buf_proc_intrvl = 0; - ep->bInterval = 0; - ep->proc_buf_num = 0; - ep->pkt_per_frm = 0; - ep->pkt_per_frm = 0; - ep->desc_cnt = 0; - ep->iso_desc_addr = 0; - ep->iso_dma_desc_addr = 0; -} - - -/** - * This function is used to submit an ISOC Transfer Request to an EP. - * - * - Every time a sync period completes the request's completion callback - * is called to provide data to the gadget driver. - * - Once submitted the request cannot be modified. - * - Each request is turned into periodic data packets untill ISO - * Transfer is stopped.. - */ -static int dwc_otg_pcd_iso_ep_start(struct usb_ep *usb_ep, struct usb_iso_request *req, -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) - int gfp_flags -#else - gfp_t gfp_flags -#endif -) -{ - dwc_otg_pcd_ep_t *ep; - dwc_otg_pcd_t *pcd; - dwc_ep_t *dwc_ep; - unsigned long flags = 0; - int32_t frm_data; - dwc_otg_core_if_t *core_if; - dcfg_data_t dcfg; - dsts_data_t dsts; - - - if (!req || !req->process_buffer || !req->buf0 || !req->buf1) { - DWC_WARN("%s, bad params\n", __func__); - return -EINVAL; - } - - ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep); - - if (!usb_ep || !ep->desc || ep->dwc_ep.num == 0) { - DWC_WARN("%s, bad ep\n", __func__); - return -EINVAL; - } - - pcd = ep->pcd; - core_if = GET_CORE_IF(pcd); - - dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg); - - if (!pcd->driver || pcd->gadget.speed == USB_SPEED_UNKNOWN) { - DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n", pcd->gadget.speed); - DWC_WARN("%s, bogus device state\n", __func__); - return -ESHUTDOWN; - } - - SPIN_LOCK_IRQSAVE(&ep->pcd->lock, flags); - - dwc_ep = &ep->dwc_ep; - - if(ep->iso_req) { - DWC_WARN("%s, iso request in progress\n", __func__); - } - req->status = -EINPROGRESS; - - dwc_ep->dma_addr0 = req->dma0; - dwc_ep->dma_addr1 = req->dma1; - - dwc_ep->xfer_buff0 = req->buf0; - dwc_ep->xfer_buff1 = req->buf1; - - ep->iso_req = req; - - dwc_ep->data_per_frame = req->data_per_frame; - - /** @todo - pattern data support is to be implemented in the future */ - dwc_ep->data_pattern_frame = req->data_pattern_frame; - dwc_ep->sync_frame = req->sync_frame; - - dwc_ep->buf_proc_intrvl = req->buf_proc_intrvl; - - dwc_ep->bInterval = 1 << (ep->desc->bInterval - 1); - - dwc_ep->proc_buf_num = 0; - - dwc_ep->pkt_per_frm = 0; - frm_data = ep->dwc_ep.data_per_frame; - while(frm_data > 0) { - dwc_ep->pkt_per_frm++; - frm_data -= ep->dwc_ep.maxpacket; - } - - dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); - - if(req->flags & USB_REQ_ISO_ASAP) { - dwc_ep->next_frame = dsts.b.soffn + 1; - if(dwc_ep->bInterval != 1){ - dwc_ep->next_frame = dwc_ep->next_frame + (dwc_ep->bInterval - 1 - dwc_ep->next_frame % dwc_ep->bInterval); - } - } else { - dwc_ep->next_frame = req->start_frame; - } - - - if(!core_if->pti_enh_enable) { - dwc_ep->pkt_cnt = dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm / dwc_ep->bInterval; - } else { - dwc_ep->pkt_cnt = - (dwc_ep->data_per_frame * (dwc_ep->buf_proc_intrvl / dwc_ep->bInterval) - - 1 + dwc_ep->maxpacket) / dwc_ep->maxpacket; - } - - if(core_if->dma_desc_enable) { - dwc_ep->desc_cnt = - dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm / dwc_ep->bInterval; - } - - dwc_ep->pkt_info = kmalloc(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt, GFP_KERNEL); - if(!dwc_ep->pkt_info) { - return -ENOMEM; - } - if(core_if->pti_enh_enable) { - memset(dwc_ep->pkt_info, 0, sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt); - } - - dwc_ep->cur_pkt = 0; - - SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags); - - dwc_otg_iso_ep_start_transfer(core_if, dwc_ep); - - return 0; -} - -/** - * This function stops ISO EP Periodic Data Transfer. - */ -static int dwc_otg_pcd_iso_ep_stop(struct usb_ep *usb_ep, struct usb_iso_request *req) -{ - dwc_otg_pcd_ep_t *ep; - dwc_otg_pcd_t *pcd; - dwc_ep_t *dwc_ep; - unsigned long flags; - - ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep); - - if (!usb_ep || !ep->desc || ep->dwc_ep.num == 0) { - DWC_WARN("%s, bad ep\n", __func__); - return -EINVAL; - } - - pcd = ep->pcd; - - if (!pcd->driver || pcd->gadget.speed == USB_SPEED_UNKNOWN) { - DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n", pcd->gadget.speed); - DWC_WARN("%s, bogus device state\n", __func__); - return -ESHUTDOWN; - } - - dwc_ep = &ep->dwc_ep; - - dwc_otg_iso_ep_stop_transfer(GET_CORE_IF(pcd), dwc_ep); - - kfree(dwc_ep->pkt_info); - - SPIN_LOCK_IRQSAVE(&pcd->lock, flags); - - if(ep->iso_req != req) { - return -EINVAL; - } - - req->status = -ECONNRESET; - - SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags); - - - ep->iso_req = 0; - - return 0; -} - -/** - * This function is used for perodical data exchnage between PCD and gadget drivers. - * for Isochronous EPs - * - * - Every time a sync period completes this function is called to - * perform data exchange between PCD and gadget - */ -void dwc_otg_iso_buffer_done(dwc_otg_pcd_ep_t *ep, dwc_otg_pcd_iso_request_t *req) -{ - int i; - struct usb_gadget_iso_packet_descriptor *iso_packet; - dwc_ep_t *dwc_ep; - - dwc_ep = &ep->dwc_ep; - - if(ep->iso_req->status == -ECONNRESET) { - DWC_PRINT("Device has already disconnected\n"); - /*Device has been disconnected*/ - return; - } - - if(dwc_ep->proc_buf_num != 0) { - iso_packet = ep->iso_req->iso_packet_desc0; - } - - else { - iso_packet = ep->iso_req->iso_packet_desc1; - } - - /* Fill in ISOC packets descriptors & pass to gadget driver*/ - - for(i = 0; i < dwc_ep->pkt_cnt; ++i) { - iso_packet[i].status = dwc_ep->pkt_info[i].status; - iso_packet[i].offset = dwc_ep->pkt_info[i].offset; - iso_packet[i].actual_length = dwc_ep->pkt_info[i].length; - dwc_ep->pkt_info[i].status = 0; - dwc_ep->pkt_info[i].offset = 0; - dwc_ep->pkt_info[i].length = 0; - } - - /* Call callback function to process data buffer */ - ep->iso_req->status = 0;/* success */ - - SPIN_UNLOCK(&ep->pcd->lock); - ep->iso_req->process_buffer(&ep->ep, ep->iso_req); - SPIN_LOCK(&ep->pcd->lock); -} - - -static struct usb_iso_request *dwc_otg_pcd_alloc_iso_request(struct usb_ep *ep,int packets, -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) - int gfp_flags -#else - gfp_t gfp_flags -#endif -) -{ - struct usb_iso_request *pReq = NULL; - uint32_t req_size; - - - req_size = sizeof(struct usb_iso_request); - req_size += (2 * packets * (sizeof(struct usb_gadget_iso_packet_descriptor))); - - - pReq = kmalloc(req_size, gfp_flags); - if (!pReq) { - DWC_WARN("%s, can't allocate Iso Request\n", __func__); - return 0; - } - pReq->iso_packet_desc0 = (void*) (pReq + 1); - - pReq->iso_packet_desc1 = pReq->iso_packet_desc0 + packets; - - return pReq; -} - -static void dwc_otg_pcd_free_iso_request(struct usb_ep *ep, struct usb_iso_request *req) -{ - kfree(req); -} - -static struct usb_isoc_ep_ops dwc_otg_pcd_ep_ops = -{ - .ep_ops = - { - .enable = dwc_otg_pcd_ep_enable, - .disable = dwc_otg_pcd_ep_disable, - - .alloc_request = dwc_otg_pcd_alloc_request, - .free_request = dwc_otg_pcd_free_request, - -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) - .alloc_buffer = dwc_otg_pcd_alloc_buffer, - .free_buffer = dwc_otg_pcd_free_buffer, -#endif - - .queue = dwc_otg_pcd_ep_queue, - .dequeue = dwc_otg_pcd_ep_dequeue, - - .set_halt = dwc_otg_pcd_ep_set_halt, - .fifo_status = 0, - .fifo_flush = 0, - }, - .iso_ep_start = dwc_otg_pcd_iso_ep_start, - .iso_ep_stop = dwc_otg_pcd_iso_ep_stop, - .alloc_iso_request = dwc_otg_pcd_alloc_iso_request, - .free_iso_request = dwc_otg_pcd_free_iso_request, -}; - -#else - - -static struct usb_ep_ops dwc_otg_pcd_ep_ops = -{ - .enable = dwc_otg_pcd_ep_enable, - .disable = dwc_otg_pcd_ep_disable, - - .alloc_request = dwc_otg_pcd_alloc_request, - .free_request = dwc_otg_pcd_free_request, - -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) - .alloc_buffer = dwc_otg_pcd_alloc_buffer, - .free_buffer = dwc_otg_pcd_free_buffer, -#endif - - .queue = dwc_otg_pcd_ep_queue, - .dequeue = dwc_otg_pcd_ep_dequeue, - - .set_halt = dwc_otg_pcd_ep_set_halt, - .fifo_status = 0, - .fifo_flush = 0, - - -}; - -#endif /* DWC_EN_ISOC */ -/* Gadget Operations */ -/** - * The following gadget operations will be implemented in the DWC_otg - * PCD. Functions in the API that are not described below are not - * implemented. - * - * The Gadget API provides wrapper functions for each of the function - * pointers defined in usb_gadget_ops. The Gadget Driver calls the - * wrapper function, which then calls the underlying PCD function. The - * following sections are named according to the wrapper functions - * (except for ioctl, which doesn't have a wrapper function). Within - * each section, the corresponding DWC_otg PCD function name is - * specified. - * - */ - -/** - *Gets the USB Frame number of the last SOF. - */ -static int dwc_otg_pcd_get_frame(struct usb_gadget *gadget) -{ - dwc_otg_pcd_t *pcd; - - DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, gadget); - - if (gadget == 0) { - return -ENODEV; - } - else { - pcd = container_of(gadget, dwc_otg_pcd_t, gadget); - dwc_otg_get_frame_number(GET_CORE_IF(pcd)); - } - - return 0; -} - -void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t *pcd) -{ - uint32_t *addr = (uint32_t *)&(GET_CORE_IF(pcd)->core_global_regs->gotgctl); - gotgctl_data_t mem; - gotgctl_data_t val; - - val.d32 = dwc_read_reg32(addr); - if (val.b.sesreq) { - DWC_ERROR("Session Request Already active!\n"); - return; - } - - DWC_NOTICE("Session Request Initated\n"); - mem.d32 = dwc_read_reg32(addr); - mem.b.sesreq = 1; - dwc_write_reg32(addr, mem.d32); - - /* Start the SRP timer */ - dwc_otg_pcd_start_srp_timer(pcd); - return; -} - -void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t *pcd, int set) -{ - dctl_data_t dctl = {.d32=0}; - volatile uint32_t *addr = &(GET_CORE_IF(pcd)->dev_if->dev_global_regs->dctl); - - if (dwc_otg_is_device_mode(GET_CORE_IF(pcd))) { - if (pcd->remote_wakeup_enable) { - if (set) { - dctl.b.rmtwkupsig = 1; - dwc_modify_reg32(addr, 0, dctl.d32); - DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n"); - mdelay(1); - dwc_modify_reg32(addr, dctl.d32, 0); - DWC_DEBUGPL(DBG_PCD, "Clear Remote Wakeup\n"); - } - else { - } - } - else { - DWC_DEBUGPL(DBG_PCD, "Remote Wakeup is disabled\n"); - } - } - return; -} - -/** - * Initiates Session Request Protocol (SRP) to wakeup the host if no - * session is in progress. If a session is already in progress, but - * the device is suspended, remote wakeup signaling is started. - * - */ -static int dwc_otg_pcd_wakeup(struct usb_gadget *gadget) -{ - unsigned long flags; - dwc_otg_pcd_t *pcd; - dsts_data_t dsts; - gotgctl_data_t gotgctl; - - DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, gadget); - - if (gadget == 0) { - return -ENODEV; - } - else { - pcd = container_of(gadget, dwc_otg_pcd_t, gadget); - } - SPIN_LOCK_IRQSAVE(&pcd->lock, flags); - - /* - * This function starts the Protocol if no session is in progress. If - * a session is already in progress, but the device is suspended, - * remote wakeup signaling is started. - */ - - /* Check if valid session */ - gotgctl.d32 = dwc_read_reg32(&(GET_CORE_IF(pcd)->core_global_regs->gotgctl)); - if (gotgctl.b.bsesvld) { - /* Check if suspend state */ - dsts.d32 = dwc_read_reg32(&(GET_CORE_IF(pcd)->dev_if->dev_global_regs->dsts)); - if (dsts.b.suspsts) { - dwc_otg_pcd_remote_wakeup(pcd, 1); - } - } - else { - dwc_otg_pcd_initiate_srp(pcd); - } - - SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags); - return 0; -} - -static const struct usb_gadget_ops dwc_otg_pcd_ops = -{ - .get_frame = dwc_otg_pcd_get_frame, - .wakeup = dwc_otg_pcd_wakeup, - // current versions must always be self-powered -}; - -/** - * This function updates the otg values in the gadget structure. - */ -void dwc_otg_pcd_update_otg(dwc_otg_pcd_t *pcd, const unsigned reset) -{ - - if (!pcd->gadget.is_otg) - return; - - if (reset) { - pcd->b_hnp_enable = 0; - pcd->a_hnp_support = 0; - pcd->a_alt_hnp_support = 0; - } - - pcd->gadget.b_hnp_enable = pcd->b_hnp_enable; - pcd->gadget.a_hnp_support = pcd->a_hnp_support; - pcd->gadget.a_alt_hnp_support = pcd->a_alt_hnp_support; -} - -/** - * This function is the top level PCD interrupt handler. - */ -static irqreturn_t dwc_otg_pcd_irq(int irq, void *dev -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) - , struct pt_regs *r -#endif - ) -{ - dwc_otg_pcd_t *pcd = dev; - int32_t retval = IRQ_NONE; - - retval = dwc_otg_pcd_handle_intr(pcd); - return IRQ_RETVAL(retval); -} - -/** - * PCD Callback function for initializing the PCD when switching to - * device mode. - * - * @param p void pointer to the dwc_otg_pcd_t - */ -static int32_t dwc_otg_pcd_start_cb(void *p) -{ - dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)p; - - /* - * Initialized the Core for Device mode. - */ - if (dwc_otg_is_device_mode(GET_CORE_IF(pcd))) { - dwc_otg_core_dev_init(GET_CORE_IF(pcd)); - } - return 1; -} - -/** - * PCD Callback function for stopping the PCD when switching to Host - * mode. - * - * @param p void pointer to the dwc_otg_pcd_t - */ -static int32_t dwc_otg_pcd_stop_cb(void *p) -{ - dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)p; - extern void dwc_otg_pcd_stop(dwc_otg_pcd_t *_pcd); - - dwc_otg_pcd_stop(pcd); - return 1; -} - - -/** - * PCD Callback function for notifying the PCD when resuming from - * suspend. - * - * @param p void pointer to the dwc_otg_pcd_t - */ -static int32_t dwc_otg_pcd_suspend_cb(void *p) -{ - dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)p; - - if (pcd->driver && pcd->driver->resume) { - SPIN_UNLOCK(&pcd->lock); - pcd->driver->suspend(&pcd->gadget); - SPIN_LOCK(&pcd->lock); - } - - return 1; -} - - -/** - * PCD Callback function for notifying the PCD when resuming from - * suspend. - * - * @param p void pointer to the dwc_otg_pcd_t - */ -static int32_t dwc_otg_pcd_resume_cb(void *p) -{ - dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)p; - - if (pcd->driver && pcd->driver->resume) { - SPIN_UNLOCK(&pcd->lock); - pcd->driver->resume(&pcd->gadget); - SPIN_LOCK(&pcd->lock); - } - - /* Stop the SRP timeout timer. */ - if ((GET_CORE_IF(pcd)->core_params->phy_type != DWC_PHY_TYPE_PARAM_FS) || - (!GET_CORE_IF(pcd)->core_params->i2c_enable)) { - if (GET_CORE_IF(pcd)->srp_timer_started) { - GET_CORE_IF(pcd)->srp_timer_started = 0; - del_timer(&pcd->srp_timer); - } - } - return 1; -} - - -/** - * PCD Callback structure for handling mode switching. - */ -static dwc_otg_cil_callbacks_t pcd_callbacks = -{ - .start = dwc_otg_pcd_start_cb, - .stop = dwc_otg_pcd_stop_cb, - .suspend = dwc_otg_pcd_suspend_cb, - .resume_wakeup = dwc_otg_pcd_resume_cb, - .p = 0, /* Set at registration */ -}; - -/** - * This function is called when the SRP timer expires. The SRP should - * complete within 6 seconds. - */ -static void srp_timeout(unsigned long ptr) -{ - gotgctl_data_t gotgctl; - dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *)ptr; - volatile uint32_t *addr = &core_if->core_global_regs->gotgctl; - - gotgctl.d32 = dwc_read_reg32(addr); - - core_if->srp_timer_started = 0; - - if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) && - (core_if->core_params->i2c_enable)) { - DWC_PRINT("SRP Timeout\n"); - - if ((core_if->srp_success) && - (gotgctl.b.bsesvld)) { - if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) { - core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p); - } - - /* Clear Session Request */ - gotgctl.d32 = 0; - gotgctl.b.sesreq = 1; - dwc_modify_reg32(&core_if->core_global_regs->gotgctl, - gotgctl.d32, 0); - - core_if->srp_success = 0; - } - else { - DWC_ERROR("Device not connected/responding\n"); - gotgctl.b.sesreq = 0; - dwc_write_reg32(addr, gotgctl.d32); - } - } - else if (gotgctl.b.sesreq) { - DWC_PRINT("SRP Timeout\n"); - - DWC_ERROR("Device not connected/responding\n"); - gotgctl.b.sesreq = 0; - dwc_write_reg32(addr, gotgctl.d32); - } - else { - DWC_PRINT(" SRP GOTGCTL=%0x\n", gotgctl.d32); - } -} - -/** - * Start the SRP timer to detect when the SRP does not complete within - * 6 seconds. - * - * @param pcd the pcd structure. - */ -void dwc_otg_pcd_start_srp_timer(dwc_otg_pcd_t *pcd) -{ - struct timer_list *srp_timer = &pcd->srp_timer; - GET_CORE_IF(pcd)->srp_timer_started = 1; - init_timer(srp_timer); - srp_timer->function = srp_timeout; - srp_timer->data = (unsigned long)GET_CORE_IF(pcd); - srp_timer->expires = jiffies + (HZ*6); - add_timer(srp_timer); -} - -/** - * Tasklet - * - */ -extern void start_next_request(dwc_otg_pcd_ep_t *ep); - -static void start_xfer_tasklet_func (unsigned long data) -{ - dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t*)data; - dwc_otg_core_if_t *core_if = pcd->otg_dev->core_if; - - int i; - depctl_data_t diepctl; - - DWC_DEBUGPL(DBG_PCDV, "Start xfer tasklet\n"); - - diepctl.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[0]->diepctl); - - if (pcd->ep0.queue_sof) { - pcd->ep0.queue_sof = 0; - start_next_request (&pcd->ep0); - // break; - } - - for (i=0; idev_if->num_in_eps; i++) - { - depctl_data_t diepctl; - diepctl.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[i]->diepctl); - - if (pcd->in_ep[i].queue_sof) { - pcd->in_ep[i].queue_sof = 0; - start_next_request (&pcd->in_ep[i]); - // break; - } - } - - return; -} - - - - - - - -static struct tasklet_struct start_xfer_tasklet = { - .next = NULL, - .state = 0, - .count = ATOMIC_INIT(0), - .func = start_xfer_tasklet_func, - .data = 0, -}; -/** - * This function initialized the pcd Dp structures to there default - * state. - * - * @param pcd the pcd structure. - */ -void dwc_otg_pcd_reinit(dwc_otg_pcd_t *pcd) -{ - static const char * names[] = - { - - "ep0", - "ep1in", - "ep2in", - "ep3in", - "ep4in", - "ep5in", - "ep6in", - "ep7in", - "ep8in", - "ep9in", - "ep10in", - "ep11in", - "ep12in", - "ep13in", - "ep14in", - "ep15in", - "ep1out", - "ep2out", - "ep3out", - "ep4out", - "ep5out", - "ep6out", - "ep7out", - "ep8out", - "ep9out", - "ep10out", - "ep11out", - "ep12out", - "ep13out", - "ep14out", - "ep15out" - - }; - - int i; - int in_ep_cntr, out_ep_cntr; - uint32_t hwcfg1; - uint32_t num_in_eps = (GET_CORE_IF(pcd))->dev_if->num_in_eps; - uint32_t num_out_eps = (GET_CORE_IF(pcd))->dev_if->num_out_eps; - dwc_otg_pcd_ep_t *ep; - - DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pcd); - - INIT_LIST_HEAD (&pcd->gadget.ep_list); - pcd->gadget.ep0 = &pcd->ep0.ep; - pcd->gadget.speed = USB_SPEED_UNKNOWN; - - INIT_LIST_HEAD (&pcd->gadget.ep0->ep_list); - - /** - * Initialize the EP0 structure. - */ - ep = &pcd->ep0; - - /* Init EP structure */ - ep->desc = 0; - ep->pcd = pcd; - ep->stopped = 1; - - /* Init DWC ep structure */ - ep->dwc_ep.num = 0; - ep->dwc_ep.active = 0; - ep->dwc_ep.tx_fifo_num = 0; - /* Control until ep is actvated */ - ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL; - ep->dwc_ep.maxpacket = MAX_PACKET_SIZE; - ep->dwc_ep.dma_addr = 0; - ep->dwc_ep.start_xfer_buff = 0; - ep->dwc_ep.xfer_buff = 0; - ep->dwc_ep.xfer_len = 0; - ep->dwc_ep.xfer_count = 0; - ep->dwc_ep.sent_zlp = 0; - ep->dwc_ep.total_len = 0; - ep->queue_sof = 0; - ep->dwc_ep.desc_addr = 0; - ep->dwc_ep.dma_desc_addr = 0; - - - /* Init the usb_ep structure. */ - ep->ep.name = names[0]; - ep->ep.ops = (struct usb_ep_ops*)&dwc_otg_pcd_ep_ops; - - /** - * @todo NGS: What should the max packet size be set to - * here? Before EP type is set? - */ - ep->ep.maxpacket = MAX_PACKET_SIZE; - - list_add_tail (&ep->ep.ep_list, &pcd->gadget.ep_list); - - INIT_LIST_HEAD (&ep->queue); - /** - * Initialize the EP structures. - */ - in_ep_cntr = 0; - hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 3; - - for (i = 1; in_ep_cntr < num_in_eps; i++) - { - if((hwcfg1 & 0x1) == 0) { - dwc_otg_pcd_ep_t *ep = &pcd->in_ep[in_ep_cntr]; - in_ep_cntr ++; - - /* Init EP structure */ - ep->desc = 0; - ep->pcd = pcd; - ep->stopped = 1; - - /* Init DWC ep structure */ - ep->dwc_ep.is_in = 1; - ep->dwc_ep.num = i; - ep->dwc_ep.active = 0; - ep->dwc_ep.tx_fifo_num = 0; - - /* Control until ep is actvated */ - ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL; - ep->dwc_ep.maxpacket = MAX_PACKET_SIZE; - ep->dwc_ep.dma_addr = 0; - ep->dwc_ep.start_xfer_buff = 0; - ep->dwc_ep.xfer_buff = 0; - ep->dwc_ep.xfer_len = 0; - ep->dwc_ep.xfer_count = 0; - ep->dwc_ep.sent_zlp = 0; - ep->dwc_ep.total_len = 0; - ep->queue_sof = 0; - ep->dwc_ep.desc_addr = 0; - ep->dwc_ep.dma_desc_addr = 0; - - /* Init the usb_ep structure. */ - ep->ep.name = names[i]; - ep->ep.ops = (struct usb_ep_ops*)&dwc_otg_pcd_ep_ops; - - /** - * @todo NGS: What should the max packet size be set to - * here? Before EP type is set? - */ - ep->ep.maxpacket = MAX_PACKET_SIZE; - - list_add_tail (&ep->ep.ep_list, &pcd->gadget.ep_list); - - INIT_LIST_HEAD (&ep->queue); - } - hwcfg1 >>= 2; - } - - out_ep_cntr = 0; - hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 2; - - for (i = 1; out_ep_cntr < num_out_eps; i++) - { - if((hwcfg1 & 0x1) == 0) { - dwc_otg_pcd_ep_t *ep = &pcd->out_ep[out_ep_cntr]; - out_ep_cntr++; - - /* Init EP structure */ - ep->desc = 0; - ep->pcd = pcd; - ep->stopped = 1; - - /* Init DWC ep structure */ - ep->dwc_ep.is_in = 0; - ep->dwc_ep.num = i; - ep->dwc_ep.active = 0; - ep->dwc_ep.tx_fifo_num = 0; - /* Control until ep is actvated */ - ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL; - ep->dwc_ep.maxpacket = MAX_PACKET_SIZE; - ep->dwc_ep.dma_addr = 0; - ep->dwc_ep.start_xfer_buff = 0; - ep->dwc_ep.xfer_buff = 0; - ep->dwc_ep.xfer_len = 0; - ep->dwc_ep.xfer_count = 0; - ep->dwc_ep.sent_zlp = 0; - ep->dwc_ep.total_len = 0; - ep->queue_sof = 0; - - /* Init the usb_ep structure. */ - ep->ep.name = names[15 + i]; - ep->ep.ops = (struct usb_ep_ops*)&dwc_otg_pcd_ep_ops; - /** - * @todo NGS: What should the max packet size be set to - * here? Before EP type is set? - */ - ep->ep.maxpacket = MAX_PACKET_SIZE; - - list_add_tail (&ep->ep.ep_list, &pcd->gadget.ep_list); - - INIT_LIST_HEAD (&ep->queue); - } - hwcfg1 >>= 2; - } - - /* remove ep0 from the list. There is a ep0 pointer.*/ - list_del_init (&pcd->ep0.ep.ep_list); - - pcd->ep0state = EP0_DISCONNECT; - pcd->ep0.ep.maxpacket = MAX_EP0_SIZE; - pcd->ep0.dwc_ep.maxpacket = MAX_EP0_SIZE; - pcd->ep0.dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL; -} - -/** - * This function releases the Gadget device. - * required by device_unregister(). - * - * @todo Should this do something? Should it free the PCD? - */ -static void dwc_otg_pcd_gadget_release(struct device *dev) -{ - DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, dev); -} - - - -/** - * This function initialized the PCD portion of the driver. - * - */ - -int dwc_otg_pcd_init(struct device *dev) -{ - static char pcd_name[] = "dwc_otg_pcd"; - dwc_otg_pcd_t *pcd; - dwc_otg_core_if_t* core_if; - dwc_otg_dev_if_t* dev_if; - dwc_otg_device_t *otg_dev = dev_get_drvdata(dev); - int retval = 0; - - - DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n",__func__, dev); - /* - * Allocate PCD structure - */ - pcd = kmalloc(sizeof(dwc_otg_pcd_t), GFP_KERNEL); - - if (pcd == 0) { - return -ENOMEM; - } - - memset(pcd, 0, sizeof(dwc_otg_pcd_t)); - spin_lock_init(&pcd->lock); - - otg_dev->pcd = pcd; - s_pcd = pcd; - pcd->gadget.name = pcd_name; -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) - strcpy(pcd->gadget.dev.bus_id, "gadget"); -#else - dev_set_name(&pcd->gadget.dev, "%s", "gadget"); -#endif - - pcd->otg_dev = dev_get_drvdata(dev); - - pcd->gadget.dev.parent = dev; - pcd->gadget.dev.release = dwc_otg_pcd_gadget_release; - pcd->gadget.ops = &dwc_otg_pcd_ops; - - core_if = GET_CORE_IF(pcd); - dev_if = core_if->dev_if; - - if(core_if->hwcfg4.b.ded_fifo_en) { - DWC_PRINT("Dedicated Tx FIFOs mode\n"); - } - else { - DWC_PRINT("Shared Tx FIFO mode\n"); - } - - /* If the module is set to FS or if the PHY_TYPE is FS then the gadget - * should not report as dual-speed capable. replace the following line - * with the block of code below it once the software is debugged for - * this. If is_dualspeed = 0 then the gadget driver should not report - * a device qualifier descriptor when queried. */ - if ((GET_CORE_IF(pcd)->core_params->speed == DWC_SPEED_PARAM_FULL) || - ((GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == 2) && - (GET_CORE_IF(pcd)->hwcfg2.b.fs_phy_type == 1) && - (GET_CORE_IF(pcd)->core_params->ulpi_fs_ls))) { - pcd->gadget.is_dualspeed = 0; - } - else { - pcd->gadget.is_dualspeed = 1; - } - - if ((otg_dev->core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE) || - (otg_dev->core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST) || - (otg_dev->core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) || - (otg_dev->core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) { - pcd->gadget.is_otg = 0; - } - else { - pcd->gadget.is_otg = 1; - } - - - pcd->driver = 0; - /* Register the gadget device */ - retval = device_register(&pcd->gadget.dev); - if (retval != 0) { - kfree (pcd); - return retval; - } - - - /* - * Initialized the Core for Device mode. - */ - if (dwc_otg_is_device_mode(core_if)) { - dwc_otg_core_dev_init(core_if); - } - - /* - * Initialize EP structures - */ - dwc_otg_pcd_reinit(pcd); - - /* - * Register the PCD Callbacks. - */ - dwc_otg_cil_register_pcd_callbacks(otg_dev->core_if, &pcd_callbacks, - pcd); - /* - * Setup interupt handler - */ - DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n", otg_dev->irq); - retval = request_irq(otg_dev->irq, dwc_otg_pcd_irq, - IRQF_SHARED, pcd->gadget.name, pcd); - if (retval != 0) { - DWC_ERROR("request of irq%d failed\n", otg_dev->irq); - device_unregister(&pcd->gadget.dev); - kfree (pcd); - return -EBUSY; - } - - /* - * Initialize the DMA buffer for SETUP packets - */ - if (GET_CORE_IF(pcd)->dma_enable) { - pcd->setup_pkt = dma_alloc_coherent (NULL, sizeof (*pcd->setup_pkt) * 5, &pcd->setup_pkt_dma_handle, 0); - if (pcd->setup_pkt == 0) { - free_irq(otg_dev->irq, pcd); - device_unregister(&pcd->gadget.dev); - kfree (pcd); - return -ENOMEM; - } - - pcd->status_buf = dma_alloc_coherent (NULL, sizeof (uint16_t), &pcd->status_buf_dma_handle, 0); - if (pcd->status_buf == 0) { - dma_free_coherent(NULL, sizeof(*pcd->setup_pkt), pcd->setup_pkt, pcd->setup_pkt_dma_handle); - free_irq(otg_dev->irq, pcd); - device_unregister(&pcd->gadget.dev); - kfree (pcd); - return -ENOMEM; - } - - if (GET_CORE_IF(pcd)->dma_desc_enable) { - dev_if->setup_desc_addr[0] = dwc_otg_ep_alloc_desc_chain(&dev_if->dma_setup_desc_addr[0], 1); - dev_if->setup_desc_addr[1] = dwc_otg_ep_alloc_desc_chain(&dev_if->dma_setup_desc_addr[1], 1); - dev_if->in_desc_addr = dwc_otg_ep_alloc_desc_chain(&dev_if->dma_in_desc_addr, 1); - dev_if->out_desc_addr = dwc_otg_ep_alloc_desc_chain(&dev_if->dma_out_desc_addr, 1); - - if(dev_if->setup_desc_addr[0] == 0 - || dev_if->setup_desc_addr[1] == 0 - || dev_if->in_desc_addr == 0 - || dev_if->out_desc_addr == 0 ) { - - if(dev_if->out_desc_addr) - dwc_otg_ep_free_desc_chain(dev_if->out_desc_addr, dev_if->dma_out_desc_addr, 1); - if(dev_if->in_desc_addr) - dwc_otg_ep_free_desc_chain(dev_if->in_desc_addr, dev_if->dma_in_desc_addr, 1); - if(dev_if->setup_desc_addr[1]) - dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[1], dev_if->dma_setup_desc_addr[1], 1); - if(dev_if->setup_desc_addr[0]) - dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[0], dev_if->dma_setup_desc_addr[0], 1); - - - dma_free_coherent(NULL, sizeof(*pcd->status_buf), pcd->status_buf, pcd->setup_pkt_dma_handle); - dma_free_coherent(NULL, sizeof(*pcd->setup_pkt), pcd->setup_pkt, pcd->setup_pkt_dma_handle); - - free_irq(otg_dev->irq, pcd); - device_unregister(&pcd->gadget.dev); - kfree (pcd); - - return -ENOMEM; - } - } - } - else { - pcd->setup_pkt = kmalloc (sizeof (*pcd->setup_pkt) * 5, GFP_KERNEL); - if (pcd->setup_pkt == 0) { - free_irq(otg_dev->irq, pcd); - device_unregister(&pcd->gadget.dev); - kfree (pcd); - return -ENOMEM; - } - - pcd->status_buf = kmalloc (sizeof (uint16_t), GFP_KERNEL); - if (pcd->status_buf == 0) { - kfree(pcd->setup_pkt); - free_irq(otg_dev->irq, pcd); - device_unregister(&pcd->gadget.dev); - kfree (pcd); - return -ENOMEM; - } - } - - - /* Initialize tasklet */ - start_xfer_tasklet.data = (unsigned long)pcd; - pcd->start_xfer_tasklet = &start_xfer_tasklet; - - return 0; -} - -/** - * Cleanup the PCD. - */ -void dwc_otg_pcd_remove(struct device *dev) -{ - dwc_otg_device_t *otg_dev = dev_get_drvdata(dev); - dwc_otg_pcd_t *pcd = otg_dev->pcd; - dwc_otg_dev_if_t* dev_if = GET_CORE_IF(pcd)->dev_if; - - DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, dev); - - /* - * Free the IRQ - */ - free_irq(otg_dev->irq, pcd); - - /* start with the driver above us */ - if (pcd->driver) { - /* should have been done already by driver model core */ - DWC_WARN("driver '%s' is still registered\n", - pcd->driver->driver.name); - usb_gadget_unregister_driver(pcd->driver); - } - device_unregister(&pcd->gadget.dev); - - if (GET_CORE_IF(pcd)->dma_enable) { - dma_free_coherent (NULL, sizeof (*pcd->setup_pkt) * 5, pcd->setup_pkt, pcd->setup_pkt_dma_handle); - dma_free_coherent (NULL, sizeof (uint16_t), pcd->status_buf, pcd->status_buf_dma_handle); - if (GET_CORE_IF(pcd)->dma_desc_enable) { - dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[0], dev_if->dma_setup_desc_addr[0], 1); - dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[1], dev_if->dma_setup_desc_addr[1], 1); - dwc_otg_ep_free_desc_chain(dev_if->in_desc_addr, dev_if->dma_in_desc_addr, 1); - dwc_otg_ep_free_desc_chain(dev_if->out_desc_addr, dev_if->dma_out_desc_addr, 1); - } - } - else { - kfree (pcd->setup_pkt); - kfree (pcd->status_buf); - } - - kfree(pcd); - otg_dev->pcd = 0; -} - -/** - * This function registers a gadget driver with the PCD. - * - * When a driver is successfully registered, it will receive control - * requests including set_configuration(), which enables non-control - * requests. then usb traffic follows until a disconnect is reported. - * then a host may connect again, or the driver might get unbound. - * - * @param driver The driver being registered - */ -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37) -int usb_gadget_probe_driver(struct usb_gadget_driver *driver, int (*bind)(struct usb_gadget *)) -#else -int usb_gadget_register_driver(struct usb_gadget_driver *driver) -#endif -{ - int retval; - int (*d_bind)(struct usb_gadget *); -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37) - d_bind = bind; -#else - d_bind = driver->bind; -#endif - - DWC_DEBUGPL(DBG_PCD, "registering gadget driver '%s'\n", driver->driver.name); - - if (!driver || driver->speed == USB_SPEED_UNKNOWN || - !d_bind || - !driver->unbind || - !driver->disconnect || - !driver->setup) { - DWC_DEBUGPL(DBG_PCDV,"EINVAL\n"); - return -EINVAL; - } - if (s_pcd == 0) { - DWC_DEBUGPL(DBG_PCDV,"ENODEV\n"); - return -ENODEV; - } - if (s_pcd->driver != 0) { - DWC_DEBUGPL(DBG_PCDV,"EBUSY (%p)\n", s_pcd->driver); - return -EBUSY; - } - - /* hook up the driver */ - s_pcd->driver = driver; - s_pcd->gadget.dev.driver = &driver->driver; - - DWC_DEBUGPL(DBG_PCD, "bind to driver %s\n", driver->driver.name); - retval = d_bind(&s_pcd->gadget); - if (retval) { - DWC_ERROR("bind to driver %s --> error %d\n", - driver->driver.name, retval); - s_pcd->driver = 0; - s_pcd->gadget.dev.driver = 0; - return retval; - } - DWC_DEBUGPL(DBG_ANY, "registered gadget driver '%s'\n", - driver->driver.name); - return 0; -} - -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37) -EXPORT_SYMBOL(usb_gadget_probe_driver); -#else -EXPORT_SYMBOL(usb_gadget_register_driver); -#endif - -/** - * This function unregisters a gadget driver - * - * @param driver The driver being unregistered - */ -int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) -{ - //DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, _driver); - - if (s_pcd == 0) { - DWC_DEBUGPL(DBG_ANY, "%s Return(%d): s_pcd==0\n", __func__, - -ENODEV); - return -ENODEV; - } - if (driver == 0 || driver != s_pcd->driver) { - DWC_DEBUGPL(DBG_ANY, "%s Return(%d): driver?\n", __func__, - -EINVAL); - return -EINVAL; - } - - driver->unbind(&s_pcd->gadget); - s_pcd->driver = 0; - - DWC_DEBUGPL(DBG_ANY, "unregistered driver '%s'\n", - driver->driver.name); - return 0; -} -EXPORT_SYMBOL(usb_gadget_unregister_driver); - -#endif /* DWC_HOST_ONLY */ diff --git a/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_pcd.h b/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_pcd.h deleted file mode 100644 index 48de957840..0000000000 --- a/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_pcd.h +++ /dev/null @@ -1,248 +0,0 @@ -/* ========================================================================== - * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $ - * $Revision: 1.2 $ - * $Date: 2008-11-21 05:39:15 $ - * $Change: 1103515 $ - * - * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, - * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless - * otherwise expressly agreed to in writing between Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ -#ifndef DWC_HOST_ONLY -#if !defined(__DWC_PCD_H__) -#define __DWC_PCD_H__ - -#include -#include -#include -#include - -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21) -# include -#else -# include -#endif - -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) -#include -#else -#include -#endif -#include -#include - -struct dwc_otg_device; - -#include "dwc_otg_cil.h" - -/** - * @file - * - * This file contains the structures, constants, and interfaces for - * the Perpherial Contoller Driver (PCD). - * - * The Peripheral Controller Driver (PCD) for Linux will implement the - * Gadget API, so that the existing Gadget drivers can be used. For - * the Mass Storage Function driver the File-backed USB Storage Gadget - * (FBS) driver will be used. The FBS driver supports the - * Control-Bulk (CB), Control-Bulk-Interrupt (CBI), and Bulk-Only - * transports. - * - */ - -/** Invalid DMA Address */ -#define DMA_ADDR_INVALID (~(dma_addr_t)0) -/** Maxpacket size for EP0 */ -#define MAX_EP0_SIZE 64 -/** Maxpacket size for any EP */ -#define MAX_PACKET_SIZE 1024 - -/** Max Transfer size for any EP */ -#define MAX_TRANSFER_SIZE 65535 - -/** Max DMA Descriptor count for any EP */ -#define MAX_DMA_DESC_CNT 64 - -/** - * Get the pointer to the core_if from the pcd pointer. - */ -#define GET_CORE_IF( _pcd ) (_pcd->otg_dev->core_if) - -/** - * States of EP0. - */ -typedef enum ep0_state -{ - EP0_DISCONNECT, /* no host */ - EP0_IDLE, - EP0_IN_DATA_PHASE, - EP0_OUT_DATA_PHASE, - EP0_IN_STATUS_PHASE, - EP0_OUT_STATUS_PHASE, - EP0_STALL, -} ep0state_e; - -/** Fordward declaration.*/ -struct dwc_otg_pcd; - -/** DWC_otg iso request structure. - * - */ -typedef struct usb_iso_request dwc_otg_pcd_iso_request_t; - -/** PCD EP structure. - * This structure describes an EP, there is an array of EPs in the PCD - * structure. - */ -typedef struct dwc_otg_pcd_ep -{ - /** USB EP data */ - struct usb_ep ep; - /** USB EP Descriptor */ - const struct usb_endpoint_descriptor *desc; - - /** queue of dwc_otg_pcd_requests. */ - struct list_head queue; - unsigned stopped : 1; - unsigned disabling : 1; - unsigned dma : 1; - unsigned queue_sof : 1; - -#ifdef DWC_EN_ISOC - /** DWC_otg Isochronous Transfer */ - struct usb_iso_request* iso_req; -#endif //DWC_EN_ISOC - - /** DWC_otg ep data. */ - dwc_ep_t dwc_ep; - - /** Pointer to PCD */ - struct dwc_otg_pcd *pcd; -}dwc_otg_pcd_ep_t; - - - -/** DWC_otg PCD Structure. - * This structure encapsulates the data for the dwc_otg PCD. - */ -typedef struct dwc_otg_pcd -{ - /** USB gadget */ - struct usb_gadget gadget; - /** USB gadget driver pointer*/ - struct usb_gadget_driver *driver; - /** The DWC otg device pointer. */ - struct dwc_otg_device *otg_dev; - - /** State of EP0 */ - ep0state_e ep0state; - /** EP0 Request is pending */ - unsigned ep0_pending : 1; - /** Indicates when SET CONFIGURATION Request is in process */ - unsigned request_config : 1; - /** The state of the Remote Wakeup Enable. */ - unsigned remote_wakeup_enable : 1; - /** The state of the B-Device HNP Enable. */ - unsigned b_hnp_enable : 1; - /** The state of A-Device HNP Support. */ - unsigned a_hnp_support : 1; - /** The state of the A-Device Alt HNP support. */ - unsigned a_alt_hnp_support : 1; - /** Count of pending Requests */ - unsigned request_pending; - - /** SETUP packet for EP0 - * This structure is allocated as a DMA buffer on PCD initialization - * with enough space for up to 3 setup packets. - */ - union - { - struct usb_ctrlrequest req; - uint32_t d32[2]; - } *setup_pkt; - - dma_addr_t setup_pkt_dma_handle; - - /** 2-byte dma buffer used to return status from GET_STATUS */ - uint16_t *status_buf; - dma_addr_t status_buf_dma_handle; - - /** EP0 */ - dwc_otg_pcd_ep_t ep0; - - /** Array of IN EPs. */ - dwc_otg_pcd_ep_t in_ep[ MAX_EPS_CHANNELS - 1]; - /** Array of OUT EPs. */ - dwc_otg_pcd_ep_t out_ep[ MAX_EPS_CHANNELS - 1]; - /** number of valid EPs in the above array. */ -// unsigned num_eps : 4; - spinlock_t lock; - /** Timer for SRP. If it expires before SRP is successful - * clear the SRP. */ - struct timer_list srp_timer; - - /** Tasklet to defer starting of TEST mode transmissions until - * Status Phase has been completed. - */ - struct tasklet_struct test_mode_tasklet; - - /** Tasklet to delay starting of xfer in DMA mode */ - struct tasklet_struct *start_xfer_tasklet; - - /** The test mode to enter when the tasklet is executed. */ - unsigned test_mode; - -} dwc_otg_pcd_t; - - -/** DWC_otg request structure. - * This structure is a list of requests. - */ -typedef struct -{ - struct usb_request req; /**< USB Request. */ - struct list_head queue; /**< queue of these requests. */ -} dwc_otg_pcd_request_t; - - -extern int dwc_otg_pcd_init(struct device *dev); - -//extern void dwc_otg_pcd_remove( struct dwc_otg_device *_otg_dev ); -extern void dwc_otg_pcd_remove( struct device *dev); -extern int32_t dwc_otg_pcd_handle_intr( dwc_otg_pcd_t *pcd ); -extern void dwc_otg_pcd_start_srp_timer(dwc_otg_pcd_t *pcd ); - -extern void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t *pcd); -extern void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t *pcd, int set); - -extern void dwc_otg_iso_buffer_done(dwc_otg_pcd_ep_t *ep, dwc_otg_pcd_iso_request_t *req); -extern void dwc_otg_request_done(dwc_otg_pcd_ep_t *_ep, dwc_otg_pcd_request_t *req, - int status); -extern void dwc_otg_request_nuke(dwc_otg_pcd_ep_t *_ep); -extern void dwc_otg_pcd_update_otg(dwc_otg_pcd_t *_pcd, - const unsigned reset); - -#endif -#endif /* DWC_HOST_ONLY */ diff --git a/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_pcd_intr.c b/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_pcd_intr.c deleted file mode 100644 index fd44fd89c3..0000000000 --- a/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_pcd_intr.c +++ /dev/null @@ -1,3654 +0,0 @@ -/* ========================================================================== - * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_intr.c $ - * $Revision: 1.2 $ - * $Date: 2008-11-21 05:39:15 $ - * $Change: 1115682 $ - * - * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, - * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless - * otherwise expressly agreed to in writing between Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ -#ifndef DWC_HOST_ONLY -#include -#include -#include - -#include "dwc_otg_driver.h" -#include "dwc_otg_pcd.h" - - -#define DEBUG_EP0 - -/* request functions defined in "dwc_otg_pcd.c" */ - -/** @file - * This file contains the implementation of the PCD Interrupt handlers. - * - * The PCD handles the device interrupts. Many conditions can cause a - * device interrupt. When an interrupt occurs, the device interrupt - * service routine determines the cause of the interrupt and - * dispatches handling to the appropriate function. These interrupt - * handling functions are described below. - * All interrupt registers are processed from LSB to MSB. - */ - - -/** - * This function prints the ep0 state for debug purposes. - */ -static inline void print_ep0_state(dwc_otg_pcd_t *pcd) -{ -#ifdef DEBUG - char str[40]; - - switch (pcd->ep0state) { - case EP0_DISCONNECT: - strcpy(str, "EP0_DISCONNECT"); - break; - case EP0_IDLE: - strcpy(str, "EP0_IDLE"); - break; - case EP0_IN_DATA_PHASE: - strcpy(str, "EP0_IN_DATA_PHASE"); - break; - case EP0_OUT_DATA_PHASE: - strcpy(str, "EP0_OUT_DATA_PHASE"); - break; - case EP0_IN_STATUS_PHASE: - strcpy(str,"EP0_IN_STATUS_PHASE"); - break; - case EP0_OUT_STATUS_PHASE: - strcpy(str,"EP0_OUT_STATUS_PHASE"); - break; - case EP0_STALL: - strcpy(str,"EP0_STALL"); - break; - default: - strcpy(str,"EP0_INVALID"); - } - - DWC_DEBUGPL(DBG_ANY, "%s(%d)\n", str, pcd->ep0state); -#endif -} - -/** - * This function returns pointer to in ep struct with number ep_num - */ -static inline dwc_otg_pcd_ep_t* get_in_ep(dwc_otg_pcd_t *pcd, uint32_t ep_num) -{ - int i; - int num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps; - if(ep_num == 0) { - return &pcd->ep0; - } - else { - for(i = 0; i < num_in_eps; ++i) - { - if(pcd->in_ep[i].dwc_ep.num == ep_num) - return &pcd->in_ep[i]; - } - return 0; - } -} -/** - * This function returns pointer to out ep struct with number ep_num - */ -static inline dwc_otg_pcd_ep_t* get_out_ep(dwc_otg_pcd_t *pcd, uint32_t ep_num) -{ - int i; - int num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps; - if(ep_num == 0) { - return &pcd->ep0; - } - else { - for(i = 0; i < num_out_eps; ++i) - { - if(pcd->out_ep[i].dwc_ep.num == ep_num) - return &pcd->out_ep[i]; - } - return 0; - } -} -/** - * This functions gets a pointer to an EP from the wIndex address - * value of the control request. - */ -static dwc_otg_pcd_ep_t *get_ep_by_addr (dwc_otg_pcd_t *pcd, u16 wIndex) -{ - dwc_otg_pcd_ep_t *ep; - - if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0) - return &pcd->ep0; - list_for_each_entry(ep, &pcd->gadget.ep_list, ep.ep_list) - { - u8 bEndpointAddress; - - if (!ep->desc) - continue; - - bEndpointAddress = ep->desc->bEndpointAddress; - if((wIndex & (USB_DIR_IN | USB_ENDPOINT_NUMBER_MASK)) - == (bEndpointAddress & (USB_DIR_IN | USB_ENDPOINT_NUMBER_MASK))) - return ep; - } - return NULL; -} - -/** - * This function checks the EP request queue, if the queue is not - * empty the next request is started. - */ -void start_next_request(dwc_otg_pcd_ep_t *ep) -{ - dwc_otg_pcd_request_t *req = 0; - uint32_t max_transfer = GET_CORE_IF(ep->pcd)->core_params->max_transfer_size; - - if (!list_empty(&ep->queue)) { - req = list_entry(ep->queue.next, - dwc_otg_pcd_request_t, queue); - - /* Setup and start the Transfer */ - ep->dwc_ep.dma_addr = req->req.dma; - ep->dwc_ep.start_xfer_buff = req->req.buf; - ep->dwc_ep.xfer_buff = req->req.buf; - ep->dwc_ep.sent_zlp = 0; - ep->dwc_ep.total_len = req->req.length; - ep->dwc_ep.xfer_len = 0; - ep->dwc_ep.xfer_count = 0; - - if(max_transfer > MAX_TRANSFER_SIZE) { - ep->dwc_ep.maxxfer = max_transfer - (max_transfer % ep->dwc_ep.maxpacket); - } else { - ep->dwc_ep.maxxfer = max_transfer; - } - - if(req->req.zero) { - if((ep->dwc_ep.total_len % ep->dwc_ep.maxpacket == 0) - && (ep->dwc_ep.total_len != 0)) { - ep->dwc_ep.sent_zlp = 1; - } - - } - - dwc_otg_ep_start_transfer(GET_CORE_IF(ep->pcd), &ep->dwc_ep); - } -} - -/** - * This function handles the SOF Interrupts. At this time the SOF - * Interrupt is disabled. - */ -int32_t dwc_otg_pcd_handle_sof_intr(dwc_otg_pcd_t *pcd) -{ - dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); - - gintsts_data_t gintsts; - - DWC_DEBUGPL(DBG_PCD, "SOF\n"); - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.sofintr = 1; - dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32); - - return 1; -} - - -/** - * This function handles the Rx Status Queue Level Interrupt, which - * indicates that there is a least one packet in the Rx FIFO. The - * packets are moved from the FIFO to memory, where they will be - * processed when the Endpoint Interrupt Register indicates Transfer - * Complete or SETUP Phase Done. - * - * Repeat the following until the Rx Status Queue is empty: - * -# Read the Receive Status Pop Register (GRXSTSP) to get Packet - * info - * -# If Receive FIFO is empty then skip to step Clear the interrupt - * and exit - * -# If SETUP Packet call dwc_otg_read_setup_packet to copy the - * SETUP data to the buffer - * -# If OUT Data Packet call dwc_otg_read_packet to copy the data - * to the destination buffer - */ -int32_t dwc_otg_pcd_handle_rx_status_q_level_intr(dwc_otg_pcd_t *pcd) -{ - dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); - dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; - gintmsk_data_t gintmask = {.d32=0}; - device_grxsts_data_t status; - dwc_otg_pcd_ep_t *ep; - gintsts_data_t gintsts; -#ifdef DEBUG - static char *dpid_str[] ={ "D0", "D2", "D1", "MDATA" }; -#endif - - //DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _pcd); - /* Disable the Rx Status Queue Level interrupt */ - gintmask.b.rxstsqlvl= 1; - dwc_modify_reg32(&global_regs->gintmsk, gintmask.d32, 0); - - /* Get the Status from the top of the FIFO */ - status.d32 = dwc_read_reg32(&global_regs->grxstsp); - - DWC_DEBUGPL(DBG_PCD, "EP:%d BCnt:%d DPID:%s " - "pktsts:%x Frame:%d(0x%0x)\n", - status.b.epnum, status.b.bcnt, - dpid_str[status.b.dpid], - status.b.pktsts, status.b.fn, status.b.fn); - /* Get pointer to EP structure */ - ep = get_out_ep(pcd, status.b.epnum); - - switch (status.b.pktsts) { - case DWC_DSTS_GOUT_NAK: - DWC_DEBUGPL(DBG_PCDV, "Global OUT NAK\n"); - break; - case DWC_STS_DATA_UPDT: - DWC_DEBUGPL(DBG_PCDV, "OUT Data Packet\n"); - if (status.b.bcnt && ep->dwc_ep.xfer_buff) { - /** @todo NGS Check for buffer overflow? */ - dwc_otg_read_packet(core_if, - ep->dwc_ep.xfer_buff, - status.b.bcnt); - ep->dwc_ep.xfer_count += status.b.bcnt; - ep->dwc_ep.xfer_buff += status.b.bcnt; - } - break; - case DWC_STS_XFER_COMP: - DWC_DEBUGPL(DBG_PCDV, "OUT Complete\n"); - break; - case DWC_DSTS_SETUP_COMP: -#ifdef DEBUG_EP0 - DWC_DEBUGPL(DBG_PCDV, "Setup Complete\n"); -#endif - break; -case DWC_DSTS_SETUP_UPDT: - dwc_otg_read_setup_packet(core_if, pcd->setup_pkt->d32); -#ifdef DEBUG_EP0 - DWC_DEBUGPL(DBG_PCD, - "SETUP PKT: %02x.%02x v%04x i%04x l%04x\n", - pcd->setup_pkt->req.bRequestType, - pcd->setup_pkt->req.bRequest, - pcd->setup_pkt->req.wValue, - pcd->setup_pkt->req.wIndex, - pcd->setup_pkt->req.wLength); -#endif - ep->dwc_ep.xfer_count += status.b.bcnt; - break; - default: - DWC_DEBUGPL(DBG_PCDV, "Invalid Packet Status (0x%0x)\n", - status.b.pktsts); - break; - } - - /* Enable the Rx Status Queue Level interrupt */ - dwc_modify_reg32(&global_regs->gintmsk, 0, gintmask.d32); - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.rxstsqlvl = 1; - dwc_write_reg32 (&global_regs->gintsts, gintsts.d32); - - //DWC_DEBUGPL(DBG_PCDV, "EXIT: %s\n", __func__); - return 1; -} -/** - * This function examines the Device IN Token Learning Queue to - * determine the EP number of the last IN token received. This - * implementation is for the Mass Storage device where there are only - * 2 IN EPs (Control-IN and BULK-IN). - * - * The EP numbers for the first six IN Tokens are in DTKNQR1 and there - * are 8 EP Numbers in each of the other possible DTKNQ Registers. - * - * @param core_if Programming view of DWC_otg controller. - * - */ -static inline int get_ep_of_last_in_token(dwc_otg_core_if_t *core_if) -{ - dwc_otg_device_global_regs_t *dev_global_regs = - core_if->dev_if->dev_global_regs; - const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth; - /* Number of Token Queue Registers */ - const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8; - dtknq1_data_t dtknqr1; - uint32_t in_tkn_epnums[4]; - int ndx = 0; - int i = 0; - volatile uint32_t *addr = &dev_global_regs->dtknqr1; - int epnum = 0; - - //DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH); - - - /* Read the DTKNQ Registers */ - for (i = 0; i < DTKNQ_REG_CNT; i++) - { - in_tkn_epnums[ i ] = dwc_read_reg32(addr); - DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i+1, - in_tkn_epnums[i]); - if (addr == &dev_global_regs->dvbusdis) { - addr = &dev_global_regs->dtknqr3_dthrctl; - } - else { - ++addr; - } - - } - - /* Copy the DTKNQR1 data to the bit field. */ - dtknqr1.d32 = in_tkn_epnums[0]; - /* Get the EP numbers */ - in_tkn_epnums[0] = dtknqr1.b.epnums0_5; - ndx = dtknqr1.b.intknwptr - 1; - - //DWC_DEBUGPL(DBG_PCDV,"ndx=%d\n",ndx); - if (ndx == -1) { - /** @todo Find a simpler way to calculate the max - * queue position.*/ - int cnt = TOKEN_Q_DEPTH; - if (TOKEN_Q_DEPTH <= 6) { - cnt = TOKEN_Q_DEPTH - 1; - } - else if (TOKEN_Q_DEPTH <= 14) { - cnt = TOKEN_Q_DEPTH - 7; - } - else if (TOKEN_Q_DEPTH <= 22) { - cnt = TOKEN_Q_DEPTH - 15; - } - else { - cnt = TOKEN_Q_DEPTH - 23; - } - epnum = (in_tkn_epnums[ DTKNQ_REG_CNT - 1 ] >> (cnt * 4)) & 0xF; - } - else { - if (ndx <= 5) { - epnum = (in_tkn_epnums[0] >> (ndx * 4)) & 0xF; - } - else if (ndx <= 13) { - ndx -= 6; - epnum = (in_tkn_epnums[1] >> (ndx * 4)) & 0xF; - } - else if (ndx <= 21) { - ndx -= 14; - epnum = (in_tkn_epnums[2] >> (ndx * 4)) & 0xF; - } - else if (ndx <= 29) { - ndx -= 22; - epnum = (in_tkn_epnums[3] >> (ndx * 4)) & 0xF; - } - } - //DWC_DEBUGPL(DBG_PCD,"epnum=%d\n",epnum); - return epnum; -} - -/** - * This interrupt occurs when the non-periodic Tx FIFO is half-empty. - * The active request is checked for the next packet to be loaded into - * the non-periodic Tx FIFO. - */ -int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr(dwc_otg_pcd_t *pcd) -{ - dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); - dwc_otg_core_global_regs_t *global_regs = - core_if->core_global_regs; - dwc_otg_dev_in_ep_regs_t *ep_regs; - gnptxsts_data_t txstatus = {.d32 = 0}; - gintsts_data_t gintsts; - - int epnum = 0; - dwc_otg_pcd_ep_t *ep = 0; - uint32_t len = 0; - int dwords; - - /* Get the epnum from the IN Token Learning Queue. */ - epnum = get_ep_of_last_in_token(core_if); - ep = get_in_ep(pcd, epnum); - - DWC_DEBUGPL(DBG_PCD, "NP TxFifo Empty: %s(%d) \n", ep->ep.name, epnum); - ep_regs = core_if->dev_if->in_ep_regs[epnum]; - - len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count; - if (len > ep->dwc_ep.maxpacket) { - len = ep->dwc_ep.maxpacket; - } - dwords = (len + 3)/4; - - - /* While there is space in the queue and space in the FIFO and - * More data to tranfer, Write packets to the Tx FIFO */ - txstatus.d32 = dwc_read_reg32(&global_regs->gnptxsts); - DWC_DEBUGPL(DBG_PCDV, "b4 GNPTXSTS=0x%08x\n",txstatus.d32); - - while (txstatus.b.nptxqspcavail > 0 && - txstatus.b.nptxfspcavail > dwords && - ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len) { - /* Write the FIFO */ - dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0); - len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count; - - if (len > ep->dwc_ep.maxpacket) { - len = ep->dwc_ep.maxpacket; - } - - dwords = (len + 3)/4; - txstatus.d32 = dwc_read_reg32(&global_regs->gnptxsts); - DWC_DEBUGPL(DBG_PCDV,"GNPTXSTS=0x%08x\n",txstatus.d32); - } - - DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n", - dwc_read_reg32(&global_regs->gnptxsts)); - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.nptxfempty = 1; - dwc_write_reg32 (&global_regs->gintsts, gintsts.d32); - - return 1; -} - -/** - * This function is called when dedicated Tx FIFO Empty interrupt occurs. - * The active request is checked for the next packet to be loaded into - * apropriate Tx FIFO. - */ -static int32_t write_empty_tx_fifo(dwc_otg_pcd_t *pcd, uint32_t epnum) -{ - dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); - dwc_otg_dev_if_t* dev_if = core_if->dev_if; - dwc_otg_dev_in_ep_regs_t *ep_regs; - dtxfsts_data_t txstatus = {.d32 = 0}; - dwc_otg_pcd_ep_t *ep = 0; - uint32_t len = 0; - int dwords; - - ep = get_in_ep(pcd, epnum); - - DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %s(%d) \n", ep->ep.name, epnum); - - ep_regs = core_if->dev_if->in_ep_regs[epnum]; - - len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count; - - if (len > ep->dwc_ep.maxpacket) { - len = ep->dwc_ep.maxpacket; - } - - dwords = (len + 3)/4; - - /* While there is space in the queue and space in the FIFO and - * More data to tranfer, Write packets to the Tx FIFO */ - txstatus.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts); - DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n",epnum,txstatus.d32); - - while (txstatus.b.txfspcavail > dwords && - ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len && - ep->dwc_ep.xfer_len != 0) { - /* Write the FIFO */ - dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0); - - len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count; - if (len > ep->dwc_ep.maxpacket) { - len = ep->dwc_ep.maxpacket; - } - - dwords = (len + 3)/4; - txstatus.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts); - DWC_DEBUGPL(DBG_PCDV,"dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32); - } - - DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n",epnum,dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts)); - - return 1; -} - - -/** - * This function is called when the Device is disconnected. It stops - * any active requests and informs the Gadget driver of the - * disconnect. - */ -void dwc_otg_pcd_stop(dwc_otg_pcd_t *pcd) -{ - int i, num_in_eps, num_out_eps; - dwc_otg_pcd_ep_t *ep; - - gintmsk_data_t intr_mask = {.d32 = 0}; - - num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps; - num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps; - - DWC_DEBUGPL(DBG_PCDV, "%s() \n", __func__); - /* don't disconnect drivers more than once */ - if (pcd->ep0state == EP0_DISCONNECT) { - DWC_DEBUGPL(DBG_ANY, "%s() Already Disconnected\n", __func__); - return; - } - pcd->ep0state = EP0_DISCONNECT; - - /* Reset the OTG state. */ - dwc_otg_pcd_update_otg(pcd, 1); - - /* Disable the NP Tx Fifo Empty Interrupt. */ - intr_mask.b.nptxfempty = 1; - dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, - intr_mask.d32, 0); - - /* Flush the FIFOs */ - /**@todo NGS Flush Periodic FIFOs */ - dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), 0x10); - dwc_otg_flush_rx_fifo(GET_CORE_IF(pcd)); - - /* prevent new request submissions, kill any outstanding requests */ - ep = &pcd->ep0; - dwc_otg_request_nuke(ep); - /* prevent new request submissions, kill any outstanding requests */ - for (i = 0; i < num_in_eps; i++) - { - dwc_otg_pcd_ep_t *ep = &pcd->in_ep[i]; - dwc_otg_request_nuke(ep); - } - /* prevent new request submissions, kill any outstanding requests */ - for (i = 0; i < num_out_eps; i++) - { - dwc_otg_pcd_ep_t *ep = &pcd->out_ep[i]; - dwc_otg_request_nuke(ep); - } - - /* report disconnect; the driver is already quiesced */ - if (pcd->driver && pcd->driver->disconnect) { - SPIN_UNLOCK(&pcd->lock); - pcd->driver->disconnect(&pcd->gadget); - SPIN_LOCK(&pcd->lock); - } -} - -/** - * This interrupt indicates that ... - */ -int32_t dwc_otg_pcd_handle_i2c_intr(dwc_otg_pcd_t *pcd) -{ - gintmsk_data_t intr_mask = { .d32 = 0}; - gintsts_data_t gintsts; - - DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "i2cintr"); - intr_mask.b.i2cintr = 1; - dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, - intr_mask.d32, 0); - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.i2cintr = 1; - dwc_write_reg32 (&GET_CORE_IF(pcd)->core_global_regs->gintsts, - gintsts.d32); - return 1; -} - - -/** - * This interrupt indicates that ... - */ -int32_t dwc_otg_pcd_handle_early_suspend_intr(dwc_otg_pcd_t *pcd) -{ - gintsts_data_t gintsts; -#if defined(VERBOSE) - DWC_PRINT("Early Suspend Detected\n"); -#endif - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.erlysuspend = 1; - dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, - gintsts.d32); - return 1; -} - -/** - * This function configures EPO to receive SETUP packets. - * - * @todo NGS: Update the comments from the HW FS. - * - * -# Program the following fields in the endpoint specific registers - * for Control OUT EP 0, in order to receive a setup packet - * - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back - * setup packets) - * - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back - * to back setup packets) - * - In DMA mode, DOEPDMA0 Register with a memory address to - * store any setup packets received - * - * @param core_if Programming view of DWC_otg controller. - * @param pcd Programming view of the PCD. - */ -static inline void ep0_out_start(dwc_otg_core_if_t *core_if, dwc_otg_pcd_t *pcd) -{ - dwc_otg_dev_if_t *dev_if = core_if->dev_if; - deptsiz0_data_t doeptsize0 = { .d32 = 0}; - dwc_otg_dma_desc_t* dma_desc; - depctl_data_t doepctl = { .d32 = 0 }; - -#ifdef VERBOSE - DWC_DEBUGPL(DBG_PCDV,"%s() doepctl0=%0x\n", __func__, - dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl)); -#endif - - doeptsize0.b.supcnt = 3; - doeptsize0.b.pktcnt = 1; - doeptsize0.b.xfersize = 8*3; - - - if (core_if->dma_enable) { - if (!core_if->dma_desc_enable) { - /** put here as for Hermes mode deptisz register should not be written */ - dwc_write_reg32(&dev_if->out_ep_regs[0]->doeptsiz, - doeptsize0.d32); - - /** @todo dma needs to handle multiple setup packets (up to 3) */ - dwc_write_reg32(&dev_if->out_ep_regs[0]->doepdma, - pcd->setup_pkt_dma_handle); - } else { - dev_if->setup_desc_index = (dev_if->setup_desc_index + 1) & 1; - dma_desc = dev_if->setup_desc_addr[dev_if->setup_desc_index]; - - /** DMA Descriptor Setup */ - dma_desc->status.b.bs = BS_HOST_BUSY; - dma_desc->status.b.l = 1; - dma_desc->status.b.ioc = 1; - dma_desc->status.b.bytes = pcd->ep0.dwc_ep.maxpacket; - dma_desc->buf = pcd->setup_pkt_dma_handle; - dma_desc->status.b.bs = BS_HOST_READY; - - /** DOEPDMA0 Register write */ - dwc_write_reg32(&dev_if->out_ep_regs[0]->doepdma, dev_if->dma_setup_desc_addr[dev_if->setup_desc_index]); - } - - } else { - /** put here as for Hermes mode deptisz register should not be written */ - dwc_write_reg32(&dev_if->out_ep_regs[0]->doeptsiz, - doeptsize0.d32); - } - - /** DOEPCTL0 Register write */ - doepctl.b.epena = 1; - doepctl.b.cnak = 1; - dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32); - -#ifdef VERBOSE - DWC_DEBUGPL(DBG_PCDV,"doepctl0=%0x\n", - dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl)); - DWC_DEBUGPL(DBG_PCDV,"diepctl0=%0x\n", - dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl)); -#endif -} - - -/** - * This interrupt occurs when a USB Reset is detected. When the USB - * Reset Interrupt occurs the device state is set to DEFAULT and the - * EP0 state is set to IDLE. - * -# Set the NAK bit for all OUT endpoints (DOEPCTLn.SNAK = 1) - * -# Unmask the following interrupt bits - * - DAINTMSK.INEP0 = 1 (Control 0 IN endpoint) - * - DAINTMSK.OUTEP0 = 1 (Control 0 OUT endpoint) - * - DOEPMSK.SETUP = 1 - * - DOEPMSK.XferCompl = 1 - * - DIEPMSK.XferCompl = 1 - * - DIEPMSK.TimeOut = 1 - * -# Program the following fields in the endpoint specific registers - * for Control OUT EP 0, in order to receive a setup packet - * - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back - * setup packets) - * - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back - * to back setup packets) - * - In DMA mode, DOEPDMA0 Register with a memory address to - * store any setup packets received - * At this point, all the required initialization, except for enabling - * the control 0 OUT endpoint is done, for receiving SETUP packets. - */ -int32_t dwc_otg_pcd_handle_usb_reset_intr(dwc_otg_pcd_t * pcd) -{ - dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); - dwc_otg_dev_if_t *dev_if = core_if->dev_if; - depctl_data_t doepctl = { .d32 = 0}; - - daint_data_t daintmsk = { .d32 = 0}; - doepmsk_data_t doepmsk = { .d32 = 0}; - diepmsk_data_t diepmsk = { .d32 = 0}; - - dcfg_data_t dcfg = { .d32=0 }; - grstctl_t resetctl = { .d32=0 }; - dctl_data_t dctl = {.d32=0}; - int i = 0; - gintsts_data_t gintsts; - - DWC_PRINT("USB RESET\n"); -#ifdef DWC_EN_ISOC - for(i = 1;i < 16; ++i) - { - dwc_otg_pcd_ep_t *ep; - dwc_ep_t *dwc_ep; - ep = get_in_ep(pcd,i); - if(ep != 0){ - dwc_ep = &ep->dwc_ep; - dwc_ep->next_frame = 0xffffffff; - } - } -#endif /* DWC_EN_ISOC */ - - /* reset the HNP settings */ - dwc_otg_pcd_update_otg(pcd, 1); - - /* Clear the Remote Wakeup Signalling */ - dctl.b.rmtwkupsig = 1; - dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl, - dctl.d32, 0); - - /* Set NAK for all OUT EPs */ - doepctl.b.snak = 1; - for (i=0; i <= dev_if->num_out_eps; i++) - { - dwc_write_reg32(&dev_if->out_ep_regs[i]->doepctl, - doepctl.d32); - } - - /* Flush the NP Tx FIFO */ - dwc_otg_flush_tx_fifo(core_if, 0x10); - /* Flush the Learning Queue */ - resetctl.b.intknqflsh = 1; - dwc_write_reg32(&core_if->core_global_regs->grstctl, resetctl.d32); - - if(core_if->multiproc_int_enable) { - daintmsk.b.inep0 = 1; - daintmsk.b.outep0 = 1; - dwc_write_reg32(&dev_if->dev_global_regs->deachintmsk, daintmsk.d32); - - doepmsk.b.setup = 1; - doepmsk.b.xfercompl = 1; - doepmsk.b.ahberr = 1; - doepmsk.b.epdisabled = 1; - - if(core_if->dma_desc_enable) { - doepmsk.b.stsphsercvd = 1; - doepmsk.b.bna = 1; - } -/* - doepmsk.b.babble = 1; - doepmsk.b.nyet = 1; - - if(core_if->dma_enable) { - doepmsk.b.nak = 1; - } -*/ - dwc_write_reg32(&dev_if->dev_global_regs->doepeachintmsk[0], doepmsk.d32); - - diepmsk.b.xfercompl = 1; - diepmsk.b.timeout = 1; - diepmsk.b.epdisabled = 1; - diepmsk.b.ahberr = 1; - diepmsk.b.intknepmis = 1; - - if(core_if->dma_desc_enable) { - diepmsk.b.bna = 1; - } -/* - if(core_if->dma_enable) { - diepmsk.b.nak = 1; - } -*/ - dwc_write_reg32(&dev_if->dev_global_regs->diepeachintmsk[0], diepmsk.d32); - } else{ - daintmsk.b.inep0 = 1; - daintmsk.b.outep0 = 1; - dwc_write_reg32(&dev_if->dev_global_regs->daintmsk, daintmsk.d32); - - doepmsk.b.setup = 1; - doepmsk.b.xfercompl = 1; - doepmsk.b.ahberr = 1; - doepmsk.b.epdisabled = 1; - - if(core_if->dma_desc_enable) { - doepmsk.b.stsphsercvd = 1; - doepmsk.b.bna = 1; - } -/* - doepmsk.b.babble = 1; - doepmsk.b.nyet = 1; - doepmsk.b.nak = 1; -*/ - dwc_write_reg32(&dev_if->dev_global_regs->doepmsk, doepmsk.d32); - - diepmsk.b.xfercompl = 1; - diepmsk.b.timeout = 1; - diepmsk.b.epdisabled = 1; - diepmsk.b.ahberr = 1; - diepmsk.b.intknepmis = 1; - - if(core_if->dma_desc_enable) { - diepmsk.b.bna = 1; - } - -// diepmsk.b.nak = 1; - - dwc_write_reg32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32); - } - - /* Reset Device Address */ - dcfg.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dcfg); - dcfg.b.devaddr = 0; - dwc_write_reg32(&dev_if->dev_global_regs->dcfg, dcfg.d32); - - /* setup EP0 to receive SETUP packets */ - ep0_out_start(core_if, pcd); - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.usbreset = 1; - dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32); - - return 1; -} - -/** - * Get the device speed from the device status register and convert it - * to USB speed constant. - * - * @param core_if Programming view of DWC_otg controller. - */ -static int get_device_speed(dwc_otg_core_if_t *core_if) -{ - dsts_data_t dsts; - enum usb_device_speed speed = USB_SPEED_UNKNOWN; - dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); - - switch (dsts.b.enumspd) { - case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: - speed = USB_SPEED_HIGH; - break; - case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: - case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ: - speed = USB_SPEED_FULL; - break; - - case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ: - speed = USB_SPEED_LOW; - break; - } - - return speed; -} - -/** - * Read the device status register and set the device speed in the - * data structure. - * Set up EP0 to receive SETUP packets by calling dwc_ep0_activate. - */ -int32_t dwc_otg_pcd_handle_enum_done_intr(dwc_otg_pcd_t *pcd) -{ - dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; - gintsts_data_t gintsts; - gusbcfg_data_t gusbcfg; - dwc_otg_core_global_regs_t *global_regs = - GET_CORE_IF(pcd)->core_global_regs; - uint8_t utmi16b, utmi8b; - DWC_DEBUGPL(DBG_PCD, "SPEED ENUM\n"); - - if (GET_CORE_IF(pcd)->snpsid >= 0x4F54260A) { - utmi16b = 6; - utmi8b = 9; - } else { - utmi16b = 4; - utmi8b = 8; - } - dwc_otg_ep0_activate(GET_CORE_IF(pcd), &ep0->dwc_ep); - -#ifdef DEBUG_EP0 - print_ep0_state(pcd); -#endif - - if (pcd->ep0state == EP0_DISCONNECT) { - pcd->ep0state = EP0_IDLE; - } - else if (pcd->ep0state == EP0_STALL) { - pcd->ep0state = EP0_IDLE; - } - - pcd->ep0state = EP0_IDLE; - - ep0->stopped = 0; - - pcd->gadget.speed = get_device_speed(GET_CORE_IF(pcd)); - - /* Set USB turnaround time based on device speed and PHY interface. */ - gusbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); - if (pcd->gadget.speed == USB_SPEED_HIGH) { - if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == DWC_HWCFG2_HS_PHY_TYPE_ULPI) { - /* ULPI interface */ - gusbcfg.b.usbtrdtim = 9; - } - if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == DWC_HWCFG2_HS_PHY_TYPE_UTMI) { - /* UTMI+ interface */ - if (GET_CORE_IF(pcd)->hwcfg4.b.utmi_phy_data_width == 0) { - gusbcfg.b.usbtrdtim = utmi8b; - } - else if (GET_CORE_IF(pcd)->hwcfg4.b.utmi_phy_data_width == 1) { - gusbcfg.b.usbtrdtim = utmi16b; - } - else if (GET_CORE_IF(pcd)->core_params->phy_utmi_width == 8) { - gusbcfg.b.usbtrdtim = utmi8b; - } - else { - gusbcfg.b.usbtrdtim = utmi16b; - } - } - if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI) { - /* UTMI+ OR ULPI interface */ - if (gusbcfg.b.ulpi_utmi_sel == 1) { - /* ULPI interface */ - gusbcfg.b.usbtrdtim = 9; - } - else { - /* UTMI+ interface */ - if (GET_CORE_IF(pcd)->core_params->phy_utmi_width == 16) { - gusbcfg.b.usbtrdtim = utmi16b; - } - else { - gusbcfg.b.usbtrdtim = utmi8b; - } - } - } - } - else { - /* Full or low speed */ - gusbcfg.b.usbtrdtim = 9; - } - dwc_write_reg32(&global_regs->gusbcfg, gusbcfg.d32); - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.enumdone = 1; - dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, - gintsts.d32); - return 1; -} - -/** - * This interrupt indicates that the ISO OUT Packet was dropped due to - * Rx FIFO full or Rx Status Queue Full. If this interrupt occurs - * read all the data from the Rx FIFO. - */ -int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(dwc_otg_pcd_t *pcd) -{ - gintmsk_data_t intr_mask = { .d32 = 0}; - gintsts_data_t gintsts; - - DWC_PRINT("INTERRUPT Handler not implemented for %s\n", - "ISOC Out Dropped"); - - intr_mask.b.isooutdrop = 1; - dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, - intr_mask.d32, 0); - - /* Clear interrupt */ - - gintsts.d32 = 0; - gintsts.b.isooutdrop = 1; - dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, - gintsts.d32); - - return 1; -} - -/** - * This interrupt indicates the end of the portion of the micro-frame - * for periodic transactions. If there is a periodic transaction for - * the next frame, load the packets into the EP periodic Tx FIFO. - */ -int32_t dwc_otg_pcd_handle_end_periodic_frame_intr(dwc_otg_pcd_t *pcd) -{ - gintmsk_data_t intr_mask = { .d32 = 0}; - gintsts_data_t gintsts; - DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "EOP"); - - intr_mask.b.eopframe = 1; - dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, - intr_mask.d32, 0); - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.eopframe = 1; - dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, gintsts.d32); - - return 1; -} - -/** - * This interrupt indicates that EP of the packet on the top of the - * non-periodic Tx FIFO does not match EP of the IN Token received. - * - * The "Device IN Token Queue" Registers are read to determine the - * order the IN Tokens have been received. The non-periodic Tx FIFO - * is flushed, so it can be reloaded in the order seen in the IN Token - * Queue. - */ -int32_t dwc_otg_pcd_handle_ep_mismatch_intr(dwc_otg_core_if_t *core_if) -{ - gintsts_data_t gintsts; - DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if); - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.epmismatch = 1; - dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32); - - return 1; -} - -/** - * This funcion stalls EP0. - */ -static inline void ep0_do_stall(dwc_otg_pcd_t *pcd, const int err_val) -{ - dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; - struct usb_ctrlrequest *ctrl = &pcd->setup_pkt->req; - DWC_WARN("req %02x.%02x protocol STALL; err %d\n", - ctrl->bRequestType, ctrl->bRequest, err_val); - - ep0->dwc_ep.is_in = 1; - dwc_otg_ep_set_stall(pcd->otg_dev->core_if, &ep0->dwc_ep); - pcd->ep0.stopped = 1; - pcd->ep0state = EP0_IDLE; - ep0_out_start(GET_CORE_IF(pcd), pcd); -} - -/** - * This functions delegates the setup command to the gadget driver. - */ -static inline void do_gadget_setup(dwc_otg_pcd_t *pcd, - struct usb_ctrlrequest * ctrl) -{ - int ret = 0; - if (pcd->driver && pcd->driver->setup) { - SPIN_UNLOCK(&pcd->lock); - ret = pcd->driver->setup(&pcd->gadget, ctrl); - SPIN_LOCK(&pcd->lock); - if (ret < 0) { - ep0_do_stall(pcd, ret); - } - - /** @todo This is a g_file_storage gadget driver specific - * workaround: a DELAYED_STATUS result from the fsg_setup - * routine will result in the gadget queueing a EP0 IN status - * phase for a two-stage control transfer. Exactly the same as - * a SET_CONFIGURATION/SET_INTERFACE except that this is a class - * specific request. Need a generic way to know when the gadget - * driver will queue the status phase. Can we assume when we - * call the gadget driver setup() function that it will always - * queue and require the following flag? Need to look into - * this. - */ - - if (ret == 256 + 999) { - pcd->request_config = 1; - } - } -} - -/** - * This function starts the Zero-Length Packet for the IN status phase - * of a 2 stage control transfer. - */ -static inline void do_setup_in_status_phase(dwc_otg_pcd_t *pcd) -{ - dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; - if (pcd->ep0state == EP0_STALL) { - return; - } - - pcd->ep0state = EP0_IN_STATUS_PHASE; - - /* Prepare for more SETUP Packets */ - DWC_DEBUGPL(DBG_PCD, "EP0 IN ZLP\n"); - ep0->dwc_ep.xfer_len = 0; - ep0->dwc_ep.xfer_count = 0; - ep0->dwc_ep.is_in = 1; - ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle; - dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep); - - /* Prepare for more SETUP Packets */ -// if(GET_CORE_IF(pcd)->dma_enable == 0) ep0_out_start(GET_CORE_IF(pcd), pcd); -} - -/** - * This function starts the Zero-Length Packet for the OUT status phase - * of a 2 stage control transfer. - */ -static inline void do_setup_out_status_phase(dwc_otg_pcd_t *pcd) -{ - dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; - if (pcd->ep0state == EP0_STALL) { - DWC_DEBUGPL(DBG_PCD, "EP0 STALLED\n"); - return; - } - pcd->ep0state = EP0_OUT_STATUS_PHASE; - - DWC_DEBUGPL(DBG_PCD, "EP0 OUT ZLP\n"); - ep0->dwc_ep.xfer_len = 0; - ep0->dwc_ep.xfer_count = 0; - ep0->dwc_ep.is_in = 0; - ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle; - dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep); - - /* Prepare for more SETUP Packets */ - if(GET_CORE_IF(pcd)->dma_enable == 0) { - ep0_out_start(GET_CORE_IF(pcd), pcd); - } -} - -/** - * Clear the EP halt (STALL) and if pending requests start the - * transfer. - */ -static inline void pcd_clear_halt(dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep) -{ - if(ep->dwc_ep.stall_clear_flag == 0) - dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep); - - /* Reactive the EP */ - dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep); - if (ep->stopped) { - ep->stopped = 0; - /* If there is a request in the EP queue start it */ - - /** @todo FIXME: this causes an EP mismatch in DMA mode. - * epmismatch not yet implemented. */ - - /* - * Above fixme is solved by implmenting a tasklet to call the - * start_next_request(), outside of interrupt context at some - * time after the current time, after a clear-halt setup packet. - * Still need to implement ep mismatch in the future if a gadget - * ever uses more than one endpoint at once - */ - ep->queue_sof = 1; - tasklet_schedule (pcd->start_xfer_tasklet); - } - /* Start Control Status Phase */ - do_setup_in_status_phase(pcd); -} - -/** - * This function is called when the SET_FEATURE TEST_MODE Setup packet - * is sent from the host. The Device Control register is written with - * the Test Mode bits set to the specified Test Mode. This is done as - * a tasklet so that the "Status" phase of the control transfer - * completes before transmitting the TEST packets. - * - * @todo This has not been tested since the tasklet struct was put - * into the PCD struct! - * - */ -static void do_test_mode(unsigned long data) -{ - dctl_data_t dctl; - dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)data; - dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); - int test_mode = pcd->test_mode; - - -// DWC_WARN("%s() has not been tested since being rewritten!\n", __func__); - - dctl.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dctl); - switch (test_mode) { - case 1: // TEST_J - dctl.b.tstctl = 1; - break; - - case 2: // TEST_K - dctl.b.tstctl = 2; - break; - - case 3: // TEST_SE0_NAK - dctl.b.tstctl = 3; - break; - - case 4: // TEST_PACKET - dctl.b.tstctl = 4; - break; - - case 5: // TEST_FORCE_ENABLE - dctl.b.tstctl = 5; - break; - } - dwc_write_reg32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32); -} - -/** - * This function process the GET_STATUS Setup Commands. - */ -static inline void do_get_status(dwc_otg_pcd_t *pcd) -{ - struct usb_ctrlrequest ctrl = pcd->setup_pkt->req; - dwc_otg_pcd_ep_t *ep; - dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; - uint16_t *status = pcd->status_buf; - -#ifdef DEBUG_EP0 - DWC_DEBUGPL(DBG_PCD, - "GET_STATUS %02x.%02x v%04x i%04x l%04x\n", - ctrl.bRequestType, ctrl.bRequest, - ctrl.wValue, ctrl.wIndex, ctrl.wLength); -#endif - - switch (ctrl.bRequestType & USB_RECIP_MASK) { - case USB_RECIP_DEVICE: - *status = 0x1; /* Self powered */ - *status |= pcd->remote_wakeup_enable << 1; - break; - - case USB_RECIP_INTERFACE: - *status = 0; - break; - - case USB_RECIP_ENDPOINT: - ep = get_ep_by_addr(pcd, ctrl.wIndex); - if (ep == 0 || ctrl.wLength > 2) { - ep0_do_stall(pcd, -EOPNOTSUPP); - return; - } - /** @todo check for EP stall */ - *status = ep->stopped; - break; - } - pcd->ep0_pending = 1; - ep0->dwc_ep.start_xfer_buff = (uint8_t *)status; - ep0->dwc_ep.xfer_buff = (uint8_t *)status; - ep0->dwc_ep.dma_addr = pcd->status_buf_dma_handle; - ep0->dwc_ep.xfer_len = 2; - ep0->dwc_ep.xfer_count = 0; - ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len; - dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep); -} -/** - * This function process the SET_FEATURE Setup Commands. - */ -static inline void do_set_feature(dwc_otg_pcd_t *pcd) -{ - dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); - dwc_otg_core_global_regs_t *global_regs = - core_if->core_global_regs; - struct usb_ctrlrequest ctrl = pcd->setup_pkt->req; - dwc_otg_pcd_ep_t *ep = 0; - int32_t otg_cap_param = core_if->core_params->otg_cap; - gotgctl_data_t gotgctl = { .d32 = 0 }; - - DWC_DEBUGPL(DBG_PCD, "SET_FEATURE:%02x.%02x v%04x i%04x l%04x\n", - ctrl.bRequestType, ctrl.bRequest, - ctrl.wValue, ctrl.wIndex, ctrl.wLength); - DWC_DEBUGPL(DBG_PCD,"otg_cap=%d\n", otg_cap_param); - - - switch (ctrl.bRequestType & USB_RECIP_MASK) { - case USB_RECIP_DEVICE: - switch (ctrl.wValue) { - case USB_DEVICE_REMOTE_WAKEUP: - pcd->remote_wakeup_enable = 1; - break; - - case USB_DEVICE_TEST_MODE: - /* Setup the Test Mode tasklet to do the Test - * Packet generation after the SETUP Status - * phase has completed. */ - - /** @todo This has not been tested since the - * tasklet struct was put into the PCD - * struct! */ - pcd->test_mode_tasklet.next = 0; - pcd->test_mode_tasklet.state = 0; - atomic_set(&pcd->test_mode_tasklet.count, 0); - pcd->test_mode_tasklet.func = do_test_mode; - pcd->test_mode_tasklet.data = (unsigned long)pcd; - pcd->test_mode = ctrl.wIndex >> 8; - tasklet_schedule(&pcd->test_mode_tasklet); - break; - - case USB_DEVICE_B_HNP_ENABLE: - DWC_DEBUGPL(DBG_PCDV, "SET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n"); - - /* dev may initiate HNP */ - if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) { - pcd->b_hnp_enable = 1; - dwc_otg_pcd_update_otg(pcd, 0); - DWC_DEBUGPL(DBG_PCD, "Request B HNP\n"); - /**@todo Is the gotgctl.devhnpen cleared - * by a USB Reset? */ - gotgctl.b.devhnpen = 1; - gotgctl.b.hnpreq = 1; - dwc_write_reg32(&global_regs->gotgctl, gotgctl.d32); - } - else { - ep0_do_stall(pcd, -EOPNOTSUPP); - } - break; - - case USB_DEVICE_A_HNP_SUPPORT: - /* RH port supports HNP */ - DWC_DEBUGPL(DBG_PCDV, "SET_FEATURE: USB_DEVICE_A_HNP_SUPPORT\n"); - if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) { - pcd->a_hnp_support = 1; - dwc_otg_pcd_update_otg(pcd, 0); - } - else { - ep0_do_stall(pcd, -EOPNOTSUPP); - } - break; - - case USB_DEVICE_A_ALT_HNP_SUPPORT: - /* other RH port does */ - DWC_DEBUGPL(DBG_PCDV, "SET_FEATURE: USB_DEVICE_A_ALT_HNP_SUPPORT\n"); - if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) { - pcd->a_alt_hnp_support = 1; - dwc_otg_pcd_update_otg(pcd, 0); - } - else { - ep0_do_stall(pcd, -EOPNOTSUPP); - } - break; - } - do_setup_in_status_phase(pcd); - break; - - case USB_RECIP_INTERFACE: - do_gadget_setup(pcd, &ctrl); - break; - - case USB_RECIP_ENDPOINT: - if (ctrl.wValue == USB_ENDPOINT_HALT) { - ep = get_ep_by_addr(pcd, ctrl.wIndex); - if (ep == 0) { - ep0_do_stall(pcd, -EOPNOTSUPP); - return; - } - ep->stopped = 1; - dwc_otg_ep_set_stall(core_if, &ep->dwc_ep); - } - do_setup_in_status_phase(pcd); - break; - } -} - -/** - * This function process the CLEAR_FEATURE Setup Commands. - */ -static inline void do_clear_feature(dwc_otg_pcd_t *pcd) -{ - struct usb_ctrlrequest ctrl = pcd->setup_pkt->req; - dwc_otg_pcd_ep_t *ep = 0; - - DWC_DEBUGPL(DBG_PCD, - "CLEAR_FEATURE:%02x.%02x v%04x i%04x l%04x\n", - ctrl.bRequestType, ctrl.bRequest, - ctrl.wValue, ctrl.wIndex, ctrl.wLength); - - switch (ctrl.bRequestType & USB_RECIP_MASK) { - case USB_RECIP_DEVICE: - switch (ctrl.wValue) { - case USB_DEVICE_REMOTE_WAKEUP: - pcd->remote_wakeup_enable = 0; - break; - - case USB_DEVICE_TEST_MODE: - /** @todo Add CLEAR_FEATURE for TEST modes. */ - break; - } - do_setup_in_status_phase(pcd); - break; - - case USB_RECIP_ENDPOINT: - ep = get_ep_by_addr(pcd, ctrl.wIndex); - if (ep == 0) { - ep0_do_stall(pcd, -EOPNOTSUPP); - return; - } - - pcd_clear_halt(pcd, ep); - - break; - } -} - -/** - * This function process the SET_ADDRESS Setup Commands. - */ -static inline void do_set_address(dwc_otg_pcd_t *pcd) -{ - dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if; - struct usb_ctrlrequest ctrl = pcd->setup_pkt->req; - - if (ctrl.bRequestType == USB_RECIP_DEVICE) { - dcfg_data_t dcfg = {.d32=0}; - -#ifdef DEBUG_EP0 -// DWC_DEBUGPL(DBG_PCDV, "SET_ADDRESS:%d\n", ctrl.wValue); -#endif - dcfg.b.devaddr = ctrl.wValue; - dwc_modify_reg32(&dev_if->dev_global_regs->dcfg, 0, dcfg.d32); - do_setup_in_status_phase(pcd); - } -} - -/** - * This function processes SETUP commands. In Linux, the USB Command - * processing is done in two places - the first being the PCD and the - * second in the Gadget Driver (for example, the File-Backed Storage - * Gadget Driver). - * - *
Parameter NameMeaning
otg_capSpecifies the OTG capabilities. The driver will automatically detect the - value for this parameter if none is specified. - - 0: HNP and SRP capable (default, if available) - - 1: SRP Only capable - - 2: No HNP/SRP capable -
dma_enableSpecifies whether to use slave or DMA mode for accessing the data FIFOs. - The driver will automatically detect the value for this parameter if none is - specified. - - 0: Slave - - 1: DMA (default, if available) -
dma_burst_sizeThe DMA Burst size (applicable only for External DMA Mode). - - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32) -
speedSpecifies the maximum speed of operation in host and device mode. The - actual speed depends on the speed of the attached device and the value of - phy_type. - - 0: High Speed (default) - - 1: Full Speed -
host_support_fs_ls_low_powerSpecifies whether low power mode is supported when attached to a Full - Speed or Low Speed device in host mode. - - 0: Don't support low power mode (default) - - 1: Support low power mode -
host_ls_low_power_phy_clkSpecifies the PHY clock rate in low power mode when connected to a Low - Speed device in host mode. This parameter is applicable only if - HOST_SUPPORT_FS_LS_LOW_POWER is enabled. - - 0: 48 MHz (default) - - 1: 6 MHz -
enable_dynamic_fifo Specifies whether FIFOs may be resized by the driver software. - - 0: Use cC FIFO size parameters - - 1: Allow dynamic FIFO sizing (default) -
data_fifo_sizeTotal number of 4-byte words in the data FIFO memory. This memory - includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs. - - Values: 32 to 32768 (default 8192) - - Note: The total FIFO memory depth in the FPGA configuration is 8192. -
dev_rx_fifo_sizeNumber of 4-byte words in the Rx FIFO in device mode when dynamic - FIFO sizing is enabled. - - Values: 16 to 32768 (default 1064) -
dev_nperio_tx_fifo_sizeNumber of 4-byte words in the non-periodic Tx FIFO in device mode when - dynamic FIFO sizing is enabled. - - Values: 16 to 32768 (default 1024) -
dev_perio_tx_fifo_size_n (n = 1 to 15)Number of 4-byte words in each of the periodic Tx FIFOs in device mode - when dynamic FIFO sizing is enabled. - - Values: 4 to 768 (default 256) -
host_rx_fifo_sizeNumber of 4-byte words in the Rx FIFO in host mode when dynamic FIFO - sizing is enabled. - - Values: 16 to 32768 (default 1024) -
host_nperio_tx_fifo_sizeNumber of 4-byte words in the non-periodic Tx FIFO in host mode when - dynamic FIFO sizing is enabled in the core. - - Values: 16 to 32768 (default 1024) -
host_perio_tx_fifo_sizeNumber of 4-byte words in the host periodic Tx FIFO when dynamic FIFO - sizing is enabled. - - Values: 16 to 32768 (default 1024) -
max_transfer_sizeThe maximum transfer size supported in bytes. - - Values: 2047 to 65,535 (default 65,535) -
max_packet_countThe maximum number of packets in a transfer. - - Values: 15 to 511 (default 511) -
host_channelsThe number of host channel registers to use. - - Values: 1 to 16 (default 12) - - Note: The FPGA configuration supports a maximum of 12 host channels. -
dev_endpointsThe number of endpoints in addition to EP0 available for device mode - operations. - - Values: 1 to 15 (default 6 IN and OUT) - - Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in - addition to EP0. -
phy_typeSpecifies the type of PHY interface to use. By default, the driver will - automatically detect the phy_type. - - 0: Full Speed - - 1: UTMI+ (default, if available) - - 2: ULPI -
phy_utmi_widthSpecifies the UTMI+ Data Width. This parameter is applicable for a - phy_type of UTMI+. Also, this parameter is applicable only if the - OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the - core has been configured to work at either data path width. - - Values: 8 or 16 bits (default 16) -
phy_ulpi_ddrSpecifies whether the ULPI operates at double or single data rate. This - parameter is only applicable if phy_type is ULPI. - - 0: single data rate ULPI interface with 8 bit wide data bus (default) - - 1: double data rate ULPI interface with 4 bit wide data bus -
i2c_enableSpecifies whether to use the I2C interface for full speed PHY. This - parameter is only applicable if PHY_TYPE is FS. - - 0: Disabled (default) - - 1: Enabled -
otg_en_multiple_tx_fifoSpecifies whether dedicatedto tx fifos are enabled for non periodic IN EPs. - The driver will automatically detect the value for this parameter if none is - specified. - - 0: Disabled - - 1: Enabled (default, if available) -
dev_tx_fifo_size_n (n = 1 to 15)Number of 4-byte words in each of the Tx FIFOs in device mode - when dynamic FIFO sizing is enabled. - - Values: 4 to 768 (default 256) -
- * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Command Driver Description
GET_STATUS PCD Command is processed as - * defined in chapter 9 of the USB 2.0 Specification chapter 9 - *
CLEAR_FEATURE PCD The Device and Endpoint - * requests are the ENDPOINT_HALT feature is procesed, all others the - * interface requests are ignored.
SET_FEATURE PCD The Device and Endpoint - * requests are processed by the PCD. Interface requests are passed - * to the Gadget Driver.
SET_ADDRESS PCD Program the DCFG reg, - * with device address received
GET_DESCRIPTOR Gadget Driver Return the - * requested descriptor
SET_DESCRIPTOR Gadget Driver Optional - - * not implemented by any of the existing Gadget Drivers.
SET_CONFIGURATION Gadget Driver Disable - * all EPs and enable EPs for new configuration.
GET_CONFIGURATION Gadget Driver Return - * the current configuration
SET_INTERFACE Gadget Driver Disable all - * EPs and enable EPs for new configuration.
GET_INTERFACE Gadget Driver Return the - * current interface.
SYNC_FRAME PCD Display debug - * message.
- * - * When the SETUP Phase Done interrupt occurs, the PCD SETUP commands are - * processed by pcd_setup. Calling the Function Driver's setup function from - * pcd_setup processes the gadget SETUP commands. - */ -static inline void pcd_setup(dwc_otg_pcd_t *pcd) -{ - dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); - dwc_otg_dev_if_t *dev_if = core_if->dev_if; - struct usb_ctrlrequest ctrl = pcd->setup_pkt->req; - dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; - - deptsiz0_data_t doeptsize0 = { .d32 = 0}; - -#ifdef DEBUG_EP0 - DWC_DEBUGPL(DBG_PCD, "SETUP %02x.%02x v%04x i%04x l%04x\n", - ctrl.bRequestType, ctrl.bRequest, - ctrl.wValue, ctrl.wIndex, ctrl.wLength); -#endif - - doeptsize0.d32 = dwc_read_reg32(&dev_if->out_ep_regs[0]->doeptsiz); - - /** @todo handle > 1 setup packet , assert error for now */ - - if (core_if->dma_enable && core_if->dma_desc_enable == 0 && (doeptsize0.b.supcnt < 2)) { - DWC_ERROR ("\n\n----------- CANNOT handle > 1 setup packet in DMA mode\n\n"); - } - - /* Clean up the request queue */ - dwc_otg_request_nuke(ep0); - ep0->stopped = 0; - - if (ctrl.bRequestType & USB_DIR_IN) { - ep0->dwc_ep.is_in = 1; - pcd->ep0state = EP0_IN_DATA_PHASE; - } - else { - ep0->dwc_ep.is_in = 0; - pcd->ep0state = EP0_OUT_DATA_PHASE; - } - - if(ctrl.wLength == 0) { - ep0->dwc_ep.is_in = 1; - pcd->ep0state = EP0_IN_STATUS_PHASE; - } - - if ((ctrl.bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD) { - /* handle non-standard (class/vendor) requests in the gadget driver */ - do_gadget_setup(pcd, &ctrl); - return; - } - - /** @todo NGS: Handle bad setup packet? */ - -/////////////////////////////////////////// -//// --- Standard Request handling --- //// - - switch (ctrl.bRequest) { - case USB_REQ_GET_STATUS: - do_get_status(pcd); - break; - - case USB_REQ_CLEAR_FEATURE: - do_clear_feature(pcd); - break; - - case USB_REQ_SET_FEATURE: - do_set_feature(pcd); - break; - - case USB_REQ_SET_ADDRESS: - do_set_address(pcd); - break; - - case USB_REQ_SET_INTERFACE: - case USB_REQ_SET_CONFIGURATION: -// _pcd->request_config = 1; /* Configuration changed */ - do_gadget_setup(pcd, &ctrl); - break; - - case USB_REQ_SYNCH_FRAME: - do_gadget_setup(pcd, &ctrl); - break; - - default: - /* Call the Gadget Driver's setup functions */ - do_gadget_setup(pcd, &ctrl); - break; - } -} - -/** - * This function completes the ep0 control transfer. - */ -static int32_t ep0_complete_request(dwc_otg_pcd_ep_t *ep) -{ - dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd); - dwc_otg_dev_if_t *dev_if = core_if->dev_if; - dwc_otg_dev_in_ep_regs_t *in_ep_regs = - dev_if->in_ep_regs[ep->dwc_ep.num]; -#ifdef DEBUG_EP0 - dwc_otg_dev_out_ep_regs_t *out_ep_regs = - dev_if->out_ep_regs[ep->dwc_ep.num]; -#endif - deptsiz0_data_t deptsiz; - desc_sts_data_t desc_sts; - dwc_otg_pcd_request_t *req; - int is_last = 0; - dwc_otg_pcd_t *pcd = ep->pcd; - - //DWC_DEBUGPL(DBG_PCDV, "%s() %s\n", __func__, _ep->ep.name); - - if (pcd->ep0_pending && list_empty(&ep->queue)) { - if (ep->dwc_ep.is_in) { -#ifdef DEBUG_EP0 - DWC_DEBUGPL(DBG_PCDV, "Do setup OUT status phase\n"); -#endif - do_setup_out_status_phase(pcd); - } - else { -#ifdef DEBUG_EP0 - DWC_DEBUGPL(DBG_PCDV, "Do setup IN status phase\n"); -#endif - do_setup_in_status_phase(pcd); - } - pcd->ep0_pending = 0; - return 1; - } - - if (list_empty(&ep->queue)) { - return 0; - } - req = list_entry(ep->queue.next, dwc_otg_pcd_request_t, queue); - - - if (pcd->ep0state == EP0_OUT_STATUS_PHASE || pcd->ep0state == EP0_IN_STATUS_PHASE) { - is_last = 1; - } - else if (ep->dwc_ep.is_in) { - deptsiz.d32 = dwc_read_reg32(&in_ep_regs->dieptsiz); - if(core_if->dma_desc_enable != 0) - desc_sts.d32 = readl(dev_if->in_desc_addr); -#ifdef DEBUG_EP0 - DWC_DEBUGPL(DBG_PCDV, "%s len=%d xfersize=%d pktcnt=%d\n", - ep->ep.name, ep->dwc_ep.xfer_len, - deptsiz.b.xfersize, deptsiz.b.pktcnt); -#endif - - if (((core_if->dma_desc_enable == 0) && (deptsiz.b.xfersize == 0)) || - ((core_if->dma_desc_enable != 0) && (desc_sts.b.bytes == 0))) { - req->req.actual = ep->dwc_ep.xfer_count; - /* Is a Zero Len Packet needed? */ - if (req->req.zero) { -#ifdef DEBUG_EP0 - DWC_DEBUGPL(DBG_PCD, "Setup Rx ZLP\n"); -#endif - req->req.zero = 0; - } - do_setup_out_status_phase(pcd); - } - } - else { - /* ep0-OUT */ -#ifdef DEBUG_EP0 - deptsiz.d32 = dwc_read_reg32(&out_ep_regs->doeptsiz); - DWC_DEBUGPL(DBG_PCDV, "%s len=%d xsize=%d pktcnt=%d\n", - ep->ep.name, ep->dwc_ep.xfer_len, - deptsiz.b.xfersize, - deptsiz.b.pktcnt); -#endif - req->req.actual = ep->dwc_ep.xfer_count; - /* Is a Zero Len Packet needed? */ - if (req->req.zero) { -#ifdef DEBUG_EP0 - DWC_DEBUGPL(DBG_PCDV, "Setup Tx ZLP\n"); -#endif - req->req.zero = 0; - } - if(core_if->dma_desc_enable == 0) - do_setup_in_status_phase(pcd); - } - - /* Complete the request */ - if (is_last) { - dwc_otg_request_done(ep, req, 0); - ep->dwc_ep.start_xfer_buff = 0; - ep->dwc_ep.xfer_buff = 0; - ep->dwc_ep.xfer_len = 0; - return 1; - } - return 0; -} - -/** - * This function completes the request for the EP. If there are - * additional requests for the EP in the queue they will be started. - */ -static void complete_ep(dwc_otg_pcd_ep_t *ep) -{ - dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd); - dwc_otg_dev_if_t *dev_if = core_if->dev_if; - dwc_otg_dev_in_ep_regs_t *in_ep_regs = - dev_if->in_ep_regs[ep->dwc_ep.num]; - deptsiz_data_t deptsiz; - desc_sts_data_t desc_sts; - dwc_otg_pcd_request_t *req = 0; - dwc_otg_dma_desc_t* dma_desc; - uint32_t byte_count = 0; - int is_last = 0; - int i; - - DWC_DEBUGPL(DBG_PCDV,"%s() %s-%s\n", __func__, ep->ep.name, - (ep->dwc_ep.is_in?"IN":"OUT")); - - /* Get any pending requests */ - if (!list_empty(&ep->queue)) { - req = list_entry(ep->queue.next, dwc_otg_pcd_request_t, - queue); - if (!req) { - printk("complete_ep 0x%p, req = NULL!\n", ep); - return; - } - } - else { - printk("complete_ep 0x%p, ep->queue empty!\n", ep); - return; - } - DWC_DEBUGPL(DBG_PCD, "Requests %d\n", ep->pcd->request_pending); - - if (ep->dwc_ep.is_in) { - deptsiz.d32 = dwc_read_reg32(&in_ep_regs->dieptsiz); - - if (core_if->dma_enable) { - if(core_if->dma_desc_enable == 0) { - if (deptsiz.b.xfersize == 0 && deptsiz.b.pktcnt == 0) { - byte_count = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count; - - ep->dwc_ep.xfer_buff += byte_count; - ep->dwc_ep.dma_addr += byte_count; - ep->dwc_ep.xfer_count += byte_count; - - DWC_DEBUGPL(DBG_PCDV, "%s len=%d xfersize=%d pktcnt=%d\n", - ep->ep.name, ep->dwc_ep.xfer_len, - deptsiz.b.xfersize, deptsiz.b.pktcnt); - - - if(ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) { - dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep); - } else if(ep->dwc_ep.sent_zlp) { - /* - * This fragment of code should initiate 0 - * length trasfer in case if it is queued - * a trasfer with size divisible to EPs max - * packet size and with usb_request zero field - * is set, which means that after data is transfered, - * it is also should be transfered - * a 0 length packet at the end. For Slave and - * Buffer DMA modes in this case SW has - * to initiate 2 transfers one with transfer size, - * and the second with 0 size. For Desriptor - * DMA mode SW is able to initiate a transfer, - * which will handle all the packets including - * the last 0 legth. - */ - ep->dwc_ep.sent_zlp = 0; - dwc_otg_ep_start_zl_transfer(core_if, &ep->dwc_ep); - } else { - is_last = 1; - } - } else { - DWC_WARN("Incomplete transfer (%s-%s [siz=%d pkt=%d])\n", - ep->ep.name, (ep->dwc_ep.is_in?"IN":"OUT"), - deptsiz.b.xfersize, deptsiz.b.pktcnt); - } - } else { - dma_desc = ep->dwc_ep.desc_addr; - byte_count = 0; - ep->dwc_ep.sent_zlp = 0; - - for(i = 0; i < ep->dwc_ep.desc_cnt; ++i) { - desc_sts.d32 = readl(dma_desc); - byte_count += desc_sts.b.bytes; - dma_desc++; - } - - if(byte_count == 0) { - ep->dwc_ep.xfer_count = ep->dwc_ep.total_len; - is_last = 1; - } else { - DWC_WARN("Incomplete transfer\n"); - } - } - } else { - if (deptsiz.b.xfersize == 0 && deptsiz.b.pktcnt == 0) { - /* Check if the whole transfer was completed, - * if no, setup transfer for next portion of data - */ - DWC_DEBUGPL(DBG_PCDV, "%s len=%d xfersize=%d pktcnt=%d\n", - ep->ep.name, ep->dwc_ep.xfer_len, - deptsiz.b.xfersize, deptsiz.b.pktcnt); - if(ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) { - dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep); - } else if(ep->dwc_ep.sent_zlp) { - /* - * This fragment of code should initiate 0 - * length trasfer in case if it is queued - * a trasfer with size divisible to EPs max - * packet size and with usb_request zero field - * is set, which means that after data is transfered, - * it is also should be transfered - * a 0 length packet at the end. For Slave and - * Buffer DMA modes in this case SW has - * to initiate 2 transfers one with transfer size, - * and the second with 0 size. For Desriptor - * DMA mode SW is able to initiate a transfer, - * which will handle all the packets including - * the last 0 legth. - */ - ep->dwc_ep.sent_zlp = 0; - dwc_otg_ep_start_zl_transfer(core_if, &ep->dwc_ep); - } else { - is_last = 1; - } - } - else { - DWC_WARN("Incomplete transfer (%s-%s [siz=%d pkt=%d])\n", - ep->ep.name, (ep->dwc_ep.is_in?"IN":"OUT"), - deptsiz.b.xfersize, deptsiz.b.pktcnt); - } - } - } else { - dwc_otg_dev_out_ep_regs_t *out_ep_regs = - dev_if->out_ep_regs[ep->dwc_ep.num]; - desc_sts.d32 = 0; - if(core_if->dma_enable) { - if(core_if->dma_desc_enable) { - dma_desc = ep->dwc_ep.desc_addr; - byte_count = 0; - ep->dwc_ep.sent_zlp = 0; - for(i = 0; i < ep->dwc_ep.desc_cnt; ++i) { - desc_sts.d32 = readl(dma_desc); - byte_count += desc_sts.b.bytes; - dma_desc++; - } - - ep->dwc_ep.xfer_count = ep->dwc_ep.total_len - - byte_count + ((4 - (ep->dwc_ep.total_len & 0x3)) & 0x3); - is_last = 1; - } else { - deptsiz.d32 = 0; - deptsiz.d32 = dwc_read_reg32(&out_ep_regs->doeptsiz); - - byte_count = (ep->dwc_ep.xfer_len - - ep->dwc_ep.xfer_count - deptsiz.b.xfersize); - ep->dwc_ep.xfer_buff += byte_count; - ep->dwc_ep.dma_addr += byte_count; - ep->dwc_ep.xfer_count += byte_count; - - /* Check if the whole transfer was completed, - * if no, setup transfer for next portion of data - */ - if(ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) { - dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep); - } - else if(ep->dwc_ep.sent_zlp) { - /* - * This fragment of code should initiate 0 - * length trasfer in case if it is queued - * a trasfer with size divisible to EPs max - * packet size and with usb_request zero field - * is set, which means that after data is transfered, - * it is also should be transfered - * a 0 length packet at the end. For Slave and - * Buffer DMA modes in this case SW has - * to initiate 2 transfers one with transfer size, - * and the second with 0 size. For Desriptor - * DMA mode SW is able to initiate a transfer, - * which will handle all the packets including - * the last 0 legth. - */ - ep->dwc_ep.sent_zlp = 0; - dwc_otg_ep_start_zl_transfer(core_if, &ep->dwc_ep); - } else { - is_last = 1; - } - } - } else { - /* Check if the whole transfer was completed, - * if no, setup transfer for next portion of data - */ - if(ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) { - dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep); - } - else if(ep->dwc_ep.sent_zlp) { - /* - * This fragment of code should initiate 0 - * length trasfer in case if it is queued - * a trasfer with size divisible to EPs max - * packet size and with usb_request zero field - * is set, which means that after data is transfered, - * it is also should be transfered - * a 0 length packet at the end. For Slave and - * Buffer DMA modes in this case SW has - * to initiate 2 transfers one with transfer size, - * and the second with 0 size. For Desriptor - * DMA mode SW is able to initiate a transfer, - * which will handle all the packets including - * the last 0 legth. - */ - ep->dwc_ep.sent_zlp = 0; - dwc_otg_ep_start_zl_transfer(core_if, &ep->dwc_ep); - } else { - is_last = 1; - } - } - -#ifdef DEBUG - - DWC_DEBUGPL(DBG_PCDV, "addr %p, %s len=%d cnt=%d xsize=%d pktcnt=%d\n", - &out_ep_regs->doeptsiz, ep->ep.name, ep->dwc_ep.xfer_len, - ep->dwc_ep.xfer_count, - deptsiz.b.xfersize, - deptsiz.b.pktcnt); -#endif - } - - /* Complete the request */ - if (is_last) { - req->req.actual = ep->dwc_ep.xfer_count; - - dwc_otg_request_done(ep, req, 0); - - ep->dwc_ep.start_xfer_buff = 0; - ep->dwc_ep.xfer_buff = 0; - ep->dwc_ep.xfer_len = 0; - - /* If there is a request in the queue start it.*/ - start_next_request(ep); - } -} - - -#ifdef DWC_EN_ISOC - -/** - * This function BNA interrupt for Isochronous EPs - * - */ -static void dwc_otg_pcd_handle_iso_bna(dwc_otg_pcd_ep_t *ep) -{ - dwc_ep_t *dwc_ep = &ep->dwc_ep; - volatile uint32_t *addr; - depctl_data_t depctl = {.d32 = 0}; - dwc_otg_pcd_t *pcd = ep->pcd; - dwc_otg_dma_desc_t *dma_desc; - int i; - - dma_desc = dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * (dwc_ep->proc_buf_num); - - if(dwc_ep->is_in) { - desc_sts_data_t sts = {.d32 = 0}; - for(i = 0;i < dwc_ep->desc_cnt; ++i, ++dma_desc) - { - sts.d32 = readl(&dma_desc->status); - sts.b_iso_in.bs = BS_HOST_READY; - writel(sts.d32,&dma_desc->status); - } - } - else { - desc_sts_data_t sts = {.d32 = 0}; - for(i = 0;i < dwc_ep->desc_cnt; ++i, ++dma_desc) - { - sts.d32 = readl(&dma_desc->status); - sts.b_iso_out.bs = BS_HOST_READY; - writel(sts.d32,&dma_desc->status); - } - } - - if(dwc_ep->is_in == 0){ - addr = &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->num]->doepctl; - } - else{ - addr = &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl; - } - depctl.b.epena = 1; - dwc_modify_reg32(addr,depctl.d32,depctl.d32); -} - -/** - * This function sets latest iso packet information(non-PTI mode) - * - * @param core_if Programming view of DWC_otg controller. - * @param ep The EP to start the transfer on. - * - */ -void set_current_pkt_info(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) -{ - deptsiz_data_t deptsiz = { .d32 = 0 }; - dma_addr_t dma_addr; - uint32_t offset; - - if(ep->proc_buf_num) - dma_addr = ep->dma_addr1; - else - dma_addr = ep->dma_addr0; - - - if(ep->is_in) { - deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz); - offset = ep->data_per_frame; - } else { - deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doeptsiz); - offset = ep->data_per_frame + (0x4 & (0x4 - (ep->data_per_frame & 0x3))); - } - - if(!deptsiz.b.xfersize) { - ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame; - ep->pkt_info[ep->cur_pkt].offset = ep->cur_pkt_dma_addr - dma_addr; - ep->pkt_info[ep->cur_pkt].status = 0; - } else { - ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame; - ep->pkt_info[ep->cur_pkt].offset = ep->cur_pkt_dma_addr - dma_addr; - ep->pkt_info[ep->cur_pkt].status = -ENODATA; - } - ep->cur_pkt_addr += offset; - ep->cur_pkt_dma_addr += offset; - ep->cur_pkt++; -} - -/** - * This function sets latest iso packet information(DDMA mode) - * - * @param core_if Programming view of DWC_otg controller. - * @param dwc_ep The EP to start the transfer on. - * - */ -static void set_ddma_iso_pkts_info(dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep) -{ - dwc_otg_dma_desc_t* dma_desc; - desc_sts_data_t sts = {.d32 = 0}; - iso_pkt_info_t *iso_packet; - uint32_t data_per_desc; - uint32_t offset; - int i, j; - - iso_packet = dwc_ep->pkt_info; - - /** Reinit closed DMA Descriptors*/ - /** ISO OUT EP */ - if(dwc_ep->is_in == 0) { - dma_desc = dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * dwc_ep->proc_buf_num; - offset = 0; - - for(i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; i+= dwc_ep->pkt_per_frm) - { - for(j = 0; j < dwc_ep->pkt_per_frm; ++j) - { - data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ? - dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket; - data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0; - - sts.d32 = readl(&dma_desc->status); - - /* Write status in iso_packet_decsriptor */ - iso_packet->status = sts.b_iso_out.rxsts + (sts.b_iso_out.bs^BS_DMA_DONE); - if(iso_packet->status) { - iso_packet->status = -ENODATA; - } - - /* Received data length */ - if(!sts.b_iso_out.rxbytes){ - iso_packet->length = data_per_desc - sts.b_iso_out.rxbytes; - } else { - iso_packet->length = data_per_desc - sts.b_iso_out.rxbytes + - (4 - dwc_ep->data_per_frame % 4); - } - - iso_packet->offset = offset; - - offset += data_per_desc; - dma_desc ++; - iso_packet ++; - } - } - - for(j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) - { - data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ? - dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket; - data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0; - - sts.d32 = readl(&dma_desc->status); - - /* Write status in iso_packet_decsriptor */ - iso_packet->status = sts.b_iso_out.rxsts + (sts.b_iso_out.bs^BS_DMA_DONE); - if(iso_packet->status) { - iso_packet->status = -ENODATA; - } - - /* Received data length */ - iso_packet->length = dwc_ep->data_per_frame - sts.b_iso_out.rxbytes; - - iso_packet->offset = offset; - - offset += data_per_desc; - iso_packet++; - dma_desc++; - } - - sts.d32 = readl(&dma_desc->status); - - /* Write status in iso_packet_decsriptor */ - iso_packet->status = sts.b_iso_out.rxsts + (sts.b_iso_out.bs^BS_DMA_DONE); - if(iso_packet->status) { - iso_packet->status = -ENODATA; - } - /* Received data length */ - if(!sts.b_iso_out.rxbytes){ - iso_packet->length = dwc_ep->data_per_frame - sts.b_iso_out.rxbytes; - } else { - iso_packet->length = dwc_ep->data_per_frame - sts.b_iso_out.rxbytes + - (4 - dwc_ep->data_per_frame % 4); - } - - iso_packet->offset = offset; - } - else /** ISO IN EP */ - { - dma_desc = dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * dwc_ep->proc_buf_num; - - for(i = 0; i < dwc_ep->desc_cnt - 1; i++) - { - sts.d32 = readl(&dma_desc->status); - - /* Write status in iso packet descriptor */ - iso_packet->status = sts.b_iso_in.txsts + (sts.b_iso_in.bs^BS_DMA_DONE); - if(iso_packet->status != 0) { - iso_packet->status = -ENODATA; - - } - /* Bytes has been transfered */ - iso_packet->length = dwc_ep->data_per_frame - sts.b_iso_in.txbytes; - - dma_desc ++; - iso_packet++; - } - - sts.d32 = readl(&dma_desc->status); - while(sts.b_iso_in.bs == BS_DMA_BUSY) { - sts.d32 = readl(&dma_desc->status); - } - - /* Write status in iso packet descriptor ??? do be done with ERROR codes*/ - iso_packet->status = sts.b_iso_in.txsts + (sts.b_iso_in.bs^BS_DMA_DONE); - if(iso_packet->status != 0) { - iso_packet->status = -ENODATA; - } - - /* Bytes has been transfered */ - iso_packet->length = dwc_ep->data_per_frame - sts.b_iso_in.txbytes; - } -} - -/** - * This function reinitialize DMA Descriptors for Isochronous transfer - * - * @param core_if Programming view of DWC_otg controller. - * @param dwc_ep The EP to start the transfer on. - * - */ -static void reinit_ddma_iso_xfer(dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep) -{ - int i, j; - dwc_otg_dma_desc_t* dma_desc; - dma_addr_t dma_ad; - volatile uint32_t *addr; - desc_sts_data_t sts = { .d32 =0 }; - uint32_t data_per_desc; - - if(dwc_ep->is_in == 0) { - addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl; - } - else { - addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl; - } - - - if(dwc_ep->proc_buf_num == 0) { - /** Buffer 0 descriptors setup */ - dma_ad = dwc_ep->dma_addr0; - } - else { - /** Buffer 1 descriptors setup */ - dma_ad = dwc_ep->dma_addr1; - } - - - /** Reinit closed DMA Descriptors*/ - /** ISO OUT EP */ - if(dwc_ep->is_in == 0) { - dma_desc = dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * dwc_ep->proc_buf_num; - - sts.b_iso_out.bs = BS_HOST_READY; - sts.b_iso_out.rxsts = 0; - sts.b_iso_out.l = 0; - sts.b_iso_out.sp = 0; - sts.b_iso_out.ioc = 0; - sts.b_iso_out.pid = 0; - sts.b_iso_out.framenum = 0; - - for(i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; i+= dwc_ep->pkt_per_frm) - { - for(j = 0; j < dwc_ep->pkt_per_frm; ++j) - { - data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ? - dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket; - data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0; - sts.b_iso_out.rxbytes = data_per_desc; - writel((uint32_t)dma_ad, &dma_desc->buf); - writel(sts.d32, &dma_desc->status); - - (uint32_t)dma_ad += data_per_desc; - dma_desc ++; - } - } - - for(j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) - { - - data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ? - dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket; - data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0; - sts.b_iso_out.rxbytes = data_per_desc; - - writel((uint32_t)dma_ad, &dma_desc->buf); - writel(sts.d32, &dma_desc->status); - - dma_desc++; - (uint32_t)dma_ad += data_per_desc; - } - - sts.b_iso_out.ioc = 1; - sts.b_iso_out.l = dwc_ep->proc_buf_num; - - data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ? - dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket; - data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0; - sts.b_iso_out.rxbytes = data_per_desc; - - writel((uint32_t)dma_ad, &dma_desc->buf); - writel(sts.d32, &dma_desc->status); - } - else /** ISO IN EP */ - { - dma_desc = dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * dwc_ep->proc_buf_num; - - sts.b_iso_in.bs = BS_HOST_READY; - sts.b_iso_in.txsts = 0; - sts.b_iso_in.sp = 0; - sts.b_iso_in.ioc = 0; - sts.b_iso_in.pid = dwc_ep->pkt_per_frm; - sts.b_iso_in.framenum = dwc_ep->next_frame; - sts.b_iso_in.txbytes = dwc_ep->data_per_frame; - sts.b_iso_in.l = 0; - - for(i = 0; i < dwc_ep->desc_cnt - 1; i++) - { - writel((uint32_t)dma_ad, &dma_desc->buf); - writel(sts.d32, &dma_desc->status); - - sts.b_iso_in.framenum += dwc_ep->bInterval; - (uint32_t)dma_ad += dwc_ep->data_per_frame; - dma_desc ++; - } - - sts.b_iso_in.ioc = 1; - sts.b_iso_in.l = dwc_ep->proc_buf_num; - - writel((uint32_t)dma_ad, &dma_desc->buf); - writel(sts.d32, &dma_desc->status); - - dwc_ep->next_frame = sts.b_iso_in.framenum + dwc_ep->bInterval * 1; - } - dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1; -} - - -/** - * This function is to handle Iso EP transfer complete interrupt - * in case Iso out packet was dropped - * - * @param core_if Programming view of DWC_otg controller. - * @param dwc_ep The EP for wihich transfer complete was asserted - * - */ -static uint32_t handle_iso_out_pkt_dropped(dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep) -{ - uint32_t dma_addr; - uint32_t drp_pkt; - uint32_t drp_pkt_cnt; - deptsiz_data_t deptsiz = { .d32 = 0 }; - depctl_data_t depctl = { .d32 = 0 }; - int i; - - deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz); - - drp_pkt = dwc_ep->pkt_cnt - deptsiz.b.pktcnt; - drp_pkt_cnt = dwc_ep->pkt_per_frm - (drp_pkt % dwc_ep->pkt_per_frm); - - /* Setting dropped packets status */ - for(i = 0; i < drp_pkt_cnt; ++i) { - dwc_ep->pkt_info[drp_pkt].status = -ENODATA; - drp_pkt ++; - deptsiz.b.pktcnt--; - } - - - if(deptsiz.b.pktcnt > 0) { - deptsiz.b.xfersize = dwc_ep->xfer_len - (dwc_ep->pkt_cnt - deptsiz.b.pktcnt) * dwc_ep->maxpacket; - } else { - deptsiz.b.xfersize = 0; - deptsiz.b.pktcnt = 0; - } - - dwc_write_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz, deptsiz.d32); - - if(deptsiz.b.pktcnt > 0) { - if(dwc_ep->proc_buf_num) { - dma_addr = dwc_ep->dma_addr1 + dwc_ep->xfer_len - deptsiz.b.xfersize; - } else { - dma_addr = dwc_ep->dma_addr0 + dwc_ep->xfer_len - deptsiz.b.xfersize;; - } - - dwc_write_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepdma, dma_addr); - - /** Re-enable endpoint, clear nak */ - depctl.d32 = 0; - depctl.b.epena = 1; - depctl.b.cnak = 1; - - dwc_modify_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl, - depctl.d32,depctl.d32); - return 0; - } else { - return 1; - } -} - -/** - * This function sets iso packets information(PTI mode) - * - * @param core_if Programming view of DWC_otg controller. - * @param ep The EP to start the transfer on. - * - */ -static uint32_t set_iso_pkts_info(dwc_otg_core_if_t *core_if, dwc_ep_t *ep) -{ - int i, j; - dma_addr_t dma_ad; - iso_pkt_info_t *packet_info = ep->pkt_info; - uint32_t offset; - uint32_t frame_data; - deptsiz_data_t deptsiz; - - if(ep->proc_buf_num == 0) { - /** Buffer 0 descriptors setup */ - dma_ad = ep->dma_addr0; - } - else { - /** Buffer 1 descriptors setup */ - dma_ad = ep->dma_addr1; - } - - - if(ep->is_in) { - deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz); - } else { - deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doeptsiz); - } - - if(!deptsiz.b.xfersize) { - offset = 0; - for(i = 0; i < ep->pkt_cnt; i += ep->pkt_per_frm) - { - frame_data = ep->data_per_frame; - for(j = 0; j < ep->pkt_per_frm; ++j) { - - /* Packet status - is not set as initially - * it is set to 0 and if packet was sent - successfully, status field will remain 0*/ - - - /* Bytes has been transfered */ - packet_info->length = (ep->maxpacket < frame_data) ? - ep->maxpacket : frame_data; - - /* Received packet offset */ - packet_info->offset = offset; - offset += packet_info->length; - frame_data -= packet_info->length; - - packet_info ++; - } - } - return 1; - } else { - /* This is a workaround for in case of Transfer Complete with - * PktDrpSts interrupts merging - in this case Transfer complete - * interrupt for Isoc Out Endpoint is asserted without PktDrpSts - * set and with DOEPTSIZ register non zero. Investigations showed, - * that this happens when Out packet is dropped, but because of - * interrupts merging during first interrupt handling PktDrpSts - * bit is cleared and for next merged interrupts it is not reset. - * In this case SW hadles the interrupt as if PktDrpSts bit is set. - */ - if(ep->is_in) { - return 1; - } else { - return handle_iso_out_pkt_dropped(core_if, ep); - } - } -} - -/** - * This function is to handle Iso EP transfer complete interrupt - * - * @param ep The EP for which transfer complete was asserted - * - */ -static void complete_iso_ep(dwc_otg_pcd_ep_t *ep) -{ - dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd); - dwc_ep_t *dwc_ep = &ep->dwc_ep; - uint8_t is_last = 0; - - if(core_if->dma_enable) { - if(core_if->dma_desc_enable) { - set_ddma_iso_pkts_info(core_if, dwc_ep); - reinit_ddma_iso_xfer(core_if, dwc_ep); - is_last = 1; - } else { - if(core_if->pti_enh_enable) { - if(set_iso_pkts_info(core_if, dwc_ep)) { - dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1; - dwc_otg_iso_ep_start_buf_transfer(core_if, dwc_ep); - is_last = 1; - } - } else { - set_current_pkt_info(core_if, dwc_ep); - if(dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) { - is_last = 1; - dwc_ep->cur_pkt = 0; - dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1; - if(dwc_ep->proc_buf_num) { - dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1; - dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1; - } else { - dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0; - dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0; - } - - } - dwc_otg_iso_ep_start_frm_transfer(core_if, dwc_ep); - } - } - } else { - set_current_pkt_info(core_if, dwc_ep); - if(dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) { - is_last = 1; - dwc_ep->cur_pkt = 0; - dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1; - if(dwc_ep->proc_buf_num) { - dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1; - dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1; - } else { - dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0; - dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0; - } - - } - dwc_otg_iso_ep_start_frm_transfer(core_if, dwc_ep); - } - if(is_last) - dwc_otg_iso_buffer_done(ep, ep->iso_req); -} - -#endif //DWC_EN_ISOC - - -/** - * This function handles EP0 Control transfers. - * - * The state of the control tranfers are tracked in - * ep0state. - */ -static void handle_ep0(dwc_otg_pcd_t *pcd) -{ - dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); - dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; - desc_sts_data_t desc_sts; - deptsiz0_data_t deptsiz; - uint32_t byte_count; - -#ifdef DEBUG_EP0 - DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__); - print_ep0_state(pcd); -#endif - - switch (pcd->ep0state) { - case EP0_DISCONNECT: - break; - - case EP0_IDLE: - pcd->request_config = 0; - - pcd_setup(pcd); - break; - - case EP0_IN_DATA_PHASE: -#ifdef DEBUG_EP0 - DWC_DEBUGPL(DBG_PCD, "DATA_IN EP%d-%s: type=%d, mps=%d\n", - ep0->dwc_ep.num, (ep0->dwc_ep.is_in ?"IN":"OUT"), - ep0->dwc_ep.type, ep0->dwc_ep.maxpacket); -#endif - - if (core_if->dma_enable != 0) { - /* - * For EP0 we can only program 1 packet at a time so we - * need to do the make calculations after each complete. - * Call write_packet to make the calculations, as in - * slave mode, and use those values to determine if we - * can complete. - */ - if(core_if->dma_desc_enable == 0) { - deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[0]->dieptsiz); - byte_count = ep0->dwc_ep.xfer_len - deptsiz.b.xfersize; - } - else { - desc_sts.d32 = readl(core_if->dev_if->in_desc_addr); - byte_count = ep0->dwc_ep.xfer_len - desc_sts.b.bytes; - } - ep0->dwc_ep.xfer_count += byte_count; - ep0->dwc_ep.xfer_buff += byte_count; - ep0->dwc_ep.dma_addr += byte_count; - } - if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) { - dwc_otg_ep0_continue_transfer (GET_CORE_IF(pcd), &ep0->dwc_ep); - DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n"); - } - else if(ep0->dwc_ep.sent_zlp) { - dwc_otg_ep0_continue_transfer (GET_CORE_IF(pcd), &ep0->dwc_ep); - ep0->dwc_ep.sent_zlp = 0; - DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n"); - } - else { - ep0_complete_request(ep0); - DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n"); - } - break; - case EP0_OUT_DATA_PHASE: -#ifdef DEBUG_EP0 - DWC_DEBUGPL(DBG_PCD, "DATA_OUT EP%d-%s: type=%d, mps=%d\n", - ep0->dwc_ep.num, (ep0->dwc_ep.is_in ?"IN":"OUT"), - ep0->dwc_ep.type, ep0->dwc_ep.maxpacket); -#endif - if (core_if->dma_enable != 0) { - if(core_if->dma_desc_enable == 0) { - deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->out_ep_regs[0]->doeptsiz); - byte_count = ep0->dwc_ep.maxpacket - deptsiz.b.xfersize; - } - else { - desc_sts.d32 = readl(core_if->dev_if->out_desc_addr); - byte_count = ep0->dwc_ep.maxpacket - desc_sts.b.bytes; - } - ep0->dwc_ep.xfer_count += byte_count; - ep0->dwc_ep.xfer_buff += byte_count; - ep0->dwc_ep.dma_addr += byte_count; - } - if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) { - dwc_otg_ep0_continue_transfer (GET_CORE_IF(pcd), &ep0->dwc_ep); - DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n"); - } - else if(ep0->dwc_ep.sent_zlp) { - dwc_otg_ep0_continue_transfer (GET_CORE_IF(pcd), &ep0->dwc_ep); - ep0->dwc_ep.sent_zlp = 0; - DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n"); - } - else { - ep0_complete_request(ep0); - DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n"); - } - break; - - - case EP0_IN_STATUS_PHASE: - case EP0_OUT_STATUS_PHASE: - DWC_DEBUGPL(DBG_PCD, "CASE: EP0_STATUS\n"); - ep0_complete_request(ep0); - pcd->ep0state = EP0_IDLE; - ep0->stopped = 1; - ep0->dwc_ep.is_in = 0; /* OUT for next SETUP */ - - /* Prepare for more SETUP Packets */ - if(core_if->dma_enable) { - ep0_out_start(core_if, pcd); - } - break; - - case EP0_STALL: - DWC_ERROR("EP0 STALLed, should not get here pcd_setup()\n"); - break; - } -#ifdef DEBUG_EP0 - print_ep0_state(pcd); -#endif -} - - -/** - * Restart transfer - */ -static void restart_transfer(dwc_otg_pcd_t *pcd, const uint32_t epnum) -{ - dwc_otg_core_if_t *core_if; - dwc_otg_dev_if_t *dev_if; - deptsiz_data_t dieptsiz = {.d32=0}; - dwc_otg_pcd_ep_t *ep; - - ep = get_in_ep(pcd, epnum); - -#ifdef DWC_EN_ISOC - if(ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) { - return; - } -#endif /* DWC_EN_ISOC */ - - core_if = GET_CORE_IF(pcd); - dev_if = core_if->dev_if; - - dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dieptsiz); - - DWC_DEBUGPL(DBG_PCD,"xfer_buff=%p xfer_count=%0x xfer_len=%0x" - " stopped=%d\n", ep->dwc_ep.xfer_buff, - ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len , - ep->stopped); - /* - * If xfersize is 0 and pktcnt in not 0, resend the last packet. - */ - if (dieptsiz.b.pktcnt && dieptsiz.b.xfersize == 0 && - ep->dwc_ep.start_xfer_buff != 0) { - if (ep->dwc_ep.total_len <= ep->dwc_ep.maxpacket) { - ep->dwc_ep.xfer_count = 0; - ep->dwc_ep.xfer_buff = ep->dwc_ep.start_xfer_buff; - ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count; - } - else { - ep->dwc_ep.xfer_count -= ep->dwc_ep.maxpacket; - /* convert packet size to dwords. */ - ep->dwc_ep.xfer_buff -= ep->dwc_ep.maxpacket; - ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count; - } - ep->stopped = 0; - DWC_DEBUGPL(DBG_PCD,"xfer_buff=%p xfer_count=%0x " - "xfer_len=%0x stopped=%d\n", - ep->dwc_ep.xfer_buff, - ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len , - ep->stopped - ); - if (epnum == 0) { - dwc_otg_ep0_start_transfer(core_if, &ep->dwc_ep); - } - else { - dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep); - } - } -} - - -/** - * handle the IN EP disable interrupt. - */ -static inline void handle_in_ep_disable_intr(dwc_otg_pcd_t *pcd, - const uint32_t epnum) -{ - dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); - dwc_otg_dev_if_t *dev_if = core_if->dev_if; - deptsiz_data_t dieptsiz = {.d32=0}; - dctl_data_t dctl = {.d32=0}; - dwc_otg_pcd_ep_t *ep; - dwc_ep_t *dwc_ep; - - ep = get_in_ep(pcd, epnum); - dwc_ep = &ep->dwc_ep; - - if(dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { - dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num); - return; - } - - DWC_DEBUGPL(DBG_PCD,"diepctl%d=%0x\n", epnum, - dwc_read_reg32(&dev_if->in_ep_regs[epnum]->diepctl)); - dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dieptsiz); - - DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n", - dieptsiz.b.pktcnt, - dieptsiz.b.xfersize); - - if (ep->stopped) { - /* Flush the Tx FIFO */ - dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num); - /* Clear the Global IN NP NAK */ - dctl.d32 = 0; - dctl.b.cgnpinnak = 1; - dwc_modify_reg32(&dev_if->dev_global_regs->dctl, - dctl.d32, 0); - /* Restart the transaction */ - if (dieptsiz.b.pktcnt != 0 || - dieptsiz.b.xfersize != 0) { - restart_transfer(pcd, epnum); - } - } - else { - /* Restart the transaction */ - if (dieptsiz.b.pktcnt != 0 || - dieptsiz.b.xfersize != 0) { - restart_transfer(pcd, epnum); - } - DWC_DEBUGPL(DBG_ANY, "STOPPED!!!\n"); - } -} - -/** - * Handler for the IN EP timeout handshake interrupt. - */ -static inline void handle_in_ep_timeout_intr(dwc_otg_pcd_t *pcd, - const uint32_t epnum) -{ - dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); - dwc_otg_dev_if_t *dev_if = core_if->dev_if; - -#ifdef DEBUG - deptsiz_data_t dieptsiz = {.d32=0}; - uint32_t num = 0; -#endif - dctl_data_t dctl = {.d32=0}; - dwc_otg_pcd_ep_t *ep; - - gintmsk_data_t intr_mask = {.d32 = 0}; - - ep = get_in_ep(pcd, epnum); - - /* Disable the NP Tx Fifo Empty Interrrupt */ - if (!core_if->dma_enable) { - intr_mask.b.nptxfempty = 1; - dwc_modify_reg32(&core_if->core_global_regs->gintmsk, intr_mask.d32, 0); - } - /** @todo NGS Check EP type. - * Implement for Periodic EPs */ - /* - * Non-periodic EP - */ - /* Enable the Global IN NAK Effective Interrupt */ - intr_mask.b.ginnakeff = 1; - dwc_modify_reg32(&core_if->core_global_regs->gintmsk, - 0, intr_mask.d32); - - /* Set Global IN NAK */ - dctl.b.sgnpinnak = 1; - dwc_modify_reg32(&dev_if->dev_global_regs->dctl, - dctl.d32, dctl.d32); - - ep->stopped = 1; - -#ifdef DEBUG - dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[num]->dieptsiz); - DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n", - dieptsiz.b.pktcnt, - dieptsiz.b.xfersize); -#endif - -#ifdef DISABLE_PERIODIC_EP - /* - * Set the NAK bit for this EP to - * start the disable process. - */ - diepctl.d32 = 0; - diepctl.b.snak = 1; - dwc_modify_reg32(&dev_if->in_ep_regs[num]->diepctl, diepctl.d32, diepctl.d32); - ep->disabling = 1; - ep->stopped = 1; -#endif -} - -/** - * Handler for the IN EP NAK interrupt. - */ -static inline int32_t handle_in_ep_nak_intr(dwc_otg_pcd_t *pcd, - const uint32_t epnum) -{ - /** @todo implement ISR */ - dwc_otg_core_if_t* core_if; - diepmsk_data_t intr_mask = { .d32 = 0}; - - DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "IN EP NAK"); - core_if = GET_CORE_IF(pcd); - intr_mask.b.nak = 1; - - if(core_if->multiproc_int_enable) { - dwc_modify_reg32(&core_if->dev_if->dev_global_regs->diepeachintmsk[epnum], - intr_mask.d32, 0); - } else { - dwc_modify_reg32(&core_if->dev_if->dev_global_regs->diepmsk, - intr_mask.d32, 0); - } - - return 1; -} - -/** - * Handler for the OUT EP Babble interrupt. - */ -static inline int32_t handle_out_ep_babble_intr(dwc_otg_pcd_t *pcd, - const uint32_t epnum) -{ - /** @todo implement ISR */ - dwc_otg_core_if_t* core_if; - doepmsk_data_t intr_mask = { .d32 = 0}; - - DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "OUT EP Babble"); - core_if = GET_CORE_IF(pcd); - intr_mask.b.babble = 1; - - if(core_if->multiproc_int_enable) { - dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepeachintmsk[epnum], - intr_mask.d32, 0); - } else { - dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk, - intr_mask.d32, 0); - } - - return 1; -} - -/** - * Handler for the OUT EP NAK interrupt. - */ -static inline int32_t handle_out_ep_nak_intr(dwc_otg_pcd_t *pcd, - const uint32_t epnum) -{ - /** @todo implement ISR */ - dwc_otg_core_if_t* core_if; - doepmsk_data_t intr_mask = { .d32 = 0}; - - DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "OUT EP NAK"); - core_if = GET_CORE_IF(pcd); - intr_mask.b.nak = 1; - - if(core_if->multiproc_int_enable) { - dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepeachintmsk[epnum], - intr_mask.d32, 0); - } else { - dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk, - intr_mask.d32, 0); - } - - return 1; -} - -/** - * Handler for the OUT EP NYET interrupt. - */ -static inline int32_t handle_out_ep_nyet_intr(dwc_otg_pcd_t *pcd, - const uint32_t epnum) -{ - /** @todo implement ISR */ - dwc_otg_core_if_t* core_if; - doepmsk_data_t intr_mask = { .d32 = 0}; - - DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "OUT EP NYET"); - core_if = GET_CORE_IF(pcd); - intr_mask.b.nyet = 1; - - if(core_if->multiproc_int_enable) { - dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepeachintmsk[epnum], - intr_mask.d32, 0); - } else { - dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk, - intr_mask.d32, 0); - } - - return 1; -} - -/** - * This interrupt indicates that an IN EP has a pending Interrupt. - * The sequence for handling the IN EP interrupt is shown below: - * -# Read the Device All Endpoint Interrupt register - * -# Repeat the following for each IN EP interrupt bit set (from - * LSB to MSB). - * -# Read the Device Endpoint Interrupt (DIEPINTn) register - * -# If "Transfer Complete" call the request complete function - * -# If "Endpoint Disabled" complete the EP disable procedure. - * -# If "AHB Error Interrupt" log error - * -# If "Time-out Handshake" log error - * -# If "IN Token Received when TxFIFO Empty" write packet to Tx - * FIFO. - * -# If "IN Token EP Mismatch" (disable, this is handled by EP - * Mismatch Interrupt) - */ -static int32_t dwc_otg_pcd_handle_in_ep_intr(dwc_otg_pcd_t *pcd) -{ -#define CLEAR_IN_EP_INTR(__core_if,__epnum,__intr) \ -do { \ - diepint_data_t diepint = {.d32=0}; \ - diepint.b.__intr = 1; \ - dwc_write_reg32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \ - diepint.d32); \ -} while (0) - - dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); - dwc_otg_dev_if_t *dev_if = core_if->dev_if; - diepint_data_t diepint = {.d32=0}; - dctl_data_t dctl = {.d32=0}; - depctl_data_t depctl = {.d32=0}; - uint32_t ep_intr; - uint32_t epnum = 0; - dwc_otg_pcd_ep_t *ep; - dwc_ep_t *dwc_ep; - gintmsk_data_t intr_mask = {.d32 = 0}; - - - - DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pcd); - - /* Read in the device interrupt bits */ - ep_intr = dwc_otg_read_dev_all_in_ep_intr(core_if); - - /* Service the Device IN interrupts for each endpoint */ - while(ep_intr) { - if (ep_intr&0x1) { - uint32_t empty_msk; - /* Get EP pointer */ - ep = get_in_ep(pcd, epnum); - dwc_ep = &ep->dwc_ep; - - depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->diepctl); - empty_msk = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk); - - DWC_DEBUGPL(DBG_PCDV, - "IN EP INTERRUPT - %d\nepmty_msk - %8x diepctl - %8x\n", - epnum, - empty_msk, - depctl.d32); - - DWC_DEBUGPL(DBG_PCD, - "EP%d-%s: type=%d, mps=%d\n", - dwc_ep->num, (dwc_ep->is_in ?"IN":"OUT"), - dwc_ep->type, dwc_ep->maxpacket); - - diepint.d32 = dwc_otg_read_dev_in_ep_intr(core_if, dwc_ep); - - DWC_DEBUGPL(DBG_PCDV, "EP %d Interrupt Register - 0x%x\n", epnum, diepint.d32); - /* Transfer complete */ - if (diepint.b.xfercompl) { - /* Disable the NP Tx FIFO Empty - * Interrrupt */ - if(core_if->en_multiple_tx_fifo == 0) { - intr_mask.b.nptxfempty = 1; - dwc_modify_reg32(&core_if->core_global_regs->gintmsk, intr_mask.d32, 0); - } - else { - /* Disable the Tx FIFO Empty Interrupt for this EP */ - uint32_t fifoemptymsk = 0x1 << dwc_ep->num; - dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk, - fifoemptymsk, 0); - } - /* Clear the bit in DIEPINTn for this interrupt */ - CLEAR_IN_EP_INTR(core_if,epnum,xfercompl); - - /* Complete the transfer */ - if (epnum == 0) { - handle_ep0(pcd); - } -#ifdef DWC_EN_ISOC - else if(dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { - if(!ep->stopped) - complete_iso_ep(ep); - } -#endif //DWC_EN_ISOC - else { - - complete_ep(ep); - } - } - /* Endpoint disable */ - if (diepint.b.epdisabled) { - DWC_DEBUGPL(DBG_ANY,"EP%d IN disabled\n", epnum); - handle_in_ep_disable_intr(pcd, epnum); - - /* Clear the bit in DIEPINTn for this interrupt */ - CLEAR_IN_EP_INTR(core_if,epnum,epdisabled); - } - /* AHB Error */ - if (diepint.b.ahberr) { - DWC_DEBUGPL(DBG_ANY,"EP%d IN AHB Error\n", epnum); - /* Clear the bit in DIEPINTn for this interrupt */ - CLEAR_IN_EP_INTR(core_if,epnum,ahberr); - } - /* TimeOUT Handshake (non-ISOC IN EPs) */ - if (diepint.b.timeout) { - DWC_DEBUGPL(DBG_ANY,"EP%d IN Time-out\n", epnum); - handle_in_ep_timeout_intr(pcd, epnum); - - CLEAR_IN_EP_INTR(core_if,epnum,timeout); - } - /** IN Token received with TxF Empty */ - if (diepint.b.intktxfemp) { - DWC_DEBUGPL(DBG_ANY,"EP%d IN TKN TxFifo Empty\n", - epnum); - if (!ep->stopped && epnum != 0) { - - diepmsk_data_t diepmsk = { .d32 = 0}; - diepmsk.b.intktxfemp = 1; - - if(core_if->multiproc_int_enable) { - dwc_modify_reg32(&dev_if->dev_global_regs->diepeachintmsk[epnum], - diepmsk.d32, 0); - } else { - dwc_modify_reg32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32, 0); - } - start_next_request(ep); - } - else if(core_if->dma_desc_enable && epnum == 0 && - pcd->ep0state == EP0_OUT_STATUS_PHASE) { - // EP0 IN set STALL - depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->diepctl); - - /* set the disable and stall bits */ - if (depctl.b.epena) { - depctl.b.epdis = 1; - } - depctl.b.stall = 1; - dwc_write_reg32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32); - } - CLEAR_IN_EP_INTR(core_if,epnum,intktxfemp); - } - /** IN Token Received with EP mismatch */ - if (diepint.b.intknepmis) { - DWC_DEBUGPL(DBG_ANY,"EP%d IN TKN EP Mismatch\n", epnum); - CLEAR_IN_EP_INTR(core_if,epnum,intknepmis); - } - /** IN Endpoint NAK Effective */ - if (diepint.b.inepnakeff) { - DWC_DEBUGPL(DBG_ANY,"EP%d IN EP NAK Effective\n", epnum); - /* Periodic EP */ - if (ep->disabling) { - depctl.d32 = 0; - depctl.b.snak = 1; - depctl.b.epdis = 1; - dwc_modify_reg32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32, depctl.d32); - } - CLEAR_IN_EP_INTR(core_if,epnum,inepnakeff); - - } - - /** IN EP Tx FIFO Empty Intr */ - if (diepint.b.emptyintr) { - DWC_DEBUGPL(DBG_ANY,"EP%d Tx FIFO Empty Intr \n", epnum); - write_empty_tx_fifo(pcd, epnum); - - CLEAR_IN_EP_INTR(core_if,epnum,emptyintr); - - } - - /** IN EP BNA Intr */ - if (diepint.b.bna) { - CLEAR_IN_EP_INTR(core_if,epnum,bna); - if(core_if->dma_desc_enable) { -#ifdef DWC_EN_ISOC - if(dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { - /* - * This checking is performed to prevent first "false" BNA - * handling occuring right after reconnect - */ - if(dwc_ep->next_frame != 0xffffffff) - dwc_otg_pcd_handle_iso_bna(ep); - } - else -#endif //DWC_EN_ISOC - { - dctl.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dctl); - - /* If Global Continue on BNA is disabled - disable EP */ - if(!dctl.b.gcontbna) { - depctl.d32 = 0; - depctl.b.snak = 1; - depctl.b.epdis = 1; - dwc_modify_reg32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32, depctl.d32); - } else { - start_next_request(ep); - } - } - } - } - /* NAK Interrutp */ - if (diepint.b.nak) { - DWC_DEBUGPL(DBG_ANY,"EP%d IN NAK Interrupt\n", epnum); - handle_in_ep_nak_intr(pcd, epnum); - - CLEAR_IN_EP_INTR(core_if,epnum,nak); - } - } - epnum++; - ep_intr >>=1; - } - - return 1; -#undef CLEAR_IN_EP_INTR -} - -/** - * This interrupt indicates that an OUT EP has a pending Interrupt. - * The sequence for handling the OUT EP interrupt is shown below: - * -# Read the Device All Endpoint Interrupt register - * -# Repeat the following for each OUT EP interrupt bit set (from - * LSB to MSB). - * -# Read the Device Endpoint Interrupt (DOEPINTn) register - * -# If "Transfer Complete" call the request complete function - * -# If "Endpoint Disabled" complete the EP disable procedure. - * -# If "AHB Error Interrupt" log error - * -# If "Setup Phase Done" process Setup Packet (See Standard USB - * Command Processing) - */ -static int32_t dwc_otg_pcd_handle_out_ep_intr(dwc_otg_pcd_t *pcd) -{ -#define CLEAR_OUT_EP_INTR(__core_if,__epnum,__intr) \ -do { \ - doepint_data_t doepint = {.d32=0}; \ - doepint.b.__intr = 1; \ - dwc_write_reg32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \ - doepint.d32); \ -} while (0) - - dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); - dwc_otg_dev_if_t *dev_if = core_if->dev_if; - uint32_t ep_intr; - doepint_data_t doepint = {.d32=0}; - dctl_data_t dctl = {.d32=0}; - depctl_data_t doepctl = {.d32=0}; - uint32_t epnum = 0; - dwc_otg_pcd_ep_t *ep; - dwc_ep_t *dwc_ep; - - DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__); - - /* Read in the device interrupt bits */ - ep_intr = dwc_otg_read_dev_all_out_ep_intr(core_if); - - while(ep_intr) { - if (ep_intr&0x1) { - /* Get EP pointer */ - ep = get_out_ep(pcd, epnum); - dwc_ep = &ep->dwc_ep; - -#ifdef VERBOSE - DWC_DEBUGPL(DBG_PCDV, - "EP%d-%s: type=%d, mps=%d\n", - dwc_ep->num, (dwc_ep->is_in ?"IN":"OUT"), - dwc_ep->type, dwc_ep->maxpacket); -#endif - doepint.d32 = dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep); - - /* Transfer complete */ - if (doepint.b.xfercompl) { - - if (epnum == 0) { - /* Clear the bit in DOEPINTn for this interrupt */ - CLEAR_OUT_EP_INTR(core_if,epnum,xfercompl); - if(core_if->dma_desc_enable == 0 || pcd->ep0state != EP0_IDLE) - handle_ep0(pcd); -#ifdef DWC_EN_ISOC - } else if(dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { - if (doepint.b.pktdrpsts == 0) { - /* Clear the bit in DOEPINTn for this interrupt */ - CLEAR_OUT_EP_INTR(core_if,epnum,xfercompl); - complete_iso_ep(ep); - } else { - - doepint_data_t doepint = {.d32=0}; - doepint.b.xfercompl = 1; - doepint.b.pktdrpsts = 1; - dwc_write_reg32(&core_if->dev_if->out_ep_regs[epnum]->doepint, - doepint.d32); - if(handle_iso_out_pkt_dropped(core_if,dwc_ep)) { - complete_iso_ep(ep); - } - } -#endif //DWC_EN_ISOC - } else { - /* Clear the bit in DOEPINTn for this interrupt */ - CLEAR_OUT_EP_INTR(core_if,epnum,xfercompl); - complete_ep(ep); - } - - } - - /* Endpoint disable */ - if (doepint.b.epdisabled) { - - /* Clear the bit in DOEPINTn for this interrupt */ - CLEAR_OUT_EP_INTR(core_if,epnum,epdisabled); - } - /* AHB Error */ - if (doepint.b.ahberr) { - DWC_DEBUGPL(DBG_PCD,"EP%d OUT AHB Error\n", epnum); - DWC_DEBUGPL(DBG_PCD,"EP DMA REG %d \n", core_if->dev_if->out_ep_regs[epnum]->doepdma); - CLEAR_OUT_EP_INTR(core_if,epnum,ahberr); - } - /* Setup Phase Done (contorl EPs) */ - if (doepint.b.setup) { -#ifdef DEBUG_EP0 - DWC_DEBUGPL(DBG_PCD,"EP%d SETUP Done\n", - epnum); -#endif - CLEAR_OUT_EP_INTR(core_if,epnum,setup); - - handle_ep0(pcd); - } - - /** OUT EP BNA Intr */ - if (doepint.b.bna) { - CLEAR_OUT_EP_INTR(core_if,epnum,bna); - if(core_if->dma_desc_enable) { -#ifdef DWC_EN_ISOC - if(dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { - /* - * This checking is performed to prevent first "false" BNA - * handling occuring right after reconnect - */ - if(dwc_ep->next_frame != 0xffffffff) - dwc_otg_pcd_handle_iso_bna(ep); - } - else -#endif //DWC_EN_ISOC - { - dctl.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dctl); - - /* If Global Continue on BNA is disabled - disable EP*/ - if(!dctl.b.gcontbna) { - doepctl.d32 = 0; - doepctl.b.snak = 1; - doepctl.b.epdis = 1; - dwc_modify_reg32(&dev_if->out_ep_regs[epnum]->doepctl, doepctl.d32, doepctl.d32); - } else { - start_next_request(ep); - } - } - } - } - if (doepint.b.stsphsercvd) { - CLEAR_OUT_EP_INTR(core_if,epnum,stsphsercvd); - if(core_if->dma_desc_enable) { - do_setup_in_status_phase(pcd); - } - } - /* Babble Interrutp */ - if (doepint.b.babble) { - DWC_DEBUGPL(DBG_ANY,"EP%d OUT Babble\n", epnum); - handle_out_ep_babble_intr(pcd, epnum); - - CLEAR_OUT_EP_INTR(core_if,epnum,babble); - } - /* NAK Interrutp */ - if (doepint.b.nak) { - DWC_DEBUGPL(DBG_ANY,"EP%d OUT NAK\n", epnum); - handle_out_ep_nak_intr(pcd, epnum); - - CLEAR_OUT_EP_INTR(core_if,epnum,nak); - } - /* NYET Interrutp */ - if (doepint.b.nyet) { - DWC_DEBUGPL(DBG_ANY,"EP%d OUT NYET\n", epnum); - handle_out_ep_nyet_intr(pcd, epnum); - - CLEAR_OUT_EP_INTR(core_if,epnum,nyet); - } - } - - epnum++; - ep_intr >>=1; - } - - return 1; - -#undef CLEAR_OUT_EP_INTR -} - - -/** - * Incomplete ISO IN Transfer Interrupt. - * This interrupt indicates one of the following conditions occurred - * while transmitting an ISOC transaction. - * - Corrupted IN Token for ISOC EP. - * - Packet not complete in FIFO. - * The follow actions will be taken: - * -# Determine the EP - * -# Set incomplete flag in dwc_ep structure - * -# Disable EP; when "Endpoint Disabled" interrupt is received - * Flush FIFO - */ -int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr(dwc_otg_pcd_t *pcd) -{ - gintsts_data_t gintsts; - - -#ifdef DWC_EN_ISOC - dwc_otg_dev_if_t *dev_if; - deptsiz_data_t deptsiz = { .d32 = 0}; - depctl_data_t depctl = { .d32 = 0}; - dsts_data_t dsts = { .d32 = 0}; - dwc_ep_t *dwc_ep; - int i; - - dev_if = GET_CORE_IF(pcd)->dev_if; - - for(i = 1; i <= dev_if->num_in_eps; ++i) { - dwc_ep = &pcd->in_ep[i].dwc_ep; - if(dwc_ep->active && - dwc_ep->type == USB_ENDPOINT_XFER_ISOC) - { - deptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->dieptsiz); - depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl); - - if(depctl.b.epdis && deptsiz.d32) { - set_current_pkt_info(GET_CORE_IF(pcd), dwc_ep); - if(dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) { - dwc_ep->cur_pkt = 0; - dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1; - - if(dwc_ep->proc_buf_num) { - dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1; - dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1; - } else { - dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0; - dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0; - } - - } - - dsts.d32 = dwc_read_reg32(&GET_CORE_IF(pcd)->dev_if->dev_global_regs->dsts); - dwc_ep->next_frame = dsts.b.soffn; - - dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF(pcd), dwc_ep); - } - } - } - -#else - gintmsk_data_t intr_mask = { .d32 = 0}; - DWC_PRINT("INTERRUPT Handler not implemented for %s\n", - "IN ISOC Incomplete"); - - intr_mask.b.incomplisoin = 1; - dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, - intr_mask.d32, 0); -#endif //DWC_EN_ISOC - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.incomplisoin = 1; - dwc_write_reg32 (&GET_CORE_IF(pcd)->core_global_regs->gintsts, - gintsts.d32); - - return 1; -} - -/** - * Incomplete ISO OUT Transfer Interrupt. - * - * This interrupt indicates that the core has dropped an ISO OUT - * packet. The following conditions can be the cause: - * - FIFO Full, the entire packet would not fit in the FIFO. - * - CRC Error - * - Corrupted Token - * The follow actions will be taken: - * -# Determine the EP - * -# Set incomplete flag in dwc_ep structure - * -# Read any data from the FIFO - * -# Disable EP. when "Endpoint Disabled" interrupt is received - * re-enable EP. - */ -int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr(dwc_otg_pcd_t *pcd) -{ - /* @todo implement ISR */ - gintsts_data_t gintsts; - -#ifdef DWC_EN_ISOC - dwc_otg_dev_if_t *dev_if; - deptsiz_data_t deptsiz = { .d32 = 0}; - depctl_data_t depctl = { .d32 = 0}; - dsts_data_t dsts = { .d32 = 0}; - dwc_ep_t *dwc_ep; - int i; - - dev_if = GET_CORE_IF(pcd)->dev_if; - - for(i = 1; i <= dev_if->num_out_eps; ++i) { - dwc_ep = &pcd->in_ep[i].dwc_ep; - if(pcd->out_ep[i].dwc_ep.active && - pcd->out_ep[i].dwc_ep.type == USB_ENDPOINT_XFER_ISOC) - { - deptsiz.d32 = dwc_read_reg32(&dev_if->out_ep_regs[i]->doeptsiz); - depctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[i]->doepctl); - - if(depctl.b.epdis && deptsiz.d32) { - set_current_pkt_info(GET_CORE_IF(pcd), &pcd->out_ep[i].dwc_ep); - if(dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) { - dwc_ep->cur_pkt = 0; - dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1; - - if(dwc_ep->proc_buf_num) { - dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1; - dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1; - } else { - dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0; - dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0; - } - - } - - dsts.d32 = dwc_read_reg32(&GET_CORE_IF(pcd)->dev_if->dev_global_regs->dsts); - dwc_ep->next_frame = dsts.b.soffn; - - dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF(pcd), dwc_ep); - } - } - } -#else - /** @todo implement ISR */ - gintmsk_data_t intr_mask = { .d32 = 0}; - - DWC_PRINT("INTERRUPT Handler not implemented for %s\n", - "OUT ISOC Incomplete"); - - intr_mask.b.incomplisoout = 1; - dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, - intr_mask.d32, 0); - -#endif // DWC_EN_ISOC - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.incomplisoout = 1; - dwc_write_reg32 (&GET_CORE_IF(pcd)->core_global_regs->gintsts, - gintsts.d32); - - return 1; -} - -/** - * This function handles the Global IN NAK Effective interrupt. - * - */ -int32_t dwc_otg_pcd_handle_in_nak_effective(dwc_otg_pcd_t *pcd) -{ - dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if; - depctl_data_t diepctl = { .d32 = 0}; - depctl_data_t diepctl_rd = { .d32 = 0}; - gintmsk_data_t intr_mask = { .d32 = 0}; - gintsts_data_t gintsts; - int i; - - DWC_DEBUGPL(DBG_PCD, "Global IN NAK Effective\n"); - - /* Disable all active IN EPs */ - diepctl.b.epdis = 1; - diepctl.b.snak = 1; - - for (i=0; i <= dev_if->num_in_eps; i++) - { - diepctl_rd.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl); - if (diepctl_rd.b.epena) { - dwc_write_reg32(&dev_if->in_ep_regs[i]->diepctl, - diepctl.d32); - } - } - /* Disable the Global IN NAK Effective Interrupt */ - intr_mask.b.ginnakeff = 1; - dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, - intr_mask.d32, 0); - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.ginnakeff = 1; - dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, - gintsts.d32); - - return 1; -} - -/** - * OUT NAK Effective. - * - */ -int32_t dwc_otg_pcd_handle_out_nak_effective(dwc_otg_pcd_t *pcd) -{ - gintmsk_data_t intr_mask = { .d32 = 0}; - gintsts_data_t gintsts; - - DWC_PRINT("INTERRUPT Handler not implemented for %s\n", - "Global IN NAK Effective\n"); - /* Disable the Global IN NAK Effective Interrupt */ - intr_mask.b.goutnakeff = 1; - dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, - intr_mask.d32, 0); - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.goutnakeff = 1; - dwc_write_reg32 (&GET_CORE_IF(pcd)->core_global_regs->gintsts, - gintsts.d32); - - return 1; -} - - -/** - * PCD interrupt handler. - * - * The PCD handles the device interrupts. Many conditions can cause a - * device interrupt. When an interrupt occurs, the device interrupt - * service routine determines the cause of the interrupt and - * dispatches handling to the appropriate function. These interrupt - * handling functions are described below. - * - * All interrupt registers are processed from LSB to MSB. - * - */ -int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t *pcd) -{ - dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); -#ifdef VERBOSE - dwc_otg_core_global_regs_t *global_regs = - core_if->core_global_regs; -#endif - gintsts_data_t gintr_status; - int32_t retval = 0; - - -#ifdef VERBOSE - DWC_DEBUGPL(DBG_ANY, "%s() gintsts=%08x gintmsk=%08x\n", - __func__, - dwc_read_reg32(&global_regs->gintsts), - dwc_read_reg32(&global_regs->gintmsk)); -#endif - - if (dwc_otg_is_device_mode(core_if)) { - SPIN_LOCK(&pcd->lock); -#ifdef VERBOSE - DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%08x gintmsk=%08x\n", - __func__, - dwc_read_reg32(&global_regs->gintsts), - dwc_read_reg32(&global_regs->gintmsk)); -#endif - - gintr_status.d32 = dwc_otg_read_core_intr(core_if); - -/* - if (!gintr_status.d32) { - SPIN_UNLOCK(&pcd->lock); - return 0; - } -*/ - DWC_DEBUGPL(DBG_PCDV, "%s: gintsts&gintmsk=%08x\n", - __func__, gintr_status.d32); - - if (gintr_status.b.sofintr) { - retval |= dwc_otg_pcd_handle_sof_intr(pcd); - } - if (gintr_status.b.rxstsqlvl) { - retval |= dwc_otg_pcd_handle_rx_status_q_level_intr(pcd); - } - if (gintr_status.b.nptxfempty) { - retval |= dwc_otg_pcd_handle_np_tx_fifo_empty_intr(pcd); - } - if (gintr_status.b.ginnakeff) { - retval |= dwc_otg_pcd_handle_in_nak_effective(pcd); - } - if (gintr_status.b.goutnakeff) { - retval |= dwc_otg_pcd_handle_out_nak_effective(pcd); - } - if (gintr_status.b.i2cintr) { - retval |= dwc_otg_pcd_handle_i2c_intr(pcd); - } - if (gintr_status.b.erlysuspend) { - retval |= dwc_otg_pcd_handle_early_suspend_intr(pcd); - } - if (gintr_status.b.usbreset) { - retval |= dwc_otg_pcd_handle_usb_reset_intr(pcd); - } - if (gintr_status.b.enumdone) { - retval |= dwc_otg_pcd_handle_enum_done_intr(pcd); - } - if (gintr_status.b.isooutdrop) { - retval |= dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(pcd); - } - if (gintr_status.b.eopframe) { - retval |= dwc_otg_pcd_handle_end_periodic_frame_intr(pcd); - } - if (gintr_status.b.epmismatch) { - retval |= dwc_otg_pcd_handle_ep_mismatch_intr(core_if); - } - if (gintr_status.b.inepint) { - if(!core_if->multiproc_int_enable) { - retval |= dwc_otg_pcd_handle_in_ep_intr(pcd); - } - } - if (gintr_status.b.outepintr) { - if(!core_if->multiproc_int_enable) { - retval |= dwc_otg_pcd_handle_out_ep_intr(pcd); - } - } - if (gintr_status.b.incomplisoin) { - retval |= dwc_otg_pcd_handle_incomplete_isoc_in_intr(pcd); - } - if (gintr_status.b.incomplisoout) { - retval |= dwc_otg_pcd_handle_incomplete_isoc_out_intr(pcd); - } - - /* In MPI mode De vice Endpoints intterrupts are asserted - * without setting outepintr and inepint bits set, so these - * Interrupt handlers are called without checking these bit-fields - */ - if(core_if->multiproc_int_enable) { - retval |= dwc_otg_pcd_handle_in_ep_intr(pcd); - retval |= dwc_otg_pcd_handle_out_ep_intr(pcd); - } -#ifdef VERBOSE - DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%0x\n", __func__, - dwc_read_reg32(&global_regs->gintsts)); -#endif - SPIN_UNLOCK(&pcd->lock); - } - - S3C2410X_CLEAR_EINTPEND(); - - return retval; -} - -#endif /* DWC_HOST_ONLY */ diff --git a/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_regs.h b/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_regs.h deleted file mode 100644 index 826576671b..0000000000 --- a/target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_regs.h +++ /dev/null @@ -1,2075 +0,0 @@ -/* ========================================================================== - * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $ - * $Revision: 1.2 $ - * $Date: 2008-11-21 05:39:15 $ - * $Change: 1099526 $ - * - * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, - * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless - * otherwise expressly agreed to in writing between Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ - -#ifndef __DWC_OTG_REGS_H__ -#define __DWC_OTG_REGS_H__ - -/** - * @file - * - * This file contains the data structures for accessing the DWC_otg core registers. - * - * The application interfaces with the HS OTG core by reading from and - * writing to the Control and Status Register (CSR) space through the - * AHB Slave interface. These registers are 32 bits wide, and the - * addresses are 32-bit-block aligned. - * CSRs are classified as follows: - * - Core Global Registers - * - Device Mode Registers - * - Device Global Registers - * - Device Endpoint Specific Registers - * - Host Mode Registers - * - Host Global Registers - * - Host Port CSRs - * - Host Channel Specific Registers - * - * Only the Core Global registers can be accessed in both Device and - * Host modes. When the HS OTG core is operating in one mode, either - * Device or Host, the application must not access registers from the - * other mode. When the core switches from one mode to another, the - * registers in the new mode of operation must be reprogrammed as they - * would be after a power-on reset. - */ - -/** Maximum number of Periodic FIFOs */ -#define MAX_PERIO_FIFOS 15 -/** Maximum number of Transmit FIFOs */ -#define MAX_TX_FIFOS 15 - -/** Maximum number of Endpoints/HostChannels */ -#define MAX_EPS_CHANNELS 16 - -/****************************************************************************/ -/** DWC_otg Core registers . - * The dwc_otg_core_global_regs structure defines the size - * and relative field offsets for the Core Global registers. - */ -typedef struct dwc_otg_core_global_regs -{ - /** OTG Control and Status Register. Offset: 000h */ - volatile uint32_t gotgctl; - /** OTG Interrupt Register. Offset: 004h */ - volatile uint32_t gotgint; - /**Core AHB Configuration Register. Offset: 008h */ - volatile uint32_t gahbcfg; - -#define DWC_GLBINTRMASK 0x0001 -#define DWC_DMAENABLE 0x0020 -#define DWC_NPTXEMPTYLVL_EMPTY 0x0080 -#define DWC_NPTXEMPTYLVL_HALFEMPTY 0x0000 -#define DWC_PTXEMPTYLVL_EMPTY 0x0100 -#define DWC_PTXEMPTYLVL_HALFEMPTY 0x0000 - - /**Core USB Configuration Register. Offset: 00Ch */ - volatile uint32_t gusbcfg; - /**Core Reset Register. Offset: 010h */ - volatile uint32_t grstctl; - /**Core Interrupt Register. Offset: 014h */ - volatile uint32_t gintsts; - /**Core Interrupt Mask Register. Offset: 018h */ - volatile uint32_t gintmsk; - /**Receive Status Queue Read Register (Read Only). Offset: 01Ch */ - volatile uint32_t grxstsr; - /**Receive Status Queue Read & POP Register (Read Only). Offset: 020h*/ - volatile uint32_t grxstsp; - /**Receive FIFO Size Register. Offset: 024h */ - volatile uint32_t grxfsiz; - /**Non Periodic Transmit FIFO Size Register. Offset: 028h */ - volatile uint32_t gnptxfsiz; - /**Non Periodic Transmit FIFO/Queue Status Register (Read - * Only). Offset: 02Ch */ - volatile uint32_t gnptxsts; - /**I2C Access Register. Offset: 030h */ - volatile uint32_t gi2cctl; - /**PHY Vendor Control Register. Offset: 034h */ - volatile uint32_t gpvndctl; - /**General Purpose Input/Output Register. Offset: 038h */ - volatile uint32_t ggpio; - /**User ID Register. Offset: 03Ch */ - volatile uint32_t guid; - /**Synopsys ID Register (Read Only). Offset: 040h */ - volatile uint32_t gsnpsid; - /**User HW Config1 Register (Read Only). Offset: 044h */ - volatile uint32_t ghwcfg1; - /**User HW Config2 Register (Read Only). Offset: 048h */ - volatile uint32_t ghwcfg2; -#define DWC_SLAVE_ONLY_ARCH 0 -#define DWC_EXT_DMA_ARCH 1 -#define DWC_INT_DMA_ARCH 2 - -#define DWC_MODE_HNP_SRP_CAPABLE 0 -#define DWC_MODE_SRP_ONLY_CAPABLE 1 -#define DWC_MODE_NO_HNP_SRP_CAPABLE 2 -#define DWC_MODE_SRP_CAPABLE_DEVICE 3 -#define DWC_MODE_NO_SRP_CAPABLE_DEVICE 4 -#define DWC_MODE_SRP_CAPABLE_HOST 5 -#define DWC_MODE_NO_SRP_CAPABLE_HOST 6 - - /**User HW Config3 Register (Read Only). Offset: 04Ch */ - volatile uint32_t ghwcfg3; - /**User HW Config4 Register (Read Only). Offset: 050h*/ - volatile uint32_t ghwcfg4; - /** Reserved Offset: 054h-0FFh */ - volatile uint32_t reserved[43]; - /** Host Periodic Transmit FIFO Size Register. Offset: 100h */ - volatile uint32_t hptxfsiz; - /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled, - otherwise Device Transmit FIFO#n Register. - * Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15). */ - volatile uint32_t dptxfsiz_dieptxf[15]; -} dwc_otg_core_global_regs_t; - -/** - * This union represents the bit fields of the Core OTG Control - * and Status Register (GOTGCTL). Set the bits using the bit - * fields then write the d32 value to the register. - */ -typedef union gotgctl_data -{ - /** raw register data */ - uint32_t d32; - /** register bits */ - struct - { - unsigned sesreqscs : 1; - unsigned sesreq : 1; - unsigned reserved2_7 : 6; - unsigned hstnegscs : 1; - unsigned hnpreq : 1; - unsigned hstsethnpen : 1; - unsigned devhnpen : 1; - unsigned reserved12_15 : 4; - unsigned conidsts : 1; - unsigned reserved17 : 1; - unsigned asesvld : 1; - unsigned bsesvld : 1; - unsigned currmod : 1; - unsigned reserved21_31 : 11; - } b; -} gotgctl_data_t; - -/** - * This union represents the bit fields of the Core OTG Interrupt Register - * (GOTGINT). Set/clear the bits using the bit fields then write the d32 - * value to the register. - */ -typedef union gotgint_data -{ - /** raw register data */ - uint32_t d32; - /** register bits */ - struct - { - /** Current Mode */ - unsigned reserved0_1 : 2; - - /** Session End Detected */ - unsigned sesenddet : 1; - - unsigned reserved3_7 : 5; - - /** Session Request Success Status Change */ - unsigned sesreqsucstschng : 1; - /** Host Negotiation Success Status Change */ - unsigned hstnegsucstschng : 1; - - unsigned reserver10_16 : 7; - - /** Host Negotiation Detected */ - unsigned hstnegdet : 1; - /** A-Device Timeout Change */ - unsigned adevtoutchng : 1; - /** Debounce Done */ - unsigned debdone : 1; - - unsigned reserved31_20 : 12; - - } b; -} gotgint_data_t; - - -/** - * This union represents the bit fields of the Core AHB Configuration - * Register (GAHBCFG). Set/clear the bits using the bit fields then - * write the d32 value to the register. - */ -typedef union gahbcfg_data -{ - /** raw register data */ - uint32_t d32; - /** register bits */ - struct - { - unsigned glblintrmsk : 1; -#define DWC_GAHBCFG_GLBINT_ENABLE 1 - - unsigned hburstlen : 4; -#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0 -#define DWC_GAHBCFG_INT_DMA_BURST_INCR 1 -#define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3 -#define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5 -#define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7 - - unsigned dmaenable : 1; -#define DWC_GAHBCFG_DMAENABLE 1 - unsigned reserved : 1; - unsigned nptxfemplvl_txfemplvl : 1; - unsigned ptxfemplvl : 1; -#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1 -#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 - unsigned reserved9_31 : 23; - } b; -} gahbcfg_data_t; - -/** - * This union represents the bit fields of the Core USB Configuration - * Register (GUSBCFG). Set the bits using the bit fields then write - * the d32 value to the register. - */ -typedef union gusbcfg_data -{ - /** raw register data */ - uint32_t d32; - /** register bits */ - struct - { - unsigned toutcal : 3; - unsigned phyif : 1; - unsigned ulpi_utmi_sel : 1; - unsigned fsintf : 1; - unsigned physel : 1; - unsigned ddrsel : 1; - unsigned srpcap : 1; - unsigned hnpcap : 1; - unsigned usbtrdtim : 4; - unsigned nptxfrwnden : 1; - unsigned phylpwrclksel : 1; - unsigned otgutmifssel : 1; - unsigned ulpi_fsls : 1; - unsigned ulpi_auto_res : 1; - unsigned ulpi_clk_sus_m : 1; - unsigned ulpi_ext_vbus_drv : 1; - unsigned ulpi_int_vbus_indicator : 1; - unsigned term_sel_dl_pulse : 1; - unsigned reserved23_27 : 5; - unsigned tx_end_delay : 1; - unsigned reserved29_31 : 3; - } b; -} gusbcfg_data_t; - -/** - * This union represents the bit fields of the Core Reset Register - * (GRSTCTL). Set/clear the bits using the bit fields then write the - * d32 value to the register. - */ -typedef union grstctl_data -{ - /** raw register data */ - uint32_t d32; - /** register bits */ - struct - { - /** Core Soft Reset (CSftRst) (Device and Host) - * - * The application can flush the control logic in the - * entire core using this bit. This bit resets the - * pipelines in the AHB Clock domain as well as the - * PHY Clock domain. - * - * The state machines are reset to an IDLE state, the - * control bits in the CSRs are cleared, all the - * transmit FIFOs and the receive FIFO are flushed. - * - * The status mask bits that control the generation of - * the interrupt, are cleared, to clear the - * interrupt. The interrupt status bits are not - * cleared, so the application can get the status of - * any events that occurred in the core after it has - * set this bit. - * - * Any transactions on the AHB are terminated as soon - * as possible following the protocol. Any - * transactions on the USB are terminated immediately. - * - * The configuration settings in the CSRs are - * unchanged, so the software doesn't have to - * reprogram these registers (Device - * Configuration/Host Configuration/Core System - * Configuration/Core PHY Configuration). - * - * The application can write to this bit, any time it - * wants to reset the core. This is a self clearing - * bit and the core clears this bit after all the - * necessary logic is reset in the core, which may - * take several clocks, depending on the current state - * of the core. - */ - unsigned csftrst : 1; - /** Hclk Soft Reset - * - * The application uses this bit to reset the control logic in - * the AHB clock domain. Only AHB clock domain pipelines are - * reset. - */ - unsigned hsftrst : 1; - /** Host Frame Counter Reset (Host Only)
- * - * The application can reset the (micro)frame number - * counter inside the core, using this bit. When the - * (micro)frame counter is reset, the subsequent SOF - * sent out by the core, will have a (micro)frame - * number of 0. - */ - unsigned hstfrm : 1; - /** In Token Sequence Learning Queue Flush - * (INTknQFlsh) (Device Only) - */ - unsigned intknqflsh : 1; - /** RxFIFO Flush (RxFFlsh) (Device and Host) - * - * The application can flush the entire Receive FIFO - * using this bit.

The application must first - * ensure that the core is not in the middle of a - * transaction.

The application should write into - * this bit, only after making sure that neither the - * DMA engine is reading from the RxFIFO nor the MAC - * is writing the data in to the FIFO.

The - * application should wait until the bit is cleared - * before performing any other operations. This bit - * will takes 8 clocks (slowest of PHY or AHB clock) - * to clear. - */ - unsigned rxfflsh : 1; - /** TxFIFO Flush (TxFFlsh) (Device and Host). - * - * This bit is used to selectively flush a single or - * all transmit FIFOs. The application must first - * ensure that the core is not in the middle of a - * transaction.

The application should write into - * this bit, only after making sure that neither the - * DMA engine is writing into the TxFIFO nor the MAC - * is reading the data out of the FIFO.

The - * application should wait until the core clears this - * bit, before performing any operations. This bit - * will takes 8 clocks (slowest of PHY or AHB clock) - * to clear. - */ - unsigned txfflsh : 1; - - /** TxFIFO Number (TxFNum) (Device and Host). - * - * This is the FIFO number which needs to be flushed, - * using the TxFIFO Flush bit. This field should not - * be changed until the TxFIFO Flush bit is cleared by - * the core. - * - 0x0 : Non Periodic TxFIFO Flush - * - 0x1 : Periodic TxFIFO #1 Flush in device mode - * or Periodic TxFIFO in host mode - * - 0x2 : Periodic TxFIFO #2 Flush in device mode. - * - ... - * - 0xF : Periodic TxFIFO #15 Flush in device mode - * - 0x10: Flush all the Transmit NonPeriodic and - * Transmit Periodic FIFOs in the core - */ - unsigned txfnum : 5; - /** Reserved */ - unsigned reserved11_29 : 19; - /** DMA Request Signal. Indicated DMA request is in - * probress. Used for debug purpose. */ - unsigned dmareq : 1; - /** AHB Master Idle. Indicates the AHB Master State - * Machine is in IDLE condition. */ - unsigned ahbidle : 1; - } b; -} grstctl_t; - - -/** - * This union represents the bit fields of the Core Interrupt Mask - * Register (GINTMSK). Set/clear the bits using the bit fields then - * write the d32 value to the register. - */ -typedef union gintmsk_data -{ - /** raw register data */ - uint32_t d32; - /** register bits */ - struct - { - unsigned reserved0 : 1; - unsigned modemismatch : 1; - unsigned otgintr : 1; - unsigned sofintr : 1; - unsigned rxstsqlvl : 1; - unsigned nptxfempty : 1; - unsigned ginnakeff : 1; - unsigned goutnakeff : 1; - unsigned reserved8 : 1; - unsigned i2cintr : 1; - unsigned erlysuspend : 1; - unsigned usbsuspend : 1; - unsigned usbreset : 1; - unsigned enumdone : 1; - unsigned isooutdrop : 1; - unsigned eopframe : 1; - unsigned reserved16 : 1; - unsigned epmismatch : 1; - unsigned inepintr : 1; - unsigned outepintr : 1; - unsigned incomplisoin : 1; - unsigned incomplisoout : 1; - unsigned reserved22_23 : 2; - unsigned portintr : 1; - unsigned hcintr : 1; - unsigned ptxfempty : 1; - unsigned reserved27 : 1; - unsigned conidstschng : 1; - unsigned disconnect : 1; - unsigned sessreqintr : 1; - unsigned wkupintr : 1; - } b; -} gintmsk_data_t; -/** - * This union represents the bit fields of the Core Interrupt Register - * (GINTSTS). Set/clear the bits using the bit fields then write the - * d32 value to the register. - */ -typedef union gintsts_data -{ - /** raw register data */ - uint32_t d32; -#define DWC_SOF_INTR_MASK 0x0008 - /** register bits */ - struct - { -#define DWC_HOST_MODE 1 - unsigned curmode : 1; - unsigned modemismatch : 1; - unsigned otgintr : 1; - unsigned sofintr : 1; - unsigned rxstsqlvl : 1; - unsigned nptxfempty : 1; - unsigned ginnakeff : 1; - unsigned goutnakeff : 1; - unsigned reserved8 : 1; - unsigned i2cintr : 1; - unsigned erlysuspend : 1; - unsigned usbsuspend : 1; - unsigned usbreset : 1; - unsigned enumdone : 1; - unsigned isooutdrop : 1; - unsigned eopframe : 1; - unsigned intokenrx : 1; - unsigned epmismatch : 1; - unsigned inepint: 1; - unsigned outepintr : 1; - unsigned incomplisoin : 1; - unsigned incomplisoout : 1; - unsigned reserved22_23 : 2; - unsigned portintr : 1; - unsigned hcintr : 1; - unsigned ptxfempty : 1; - unsigned reserved27 : 1; - unsigned conidstschng : 1; - unsigned disconnect : 1; - unsigned sessreqintr : 1; - unsigned wkupintr : 1; - } b; -} gintsts_data_t; - - -/** - * This union represents the bit fields in the Device Receive Status Read and - * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 - * element then read out the bits using the bit elements. - */ -typedef union device_grxsts_data -{ - /** raw register data */ - uint32_t d32; - /** register bits */ - struct - { - unsigned epnum : 4; - unsigned bcnt : 11; - unsigned dpid : 2; - -#define DWC_STS_DATA_UPDT 0x2 // OUT Data Packet -#define DWC_STS_XFER_COMP 0x3 // OUT Data Transfer Complete - -#define DWC_DSTS_GOUT_NAK 0x1 // Global OUT NAK -#define DWC_DSTS_SETUP_COMP 0x4 // Setup Phase Complete -#define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet - unsigned pktsts : 4; - unsigned fn : 4; - unsigned reserved : 7; - } b; -} device_grxsts_data_t; - -/** - * This union represents the bit fields in the Host Receive Status Read and - * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 - * element then read out the bits using the bit elements. - */ -typedef union host_grxsts_data -{ - /** raw register data */ - uint32_t d32; - /** register bits */ - struct - { - unsigned chnum : 4; - unsigned bcnt : 11; - unsigned dpid : 2; - - unsigned pktsts : 4; -#define DWC_GRXSTS_PKTSTS_IN 0x2 -#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP 0x3 -#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5 -#define DWC_GRXSTS_PKTSTS_CH_HALTED 0x7 - - unsigned reserved : 11; - } b; -} host_grxsts_data_t; - -/** - * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, - * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the d32 element then - * read out the bits using the bit elements. - */ -typedef union fifosize_data -{ - /** raw register data */ - uint32_t d32; - /** register bits */ - struct - { - unsigned startaddr : 16; - unsigned depth : 16; - } b; -} fifosize_data_t; - -/** - * This union represents the bit fields in the Non-Periodic Transmit - * FIFO/Queue Status Register (GNPTXSTS). Read the register into the - * d32 element then read out the bits using the bit - * elements. - */ -typedef union gnptxsts_data -{ - /** raw register data */ - uint32_t d32; - /** register bits */ - struct - { - unsigned nptxfspcavail : 16; - unsigned nptxqspcavail : 8; - /** Top of the Non-Periodic Transmit Request Queue - * - bit 24 - Terminate (Last entry for the selected - * channel/EP) - * - bits 26:25 - Token Type - * - 2'b00 - IN/OUT - * - 2'b01 - Zero Length OUT - * - 2'b10 - PING/Complete Split - * - 2'b11 - Channel Halt - * - bits 30:27 - Channel/EP Number - */ - unsigned nptxqtop_terminate : 1; - unsigned nptxqtop_token : 2; - unsigned nptxqtop_chnep : 4; - unsigned reserved : 1; - } b; -} gnptxsts_data_t; - -/** - * This union represents the bit fields in the Transmit - * FIFO Status Register (DTXFSTS). Read the register into the - * d32 element then read out the bits using the bit - * elements. - */ -typedef union dtxfsts_data -{ - /** raw register data */ - uint32_t d32; - /** register bits */ - struct - { - unsigned txfspcavail : 16; - unsigned reserved : 16; - } b; -} dtxfsts_data_t; - -/** - * This union represents the bit fields in the I2C Control Register - * (I2CCTL). Read the register into the d32 element then read out the - * bits using the bit elements. - */ -typedef union gi2cctl_data -{ - /** raw register data */ - uint32_t d32; - /** register bits */ - struct - { - unsigned rwdata : 8; - unsigned regaddr : 8; - unsigned addr : 7; - unsigned i2cen : 1; - unsigned ack : 1; - unsigned i2csuspctl : 1; - unsigned i2cdevaddr : 2; - unsigned reserved : 2; - unsigned rw : 1; - unsigned bsydne : 1; - } b; -} gi2cctl_data_t; - -/** - * This union represents the bit fields in the User HW Config1 - * Register. Read the register into the d32 element then read - * out the bits using the bit elements. - */ -typedef union hwcfg1_data -{ - /** raw register data */ - uint32_t d32; - /** register bits */ - struct - { - unsigned ep_dir0 : 2; - unsigned ep_dir1 : 2; - unsigned ep_dir2 : 2; - unsigned ep_dir3 : 2; - unsigned ep_dir4 : 2; - unsigned ep_dir5 : 2; - unsigned ep_dir6 : 2; - unsigned ep_dir7 : 2; - unsigned ep_dir8 : 2; - unsigned ep_dir9 : 2; - unsigned ep_dir10 : 2; - unsigned ep_dir11 : 2; - unsigned ep_dir12 : 2; - unsigned ep_dir13 : 2; - unsigned ep_dir14 : 2; - unsigned ep_dir15 : 2; - } b; -} hwcfg1_data_t; - -/** - * This union represents the bit fields in the User HW Config2 - * Register. Read the register into the d32 element then read - * out the bits using the bit elements. - */ -typedef union hwcfg2_data -{ - /** raw register data */ - uint32_t d32; - /** register bits */ - struct - { - /* GHWCFG2 */ - unsigned op_mode : 3; -#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0 -#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1 -#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2 -#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3 -#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4 -#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5 -#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6 - - unsigned architecture : 2; - unsigned point2point : 1; - unsigned hs_phy_type : 2; -#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0 -#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1 -#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2 -#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3 - - unsigned fs_phy_type : 2; - unsigned num_dev_ep : 4; - unsigned num_host_chan : 4; - unsigned perio_ep_supported : 1; - unsigned dynamic_fifo : 1; - unsigned multi_proc_int : 1; - unsigned reserved21 : 1; - unsigned nonperio_tx_q_depth : 2; - unsigned host_perio_tx_q_depth : 2; - unsigned dev_token_q_depth : 5; - unsigned reserved31 : 1; - } b; -} hwcfg2_data_t; - -/** - * This union represents the bit fields in the User HW Config3 - * Register. Read the register into the d32 element then read - * out the bits using the bit elements. - */ -typedef union hwcfg3_data -{ - /** raw register data */ - uint32_t d32; - /** register bits */ - struct - { - /* GHWCFG3 */ - unsigned xfer_size_cntr_width : 4; - unsigned packet_size_cntr_width : 3; - unsigned otg_func : 1; - unsigned i2c : 1; - unsigned vendor_ctrl_if : 1; - unsigned optional_features : 1; - unsigned synch_reset_type : 1; - unsigned ahb_phy_clock_synch : 1; - unsigned reserved15_13 : 3; - unsigned dfifo_depth : 16; - } b; -} hwcfg3_data_t; - -/** - * This union represents the bit fields in the User HW Config4 - * Register. Read the register into the d32 element then read - * out the bits using the bit elements. - */ -typedef union hwcfg4_data -{ - /** raw register data */ - uint32_t d32; - /** register bits */ - struct - { - unsigned num_dev_perio_in_ep : 4; - unsigned power_optimiz : 1; - unsigned min_ahb_freq : 9; - unsigned utmi_phy_data_width : 2; - unsigned num_dev_mode_ctrl_ep : 4; - unsigned iddig_filt_en : 1; - unsigned vbus_valid_filt_en : 1; - unsigned a_valid_filt_en : 1; - unsigned b_valid_filt_en : 1; - unsigned session_end_filt_en : 1; - unsigned ded_fifo_en : 1; - unsigned num_in_eps : 4; - unsigned desc_dma : 1; - unsigned desc_dma_dyn : 1; - } b; -} hwcfg4_data_t; - -//////////////////////////////////////////// -// Device Registers -/** - * Device Global Registers. Offsets 800h-BFFh - * - * The following structures define the size and relative field offsets - * for the Device Mode Registers. - * - * These registers are visible only in Device mode and must not be - * accessed in Host mode, as the results are unknown. - */ -typedef struct dwc_otg_dev_global_regs -{ - /** Device Configuration Register. Offset 800h */ - volatile uint32_t dcfg; - /** Device Control Register. Offset: 804h */ - volatile uint32_t dctl; - /** Device Status Register (Read Only). Offset: 808h */ - volatile uint32_t dsts; - /** Reserved. Offset: 80Ch */ - uint32_t unused; - /** Device IN Endpoint Common Interrupt Mask - * Register. Offset: 810h */ - volatile uint32_t diepmsk; - /** Device OUT Endpoint Common Interrupt Mask - * Register. Offset: 814h */ - volatile uint32_t doepmsk; - /** Device All Endpoints Interrupt Register. Offset: 818h */ - volatile uint32_t daint; - /** Device All Endpoints Interrupt Mask Register. Offset: - * 81Ch */ - volatile uint32_t daintmsk; - /** Device IN Token Queue Read Register-1 (Read Only). - * Offset: 820h */ - volatile uint32_t dtknqr1; - /** Device IN Token Queue Read Register-2 (Read Only). - * Offset: 824h */ - volatile uint32_t dtknqr2; - /** Device VBUS discharge Register. Offset: 828h */ - volatile uint32_t dvbusdis; - /** Device VBUS Pulse Register. Offset: 82Ch */ - volatile uint32_t dvbuspulse; - /** Device IN Token Queue Read Register-3 (Read Only). / - * Device Thresholding control register (Read/Write) - * Offset: 830h */ - volatile uint32_t dtknqr3_dthrctl; - /** Device IN Token Queue Read Register-4 (Read Only). / - * Device IN EPs empty Inr. Mask Register (Read/Write) - * Offset: 834h */ - volatile uint32_t dtknqr4_fifoemptymsk; - /** Device Each Endpoint Interrupt Register (Read Only). / - * Offset: 838h */ - volatile uint32_t deachint; - /** Device Each Endpoint Interrupt mask Register (Read/Write). / - * Offset: 83Ch */ - volatile uint32_t deachintmsk; - /** Device Each In Endpoint Interrupt mask Register (Read/Write). / - * Offset: 840h */ - volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS]; - /** Device Each Out Endpoint Interrupt mask Register (Read/Write). / - * Offset: 880h */ - volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS]; -} dwc_otg_device_global_regs_t; - -/** - * This union represents the bit fields in the Device Configuration - * Register. Read the register into the d32 member then - * set/clear the bits using the bit elements. Write the - * d32 member to the dcfg register. - */ -typedef union dcfg_data -{ - /** raw register data */ - uint32_t d32; - /** register bits */ - struct - { - /** Device Speed */ - unsigned devspd : 2; - /** Non Zero Length Status OUT Handshake */ - unsigned nzstsouthshk : 1; -#define DWC_DCFG_SEND_STALL 1 - - unsigned reserved3 : 1; - /** Device Addresses */ - unsigned devaddr : 7; - /** Periodic Frame Interval */ - unsigned perfrint : 2; -#define DWC_DCFG_FRAME_INTERVAL_80 0 -#define DWC_DCFG_FRAME_INTERVAL_85 1 -#define DWC_DCFG_FRAME_INTERVAL_90 2 -#define DWC_DCFG_FRAME_INTERVAL_95 3 - - unsigned reserved13_17 : 5; - /** In Endpoint Mis-match count */ - unsigned epmscnt : 5; - /** Enable Descriptor DMA in Device mode */ - unsigned descdma : 1; - } b; -} dcfg_data_t; - -/** - * This union represents the bit fields in the Device Control - * Register. Read the register into the d32 member then - * set/clear the bits using the bit elements. - */ -typedef union dctl_data -{ - /** raw register data */ - uint32_t d32; - /** register bits */ - struct - { - /** Remote Wakeup */ - unsigned rmtwkupsig : 1; - /** Soft Disconnect */ - unsigned sftdiscon : 1; - /** Global Non-Periodic IN NAK Status */ - unsigned gnpinnaksts : 1; - /** Global OUT NAK Status */ - unsigned goutnaksts : 1; - /** Test Control */ - unsigned tstctl : 3; - /** Set Global Non-Periodic IN NAK */ - unsigned sgnpinnak : 1; - /** Clear Global Non-Periodic IN NAK */ - unsigned cgnpinnak : 1; - /** Set Global OUT NAK */ - unsigned sgoutnak : 1; - /** Clear Global OUT NAK */ - unsigned cgoutnak : 1; - - /** Power-On Programming Done */ - unsigned pwronprgdone : 1; - /** Global Continue on BNA */ - unsigned gcontbna : 1; - /** Global Multi Count */ - unsigned gmc : 2; - /** Ignore Frame Number for ISOC EPs */ - unsigned ifrmnum : 1; - /** NAK on Babble */ - unsigned nakonbble : 1; - - unsigned reserved16_31 : 16; - } b; -} dctl_data_t; - -/** - * This union represents the bit fields in the Device Status - * Register. Read the register into the d32 member then - * set/clear the bits using the bit elements. - */ -typedef union dsts_data -{ - /** raw register data */ - uint32_t d32; - /** register bits */ - struct - { - /** Suspend Status */ - unsigned suspsts : 1; - /** Enumerated Speed */ - unsigned enumspd : 2; -#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 -#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 -#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2 -#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3 - /** Erratic Error */ - unsigned errticerr : 1; - unsigned reserved4_7: 4; - /** Frame or Microframe Number of the received SOF */ - unsigned soffn : 14; - unsigned reserved22_31 : 10; - } b; -} dsts_data_t; - - -/** - * This union represents the bit fields in the Device IN EP Interrupt - * Register and the Device IN EP Common Mask Register. - * - * - Read the register into the d32 member then set/clear the - * bits using the bit elements. - */ -typedef union diepint_data -{ - /** raw register data */ - uint32_t d32; - /** register bits */ - struct - { - /** Transfer complete mask */ - unsigned xfercompl : 1; - /** Endpoint disable mask */ - unsigned epdisabled : 1; - /** AHB Error mask */ - unsigned ahberr : 1; - /** TimeOUT Handshake mask (non-ISOC EPs) */ - unsigned timeout : 1; - /** IN Token received with TxF Empty mask */ - unsigned intktxfemp : 1; - /** IN Token Received with EP mismatch mask */ - unsigned intknepmis : 1; - /** IN Endpoint HAK Effective mask */ - unsigned inepnakeff : 1; - /** IN Endpoint HAK Effective mask */ - unsigned emptyintr : 1; - - unsigned txfifoundrn : 1; - - /** BNA Interrupt mask */ - unsigned bna : 1; - - unsigned reserved10_12 : 3; - /** BNA Interrupt mask */ - unsigned nak : 1; - - unsigned reserved14_31 : 18; - } b; -} diepint_data_t; - -/** - * This union represents the bit fields in the Device IN EP - * Common/Dedicated Interrupt Mask Register. - */ -typedef union diepint_data diepmsk_data_t; - -/** - * This union represents the bit fields in the Device OUT EP Interrupt - * Registerand Device OUT EP Common Interrupt Mask Register. - * - * - Read the register into the d32 member then set/clear the - * bits using the bit elements. - */ -typedef union doepint_data -{ - /** raw register data */ - uint32_t d32; - /** register bits */ - struct - { - /** Transfer complete */ - unsigned xfercompl : 1; - /** Endpoint disable */ - unsigned epdisabled : 1; - /** AHB Error */ - unsigned ahberr : 1; - /** Setup Phase Done (contorl EPs) */ - unsigned setup : 1; - /** OUT Token Received when Endpoint Disabled */ - unsigned outtknepdis : 1; - - unsigned stsphsercvd : 1; - /** Back-to-Back SETUP Packets Received */ - unsigned back2backsetup : 1; - - unsigned reserved7 : 1; - /** OUT packet Error */ - unsigned outpkterr : 1; - /** BNA Interrupt */ - unsigned bna : 1; - - unsigned reserved10 : 1; - /** Packet Drop Status */ - unsigned pktdrpsts : 1; - /** Babble Interrupt */ - unsigned babble : 1; - /** NAK Interrupt */ - unsigned nak : 1; - /** NYET Interrupt */ - unsigned nyet : 1; - - unsigned reserved15_31 : 17; - } b; -} doepint_data_t; - -/** - * This union represents the bit fields in the Device OUT EP - * Common/Dedicated Interrupt Mask Register. - */ -typedef union doepint_data doepmsk_data_t; - -/** - * This union represents the bit fields in the Device All EP Interrupt - * and Mask Registers. - * - Read the register into the d32 member then set/clear the - * bits using the bit elements. - */ -typedef union daint_data -{ - /** raw register data */ - uint32_t d32; - /** register bits */ - struct - { - /** IN Endpoint bits */ - unsigned in : 16; - /** OUT Endpoint bits */ - unsigned out : 16; - } ep; - struct - { - /** IN Endpoint bits */ - unsigned inep0 : 1; - unsigned inep1 : 1; - unsigned inep2 : 1; - unsigned inep3 : 1; - unsigned inep4 : 1; - unsigned inep5 : 1; - unsigned inep6 : 1; - unsigned inep7 : 1; - unsigned inep8 : 1; - unsigned inep9 : 1; - unsigned inep10 : 1; - unsigned inep11 : 1; - unsigned inep12 : 1; - unsigned inep13 : 1; - unsigned inep14 : 1; - unsigned inep15 : 1; - /** OUT Endpoint bits */ - unsigned outep0 : 1; - unsigned outep1 : 1; - unsigned outep2 : 1; - unsigned outep3 : 1; - unsigned outep4 : 1; - unsigned outep5 : 1; - unsigned outep6 : 1; - unsigned outep7 : 1; - unsigned outep8 : 1; - unsigned outep9 : 1; - unsigned outep10 : 1; - unsigned outep11 : 1; - unsigned outep12 : 1; - unsigned outep13 : 1; - unsigned outep14 : 1; - unsigned outep15 : 1; - } b; -} daint_data_t; - -/** - * This union represents the bit fields in the Device IN Token Queue - * Read Registers. - * - Read the register into the d32 member. - * - READ-ONLY Register - */ -typedef union dtknq1_data -{ - /** raw register data */ - uint32_t d32; - /** register bits */ - struct - { - /** In Token Queue Write Pointer */ - unsigned intknwptr : 5; - /** Reserved */ - unsigned reserved05_06 : 2; - /** write pointer has wrapped. */ - unsigned wrap_bit : 1; - /** EP Numbers of IN Tokens 0 ... 4 */ - unsigned epnums0_5 : 24; - }b; -} dtknq1_data_t; - -/** - * This union represents Threshold control Register - * - Read and write the register into the d32 member. - * - READ-WRITABLE Register - */ -typedef union dthrctl_data -{ - /** raw register data */ - uint32_t d32; - /** register bits */ - struct - { - /** non ISO Tx Thr. Enable */ - unsigned non_iso_thr_en : 1; - /** ISO Tx Thr. Enable */ - unsigned iso_thr_en : 1; - /** Tx Thr. Length */ - unsigned tx_thr_len : 9; - /** Reserved */ - unsigned reserved11_15 : 5; - /** Rx Thr. Enable */ - unsigned rx_thr_en : 1; - /** Rx Thr. Length */ - unsigned rx_thr_len : 9; - /** Reserved */ - unsigned reserved26_31 : 6; - }b; -} dthrctl_data_t; - - -/** - * Device Logical IN Endpoint-Specific Registers. Offsets - * 900h-AFCh - * - * There will be one set of endpoint registers per logical endpoint - * implemented. - * - * These registers are visible only in Device mode and must not be - * accessed in Host mode, as the results are unknown. - */ -typedef struct dwc_otg_dev_in_ep_regs -{ - /** Device IN Endpoint Control Register. Offset:900h + - * (ep_num * 20h) + 00h */ - volatile uint32_t diepctl; - /** Reserved. Offset:900h + (ep_num * 20h) + 04h */ - uint32_t reserved04; - /** Device IN Endpoint Interrupt Register. Offset:900h + - * (ep_num * 20h) + 08h */ - volatile uint32_t diepint; - /** Reserved. Offset:900h + (ep_num * 20h) + 0Ch */ - uint32_t reserved0C; - /** Device IN Endpoint Transfer Size - * Register. Offset:900h + (ep_num * 20h) + 10h */ - volatile uint32_t dieptsiz; - /** Device IN Endpoint DMA Address Register. Offset:900h + - * (ep_num * 20h) + 14h */ - volatile uint32_t diepdma; - /** Device IN Endpoint Transmit FIFO Status Register. Offset:900h + - * (ep_num * 20h) + 18h */ - volatile uint32_t dtxfsts; - /** Device IN Endpoint DMA Buffer Register. Offset:900h + - * (ep_num * 20h) + 1Ch */ - volatile uint32_t diepdmab; -} dwc_otg_dev_in_ep_regs_t; - -/** - * Device Logical OUT Endpoint-Specific Registers. Offsets: - * B00h-CFCh - * - * There will be one set of endpoint registers per logical endpoint - * implemented. - * - * These registers are visible only in Device mode and must not be - * accessed in Host mode, as the results are unknown. - */ -typedef struct dwc_otg_dev_out_ep_regs -{ - /** Device OUT Endpoint Control Register. Offset:B00h + - * (ep_num * 20h) + 00h */ - volatile uint32_t doepctl; - /** Device OUT Endpoint Frame number Register. Offset: - * B00h + (ep_num * 20h) + 04h */ - volatile uint32_t doepfn; - /** Device OUT Endpoint Interrupt Register. Offset:B00h + - * (ep_num * 20h) + 08h */ - volatile uint32_t doepint; - /** Reserved. Offset:B00h + (ep_num * 20h) + 0Ch */ - uint32_t reserved0C; - /** Device OUT Endpoint Transfer Size Register. Offset: - * B00h + (ep_num * 20h) + 10h */ - volatile uint32_t doeptsiz; - /** Device OUT Endpoint DMA Address Register. Offset:B00h - * + (ep_num * 20h) + 14h */ - volatile uint32_t doepdma; - /** Reserved. Offset:B00h + * (ep_num * 20h) + 1Ch */ - uint32_t unused; - /** Device OUT Endpoint DMA Buffer Register. Offset:B00h - * + (ep_num * 20h) + 1Ch */ - uint32_t doepdmab; -} dwc_otg_dev_out_ep_regs_t; - -/** - * This union represents the bit fields in the Device EP Control - * Register. Read the register into the d32 member then - * set/clear the bits using the bit elements. - */ -typedef union depctl_data -{ - /** raw register data */ - uint32_t d32; - /** register bits */ - struct - { - /** Maximum Packet Size - * IN/OUT EPn - * IN/OUT EP0 - 2 bits - * 2'b00: 64 Bytes - * 2'b01: 32 - * 2'b10: 16 - * 2'b11: 8 */ - unsigned mps : 11; -#define DWC_DEP0CTL_MPS_64 0 -#define DWC_DEP0CTL_MPS_32 1 -#define DWC_DEP0CTL_MPS_16 2 -#define DWC_DEP0CTL_MPS_8 3 - - /** Next Endpoint - * IN EPn/IN EP0 - * OUT EPn/OUT EP0 - reserved */ - unsigned nextep : 4; - - /** USB Active Endpoint */ - unsigned usbactep : 1; - - /** Endpoint DPID (INTR/Bulk IN and OUT endpoints) - * This field contains the PID of the packet going to - * be received or transmitted on this endpoint. The - * application should program the PID of the first - * packet going to be received or transmitted on this - * endpoint , after the endpoint is - * activated. Application use the SetD1PID and - * SetD0PID fields of this register to program either - * D0 or D1 PID. - * - * The encoding for this field is - * - 0: D0 - * - 1: D1 - */ - unsigned dpid : 1; - - /** NAK Status */ - unsigned naksts : 1; - - /** Endpoint Type - * 2'b00: Control - * 2'b01: Isochronous - * 2'b10: Bulk - * 2'b11: Interrupt */ - unsigned eptype : 2; - - /** Snoop Mode - * OUT EPn/OUT EP0 - * IN EPn/IN EP0 - reserved */ - unsigned snp : 1; - - /** Stall Handshake */ - unsigned stall : 1; - - /** Tx Fifo Number - * IN EPn/IN EP0 - * OUT EPn/OUT EP0 - reserved */ - unsigned txfnum : 4; - - /** Clear NAK */ - unsigned cnak : 1; - /** Set NAK */ - unsigned snak : 1; - /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints) - * Writing to this field sets the Endpoint DPID (DPID) - * field in this register to DATA0. Set Even - * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints) - * Writing to this field sets the Even/Odd - * (micro)frame (EO_FrNum) field to even (micro) - * frame. - */ - unsigned setd0pid : 1; - /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints) - * Writing to this field sets the Endpoint DPID (DPID) - * field in this register to DATA1 Set Odd - * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints) - * Writing to this field sets the Even/Odd - * (micro)frame (EO_FrNum) field to odd (micro) frame. - */ - unsigned setd1pid : 1; - - /** Endpoint Disable */ - unsigned epdis : 1; - /** Endpoint Enable */ - unsigned epena : 1; - } b; -} depctl_data_t; - -/** - * This union represents the bit fields in the Device EP Transfer - * Size Register. Read the register into the d32 member then - * set/clear the bits using the bit elements. - */ -typedef union deptsiz_data -{ - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - /** Transfer size */ - unsigned xfersize : 19; - /** Packet Count */ - unsigned pktcnt : 10; - /** Multi Count - Periodic IN endpoints */ - unsigned mc : 2; - unsigned reserved : 1; - } b; -} deptsiz_data_t; - -/** - * This union represents the bit fields in the Device EP 0 Transfer - * Size Register. Read the register into the d32 member then - * set/clear the bits using the bit elements. - */ -typedef union deptsiz0_data -{ - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - /** Transfer size */ - unsigned xfersize : 7; - /** Reserved */ - unsigned reserved7_18 : 12; - /** Packet Count */ - unsigned pktcnt : 1; - /** Reserved */ - unsigned reserved20_28 : 9; - /**Setup Packet Count (DOEPTSIZ0 Only) */ - unsigned supcnt : 2; - unsigned reserved31; - } b; -} deptsiz0_data_t; - - -///////////////////////////////////////////////// -// DMA Descriptor Specific Structures -// - -/** Buffer status definitions */ - -#define BS_HOST_READY 0x0 -#define BS_DMA_BUSY 0x1 -#define BS_DMA_DONE 0x2 -#define BS_HOST_BUSY 0x3 - -/** Receive/Transmit status definitions */ - -#define RTS_SUCCESS 0x0 -#define RTS_BUFFLUSH 0x1 -#define RTS_RESERVED 0x2 -#define RTS_BUFERR 0x3 - - -/** - * This union represents the bit fields in the DMA Descriptor - * status quadlet. Read the quadlet into the d32 member then - * set/clear the bits using the bit, b_iso_out and - * b_iso_in elements. - */ -typedef union desc_sts_data -{ - /** raw register data */ - uint32_t d32; - /** quadlet bits */ - struct { - /** Received number of bytes */ - unsigned bytes : 16; - - unsigned reserved16_22 : 7; - /** Multiple Transfer - only for OUT EPs */ - unsigned mtrf : 1; - /** Setup Packet received - only for OUT EPs */ - unsigned sr : 1; - /** Interrupt On Complete */ - unsigned ioc : 1; - /** Short Packet */ - unsigned sp : 1; - /** Last */ - unsigned l : 1; - /** Receive Status */ - unsigned sts : 2; - /** Buffer Status */ - unsigned bs : 2; - } b; - -#ifdef DWC_EN_ISOC - /** iso out quadlet bits */ - struct { - /** Received number of bytes */ - unsigned rxbytes : 11; - - unsigned reserved11 : 1; - /** Frame Number */ - unsigned framenum : 11; - /** Received ISO Data PID */ - unsigned pid : 2; - /** Interrupt On Complete */ - unsigned ioc : 1; - /** Short Packet */ - unsigned sp : 1; - /** Last */ - unsigned l : 1; - /** Receive Status */ - unsigned rxsts : 2; - /** Buffer Status */ - unsigned bs : 2; - } b_iso_out; - - /** iso in quadlet bits */ - struct { - /** Transmited number of bytes */ - unsigned txbytes : 12; - /** Frame Number */ - unsigned framenum : 11; - /** Transmited ISO Data PID */ - unsigned pid : 2; - /** Interrupt On Complete */ - unsigned ioc : 1; - /** Short Packet */ - unsigned sp : 1; - /** Last */ - unsigned l : 1; - /** Transmit Status */ - unsigned txsts : 2; - /** Buffer Status */ - unsigned bs : 2; - } b_iso_in; -#endif //DWC_EN_ISOC -} desc_sts_data_t; - -/** - * DMA Descriptor structure - * - * DMA Descriptor structure contains two quadlets: - * Status quadlet and Data buffer pointer. - */ -typedef struct dwc_otg_dma_desc -{ - /** DMA Descriptor status quadlet */ - desc_sts_data_t status; - /** DMA Descriptor data buffer pointer */ - dma_addr_t buf; -} dwc_otg_dma_desc_t; - -/** - * The dwc_otg_dev_if structure contains information needed to manage - * the DWC_otg controller acting in device mode. It represents the - * programming view of the device-specific aspects of the controller. - */ -typedef struct dwc_otg_dev_if -{ - /** Pointer to device Global registers. - * Device Global Registers starting at offset 800h - */ - dwc_otg_device_global_regs_t *dev_global_regs; -#define DWC_DEV_GLOBAL_REG_OFFSET 0x800 - - /** - * Device Logical IN Endpoint-Specific Registers 900h-AFCh - */ - dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS]; -#define DWC_DEV_IN_EP_REG_OFFSET 0x900 -#define DWC_EP_REG_OFFSET 0x20 - - /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */ - dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS]; -#define DWC_DEV_OUT_EP_REG_OFFSET 0xB00 - - /* Device configuration information*/ - uint8_t speed; /**< Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS */ - uint8_t num_in_eps; /**< Number # of Tx EP range: 0-15 exept ep0 */ - uint8_t num_out_eps; /**< Number # of Rx EP range: 0-15 exept ep 0*/ - - /** Size of periodic FIFOs (Bytes) */ - uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS]; - - /** Size of Tx FIFOs (Bytes) */ - uint16_t tx_fifo_size[MAX_TX_FIFOS]; - - /** Thresholding enable flags and length varaiables **/ - uint16_t rx_thr_en; - uint16_t iso_tx_thr_en; - uint16_t non_iso_tx_thr_en; - - uint16_t rx_thr_length; - uint16_t tx_thr_length; - - /** - * Pointers to the DMA Descriptors for EP0 Control - * transfers (virtual and physical) - */ - - /** 2 descriptors for SETUP packets */ - uint32_t dma_setup_desc_addr[2]; - dwc_otg_dma_desc_t* setup_desc_addr[2]; - - /** Pointer to Descriptor with latest SETUP packet */ - dwc_otg_dma_desc_t* psetup; - - /** Index of current SETUP handler descriptor */ - uint32_t setup_desc_index; - - /** Descriptor for Data In or Status In phases */ - uint32_t dma_in_desc_addr; - dwc_otg_dma_desc_t* in_desc_addr;; - - /** Descriptor for Data Out or Status Out phases */ - uint32_t dma_out_desc_addr; - dwc_otg_dma_desc_t* out_desc_addr; - -} dwc_otg_dev_if_t; - - - - -///////////////////////////////////////////////// -// Host Mode Register Structures -// -/** - * The Host Global Registers structure defines the size and relative - * field offsets for the Host Mode Global Registers. Host Global - * Registers offsets 400h-7FFh. -*/ -typedef struct dwc_otg_host_global_regs -{ - /** Host Configuration Register. Offset: 400h */ - volatile uint32_t hcfg; - /** Host Frame Interval Register. Offset: 404h */ - volatile uint32_t hfir; - /** Host Frame Number / Frame Remaining Register. Offset: 408h */ - volatile uint32_t hfnum; - /** Reserved. Offset: 40Ch */ - uint32_t reserved40C; - /** Host Periodic Transmit FIFO/ Queue Status Register. Offset: 410h */ - volatile uint32_t hptxsts; - /** Host All Channels Interrupt Register. Offset: 414h */ - volatile uint32_t haint; - /** Host All Channels Interrupt Mask Register. Offset: 418h */ - volatile uint32_t haintmsk; -} dwc_otg_host_global_regs_t; - -/** - * This union represents the bit fields in the Host Configuration Register. - * Read the register into the d32 member then set/clear the bits using - * the bit elements. Write the d32 member to the hcfg register. - */ -typedef union hcfg_data -{ - /** raw register data */ - uint32_t d32; - - /** register bits */ - struct - { - /** FS/LS Phy Clock Select */ - unsigned fslspclksel : 2; -#define DWC_HCFG_30_60_MHZ 0 -#define DWC_HCFG_48_MHZ 1 -#define DWC_HCFG_6_MHZ 2 - - /** FS/LS Only Support */ - unsigned fslssupp : 1; - } b; -} hcfg_data_t; - -/** - * This union represents the bit fields in the Host Frame Remaing/Number - * Register. - */ -typedef union hfir_data -{ - /** raw register data */ - uint32_t d32; - - /** register bits */ - struct - { - unsigned frint : 16; - unsigned reserved : 16; - } b; -} hfir_data_t; - -/** - * This union represents the bit fields in the Host Frame Remaing/Number - * Register. - */ -typedef union hfnum_data -{ - /** raw register data */ - uint32_t d32; - - /** register bits */ - struct - { - unsigned frnum : 16; -#define DWC_HFNUM_MAX_FRNUM 0x3FFF - unsigned frrem : 16; - } b; -} hfnum_data_t; - -typedef union hptxsts_data -{ - /** raw register data */ - uint32_t d32; - - /** register bits */ - struct - { - unsigned ptxfspcavail : 16; - unsigned ptxqspcavail : 8; - /** Top of the Periodic Transmit Request Queue - * - bit 24 - Terminate (last entry for the selected channel) - * - bits 26:25 - Token Type - * - 2'b00 - Zero length - * - 2'b01 - Ping - * - 2'b10 - Disable - * - bits 30:27 - Channel Number - * - bit 31 - Odd/even microframe - */ - unsigned ptxqtop_terminate : 1; - unsigned ptxqtop_token : 2; - unsigned ptxqtop_chnum : 4; - unsigned ptxqtop_odd : 1; - } b; -} hptxsts_data_t; - -/** - * This union represents the bit fields in the Host Port Control and Status - * Register. Read the register into the d32 member then set/clear the - * bits using the bit elements. Write the d32 member to the - * hprt0 register. - */ -typedef union hprt0_data -{ - /** raw register data */ - uint32_t d32; - /** register bits */ - struct - { - unsigned prtconnsts : 1; - unsigned prtconndet : 1; - unsigned prtena : 1; - unsigned prtenchng : 1; - unsigned prtovrcurract : 1; - unsigned prtovrcurrchng : 1; - unsigned prtres : 1; - unsigned prtsusp : 1; - unsigned prtrst : 1; - unsigned reserved9 : 1; - unsigned prtlnsts : 2; - unsigned prtpwr : 1; - unsigned prttstctl : 4; - unsigned prtspd : 2; -#define DWC_HPRT0_PRTSPD_HIGH_SPEED 0 -#define DWC_HPRT0_PRTSPD_FULL_SPEED 1 -#define DWC_HPRT0_PRTSPD_LOW_SPEED 2 - unsigned reserved19_31 : 13; - } b; -} hprt0_data_t; - -/** - * This union represents the bit fields in the Host All Interrupt - * Register. - */ -typedef union haint_data -{ - /** raw register data */ - uint32_t d32; - /** register bits */ - struct - { - unsigned ch0 : 1; - unsigned ch1 : 1; - unsigned ch2 : 1; - unsigned ch3 : 1; - unsigned ch4 : 1; - unsigned ch5 : 1; - unsigned ch6 : 1; - unsigned ch7 : 1; - unsigned ch8 : 1; - unsigned ch9 : 1; - unsigned ch10 : 1; - unsigned ch11 : 1; - unsigned ch12 : 1; - unsigned ch13 : 1; - unsigned ch14 : 1; - unsigned ch15 : 1; - unsigned reserved : 16; - } b; - - struct - { - unsigned chint : 16; - unsigned reserved : 16; - } b2; -} haint_data_t; - -/** - * This union represents the bit fields in the Host All Interrupt - * Register. - */ -typedef union haintmsk_data -{ - /** raw register data */ - uint32_t d32; - /** register bits */ - struct - { - unsigned ch0 : 1; - unsigned ch1 : 1; - unsigned ch2 : 1; - unsigned ch3 : 1; - unsigned ch4 : 1; - unsigned ch5 : 1; - unsigned ch6 : 1; - unsigned ch7 : 1; - unsigned ch8 : 1; - unsigned ch9 : 1; - unsigned ch10 : 1; - unsigned ch11 : 1; - unsigned ch12 : 1; - unsigned ch13 : 1; - unsigned ch14 : 1; - unsigned ch15 : 1; - unsigned reserved : 16; - } b; - - struct - { - unsigned chint : 16; - unsigned reserved : 16; - } b2; -} haintmsk_data_t; - -/** - * Host Channel Specific Registers. 500h-5FCh - */ -typedef struct dwc_otg_hc_regs -{ - /** Host Channel 0 Characteristic Register. Offset: 500h + (chan_num * 20h) + 00h */ - volatile uint32_t hcchar; - /** Host Channel 0 Split Control Register. Offset: 500h + (chan_num * 20h) + 04h */ - volatile uint32_t hcsplt; - /** Host Channel 0 Interrupt Register. Offset: 500h + (chan_num * 20h) + 08h */ - volatile uint32_t hcint; - /** Host Channel 0 Interrupt Mask Register. Offset: 500h + (chan_num * 20h) + 0Ch */ - volatile uint32_t hcintmsk; - /** Host Channel 0 Transfer Size Register. Offset: 500h + (chan_num * 20h) + 10h */ - volatile uint32_t hctsiz; - /** Host Channel 0 DMA Address Register. Offset: 500h + (chan_num * 20h) + 14h */ - volatile uint32_t hcdma; - /** Reserved. Offset: 500h + (chan_num * 20h) + 18h - 500h + (chan_num * 20h) + 1Ch */ - uint32_t reserved[2]; -} dwc_otg_hc_regs_t; - -/** - * This union represents the bit fields in the Host Channel Characteristics - * Register. Read the register into the d32 member then set/clear the - * bits using the bit elements. Write the d32 member to the - * hcchar register. - */ -typedef union hcchar_data -{ - /** raw register data */ - uint32_t d32; - - /** register bits */ - struct - { - /** Maximum packet size in bytes */ - unsigned mps : 11; - - /** Endpoint number */ - unsigned epnum : 4; - - /** 0: OUT, 1: IN */ - unsigned epdir : 1; - - unsigned reserved : 1; - - /** 0: Full/high speed device, 1: Low speed device */ - unsigned lspddev : 1; - - /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */ - unsigned eptype : 2; - - /** Packets per frame for periodic transfers. 0 is reserved. */ - unsigned multicnt : 2; - - /** Device address */ - unsigned devaddr : 7; - - /** - * Frame to transmit periodic transaction. - * 0: even, 1: odd - */ - unsigned oddfrm : 1; - - /** Channel disable */ - unsigned chdis : 1; - - /** Channel enable */ - unsigned chen : 1; - } b; -} hcchar_data_t; - -typedef union hcsplt_data -{ - /** raw register data */ - uint32_t d32; - - /** register bits */ - struct - { - /** Port Address */ - unsigned prtaddr : 7; - - /** Hub Address */ - unsigned hubaddr : 7; - - /** Transaction Position */ - unsigned xactpos : 2; -#define DWC_HCSPLIT_XACTPOS_MID 0 -#define DWC_HCSPLIT_XACTPOS_END 1 -#define DWC_HCSPLIT_XACTPOS_BEGIN 2 -#define DWC_HCSPLIT_XACTPOS_ALL 3 - - /** Do Complete Split */ - unsigned compsplt : 1; - - /** Reserved */ - unsigned reserved : 14; - - /** Split Enble */ - unsigned spltena : 1; - } b; -} hcsplt_data_t; - - -/** - * This union represents the bit fields in the Host All Interrupt - * Register. - */ -typedef union hcint_data -{ - /** raw register data */ - uint32_t d32; - /** register bits */ - struct - { - /** Transfer Complete */ - unsigned xfercomp : 1; - /** Channel Halted */ - unsigned chhltd : 1; - /** AHB Error */ - unsigned ahberr : 1; - /** STALL Response Received */ - unsigned stall : 1; - /** NAK Response Received */ - unsigned nak : 1; - /** ACK Response Received */ - unsigned ack : 1; - /** NYET Response Received */ - unsigned nyet : 1; - /** Transaction Err */ - unsigned xacterr : 1; - /** Babble Error */ - unsigned bblerr : 1; - /** Frame Overrun */ - unsigned frmovrun : 1; - /** Data Toggle Error */ - unsigned datatglerr : 1; - /** Reserved */ - unsigned reserved : 21; - } b; -} hcint_data_t; - -/** - * This union represents the bit fields in the Host Channel Transfer Size - * Register. Read the register into the d32 member then set/clear the - * bits using the bit elements. Write the d32 member to the - * hcchar register. - */ -typedef union hctsiz_data -{ - /** raw register data */ - uint32_t d32; - - /** register bits */ - struct - { - /** Total transfer size in bytes */ - unsigned xfersize : 19; - - /** Data packets to transfer */ - unsigned pktcnt : 10; - - /** - * Packet ID for next data packet - * 0: DATA0 - * 1: DATA2 - * 2: DATA1 - * 3: MDATA (non-Control), SETUP (Control) - */ - unsigned pid : 2; -#define DWC_HCTSIZ_DATA0 0 -#define DWC_HCTSIZ_DATA1 2 -#define DWC_HCTSIZ_DATA2 1 -#define DWC_HCTSIZ_MDATA 3 -#define DWC_HCTSIZ_SETUP 3 - - /** Do PING protocol when 1 */ - unsigned dopng : 1; - } b; -} hctsiz_data_t; - -/** - * This union represents the bit fields in the Host Channel Interrupt Mask - * Register. Read the register into the d32 member then set/clear the - * bits using the bit elements. Write the d32 member to the - * hcintmsk register. - */ -typedef union hcintmsk_data -{ - /** raw register data */ - uint32_t d32; - - /** register bits */ - struct - { - unsigned xfercompl : 1; - unsigned chhltd : 1; - unsigned ahberr : 1; - unsigned stall : 1; - unsigned nak : 1; - unsigned ack : 1; - unsigned nyet : 1; - unsigned xacterr : 1; - unsigned bblerr : 1; - unsigned frmovrun : 1; - unsigned datatglerr : 1; - unsigned reserved : 21; - } b; -} hcintmsk_data_t; - -/** OTG Host Interface Structure. - * - * The OTG Host Interface Structure structure contains information - * needed to manage the DWC_otg controller acting in host mode. It - * represents the programming view of the host-specific aspects of the - * controller. - */ -typedef struct dwc_otg_host_if -{ - /** Host Global Registers starting at offset 400h.*/ - dwc_otg_host_global_regs_t *host_global_regs; -#define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400 - - /** Host Port 0 Control and Status Register */ - volatile uint32_t *hprt0; -#define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440 - - - /** Host Channel Specific Registers at offsets 500h-5FCh. */ - dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS]; -#define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500 -#define DWC_OTG_CHAN_REGS_OFFSET 0x20 - - - /* Host configuration information */ - /** Number of Host Channels (range: 1-16) */ - uint8_t num_host_channels; - /** Periodic EPs supported (0: no, 1: yes) */ - uint8_t perio_eps_supported; - /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */ - uint16_t perio_tx_fifo_size; - -} dwc_otg_host_if_t; - - -/** - * This union represents the bit fields in the Power and Clock Gating Control - * Register. Read the register into the d32 member then set/clear the - * bits using the bit elements. - */ -typedef union pcgcctl_data -{ - /** raw register data */ - uint32_t d32; - - /** register bits */ - struct - { - /** Stop Pclk */ - unsigned stoppclk : 1; - /** Gate Hclk */ - unsigned gatehclk : 1; - /** Power Clamp */ - unsigned pwrclmp : 1; - /** Reset Power Down Modules */ - unsigned rstpdwnmodule : 1; - /** PHY Suspended */ - unsigned physuspended : 1; - - unsigned reserved : 27; - } b; -} pcgcctl_data_t; - - -#endif diff --git a/target/linux/ramips/files/drivers/usb/dwc_otg/linux/dwc_otg_plat.h b/target/linux/ramips/files/drivers/usb/dwc_otg/linux/dwc_otg_plat.h deleted file mode 100644 index 618151b42a..0000000000 --- a/target/linux/ramips/files/drivers/usb/dwc_otg/linux/dwc_otg_plat.h +++ /dev/null @@ -1,260 +0,0 @@ -/* ========================================================================== - * $File: //dwh/usb_iip/dev/software/otg/linux/platform/dwc_otg_plat.h $ - * $Revision: 1.2 $ - * $Date: 2008-11-21 05:39:16 $ - * $Change: 1064915 $ - * - * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, - * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless - * otherwise expressly agreed to in writing between Synopsys and you. - * - * The Software IS NOT an item of Licensed Software or Licensed Product under - * any End User Software License Agreement or Agreement for Licensed Product - * with Synopsys or any supplement thereto. You are permitted to use and - * redistribute this Software in source and binary forms, with or without - * modification, provided that redistributions of source code must retain this - * notice. You may not view, use, disclose, copy or distribute this file or - * any information contained herein except pursuant to this license grant from - * Synopsys. If you do not agree with this notice, including the disclaimer - * below, then you are not authorized to use the Software. - * - * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * ========================================================================== */ - -#if !defined(__DWC_OTG_PLAT_H__) -#define __DWC_OTG_PLAT_H__ - -#include -#include -#include -#include -#include - -/** - * @file - * - * This file contains the Platform Specific constants, interfaces - * (functions and macros) for Linux. - * - */ -//#if !defined(__LINUX_ARM_ARCH__) -//#error "The contents of this file is Linux specific!!!" -//#endif - -/** - * Reads the content of a register. - * - * @param reg address of register to read. - * @return contents of the register. - * - - * Usage:
- * uint32_t dev_ctl = dwc_read_reg32(&dev_regs->dctl); - */ -static __inline__ uint32_t dwc_read_reg32( volatile uint32_t *reg) -{ - return readl(reg); -}; - -/** - * Writes a register with a 32 bit value. - * - * @param reg address of register to read. - * @param value to write to _reg. - * - * Usage:
- * dwc_write_reg32(&dev_regs->dctl, 0); - */ -static __inline__ void dwc_write_reg32( volatile uint32_t *reg, const uint32_t value) -{ - writel( value, reg ); -}; - -/** - * This function modifies bit values in a register. Using the - * algorithm: (reg_contents & ~clear_mask) | set_mask. - * - * @param reg address of register to read. - * @param clear_mask bit mask to be cleared. - * @param set_mask bit mask to be set. - * - * Usage:
- * // Clear the SOF Interrupt Mask bit and
- * // set the OTG Interrupt mask bit, leaving all others as they were. - * dwc_modify_reg32(&dev_regs->gintmsk, DWC_SOF_INT, DWC_OTG_INT); - */ -static __inline__ - void dwc_modify_reg32( volatile uint32_t *reg, const uint32_t clear_mask, const uint32_t set_mask) -{ - writel( (readl(reg) & ~clear_mask) | set_mask, reg ); -}; - - -/** - * Wrapper for the OS micro-second delay function. - * @param[in] usecs Microseconds of delay - */ -static __inline__ void UDELAY( const uint32_t usecs ) -{ - udelay( usecs ); -} - -/** - * Wrapper for the OS milli-second delay function. - * @param[in] msecs milliseconds of delay - */ -static __inline__ void MDELAY( const uint32_t msecs ) -{ - mdelay( msecs ); -} - -/** - * Wrapper for the Linux spin_lock. On the ARM (Integrator) - * spin_lock() is a nop. - * - * @param lock Pointer to the spinlock. - */ -static __inline__ void SPIN_LOCK( spinlock_t *lock ) -{ - spin_lock(lock); -} - -/** - * Wrapper for the Linux spin_unlock. On the ARM (Integrator) - * spin_lock() is a nop. - * - * @param lock Pointer to the spinlock. - */ -static __inline__ void SPIN_UNLOCK( spinlock_t *lock ) -{ - spin_unlock(lock); -} - -/** - * Wrapper (macro) for the Linux spin_lock_irqsave. On the ARM - * (Integrator) spin_lock() is a nop. - * - * @param l Pointer to the spinlock. - * @param f unsigned long for irq flags storage. - */ -#define SPIN_LOCK_IRQSAVE( l, f ) spin_lock_irqsave(l,f); - -/** - * Wrapper (macro) for the Linux spin_unlock_irqrestore. On the ARM - * (Integrator) spin_lock() is a nop. - * - * @param l Pointer to the spinlock. - * @param f unsigned long for irq flags storage. - */ -#define SPIN_UNLOCK_IRQRESTORE( l,f ) spin_unlock_irqrestore(l,f); - -/* - * Debugging support vanishes in non-debug builds. - */ - - -/** - * The Debug Level bit-mask variable. - */ -extern uint32_t g_dbg_lvl; -/** - * Set the Debug Level variable. - */ -static inline uint32_t SET_DEBUG_LEVEL( const uint32_t new ) -{ - uint32_t old = g_dbg_lvl; - g_dbg_lvl = new; - return old; -} - -/** When debug level has the DBG_CIL bit set, display CIL Debug messages. */ -#define DBG_CIL (0x2) -/** When debug level has the DBG_CILV bit set, display CIL Verbose debug - * messages */ -#define DBG_CILV (0x20) -/** When debug level has the DBG_PCD bit set, display PCD (Device) debug - * messages */ -#define DBG_PCD (0x4) -/** When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug - * messages */ -#define DBG_PCDV (0x40) -/** When debug level has the DBG_HCD bit set, display Host debug messages */ -#define DBG_HCD (0x8) -/** When debug level has the DBG_HCDV bit set, display Verbose Host debug - * messages */ -#define DBG_HCDV (0x80) -/** When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host - * mode. */ -#define DBG_HCD_URB (0x800) - -/** When debug level has any bit set, display debug messages */ -#define DBG_ANY (0xFF) - -/** All debug messages off */ -#define DBG_OFF 0 - -/** Prefix string for DWC_DEBUG print macros. */ -#define USB_DWC "dwc_otg: " - -/** - * Print a debug message when the Global debug level variable contains - * the bit defined in lvl. - * - * @param[in] lvl - Debug level, use one of the DBG_ constants above. - * @param[in] x - like printf - * - * Example:

- * - * DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr); - * - *
- * results in:
- * - * usb-DWC_otg: dwc_otg_cil_init(ca867000) - * - */ -#ifdef DEBUG - -# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)printk( KERN_DEBUG USB_DWC x ); }while(0) -# define DWC_DEBUGP(x...) DWC_DEBUGPL(DBG_ANY, x ) - -# define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl) - -#else - -# define DWC_DEBUGPL(lvl, x...) do{}while(0) -# define DWC_DEBUGP(x...) - -# define CHK_DEBUG_LEVEL(level) (0) - -#endif /*DEBUG*/ - -/** - * Print an Error message. - */ -#define DWC_ERROR(x...) printk( KERN_ERR USB_DWC x ) -/** - * Print a Warning message. - */ -#define DWC_WARN(x...) printk( KERN_WARNING USB_DWC x ) -/** - * Print a notice (normal but significant message). - */ -#define DWC_NOTICE(x...) printk( KERN_NOTICE USB_DWC x ) -/** - * Basic message printing. - */ -#define DWC_PRINT(x...) printk( KERN_INFO USB_DWC x ) - -#endif - diff --git a/target/linux/ramips/files/drivers/watchdog/ramips_wdt.c b/target/linux/ramips/files/drivers/watchdog/ramips_wdt.c deleted file mode 100644 index fa7e9e85ef..0000000000 --- a/target/linux/ramips/files/drivers/watchdog/ramips_wdt.c +++ /dev/null @@ -1,355 +0,0 @@ -/* - * Ralink RT288X/RT305X built-in hardware watchdog timer - * - * Copyright (C) 2011 Gabor Juhos - * - * This driver was based on: drivers/watchdog/ixp4xx_wdt.c - * Author: Deepak Saxena - * Copyright 2004 (c) MontaVista, Software, Inc. - * - * which again was based on sa1100 driver, - * Copyright (C) 2000 Oleg Drokin - * - * parts of the driver are based on Ralink's 2.6.21 BSP - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define DRIVER_NAME "ramips-wdt" - -#define RAMIPS_WDT_TIMEOUT 0 /* seconds */ -#define RAMIPS_WDT_PRESCALE 65536 - -#define TIMER_REG_TMRSTAT 0x00 -#define TIMER_REG_TMR1LOAD 0x20 -#define TIMER_REG_TMR1CTL 0x28 - -#define TMRSTAT_TMR1RST BIT(5) - -#define TMR1CTL_ENABLE BIT(7) -#define TMR1CTL_MODE_SHIFT 4 -#define TMR1CTL_MODE_MASK 0x3 -#define TMR1CTL_MODE_FREE_RUNNING 0x0 -#define TMR1CTL_MODE_PERIODIC 0x1 -#define TMR1CTL_MODE_TIMEOUT 0x2 -#define TMR1CTL_MODE_WDT 0x3 -#define TMR1CTL_PRESCALE_MASK 0xf -#define TMR1CTL_PRESCALE_65536 0xf - -static int nowayout = WATCHDOG_NOWAYOUT; -module_param(nowayout, int, 0); -MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started " - "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); - -static int ramips_wdt_timeout = RAMIPS_WDT_TIMEOUT; -module_param_named(timeout, ramips_wdt_timeout, int, 0); -MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds, 0 means use maximum " - "(default=" __MODULE_STRING(RAMIPS_WDT_TIMEOUT) "s)"); - -static unsigned long ramips_wdt_flags; - -#define WDT_FLAGS_BUSY 0 -#define WDT_FLAGS_EXPECT_CLOSE 1 - -static struct clk *ramips_wdt_clk; -static unsigned long ramips_wdt_freq; -static int ramips_wdt_max_timeout; -static void __iomem *ramips_wdt_base; - -static inline void ramips_wdt_wr(unsigned reg, u32 val) -{ - __raw_writel(val, ramips_wdt_base + reg); -} - -static inline u32 ramips_wdt_rr(unsigned reg) -{ - return __raw_readl(ramips_wdt_base + reg); -} - -static inline void ramips_wdt_keepalive(void) -{ - ramips_wdt_wr(TIMER_REG_TMR1LOAD, ramips_wdt_timeout * ramips_wdt_freq); -} - -static inline void ramips_wdt_enable(void) -{ - u32 t; - - ramips_wdt_keepalive(); - - t = ramips_wdt_rr(TIMER_REG_TMR1CTL); - t |= TMR1CTL_ENABLE; - ramips_wdt_wr(TIMER_REG_TMR1CTL, t); -} - -static inline void ramips_wdt_disable(void) -{ - u32 t; - - ramips_wdt_keepalive(); - - t = ramips_wdt_rr(TIMER_REG_TMR1CTL); - t &= ~TMR1CTL_ENABLE; - ramips_wdt_wr(TIMER_REG_TMR1CTL, t); -} - -static int ramips_wdt_set_timeout(int val) -{ - if (val < 1 || val > ramips_wdt_max_timeout) { - pr_warn(DRIVER_NAME - ": timeout value %d must be 0 < timeout <= %d, using %d\n", - val, ramips_wdt_max_timeout, ramips_wdt_timeout); - return -EINVAL; - } - - ramips_wdt_timeout = val; - ramips_wdt_keepalive(); - - return 0; -} - -static int ramips_wdt_open(struct inode *inode, struct file *file) -{ - u32 t; - - if (test_and_set_bit(WDT_FLAGS_BUSY, &ramips_wdt_flags)) - return -EBUSY; - - clear_bit(WDT_FLAGS_EXPECT_CLOSE, &ramips_wdt_flags); - - t = ramips_wdt_rr(TIMER_REG_TMR1CTL); - t &= ~(TMR1CTL_MODE_MASK << TMR1CTL_MODE_SHIFT | - TMR1CTL_PRESCALE_MASK); - t |= (TMR1CTL_MODE_WDT << TMR1CTL_MODE_SHIFT | - TMR1CTL_PRESCALE_65536); - ramips_wdt_wr(TIMER_REG_TMR1CTL, t); - - ramips_wdt_enable(); - - return nonseekable_open(inode, file); -} - -static int ramips_wdt_release(struct inode *inode, struct file *file) -{ - if (test_bit(WDT_FLAGS_EXPECT_CLOSE, &ramips_wdt_flags)) - ramips_wdt_disable(); - else { - pr_crit(DRIVER_NAME ": device closed unexpectedly, " - "watchdog timer will not stop!\n"); - ramips_wdt_keepalive(); - } - - clear_bit(WDT_FLAGS_BUSY, &ramips_wdt_flags); - clear_bit(WDT_FLAGS_EXPECT_CLOSE, &ramips_wdt_flags); - - return 0; -} - -static ssize_t ramips_wdt_write(struct file *file, const char *data, - size_t len, loff_t *ppos) -{ - if (len) { - if (!nowayout) { - size_t i; - - clear_bit(WDT_FLAGS_EXPECT_CLOSE, &ramips_wdt_flags); - - for (i = 0; i != len; i++) { - char c; - - if (get_user(c, data + i)) - return -EFAULT; - - if (c == 'V') - set_bit(WDT_FLAGS_EXPECT_CLOSE, - &ramips_wdt_flags); - } - } - - ramips_wdt_keepalive(); - } - - return len; -} - -static const struct watchdog_info ramips_wdt_info = { - .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | - WDIOF_MAGICCLOSE, - .firmware_version = 0, - .identity = "RAMIPS watchdog", -}; - -static long ramips_wdt_ioctl(struct file *file, unsigned int cmd, - unsigned long arg) -{ - void __user *argp = (void __user *)arg; - int __user *p = argp; - int err; - int t; - - switch (cmd) { - case WDIOC_GETSUPPORT: - err = copy_to_user(argp, &ramips_wdt_info, - sizeof(ramips_wdt_info)) ? -EFAULT : 0; - break; - - case WDIOC_GETSTATUS: - err = put_user(0, p); - break; - - case WDIOC_KEEPALIVE: - ramips_wdt_keepalive(); - err = 0; - break; - - case WDIOC_SETTIMEOUT: - err = get_user(t, p); - if (err) - break; - - err = ramips_wdt_set_timeout(t); - if (err) - break; - - /* fallthrough */ - case WDIOC_GETTIMEOUT: - err = put_user(ramips_wdt_timeout, p); - break; - - default: - err = -ENOTTY; - break; - } - - return err; -} - -static const struct file_operations ramips_wdt_fops = { - .owner = THIS_MODULE, - .llseek = no_llseek, - .write = ramips_wdt_write, - .unlocked_ioctl = ramips_wdt_ioctl, - .open = ramips_wdt_open, - .release = ramips_wdt_release, -}; - -static struct miscdevice ramips_wdt_miscdev = { - .minor = WATCHDOG_MINOR, - .name = "watchdog", - .fops = &ramips_wdt_fops, -}; - -static int ramips_wdt_probe(struct platform_device *pdev) -{ - struct resource *res; - int err; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(&pdev->dev, "no memory resource found\n"); - return -EINVAL; - } - - ramips_wdt_base = ioremap(res->start, resource_size(res)); - if (!ramips_wdt_base) - return -ENOMEM; - - ramips_wdt_clk = clk_get(&pdev->dev, "wdt"); - if (IS_ERR(ramips_wdt_clk)) { - err = PTR_ERR(ramips_wdt_clk); - goto err_unmap; - } - - err = clk_enable(ramips_wdt_clk); - if (err) - goto err_clk_put; - - ramips_wdt_freq = clk_get_rate(ramips_wdt_clk) / RAMIPS_WDT_PRESCALE; - if (!ramips_wdt_freq) { - err = -EINVAL; - goto err_clk_disable; - } - - ramips_wdt_max_timeout = (0xfffful / ramips_wdt_freq); - if (ramips_wdt_timeout < 1 || - ramips_wdt_timeout > ramips_wdt_max_timeout) { - ramips_wdt_timeout = ramips_wdt_max_timeout; - dev_info(&pdev->dev, - "timeout value must be 0 < timeout <= %d, using %d\n", - ramips_wdt_max_timeout, ramips_wdt_timeout); - } - - err = misc_register(&ramips_wdt_miscdev); - if (err) { - dev_err(&pdev->dev, - "unable to register misc device, err=%d\n", err); - goto err_clk_disable; - } - - return 0; - -err_clk_disable: - clk_disable(ramips_wdt_clk); -err_clk_put: - clk_put(ramips_wdt_clk); -err_unmap: - iounmap(ramips_wdt_base); - return err; -} - -static int ramips_wdt_remove(struct platform_device *pdev) -{ - misc_deregister(&ramips_wdt_miscdev); - clk_disable(ramips_wdt_clk); - clk_put(ramips_wdt_clk); - iounmap(ramips_wdt_base); - return 0; -} - -static void ramips_wdt_shutdown(struct platform_device *pdev) -{ - ramips_wdt_disable(); -} - -static struct platform_driver ramips_wdt_driver = { - .remove = ramips_wdt_remove, - .shutdown = ramips_wdt_shutdown, - .driver = { - .name = DRIVER_NAME, - .owner = THIS_MODULE, - }, -}; - -static int __init ramips_wdt_init(void) -{ - return platform_driver_probe(&ramips_wdt_driver, ramips_wdt_probe); -} -module_init(ramips_wdt_init); - -static void __exit ramips_wdt_exit(void) -{ - platform_driver_unregister(&ramips_wdt_driver); -} -module_exit(ramips_wdt_exit); - -MODULE_DESCRIPTION("Ralink RT288X/RT305X hardware watchdog driver"); -MODULE_AUTHOR("Gabor Juhos