From: Lars-Peter Clausen <lars@metafoo.de>
Date: Sun, 11 Apr 2010 16:24:06 +0000 (+0000)
Subject: time.c: Timer enable registers are only 8bit width.
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=d1031cd8610e12842b551431e694c7bceebbab6c;p=openwrt%2Fstaging%2Fstintel.git

time.c: Timer enable registers are only 8bit width.

SVN-Revision: 20796
---

diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/time.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/time.c
index d9c5eba61c..77fc2012ed 100644
--- a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/time.c
+++ b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/time.c
@@ -98,12 +98,12 @@ static void jz4740_init_timer(void)
 static void jz4740_timer_enable(unsigned int timer)
 {
 	writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
-	writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
+	writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
 }
 
 static void jz4740_timer_disable(unsigned int timer)
 {
-	writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
+	writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
 	writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
 }