From: Mantas Pucka Date: Mon, 12 Feb 2024 13:05:25 +0000 (+0200) Subject: qca-ssdk: support selecting PCS channel for PORT3 on IPQ6018 X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=d08d53346b993431e309797d5e6de8da20147c3c;p=openwrt%2Fstaging%2Fnbd.git qca-ssdk: support selecting PCS channel for PORT3 on IPQ6018 When QCA8072 is used in PSGMII mode with IPQ6018, PCS used for second PHY port would overlap with one used by SGMII+ port. SoC has register to select different PCS in such case. Original code used PHY_ID for this decision, which also had other issues, but is no longer viable since we moved to upstream QCA807x driver. Introduce DT property port3_pcs_channel to allow describing this in DT. Default value is <2>, and for some QCA8072 designs <4> would be needed. Signed-off-by: Mantas Pucka --- diff --git a/package/kernel/qca-ssdk/patches/102-qca-ssdk-support-selecting-PCS-channel-for-PORT3-on-.patch b/package/kernel/qca-ssdk/patches/102-qca-ssdk-support-selecting-PCS-channel-for-PORT3-on-.patch new file mode 100644 index 0000000000..a8863bf463 --- /dev/null +++ b/package/kernel/qca-ssdk/patches/102-qca-ssdk-support-selecting-PCS-channel-for-PORT3-on-.patch @@ -0,0 +1,146 @@ +From 0116bb7359bd99c09bcad1b2051652cd1a04be3f Mon Sep 17 00:00:00 2001 +From: Mantas Pucka +Date: Mon, 12 Feb 2024 14:23:04 +0200 +Subject: [PATCH] qca-ssdk: support selecting PCS channel for PORT3 on IPQ6018 + +When QCA8072 is used in PSGMII mode with IPQ6018, PCS used for second +PHY port would overlap with one used by SGMII+ port. SoC has register +to select different PCS in such case. + +Original code used PHY_ID for this decision, which also had other +issues, but is no longer viable since we moved to upstream QCA807x +driver. + +Introduce DT property port3_pcs_channel to allow describing this in DT. +Default value is <2>, and for some QCA8072 designs <4> would be needed. + +Signed-off-by: Mantas Pucka +--- + include/init/ssdk_dts.h | 2 ++ + src/adpt/cppe/adpt_cppe_portctrl.c | 4 ++-- + src/adpt/hppe/adpt_hppe_uniphy.c | 7 +------ + src/init/ssdk_dts.c | 27 +++++++++++++++++++++++++++ + 4 files changed, 32 insertions(+), 8 deletions(-) + +diff --git a/include/init/ssdk_dts.h b/include/init/ssdk_dts.h +index 00fa4c1..210c788 100755 +--- a/include/init/ssdk_dts.h ++++ b/include/init/ssdk_dts.h +@@ -101,6 +101,7 @@ typedef struct + a_uint32_t emu_chip_ver; /*only valid when is_emulation is true*/ + a_uint32_t clk_mode; + a_uint32_t pcie_hw_base; ++ a_uint32_t port3_pcs_channel; + } ssdk_dt_cfg; + + #define SSDK_MAX_NR_ETH 6 +@@ -163,6 +164,7 @@ a_uint32_t ssdk_device_id_get(a_uint32_t index); + struct device_node *ssdk_dts_node_get(a_uint32_t dev_id); + struct clk *ssdk_dts_essclk_get(a_uint32_t dev_id); + struct clk *ssdk_dts_cmnclk_get(a_uint32_t dev_id); ++a_uint32_t ssdk_dts_port3_pcs_channel_get(a_uint32_t dev_id); + + int ssdk_switch_device_num_init(void); + void ssdk_switch_device_num_exit(void); +diff --git a/src/adpt/cppe/adpt_cppe_portctrl.c b/src/adpt/cppe/adpt_cppe_portctrl.c +index 00d0404..6b32f79 100755 +--- a/src/adpt/cppe/adpt_cppe_portctrl.c ++++ b/src/adpt/cppe/adpt_cppe_portctrl.c +@@ -33,6 +33,7 @@ + #include "hsl_phy.h" + #include "hsl_port_prop.h" + #include "hppe_init.h" ++#include "ssdk_dts.h" + #include "adpt.h" + #include "adpt_hppe.h" + #include "adpt_cppe_portctrl.h" +@@ -60,8 +61,7 @@ _adpt_cppe_port_mux_mac_set(a_uint32_t dev_id, fal_port_t port_id, + case SSDK_PHYSICAL_PORT3: + case SSDK_PHYSICAL_PORT4: + if (mode0 == PORT_WRAPPER_PSGMII) { +- if (hsl_port_phyid_get(dev_id, +- SSDK_PHYSICAL_PORT3) == MALIBU2PORT_PHY) { ++ if (ssdk_dts_port3_pcs_channel_get(dev_id) == 4) { + cppe_port_mux_ctrl.bf.port3_pcs_sel = + CPPE_PORT3_PCS_SEL_PCS0_CHANNEL4; + cppe_port_mux_ctrl.bf.port4_pcs_sel = +diff --git a/src/adpt/hppe/adpt_hppe_uniphy.c b/src/adpt/hppe/adpt_hppe_uniphy.c +index 5e36602..bad1eab 100644 +--- a/src/adpt/hppe/adpt_hppe_uniphy.c ++++ b/src/adpt/hppe/adpt_hppe_uniphy.c +@@ -1122,9 +1122,6 @@ __adpt_hppe_uniphy_psgmii_mode_set(a_uint32_t dev_id, a_uint32_t uniphy_index) + { + a_uint32_t i; + sw_error_t rv = SW_OK; +-#if defined(CPPE) +- a_uint32_t phy_type = 0; +-#endif + + union uniphy_mode_ctrl_u uniphy_mode_ctrl; + +@@ -1134,9 +1131,7 @@ __adpt_hppe_uniphy_psgmii_mode_set(a_uint32_t dev_id, a_uint32_t uniphy_index) + SSDK_DEBUG("uniphy %d is psgmii mode\n", uniphy_index); + #if defined(CPPE) + if (adpt_ppe_type_get(dev_id) == CPPE_TYPE) { +- phy_type = hsl_port_phyid_get(dev_id, +- SSDK_PHYSICAL_PORT3); +- if (phy_type == MALIBU2PORT_PHY) { ++ if (ssdk_dts_port3_pcs_channel_get(dev_id) == 4) { + SSDK_INFO("cypress uniphy %d is qca8072 psgmii mode\n", uniphy_index); + rv = __adpt_cppe_uniphy_mode_set(dev_id, uniphy_index, + PORT_WRAPPER_PSGMII); +diff --git a/src/init/ssdk_dts.c b/src/init/ssdk_dts.c +index 686b6d2..70b0a09 100644 +--- a/src/init/ssdk_dts.c ++++ b/src/init/ssdk_dts.c +@@ -279,6 +279,13 @@ struct clk *ssdk_dts_cmnclk_get(a_uint32_t dev_id) + return cfg->cmnblk_clk; + } + ++a_uint32_t ssdk_dts_port3_pcs_channel_get(a_uint32_t dev_id) ++{ ++ ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]; ++ ++ return cfg->port3_pcs_channel; ++} ++ + #ifndef BOARD_AR71XX + #if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) + static void ssdk_dt_parse_mac_mode(a_uint32_t dev_id, +@@ -313,6 +320,25 @@ static void ssdk_dt_parse_mac_mode(a_uint32_t dev_id, + + return; + } ++ ++static void ssdk_dt_parse_port3_pcs_channel(a_uint32_t dev_id, ++ struct device_node *switch_node, ssdk_init_cfg *cfg) ++{ ++ const __be32 *port3_pcs_channel; ++ a_uint32_t len = 0; ++ ++ port3_pcs_channel = of_get_property(switch_node, "port3_pcs_channel", &len); ++ if (!port3_pcs_channel) { ++ ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port3_pcs_channel = 2; ++ } ++ else { ++ ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port3_pcs_channel = ++ be32_to_cpup(port3_pcs_channel); ++ } ++ ++ return; ++} ++ + #ifdef IN_UNIPHY + static void ssdk_dt_parse_uniphy(a_uint32_t dev_id) + { +@@ -1307,6 +1333,7 @@ sw_error_t ssdk_dt_parse(ssdk_init_cfg *cfg, a_uint32_t num, a_uint32_t *dev_id) + rv = ssdk_dt_parse_access_mode(switch_node, ssdk_dt_priv); + SW_RTN_ON_ERROR(rv); + ssdk_dt_parse_mac_mode(*dev_id, switch_node, cfg); ++ ssdk_dt_parse_port3_pcs_channel(*dev_id, switch_node, cfg); + ssdk_dt_parse_mdio(*dev_id, switch_node, cfg); + ssdk_dt_parse_port_bmp(*dev_id, switch_node, cfg); + ssdk_dt_parse_interrupt(*dev_id, switch_node); +-- +2.7.4 +