From: Wenjing Liu <Wenjing.Liu@amd.com>
Date: Thu, 25 Apr 2019 16:11:50 +0000 (-0400)
Subject: drm/amd/display: fix a potential issue in DSC logic
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=cba4d59c936cd17ac601c188725ccd779467a509;p=openwrt%2Fstaging%2Fblogic.git

drm/amd/display: fix a potential issue in DSC logic

[why]
In compute dsc bandwidth range there is an uninitialized variable

[how]
Initialize the variable to the correct value.

Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---

diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index 94a623dc37f4..252c3d0a2555 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -826,10 +826,16 @@ bool dc_dsc_compute_bandwidth_range(
 	struct dc_dsc_config config;
 
 	get_dsc_enc_caps(dc, &dsc_enc_caps, timing->pix_clk_100hz);
-	is_dsc_possible = setup_dsc_config(dsc_sink_caps,
-			&dsc_enc_caps,
-			0,
-			timing, &config);
+
+	is_dsc_possible = intersect_dsc_caps(dsc_sink_caps, &dsc_enc_caps,
+			timing->pixel_encoding, &dsc_common_caps);
+
+	if (is_dsc_possible)
+		is_dsc_possible = setup_dsc_config(dsc_sink_caps,
+				&dsc_enc_caps,
+				0,
+				timing, &config);
+
 	if (is_dsc_possible)
 		get_dsc_bandwidth_range(min_bpp, max_bpp, &dsc_common_caps, timing, range);