From: Christophe Leroy Date: Tue, 21 May 2019 13:34:18 +0000 (+0000) Subject: crypto: talitos - Align SEC1 accesses to 32 bits boundaries. X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=c9cca7034b34a2d82e9a03b757de2485c294851c;p=openwrt%2Fstaging%2Fblogic.git crypto: talitos - Align SEC1 accesses to 32 bits boundaries. The MPC885 reference manual states: SEC Lite-initiated 8xx writes can occur only on 32-bit-word boundaries, but reads can occur on any byte boundary. Writing back a header read from a non-32-bit-word boundary will yield unpredictable results. In order to ensure that, cra_alignmask is set to 3 for SEC1. Signed-off-by: Christophe Leroy Fixes: 9c4a79653b35 ("crypto: talitos - Freescale integrated security engine (SEC) driver") Signed-off-by: Herbert Xu --- diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c index 7c8a3a717b91..750b0159e654 100644 --- a/drivers/crypto/talitos.c +++ b/drivers/crypto/talitos.c @@ -3327,7 +3327,10 @@ static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev, alg->cra_priority = t_alg->algt.priority; else alg->cra_priority = TALITOS_CRA_PRIORITY; - alg->cra_alignmask = 0; + if (has_ftr_sec1(priv)) + alg->cra_alignmask = 3; + else + alg->cra_alignmask = 0; alg->cra_ctxsize = sizeof(struct talitos_ctx); alg->cra_flags |= CRYPTO_ALG_KERN_DRIVER_ONLY;