From: Tom Warren <twarren.nvidia@gmail.com>
Date: Fri, 24 Jan 2014 17:16:22 +0000 (-0700)
Subject: ARM: tegra: implement MASK_BITS_31_29
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=c82014daf5ed8030d2ec5903bd51b5ab817fb000;p=project%2Fbcm63xx%2Fu-boot.git

ARM: tegra: implement MASK_BITS_31_29

Some clock sources have 3-bit muxes in bits 31:29. Implement core
support for this mux field.

Signed-off-by: Tom Warren <twarren@nvidia.com>
[swarren, extracted from a larger patch by Tom]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---

diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c
index 96b705f2f6..33bb19084b 100644
--- a/arch/arm/cpu/tegra-common/clock.c
+++ b/arch/arm/cpu/tegra-common/clock.c
@@ -304,13 +304,27 @@ static int adjust_periph_pll(enum periph_id periph_id, int source,
 	/* work out the source clock and set it */
 	if (source < 0)
 		return -1;
-	if (mux_bits == MASK_BITS_31_28) {
-		clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
-				source << OUT_CLK_SOURCE_31_28_SHIFT);
-	} else {
+
+	switch (mux_bits) {
+	case MASK_BITS_31_30:
 		clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
 				source << OUT_CLK_SOURCE_31_30_SHIFT);
+		break;
+
+	case MASK_BITS_31_29:
+		clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK,
+				source << OUT_CLK_SOURCE_31_29_SHIFT);
+		break;
+
+	case MASK_BITS_31_28:
+		clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
+				source << OUT_CLK_SOURCE_31_28_SHIFT);
+		break;
+
+	default:
+		return -1;
 	}
+
 	udelay(2);
 	return 0;
 }
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h
index 9f81237d28..f07b83d26a 100644
--- a/arch/arm/include/asm/arch-tegra/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -236,6 +236,9 @@ enum {
 #define OUT_CLK_SOURCE_31_30_SHIFT	30
 #define OUT_CLK_SOURCE_31_30_MASK	(3U << OUT_CLK_SOURCE_31_30_SHIFT)
 
+#define OUT_CLK_SOURCE_31_29_SHIFT	29
+#define OUT_CLK_SOURCE_31_29_MASK	(7U << OUT_CLK_SOURCE_31_29_SHIFT)
+
 /* Note: See comment for MASK_BITS_31_28 in arch-tegra/clock.h */
 #define OUT_CLK_SOURCE_31_28_SHIFT	28
 #define OUT_CLK_SOURCE_31_28_MASK	(15U << OUT_CLK_SOURCE_31_28_SHIFT)