From: Tianling Shen Date: Wed, 26 Jun 2024 18:22:46 +0000 (+0800) Subject: rockchip: reorder patches X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=c7c0b7bc02b5464a8a852b6faedca85be649cfca;p=openwrt%2Fstaging%2Fthess.git rockchip: reorder patches Reorder to start from 001. Signed-off-by: Tianling Shen Link: https://github.com/openwrt/openwrt/pull/16149 Signed-off-by: Hauke Mehrtens --- diff --git a/target/linux/rockchip/patches-6.6/001-v6.8-arm64-dts-rockchip-Add-ethernet0-alias-to-the-dts-for-RK3566-boards.patch b/target/linux/rockchip/patches-6.6/001-v6.8-arm64-dts-rockchip-Add-ethernet0-alias-to-the-dts-for-RK3566-boards.patch new file mode 100644 index 0000000000..fb5015cf6e --- /dev/null +++ b/target/linux/rockchip/patches-6.6/001-v6.8-arm64-dts-rockchip-Add-ethernet0-alias-to-the-dts-for-RK3566-boards.patch @@ -0,0 +1,28 @@ +From 36d9b3ae708e865cdab95692db5a24c5d975383d Mon Sep 17 00:00:00 2001 +From: Dragan Simic +Date: Tue, 12 Dec 2023 09:01:39 +0100 +Subject: [PATCH] arm64: dts: rockchip: Add ethernet0 alias to the dts for + RK3566 boards + +Add ethernet0 alias to the board dts files for a few supported RK3566 boards +that had it missing. Also, remove the ethernet0 alias from one RK3566 SoM +dtsi file, which doesn't enable the GMAC, and add the ethernet0 alias back to +the dependent board dts files, which actually enable the GMAC. + +Signed-off-by: Dragan Simic +Link: https://lore.kernel.org/r/d2a272e0ae0fff0adfab8bb0238243b11d348799.1702368023.git.dsimic@manjaro.org +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 1 + + 1 files changed, 1 insertions(+), 0 deletion(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts +@@ -14,6 +14,7 @@ + compatible = "radxa,cm3-io", "radxa,cm3", "rockchip,rk3566"; + + aliases { ++ ethernet0 = &gmac1; + mmc1 = &sdmmc0; + }; + diff --git a/target/linux/rockchip/patches-6.6/002-v6.9-arm64-dts-rockchip-adjust-vendor-on-Banana-Pi-R2-Pro.patch b/target/linux/rockchip/patches-6.6/002-v6.9-arm64-dts-rockchip-adjust-vendor-on-Banana-Pi-R2-Pro.patch new file mode 100644 index 0000000000..9be609f661 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/002-v6.9-arm64-dts-rockchip-adjust-vendor-on-Banana-Pi-R2-Pro.patch @@ -0,0 +1,27 @@ +From 437644753208092f642b7669c69da606aa07dfb4 Mon Sep 17 00:00:00 2001 +From: Tim Lunn +Date: Wed, 14 Feb 2024 15:07:30 +1100 +Subject: [PATCH] arm64: dts: rockchip: adjust vendor on Banana Pi R2 Pro board + +Adjust compatible string to match the board vendor of Sinovoip + +Signed-off-by: Tim Lunn +Reviewed-by: Dragan Simic +Acked-by: Conor Dooley +Link: https://lore.kernel.org/r/20240214040731.3069111-4-tim@feathertop.org +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +@@ -13,7 +13,7 @@ + + / { + model = "Bananapi-R2 Pro (RK3568) DDR4 Board"; +- compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568"; ++ compatible = "sinovoip,rk3568-bpi-r2pro", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; diff --git a/target/linux/rockchip/patches-6.6/003-v6.10-arm64-dts-rockchip-Add-cache-information-to-the-SoC-dtsi-.patch b/target/linux/rockchip/patches-6.6/003-v6.10-arm64-dts-rockchip-Add-cache-information-to-the-SoC-dtsi-.patch new file mode 100644 index 0000000000..b23d7e06b9 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/003-v6.10-arm64-dts-rockchip-Add-cache-information-to-the-SoC-dtsi-.patch @@ -0,0 +1,127 @@ +From 8612169a05c5e979af033868b7a9b177e0f9fcdf Mon Sep 17 00:00:00 2001 +From: Dragan Simic +Date: Sat, 9 Mar 2024 05:25:06 +0100 +Subject: [PATCH] arm64: dts: rockchip: Add cache information to the SoC dtsi + for RK356x + +Add missing cache information to the Rockchip RK356x SoC dtsi, to allow +the userspace, which includes lscpu(1) that uses the virtual files provided +by the kernel under the /sys/devices/system/cpu directory, to display the +proper RK3566 and RK3568 cache information. + +Adding the cache information to the RK356x SoC dtsi also makes the following +warning message in the kernel log go away: + + cacheinfo: Unable to detect cache hierarchy for CPU 0 + +The cache parameters for the RK356x dtsi were obtained and partially derived +by hand from the cache size and layout specifications found in the following +datasheets and technical reference manuals: + + - Rockchip RK3566 datasheet, version 1.1 + - Rockchip RK3568 datasheet, version 1.3 + - ARM Cortex-A55 revision r1p0 TRM, version 0100-00 + - ARM DynamIQ Shared Unit revision r4p0 TRM, version 0400-02 + +For future reference, here's a rather detailed summary of the documentation, +which applies to both Rockchip RK3566 and RK3568 SoCs: + + - All caches employ the 64-byte cache line length + - Each Cortex-A55 core has 32 KB of L1 4-way, set-associative instruction + cache and 32 KB of L1 4-way, set-associative data cache + - There are no L2 caches, which are per-core and private in Cortex-A55, + because it belongs to the ARM DynamIQ IP core lineup + - The entire SoC has 512 KB of unified L3 16-way, set-associative cache, + which is shared among all four Cortex-A55 CPU cores + - Cortex-A55 cores can be configured without private per-core L2 caches, + in which case the shared L3 cache appears to them as an L2 cache; this + is the case for the RK356x SoCs, so let's use "cache-level = <2>" to + prevent the "huh, no L2 caches, but an L3 cache?" confusion among the + users viewing the data presented to the userspace; another option could + be to have additional 0 KB L2 caches defined, which may be technically + correct, but would probably be even more confusing + +Helped-by: Anand Moon +Tested-By: Diederik de Haas +Reviewed-by: Anand Moon +Signed-off-by: Dragan Simic +Link: https://lore.kernel.org/r/2dee6dad8460b0c5f3b5da53cf55f735840efef1.1709957777.git.dsimic@manjaro.org +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 41 ++++++++++++++++++++++++ + 1 file changed, 41 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -57,6 +57,13 @@ + #cooling-cells = <2>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; ++ i-cache-size = <0x8000>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <128>; ++ d-cache-size = <0x8000>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <128>; ++ next-level-cache = <&l3_cache>; + }; + + cpu1: cpu@100 { +@@ -66,6 +73,13 @@ + #cooling-cells = <2>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; ++ i-cache-size = <0x8000>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <128>; ++ d-cache-size = <0x8000>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <128>; ++ next-level-cache = <&l3_cache>; + }; + + cpu2: cpu@200 { +@@ -75,6 +89,13 @@ + #cooling-cells = <2>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; ++ i-cache-size = <0x8000>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <128>; ++ d-cache-size = <0x8000>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <128>; ++ next-level-cache = <&l3_cache>; + }; + + cpu3: cpu@300 { +@@ -84,9 +105,29 @@ + #cooling-cells = <2>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; ++ i-cache-size = <0x8000>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <128>; ++ d-cache-size = <0x8000>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <128>; ++ next-level-cache = <&l3_cache>; + }; + }; + ++ /* ++ * There are no private per-core L2 caches, but only the ++ * L3 cache that appears to the CPU cores as L2 caches ++ */ ++ l3_cache: l3-cache { ++ compatible = "cache"; ++ cache-level = <2>; ++ cache-unified; ++ cache-size = <0x80000>; ++ cache-line-size = <64>; ++ cache-sets = <512>; ++ }; ++ + cpu0_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; diff --git a/target/linux/rockchip/patches-6.6/004-next-soc-rockchip-io-domain-Add-RK3308-IO-voltage-domains.patch b/target/linux/rockchip/patches-6.6/004-next-soc-rockchip-io-domain-Add-RK3308-IO-voltage-domains.patch new file mode 100644 index 0000000000..bb7f833977 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/004-next-soc-rockchip-io-domain-Add-RK3308-IO-voltage-domains.patch @@ -0,0 +1,86 @@ +From 0536fa6e6fa3e48f4ca11855b586c277be524fbe Mon Sep 17 00:00:00 2001 +From: David Wu +Date: Tue, 21 May 2024 21:10:13 +0000 +Subject: [PATCH] soc: rockchip: io-domain: Add RK3308 IO voltage domains + +Add IO voltage domains support for the RK3308 SoC. + +Signed-off-by: David Wu +Signed-off-by: Jianqun Xu +Signed-off-by: Jonas Karlman +Link: https://lore.kernel.org/r/20240521211029.1236094-11-jonas@kwiboo.se +Signed-off-by: Heiko Stuebner +--- + drivers/soc/rockchip/io-domain.c | 40 ++++++++++++++++++++++++++++++++ + 1 file changed, 40 insertions(+) + +--- a/drivers/soc/rockchip/io-domain.c ++++ b/drivers/soc/rockchip/io-domain.c +@@ -39,6 +39,10 @@ + #define RK3288_SOC_CON2_FLASH0 BIT(7) + #define RK3288_SOC_FLASH_SUPPLY_NUM 2 + ++#define RK3308_SOC_CON0 0x300 ++#define RK3308_SOC_CON0_VCCIO3 BIT(8) ++#define RK3308_SOC_VCCIO3_SUPPLY_NUM 3 ++ + #define RK3328_SOC_CON4 0x410 + #define RK3328_SOC_CON4_VCCIO2 BIT(7) + #define RK3328_SOC_VCCIO2_SUPPLY_NUM 1 +@@ -229,6 +233,25 @@ static void rk3288_iodomain_init(struct + dev_warn(iod->dev, "couldn't update flash0 ctrl\n"); + } + ++static void rk3308_iodomain_init(struct rockchip_iodomain *iod) ++{ ++ int ret; ++ u32 val; ++ ++ /* if no vccio3 supply we should leave things alone */ ++ if (!iod->supplies[RK3308_SOC_VCCIO3_SUPPLY_NUM].reg) ++ return; ++ ++ /* ++ * set vccio3 iodomain to also use this framework ++ * instead of a special gpio. ++ */ ++ val = RK3308_SOC_CON0_VCCIO3 | (RK3308_SOC_CON0_VCCIO3 << 16); ++ ret = regmap_write(iod->grf, RK3308_SOC_CON0, val); ++ if (ret < 0) ++ dev_warn(iod->dev, "couldn't update vccio3 vsel ctrl\n"); ++} ++ + static void rk3328_iodomain_init(struct rockchip_iodomain *iod) + { + int ret; +@@ -376,6 +399,19 @@ static const struct rockchip_iodomain_so + .init = rk3288_iodomain_init, + }; + ++static const struct rockchip_iodomain_soc_data soc_data_rk3308 = { ++ .grf_offset = 0x300, ++ .supply_names = { ++ "vccio0", ++ "vccio1", ++ "vccio2", ++ "vccio3", ++ "vccio4", ++ "vccio5", ++ }, ++ .init = rk3308_iodomain_init, ++}; ++ + static const struct rockchip_iodomain_soc_data soc_data_rk3328 = { + .grf_offset = 0x410, + .supply_names = { +@@ -529,6 +565,10 @@ static const struct of_device_id rockchi + .data = &soc_data_rk3288 + }, + { ++ .compatible = "rockchip,rk3308-io-voltage-domain", ++ .data = &soc_data_rk3308 ++ }, ++ { + .compatible = "rockchip,rk3328-io-voltage-domain", + .data = &soc_data_rk3328 + }, diff --git a/target/linux/rockchip/patches-6.6/005-v6.11-arm64-dts-rockchip-Add-rk3308-IO-voltage-domains.patch b/target/linux/rockchip/patches-6.6/005-v6.11-arm64-dts-rockchip-Add-rk3308-IO-voltage-domains.patch new file mode 100644 index 0000000000..3565acd2e4 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/005-v6.11-arm64-dts-rockchip-Add-rk3308-IO-voltage-domains.patch @@ -0,0 +1,28 @@ +From d1829ba469d5743734e37d59fece73e3668ab084 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Tue, 21 May 2024 21:10:14 +0000 +Subject: [PATCH] arm64: dts: rockchip: Add rk3308 IO voltage domains + +Add a disabled RK3308 IO voltage domains node to SoC DT. + +Signed-off-by: Jonas Karlman +Link: https://lore.kernel.org/r/20240521211029.1236094-12-jonas@kwiboo.se +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3308.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi +@@ -168,6 +168,11 @@ + compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; + reg = <0x0 0xff000000 0x0 0x08000>; + ++ io_domains: io-domains { ++ compatible = "rockchip,rk3308-io-voltage-domain"; ++ status = "disabled"; ++ }; ++ + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x500>; diff --git a/target/linux/rockchip/patches-6.6/006-v6.8-arm64-dts-rockchip-add-gpio-line-names-to-rk3308-roc.patch b/target/linux/rockchip/patches-6.6/006-v6.8-arm64-dts-rockchip-add-gpio-line-names-to-rk3308-roc.patch new file mode 100644 index 0000000000..83ebe67789 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/006-v6.8-arm64-dts-rockchip-add-gpio-line-names-to-rk3308-roc.patch @@ -0,0 +1,84 @@ +From c45de75d7a9ab44a15dedc7a121d6371d6891301 Mon Sep 17 00:00:00 2001 +From: Trevor Woerner +Date: Mon, 20 Nov 2023 11:22:32 -0500 +Subject: [PATCH] arm64: dts: rockchip: add gpio-line-names to rk3308-rock-pi-s + +Add names to the pins of the general-purpose expansion header as given in the +Radxa GPIO page[1] following the conventions in the kernel documentation[2] to +make it easier for users to correlate the pins with functions when using +utilities such as gpioinfo. + +[1] https://wiki.radxa.com/RockpiS/hardware/gpio +[2] Documentation/devicetree/bindings/gpio/gpio.txt + +Signed-off-by: Trevor Woerner +Link: https://lore.kernel.org/r/20231120162232.27653-1-twoerner@gmail.com +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3308-rock-pi-s.dts | 58 +++++++++++++++++++ + 1 file changed, 58 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts +@@ -315,3 +315,61 @@ + &wdt { + status = "okay"; + }; ++ ++&gpio0 { ++ gpio-line-names = ++ /* GPIO0_A0 - A7 */ ++ "", "", "", "", "", "", "", "", ++ /* GPIO0_B0 - B7 */ ++ "", "", "", "header1-pin3 [GPIO0_B3]", "header1-pin5 [GPIO0_B4]", ++ "", "", "header1-pin11 [GPIO0_B7]", ++ /* GPIO0_C0 - C7 */ ++ "header1-pin13 [GPIO0_C0]", "header1-pin15 [GPIO0_C1]", "", "", "", ++ "", "", "", ++ /* GPIO0_D0 - D8 */ ++ "", "", "", "", "", "", "", ""; ++}; ++ ++&gpio1 { ++ gpio-line-names = ++ /* GPIO1_A0 - A7 */ ++ "", "", "", "", "", "", "", "", ++ /* GPIO1_B0 - B7 */ ++ "", "", "", "", "", "", "", "", ++ /* GPIO1_C0 - C7 */ ++ "", "", "", "", "", "", "header1-pin21 [GPIO1_C6]", ++ "header1-pin19 [GPIO1_C7]", ++ /* GPIO1_D0 - D8 */ ++ "header1-pin23 [GPIO1_D0]", "header1-pin24 [GPIO1_D1]", "", "", "", ++ "", "", ""; ++}; ++ ++&gpio2 { ++ gpio-line-names = ++ /* GPIO2_A0 - A7 */ ++ "header1-pin10 [GPIO2_A0]", "header1-pin8 [GPIO2_A1]", "", "", ++ "header1-pin7 [GPIO2_A4]", "header1-pin12 [GPIO2_A5]", ++ "header2-pin46 [GPIO2_A6]", "header1-pin22 [GPIO1_A7]", ++ /* GPIO2_B0 - B7 */ ++ "header2-pin45 [GPIO2_B0]", "header1-pin18 [GPIO2_B1]", ++ "header1-pin16 [GPIO2_B2]", "header2-pin44 [GPIO2_B3]", ++ "header2-pin43 [GPIO2_B4]", "header2-pin28 [GPIO2_B5]", ++ "header2-pin30 [GPIO2_B6]", "header2-pin32 [GPIO2_B7]", ++ /* GPIO2_C0 - C7 */ ++ "header2-pin34 [GPIO2_C0]", "", "", "", "", "", "", "", ++ /* GPIO2_D0 - D8 */ ++ "", "", "", "", "", "", "", ""; ++}; ++ ++&gpio3 { ++ gpio-line-names = ++ /* GPIO3_A0 - A7 */ ++ "", "", "", "", "", "", "", "", ++ /* GPIO3_B0 - B7 */ ++ "", "", "header2-pin42 [GPIO3_B2]", "header2-pin41 [GPIO3_B3]", ++ "header2-pin40 [GPIO3_B4]", "header2-pin39 [GPIO3_B5]", "", "", ++ /* GPIO3_C0 - C7 */ ++ "", "", "", "", "", "", "", "", ++ /* GPIO3_D0 - D8 */ ++ "", "", "", "", "", "", "", ""; ++}; diff --git a/target/linux/rockchip/patches-6.6/007-v6.8-arm64-dts-rockchip-rk3308-rock-pi-s-gpio-line-names-.patch b/target/linux/rockchip/patches-6.6/007-v6.8-arm64-dts-rockchip-rk3308-rock-pi-s-gpio-line-names-.patch new file mode 100644 index 0000000000..994644e142 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/007-v6.8-arm64-dts-rockchip-rk3308-rock-pi-s-gpio-line-names-.patch @@ -0,0 +1,152 @@ +From 085021cc825ed90a6ddc4406f608fb8a85745f81 Mon Sep 17 00:00:00 2001 +From: Trevor Woerner +Date: Tue, 19 Dec 2023 12:38:13 -0500 +Subject: [PATCH] arm64: dts: rockchip: rk3308-rock-pi-s gpio-line-names + cleanup + +Perform the following cleanups on a previous patch: +- indent lines after "gpio-line-names" +- fix D0-D8 -> D0-D7 +- sort phandle references + +Fixes: c45de75d7a9a ("arm64: dts: rockchip: add gpio-line-names to rk3308-rock-pi-s") +Signed-off-by: Trevor Woerner +Link: https://lore.kernel.org/r/20231219173814.1569-1-twoerner@gmail.com +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3308-rock-pi-s.dts | 120 +++++++++--------- + 1 file changed, 62 insertions(+), 58 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts +@@ -166,6 +166,68 @@ + }; + }; + ++&gpio0 { ++ gpio-line-names = ++ /* GPIO0_A0 - A7 */ ++ "", "", "", "", "", "", "", "", ++ /* GPIO0_B0 - B7 */ ++ "", "", "", "header1-pin3 [GPIO0_B3]", ++ "header1-pin5 [GPIO0_B4]", "", "", ++ "header1-pin11 [GPIO0_B7]", ++ /* GPIO0_C0 - C7 */ ++ "header1-pin13 [GPIO0_C0]", ++ "header1-pin15 [GPIO0_C1]", "", "", "", ++ "", "", "", ++ /* GPIO0_D0 - D7 */ ++ "", "", "", "", "", "", "", ""; ++}; ++ ++&gpio1 { ++ gpio-line-names = ++ /* GPIO1_A0 - A7 */ ++ "", "", "", "", "", "", "", "", ++ /* GPIO1_B0 - B7 */ ++ "", "", "", "", "", "", "", "", ++ /* GPIO1_C0 - C7 */ ++ "", "", "", "", "", "", "header1-pin21 [GPIO1_C6]", ++ "header1-pin19 [GPIO1_C7]", ++ /* GPIO1_D0 - D7 */ ++ "header1-pin23 [GPIO1_D0]", "header1-pin24 [GPIO1_D1]", ++ "", "", "", "", "", ""; ++}; ++ ++&gpio2 { ++ gpio-line-names = ++ /* GPIO2_A0 - A7 */ ++ "header1-pin10 [GPIO2_A0]", "header1-pin8 [GPIO2_A1]", ++ "", "", ++ "header1-pin7 [GPIO2_A4]", "header1-pin12 [GPIO2_A5]", ++ "header2-pin46 [GPIO2_A6]", "header1-pin22 [GPIO1_A7]", ++ /* GPIO2_B0 - B7 */ ++ "header2-pin45 [GPIO2_B0]", "header1-pin18 [GPIO2_B1]", ++ "header1-pin16 [GPIO2_B2]", "header2-pin44 [GPIO2_B3]", ++ "header2-pin43 [GPIO2_B4]", "header2-pin28 [GPIO2_B5]", ++ "header2-pin30 [GPIO2_B6]", "header2-pin32 [GPIO2_B7]", ++ /* GPIO2_C0 - C7 */ ++ "header2-pin34 [GPIO2_C0]", "", "", "", "", "", "", "", ++ /* GPIO2_D0 - D7 */ ++ "", "", "", "", "", "", "", ""; ++}; ++ ++&gpio3 { ++ gpio-line-names = ++ /* GPIO3_A0 - A7 */ ++ "", "", "", "", "", "", "", "", ++ /* GPIO3_B0 - B7 */ ++ "", "", "header2-pin42 [GPIO3_B2]", ++ "header2-pin41 [GPIO3_B3]", "header2-pin40 [GPIO3_B4]", ++ "header2-pin39 [GPIO3_B5]", "", "", ++ /* GPIO3_C0 - C7 */ ++ "", "", "", "", "", "", "", "", ++ /* GPIO3_D0 - D7 */ ++ "", "", "", "", "", "", "", ""; ++}; ++ + &i2c1 { + status = "okay"; + }; +@@ -315,61 +377,3 @@ + &wdt { + status = "okay"; + }; +- +-&gpio0 { +- gpio-line-names = +- /* GPIO0_A0 - A7 */ +- "", "", "", "", "", "", "", "", +- /* GPIO0_B0 - B7 */ +- "", "", "", "header1-pin3 [GPIO0_B3]", "header1-pin5 [GPIO0_B4]", +- "", "", "header1-pin11 [GPIO0_B7]", +- /* GPIO0_C0 - C7 */ +- "header1-pin13 [GPIO0_C0]", "header1-pin15 [GPIO0_C1]", "", "", "", +- "", "", "", +- /* GPIO0_D0 - D8 */ +- "", "", "", "", "", "", "", ""; +-}; +- +-&gpio1 { +- gpio-line-names = +- /* GPIO1_A0 - A7 */ +- "", "", "", "", "", "", "", "", +- /* GPIO1_B0 - B7 */ +- "", "", "", "", "", "", "", "", +- /* GPIO1_C0 - C7 */ +- "", "", "", "", "", "", "header1-pin21 [GPIO1_C6]", +- "header1-pin19 [GPIO1_C7]", +- /* GPIO1_D0 - D8 */ +- "header1-pin23 [GPIO1_D0]", "header1-pin24 [GPIO1_D1]", "", "", "", +- "", "", ""; +-}; +- +-&gpio2 { +- gpio-line-names = +- /* GPIO2_A0 - A7 */ +- "header1-pin10 [GPIO2_A0]", "header1-pin8 [GPIO2_A1]", "", "", +- "header1-pin7 [GPIO2_A4]", "header1-pin12 [GPIO2_A5]", +- "header2-pin46 [GPIO2_A6]", "header1-pin22 [GPIO1_A7]", +- /* GPIO2_B0 - B7 */ +- "header2-pin45 [GPIO2_B0]", "header1-pin18 [GPIO2_B1]", +- "header1-pin16 [GPIO2_B2]", "header2-pin44 [GPIO2_B3]", +- "header2-pin43 [GPIO2_B4]", "header2-pin28 [GPIO2_B5]", +- "header2-pin30 [GPIO2_B6]", "header2-pin32 [GPIO2_B7]", +- /* GPIO2_C0 - C7 */ +- "header2-pin34 [GPIO2_C0]", "", "", "", "", "", "", "", +- /* GPIO2_D0 - D8 */ +- "", "", "", "", "", "", "", ""; +-}; +- +-&gpio3 { +- gpio-line-names = +- /* GPIO3_A0 - A7 */ +- "", "", "", "", "", "", "", "", +- /* GPIO3_B0 - B7 */ +- "", "", "header2-pin42 [GPIO3_B2]", "header2-pin41 [GPIO3_B3]", +- "header2-pin40 [GPIO3_B4]", "header2-pin39 [GPIO3_B5]", "", "", +- /* GPIO3_C0 - C7 */ +- "", "", "", "", "", "", "", "", +- /* GPIO3_D0 - D8 */ +- "", "", "", "", "", "", "", ""; +-}; diff --git a/target/linux/rockchip/patches-6.6/008-v6.11-arm64-dts-rockchip-Add-io-domains-to-rk3308-rock-pi-.patch b/target/linux/rockchip/patches-6.6/008-v6.11-arm64-dts-rockchip-Add-io-domains-to-rk3308-rock-pi-.patch new file mode 100644 index 0000000000..ad746df3b0 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/008-v6.11-arm64-dts-rockchip-Add-io-domains-to-rk3308-rock-pi-.patch @@ -0,0 +1,35 @@ +From 100b3bdee6035192f6d4a1847970fe004bb505fb Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Tue, 21 May 2024 21:10:15 +0000 +Subject: [PATCH] arm64: dts: rockchip: Add io-domains to rk3308-rock-pi-s + +The VCCIO4 io-domain used for WiFi/BT is using 1v8 IO signal voltage. + +Add io-domains node with the VCCIO supplies connected on the board. + +Signed-off-by: Jonas Karlman +Link: https://lore.kernel.org/r/20240521211029.1236094-13-jonas@kwiboo.se +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts +@@ -232,6 +232,16 @@ + status = "okay"; + }; + ++&io_domains { ++ vccio0-supply = <&vcc_io>; ++ vccio1-supply = <&vcc_io>; ++ vccio2-supply = <&vcc_io>; ++ vccio3-supply = <&vcc_io>; ++ vccio4-supply = <&vcc_1v8>; ++ vccio5-supply = <&vcc_io>; ++ status = "okay"; ++}; ++ + &pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&rtc_32k>; diff --git a/target/linux/rockchip/patches-6.6/010-next-soc-rockchip-io-domain-Add-RK3308-IO-voltage-domains.patch b/target/linux/rockchip/patches-6.6/010-next-soc-rockchip-io-domain-Add-RK3308-IO-voltage-domains.patch deleted file mode 100644 index bb7f833977..0000000000 --- a/target/linux/rockchip/patches-6.6/010-next-soc-rockchip-io-domain-Add-RK3308-IO-voltage-domains.patch +++ /dev/null @@ -1,86 +0,0 @@ -From 0536fa6e6fa3e48f4ca11855b586c277be524fbe Mon Sep 17 00:00:00 2001 -From: David Wu -Date: Tue, 21 May 2024 21:10:13 +0000 -Subject: [PATCH] soc: rockchip: io-domain: Add RK3308 IO voltage domains - -Add IO voltage domains support for the RK3308 SoC. - -Signed-off-by: David Wu -Signed-off-by: Jianqun Xu -Signed-off-by: Jonas Karlman -Link: https://lore.kernel.org/r/20240521211029.1236094-11-jonas@kwiboo.se -Signed-off-by: Heiko Stuebner ---- - drivers/soc/rockchip/io-domain.c | 40 ++++++++++++++++++++++++++++++++ - 1 file changed, 40 insertions(+) - ---- a/drivers/soc/rockchip/io-domain.c -+++ b/drivers/soc/rockchip/io-domain.c -@@ -39,6 +39,10 @@ - #define RK3288_SOC_CON2_FLASH0 BIT(7) - #define RK3288_SOC_FLASH_SUPPLY_NUM 2 - -+#define RK3308_SOC_CON0 0x300 -+#define RK3308_SOC_CON0_VCCIO3 BIT(8) -+#define RK3308_SOC_VCCIO3_SUPPLY_NUM 3 -+ - #define RK3328_SOC_CON4 0x410 - #define RK3328_SOC_CON4_VCCIO2 BIT(7) - #define RK3328_SOC_VCCIO2_SUPPLY_NUM 1 -@@ -229,6 +233,25 @@ static void rk3288_iodomain_init(struct - dev_warn(iod->dev, "couldn't update flash0 ctrl\n"); - } - -+static void rk3308_iodomain_init(struct rockchip_iodomain *iod) -+{ -+ int ret; -+ u32 val; -+ -+ /* if no vccio3 supply we should leave things alone */ -+ if (!iod->supplies[RK3308_SOC_VCCIO3_SUPPLY_NUM].reg) -+ return; -+ -+ /* -+ * set vccio3 iodomain to also use this framework -+ * instead of a special gpio. -+ */ -+ val = RK3308_SOC_CON0_VCCIO3 | (RK3308_SOC_CON0_VCCIO3 << 16); -+ ret = regmap_write(iod->grf, RK3308_SOC_CON0, val); -+ if (ret < 0) -+ dev_warn(iod->dev, "couldn't update vccio3 vsel ctrl\n"); -+} -+ - static void rk3328_iodomain_init(struct rockchip_iodomain *iod) - { - int ret; -@@ -376,6 +399,19 @@ static const struct rockchip_iodomain_so - .init = rk3288_iodomain_init, - }; - -+static const struct rockchip_iodomain_soc_data soc_data_rk3308 = { -+ .grf_offset = 0x300, -+ .supply_names = { -+ "vccio0", -+ "vccio1", -+ "vccio2", -+ "vccio3", -+ "vccio4", -+ "vccio5", -+ }, -+ .init = rk3308_iodomain_init, -+}; -+ - static const struct rockchip_iodomain_soc_data soc_data_rk3328 = { - .grf_offset = 0x410, - .supply_names = { -@@ -529,6 +565,10 @@ static const struct of_device_id rockchi - .data = &soc_data_rk3288 - }, - { -+ .compatible = "rockchip,rk3308-io-voltage-domain", -+ .data = &soc_data_rk3308 -+ }, -+ { - .compatible = "rockchip,rk3328-io-voltage-domain", - .data = &soc_data_rk3328 - }, diff --git a/target/linux/rockchip/patches-6.6/011-v6.11-arm64-dts-rockchip-Add-rk3308-IO-voltage-domains.patch b/target/linux/rockchip/patches-6.6/011-v6.11-arm64-dts-rockchip-Add-rk3308-IO-voltage-domains.patch deleted file mode 100644 index 3565acd2e4..0000000000 --- a/target/linux/rockchip/patches-6.6/011-v6.11-arm64-dts-rockchip-Add-rk3308-IO-voltage-domains.patch +++ /dev/null @@ -1,28 +0,0 @@ -From d1829ba469d5743734e37d59fece73e3668ab084 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Tue, 21 May 2024 21:10:14 +0000 -Subject: [PATCH] arm64: dts: rockchip: Add rk3308 IO voltage domains - -Add a disabled RK3308 IO voltage domains node to SoC DT. - -Signed-off-by: Jonas Karlman -Link: https://lore.kernel.org/r/20240521211029.1236094-12-jonas@kwiboo.se -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3308.dtsi | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi -@@ -168,6 +168,11 @@ - compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; - reg = <0x0 0xff000000 0x0 0x08000>; - -+ io_domains: io-domains { -+ compatible = "rockchip,rk3308-io-voltage-domain"; -+ status = "disabled"; -+ }; -+ - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x500>; diff --git a/target/linux/rockchip/patches-6.6/023-v6.8-arm64-dts-rockchip-Add-ethernet0-alias-to-the-dts-for-RK3566-boards.patch b/target/linux/rockchip/patches-6.6/023-v6.8-arm64-dts-rockchip-Add-ethernet0-alias-to-the-dts-for-RK3566-boards.patch deleted file mode 100644 index fb5015cf6e..0000000000 --- a/target/linux/rockchip/patches-6.6/023-v6.8-arm64-dts-rockchip-Add-ethernet0-alias-to-the-dts-for-RK3566-boards.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 36d9b3ae708e865cdab95692db5a24c5d975383d Mon Sep 17 00:00:00 2001 -From: Dragan Simic -Date: Tue, 12 Dec 2023 09:01:39 +0100 -Subject: [PATCH] arm64: dts: rockchip: Add ethernet0 alias to the dts for - RK3566 boards - -Add ethernet0 alias to the board dts files for a few supported RK3566 boards -that had it missing. Also, remove the ethernet0 alias from one RK3566 SoM -dtsi file, which doesn't enable the GMAC, and add the ethernet0 alias back to -the dependent board dts files, which actually enable the GMAC. - -Signed-off-by: Dragan Simic -Link: https://lore.kernel.org/r/d2a272e0ae0fff0adfab8bb0238243b11d348799.1702368023.git.dsimic@manjaro.org -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 1 + - 1 files changed, 1 insertions(+), 0 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts -@@ -14,6 +14,7 @@ - compatible = "radxa,cm3-io", "radxa,cm3", "rockchip,rk3566"; - - aliases { -+ ethernet0 = &gmac1; - mmc1 = &sdmmc0; - }; - diff --git a/target/linux/rockchip/patches-6.6/030-v6.9-arm64-dts-rockchip-adjust-vendor-on-Banana-Pi-R2-Pro.patch b/target/linux/rockchip/patches-6.6/030-v6.9-arm64-dts-rockchip-adjust-vendor-on-Banana-Pi-R2-Pro.patch deleted file mode 100644 index 9be609f661..0000000000 --- a/target/linux/rockchip/patches-6.6/030-v6.9-arm64-dts-rockchip-adjust-vendor-on-Banana-Pi-R2-Pro.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 437644753208092f642b7669c69da606aa07dfb4 Mon Sep 17 00:00:00 2001 -From: Tim Lunn -Date: Wed, 14 Feb 2024 15:07:30 +1100 -Subject: [PATCH] arm64: dts: rockchip: adjust vendor on Banana Pi R2 Pro board - -Adjust compatible string to match the board vendor of Sinovoip - -Signed-off-by: Tim Lunn -Reviewed-by: Dragan Simic -Acked-by: Conor Dooley -Link: https://lore.kernel.org/r/20240214040731.3069111-4-tim@feathertop.org -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -@@ -13,7 +13,7 @@ - - / { - model = "Bananapi-R2 Pro (RK3568) DDR4 Board"; -- compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568"; -+ compatible = "sinovoip,rk3568-bpi-r2pro", "rockchip,rk3568"; - - aliases { - ethernet0 = &gmac0; diff --git a/target/linux/rockchip/patches-6.6/031-v6.10-arm64-dts-rockchip-Add-cache-information-to-the-SoC-dtsi-.patch b/target/linux/rockchip/patches-6.6/031-v6.10-arm64-dts-rockchip-Add-cache-information-to-the-SoC-dtsi-.patch deleted file mode 100644 index b23d7e06b9..0000000000 --- a/target/linux/rockchip/patches-6.6/031-v6.10-arm64-dts-rockchip-Add-cache-information-to-the-SoC-dtsi-.patch +++ /dev/null @@ -1,127 +0,0 @@ -From 8612169a05c5e979af033868b7a9b177e0f9fcdf Mon Sep 17 00:00:00 2001 -From: Dragan Simic -Date: Sat, 9 Mar 2024 05:25:06 +0100 -Subject: [PATCH] arm64: dts: rockchip: Add cache information to the SoC dtsi - for RK356x - -Add missing cache information to the Rockchip RK356x SoC dtsi, to allow -the userspace, which includes lscpu(1) that uses the virtual files provided -by the kernel under the /sys/devices/system/cpu directory, to display the -proper RK3566 and RK3568 cache information. - -Adding the cache information to the RK356x SoC dtsi also makes the following -warning message in the kernel log go away: - - cacheinfo: Unable to detect cache hierarchy for CPU 0 - -The cache parameters for the RK356x dtsi were obtained and partially derived -by hand from the cache size and layout specifications found in the following -datasheets and technical reference manuals: - - - Rockchip RK3566 datasheet, version 1.1 - - Rockchip RK3568 datasheet, version 1.3 - - ARM Cortex-A55 revision r1p0 TRM, version 0100-00 - - ARM DynamIQ Shared Unit revision r4p0 TRM, version 0400-02 - -For future reference, here's a rather detailed summary of the documentation, -which applies to both Rockchip RK3566 and RK3568 SoCs: - - - All caches employ the 64-byte cache line length - - Each Cortex-A55 core has 32 KB of L1 4-way, set-associative instruction - cache and 32 KB of L1 4-way, set-associative data cache - - There are no L2 caches, which are per-core and private in Cortex-A55, - because it belongs to the ARM DynamIQ IP core lineup - - The entire SoC has 512 KB of unified L3 16-way, set-associative cache, - which is shared among all four Cortex-A55 CPU cores - - Cortex-A55 cores can be configured without private per-core L2 caches, - in which case the shared L3 cache appears to them as an L2 cache; this - is the case for the RK356x SoCs, so let's use "cache-level = <2>" to - prevent the "huh, no L2 caches, but an L3 cache?" confusion among the - users viewing the data presented to the userspace; another option could - be to have additional 0 KB L2 caches defined, which may be technically - correct, but would probably be even more confusing - -Helped-by: Anand Moon -Tested-By: Diederik de Haas -Reviewed-by: Anand Moon -Signed-off-by: Dragan Simic -Link: https://lore.kernel.org/r/2dee6dad8460b0c5f3b5da53cf55f735840efef1.1709957777.git.dsimic@manjaro.org -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk356x.dtsi | 41 ++++++++++++++++++++++++ - 1 file changed, 41 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -57,6 +57,13 @@ - #cooling-cells = <2>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; -+ i-cache-size = <0x8000>; -+ i-cache-line-size = <64>; -+ i-cache-sets = <128>; -+ d-cache-size = <0x8000>; -+ d-cache-line-size = <64>; -+ d-cache-sets = <128>; -+ next-level-cache = <&l3_cache>; - }; - - cpu1: cpu@100 { -@@ -66,6 +73,13 @@ - #cooling-cells = <2>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; -+ i-cache-size = <0x8000>; -+ i-cache-line-size = <64>; -+ i-cache-sets = <128>; -+ d-cache-size = <0x8000>; -+ d-cache-line-size = <64>; -+ d-cache-sets = <128>; -+ next-level-cache = <&l3_cache>; - }; - - cpu2: cpu@200 { -@@ -75,6 +89,13 @@ - #cooling-cells = <2>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; -+ i-cache-size = <0x8000>; -+ i-cache-line-size = <64>; -+ i-cache-sets = <128>; -+ d-cache-size = <0x8000>; -+ d-cache-line-size = <64>; -+ d-cache-sets = <128>; -+ next-level-cache = <&l3_cache>; - }; - - cpu3: cpu@300 { -@@ -84,9 +105,29 @@ - #cooling-cells = <2>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; -+ i-cache-size = <0x8000>; -+ i-cache-line-size = <64>; -+ i-cache-sets = <128>; -+ d-cache-size = <0x8000>; -+ d-cache-line-size = <64>; -+ d-cache-sets = <128>; -+ next-level-cache = <&l3_cache>; - }; - }; - -+ /* -+ * There are no private per-core L2 caches, but only the -+ * L3 cache that appears to the CPU cores as L2 caches -+ */ -+ l3_cache: l3-cache { -+ compatible = "cache"; -+ cache-level = <2>; -+ cache-unified; -+ cache-size = <0x80000>; -+ cache-line-size = <64>; -+ cache-sets = <512>; -+ }; -+ - cpu0_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; diff --git a/target/linux/rockchip/patches-6.6/031-v6.9-arm64-dts-rockchip-Add-support-for-NanoPi-R6S.patch b/target/linux/rockchip/patches-6.6/031-v6.9-arm64-dts-rockchip-Add-support-for-NanoPi-R6S.patch deleted file mode 100644 index e5afbb4f40..0000000000 --- a/target/linux/rockchip/patches-6.6/031-v6.9-arm64-dts-rockchip-Add-support-for-NanoPi-R6S.patch +++ /dev/null @@ -1,792 +0,0 @@ -From f1b11f43b3e983b26d8010fc43ba6c2b979826f2 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Sat, 30 Dec 2023 14:18:00 +0300 -Subject: [PATCH] arm64: dts: rockchip: Add support for NanoPi R6S - -Add basic NanoPi R6S support that comes with USB2, PCIe, SD card, eMMC -support. - -Signed-off-by: Muhammed Efe Cetin -Link: https://lore.kernel.org/r/6db3b653efc6f0a2dca8e96fdd0503906db72fb6.1703934548.git.efectn@protonmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../boot/dts/rockchip/rk3588s-nanopi-r6s.dts | 764 ++++++++++++++++++ - 2 files changed, 765 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts - ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -104,4 +104,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-na - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-indiedroid-nova.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts -@@ -0,0 +1,764 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+ -+#include -+#include -+#include -+#include "rk3588s.dtsi" -+ -+/ { -+ model = "FriendlyElec NanoPi R6S"; -+ compatible = "friendlyarm,nanopi-r6s", "rockchip,rk3588s"; -+ -+ aliases { -+ ethernet0 = &gmac1; -+ mmc0 = &sdmmc; -+ mmc1 = &sdhci; -+ }; -+ -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ adc-keys { -+ compatible = "adc-keys"; -+ io-channels = <&saradc 0>; -+ io-channel-names = "buttons"; -+ keyup-threshold-microvolt = <1800000>; -+ poll-interval = <100>; -+ -+ button-maskrom { -+ label = "Maskrom"; -+ linux,code = ; -+ press-threshold-microvolt = <1800>; -+ }; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&key1_pin>; -+ -+ button-user { -+ label = "User"; -+ linux,code = ; -+ gpios = <&gpio1 RK_PC0 GPIO_ACTIVE_LOW>; -+ debounce-interval = <50>; -+ }; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ sys_led: led-0 { -+ label = "sys_led"; -+ gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "heartbeat"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sys_led_pin>; -+ }; -+ -+ wan_led: led-1 { -+ label = "wan_led"; -+ gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wan_led_pin>; -+ }; -+ -+ lan1_led: led-2 { -+ label = "lan1_led"; -+ gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&lan1_led_pin>; -+ }; -+ -+ lan2_led: led-3 { -+ label = "lan2_led"; -+ gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&lan2_led_pin>; -+ }; -+ }; -+ -+ vcc5v0_sys: vcc5v0-sys-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_1v1_nldo_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1100000>; -+ regulator-max-microvolt = <1100000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc_3v3_s0: vcc-3v3-s0-regulator { -+ compatible = "regulator-fixed"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc_3v3_s0"; -+ vin-supply = <&vcc_3v3_s3>; -+ }; -+ -+ vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sd_s0_pwr>; -+ regulator-name = "vcc_3v3_sd_s0"; -+ regulator-boot-on; -+ regulator-max-microvolt = <3000000>; -+ regulator-min-microvolt = <3000000>; -+ vin-supply = <&vcc_3v3_s3>; -+ }; -+ -+ vcc_3v3_pcie20: vcc3v3-pcie20-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_3v3_pcie20"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_3v3_s3>; -+ }; -+ -+ vcc5v0_usb: vcc5v0-usb-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_usb"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc5v0_usb_otg0: vcc5v0-usb-otg0-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&typec5v_pwren>; -+ regulator-name = "vcc5v0_usb_otg0"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_usb>; -+ }; -+ -+ vcc5v0_host_20: vcc5v0-host-20-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_host20_en>; -+ regulator-name = "vcc5v0_host_20"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_usb>; -+ }; -+}; -+ -+&combphy0_ps { -+ status = "okay"; -+}; -+ -+&combphy2_psu { -+ status = "okay"; -+}; -+ -+&cpu_b0 { -+ cpu-supply = <&vdd_cpu_big0_s0>; -+}; -+ -+&cpu_b1 { -+ cpu-supply = <&vdd_cpu_big0_s0>; -+}; -+ -+&cpu_b2 { -+ cpu-supply = <&vdd_cpu_big1_s0>; -+}; -+ -+&cpu_b3 { -+ cpu-supply = <&vdd_cpu_big1_s0>; -+}; -+ -+&cpu_l0 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l1 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l2 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l3 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&gmac1 { -+ clock_in_out = "output"; -+ phy-handle = <&rgmii_phy1>; -+ phy-mode = "rgmii-rxid"; -+ pinctrl-0 = <&gmac1_miim -+ &gmac1_tx_bus2 -+ &gmac1_rx_bus2 -+ &gmac1_rgmii_clk -+ &gmac1_rgmii_bus>; -+ pinctrl-names = "default"; -+ tx_delay = <0x42>; -+ status = "okay"; -+}; -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0m2_xfer>; -+ status = "okay"; -+ -+ vdd_cpu_big0_s0: regulator@42 { -+ compatible = "rockchip,rk8602"; -+ reg = <0x42>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu_big0_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_big1_s0: regulator@43 { -+ compatible = "rockchip,rk8603", "rockchip,rk8602"; -+ reg = <0x43>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu_big1_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+&i2c2 { -+ status = "okay"; -+ -+ vdd_npu_s0: regulator@42 { -+ compatible = "rockchip,rk8602"; -+ reg = <0x42>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_npu_s0"; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <2300>; -+ regulator-boot-on; -+ regulator-always-on; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+&i2c6 { -+ clock-frequency = <200000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c6m0_xfer>; -+ status = "okay"; -+ -+ hym8563: rtc@51 { -+ compatible = "haoyu,hym8563"; -+ reg = <0x51>; -+ #clock-cells = <0>; -+ clock-output-names = "hym8563"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rtc_int>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ wakeup-source; -+ }; -+}; -+ -+&mdio1 { -+ rgmii_phy1: ethernet-phy@1 { -+ compatible = "ethernet-phy-id001c.c916"; -+ reg = <0x1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rtl8211f_rst>; -+ reset-assert-us = <20000>; -+ reset-deassert-us = <100000>; -+ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; -+ }; -+}; -+ -+&pcie2x1l1 { -+ reset-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc_3v3_pcie20>; -+ status = "okay"; -+}; -+ -+&pcie2x1l2 { -+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc_3v3_pcie20>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ gpio-key { -+ key1_pin: key1-pin { -+ rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ gpio-leds { -+ sys_led_pin: sys-led-pin { -+ rockchip,pins = -+ <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wan_led_pin: wan-led-pin { -+ rockchip,pins = -+ <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ lan1_led_pin: lan1-led-pin { -+ rockchip,pins = -+ <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ lan2_led_pin: lan2-led-pin { -+ rockchip,pins = -+ <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ hym8563 { -+ rtc_int: rtc-int { -+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ sdmmc { -+ sd_s0_pwr: sd-s0-pwr { -+ rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ usb { -+ typec5v_pwren: typec5v-pwren { -+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ vcc5v0_host20_en: vcc5v0-host20-en { -+ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ rtl8211f { -+ rtl8211f_rst: rtl8211f-rst { -+ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&saradc { -+ vref-supply = <&avcc_1v8_s0>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ no-sdio; -+ no-sd; -+ non-removable; -+ mmc-hs200-1_8v; -+ status = "okay"; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ disable-wp; -+ max-frequency = <150000000>; -+ no-mmc; -+ no-sdio; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc_3v3_sd_s0>; -+ vqmmc-supply = <&vccio_sd_s0>; -+ status = "okay"; -+}; -+ -+&spi2 { -+ status = "okay"; -+ assigned-clocks = <&cru CLK_SPI2>; -+ assigned-clock-rates = <200000000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; -+ num-cs = <1>; -+ -+ pmic@0 { -+ compatible = "rockchip,rk806"; -+ spi-max-frequency = <1000000>; -+ reg = <0x0>; -+ -+ interrupt-parent = <&gpio0>; -+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, -+ <&rk806_dvs2_null>, <&rk806_dvs3_null>; -+ -+ system-power-controller; -+ -+ vcc1-supply = <&vcc5v0_sys>; -+ vcc2-supply = <&vcc5v0_sys>; -+ vcc3-supply = <&vcc5v0_sys>; -+ vcc4-supply = <&vcc5v0_sys>; -+ vcc5-supply = <&vcc5v0_sys>; -+ vcc6-supply = <&vcc5v0_sys>; -+ vcc7-supply = <&vcc5v0_sys>; -+ vcc8-supply = <&vcc5v0_sys>; -+ vcc9-supply = <&vcc5v0_sys>; -+ vcc10-supply = <&vcc5v0_sys>; -+ vcc11-supply = <&vcc_2v0_pldo_s3>; -+ vcc12-supply = <&vcc5v0_sys>; -+ vcc13-supply = <&vcc_1v1_nldo_s3>; -+ vcc14-supply = <&vcc_1v1_nldo_s3>; -+ vcca-supply = <&vcc5v0_sys>; -+ -+ gpio-controller; -+ #gpio-cells = <2>; -+ -+ rk806_dvs1_null: dvs1-null-pins { -+ pins = "gpio_pwrctrl1"; -+ function = "pin_fun0"; -+ }; -+ -+ rk806_dvs2_null: dvs2-null-pins { -+ pins = "gpio_pwrctrl2"; -+ function = "pin_fun0"; -+ }; -+ -+ rk806_dvs3_null: dvs3-null-pins { -+ pins = "gpio_pwrctrl3"; -+ function = "pin_fun0"; -+ }; -+ -+ regulators { -+ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_gpu_s0"; -+ regulator-enable-ramp-delay = <400>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_cpu_lit_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_log_s0: dcdc-reg3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <675000>; -+ regulator-max-microvolt = <750000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_log_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <750000>; -+ }; -+ }; -+ -+ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_vdenc_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_ddr_s0: dcdc-reg5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <675000>; -+ regulator-max-microvolt = <900000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_ddr_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <850000>; -+ }; -+ }; -+ -+ vdd2_ddr_s3: dcdc-reg6 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vdd2_ddr_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_2v0_pldo_s3: dcdc-reg7 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <2000000>; -+ regulator-max-microvolt = <2000000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_2v0_pldo_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <2000000>; -+ }; -+ }; -+ -+ vcc_3v3_s3: dcdc-reg8 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc_3v3_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vddq_ddr_s0: dcdc-reg9 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vddq_ddr_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8_s3: dcdc-reg10 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc_1v8_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ avcc_1v8_s0: pldo-reg1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "avcc_1v8_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc_1v8_s0: pldo-reg2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc_1v8_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ avdd_1v2_s0: pldo-reg3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <1200000>; -+ regulator-name = "avdd_1v2_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ avcc_3v3_s0: pldo-reg4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "avcc_3v3_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vccio_sd_s0: pldo-reg5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vccio_sd_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ pldo6_s3: pldo-reg6 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "pldo6_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vdd_0v75_s3: nldo-reg1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ regulator-name = "vdd_0v75_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <750000>; -+ }; -+ }; -+ -+ avdd_ddr_pll_s0: nldo-reg2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <850000>; -+ regulator-max-microvolt = <850000>; -+ regulator-name = "avdd_ddr_pll_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <850000>; -+ }; -+ }; -+ -+ avdd_0v75_s0: nldo-reg3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ regulator-name = "avdd_0v75_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ avdd_0v85_s0: nldo-reg4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <850000>; -+ regulator-max-microvolt = <850000>; -+ regulator-name = "avdd_0v85_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_0v75_s0: nldo-reg5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ regulator-name = "vdd_0v75_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&tsadc { -+ status = "okay"; -+}; -+ -+&u2phy2 { -+ status = "okay"; -+}; -+ -+&u2phy2_host { -+ phy-supply = <&vcc5v0_host_20>; -+ status = "okay"; -+}; -+ -+&uart2 { -+ pinctrl-0 = <&uart2m0_xfer>; -+ status = "okay"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; diff --git a/target/linux/rockchip/patches-6.6/032-v6.8-arm64-dts-rockchip-move-rk3588-serial-aliases-to-soc-dtsi.patch b/target/linux/rockchip/patches-6.6/032-v6.8-arm64-dts-rockchip-move-rk3588-serial-aliases-to-soc-dtsi.patch deleted file mode 100644 index 88919893a3..0000000000 --- a/target/linux/rockchip/patches-6.6/032-v6.8-arm64-dts-rockchip-move-rk3588-serial-aliases-to-soc-dtsi.patch +++ /dev/null @@ -1,129 +0,0 @@ -From 9918d10d16665527e59fdb87c5acac70cc1cfe8f Mon Sep 17 00:00:00 2001 -From: Heiko Stuebner -Date: Tue, 5 Dec 2023 17:48:39 +0100 -Subject: [PATCH] arm64: dts: rockchip: move rk3588 serial aliases to soc dtsi - -The serial ports on rk3588 are named uart0 - uart9. Board schematics -also use these exact numbers and we want those names to also reflect -in the OS devices because everything else would just cause confusion. - -To prevent each board repeating their list of serial aliases, move them -to the soc dtsi, as all previous Rockchip soc do already. - -Signed-off-by: Heiko Stuebner -Reviewed-by: Dragan Simic -Link: https://lore.kernel.org/r/20231205164842.556684-2-heiko@sntech.de ---- - .../boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts | 4 ---- - .../boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts | 4 ---- - arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 1 - - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 1 - - .../boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 1 - - arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts | 1 - - arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 1 - - arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 2 -- - .../boot/dts/rockchip/rk3588s-indiedroid-nova.dts | 1 - - .../boot/dts/rockchip/rk3588s-khadas-edge2.dts | 1 - - arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts | 1 - - arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 1 - - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 13 +++++++++++++ - 13 files changed, 13 insertions(+), 19 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts -@@ -12,10 +12,6 @@ - compatible = "edgeble,neural-compute-module-6a-io", - "edgeble,neural-compute-module-6a", "rockchip,rk3588"; - -- aliases { -- serial2 = &uart2; -- }; -- - chosen { - stdout-path = "serial2:1500000n8"; - }; ---- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts -@@ -12,10 +12,6 @@ - compatible = "edgeble,neural-compute-module-6b-io", - "edgeble,neural-compute-module-6b", "rockchip,rk3588"; - -- aliases { -- serial2 = &uart2; -- }; -- - chosen { - stdout-path = "serial2:1500000n8"; - }; ---- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts -@@ -16,7 +16,6 @@ - - aliases { - mmc0 = &sdhci; -- serial2 = &uart2; - }; - - chosen { ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts -@@ -19,7 +19,6 @@ - aliases { - mmc0 = &sdhci; - mmc1 = &sdmmc; -- serial2 = &uart2; - }; - - chosen { ---- a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts -@@ -15,7 +15,6 @@ - mmc0 = &sdhci; - mmc1 = &sdmmc; - mmc2 = &sdio; -- serial2 = &uart2; - }; - - chosen { ---- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -@@ -12,7 +12,6 @@ - - aliases { - mmc0 = &sdhci; -- serial2 = &uart2; - }; - - chosen { ---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -@@ -14,7 +14,6 @@ - aliases { - mmc0 = &sdhci; - mmc1 = &sdmmc; -- serial2 = &uart2; - }; - - analog-sound { ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -18,6 +18,19 @@ - #address-cells = <2>; - #size-cells = <2>; - -+ aliases { -+ serial0 = &uart0; -+ serial1 = &uart1; -+ serial2 = &uart2; -+ serial3 = &uart3; -+ serial4 = &uart4; -+ serial5 = &uart5; -+ serial6 = &uart6; -+ serial7 = &uart7; -+ serial8 = &uart8; -+ serial9 = &uart9; -+ }; -+ - cpus { - #address-cells = <1>; - #size-cells = <0>; diff --git a/target/linux/rockchip/patches-6.6/033-v6.8-arm64-dts-rockchip-add-rk3588-i2c-aliases-to-soc-dtsi.patch b/target/linux/rockchip/patches-6.6/033-v6.8-arm64-dts-rockchip-add-rk3588-i2c-aliases-to-soc-dtsi.patch deleted file mode 100644 index 2daaec3953..0000000000 --- a/target/linux/rockchip/patches-6.6/033-v6.8-arm64-dts-rockchip-add-rk3588-i2c-aliases-to-soc-dtsi.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 328e901b7b03d292c1520ffb38e9164feef4f1ea Mon Sep 17 00:00:00 2001 -From: Heiko Stuebner -Date: Tue, 5 Dec 2023 17:48:40 +0100 -Subject: [PATCH] arm64: dts: rockchip: add rk3588 i2c aliases to soc dtsi - -The i2c controllers on rk3588 are named i2c0 - i2c8. Board schematics -also use these exact numbers and we want those names to also reflect -in the OS devices because everything else would just cause confusion. -Userspace i2c access is a thing afterall. - -To prevent each board repeating their list of i2c aliases, define them -in the soc dtsi, as all previous Rockchip soc do already. - -Signed-off-by: Heiko Stuebner -Reviewed-by: Dragan Simic -Link: https://lore.kernel.org/r/20231205164842.556684-3-heiko@sntech.de ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -19,6 +19,15 @@ - #size-cells = <2>; - - aliases { -+ i2c0 = &i2c0; -+ i2c1 = &i2c1; -+ i2c2 = &i2c2; -+ i2c3 = &i2c3; -+ i2c4 = &i2c4; -+ i2c5 = &i2c5; -+ i2c6 = &i2c6; -+ i2c7 = &i2c7; -+ i2c8 = &i2c8; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; diff --git a/target/linux/rockchip/patches-6.6/034-v6.8-arm64-dts-rockchip-add-rk3588-gpio-aliases-to-soc-dtsi.patch b/target/linux/rockchip/patches-6.6/034-v6.8-arm64-dts-rockchip-add-rk3588-gpio-aliases-to-soc-dtsi.patch deleted file mode 100644 index 19e6c6a4f5..0000000000 --- a/target/linux/rockchip/patches-6.6/034-v6.8-arm64-dts-rockchip-add-rk3588-gpio-aliases-to-soc-dtsi.patch +++ /dev/null @@ -1,34 +0,0 @@ -From a024abedbca99a20aeb96f5beec9ded13c85dcb3 Mon Sep 17 00:00:00 2001 -From: Heiko Stuebner -Date: Tue, 5 Dec 2023 17:48:41 +0100 -Subject: [PATCH] arm64: dts: rockchip: add rk3588 gpio aliases to soc dtsi - -The gpio controllers on rk3588 are named gpio0 - gpio4. Board schematics -also use these exact numbers and we want those names to also reflect -in the OS devices because everything else would just cause confusion. -Userspace gpio access is a thing afterall. - -To prevent each board repeating their list of gpio aliases, define them -in the soc dtsi, as previous Rockchip soc like the rk356x do already. - -Signed-off-by: Heiko Stuebner -Reviewed-by: Dragan Simic -Link: https://lore.kernel.org/r/20231205164842.556684-4-heiko@sntech.de ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -19,6 +19,11 @@ - #size-cells = <2>; - - aliases { -+ gpio0 = &gpio0; -+ gpio1 = &gpio1; -+ gpio2 = &gpio2; -+ gpio3 = &gpio3; -+ gpio4 = &gpio4; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; diff --git a/target/linux/rockchip/patches-6.6/035-v6.8-arm64-dts-rockchip-add-rk3588-spi-aliases-to-soc-dtsi.patch b/target/linux/rockchip/patches-6.6/035-v6.8-arm64-dts-rockchip-add-rk3588-spi-aliases-to-soc-dtsi.patch deleted file mode 100644 index 6a66d99668..0000000000 --- a/target/linux/rockchip/patches-6.6/035-v6.8-arm64-dts-rockchip-add-rk3588-spi-aliases-to-soc-dtsi.patch +++ /dev/null @@ -1,34 +0,0 @@ -From a86e88043de929da76f7f6cf0990ba92aed8391a Mon Sep 17 00:00:00 2001 -From: Heiko Stuebner -Date: Tue, 5 Dec 2023 17:48:42 +0100 -Subject: [PATCH] arm64: dts: rockchip: add rk3588 spi aliases to soc dtsi - -The spi controllers on rk3588 are named spi0 - spi4. Board schematics -also use these exact numbers and we want those names to also reflect -in the OS devices because everything else would just cause confusion. -Userspace spi access is a thing afterall. - -To prevent each board repeating their list of spi aliases, define them -in the soc dtsi, as previous Rockchip soc like the rk356x do already. - -Signed-off-by: Heiko Stuebner -Reviewed-by: Dragan Simic -Link: https://lore.kernel.org/r/20231205164842.556684-5-heiko@sntech.de ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -43,6 +43,11 @@ - serial7 = &uart7; - serial8 = &uart8; - serial9 = &uart9; -+ spi0 = &spi0; -+ spi1 = &spi1; -+ spi2 = &spi2; -+ spi3 = &spi3; -+ spi4 = &spi4; - }; - - cpus { diff --git a/target/linux/rockchip/patches-6.6/040-v6.8-arm64-dts-rockchip-add-gpio-line-names-to-rk3308-roc.patch b/target/linux/rockchip/patches-6.6/040-v6.8-arm64-dts-rockchip-add-gpio-line-names-to-rk3308-roc.patch deleted file mode 100644 index 83ebe67789..0000000000 --- a/target/linux/rockchip/patches-6.6/040-v6.8-arm64-dts-rockchip-add-gpio-line-names-to-rk3308-roc.patch +++ /dev/null @@ -1,84 +0,0 @@ -From c45de75d7a9ab44a15dedc7a121d6371d6891301 Mon Sep 17 00:00:00 2001 -From: Trevor Woerner -Date: Mon, 20 Nov 2023 11:22:32 -0500 -Subject: [PATCH] arm64: dts: rockchip: add gpio-line-names to rk3308-rock-pi-s - -Add names to the pins of the general-purpose expansion header as given in the -Radxa GPIO page[1] following the conventions in the kernel documentation[2] to -make it easier for users to correlate the pins with functions when using -utilities such as gpioinfo. - -[1] https://wiki.radxa.com/RockpiS/hardware/gpio -[2] Documentation/devicetree/bindings/gpio/gpio.txt - -Signed-off-by: Trevor Woerner -Link: https://lore.kernel.org/r/20231120162232.27653-1-twoerner@gmail.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3308-rock-pi-s.dts | 58 +++++++++++++++++++ - 1 file changed, 58 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts -@@ -315,3 +315,61 @@ - &wdt { - status = "okay"; - }; -+ -+&gpio0 { -+ gpio-line-names = -+ /* GPIO0_A0 - A7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO0_B0 - B7 */ -+ "", "", "", "header1-pin3 [GPIO0_B3]", "header1-pin5 [GPIO0_B4]", -+ "", "", "header1-pin11 [GPIO0_B7]", -+ /* GPIO0_C0 - C7 */ -+ "header1-pin13 [GPIO0_C0]", "header1-pin15 [GPIO0_C1]", "", "", "", -+ "", "", "", -+ /* GPIO0_D0 - D8 */ -+ "", "", "", "", "", "", "", ""; -+}; -+ -+&gpio1 { -+ gpio-line-names = -+ /* GPIO1_A0 - A7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO1_B0 - B7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO1_C0 - C7 */ -+ "", "", "", "", "", "", "header1-pin21 [GPIO1_C6]", -+ "header1-pin19 [GPIO1_C7]", -+ /* GPIO1_D0 - D8 */ -+ "header1-pin23 [GPIO1_D0]", "header1-pin24 [GPIO1_D1]", "", "", "", -+ "", "", ""; -+}; -+ -+&gpio2 { -+ gpio-line-names = -+ /* GPIO2_A0 - A7 */ -+ "header1-pin10 [GPIO2_A0]", "header1-pin8 [GPIO2_A1]", "", "", -+ "header1-pin7 [GPIO2_A4]", "header1-pin12 [GPIO2_A5]", -+ "header2-pin46 [GPIO2_A6]", "header1-pin22 [GPIO1_A7]", -+ /* GPIO2_B0 - B7 */ -+ "header2-pin45 [GPIO2_B0]", "header1-pin18 [GPIO2_B1]", -+ "header1-pin16 [GPIO2_B2]", "header2-pin44 [GPIO2_B3]", -+ "header2-pin43 [GPIO2_B4]", "header2-pin28 [GPIO2_B5]", -+ "header2-pin30 [GPIO2_B6]", "header2-pin32 [GPIO2_B7]", -+ /* GPIO2_C0 - C7 */ -+ "header2-pin34 [GPIO2_C0]", "", "", "", "", "", "", "", -+ /* GPIO2_D0 - D8 */ -+ "", "", "", "", "", "", "", ""; -+}; -+ -+&gpio3 { -+ gpio-line-names = -+ /* GPIO3_A0 - A7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO3_B0 - B7 */ -+ "", "", "header2-pin42 [GPIO3_B2]", "header2-pin41 [GPIO3_B3]", -+ "header2-pin40 [GPIO3_B4]", "header2-pin39 [GPIO3_B5]", "", "", -+ /* GPIO3_C0 - C7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO3_D0 - D8 */ -+ "", "", "", "", "", "", "", ""; -+}; diff --git a/target/linux/rockchip/patches-6.6/041-v6.8-arm64-dts-rockchip-rk3308-rock-pi-s-gpio-line-names-.patch b/target/linux/rockchip/patches-6.6/041-v6.8-arm64-dts-rockchip-rk3308-rock-pi-s-gpio-line-names-.patch deleted file mode 100644 index 994644e142..0000000000 --- a/target/linux/rockchip/patches-6.6/041-v6.8-arm64-dts-rockchip-rk3308-rock-pi-s-gpio-line-names-.patch +++ /dev/null @@ -1,152 +0,0 @@ -From 085021cc825ed90a6ddc4406f608fb8a85745f81 Mon Sep 17 00:00:00 2001 -From: Trevor Woerner -Date: Tue, 19 Dec 2023 12:38:13 -0500 -Subject: [PATCH] arm64: dts: rockchip: rk3308-rock-pi-s gpio-line-names - cleanup - -Perform the following cleanups on a previous patch: -- indent lines after "gpio-line-names" -- fix D0-D8 -> D0-D7 -- sort phandle references - -Fixes: c45de75d7a9a ("arm64: dts: rockchip: add gpio-line-names to rk3308-rock-pi-s") -Signed-off-by: Trevor Woerner -Link: https://lore.kernel.org/r/20231219173814.1569-1-twoerner@gmail.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3308-rock-pi-s.dts | 120 +++++++++--------- - 1 file changed, 62 insertions(+), 58 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts -@@ -166,6 +166,68 @@ - }; - }; - -+&gpio0 { -+ gpio-line-names = -+ /* GPIO0_A0 - A7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO0_B0 - B7 */ -+ "", "", "", "header1-pin3 [GPIO0_B3]", -+ "header1-pin5 [GPIO0_B4]", "", "", -+ "header1-pin11 [GPIO0_B7]", -+ /* GPIO0_C0 - C7 */ -+ "header1-pin13 [GPIO0_C0]", -+ "header1-pin15 [GPIO0_C1]", "", "", "", -+ "", "", "", -+ /* GPIO0_D0 - D7 */ -+ "", "", "", "", "", "", "", ""; -+}; -+ -+&gpio1 { -+ gpio-line-names = -+ /* GPIO1_A0 - A7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO1_B0 - B7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO1_C0 - C7 */ -+ "", "", "", "", "", "", "header1-pin21 [GPIO1_C6]", -+ "header1-pin19 [GPIO1_C7]", -+ /* GPIO1_D0 - D7 */ -+ "header1-pin23 [GPIO1_D0]", "header1-pin24 [GPIO1_D1]", -+ "", "", "", "", "", ""; -+}; -+ -+&gpio2 { -+ gpio-line-names = -+ /* GPIO2_A0 - A7 */ -+ "header1-pin10 [GPIO2_A0]", "header1-pin8 [GPIO2_A1]", -+ "", "", -+ "header1-pin7 [GPIO2_A4]", "header1-pin12 [GPIO2_A5]", -+ "header2-pin46 [GPIO2_A6]", "header1-pin22 [GPIO1_A7]", -+ /* GPIO2_B0 - B7 */ -+ "header2-pin45 [GPIO2_B0]", "header1-pin18 [GPIO2_B1]", -+ "header1-pin16 [GPIO2_B2]", "header2-pin44 [GPIO2_B3]", -+ "header2-pin43 [GPIO2_B4]", "header2-pin28 [GPIO2_B5]", -+ "header2-pin30 [GPIO2_B6]", "header2-pin32 [GPIO2_B7]", -+ /* GPIO2_C0 - C7 */ -+ "header2-pin34 [GPIO2_C0]", "", "", "", "", "", "", "", -+ /* GPIO2_D0 - D7 */ -+ "", "", "", "", "", "", "", ""; -+}; -+ -+&gpio3 { -+ gpio-line-names = -+ /* GPIO3_A0 - A7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO3_B0 - B7 */ -+ "", "", "header2-pin42 [GPIO3_B2]", -+ "header2-pin41 [GPIO3_B3]", "header2-pin40 [GPIO3_B4]", -+ "header2-pin39 [GPIO3_B5]", "", "", -+ /* GPIO3_C0 - C7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO3_D0 - D7 */ -+ "", "", "", "", "", "", "", ""; -+}; -+ - &i2c1 { - status = "okay"; - }; -@@ -315,61 +377,3 @@ - &wdt { - status = "okay"; - }; -- --&gpio0 { -- gpio-line-names = -- /* GPIO0_A0 - A7 */ -- "", "", "", "", "", "", "", "", -- /* GPIO0_B0 - B7 */ -- "", "", "", "header1-pin3 [GPIO0_B3]", "header1-pin5 [GPIO0_B4]", -- "", "", "header1-pin11 [GPIO0_B7]", -- /* GPIO0_C0 - C7 */ -- "header1-pin13 [GPIO0_C0]", "header1-pin15 [GPIO0_C1]", "", "", "", -- "", "", "", -- /* GPIO0_D0 - D8 */ -- "", "", "", "", "", "", "", ""; --}; -- --&gpio1 { -- gpio-line-names = -- /* GPIO1_A0 - A7 */ -- "", "", "", "", "", "", "", "", -- /* GPIO1_B0 - B7 */ -- "", "", "", "", "", "", "", "", -- /* GPIO1_C0 - C7 */ -- "", "", "", "", "", "", "header1-pin21 [GPIO1_C6]", -- "header1-pin19 [GPIO1_C7]", -- /* GPIO1_D0 - D8 */ -- "header1-pin23 [GPIO1_D0]", "header1-pin24 [GPIO1_D1]", "", "", "", -- "", "", ""; --}; -- --&gpio2 { -- gpio-line-names = -- /* GPIO2_A0 - A7 */ -- "header1-pin10 [GPIO2_A0]", "header1-pin8 [GPIO2_A1]", "", "", -- "header1-pin7 [GPIO2_A4]", "header1-pin12 [GPIO2_A5]", -- "header2-pin46 [GPIO2_A6]", "header1-pin22 [GPIO1_A7]", -- /* GPIO2_B0 - B7 */ -- "header2-pin45 [GPIO2_B0]", "header1-pin18 [GPIO2_B1]", -- "header1-pin16 [GPIO2_B2]", "header2-pin44 [GPIO2_B3]", -- "header2-pin43 [GPIO2_B4]", "header2-pin28 [GPIO2_B5]", -- "header2-pin30 [GPIO2_B6]", "header2-pin32 [GPIO2_B7]", -- /* GPIO2_C0 - C7 */ -- "header2-pin34 [GPIO2_C0]", "", "", "", "", "", "", "", -- /* GPIO2_D0 - D8 */ -- "", "", "", "", "", "", "", ""; --}; -- --&gpio3 { -- gpio-line-names = -- /* GPIO3_A0 - A7 */ -- "", "", "", "", "", "", "", "", -- /* GPIO3_B0 - B7 */ -- "", "", "header2-pin42 [GPIO3_B2]", "header2-pin41 [GPIO3_B3]", -- "header2-pin40 [GPIO3_B4]", "header2-pin39 [GPIO3_B5]", "", "", -- /* GPIO3_C0 - C7 */ -- "", "", "", "", "", "", "", "", -- /* GPIO3_D0 - D8 */ -- "", "", "", "", "", "", "", ""; --}; diff --git a/target/linux/rockchip/patches-6.6/047-v6.11-arm64-dts-rockchip-Add-io-domains-to-rk3308-rock-pi-.patch b/target/linux/rockchip/patches-6.6/047-v6.11-arm64-dts-rockchip-Add-io-domains-to-rk3308-rock-pi-.patch deleted file mode 100644 index ad746df3b0..0000000000 --- a/target/linux/rockchip/patches-6.6/047-v6.11-arm64-dts-rockchip-Add-io-domains-to-rk3308-rock-pi-.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 100b3bdee6035192f6d4a1847970fe004bb505fb Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Tue, 21 May 2024 21:10:15 +0000 -Subject: [PATCH] arm64: dts: rockchip: Add io-domains to rk3308-rock-pi-s - -The VCCIO4 io-domain used for WiFi/BT is using 1v8 IO signal voltage. - -Add io-domains node with the VCCIO supplies connected on the board. - -Signed-off-by: Jonas Karlman -Link: https://lore.kernel.org/r/20240521211029.1236094-13-jonas@kwiboo.se -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts -@@ -232,6 +232,16 @@ - status = "okay"; - }; - -+&io_domains { -+ vccio0-supply = <&vcc_io>; -+ vccio1-supply = <&vcc_io>; -+ vccio2-supply = <&vcc_io>; -+ vccio3-supply = <&vcc_io>; -+ vccio4-supply = <&vcc_1v8>; -+ vccio5-supply = <&vcc_io>; -+ status = "okay"; -+}; -+ - &pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&rtc_32k>; diff --git a/target/linux/rockchip/patches-6.6/050-01-v6.8-arm64-dts-rockchip-move-rk3588-serial-aliases-to-soc-dtsi.patch b/target/linux/rockchip/patches-6.6/050-01-v6.8-arm64-dts-rockchip-move-rk3588-serial-aliases-to-soc-dtsi.patch new file mode 100644 index 0000000000..88919893a3 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/050-01-v6.8-arm64-dts-rockchip-move-rk3588-serial-aliases-to-soc-dtsi.patch @@ -0,0 +1,129 @@ +From 9918d10d16665527e59fdb87c5acac70cc1cfe8f Mon Sep 17 00:00:00 2001 +From: Heiko Stuebner +Date: Tue, 5 Dec 2023 17:48:39 +0100 +Subject: [PATCH] arm64: dts: rockchip: move rk3588 serial aliases to soc dtsi + +The serial ports on rk3588 are named uart0 - uart9. Board schematics +also use these exact numbers and we want those names to also reflect +in the OS devices because everything else would just cause confusion. + +To prevent each board repeating their list of serial aliases, move them +to the soc dtsi, as all previous Rockchip soc do already. + +Signed-off-by: Heiko Stuebner +Reviewed-by: Dragan Simic +Link: https://lore.kernel.org/r/20231205164842.556684-2-heiko@sntech.de +--- + .../boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts | 4 ---- + .../boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts | 4 ---- + arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 1 - + arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 1 - + .../boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 1 - + arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts | 1 - + arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 1 - + arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 2 -- + .../boot/dts/rockchip/rk3588s-indiedroid-nova.dts | 1 - + .../boot/dts/rockchip/rk3588s-khadas-edge2.dts | 1 - + arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts | 1 - + arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 1 - + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 13 +++++++++++++ + 13 files changed, 13 insertions(+), 19 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts +@@ -12,10 +12,6 @@ + compatible = "edgeble,neural-compute-module-6a-io", + "edgeble,neural-compute-module-6a", "rockchip,rk3588"; + +- aliases { +- serial2 = &uart2; +- }; +- + chosen { + stdout-path = "serial2:1500000n8"; + }; +--- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts +@@ -12,10 +12,6 @@ + compatible = "edgeble,neural-compute-module-6b-io", + "edgeble,neural-compute-module-6b", "rockchip,rk3588"; + +- aliases { +- serial2 = &uart2; +- }; +- + chosen { + stdout-path = "serial2:1500000n8"; + }; +--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +@@ -16,7 +16,6 @@ + + aliases { + mmc0 = &sdhci; +- serial2 = &uart2; + }; + + chosen { +--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts +@@ -19,7 +19,6 @@ + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; +- serial2 = &uart2; + }; + + chosen { +--- a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts +@@ -15,7 +15,6 @@ + mmc0 = &sdhci; + mmc1 = &sdmmc; + mmc2 = &sdio; +- serial2 = &uart2; + }; + + chosen { +--- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +@@ -12,7 +12,6 @@ + + aliases { + mmc0 = &sdhci; +- serial2 = &uart2; + }; + + chosen { +--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +@@ -14,7 +14,6 @@ + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; +- serial2 = &uart2; + }; + + analog-sound { +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -18,6 +18,19 @@ + #address-cells = <2>; + #size-cells = <2>; + ++ aliases { ++ serial0 = &uart0; ++ serial1 = &uart1; ++ serial2 = &uart2; ++ serial3 = &uart3; ++ serial4 = &uart4; ++ serial5 = &uart5; ++ serial6 = &uart6; ++ serial7 = &uart7; ++ serial8 = &uart8; ++ serial9 = &uart9; ++ }; ++ + cpus { + #address-cells = <1>; + #size-cells = <0>; diff --git a/target/linux/rockchip/patches-6.6/050-02-v6.8-arm64-dts-rockchip-add-rk3588-i2c-aliases-to-soc-dtsi.patch b/target/linux/rockchip/patches-6.6/050-02-v6.8-arm64-dts-rockchip-add-rk3588-i2c-aliases-to-soc-dtsi.patch new file mode 100644 index 0000000000..2daaec3953 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/050-02-v6.8-arm64-dts-rockchip-add-rk3588-i2c-aliases-to-soc-dtsi.patch @@ -0,0 +1,38 @@ +From 328e901b7b03d292c1520ffb38e9164feef4f1ea Mon Sep 17 00:00:00 2001 +From: Heiko Stuebner +Date: Tue, 5 Dec 2023 17:48:40 +0100 +Subject: [PATCH] arm64: dts: rockchip: add rk3588 i2c aliases to soc dtsi + +The i2c controllers on rk3588 are named i2c0 - i2c8. Board schematics +also use these exact numbers and we want those names to also reflect +in the OS devices because everything else would just cause confusion. +Userspace i2c access is a thing afterall. + +To prevent each board repeating their list of i2c aliases, define them +in the soc dtsi, as all previous Rockchip soc do already. + +Signed-off-by: Heiko Stuebner +Reviewed-by: Dragan Simic +Link: https://lore.kernel.org/r/20231205164842.556684-3-heiko@sntech.de +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -19,6 +19,15 @@ + #size-cells = <2>; + + aliases { ++ i2c0 = &i2c0; ++ i2c1 = &i2c1; ++ i2c2 = &i2c2; ++ i2c3 = &i2c3; ++ i2c4 = &i2c4; ++ i2c5 = &i2c5; ++ i2c6 = &i2c6; ++ i2c7 = &i2c7; ++ i2c8 = &i2c8; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; diff --git a/target/linux/rockchip/patches-6.6/050-03-v6.8-arm64-dts-rockchip-add-rk3588-gpio-aliases-to-soc-dtsi.patch b/target/linux/rockchip/patches-6.6/050-03-v6.8-arm64-dts-rockchip-add-rk3588-gpio-aliases-to-soc-dtsi.patch new file mode 100644 index 0000000000..19e6c6a4f5 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/050-03-v6.8-arm64-dts-rockchip-add-rk3588-gpio-aliases-to-soc-dtsi.patch @@ -0,0 +1,34 @@ +From a024abedbca99a20aeb96f5beec9ded13c85dcb3 Mon Sep 17 00:00:00 2001 +From: Heiko Stuebner +Date: Tue, 5 Dec 2023 17:48:41 +0100 +Subject: [PATCH] arm64: dts: rockchip: add rk3588 gpio aliases to soc dtsi + +The gpio controllers on rk3588 are named gpio0 - gpio4. Board schematics +also use these exact numbers and we want those names to also reflect +in the OS devices because everything else would just cause confusion. +Userspace gpio access is a thing afterall. + +To prevent each board repeating their list of gpio aliases, define them +in the soc dtsi, as previous Rockchip soc like the rk356x do already. + +Signed-off-by: Heiko Stuebner +Reviewed-by: Dragan Simic +Link: https://lore.kernel.org/r/20231205164842.556684-4-heiko@sntech.de +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -19,6 +19,11 @@ + #size-cells = <2>; + + aliases { ++ gpio0 = &gpio0; ++ gpio1 = &gpio1; ++ gpio2 = &gpio2; ++ gpio3 = &gpio3; ++ gpio4 = &gpio4; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; diff --git a/target/linux/rockchip/patches-6.6/050-04-v6.8-arm64-dts-rockchip-add-rk3588-spi-aliases-to-soc-dtsi.patch b/target/linux/rockchip/patches-6.6/050-04-v6.8-arm64-dts-rockchip-add-rk3588-spi-aliases-to-soc-dtsi.patch new file mode 100644 index 0000000000..6a66d99668 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/050-04-v6.8-arm64-dts-rockchip-add-rk3588-spi-aliases-to-soc-dtsi.patch @@ -0,0 +1,34 @@ +From a86e88043de929da76f7f6cf0990ba92aed8391a Mon Sep 17 00:00:00 2001 +From: Heiko Stuebner +Date: Tue, 5 Dec 2023 17:48:42 +0100 +Subject: [PATCH] arm64: dts: rockchip: add rk3588 spi aliases to soc dtsi + +The spi controllers on rk3588 are named spi0 - spi4. Board schematics +also use these exact numbers and we want those names to also reflect +in the OS devices because everything else would just cause confusion. +Userspace spi access is a thing afterall. + +To prevent each board repeating their list of spi aliases, define them +in the soc dtsi, as previous Rockchip soc like the rk356x do already. + +Signed-off-by: Heiko Stuebner +Reviewed-by: Dragan Simic +Link: https://lore.kernel.org/r/20231205164842.556684-5-heiko@sntech.de +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -43,6 +43,11 @@ + serial7 = &uart7; + serial8 = &uart8; + serial9 = &uart9; ++ spi0 = &spi0; ++ spi1 = &spi1; ++ spi2 = &spi2; ++ spi3 = &spi3; ++ spi4 = &spi4; + }; + + cpus { diff --git a/target/linux/rockchip/patches-6.6/053-v6.9-arm64-dts-rockchip-Add-support-for-NanoPi-R6S.patch b/target/linux/rockchip/patches-6.6/053-v6.9-arm64-dts-rockchip-Add-support-for-NanoPi-R6S.patch new file mode 100644 index 0000000000..e5afbb4f40 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/053-v6.9-arm64-dts-rockchip-Add-support-for-NanoPi-R6S.patch @@ -0,0 +1,792 @@ +From f1b11f43b3e983b26d8010fc43ba6c2b979826f2 Mon Sep 17 00:00:00 2001 +From: Muhammed Efe Cetin +Date: Sat, 30 Dec 2023 14:18:00 +0300 +Subject: [PATCH] arm64: dts: rockchip: Add support for NanoPi R6S + +Add basic NanoPi R6S support that comes with USB2, PCIe, SD card, eMMC +support. + +Signed-off-by: Muhammed Efe Cetin +Link: https://lore.kernel.org/r/6db3b653efc6f0a2dca8e96fdd0503906db72fb6.1703934548.git.efectn@protonmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../boot/dts/rockchip/rk3588s-nanopi-r6s.dts | 764 ++++++++++++++++++ + 2 files changed, 765 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts + +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -104,4 +104,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-na + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-indiedroid-nova.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts +@@ -0,0 +1,764 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include ++#include ++#include ++#include "rk3588s.dtsi" ++ ++/ { ++ model = "FriendlyElec NanoPi R6S"; ++ compatible = "friendlyarm,nanopi-r6s", "rockchip,rk3588s"; ++ ++ aliases { ++ ethernet0 = &gmac1; ++ mmc0 = &sdmmc; ++ mmc1 = &sdhci; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ adc-keys { ++ compatible = "adc-keys"; ++ io-channels = <&saradc 0>; ++ io-channel-names = "buttons"; ++ keyup-threshold-microvolt = <1800000>; ++ poll-interval = <100>; ++ ++ button-maskrom { ++ label = "Maskrom"; ++ linux,code = ; ++ press-threshold-microvolt = <1800>; ++ }; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&key1_pin>; ++ ++ button-user { ++ label = "User"; ++ linux,code = ; ++ gpios = <&gpio1 RK_PC0 GPIO_ACTIVE_LOW>; ++ debounce-interval = <50>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ sys_led: led-0 { ++ label = "sys_led"; ++ gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sys_led_pin>; ++ }; ++ ++ wan_led: led-1 { ++ label = "wan_led"; ++ gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wan_led_pin>; ++ }; ++ ++ lan1_led: led-2 { ++ label = "lan1_led"; ++ gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&lan1_led_pin>; ++ }; ++ ++ lan2_led: led-3 { ++ label = "lan2_led"; ++ gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&lan2_led_pin>; ++ }; ++ }; ++ ++ vcc5v0_sys: vcc5v0-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_1v1_nldo_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc_3v3_s0: vcc-3v3-s0-regulator { ++ compatible = "regulator-fixed"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc_3v3_s0"; ++ vin-supply = <&vcc_3v3_s3>; ++ }; ++ ++ vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sd_s0_pwr>; ++ regulator-name = "vcc_3v3_sd_s0"; ++ regulator-boot-on; ++ regulator-max-microvolt = <3000000>; ++ regulator-min-microvolt = <3000000>; ++ vin-supply = <&vcc_3v3_s3>; ++ }; ++ ++ vcc_3v3_pcie20: vcc3v3-pcie20-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_3v3_pcie20"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_3v3_s3>; ++ }; ++ ++ vcc5v0_usb: vcc5v0-usb-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_usb"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_usb_otg0: vcc5v0-usb-otg0-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&typec5v_pwren>; ++ regulator-name = "vcc5v0_usb_otg0"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_usb>; ++ }; ++ ++ vcc5v0_host_20: vcc5v0-host-20-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_host20_en>; ++ regulator-name = "vcc5v0_host_20"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_usb>; ++ }; ++}; ++ ++&combphy0_ps { ++ status = "okay"; ++}; ++ ++&combphy2_psu { ++ status = "okay"; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_big0_s0>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_big0_s0>; ++}; ++ ++&cpu_b2 { ++ cpu-supply = <&vdd_cpu_big1_s0>; ++}; ++ ++&cpu_b3 { ++ cpu-supply = <&vdd_cpu_big1_s0>; ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&gmac1 { ++ clock_in_out = "output"; ++ phy-handle = <&rgmii_phy1>; ++ phy-mode = "rgmii-rxid"; ++ pinctrl-0 = <&gmac1_miim ++ &gmac1_tx_bus2 ++ &gmac1_rx_bus2 ++ &gmac1_rgmii_clk ++ &gmac1_rgmii_bus>; ++ pinctrl-names = "default"; ++ tx_delay = <0x42>; ++ status = "okay"; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0m2_xfer>; ++ status = "okay"; ++ ++ vdd_cpu_big0_s0: regulator@42 { ++ compatible = "rockchip,rk8602"; ++ reg = <0x42>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_big0_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_big1_s0: regulator@43 { ++ compatible = "rockchip,rk8603", "rockchip,rk8602"; ++ reg = <0x43>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_big1_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&i2c2 { ++ status = "okay"; ++ ++ vdd_npu_s0: regulator@42 { ++ compatible = "rockchip,rk8602"; ++ reg = <0x42>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_npu_s0"; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <2300>; ++ regulator-boot-on; ++ regulator-always-on; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&i2c6 { ++ clock-frequency = <200000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c6m0_xfer>; ++ status = "okay"; ++ ++ hym8563: rtc@51 { ++ compatible = "haoyu,hym8563"; ++ reg = <0x51>; ++ #clock-cells = <0>; ++ clock-output-names = "hym8563"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rtc_int>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ wakeup-source; ++ }; ++}; ++ ++&mdio1 { ++ rgmii_phy1: ethernet-phy@1 { ++ compatible = "ethernet-phy-id001c.c916"; ++ reg = <0x1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rtl8211f_rst>; ++ reset-assert-us = <20000>; ++ reset-deassert-us = <100000>; ++ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&pcie2x1l1 { ++ reset-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc_3v3_pcie20>; ++ status = "okay"; ++}; ++ ++&pcie2x1l2 { ++ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc_3v3_pcie20>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ gpio-key { ++ key1_pin: key1-pin { ++ rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ gpio-leds { ++ sys_led_pin: sys-led-pin { ++ rockchip,pins = ++ <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wan_led_pin: wan-led-pin { ++ rockchip,pins = ++ <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ lan1_led_pin: lan1-led-pin { ++ rockchip,pins = ++ <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ lan2_led_pin: lan2-led-pin { ++ rockchip,pins = ++ <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ hym8563 { ++ rtc_int: rtc-int { ++ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ sdmmc { ++ sd_s0_pwr: sd-s0-pwr { ++ rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ usb { ++ typec5v_pwren: typec5v-pwren { ++ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ vcc5v0_host20_en: vcc5v0-host20-en { ++ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ rtl8211f { ++ rtl8211f_rst: rtl8211f-rst { ++ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&saradc { ++ vref-supply = <&avcc_1v8_s0>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ no-sdio; ++ no-sd; ++ non-removable; ++ mmc-hs200-1_8v; ++ status = "okay"; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ disable-wp; ++ max-frequency = <150000000>; ++ no-mmc; ++ no-sdio; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc_3v3_sd_s0>; ++ vqmmc-supply = <&vccio_sd_s0>; ++ status = "okay"; ++}; ++ ++&spi2 { ++ status = "okay"; ++ assigned-clocks = <&cru CLK_SPI2>; ++ assigned-clock-rates = <200000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; ++ num-cs = <1>; ++ ++ pmic@0 { ++ compatible = "rockchip,rk806"; ++ spi-max-frequency = <1000000>; ++ reg = <0x0>; ++ ++ interrupt-parent = <&gpio0>; ++ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, ++ <&rk806_dvs2_null>, <&rk806_dvs3_null>; ++ ++ system-power-controller; ++ ++ vcc1-supply = <&vcc5v0_sys>; ++ vcc2-supply = <&vcc5v0_sys>; ++ vcc3-supply = <&vcc5v0_sys>; ++ vcc4-supply = <&vcc5v0_sys>; ++ vcc5-supply = <&vcc5v0_sys>; ++ vcc6-supply = <&vcc5v0_sys>; ++ vcc7-supply = <&vcc5v0_sys>; ++ vcc8-supply = <&vcc5v0_sys>; ++ vcc9-supply = <&vcc5v0_sys>; ++ vcc10-supply = <&vcc5v0_sys>; ++ vcc11-supply = <&vcc_2v0_pldo_s3>; ++ vcc12-supply = <&vcc5v0_sys>; ++ vcc13-supply = <&vcc_1v1_nldo_s3>; ++ vcc14-supply = <&vcc_1v1_nldo_s3>; ++ vcca-supply = <&vcc5v0_sys>; ++ ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ rk806_dvs1_null: dvs1-null-pins { ++ pins = "gpio_pwrctrl1"; ++ function = "pin_fun0"; ++ }; ++ ++ rk806_dvs2_null: dvs2-null-pins { ++ pins = "gpio_pwrctrl2"; ++ function = "pin_fun0"; ++ }; ++ ++ rk806_dvs3_null: dvs3-null-pins { ++ pins = "gpio_pwrctrl3"; ++ function = "pin_fun0"; ++ }; ++ ++ regulators { ++ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_gpu_s0"; ++ regulator-enable-ramp-delay = <400>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_cpu_lit_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_log_s0: dcdc-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <675000>; ++ regulator-max-microvolt = <750000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_log_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <750000>; ++ }; ++ }; ++ ++ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_vdenc_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_ddr_s0: dcdc-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <675000>; ++ regulator-max-microvolt = <900000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_ddr_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <850000>; ++ }; ++ }; ++ ++ vdd2_ddr_s3: dcdc-reg6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vdd2_ddr_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_2v0_pldo_s3: dcdc-reg7 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <2000000>; ++ regulator-max-microvolt = <2000000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_2v0_pldo_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <2000000>; ++ }; ++ }; ++ ++ vcc_3v3_s3: dcdc-reg8 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc_3v3_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vddq_ddr_s0: dcdc-reg9 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vddq_ddr_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8_s3: dcdc-reg10 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ avcc_1v8_s0: pldo-reg1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "avcc_1v8_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc_1v8_s0: pldo-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ avdd_1v2_s0: pldo-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "avdd_1v2_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ avcc_3v3_s0: pldo-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "avcc_3v3_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd_s0: pldo-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vccio_sd_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ pldo6_s3: pldo-reg6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "pldo6_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdd_0v75_s3: nldo-reg1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "vdd_0v75_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <750000>; ++ }; ++ }; ++ ++ avdd_ddr_pll_s0: nldo-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ regulator-name = "avdd_ddr_pll_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <850000>; ++ }; ++ }; ++ ++ avdd_0v75_s0: nldo-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "avdd_0v75_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ avdd_0v85_s0: nldo-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ regulator-name = "avdd_0v85_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_0v75_s0: nldo-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "vdd_0v75_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&tsadc { ++ status = "okay"; ++}; ++ ++&u2phy2 { ++ status = "okay"; ++}; ++ ++&u2phy2_host { ++ phy-supply = <&vcc5v0_host_20>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ pinctrl-0 = <&uart2m0_xfer>; ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++};