From: Daniel Golle <daniel@makrotopia.org>
Date: Thu, 12 Sep 2024 13:43:05 +0000 (+0200)
Subject: mediatek: apply pending PHY driver fixes
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=c4a926516038250105aef1cc5c6ec9fd5c74e300;p=openwrt%2Fstaging%2Fansuel.git

mediatek: apply pending PHY driver fixes

Apply changes suggested by SkyLake Huang for pending series improving
MediaTek Ethernet PHY drivers.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---

diff --git a/target/linux/mediatek/patches-6.6/733-10-net-phy-mediatek-Extend-1G-TX-RX-link-pulse-time.patch b/target/linux/mediatek/patches-6.6/733-10-net-phy-mediatek-Extend-1G-TX-RX-link-pulse-time.patch
index dcbe957836..2fc1adb5ec 100644
--- a/target/linux/mediatek/patches-6.6/733-10-net-phy-mediatek-Extend-1G-TX-RX-link-pulse-time.patch
+++ b/target/linux/mediatek/patches-6.6/733-10-net-phy-mediatek-Extend-1G-TX-RX-link-pulse-time.patch
@@ -69,7 +69,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
  		 */
 --- a/drivers/net/phy/mediatek/mtk-phy-lib.c
 +++ b/drivers/net/phy/mediatek/mtk-phy-lib.c
-@@ -109,6 +109,98 @@ int mtk_phy_write_page(struct phy_device
+@@ -109,6 +109,108 @@ int mtk_phy_write_page(struct phy_device
  }
  EXPORT_SYMBOL_GPL(mtk_phy_write_page);
  
@@ -79,7 +79,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
 + */
 +static int extend_an_new_lp_cnt_limit(struct phy_device *phydev)
 +{
-+	int mmd_read_ret;
++	int ret;
 +	u32 reg_val;
 +	int timeout;
 +
@@ -90,13 +90,14 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
 +	 * this PHY's 1G training starts. If 1G training never starts, we do
 +	 * nothing but leave.
 +	 */
-+	timeout = read_poll_timeout(mmd_read_ret = phy_read_mmd, reg_val,
-+				    (mmd_read_ret < 0) ||
++	timeout = read_poll_timeout(ret = phy_read_mmd, reg_val,
++				    (ret < 0) ||
 +				    reg_val & MTK_PHY_FINAL_SPEED_1000,
-+				    10000, 1000000, false, phydev,
++				    10000, 500000, false, phydev,
 +				    MDIO_MMD_VEND1, MTK_PHY_LINK_STATUS_MISC);
-+	if (mmd_read_ret < 0)
-+		return mmd_read_ret;
++	phydev_dbg(phydev, "%s: Training Indicator: 0x%x\n", __func__, reg_val);
++	if (ret < 0)
++		return ret;
 +
 +	if (!timeout) {
 +		/* Once we found MTK_PHY_FINAL_SPEED_1000 is set, no matter 1G
@@ -105,7 +106,16 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
 +		 */
 +		mtk_tr_modify(phydev, 0x0, 0xf, 0x3c, AN_NEW_LP_CNT_LIMIT_MASK,
 +			      FIELD_PREP(AN_NEW_LP_CNT_LIMIT_MASK, 0xf));
-+		mdelay(1500);
++		msleep(1500);
++
++		/* Read phy status again to make sure the following step won't
++		 * affect normal devices.
++		 */
++		ret = genphy_read_status(phydev);
++		if (ret)
++			return ret;
++		if (phydev->link)
++			return 0;
 +
 +		timeout = read_poll_timeout(mtk_tr_read, reg_val,
 +					    (reg_val & AN_STATE_MASK) !=
@@ -113,19 +123,18 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
 +					     AN_STATE_SHIFT),
 +					    10000, 1000000, false, phydev,
 +					    0x0, 0xf, 0x2);
++		phydev_dbg(phydev, "%s: AN State: 0x%x\n", __func__, reg_val);
 +		if (!timeout) {
-+			mdelay(625);
++			msleep(625);
 +			mtk_tr_modify(phydev, 0x0, 0xf, 0x3c,
 +				      AN_NEW_LP_CNT_LIMIT_MASK,
 +				      FIELD_PREP(AN_NEW_LP_CNT_LIMIT_MASK,
 +						 0x8));
-+			mdelay(500);
++			msleep(500);
 +			mtk_tr_modify(phydev, 0x0, 0xf, 0x3c,
 +				      AN_NEW_LP_CNT_LIMIT_MASK,
 +				      FIELD_PREP(AN_NEW_LP_CNT_LIMIT_MASK,
 +						 0xf));
-+		} else {
-+			return -ETIMEDOUT;
 +		}
 +	}
 +
@@ -156,6 +165,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
 +		ret = phy_read(phydev, MII_CTRL1000);
 +		if (ret & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) {
 +			ret = extend_an_new_lp_cnt_limit(phydev);
++			phydev_dbg(phydev, "%s: counter limit ret: %d\n", __func__, ret);
 +			if (ret < 0)
 +				return ret;
 +		}