From: Álvaro Fernández Rojas Date: Tue, 6 Aug 2024 10:33:48 +0000 (+0200) Subject: generic: 6.6: add backported bmips CBR patches X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=c11adb4b53cb1573bd7700b80b0c18e05c33fba6;p=openwrt%2Fstaging%2Fthess.git generic: 6.6: add backported bmips CBR patches Move v6.11 backported bmips CBR patches from bmips target to generic. Signed-off-by: Álvaro Fernández Rojas --- diff --git a/target/linux/bcm47xx/patches-6.6/830-huawei_e970_support.patch b/target/linux/bcm47xx/patches-6.6/830-huawei_e970_support.patch index 21ab40206f..08813da1ba 100644 --- a/target/linux/bcm47xx/patches-6.6/830-huawei_e970_support.patch +++ b/target/linux/bcm47xx/patches-6.6/830-huawei_e970_support.patch @@ -1,14 +1,14 @@ --- a/arch/mips/bcm47xx/setup.c +++ b/arch/mips/bcm47xx/setup.c -@@ -37,6 +37,7 @@ - #include +@@ -38,6 +38,7 @@ #include #include + #include +#include #include #include #include -@@ -254,6 +255,33 @@ static struct fixed_phy_status bcm47xx_f +@@ -262,6 +263,33 @@ static struct fixed_phy_status bcm47xx_f .duplex = DUPLEX_FULL, }; @@ -42,7 +42,7 @@ static int __init bcm47xx_register_bus_complete(void) { switch (bcm47xx_bus_type) { -@@ -275,6 +303,7 @@ static int __init bcm47xx_register_bus_c +@@ -283,6 +311,7 @@ static int __init bcm47xx_register_bus_c bcm47xx_workarounds(); fixed_phy_add(PHY_POLL, 0, &bcm47xx_fixed_phy_status); diff --git a/target/linux/bmips/patches-6.6/020-v6.11-mips-bmips-rework-and-cache-CBR-addr-handling.patch b/target/linux/bmips/patches-6.6/020-v6.11-mips-bmips-rework-and-cache-CBR-addr-handling.patch deleted file mode 100644 index 21eaa3d6cb..0000000000 --- a/target/linux/bmips/patches-6.6/020-v6.11-mips-bmips-rework-and-cache-CBR-addr-handling.patch +++ /dev/null @@ -1,171 +0,0 @@ -From a5c05453a13ab324ad8719e8a23dfb6af01f3652 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 20 Jun 2024 17:26:42 +0200 -Subject: [PATCH 1/4] mips: bmips: rework and cache CBR addr handling - -Rework the handling of the CBR address and cache it. This address -doesn't change and can be cached instead of reading the register every -time. - -This is in preparation of permitting to tweak the CBR address in DT with -broken SoC or bootloader. - -bmips_cbr_addr is defined in setup.c for each arch to keep compatibility -with legacy brcm47xx/brcm63xx and generic BMIPS target. - -Acked-by: Florian Fainelli -Signed-off-by: Christian Marangi -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/bcm47xx/prom.c | 3 +++ - arch/mips/bcm47xx/setup.c | 4 ++++ - arch/mips/bcm63xx/prom.c | 3 +++ - arch/mips/bcm63xx/setup.c | 4 ++++ - arch/mips/bmips/dma.c | 2 +- - arch/mips/bmips/setup.c | 7 ++++++- - arch/mips/include/asm/bmips.h | 1 + - arch/mips/kernel/smp-bmips.c | 4 ++-- - 8 files changed, 24 insertions(+), 4 deletions(-) - ---- a/arch/mips/bcm47xx/prom.c -+++ b/arch/mips/bcm47xx/prom.c -@@ -32,6 +32,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -109,6 +110,8 @@ static __init void prom_init_mem(void) - - void __init prom_init(void) - { -+ /* Cache CBR addr before CPU/DMA setup */ -+ bmips_cbr_addr = BMIPS_GET_CBR(); - prom_init_mem(); - setup_8250_early_printk_port(CKSEG1ADDR(BCM47XX_SERIAL_ADDR), 0, 0); - } ---- a/arch/mips/bcm47xx/setup.c -+++ b/arch/mips/bcm47xx/setup.c -@@ -37,6 +37,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -45,6 +46,9 @@ - #include - #include - -+/* CBR addr doesn't change and we can cache it */ -+void __iomem *bmips_cbr_addr __read_mostly; -+ - union bcm47xx_bus bcm47xx_bus; - EXPORT_SYMBOL(bcm47xx_bus); - ---- a/arch/mips/bcm63xx/prom.c -+++ b/arch/mips/bcm63xx/prom.c -@@ -22,6 +22,9 @@ void __init prom_init(void) - { - u32 reg, mask; - -+ /* Cache CBR addr before CPU/DMA setup */ -+ bmips_cbr_addr = BMIPS_GET_CBR(); -+ - bcm63xx_cpu_init(); - - /* stop any running watchdog */ ---- a/arch/mips/bcm63xx/setup.c -+++ b/arch/mips/bcm63xx/setup.c -@@ -12,6 +12,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -22,6 +23,9 @@ - #include - #include - -+/* CBR addr doesn't change and we can cache it */ -+void __iomem *bmips_cbr_addr __read_mostly; -+ - void bcm63xx_machine_halt(void) - { - pr_info("System halted\n"); ---- a/arch/mips/bmips/dma.c -+++ b/arch/mips/bmips/dma.c -@@ -9,7 +9,7 @@ bool bmips_rac_flush_disable; - - void arch_sync_dma_for_cpu_all(void) - { -- void __iomem *cbr = BMIPS_GET_CBR(); -+ void __iomem *cbr = bmips_cbr_addr; - u32 cfg; - - if (boot_cpu_type() != CPU_BMIPS3300 && ---- a/arch/mips/bmips/setup.c -+++ b/arch/mips/bmips/setup.c -@@ -34,6 +34,9 @@ - #define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c)) - #define BCM6328_TP1_DISABLED BIT(9) - -+/* CBR addr doesn't change and we can cache it */ -+void __iomem *bmips_cbr_addr __read_mostly; -+ - extern bool bmips_rac_flush_disable; - - static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000; -@@ -111,7 +114,7 @@ static void bcm6358_quirks(void) - * because the bootloader is not initializing it properly. - */ - bmips_rac_flush_disable = !!(read_c0_brcm_cmt_local() & (1 << 31)) || -- !!BMIPS_GET_CBR(); -+ !!bmips_cbr_addr; - } - - static void bcm6368_quirks(void) -@@ -144,6 +147,8 @@ static void __init bmips_init_cfe(void) - - void __init prom_init(void) - { -+ /* Cache CBR addr before CPU/DMA setup */ -+ bmips_cbr_addr = BMIPS_GET_CBR(); - bmips_init_cfe(); - bmips_cpu_setup(); - register_bmips_smp_ops(); ---- a/arch/mips/include/asm/bmips.h -+++ b/arch/mips/include/asm/bmips.h -@@ -81,6 +81,7 @@ extern char bmips_smp_movevec[]; - extern char bmips_smp_int_vec[]; - extern char bmips_smp_int_vec_end[]; - -+extern void __iomem *bmips_cbr_addr; - extern int bmips_smp_enabled; - extern int bmips_cpu_offset; - extern cpumask_t bmips_booted_mask; ---- a/arch/mips/kernel/smp-bmips.c -+++ b/arch/mips/kernel/smp-bmips.c -@@ -518,7 +518,7 @@ static void bmips_set_reset_vec(int cpu, - info.val = val; - bmips_set_reset_vec_remote(&info); - } else { -- void __iomem *cbr = BMIPS_GET_CBR(); -+ void __iomem *cbr = bmips_cbr_addr; - - if (cpu == 0) - __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0); -@@ -591,7 +591,7 @@ asmlinkage void __weak plat_wired_tlb_se - - void bmips_cpu_setup(void) - { -- void __iomem __maybe_unused *cbr = BMIPS_GET_CBR(); -+ void __iomem __maybe_unused *cbr = bmips_cbr_addr; - u32 __maybe_unused cfg; - - switch (current_cpu_type()) { diff --git a/target/linux/bmips/patches-6.6/021-v6.11-mips-bmips-setup-make-CBR-address-configurable.patch b/target/linux/bmips/patches-6.6/021-v6.11-mips-bmips-setup-make-CBR-address-configurable.patch deleted file mode 100644 index 10a710a31d..0000000000 --- a/target/linux/bmips/patches-6.6/021-v6.11-mips-bmips-setup-make-CBR-address-configurable.patch +++ /dev/null @@ -1,111 +0,0 @@ -From b95b30e50aed225d26e20737873ae2404941901c Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 20 Jun 2024 17:26:44 +0200 -Subject: [PATCH 3/4] mips: bmips: setup: make CBR address configurable - -Add support to provide CBR address from DT to handle broken -SoC/Bootloader that doesn't correctly init it. This permits to use the -RAC flush even in these condition. - -To provide a CBR address from DT, the property "brcm,bmips-cbr-reg" -needs to be set in the "cpus" node. On DT init, this property presence -will be checked and will set the bmips_cbr_addr value accordingly. Also -bmips_rac_flush_disable will be set to false as RAC flush can be -correctly supported. - -The CBR address from DT will overwrite the cached one and the -one set in the CBR register will be ignored. - -Also the DT CBR address is validated on being outside DRAM window. - -Signed-off-by: Christian Marangi -Acked-by: Florian Fainelli -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/bcm47xx/setup.c | 6 +++++- - arch/mips/bcm63xx/setup.c | 6 +++++- - arch/mips/bmips/setup.c | 30 ++++++++++++++++++++++++++++-- - 3 files changed, 38 insertions(+), 4 deletions(-) - ---- a/arch/mips/bcm47xx/setup.c -+++ b/arch/mips/bcm47xx/setup.c -@@ -46,7 +46,11 @@ - #include - #include - --/* CBR addr doesn't change and we can cache it */ -+/* -+ * CBR addr doesn't change and we can cache it. -+ * For broken SoC/Bootloader CBR addr might also be provided via DT -+ * with "brcm,bmips-cbr-reg" in the "cpus" node. -+ */ - void __iomem *bmips_cbr_addr __read_mostly; - - union bcm47xx_bus bcm47xx_bus; ---- a/arch/mips/bcm63xx/setup.c -+++ b/arch/mips/bcm63xx/setup.c -@@ -23,7 +23,11 @@ - #include - #include - --/* CBR addr doesn't change and we can cache it */ -+/* -+ * CBR addr doesn't change and we can cache it. -+ * For broken SoC/Bootloader CBR addr might also be provided via DT -+ * with "brcm,bmips-cbr-reg" in the "cpus" node. -+ */ - void __iomem *bmips_cbr_addr __read_mostly; - - void bcm63xx_machine_halt(void) ---- a/arch/mips/bmips/setup.c -+++ b/arch/mips/bmips/setup.c -@@ -34,7 +34,11 @@ - #define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c)) - #define BCM6328_TP1_DISABLED BIT(9) - --/* CBR addr doesn't change and we can cache it */ -+/* -+ * CBR addr doesn't change and we can cache it. -+ * For broken SoC/Bootloader CBR addr might also be provided via DT -+ * with "brcm,bmips-cbr-reg" in the "cpus" node. -+ */ - void __iomem *bmips_cbr_addr __read_mostly; - - extern bool bmips_rac_flush_disable; -@@ -208,13 +212,35 @@ void __init plat_mem_setup(void) - void __init device_tree_init(void) - { - struct device_node *np; -+ u32 addr; - - unflatten_and_copy_device_tree(); - - /* Disable SMP boot unless both CPUs are listed in DT and !disabled */ - np = of_find_node_by_name(NULL, "cpus"); -- if (np && of_get_available_child_count(np) <= 1) -+ if (!np) -+ return; -+ -+ if (of_get_available_child_count(np) <= 1) - bmips_smp_enabled = 0; -+ -+ /* Check if DT provide a CBR address */ -+ if (of_property_read_u32(np, "brcm,bmips-cbr-reg", &addr)) -+ goto exit; -+ -+ /* Make sure CBR address is outside DRAM window */ -+ if (addr >= (u32)memblock_start_of_DRAM() && -+ addr < (u32)memblock_end_of_DRAM()) { -+ WARN(1, "DT CBR %x inside DRAM window. Ignoring DT CBR.\n", -+ addr); -+ goto exit; -+ } -+ -+ bmips_cbr_addr = (void __iomem *)addr; -+ /* Since CBR is provided by DT, enable RAC flush */ -+ bmips_rac_flush_disable = false; -+ -+exit: - of_node_put(np); - } - diff --git a/target/linux/bmips/patches-6.6/022-v6.11-mips-bmips-enable-RAC-on-BMIPS4350.patch b/target/linux/bmips/patches-6.6/022-v6.11-mips-bmips-enable-RAC-on-BMIPS4350.patch deleted file mode 100644 index 2af45df259..0000000000 --- a/target/linux/bmips/patches-6.6/022-v6.11-mips-bmips-enable-RAC-on-BMIPS4350.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 04f38d1a4db017f17e82442727b91ce03dd72759 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Daniel=20Gonz=C3=A1lez=20Cabanelas?= -Date: Thu, 20 Jun 2024 17:26:45 +0200 -Subject: [PATCH 4/4] mips: bmips: enable RAC on BMIPS4350 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The data RAC is left disabled by the bootloader in some SoCs, at least in -the core it boots from. -Enabling this feature increases the performance up to +30% depending on the -task. - -Signed-off-by: Daniel González Cabanelas -Signed-off-by: Álvaro Fernández Rojas -[ rework code and reduce code duplication ] -Acked-by: Florian Fainelli -Signed-off-by: Christian Marangi -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/kernel/smp-bmips.c | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - ---- a/arch/mips/kernel/smp-bmips.c -+++ b/arch/mips/kernel/smp-bmips.c -@@ -592,6 +592,7 @@ asmlinkage void __weak plat_wired_tlb_se - void bmips_cpu_setup(void) - { - void __iomem __maybe_unused *cbr = bmips_cbr_addr; -+ u32 __maybe_unused rac_addr; - u32 __maybe_unused cfg; - - switch (current_cpu_type()) { -@@ -620,6 +621,23 @@ void bmips_cpu_setup(void) - __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE); - break; - -+ case CPU_BMIPS4350: -+ rac_addr = BMIPS_RAC_CONFIG_1; -+ -+ if (!(read_c0_brcm_cmt_local() & (1 << 31))) -+ rac_addr = BMIPS_RAC_CONFIG; -+ -+ /* Enable data RAC */ -+ cfg = __raw_readl(cbr + rac_addr); -+ __raw_writel(cfg | 0xf, cbr + rac_addr); -+ __raw_readl(cbr + rac_addr); -+ -+ /* Flush stale data out of the readahead cache */ -+ cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); -+ __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG); -+ __raw_readl(cbr + BMIPS_RAC_CONFIG); -+ break; -+ - case CPU_BMIPS4380: - /* CBG workaround for early BMIPS4380 CPUs */ - switch (read_c0_prid()) { diff --git a/target/linux/generic/backport-6.6/320-v6.11-mips-bmips-rework-and-cache-CBR-addr-handling.patch b/target/linux/generic/backport-6.6/320-v6.11-mips-bmips-rework-and-cache-CBR-addr-handling.patch new file mode 100644 index 0000000000..21eaa3d6cb --- /dev/null +++ b/target/linux/generic/backport-6.6/320-v6.11-mips-bmips-rework-and-cache-CBR-addr-handling.patch @@ -0,0 +1,171 @@ +From a5c05453a13ab324ad8719e8a23dfb6af01f3652 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 20 Jun 2024 17:26:42 +0200 +Subject: [PATCH 1/4] mips: bmips: rework and cache CBR addr handling + +Rework the handling of the CBR address and cache it. This address +doesn't change and can be cached instead of reading the register every +time. + +This is in preparation of permitting to tweak the CBR address in DT with +broken SoC or bootloader. + +bmips_cbr_addr is defined in setup.c for each arch to keep compatibility +with legacy brcm47xx/brcm63xx and generic BMIPS target. + +Acked-by: Florian Fainelli +Signed-off-by: Christian Marangi +Signed-off-by: Thomas Bogendoerfer +--- + arch/mips/bcm47xx/prom.c | 3 +++ + arch/mips/bcm47xx/setup.c | 4 ++++ + arch/mips/bcm63xx/prom.c | 3 +++ + arch/mips/bcm63xx/setup.c | 4 ++++ + arch/mips/bmips/dma.c | 2 +- + arch/mips/bmips/setup.c | 7 ++++++- + arch/mips/include/asm/bmips.h | 1 + + arch/mips/kernel/smp-bmips.c | 4 ++-- + 8 files changed, 24 insertions(+), 4 deletions(-) + +--- a/arch/mips/bcm47xx/prom.c ++++ b/arch/mips/bcm47xx/prom.c +@@ -32,6 +32,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -109,6 +110,8 @@ static __init void prom_init_mem(void) + + void __init prom_init(void) + { ++ /* Cache CBR addr before CPU/DMA setup */ ++ bmips_cbr_addr = BMIPS_GET_CBR(); + prom_init_mem(); + setup_8250_early_printk_port(CKSEG1ADDR(BCM47XX_SERIAL_ADDR), 0, 0); + } +--- a/arch/mips/bcm47xx/setup.c ++++ b/arch/mips/bcm47xx/setup.c +@@ -37,6 +37,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -45,6 +46,9 @@ + #include + #include + ++/* CBR addr doesn't change and we can cache it */ ++void __iomem *bmips_cbr_addr __read_mostly; ++ + union bcm47xx_bus bcm47xx_bus; + EXPORT_SYMBOL(bcm47xx_bus); + +--- a/arch/mips/bcm63xx/prom.c ++++ b/arch/mips/bcm63xx/prom.c +@@ -22,6 +22,9 @@ void __init prom_init(void) + { + u32 reg, mask; + ++ /* Cache CBR addr before CPU/DMA setup */ ++ bmips_cbr_addr = BMIPS_GET_CBR(); ++ + bcm63xx_cpu_init(); + + /* stop any running watchdog */ +--- a/arch/mips/bcm63xx/setup.c ++++ b/arch/mips/bcm63xx/setup.c +@@ -12,6 +12,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -22,6 +23,9 @@ + #include + #include + ++/* CBR addr doesn't change and we can cache it */ ++void __iomem *bmips_cbr_addr __read_mostly; ++ + void bcm63xx_machine_halt(void) + { + pr_info("System halted\n"); +--- a/arch/mips/bmips/dma.c ++++ b/arch/mips/bmips/dma.c +@@ -9,7 +9,7 @@ bool bmips_rac_flush_disable; + + void arch_sync_dma_for_cpu_all(void) + { +- void __iomem *cbr = BMIPS_GET_CBR(); ++ void __iomem *cbr = bmips_cbr_addr; + u32 cfg; + + if (boot_cpu_type() != CPU_BMIPS3300 && +--- a/arch/mips/bmips/setup.c ++++ b/arch/mips/bmips/setup.c +@@ -34,6 +34,9 @@ + #define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c)) + #define BCM6328_TP1_DISABLED BIT(9) + ++/* CBR addr doesn't change and we can cache it */ ++void __iomem *bmips_cbr_addr __read_mostly; ++ + extern bool bmips_rac_flush_disable; + + static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000; +@@ -111,7 +114,7 @@ static void bcm6358_quirks(void) + * because the bootloader is not initializing it properly. + */ + bmips_rac_flush_disable = !!(read_c0_brcm_cmt_local() & (1 << 31)) || +- !!BMIPS_GET_CBR(); ++ !!bmips_cbr_addr; + } + + static void bcm6368_quirks(void) +@@ -144,6 +147,8 @@ static void __init bmips_init_cfe(void) + + void __init prom_init(void) + { ++ /* Cache CBR addr before CPU/DMA setup */ ++ bmips_cbr_addr = BMIPS_GET_CBR(); + bmips_init_cfe(); + bmips_cpu_setup(); + register_bmips_smp_ops(); +--- a/arch/mips/include/asm/bmips.h ++++ b/arch/mips/include/asm/bmips.h +@@ -81,6 +81,7 @@ extern char bmips_smp_movevec[]; + extern char bmips_smp_int_vec[]; + extern char bmips_smp_int_vec_end[]; + ++extern void __iomem *bmips_cbr_addr; + extern int bmips_smp_enabled; + extern int bmips_cpu_offset; + extern cpumask_t bmips_booted_mask; +--- a/arch/mips/kernel/smp-bmips.c ++++ b/arch/mips/kernel/smp-bmips.c +@@ -518,7 +518,7 @@ static void bmips_set_reset_vec(int cpu, + info.val = val; + bmips_set_reset_vec_remote(&info); + } else { +- void __iomem *cbr = BMIPS_GET_CBR(); ++ void __iomem *cbr = bmips_cbr_addr; + + if (cpu == 0) + __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0); +@@ -591,7 +591,7 @@ asmlinkage void __weak plat_wired_tlb_se + + void bmips_cpu_setup(void) + { +- void __iomem __maybe_unused *cbr = BMIPS_GET_CBR(); ++ void __iomem __maybe_unused *cbr = bmips_cbr_addr; + u32 __maybe_unused cfg; + + switch (current_cpu_type()) { diff --git a/target/linux/generic/backport-6.6/321-v6.11-mips-bmips-setup-make-CBR-address-configurable.patch b/target/linux/generic/backport-6.6/321-v6.11-mips-bmips-setup-make-CBR-address-configurable.patch new file mode 100644 index 0000000000..10a710a31d --- /dev/null +++ b/target/linux/generic/backport-6.6/321-v6.11-mips-bmips-setup-make-CBR-address-configurable.patch @@ -0,0 +1,111 @@ +From b95b30e50aed225d26e20737873ae2404941901c Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 20 Jun 2024 17:26:44 +0200 +Subject: [PATCH 3/4] mips: bmips: setup: make CBR address configurable + +Add support to provide CBR address from DT to handle broken +SoC/Bootloader that doesn't correctly init it. This permits to use the +RAC flush even in these condition. + +To provide a CBR address from DT, the property "brcm,bmips-cbr-reg" +needs to be set in the "cpus" node. On DT init, this property presence +will be checked and will set the bmips_cbr_addr value accordingly. Also +bmips_rac_flush_disable will be set to false as RAC flush can be +correctly supported. + +The CBR address from DT will overwrite the cached one and the +one set in the CBR register will be ignored. + +Also the DT CBR address is validated on being outside DRAM window. + +Signed-off-by: Christian Marangi +Acked-by: Florian Fainelli +Signed-off-by: Thomas Bogendoerfer +--- + arch/mips/bcm47xx/setup.c | 6 +++++- + arch/mips/bcm63xx/setup.c | 6 +++++- + arch/mips/bmips/setup.c | 30 ++++++++++++++++++++++++++++-- + 3 files changed, 38 insertions(+), 4 deletions(-) + +--- a/arch/mips/bcm47xx/setup.c ++++ b/arch/mips/bcm47xx/setup.c +@@ -46,7 +46,11 @@ + #include + #include + +-/* CBR addr doesn't change and we can cache it */ ++/* ++ * CBR addr doesn't change and we can cache it. ++ * For broken SoC/Bootloader CBR addr might also be provided via DT ++ * with "brcm,bmips-cbr-reg" in the "cpus" node. ++ */ + void __iomem *bmips_cbr_addr __read_mostly; + + union bcm47xx_bus bcm47xx_bus; +--- a/arch/mips/bcm63xx/setup.c ++++ b/arch/mips/bcm63xx/setup.c +@@ -23,7 +23,11 @@ + #include + #include + +-/* CBR addr doesn't change and we can cache it */ ++/* ++ * CBR addr doesn't change and we can cache it. ++ * For broken SoC/Bootloader CBR addr might also be provided via DT ++ * with "brcm,bmips-cbr-reg" in the "cpus" node. ++ */ + void __iomem *bmips_cbr_addr __read_mostly; + + void bcm63xx_machine_halt(void) +--- a/arch/mips/bmips/setup.c ++++ b/arch/mips/bmips/setup.c +@@ -34,7 +34,11 @@ + #define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c)) + #define BCM6328_TP1_DISABLED BIT(9) + +-/* CBR addr doesn't change and we can cache it */ ++/* ++ * CBR addr doesn't change and we can cache it. ++ * For broken SoC/Bootloader CBR addr might also be provided via DT ++ * with "brcm,bmips-cbr-reg" in the "cpus" node. ++ */ + void __iomem *bmips_cbr_addr __read_mostly; + + extern bool bmips_rac_flush_disable; +@@ -208,13 +212,35 @@ void __init plat_mem_setup(void) + void __init device_tree_init(void) + { + struct device_node *np; ++ u32 addr; + + unflatten_and_copy_device_tree(); + + /* Disable SMP boot unless both CPUs are listed in DT and !disabled */ + np = of_find_node_by_name(NULL, "cpus"); +- if (np && of_get_available_child_count(np) <= 1) ++ if (!np) ++ return; ++ ++ if (of_get_available_child_count(np) <= 1) + bmips_smp_enabled = 0; ++ ++ /* Check if DT provide a CBR address */ ++ if (of_property_read_u32(np, "brcm,bmips-cbr-reg", &addr)) ++ goto exit; ++ ++ /* Make sure CBR address is outside DRAM window */ ++ if (addr >= (u32)memblock_start_of_DRAM() && ++ addr < (u32)memblock_end_of_DRAM()) { ++ WARN(1, "DT CBR %x inside DRAM window. Ignoring DT CBR.\n", ++ addr); ++ goto exit; ++ } ++ ++ bmips_cbr_addr = (void __iomem *)addr; ++ /* Since CBR is provided by DT, enable RAC flush */ ++ bmips_rac_flush_disable = false; ++ ++exit: + of_node_put(np); + } + diff --git a/target/linux/generic/backport-6.6/322-v6.11-mips-bmips-enable-RAC-on-BMIPS4350.patch b/target/linux/generic/backport-6.6/322-v6.11-mips-bmips-enable-RAC-on-BMIPS4350.patch new file mode 100644 index 0000000000..2af45df259 --- /dev/null +++ b/target/linux/generic/backport-6.6/322-v6.11-mips-bmips-enable-RAC-on-BMIPS4350.patch @@ -0,0 +1,57 @@ +From 04f38d1a4db017f17e82442727b91ce03dd72759 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Daniel=20Gonz=C3=A1lez=20Cabanelas?= +Date: Thu, 20 Jun 2024 17:26:45 +0200 +Subject: [PATCH 4/4] mips: bmips: enable RAC on BMIPS4350 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The data RAC is left disabled by the bootloader in some SoCs, at least in +the core it boots from. +Enabling this feature increases the performance up to +30% depending on the +task. + +Signed-off-by: Daniel González Cabanelas +Signed-off-by: Álvaro Fernández Rojas +[ rework code and reduce code duplication ] +Acked-by: Florian Fainelli +Signed-off-by: Christian Marangi +Signed-off-by: Thomas Bogendoerfer +--- + arch/mips/kernel/smp-bmips.c | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +--- a/arch/mips/kernel/smp-bmips.c ++++ b/arch/mips/kernel/smp-bmips.c +@@ -592,6 +592,7 @@ asmlinkage void __weak plat_wired_tlb_se + void bmips_cpu_setup(void) + { + void __iomem __maybe_unused *cbr = bmips_cbr_addr; ++ u32 __maybe_unused rac_addr; + u32 __maybe_unused cfg; + + switch (current_cpu_type()) { +@@ -620,6 +621,23 @@ void bmips_cpu_setup(void) + __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE); + break; + ++ case CPU_BMIPS4350: ++ rac_addr = BMIPS_RAC_CONFIG_1; ++ ++ if (!(read_c0_brcm_cmt_local() & (1 << 31))) ++ rac_addr = BMIPS_RAC_CONFIG; ++ ++ /* Enable data RAC */ ++ cfg = __raw_readl(cbr + rac_addr); ++ __raw_writel(cfg | 0xf, cbr + rac_addr); ++ __raw_readl(cbr + rac_addr); ++ ++ /* Flush stale data out of the readahead cache */ ++ cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); ++ __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG); ++ __raw_readl(cbr + BMIPS_RAC_CONFIG); ++ break; ++ + case CPU_BMIPS4380: + /* CBG workaround for early BMIPS4380 CPUs */ + switch (read_c0_prid()) {