From: Kumar Gala Date: Fri, 30 May 2008 18:43:43 +0000 (-0500) Subject: [POWERPC] 85xx: Add next-level-cache property X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=c054065bc10a7ee2bcf78b5bc95f4b4d9bdc923a;p=openwrt%2Fstaging%2Fblogic.git [POWERPC] 85xx: Add next-level-cache property Added next-level-cache to the L1 and a reference to the new L2 label. This is per the ePAPR 0.94 spec. Since we are't really dependent on this today we aren't supporting the "legacy" l2-cache phandle that is specified in the PPC v2.1 OF Binding spec. Signed-off-by: Kumar Gala --- diff --git a/arch/powerpc/boot/dts/ksi8560.dts b/arch/powerpc/boot/dts/ksi8560.dts index f869ce3ca0b7..6eb7c771f6a4 100644 --- a/arch/powerpc/boot/dts/ksi8560.dts +++ b/arch/powerpc/boot/dts/ksi8560.dts @@ -40,6 +40,7 @@ timebase-frequency = <0>; /* From U-boot */ bus-frequency = <0>; /* From U-boot */ clock-frequency = <0>; /* From U-boot */ + next-level-cache = <&L2>; }; }; @@ -62,7 +63,7 @@ interrupts = <0x12 0x2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <0x20>; /* 32 bytes */ diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts index 58e165e87373..79881a1fb8aa 100644 --- a/arch/powerpc/boot/dts/mpc8540ads.dts +++ b/arch/powerpc/boot/dts/mpc8540ads.dts @@ -40,6 +40,7 @@ timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // 166 MHz clock-frequency = <0>; // 825 MHz, from uboot + next-level-cache = <&L2>; }; }; @@ -63,7 +64,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts index 21ebe7cc454a..66192aa0f311 100644 --- a/arch/powerpc/boot/dts/mpc8541cds.dts +++ b/arch/powerpc/boot/dts/mpc8541cds.dts @@ -40,6 +40,7 @@ timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // 166 MHz clock-frequency = <0>; // 825 MHz, from uboot + next-level-cache = <&L2>; }; }; @@ -63,7 +64,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8541-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts index 921f9f6848ea..6cf533f4b5fb 100644 --- a/arch/powerpc/boot/dts/mpc8544ds.dts +++ b/arch/powerpc/boot/dts/mpc8544ds.dts @@ -41,6 +41,7 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; }; @@ -65,7 +66,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8544-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts index 213c88e5aee8..205598d51f25 100644 --- a/arch/powerpc/boot/dts/mpc8548cds.dts +++ b/arch/powerpc/boot/dts/mpc8548cds.dts @@ -45,6 +45,7 @@ timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // 166 MHz clock-frequency = <0>; // 825 MHz, from uboot + next-level-cache = <&L2>; }; }; @@ -68,7 +69,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8548-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts index 400f6dbc3a86..7c9d0b16d7e5 100644 --- a/arch/powerpc/boot/dts/mpc8555cds.dts +++ b/arch/powerpc/boot/dts/mpc8555cds.dts @@ -40,6 +40,7 @@ timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // 166 MHz clock-frequency = <0>; // 825 MHz, from uboot + next-level-cache = <&L2>; }; }; @@ -63,7 +64,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8555-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts index f0b1f98a2df8..5d9f3c4b5b71 100644 --- a/arch/powerpc/boot/dts/mpc8560ads.dts +++ b/arch/powerpc/boot/dts/mpc8560ads.dts @@ -64,7 +64,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts index d9064ee2d2d8..d7af8db1a22f 100644 --- a/arch/powerpc/boot/dts/mpc8568mds.dts +++ b/arch/powerpc/boot/dts/mpc8568mds.dts @@ -42,6 +42,7 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; }; @@ -70,7 +71,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8568-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts index 3ca8cae493b6..a444e6a2387d 100644 --- a/arch/powerpc/boot/dts/mpc8572ds.dts +++ b/arch/powerpc/boot/dts/mpc8572ds.dts @@ -42,6 +42,7 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; PowerPC,8572@1 { @@ -54,6 +55,7 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; }; @@ -84,7 +86,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,mpc8572-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts index ce496fb27894..d252e38283e7 100644 --- a/arch/powerpc/boot/dts/sbc8548.dts +++ b/arch/powerpc/boot/dts/sbc8548.dts @@ -44,6 +44,7 @@ timebase-frequency = <0>; // From uboot bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; }; @@ -161,7 +162,7 @@ interrupts = <0x12 0x2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8548-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <0x20>; // 32 bytes diff --git a/arch/powerpc/boot/dts/sbc8560.dts b/arch/powerpc/boot/dts/sbc8560.dts index 266350196cd2..e556c5a4cf95 100644 --- a/arch/powerpc/boot/dts/sbc8560.dts +++ b/arch/powerpc/boot/dts/sbc8560.dts @@ -43,6 +43,7 @@ timebase-frequency = <0>; // From uboot bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; }; @@ -66,7 +67,7 @@ interrupts = <0x12 0x2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8560-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <0x20>; // 32 bytes diff --git a/arch/powerpc/boot/dts/stx_gp3_8560.dts b/arch/powerpc/boot/dts/stx_gp3_8560.dts index 096277b7192d..1e612836b248 100644 --- a/arch/powerpc/boot/dts/stx_gp3_8560.dts +++ b/arch/powerpc/boot/dts/stx_gp3_8560.dts @@ -38,6 +38,7 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; }; @@ -62,7 +63,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts index 8ee4664c7490..7b653a583a2d 100644 --- a/arch/powerpc/boot/dts/tqm8540.dts +++ b/arch/powerpc/boot/dts/tqm8540.dts @@ -40,6 +40,7 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; }; @@ -64,7 +65,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts index cadbebfd0edb..8fe73ef34195 100644 --- a/arch/powerpc/boot/dts/tqm8541.dts +++ b/arch/powerpc/boot/dts/tqm8541.dts @@ -39,6 +39,7 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; }; @@ -63,7 +64,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts index 9d6dc04e8c40..0a53bb9ce76f 100644 --- a/arch/powerpc/boot/dts/tqm8555.dts +++ b/arch/powerpc/boot/dts/tqm8555.dts @@ -39,6 +39,7 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; }; @@ -63,7 +64,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; diff --git a/arch/powerpc/boot/dts/tqm8560.dts b/arch/powerpc/boot/dts/tqm8560.dts index 358cbd7c7572..a4ee596e97bc 100644 --- a/arch/powerpc/boot/dts/tqm8560.dts +++ b/arch/powerpc/boot/dts/tqm8560.dts @@ -40,6 +40,7 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; }; @@ -64,7 +65,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>;