From: Tomasz Figa Date: Tue, 15 Oct 2013 17:41:20 +0000 (+0200) Subject: clk: samsung: exynos5250: Correct parent list of audio muxes X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=bfeb9f274b128833eedcdea9779042e49cf4fa85;p=openwrt%2Fstaging%2Fblogic.git clk: samsung: exynos5250: Correct parent list of audio muxes According to SoC documentation, input 5 of mout_audio muxes is connected to xxti (named fin_pll in the driver). This patch corrects defined parent arrays to match SoC documentation. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Tested-by: Tomasz Figa --- diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 73334b8d9f66..220aa3a5ba74 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -208,19 +208,19 @@ PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m", "none", "none", "none", "none" }; PNAME(mout_audio0_p) = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", - "sclk_uhostphy", "sclk_hdmiphy", + "sclk_uhostphy", "fin_pll", "mout_mpll_user", "mout_epll", "mout_vpll", "mout_cpll", "none", "none", "none", "none", "none", "none" }; PNAME(mout_audio1_p) = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", - "sclk_uhostphy", "sclk_hdmiphy", + "sclk_uhostphy", "fin_pll", "mout_mpll_user", "mout_epll", "mout_vpll", "mout_cpll", "none", "none", "none", "none", "none", "none" }; PNAME(mout_audio2_p) = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", - "sclk_uhostphy", "sclk_hdmiphy", + "sclk_uhostphy", "fin_pll", "mout_mpll_user", "mout_epll", "mout_vpll", "mout_cpll", "none", "none", "none", "none", "none",