From: Paul Beesley Date: Fri, 4 Oct 2019 16:17:46 +0000 (+0000) Subject: doc: Misc syntax and spelling fixes X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=be653a6940b6c7bf3c0c6b7049ae829fa70863c1;p=project%2Fbcm63xx%2Fatf.git doc: Misc syntax and spelling fixes Tidying up a few Sphinx warnings that had built-up over time. None of these are critical but it cleans up the Sphinx output. At the same time, fixing some spelling errors that were detected. Change-Id: I38209e235481eed287f8008c6de9dedd6b12ab2e Signed-off-by: Paul Beesley --- diff --git a/docs/components/firmware-update.rst b/docs/components/firmware-update.rst index 2bff00f5..a5915656 100644 --- a/docs/components/firmware-update.rst +++ b/docs/components/firmware-update.rst @@ -7,7 +7,7 @@ Introduction This document describes the design of the Firmware Update (FWU) feature, which enables authenticated firmware to update firmware images from external interfaces such as USB, UART, SD-eMMC, NAND, NOR or Ethernet to SoC Non-Volatile -memories such as NAND Flash, LPPDR2-NVM or any memory determined by the +memories such as NAND Flash, LPDDR2-NVM or any memory determined by the platform. This feature functions even when the current firmware in the system is corrupt or missing; it therefore may be used as a recovery mode. It may also be complemented by other, higher level firmware update software. diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst index 1deacb7f..4958fc09 100644 --- a/docs/design/firmware-design.rst +++ b/docs/design/firmware-design.rst @@ -1672,7 +1672,7 @@ The following list describes the memory layout on the Arm development platforms: point during a cold boot. - On Juno, SCP_BL2 is loaded temporarily into the EL3 Runtime Software memory - region and transfered to the SCP before being overwritten by EL3 Runtime + region and transferred to the SCP before being overwritten by EL3 Runtime Software. - BL32 (for AArch64) can be loaded in one of the following locations: @@ -2623,7 +2623,7 @@ Cortex-A architecture through ``ARM_CORTEX_A = yes`` in their Cortex-A15 target. Platform can also set ``ARM_WITH_NEON=yes`` to enable neon support. -Note that using neon at runtime has constraints on non secure wolrd context. +Note that using neon at runtime has constraints on non secure world context. TF-A does not yet provide VFP context management. Directive ``ARM_CORTEX_A`` and ``ARM_WITH_NEON`` are used to set diff --git a/docs/getting_started/image-terminology.rst b/docs/getting_started/image-terminology.rst index d9e08f76..5993d6e7 100644 --- a/docs/getting_started/image-terminology.rst +++ b/docs/getting_started/image-terminology.rst @@ -7,7 +7,7 @@ images referred to in the Trusted Firmware project. General Notes ------------- -- Some of the names and abbreviated names have changed to accomodate new +- Some of the names and abbreviated names have changed to accommodate new requirements. The changed names are as backward compatible as possible to minimize confusion. Where applicable, the previous names are indicated. Some code, documentation and build artefacts may still refer to the previous names; @@ -44,7 +44,7 @@ AP Boot ROM: ``AP_BL1`` ~~~~~~~~~~~~~~~~~~~~~~~ Typically, this is the first code to execute on the AP and cannot be modified. -Its primary purpose is to perform the minimum intialization necessary to load +Its primary purpose is to perform the minimum initialization necessary to load and authenticate an updateable AP firmware image into an executable RAM location, then hand-off control to that image. @@ -96,7 +96,7 @@ SCP Boot ROM: ``SCP_BL1`` (previously ``BL0``) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Typically, this is the first code to execute on the SCP and cannot be modified. -Its primary purpose is to perform the minimum intialization necessary to load +Its primary purpose is to perform the minimum initialization necessary to load and authenticate an updateable SCP firmware image into an executable RAM location, then hand-off control to that image. This may be performed in conjunction with other processor firmware (for example, ``AP_BL1`` and @@ -129,7 +129,7 @@ AP Firmware Update Boot ROM: ``AP_NS_BL1U`` Typically, this is the first normal world code to execute on the AP during a firmware update operation, and cannot be modified. Its primary purpose is to -load subequent firmware update images from an external interface and communicate +load subsequent firmware update images from an external interface and communicate with ``AP_BL1`` to authenticate those images. During firmware update, there are (potentially) multiple transitions between the diff --git a/docs/getting_started/porting-guide.rst b/docs/getting_started/porting-guide.rst index d7157690..9cca75e9 100644 --- a/docs/getting_started/porting-guide.rst +++ b/docs/getting_started/porting-guide.rst @@ -549,7 +549,7 @@ optionally be defined: - **PLAT_PARTITION_BLOCK_SIZE** The size of partition block. It could be either 512 bytes or 4096 bytes. The default value is 512. - `For example, define the build flag in platform.mk`_: + For example, define the build flag in ``platform.mk``: PLAT_PARTITION_BLOCK_SIZE := 4096 $(eval $(call add_define,PLAT_PARTITION_BLOCK_SIZE)) @@ -954,7 +954,7 @@ Function : plat_reset_handler() Return : void A platform may need to do additional initialization after reset. This function -allows the platform to do the platform specific intializations. Platform +allows the platform to do the platform specific initializations. Platform specific errata workarounds could also be implemented here. The API should preserve the values of callee saved registers x19 to x29. @@ -2777,7 +2777,7 @@ more functionality is required, the needed library functions will need to be added to the local implementation. Some C headers have been obtained from `FreeBSD`_ and `SCC`_, while others have -been written specifically for TF-A. Fome implementation files have been obtained +been written specifically for TF-A. Some implementation files have been obtained from `FreeBSD`_, others have been written specifically for TF-A as well. The files can be found in ``include/lib/libc`` and ``lib/libc``. diff --git a/docs/maintainers.rst b/docs/maintainers.rst index d997baac..86e445a7 100644 --- a/docs/maintainers.rst +++ b/docs/maintainers.rst @@ -49,9 +49,9 @@ Amlogic Meson S905x (GXL) platform port :F: plat/amlogic/gxl/ Amlogic Meson S905X2 (G12A) platform port ---------------------------------------- +----------------------------------------- :M: Carlo Caione -:G: `carlo.caione`_ +:G: `carlocaione`_ :F: docs/plat/meson-g12a.rst :F: drivers/amlogic/g12a :F: plat/amlogic/g12a/ @@ -122,7 +122,7 @@ Intel SocFPGA platform ports :M: Tien Hock Loh :G: `thloh85-intel`_ :M: Hadi Asyrafi -:G: `mabdulha`_ +:G: mabdulha :F: plat/intel/soc :F: drivers/intel/soc/ @@ -282,6 +282,7 @@ Xilinx platform port .. _Anson-Huang: https://github.com/Anson-Huang .. _bryanodonoghue: https://github.com/bryanodonoghue .. _b49020: https://github.com/b49020 +.. _carlocaione: https://github.com/carlocaione .. _danh-arm: https://github.com/danh-arm .. _etienne-lms: https://github.com/etienne-lms .. _glneo: https://github.com/glneo @@ -308,6 +309,7 @@ Xilinx platform port .. _sivadur: https://github.com/sivadur .. _smaeul: https://github.com/smaeul .. _soby-mathew: https://github.com/soby-mathew +.. _thloh85-intel: https://github.com/thloh85-intel .. _thomas-arm: https://github.com/thomas-arm .. _TonyXie06: https://github.com/TonyXie06 .. _vwadekar: https://github.com/vwadekar diff --git a/docs/perf/psci-performance-juno.rst b/docs/perf/psci-performance-juno.rst index 4cc43026..c127c1c4 100644 --- a/docs/perf/psci-performance-juno.rst +++ b/docs/perf/psci-performance-juno.rst @@ -168,7 +168,7 @@ the cache associated with power level 0 is flushed (L1). | 5 | 21 | 17 | 6 | +-------+---------------------+--------------------+--------------------------+ -The ``CLUSH_OVERHEAD`` times for lead CPU 4 and all CPUs in the non-lead cluster +The ``CFLUSH_OVERHEAD`` times for lead CPU 4 and all CPUs in the non-lead cluster are large because all other CPUs in the cluster are powered down during the test. The ``CPU_SUSPEND`` call powers down to the cluster level, requiring a flush of both L1 and L2 caches. diff --git a/docs/plat/marvell/porting.rst b/docs/plat/marvell/porting.rst index 8fc1c1f6..0a71dbd5 100644 --- a/docs/plat/marvell/porting.rst +++ b/docs/plat/marvell/porting.rst @@ -112,7 +112,7 @@ Comphy Porting (phy-porting-layer.h or phy-default-porting-layer.h) .. seealso:: For XFI/SFI comphy type there is procedure "rx_training" which eases - process of suiting some of the parameters. Please see :ref:`uboot_cmd` + process of suiting some of the parameters. Please see *uboot_cmd* section: rx_training. The PHY porting layer simplifies updating static values per board type, diff --git a/docs/plat/meson-g12a.rst b/docs/plat/meson-g12a.rst index 1021da47..7cd1bf74 100644 --- a/docs/plat/meson-g12a.rst +++ b/docs/plat/meson-g12a.rst @@ -1,5 +1,5 @@ Amlogic Meson S905X2 (G12A) -========================== +=========================== The Amlogic Meson S905X2 is a SoC with a quad core Arm Cortex-A53 running at ~1.8GHz. It also contains a Cortex-M3 used as SCP. diff --git a/docs/process/coding-guidelines.rst b/docs/process/coding-guidelines.rst index a53da77b..cb8b8924 100644 --- a/docs/process/coding-guidelines.rst +++ b/docs/process/coding-guidelines.rst @@ -23,8 +23,8 @@ include: - ``**WARNING: Use of volatile is usually wrong``: see `Why the “volatile” type class should not be used`_ . Although this document - contains some very useful information, there are several legimate uses of the - volatile keyword within the TF codebase. + contains some very useful information, there are several legitimate uses of + the volatile keyword within the TF codebase. Headers and inclusion --------------------- diff --git a/docs/security_advisories/security-advisory-tfv-6.rst b/docs/security_advisories/security-advisory-tfv-6.rst index 495eddda..9eeaeec5 100644 --- a/docs/security_advisories/security-advisory-tfv-6.rst +++ b/docs/security_advisories/security-advisory-tfv-6.rst @@ -51,7 +51,7 @@ the MMU. For Cortex-A73 and Cortex-A75 CPUs, the PRs in this advisory invalidate the branch predictor when entering EL3 by temporarily dropping into AArch32 Secure-EL1 and executing the ``BPIALL`` instruction. This workaround is -signifiantly more complex than the "MMU disable/enable" workaround. The latter +significantly more complex than the "MMU disable/enable" workaround. The latter is not effective at invalidating the branch predictor on Cortex-A73/Cortex-A75. Note that if other privileged software, for example a Rich OS kernel, implements