From: Sergio Paracuellos Date: Sun, 4 Nov 2018 10:49:58 +0000 (+0100) Subject: staging: mt7621-pci: move some code into 'mt7621_pcie_init_ports' X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=b8d97d43bf7a4c1746ecdfa674c3e6ef5c73c11e;p=openwrt%2Fstaging%2Fblogic.git staging: mt7621-pci: move some code into 'mt7621_pcie_init_ports' Some clocks bits related code is in driver probe function and can perfectly be moved into 'mt7621_pcie_init_ports' function which is a more accurate place for it. Signed-off-by: Sergio Paracuellos Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index a069d7f5d8d9..fb9aa6bbd5dc 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -626,6 +626,14 @@ static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie) list_del(&port->list); } } + + rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL); + rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1); + rt_sysc_m32(PCIE_CLK_GEN_EN, PCIE_CLK_GEN_DIS, RALINK_PCIE_CLK_GEN); + rt_sysc_m32(PCIE_CLK_GEN1_DIS, PCIE_CLK_GEN1_EN, RALINK_PCIE_CLK_GEN1); + rt_sysc_m32(PCIE_CLK_GEN_DIS, PCIE_CLK_GEN_EN, RALINK_PCIE_CLK_GEN); + mdelay(50); + rt_sysc_m32(RALINK_PCIE_RST, 0, RALINK_RSTCTRL); } static int mt7621_pcie_enable_port(struct mt7621_pcie_port *port) @@ -833,16 +841,6 @@ static int mt7621_pci_probe(struct platform_device *pdev) mt7621_pcie_init_ports(pcie); - rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL); - rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1); - - rt_sysc_m32(PCIE_CLK_GEN_EN, PCIE_CLK_GEN_DIS, RALINK_PCIE_CLK_GEN); - rt_sysc_m32(PCIE_CLK_GEN1_DIS, PCIE_CLK_GEN1_EN, RALINK_PCIE_CLK_GEN1); - rt_sysc_m32(PCIE_CLK_GEN_DIS, PCIE_CLK_GEN_EN, RALINK_PCIE_CLK_GEN); - - mdelay(50); - rt_sysc_m32(RALINK_PCIE_RST, 0, RALINK_RSTCTRL); - err = mt7621_pcie_init_virtual_bridges(pcie); if (err) { dev_err(dev, "Nothing is connected in virtual bridges. Exiting...");