From: Zoltan HERPAI Date: Wed, 4 Oct 2023 15:28:54 +0000 (+0200) Subject: cv18x0: add new target for Sophgo CV18x0 RISC-V SoCs X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=b55e7181d9274b28f09f78828ee9f668396a6167;p=openwrt%2Fstaging%2Fwigyori.git cv18x0: add new target for Sophgo CV18x0 RISC-V SoCs Initially targeting the Milk-V Duo+dock board. Signed-off-by: Zoltan HERPAI --- diff --git a/target/linux/cv18x0/Makefile b/target/linux/cv18x0/Makefile new file mode 100644 index 0000000000..07d9d225ca --- /dev/null +++ b/target/linux/cv18x0/Makefile @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Copyright (C) 2022 Toco Technologies +# +include $(TOPDIR)/rules.mk + +ARCH:=riscv64 +BOARD:=cv18x0 +BOARDNAME:=Cvitek CV180x boards +FEATURES:=ext4 +KERNELNAME:=Image dtbs +SUBTARGETS:=generic + +KERNEL_PATCHVER:=6.1 + +include $(INCLUDE_DIR)/target.mk + +define Target/Description + Build firmware images for the Cvitek CV1800/1810 boards +endef + +$(eval $(call BuildTarget)) diff --git a/target/linux/cv18x0/base-files/etc/board.d/01_leds b/target/linux/cv18x0/base-files/etc/board.d/01_leds new file mode 100644 index 0000000000..5610a791ec --- /dev/null +++ b/target/linux/cv18x0/base-files/etc/board.d/01_leds @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Copyright (C) 2022 OpenWrt.org +# + +. /lib/functions/uci-defaults.sh + +board_config_update + +case "$(board_name)" in +sifive,hifive-unleashed-a00) + ucidef_set_led_netdev "lan" "LAN" "green:d3" "eth0" + ;; +sifive,hifive-unmatched-a00) + ucidef_set_led_netdev "lan" "LAN" "green:d2" "eth0" + ;; +esac + +board_config_flush + +exit 0 diff --git a/target/linux/cv18x0/base-files/etc/board.d/02_network b/target/linux/cv18x0/base-files/etc/board.d/02_network new file mode 100644 index 0000000000..ca9f7f2008 --- /dev/null +++ b/target/linux/cv18x0/base-files/etc/board.d/02_network @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Copyright (C) 2022 OpenWrt.org +# + +. /lib/functions/uci-defaults.sh + +board_config_update + +case "$(board_name)" in +*) + ucidef_set_interface_lan 'eth0' + ;; +esac + +board_config_flush + +exit 0 diff --git a/target/linux/cv18x0/base-files/etc/inittab b/target/linux/cv18x0/base-files/etc/inittab new file mode 100644 index 0000000000..69f97c47c8 --- /dev/null +++ b/target/linux/cv18x0/base-files/etc/inittab @@ -0,0 +1,4 @@ +::sysinit:/etc/init.d/rcS S boot +::shutdown:/etc/init.d/rcS K shutdown +ttySIF0::askfirst:/usr/libexec/login.sh +tty1::askfirst:/usr/libexec/login.sh diff --git a/target/linux/cv18x0/base-files/lib/preinit/79_move_config b/target/linux/cv18x0/base-files/lib/preinit/79_move_config new file mode 100644 index 0000000000..2796c4d01b --- /dev/null +++ b/target/linux/cv18x0/base-files/lib/preinit/79_move_config @@ -0,0 +1,19 @@ +# Copyright (C) 2012-2015 OpenWrt.org + +move_config() { + local partdev + + . /lib/upgrade/common.sh + + if export_bootdevice && export_partdevice partdev 3; then + if mount -t vfat -o rw,noatime "/dev/$partdev" /mnt; then + if [ -f "/mnt/$BACKUP_FILE" ]; then + mv -f "/mnt/$BACKUP_FILE" / + fi + umount /mnt + fi + fi +} + +boot_hook_add preinit_mount_root move_config + diff --git a/target/linux/cv18x0/base-files/lib/upgrade/platform.sh b/target/linux/cv18x0/base-files/lib/upgrade/platform.sh new file mode 100644 index 0000000000..b5f6bada41 --- /dev/null +++ b/target/linux/cv18x0/base-files/lib/upgrade/platform.sh @@ -0,0 +1,86 @@ +platform_check_image() { + local diskdev partdev diff + + export_bootdevice && export_partdevice diskdev 0 || { + echo "Unable to determine upgrade device" + return 1 + } + + get_partitions "/dev/$diskdev" bootdisk + + #extract the boot sector from the image + get_image "$@" | dd of=/tmp/image.bs count=1 bs=512b 2>/dev/null + + get_partitions /tmp/image.bs image + + #compare tables + diff="$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)" + + rm -f /tmp/image.bs /tmp/partmap.bootdisk /tmp/partmap.image + + if [ -n "$diff" ]; then + echo "Partition layout has changed. Full image will be written." + ask_bool 0 "Abort" && exit 1 + return 0 + fi +} + +platform_copy_config() { + local partdev + + if export_partdevice partdev 3; then + mount -t vfat -o rw,noatime "/dev/$partdev" /mnt + cp -af "$UPGRADE_BACKUP" "/mnt/$BACKUP_FILE" + umount /mnt + fi +} + +platform_do_upgrade() { + local diskdev partdev diff + + export_bootdevice && export_partdevice diskdev 0 || { + echo "Unable to determine upgrade device" + return 1 + } + + sync + + if [ "$UPGRADE_OPT_SAVE_PARTITIONS" = "1" ]; then + get_partitions "/dev/$diskdev" bootdisk + + #extract the boot sector from the image + get_image "$@" | dd of=/tmp/image.bs count=1 bs=512b + + get_partitions /tmp/image.bs image + + #compare tables + diff="$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)" + else + diff=1 + fi + + if [ -n "$diff" ]; then + get_image "$@" | dd of="/dev/$diskdev" bs=4096 conv=fsync + + # Separate removal and addtion is necessary; otherwise, partition 1 + # will be missing if it overlaps with the old partition 2 + partx -d - "/dev/$diskdev" + partx -a - "/dev/$diskdev" + + return 0 + fi + + #iterate over each partition from the image and write it to the boot disk + while read part start size; do + if export_partdevice partdev $part; then + echo "Writing image to /dev/$partdev..." + get_image "$@" | dd of="/dev/$partdev" ibs="512" obs=1M skip="$start" count="$size" conv=fsync + else + echo "Unable to find partition $part device, skipped." + fi + done < /tmp/partmap.image + + #copy partition uuid + echo "Writing new UUID to /dev/$diskdev..." + get_image "$@" | dd of="/dev/$diskdev" bs=1 skip=440 count=4 seek=440 conv=fsync +} diff --git a/target/linux/cv18x0/config-6.1 b/target/linux/cv18x0/config-6.1 new file mode 100644 index 0000000000..cd43d6885f --- /dev/null +++ b/target/linux/cv18x0/config-6.1 @@ -0,0 +1,389 @@ +CONFIG_64BIT=y +CONFIG_ARCH_CLOCKSOURCE_INIT=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_RV64I=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SOPHGO=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_WANTS_THP_SWAP=y +CONFIG_ASN1=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_ATA=y +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_MQ_PCI=y +CONFIG_CAVIUM_PTP=y +CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y +CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_CC_NO_ARRAY_BOUNDS=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CLZ_TAB=y +CONFIG_CMODEL_MEDANY=y +# CONFIG_CMODEL_MEDLOW is not set +CONFIG_COMMON_CLK=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +# CONFIG_COMPAT_32BIT_TIME is not set +CONFIG_COMPAT_BRK=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_COREDUMP=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_CPU_ISOLATION=y +CONFIG_CPU_RMAP=y +CONFIG_CRC16=y +# CONFIG_CRC32_SARWATE is not set +CONFIG_CRC32_SLICEBY8=y +CONFIG_CRC7=y +CONFIG_CRC_ITU_T=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_ECHAINIV=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_RSA=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_DEVTMPFS_SAFE is not set +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DNOTIFY=y +CONFIG_DTC=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_EDAC=y +# CONFIG_EDAC_DEBUG is not set +CONFIG_EDAC_LEGACY_SYSFS=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EFI=y +CONFIG_EFIVAR_FS=m +# CONFIG_EFI_BOOTLOADER_CONTROL is not set +# CONFIG_EFI_CAPSULE_LOADER is not set +# CONFIG_EFI_COCO_SECRET is not set +# CONFIG_EFI_DISABLE_PCI_DMA is not set +# CONFIG_EFI_DISABLE_RUNTIME is not set +CONFIG_EFI_EARLYCON=y +CONFIG_EFI_ESRT=y +CONFIG_EFI_GENERIC_STUB=y +CONFIG_EFI_PARAMS_FROM_FDT=y +CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_STUB=y +# CONFIG_EFI_TEST is not set +# CONFIG_EFI_ZBOOT is not set +CONFIG_ELF_CORE=y +CONFIG_ERRATA_SIFIVE=y +CONFIG_ERRATA_SIFIVE_CIP_1200=y +CONFIG_ERRATA_SIFIVE_CIP_453=y +# CONFIG_ERRATA_THEAD is not set +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_EXT4_FS=y +CONFIG_FAILOVER=y +CONFIG_FAT_FS=y +CONFIG_FHANDLE=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FONT_8x16=y +CONFIG_FONT_AUTOSELECT=y +CONFIG_FONT_SUPPORT=y +CONFIG_FPU=y +CONFIG_FRAME_POINTER=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GCC11_NO_ARRAY_BOUNDS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IOREMAP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_INJECTION=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GLOB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_CDEV_V1=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_SIFIVE=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HID=y +CONFIG_HID_GENERIC=y +CONFIG_HOTPLUG_PCI=y +# CONFIG_HOTPLUG_PCI_CPCI is not set +CONFIG_HOTPLUG_PCI_PCIE=y +CONFIG_HOTPLUG_PCI_SHPC=y +CONFIG_HVC_DRIVER=y +CONFIG_HVC_RISCV_SBI=y +CONFIG_HW_CONSOLE=y +CONFIG_HZ_PERIODIC=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_OCORES=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INPUT=y +# CONFIG_IOMMU_DEBUGFS is not set +CONFIG_IOMMU_SUPPORT=y +CONFIG_IO_URING=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_KALLSYMS=y +CONFIG_KEYS=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_TRIGGER_DISK=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +CONFIG_LIBFDT=y +CONFIG_LOCALVERSION_AUTO=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_MACB=y +# CONFIG_MACB_PCI is not set +CONFIG_MACB_USE_HWSTAMP=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MEMFD_CREATE=y +CONFIG_MFD_SYSCON=y +CONFIG_MICROSEMI_PHY=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_CADENCE=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SPI=y +CONFIG_MMIOWB=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_MODULE_SECTIONS=y +CONFIG_MPILIB=y +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NET_FAILOVER=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_SELFTESTS=y +CONFIG_NLS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NONPORTABLE is not set +CONFIG_NR_CPUS=8 +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_DMA_DEFAULT_COHERENT=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OID_REGISTRY=y +CONFIG_PADATA=y +CONFIG_PAGE_OFFSET=0xff60000000000000 +CONFIG_PAGE_POOL=y +CONFIG_PAGE_REPORTING=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEAER_INJECT=m +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_PERFORMANCE is not set +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_DPC=y +CONFIG_PCIE_ECRC=y +CONFIG_PCIE_PTM=y +CONFIG_PCIE_XILINX=y +CONFIG_PCI_DEBUG=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_ECAM=y +CONFIG_PCI_HOST_COMMON=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PCI_SW_SWITCHTEC=y +CONFIG_PGTABLE_LEVELS=5 +CONFIG_PHYLIB=y +CONFIG_PHYLINK=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_PORTABLE=y +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_GPIO_RESTART=y +CONFIG_POWER_RESET_RESTART=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_PPS=y +CONFIG_PREEMPT_NONE_BUILD=y +CONFIG_PRINTK_TIME=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_PWM=y +CONFIG_PWM_SIFIVE=y +CONFIG_PWM_SYSFS=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RAS=y +CONFIG_RATIONAL=y +CONFIG_RCU_TRACE=y +CONFIG_RD_GZIP=y +CONFIG_REALTEK_PHY=y +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +# CONFIG_RESET_ATTACK_MITIGATION is not set +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_SIMPLE=y +CONFIG_RFS_ACCEL=y +CONFIG_RISCV=y +CONFIG_RISCV_ALTERNATIVE=y +# CONFIG_RISCV_BOOT_SPINWAIT is not set +CONFIG_RISCV_DMA_NONCOHERENT=y +CONFIG_RISCV_INTC=y +CONFIG_RISCV_ISA_C=y +CONFIG_RISCV_ISA_SVPBMT=y +CONFIG_RISCV_ISA_ZICBOM=y +CONFIG_RISCV_SBI=y +CONFIG_RISCV_SBI_V01=y +CONFIG_RISCV_TIMER=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_EFI is not set +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SCHED_DEBUG=y +CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +CONFIG_SERIAL_8250_EXAR=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_EARLYCON_RISCV_SBI=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_SIFIVE=y +CONFIG_SERIAL_SIFIVE_CONSOLE=y +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SG_POOL=y +CONFIG_SIFIVE_PLIC=y +CONFIG_SLUB_DEBUG=y +CONFIG_SMP=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +# CONFIG_SOC_MICROCHIP_POLARFIRE is not set +# CONFIG_SOC_SIFIVE is not set +CONFIG_SOC_SOPHGO=y +# CONFIG_SOC_STARFIVE is not set +# CONFIG_SOC_VIRT is not set +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_SIFIVE=y +CONFIG_SRCU=y +CONFIG_STACKDEPOT=y +CONFIG_STACKTRACE=y +CONFIG_SWIOTLB=y +CONFIG_SWPHY=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +# CONFIG_SYSFB_SIMPLEFB is not set +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TOOLCHAIN_HAS_ZICBOM=y +CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE=y +CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y +CONFIG_TRACE_CLOCK=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_TUNE_GENERIC=y +CONFIG_UCS2_STRING=y +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +CONFIG_USB_EHCI_PCI=y +CONFIG_USB_HID=y +CONFIG_USB_NET_DRIVERS=y +CONFIG_USB_PCI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_SUPPORT=y +# CONFIG_USB_UHCI_HCD is not set +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y +# CONFIG_USB_XHCI_PLATFORM is not set +CONFIG_VFAT_FS=y +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +CONFIG_VMAP_STACK=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_WATCHDOG_CORE=y +CONFIG_XPS=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA32=y diff --git a/target/linux/cv18x0/generic/target.mk b/target/linux/cv18x0/generic/target.mk new file mode 100644 index 0000000000..f5cb1fb19b --- /dev/null +++ b/target/linux/cv18x0/generic/target.mk @@ -0,0 +1 @@ +BOARDNAME:=Generic diff --git a/target/linux/cv18x0/image/Config.in b/target/linux/cv18x0/image/Config.in new file mode 100644 index 0000000000..640869b92c --- /dev/null +++ b/target/linux/cv18x0/image/Config.in @@ -0,0 +1,5 @@ +config SIFIVEU_SD_BOOT_PARTSIZE + int "Boot (SD Card) filesystem partition size (in MB)" + depends on TARGET_sifiveu + default 32 + diff --git a/target/linux/cv18x0/image/Makefile b/target/linux/cv18x0/image/Makefile new file mode 100644 index 0000000000..ef3b13eeec --- /dev/null +++ b/target/linux/cv18x0/image/Makefile @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Copyright (C) 2022 Toco Technologies +# +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +FAT32_BLOCK_SIZE=1024 +FAT32_BLOCKS=$(shell echo $$(($(CONFIG_SIFIVEU_SD_BOOT_PARTSIZE)*1024*1024/$(FAT32_BLOCK_SIZE)))) + +KERNEL_LOADADDR:=0x80200000 + +define Build/riscv-sdcard + rm -f $@.boot #$(KDIR_TMP)/$(IMG_PREFIX)-$(PROFILE)-boot.img + mkfs.fat $@.boot -C $(FAT32_BLOCKS) + + mcopy -i $@.boot $(STAGING_DIR_IMAGE)/$(DEVICE_NAME)-boot.scr ::boot.scr + mcopy -i $@.boot $(DTS_DIR)/$(DEVICE_DTS).dtb ::dtb + mcopy -i $@.boot $(IMAGE_KERNEL) ::Image + + ./gen_sifiveu_sdcard_img.sh \ + $@ \ + $@.boot \ + $(IMAGE_ROOTFS) \ + $(CONFIG_SIFIVEU_SD_BOOT_PARTSIZE) \ + $(CONFIG_TARGET_ROOTFS_PARTSIZE) \ + $(STAGING_DIR_IMAGE)/$(DEVICE_NAME)-u-boot.itb \ + $(STAGING_DIR_IMAGE)/$(DEVICE_NAME)-u-boot.itb-spl +endef + +define Device/Default + PROFILES := Default + KERNEL_NAME := Image + KERNEL := kernel-bin | libdeflate-gzip + IMAGES := sdcard.img.gz + IMAGE/sdcard.img.gz := riscv-sdcard | append-metadata | gzip +endef + +define Device/sifive_unleashed + DEVICE_VENDOR := SiFive + DEVICE_MODEL := Unleashed (FU540) + DEVICE_DTS := sifive/hifive-unleashed-a00 + UBOOT := sifive_unleashed +endef +TARGET_DEVICES += sifive_unleashed + +define Device/sifive_unmatched + DEVICE_VENDOR := SiFive + DEVICE_MODEL := Unmatched (FU740) + DEVICE_DTS := sifive/hifive-unmatched-a00 + DEVICE_PACKAGES += kmod-eeprom-at24 kmod-hwmon-lm90 + UBOOT := sifive_unmatched +endef +TARGET_DEVICES += sifive_unmatched + +$(eval $(call BuildImage)) diff --git a/target/linux/cv18x0/image/gen_sifiveu_sdcard_img.sh b/target/linux/cv18x0/image/gen_sifiveu_sdcard_img.sh new file mode 100755 index 0000000000..172f62485d --- /dev/null +++ b/target/linux/cv18x0/image/gen_sifiveu_sdcard_img.sh @@ -0,0 +1,28 @@ +#!/usr/bin/env bash +# SPDX-License-Identifier: GPL-2.0-only +# +# Copyright (C) 2022 OpenWrt.org +# + +set -ex +[ $# -eq 7 ] || { + echo "SYNTAX: $0 " + exit 1 +} + +OUTPUT="$1" +BOOTFS="$2" +ROOTFS="$3" +BOOTFSSIZE="$4" +ROOTFSSIZE="$5" +UBOOT="$6" +UBOOT_SPL="$7" + +set $(ptgen -o $OUTPUT -v -g -T sifiveu_spl -N loader1 -p 1024 -T sifiveu_uboot -N loader2 -p 4096 -t ef -N boot -p ${BOOTFSSIZE}M -N rootfs -p ${ROOTFSSIZE}M) + +ROOTFSOFFSET=$(($7 / 512)) + +dd bs=512 if="$UBOOT_SPL" of="$OUTPUT" seek=34 conv=notrunc +dd bs=512 if="$UBOOT" of="$OUTPUT" seek=2082 conv=notrunc +dd bs=512 if="$BOOTFS" of="$OUTPUT" seek=10274 conv=notrunc +dd bs=512 if="$ROOTFS" of="$OUTPUT" seek=${ROOTFSOFFSET} conv=notrunc diff --git a/target/linux/cv18x0/patches-6.1/0001-riscv-Add-Sophgo-SoC-platform-hardware-support.patch b/target/linux/cv18x0/patches-6.1/0001-riscv-Add-Sophgo-SoC-platform-hardware-support.patch new file mode 100644 index 0000000000..c5708f0a2f --- /dev/null +++ b/target/linux/cv18x0/patches-6.1/0001-riscv-Add-Sophgo-SoC-platform-hardware-support.patch @@ -0,0 +1,30 @@ +From 1806dee5a588e8d5163a6ed50bff120bea364adb Mon Sep 17 00:00:00 2001 +From: Xiaoguang Xing +Date: Thu, 31 Aug 2023 10:21:03 +0800 +Subject: [PATCH 1/8] riscv: Add Sophgo SoC platform hardware support + +Signed-off-by: Xiaoguang Xing +--- + arch/riscv/Kconfig.socs | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs +index 69774bb362d6..ad10e249c1ce 100644 +--- a/arch/riscv/Kconfig.socs ++++ b/arch/riscv/Kconfig.socs +@@ -80,4 +80,12 @@ config SOC_CANAAN_K210_DTB_SOURCE + + endif # SOC_CANAAN + ++config ARCH_SOPHGO ++ def_bool SOC_SOPHGO ++ ++config SOC_SOPHGO ++ bool "Sophgo SoCs" ++ help ++ This enables support for Sophgo SoC platform hardware. ++ + endmenu # "SoC selection" +-- +2.20.1 + diff --git a/target/linux/cv18x0/patches-6.1/0002-dt-bindings-interrupt-controller-Add-SOPHGO-CV1800B-.patch b/target/linux/cv18x0/patches-6.1/0002-dt-bindings-interrupt-controller-Add-SOPHGO-CV1800B-.patch new file mode 100644 index 0000000000..c1620c524e --- /dev/null +++ b/target/linux/cv18x0/patches-6.1/0002-dt-bindings-interrupt-controller-Add-SOPHGO-CV1800B-.patch @@ -0,0 +1,29 @@ +From 17d33a3616fc0b35b06f7de34622b17c42d3cf9e Mon Sep 17 00:00:00 2001 +From: Jisheng Zhang +Date: Sat, 30 Sep 2023 20:39:33 +0800 +Subject: [PATCH 2/8] dt-bindings: interrupt-controller: Add SOPHGO CV1800B + plic + +Add compatible string for SOPHGO CV1800B plic. + +Signed-off-by: Jisheng Zhang +Acked-by: Conor Dooley +--- + .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +index 99e01f4d0a69..d1e99a99020f 100644 +--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml ++++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +@@ -65,6 +65,7 @@ properties: + - items: + - enum: + - allwinner,sun20i-d1-plic ++ - sophgo,cv1800-plic + - const: thead,c900-plic + - items: + - const: sifive,plic-1.0.0 +-- +2.20.1 + diff --git a/target/linux/cv18x0/patches-6.1/0003-dt-bindings-riscv-add-sophgo-sg2042-bindings.patch b/target/linux/cv18x0/patches-6.1/0003-dt-bindings-riscv-add-sophgo-sg2042-bindings.patch new file mode 100644 index 0000000000..7d7f7691fe --- /dev/null +++ b/target/linux/cv18x0/patches-6.1/0003-dt-bindings-riscv-add-sophgo-sg2042-bindings.patch @@ -0,0 +1,76 @@ +From 29d03ad2139273102509e94a0b472610e002eabc Mon Sep 17 00:00:00 2001 +From: Chen Wang +Date: Wed, 20 Sep 2023 14:37:51 +0800 +Subject: [PATCH 3/8] dt-bindings: riscv: add sophgo sg2042 bindings + +Add DT binding documentation for the Sophgo SG2042 Soc [1] and the +Milk-V Pioneer board [2]. + +[1]: https://en.sophgo.com/product/introduce/sg2042.html +[2]: https://milkv.io/pioneer + +Acked-by: Chao Wei +Acked-by: Xiaoguang Xing +Signed-off-by: Chen Wang +Reviewed-by: Guo Ren +--- + .../devicetree/bindings/riscv/sophgo.yaml | 28 +++++++++++++++++++ + MAINTAINERS | 7 +++++ + 2 files changed, 35 insertions(+) + create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml + +diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/riscv/sophgo.yaml +new file mode 100644 +index 000000000000..82468ae915db +--- /dev/null ++++ b/Documentation/devicetree/bindings/riscv/sophgo.yaml +@@ -0,0 +1,28 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/riscv/sophgo.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Sophgo SoC-based boards ++ ++maintainers: ++ - Chao Wei ++ - Xiaoguang Xing ++ ++description: ++ Sophgo SoC-based boards ++ ++properties: ++ $nodename: ++ const: '/' ++ compatible: ++ oneOf: ++ - items: ++ - enum: ++ - milkv,pioneer ++ - const: sophgo,sg2042 ++ ++additionalProperties: true ++ ++... +diff --git a/MAINTAINERS b/MAINTAINERS +index 07a9c274c0e2..7087239b17a1 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -19280,6 +19280,13 @@ F: drivers/char/sonypi.c + F: drivers/platform/x86/sony-laptop.c + F: include/linux/sony-laptop.h + ++SOPHGO DEVICETREES ++M: Xiaoguang Xing ++M: Chao Wei ++S: Maintained ++F: Documentation/devicetree/bindings/riscv/sophgo.yaml ++F: arch/riscv/boot/dts/sophgo/ ++ + SOUND + M: Jaroslav Kysela + M: Takashi Iwai +-- +2.20.1 + diff --git a/target/linux/cv18x0/patches-6.1/0004-dt-bindings-riscv-Add-Milk-V-Duo-board-compatibles.patch b/target/linux/cv18x0/patches-6.1/0004-dt-bindings-riscv-Add-Milk-V-Duo-board-compatibles.patch new file mode 100644 index 0000000000..6fa38a55be --- /dev/null +++ b/target/linux/cv18x0/patches-6.1/0004-dt-bindings-riscv-Add-Milk-V-Duo-board-compatibles.patch @@ -0,0 +1,35 @@ +From d31b4fc52ca63649429a8ef656f548e1647b7b57 Mon Sep 17 00:00:00 2001 +From: Jisheng Zhang +Date: Sat, 30 Sep 2023 20:39:35 +0800 +Subject: [PATCH 4/8] dt-bindings: riscv: Add Milk-V Duo board compatibles + +Document the compatible strings for the Milk-V Duo board[1] which uses +the SOPHGO CV1800B SoC[2]. + +Link: https://milkv.io/duo [1] +Link: https://en.sophgo.com/product/introduce/cv180xB.html [2] +Signed-off-by: Jisheng Zhang +Acked-by: Conor Dooley +Acked-by: Chen Wang +--- + Documentation/devicetree/bindings/riscv/sophgo.yaml | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/riscv/sophgo.yaml +index 82468ae915db..170a1ab04259 100644 +--- a/Documentation/devicetree/bindings/riscv/sophgo.yaml ++++ b/Documentation/devicetree/bindings/riscv/sophgo.yaml +@@ -18,6 +18,10 @@ properties: + const: '/' + compatible: + oneOf: ++ - items: ++ - enum: ++ - milkv,duo ++ - const: sophgo,cv1800b + - items: + - enum: + - milkv,pioneer +-- +2.20.1 + diff --git a/target/linux/cv18x0/patches-6.1/0005-riscv-dts-sophgo-add-initial-CV1800B-SoC-device-tree.patch b/target/linux/cv18x0/patches-6.1/0005-riscv-dts-sophgo-add-initial-CV1800B-SoC-device-tree.patch new file mode 100644 index 0000000000..86d8f8afde --- /dev/null +++ b/target/linux/cv18x0/patches-6.1/0005-riscv-dts-sophgo-add-initial-CV1800B-SoC-device-tree.patch @@ -0,0 +1,139 @@ +From 47b459f4be54b4ba25dda60401c1489804a64e98 Mon Sep 17 00:00:00 2001 +From: Jisheng Zhang +Date: Sat, 30 Sep 2023 20:39:36 +0800 +Subject: [PATCH 5/8] riscv: dts: sophgo: add initial CV1800B SoC device tree + +Add initial device tree for the CV1800B RISC-V SoC by SOPHGO. + +Signed-off-by: Jisheng Zhang +--- + arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 117 ++++++++++++++++++++++++ + 1 file changed, 117 insertions(+) + create mode 100644 arch/riscv/boot/dts/sophgo/cv1800b.dtsi + +diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi +new file mode 100644 +index 000000000000..8829bebaa017 +--- /dev/null ++++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi +@@ -0,0 +1,117 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2023 Jisheng Zhang ++ */ ++ ++#include ++ ++/ { ++ compatible = "sophgo,cv1800b"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ cpus: cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ timebase-frequency = <25000000>; ++ ++ cpu0: cpu@0 { ++ compatible = "thead,c906", "riscv"; ++ device_type = "cpu"; ++ reg = <0>; ++ d-cache-block-size = <64>; ++ d-cache-sets = <512>; ++ d-cache-size = <65536>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <128>; ++ i-cache-size = <32768>; ++ mmu-type = "riscv,sv39"; ++ riscv,isa = "rv64imafdc"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", ++ "zifencei", "zihpm"; ++ ++ cpu0_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ }; ++ ++ osc: oscillator { ++ compatible = "fixed-clock"; ++ clock-output-names = "osc_25m"; ++ #clock-cells = <0>; ++ }; ++ ++ soc { ++ compatible = "simple-bus"; ++ interrupt-parent = <&plic>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ dma-noncoherent; ++ ranges; ++ ++ uart0: serial@04140000 { ++ compatible = "snps,dw-apb-uart"; ++ reg = <0x04140000 0x100>; ++ interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&osc>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ status = "disabled"; ++ }; ++ ++ uart1: serial@04150000 { ++ compatible = "snps,dw-apb-uart"; ++ reg = <0x04150000 0x100>; ++ interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&osc>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ status = "disabled"; ++ }; ++ ++ uart2: serial@04160000 { ++ compatible = "snps,dw-apb-uart"; ++ reg = <0x04160000 0x100>; ++ interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&osc>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ status = "disabled"; ++ }; ++ ++ uart3: serial@04170000 { ++ compatible = "snps,dw-apb-uart"; ++ reg = <0x04170000 0x100>; ++ interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&osc>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ status = "disabled"; ++ }; ++ ++ uart4: serial@041c0000 { ++ compatible = "snps,dw-apb-uart"; ++ reg = <0x041c0000 0x100>; ++ interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&osc>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ status = "disabled"; ++ }; ++ ++ plic: interrupt-controller@70000000 { ++ compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; ++ reg = <0x70000000 0x4000000>; ++ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; ++ interrupt-controller; ++ #address-cells = <0>; ++ #interrupt-cells = <2>; ++ riscv,ndev = <101>; ++ }; ++ }; ++}; +-- +2.20.1 + diff --git a/target/linux/cv18x0/patches-6.1/0006-riscv-dts-add-initial-SOPHGO-SG2042-SoC-device-tree.patch b/target/linux/cv18x0/patches-6.1/0006-riscv-dts-add-initial-SOPHGO-SG2042-SoC-device-tree.patch new file mode 100644 index 0000000000..90840f7e18 --- /dev/null +++ b/target/linux/cv18x0/patches-6.1/0006-riscv-dts-add-initial-SOPHGO-SG2042-SoC-device-tree.patch @@ -0,0 +1,2232 @@ +From 16bc0d77852c4930a81d88b0ec425cee5bb6eae6 Mon Sep 17 00:00:00 2001 +From: Chen Wang +Date: Wed, 20 Sep 2023 14:40:32 +0800 +Subject: [PATCH 6/8] riscv: dts: add initial SOPHGO SG2042 SoC device tree + +Milk-V Pioneer motherboard is powered by SOPHON's SG2042. + +SG2042 is server grade chip with high performance, low power +consumption and high data throughput. +Key features: +- 64 RISC-V cpu cores which implements IMAFDC +- 4 cores per cluster, 16 clusters on chip +- ...... + +More info is available at [1]. + +[1]: https://en.sophgo.com/product/introduce/sg2042.html + +Currently only support booting into console with only uart, +other features will be added soon later. + +Acked-by: Xiaoguang Xing +Signed-off-by: Xiaoguang Xing +Signed-off-by: Inochi Amaoto +Signed-off-by: Emil Renner Berthing +Signed-off-by: Chen Wang +Reviewed-by: Guo Ren +--- + arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 1744 +++++++++++++++++++ + arch/riscv/boot/dts/sophgo/sg2042.dtsi | 439 +++++ + 2 files changed, 2183 insertions(+) + create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi + create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi + +diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +new file mode 100644 +index 000000000000..9fc79b1cf3bf +--- /dev/null ++++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +@@ -0,0 +1,1744 @@ ++// SPDX-License-Identifier: GPL-2.0 OR MIT ++/* ++ * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved. ++ */ ++ ++/ { ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ timebase-frequency = <50000000>; ++ ++ cpu-map { ++ socket0 { ++ cluster0 { ++ core0 { ++ cpu = <&cpu0>; ++ }; ++ core1 { ++ cpu = <&cpu1>; ++ }; ++ core2 { ++ cpu = <&cpu2>; ++ }; ++ core3 { ++ cpu = <&cpu3>; ++ }; ++ }; ++ ++ cluster1 { ++ core0 { ++ cpu = <&cpu4>; ++ }; ++ core1 { ++ cpu = <&cpu5>; ++ }; ++ core2 { ++ cpu = <&cpu6>; ++ }; ++ core3 { ++ cpu = <&cpu7>; ++ }; ++ }; ++ ++ cluster2 { ++ core0 { ++ cpu = <&cpu16>; ++ }; ++ core1 { ++ cpu = <&cpu17>; ++ }; ++ core2 { ++ cpu = <&cpu18>; ++ }; ++ core3 { ++ cpu = <&cpu19>; ++ }; ++ }; ++ ++ cluster3 { ++ core0 { ++ cpu = <&cpu20>; ++ }; ++ core1 { ++ cpu = <&cpu21>; ++ }; ++ core2 { ++ cpu = <&cpu22>; ++ }; ++ core3 { ++ cpu = <&cpu23>; ++ }; ++ }; ++ ++ cluster4 { ++ core0 { ++ cpu = <&cpu8>; ++ }; ++ core1 { ++ cpu = <&cpu9>; ++ }; ++ core2 { ++ cpu = <&cpu10>; ++ }; ++ core3 { ++ cpu = <&cpu11>; ++ }; ++ }; ++ ++ cluster5 { ++ core0 { ++ cpu = <&cpu12>; ++ }; ++ core1 { ++ cpu = <&cpu13>; ++ }; ++ core2 { ++ cpu = <&cpu14>; ++ }; ++ core3 { ++ cpu = <&cpu15>; ++ }; ++ }; ++ ++ cluster6 { ++ core0 { ++ cpu = <&cpu24>; ++ }; ++ core1 { ++ cpu = <&cpu25>; ++ }; ++ core2 { ++ cpu = <&cpu26>; ++ }; ++ core3 { ++ cpu = <&cpu27>; ++ }; ++ }; ++ ++ cluster7 { ++ core0 { ++ cpu = <&cpu28>; ++ }; ++ core1 { ++ cpu = <&cpu29>; ++ }; ++ core2 { ++ cpu = <&cpu30>; ++ }; ++ core3 { ++ cpu = <&cpu31>; ++ }; ++ }; ++ ++ cluster8 { ++ core0 { ++ cpu = <&cpu32>; ++ }; ++ core1 { ++ cpu = <&cpu33>; ++ }; ++ core2 { ++ cpu = <&cpu34>; ++ }; ++ core3 { ++ cpu = <&cpu35>; ++ }; ++ }; ++ ++ cluster9 { ++ core0 { ++ cpu = <&cpu36>; ++ }; ++ core1 { ++ cpu = <&cpu37>; ++ }; ++ core2 { ++ cpu = <&cpu38>; ++ }; ++ core3 { ++ cpu = <&cpu39>; ++ }; ++ }; ++ ++ cluster10 { ++ core0 { ++ cpu = <&cpu48>; ++ }; ++ core1 { ++ cpu = <&cpu49>; ++ }; ++ core2 { ++ cpu = <&cpu50>; ++ }; ++ core3 { ++ cpu = <&cpu51>; ++ }; ++ }; ++ ++ cluster11 { ++ core0 { ++ cpu = <&cpu52>; ++ }; ++ core1 { ++ cpu = <&cpu53>; ++ }; ++ core2 { ++ cpu = <&cpu54>; ++ }; ++ core3 { ++ cpu = <&cpu55>; ++ }; ++ }; ++ ++ cluster12 { ++ core0 { ++ cpu = <&cpu40>; ++ }; ++ core1 { ++ cpu = <&cpu41>; ++ }; ++ core2 { ++ cpu = <&cpu42>; ++ }; ++ core3 { ++ cpu = <&cpu43>; ++ }; ++ }; ++ ++ cluster13 { ++ core0 { ++ cpu = <&cpu44>; ++ }; ++ core1 { ++ cpu = <&cpu45>; ++ }; ++ core2 { ++ cpu = <&cpu46>; ++ }; ++ core3 { ++ cpu = <&cpu47>; ++ }; ++ }; ++ ++ cluster14 { ++ core0 { ++ cpu = <&cpu56>; ++ }; ++ core1 { ++ cpu = <&cpu57>; ++ }; ++ core2 { ++ cpu = <&cpu58>; ++ }; ++ core3 { ++ cpu = <&cpu59>; ++ }; ++ }; ++ ++ cluster15 { ++ core0 { ++ cpu = <&cpu60>; ++ }; ++ core1 { ++ cpu = <&cpu61>; ++ }; ++ core2 { ++ cpu = <&cpu62>; ++ }; ++ core3 { ++ cpu = <&cpu63>; ++ }; ++ }; ++ }; ++ }; ++ ++ cpu0: cpu@0 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <0>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache0>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu0_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu1: cpu@1 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <1>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache0>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu1_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu2: cpu@2 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <2>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache0>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu2_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu3: cpu@3 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <3>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache0>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu3_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu4: cpu@4 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <4>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache1>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu4_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu5: cpu@5 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <5>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache1>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu5_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu6: cpu@6 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <6>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache1>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu6_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu7: cpu@7 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <7>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache1>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu7_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu8: cpu@8 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <8>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache4>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu8_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu9: cpu@9 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <9>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache4>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu9_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu10: cpu@10 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <10>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache4>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu10_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu11: cpu@11 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <11>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache4>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu11_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu12: cpu@12 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <12>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache5>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu12_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu13: cpu@13 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <13>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache5>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu13_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu14: cpu@14 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <14>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache5>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu14_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu15: cpu@15 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <15>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache5>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu15_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu16: cpu@16 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <16>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache2>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu16_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu17: cpu@17 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <17>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache2>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu17_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu18: cpu@18 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <18>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache2>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu18_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu19: cpu@19 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <19>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache2>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu19_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu20: cpu@20 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <20>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache3>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu20_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu21: cpu@21 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <21>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache3>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu21_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu22: cpu@22 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <22>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache3>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu22_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu23: cpu@23 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <23>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache3>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu23_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu24: cpu@24 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <24>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache6>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu24_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu25: cpu@25 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <25>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache6>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu25_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu26: cpu@26 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <26>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache6>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu26_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu27: cpu@27 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <27>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache6>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu27_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu28: cpu@28 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <28>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache7>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu28_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu29: cpu@29 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <29>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache7>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu29_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu30: cpu@30 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <30>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache7>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu30_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu31: cpu@31 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <31>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache7>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu31_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu32: cpu@32 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <32>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache8>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu32_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu33: cpu@33 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <33>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache8>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu33_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu34: cpu@34 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <34>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache8>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu34_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu35: cpu@35 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <35>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache8>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu35_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu36: cpu@36 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <36>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache9>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu36_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu37: cpu@37 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <37>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache9>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu37_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu38: cpu@38 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <38>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache9>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu38_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu39: cpu@39 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <39>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache9>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu39_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu40: cpu@40 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <40>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache12>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu40_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu41: cpu@41 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <41>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache12>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu41_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu42: cpu@42 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <42>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache12>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu42_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu43: cpu@43 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <43>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache12>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu43_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu44: cpu@44 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <44>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache13>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu44_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu45: cpu@45 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <45>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache13>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu45_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu46: cpu@46 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <46>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache13>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu46_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu47: cpu@47 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <47>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache13>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu47_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu48: cpu@48 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <48>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache10>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu48_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu49: cpu@49 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <49>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache10>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu49_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu50: cpu@50 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <50>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache10>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu50_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu51: cpu@51 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <51>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache10>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu51_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu52: cpu@52 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <52>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache11>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu52_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu53: cpu@53 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <53>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache11>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu53_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu54: cpu@54 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <54>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache11>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu54_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu55: cpu@55 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <55>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache11>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu55_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu56: cpu@56 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <56>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache14>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu56_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu57: cpu@57 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <57>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache14>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu57_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu58: cpu@58 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <58>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache14>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu58_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu59: cpu@59 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <59>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache14>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu59_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu60: cpu@60 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <60>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache15>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu60_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu61: cpu@61 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <61>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache15>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu61_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu62: cpu@62 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <62>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache15>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu62_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu63: cpu@63 { ++ compatible = "thead,c920", "riscv"; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdc"; ++ reg = <63>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <512>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <512>; ++ next-level-cache = <&l2_cache15>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu63_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ l2_cache0: l2-cache@0 { ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <1048576>; ++ cache-sets = <1024>; ++ cache-unified; ++ }; ++ ++ l2_cache1: l2-cache@1 { ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <1048576>; ++ cache-sets = <1024>; ++ cache-unified; ++ }; ++ ++ l2_cache2: l2-cache@2 { ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <1048576>; ++ cache-sets = <1024>; ++ cache-unified; ++ }; ++ ++ l2_cache3: l2-cache@3 { ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <1048576>; ++ cache-sets = <1024>; ++ cache-unified; ++ }; ++ ++ l2_cache4: l2-cache@4 { ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <1048576>; ++ cache-sets = <1024>; ++ cache-unified; ++ }; ++ ++ l2_cache5: l2-cache@5 { ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <1048576>; ++ cache-sets = <1024>; ++ cache-unified; ++ }; ++ ++ l2_cache6: l2-cache@6 { ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <1048576>; ++ cache-sets = <1024>; ++ cache-unified; ++ }; ++ ++ l2_cache7: l2-cache@7 { ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <1048576>; ++ cache-sets = <1024>; ++ cache-unified; ++ }; ++ ++ l2_cache8: l2-cache@8 { ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <1048576>; ++ cache-sets = <1024>; ++ cache-unified; ++ }; ++ ++ l2_cache9: l2-cache@9 { ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <1048576>; ++ cache-sets = <1024>; ++ cache-unified; ++ }; ++ ++ l2_cache10: l2-cache@10 { ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <1048576>; ++ cache-sets = <1024>; ++ cache-unified; ++ }; ++ ++ l2_cache11: l2-cache@11 { ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <1048576>; ++ cache-sets = <1024>; ++ cache-unified; ++ }; ++ ++ l2_cache12: l2-cache@12 { ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <1048576>; ++ cache-sets = <1024>; ++ cache-unified; ++ }; ++ ++ l2_cache13: l2-cache@13 { ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <1048576>; ++ cache-sets = <1024>; ++ cache-unified; ++ }; ++ ++ l2_cache14: l2-cache@14 { ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <1048576>; ++ cache-sets = <1024>; ++ cache-unified; ++ }; ++ ++ l2_cache15: l2-cache@15 { ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <1048576>; ++ cache-sets = <1024>; ++ cache-unified; ++ }; ++ }; ++}; +diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi +new file mode 100644 +index 000000000000..747fd9764c95 +--- /dev/null ++++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi +@@ -0,0 +1,439 @@ ++// SPDX-License-Identifier: GPL-2.0 OR MIT ++/* ++ * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved. ++ */ ++ ++/dts-v1/; ++#include ++ ++#include "sg2042-cpus.dtsi" ++ ++#define SOC_PERIPHERAL_IRQ(nr) (nr) ++ ++/ { ++ compatible = "sophgo,sg2042"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ dma-noncoherent; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ /* the mem node will be updated by ZSBL. */ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x00000000 0x00000000 0x00000000 0x00000000>; ++ }; ++ ++ memory@1 { ++ device_type = "memory"; ++ reg = <0x00000000 0x00000001 0x00000000 0x00000000>; ++ }; ++ ++ memory@2 { ++ device_type = "memory"; ++ reg = <0x00000000 0x00000002 0x00000000 0x00000000>; ++ }; ++ ++ memory@3 { ++ device_type = "memory"; ++ reg = <0x00000000 0x00000003 0x00000000 0x00000000>; ++ }; ++ ++ pmu { ++ compatible = "riscv,pmu"; ++ riscv,event-to-mhpmevent = ++ <0x00003 0x00000000 0x00000010>, ++ <0x00004 0x00000000 0x00000011>, ++ <0x00005 0x00000000 0x00000007>, ++ <0x00006 0x00000000 0x00000006>, ++ <0x00008 0x00000000 0x00000027>, ++ <0x00009 0x00000000 0x00000028>, ++ <0x10000 0x00000000 0x0000000c>, ++ <0x10001 0x00000000 0x0000000d>, ++ <0x10002 0x00000000 0x0000000e>, ++ <0x10003 0x00000000 0x0000000f>, ++ <0x10008 0x00000000 0x00000001>, ++ <0x10009 0x00000000 0x00000002>, ++ <0x10010 0x00000000 0x00000010>, ++ <0x10011 0x00000000 0x00000011>, ++ <0x10012 0x00000000 0x00000012>, ++ <0x10013 0x00000000 0x00000013>, ++ <0x10019 0x00000000 0x00000004>, ++ <0x10021 0x00000000 0x00000003>, ++ <0x10030 0x00000000 0x0000001c>, ++ <0x10031 0x00000000 0x0000001b>; ++ riscv,event-to-mhpmcounters = ++ <0x00003 0x00003 0xfffffff8>, ++ <0x00004 0x00004 0xfffffff8>, ++ <0x00005 0x00005 0xfffffff8>, ++ <0x00006 0x00006 0xfffffff8>, ++ <0x00007 0x00007 0xfffffff8>, ++ <0x00008 0x00008 0xfffffff8>, ++ <0x00009 0x00009 0xfffffff8>, ++ <0x0000a 0x0000a 0xfffffff8>, ++ <0x10000 0x10000 0xfffffff8>, ++ <0x10001 0x10001 0xfffffff8>, ++ <0x10002 0x10002 0xfffffff8>, ++ <0x10003 0x10003 0xfffffff8>, ++ <0x10008 0x10008 0xfffffff8>, ++ <0x10009 0x10009 0xfffffff8>, ++ <0x10010 0x10010 0xfffffff8>, ++ <0x10011 0x10011 0xfffffff8>, ++ <0x10012 0x10012 0xfffffff8>, ++ <0x10013 0x10013 0xfffffff8>, ++ <0x10019 0x10019 0xfffffff8>, ++ <0x10021 0x10021 0xfffffff8>, ++ <0x10030 0x10030 0xfffffff8>, ++ <0x10031 0x10031 0xfffffff8>; ++ riscv,raw-event-to-mhpmcounters = ++ <0x00000000 0x00000001 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x00000002 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x00000003 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x00000004 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x00000005 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x00000006 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x00000007 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x00000008 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x00000009 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x0000000a 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x0000000b 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x0000000c 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x0000000d 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x0000000e 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x0000000f 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x00000010 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x00000011 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x00000012 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x00000013 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x00000014 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x00000015 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x00000016 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x00000017 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x00000018 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x00000019 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x0000001a 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x0000001b 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x0000001c 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x0000001d 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x0000001e 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x0000001f 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x00000020 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x00000021 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x00000022 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x00000023 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x00000024 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x00000025 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x00000026 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x00000027 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x00000028 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x00000029 0xffffffff 0xffffffff 0xfffffff8>, ++ <0x00000000 0x0000002a 0xffffffff 0xffffffff 0xfffffff8>; ++ }; ++ ++ soc: soc { ++ compatible = "simple-bus"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ clint_mswi: interrupt-controller@7094000000 { ++ compatible = "sophgo,sg2042-clint-mswi", "thead,c900-clint-mswi"; ++ reg = <0x00000070 0x94000000 0x00000000 0x00004000>; ++ interrupts-extended = <&cpu0_intc 3>, ++ <&cpu1_intc 3>, ++ <&cpu2_intc 3>, ++ <&cpu3_intc 3>, ++ <&cpu4_intc 3>, ++ <&cpu5_intc 3>, ++ <&cpu6_intc 3>, ++ <&cpu7_intc 3>, ++ <&cpu8_intc 3>, ++ <&cpu9_intc 3>, ++ <&cpu10_intc 3>, ++ <&cpu11_intc 3>, ++ <&cpu12_intc 3>, ++ <&cpu13_intc 3>, ++ <&cpu14_intc 3>, ++ <&cpu15_intc 3>, ++ <&cpu16_intc 3>, ++ <&cpu17_intc 3>, ++ <&cpu18_intc 3>, ++ <&cpu19_intc 3>, ++ <&cpu20_intc 3>, ++ <&cpu21_intc 3>, ++ <&cpu22_intc 3>, ++ <&cpu23_intc 3>, ++ <&cpu24_intc 3>, ++ <&cpu25_intc 3>, ++ <&cpu26_intc 3>, ++ <&cpu27_intc 3>, ++ <&cpu28_intc 3>, ++ <&cpu29_intc 3>, ++ <&cpu30_intc 3>, ++ <&cpu31_intc 3>, ++ <&cpu32_intc 3>, ++ <&cpu33_intc 3>, ++ <&cpu34_intc 3>, ++ <&cpu35_intc 3>, ++ <&cpu36_intc 3>, ++ <&cpu37_intc 3>, ++ <&cpu38_intc 3>, ++ <&cpu39_intc 3>, ++ <&cpu40_intc 3>, ++ <&cpu41_intc 3>, ++ <&cpu42_intc 3>, ++ <&cpu43_intc 3>, ++ <&cpu44_intc 3>, ++ <&cpu45_intc 3>, ++ <&cpu46_intc 3>, ++ <&cpu47_intc 3>, ++ <&cpu48_intc 3>, ++ <&cpu49_intc 3>, ++ <&cpu50_intc 3>, ++ <&cpu51_intc 3>, ++ <&cpu52_intc 3>, ++ <&cpu53_intc 3>, ++ <&cpu54_intc 3>, ++ <&cpu55_intc 3>, ++ <&cpu56_intc 3>, ++ <&cpu57_intc 3>, ++ <&cpu58_intc 3>, ++ <&cpu59_intc 3>, ++ <&cpu60_intc 3>, ++ <&cpu61_intc 3>, ++ <&cpu62_intc 3>, ++ <&cpu63_intc 3>; ++ }; ++ ++ clint_mtimer0: timer@70ac000000 { ++ compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; ++ reg = <0x00000070 0xac000000 0x00000000 0x00007ff8>; ++ interrupts-extended = <&cpu0_intc 7>, ++ <&cpu1_intc 7>, ++ <&cpu2_intc 7>, ++ <&cpu3_intc 7>; ++ }; ++ ++ clint_mtimer1: timer@70ac010000 { ++ compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; ++ reg = <0x00000070 0xac010000 0x00000000 0x00007ff8>; ++ interrupts-extended = <&cpu4_intc 7>, ++ <&cpu5_intc 7>, ++ <&cpu6_intc 7>, ++ <&cpu7_intc 7>; ++ }; ++ ++ clint_mtimer2: timer@70ac020000 { ++ compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; ++ reg = <0x00000070 0xac020000 0x00000000 0x00007ff8>; ++ interrupts-extended = <&cpu8_intc 7>, ++ <&cpu9_intc 7>, ++ <&cpu10_intc 7>, ++ <&cpu11_intc 7>; ++ }; ++ ++ clint_mtimer3: timer@70ac030000 { ++ compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; ++ reg = <0x00000070 0xac030000 0x00000000 0x00007ff8>; ++ interrupts-extended = <&cpu12_intc 7>, ++ <&cpu13_intc 7>, ++ <&cpu14_intc 7>, ++ <&cpu15_intc 7>; ++ }; ++ ++ clint_mtimer4: timer@70ac040000 { ++ compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; ++ reg = <0x00000070 0xac040000 0x00000000 0x00007ff8>; ++ interrupts-extended = <&cpu16_intc 7>, ++ <&cpu17_intc 7>, ++ <&cpu18_intc 7>, ++ <&cpu19_intc 7>; ++ }; ++ ++ clint_mtimer5: timer@70ac050000 { ++ compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; ++ reg = <0x00000070 0xac050000 0x00000000 0x00007ff8>; ++ interrupts-extended = <&cpu20_intc 7>, ++ <&cpu21_intc 7>, ++ <&cpu22_intc 7>, ++ <&cpu23_intc 7>; ++ }; ++ ++ clint_mtimer6: timer@70ac060000 { ++ compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; ++ reg = <0x00000070 0xac060000 0x00000000 0x00007ff8>; ++ interrupts-extended = <&cpu24_intc 7>, ++ <&cpu25_intc 7>, ++ <&cpu26_intc 7>, ++ <&cpu27_intc 7>; ++ }; ++ ++ clint_mtimer7: timer@70ac070000 { ++ compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; ++ reg = <0x00000070 0xac070000 0x00000000 0x00007ff8>; ++ interrupts-extended = <&cpu28_intc 7>, ++ <&cpu29_intc 7>, ++ <&cpu30_intc 7>, ++ <&cpu31_intc 7>; ++ }; ++ ++ clint_mtimer8: timer@70ac080000 { ++ compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; ++ reg = <0x00000070 0xac080000 0x00000000 0x00007ff8>; ++ interrupts-extended = <&cpu32_intc 7>, ++ <&cpu33_intc 7>, ++ <&cpu34_intc 7>, ++ <&cpu35_intc 7>; ++ }; ++ ++ clint_mtimer9: timer@70ac090000 { ++ compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; ++ reg = <0x00000070 0xac090000 0x00000000 0x00007ff8>; ++ interrupts-extended = <&cpu36_intc 7>, ++ <&cpu37_intc 7>, ++ <&cpu38_intc 7>, ++ <&cpu39_intc 7>; ++ }; ++ ++ clint_mtimer10: timer@70ac0a0000 { ++ compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; ++ reg = <0x00000070 0xac0a0000 0x00000000 0x00007ff8>; ++ interrupts-extended = <&cpu40_intc 7>, ++ <&cpu41_intc 7>, ++ <&cpu42_intc 7>, ++ <&cpu43_intc 7>; ++ }; ++ ++ clint_mtimer11: timer@70ac0b0000 { ++ compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; ++ reg = <0x00000070 0xac0b0000 0x00000000 0x00007ff8>; ++ interrupts-extended = <&cpu44_intc 7>, ++ <&cpu45_intc 7>, ++ <&cpu46_intc 7>, ++ <&cpu47_intc 7>; ++ }; ++ ++ clint_mtimer12: timer@70ac0c0000 { ++ compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; ++ reg = <0x00000070 0xac0c0000 0x00000000 0x00007ff8>; ++ interrupts-extended = <&cpu48_intc 7>, ++ <&cpu49_intc 7>, ++ <&cpu50_intc 7>, ++ <&cpu51_intc 7>; ++ }; ++ ++ clint_mtimer13: timer@70ac0d0000 { ++ compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; ++ reg = <0x00000070 0xac0d0000 0x00000000 0x00007ff8>; ++ interrupts-extended = <&cpu52_intc 7>, ++ <&cpu53_intc 7>, ++ <&cpu54_intc 7>, ++ <&cpu55_intc 7>; ++ }; ++ ++ clint_mtimer14: timer@70ac0e0000 { ++ compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; ++ reg = <0x00000070 0xac0e0000 0x00000000 0x00007ff8>; ++ interrupts-extended = <&cpu56_intc 7>, ++ <&cpu57_intc 7>, ++ <&cpu58_intc 7>, ++ <&cpu59_intc 7>; ++ }; ++ ++ clint_mtimer15: timer@70ac0f0000 { ++ compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; ++ reg = <0x00000070 0xac0f0000 0x00000000 0x00007ff8>; ++ interrupts-extended = <&cpu60_intc 7>, ++ <&cpu61_intc 7>, ++ <&cpu62_intc 7>, ++ <&cpu63_intc 7>; ++ }; ++ ++ intc: interrupt-controller@7090000000 { ++ compatible = "sophgo,sg2042-plic", "thead,c900-plic"; ++ #address-cells = <0>; ++ #interrupt-cells = <2>; ++ reg = <0x00000070 0x90000000 0x00000000 0x04000000>; ++ interrupt-controller; ++ interrupts-extended = ++ <&cpu0_intc 0xffffffff>, <&cpu0_intc 9>, ++ <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>, ++ <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>, ++ <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>, ++ <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>, ++ <&cpu5_intc 0xffffffff>, <&cpu5_intc 9>, ++ <&cpu6_intc 0xffffffff>, <&cpu6_intc 9>, ++ <&cpu7_intc 0xffffffff>, <&cpu7_intc 9>, ++ <&cpu8_intc 0xffffffff>, <&cpu8_intc 9>, ++ <&cpu9_intc 0xffffffff>, <&cpu9_intc 9>, ++ <&cpu10_intc 0xffffffff>, <&cpu10_intc 9>, ++ <&cpu11_intc 0xffffffff>, <&cpu11_intc 9>, ++ <&cpu12_intc 0xffffffff>, <&cpu12_intc 9>, ++ <&cpu13_intc 0xffffffff>, <&cpu13_intc 9>, ++ <&cpu14_intc 0xffffffff>, <&cpu14_intc 9>, ++ <&cpu15_intc 0xffffffff>, <&cpu15_intc 9>, ++ <&cpu16_intc 0xffffffff>, <&cpu16_intc 9>, ++ <&cpu17_intc 0xffffffff>, <&cpu17_intc 9>, ++ <&cpu18_intc 0xffffffff>, <&cpu18_intc 9>, ++ <&cpu19_intc 0xffffffff>, <&cpu19_intc 9>, ++ <&cpu20_intc 0xffffffff>, <&cpu20_intc 9>, ++ <&cpu21_intc 0xffffffff>, <&cpu21_intc 9>, ++ <&cpu22_intc 0xffffffff>, <&cpu22_intc 9>, ++ <&cpu23_intc 0xffffffff>, <&cpu23_intc 9>, ++ <&cpu24_intc 0xffffffff>, <&cpu24_intc 9>, ++ <&cpu25_intc 0xffffffff>, <&cpu25_intc 9>, ++ <&cpu26_intc 0xffffffff>, <&cpu26_intc 9>, ++ <&cpu27_intc 0xffffffff>, <&cpu27_intc 9>, ++ <&cpu28_intc 0xffffffff>, <&cpu28_intc 9>, ++ <&cpu29_intc 0xffffffff>, <&cpu29_intc 9>, ++ <&cpu30_intc 0xffffffff>, <&cpu30_intc 9>, ++ <&cpu31_intc 0xffffffff>, <&cpu31_intc 9>, ++ <&cpu32_intc 0xffffffff>, <&cpu32_intc 9>, ++ <&cpu33_intc 0xffffffff>, <&cpu33_intc 9>, ++ <&cpu34_intc 0xffffffff>, <&cpu34_intc 9>, ++ <&cpu35_intc 0xffffffff>, <&cpu35_intc 9>, ++ <&cpu36_intc 0xffffffff>, <&cpu36_intc 9>, ++ <&cpu37_intc 0xffffffff>, <&cpu37_intc 9>, ++ <&cpu38_intc 0xffffffff>, <&cpu38_intc 9>, ++ <&cpu39_intc 0xffffffff>, <&cpu39_intc 9>, ++ <&cpu40_intc 0xffffffff>, <&cpu40_intc 9>, ++ <&cpu41_intc 0xffffffff>, <&cpu41_intc 9>, ++ <&cpu42_intc 0xffffffff>, <&cpu42_intc 9>, ++ <&cpu43_intc 0xffffffff>, <&cpu43_intc 9>, ++ <&cpu44_intc 0xffffffff>, <&cpu44_intc 9>, ++ <&cpu45_intc 0xffffffff>, <&cpu45_intc 9>, ++ <&cpu46_intc 0xffffffff>, <&cpu46_intc 9>, ++ <&cpu47_intc 0xffffffff>, <&cpu47_intc 9>, ++ <&cpu48_intc 0xffffffff>, <&cpu48_intc 9>, ++ <&cpu49_intc 0xffffffff>, <&cpu49_intc 9>, ++ <&cpu50_intc 0xffffffff>, <&cpu50_intc 9>, ++ <&cpu51_intc 0xffffffff>, <&cpu51_intc 9>, ++ <&cpu52_intc 0xffffffff>, <&cpu52_intc 9>, ++ <&cpu53_intc 0xffffffff>, <&cpu53_intc 9>, ++ <&cpu54_intc 0xffffffff>, <&cpu54_intc 9>, ++ <&cpu55_intc 0xffffffff>, <&cpu55_intc 9>, ++ <&cpu56_intc 0xffffffff>, <&cpu56_intc 9>, ++ <&cpu57_intc 0xffffffff>, <&cpu57_intc 9>, ++ <&cpu58_intc 0xffffffff>, <&cpu58_intc 9>, ++ <&cpu59_intc 0xffffffff>, <&cpu59_intc 9>, ++ <&cpu60_intc 0xffffffff>, <&cpu60_intc 9>, ++ <&cpu61_intc 0xffffffff>, <&cpu61_intc 9>, ++ <&cpu62_intc 0xffffffff>, <&cpu62_intc 9>, ++ <&cpu63_intc 0xffffffff>, <&cpu63_intc 9>; ++ riscv,ndev = <224>; ++ }; ++ ++ uart0: serial@7040000000 { ++ compatible = "sophgo,sg2042-uart", "snps,dw-apb-uart"; ++ reg = <0x00000070 0x40000000 0x00000000 0x00001000>; ++ interrupt-parent = <&intc>; ++ interrupts = ; ++ clock-frequency = <500000000>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ status = "disabled"; ++ }; ++ }; ++}; +-- +2.20.1 + diff --git a/target/linux/cv18x0/patches-6.1/0007-riscv-dts-sophgo-add-Milk-V-Pioneer-board-device-tre.patch b/target/linux/cv18x0/patches-6.1/0007-riscv-dts-sophgo-add-Milk-V-Pioneer-board-device-tre.patch new file mode 100644 index 0000000000..2f9812d290 --- /dev/null +++ b/target/linux/cv18x0/patches-6.1/0007-riscv-dts-sophgo-add-Milk-V-Pioneer-board-device-tre.patch @@ -0,0 +1,74 @@ +From 0df5090495c33632672f3250f2589b6fbd7b283f Mon Sep 17 00:00:00 2001 +From: Chen Wang +Date: Wed, 20 Sep 2023 14:40:53 +0800 +Subject: [PATCH 7/8] riscv: dts: sophgo: add Milk-V Pioneer board device tree + +Milk-V Pioneer [1] is a developer motherboard based on SOPHON +SG2042 in a standard mATX form factor. It is a good +choice for RISC-V developers and hardware pioneers to +experience the cutting edge technology of RISC-V. + +Currently only support booting into console with only uart +enabled, other features will be added soon later. + +[1]: https://milkv.io/pioneer + +Acked-by: Xiaoguang Xing +Signed-off-by: Chen Wang +Reviewed-by: Guo Ren +--- + arch/riscv/boot/dts/Makefile | 1 + + arch/riscv/boot/dts/sophgo/Makefile | 3 +++ + .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 19 +++++++++++++++++++ + 3 files changed, 23 insertions(+) + create mode 100644 arch/riscv/boot/dts/sophgo/Makefile + create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts + +diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile +index ff174996cdfd..befe9c222235 100644 +--- a/arch/riscv/boot/dts/Makefile ++++ b/arch/riscv/boot/dts/Makefile +@@ -3,5 +3,6 @@ subdir-y += sifive + subdir-y += starfive + subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan + subdir-y += microchip ++subdir-y += sophgo + + obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) +diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile +new file mode 100644 +index 000000000000..5a471b19df22 +--- /dev/null ++++ b/arch/riscv/boot/dts/sophgo/Makefile +@@ -0,0 +1,3 @@ ++# SPDX-License-Identifier: GPL-2.0 ++dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb ++ +diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +new file mode 100644 +index 000000000000..d6e8c0285d1e +--- /dev/null ++++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +@@ -0,0 +1,19 @@ ++// SPDX-License-Identifier: GPL-2.0 OR MIT ++/* ++ * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved. ++ */ ++ ++#include "sg2042.dtsi" ++ ++/ { ++ model = "Milk-V Pioneer"; ++ compatible = "milkv,pioneer", "sophgo,sg2042"; ++ ++ chosen: chosen { ++ stdout-path = "serial0"; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; +-- +2.20.1 + diff --git a/target/linux/cv18x0/patches-6.1/0008-riscv-dts-sophgo-add-Milk-V-Duo-board-device-tree.patch b/target/linux/cv18x0/patches-6.1/0008-riscv-dts-sophgo-add-Milk-V-Duo-board-device-tree.patch new file mode 100644 index 0000000000..856cc7f8be --- /dev/null +++ b/target/linux/cv18x0/patches-6.1/0008-riscv-dts-sophgo-add-Milk-V-Duo-board-device-tree.patch @@ -0,0 +1,74 @@ +From bb5fb03e0606eb192ca2e19426da182c84dac3ed Mon Sep 17 00:00:00 2001 +From: Jisheng Zhang +Date: Sat, 30 Sep 2023 20:39:37 +0800 +Subject: [PATCH 8/8] riscv: dts: sophgo: add Milk-V Duo board device tree + +Milk-V Duo[1] board is an embedded development platform based on the +CV1800B chip. Add minimal device tree files for the development board. + +Support basic uart drivers, so supports booting to a basic shell. + +Link: https://milkv.io/duo [1] +Signed-off-by: Jisheng Zhang +--- + arch/riscv/boot/dts/sophgo/Makefile | 2 +- + .../boot/dts/sophgo/cv1800b-milkv-duo.dts | 38 +++++++++++++++++++ + 2 files changed, 39 insertions(+), 1 deletion(-) + create mode 100644 arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts + +diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile +index 5a471b19df22..5ea9ce398ff6 100644 +--- a/arch/riscv/boot/dts/sophgo/Makefile ++++ b/arch/riscv/boot/dts/sophgo/Makefile +@@ -1,3 +1,3 @@ + # SPDX-License-Identifier: GPL-2.0 + dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb +- ++dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb +diff --git a/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts b/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts +new file mode 100644 +index 000000000000..3af9e34b3bc7 +--- /dev/null ++++ b/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts +@@ -0,0 +1,38 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2023 Jisheng Zhang ++ */ ++ ++/dts-v1/; ++ ++#include "cv1800b.dtsi" ++ ++/ { ++ model = "Milk-V Duo"; ++ compatible = "milkv,duo", "sophgo,cv1800b"; ++ ++ aliases { ++ serial0 = &uart0; ++ serial1 = &uart1; ++ serial2 = &uart2; ++ serial3 = &uart3; ++ serial4 = &uart4; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory@80000000 { ++ device_type = "memory"; ++ reg = <0x80000000 0x3f40000>; ++ }; ++}; ++ ++&osc { ++ clock-frequency = <25000000>; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; +-- +2.20.1 +