From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Mon, 27 Jun 2016 14:51:14 +0000 (+0200)
Subject: clk: renesas: r8a7796: Add watchdog module clock
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=b51d5275016c6edbf4656eaee30d836fef127016;p=openwrt%2Fstaging%2Fblogic.git

clk: renesas: r8a7796: Add watchdog module clock

Add the module clock for the Watchdog Timer (WDT) controller on the
Renesas R-Car M3-W (r8a7796) SoC.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---

diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index ea9ed38943a3..c0dee762ed23 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -104,6 +104,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
 
 static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
 	DEF_MOD("scif2",		 310,	R8A7796_CLK_S3D4),
+	DEF_MOD("rwdt0",		 402,	R8A7796_CLK_R),
 	DEF_MOD("intc-ap",		 408,	R8A7796_CLK_S3D1),
 };