From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Sat, 30 Jul 2016 19:56:26 +0000 (-0700)
Subject: Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git... 
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=b325e04ea21081439f0f3e7fe1117e883a9031d8;p=openwrt%2Fstaging%2Fblogic.git

Merge branch 'x86-cpu-for-linus' of git://git./linux/kernel/git/tip/tip

Pull x86 cpufeature updates from Thomas Gleixner:

 - a workaround for the MONITOR instruction erratum of Goldmont CPUs

 - small fixes and cleanups here and there

* 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/cpu: Add workaround for MONITOR instruction erratum on Goldmont based CPUs
  x86/cpu: Rename "WESTMERE2" family to "NEHALEM_G"
  x86/amd_nb: Clean up init path
  x86/cpufeature: Add helper macro for mask check macros
  x86/cpufeature: Make sure DISABLED/REQUIRED macros are updated
  x86/cpufeature: Update cpufeaure macros
---

b325e04ea21081439f0f3e7fe1117e883a9031d8
diff --cc arch/x86/events/msr.c
index 50b3a056f96b,85ef3c2e80e0..4bb3ec69e8ea
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@@ -35,34 -34,33 +35,34 @@@ static bool test_intel(int idx
  		return false;
  
  	switch (boot_cpu_data.x86_model) {
 -	case 30: /* 45nm Nehalem    */
 -	case 26: /* 45nm Nehalem-EP */
 -	case 46: /* 45nm Nehalem-EX */
 -
 -	case 37: /* 32nm Westmere    */
 -	case 44: /* 32nm Westmere-EP */
 -	case 47: /* 32nm Westmere-EX */
 -
 -	case 42: /* 32nm SandyBridge         */
 -	case 45: /* 32nm SandyBridge-E/EN/EP */
 -
 -	case 58: /* 22nm IvyBridge       */
 -	case 62: /* 22nm IvyBridge-EP/EX */
 -
 -	case 60: /* 22nm Haswell Core */
 -	case 63: /* 22nm Haswell Server */
 -	case 69: /* 22nm Haswell ULT */
 -	case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
 -
 -	case 61: /* 14nm Broadwell Core-M */
 -	case 86: /* 14nm Broadwell Xeon D */
 -	case 71: /* 14nm Broadwell + GT3e (Intel Iris Pro graphics) */
 -	case 79: /* 14nm Broadwell Server */
 -
 -	case 55: /* 22nm Atom "Silvermont"                */
 -	case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
 -	case 76: /* 14nm Atom "Airmont"                   */
 +	case INTEL_FAM6_NEHALEM:
++	case INTEL_FAM6_NEHALEM_G:
 +	case INTEL_FAM6_NEHALEM_EP:
 +	case INTEL_FAM6_NEHALEM_EX:
 +
 +	case INTEL_FAM6_WESTMERE:
- 	case INTEL_FAM6_WESTMERE2:
 +	case INTEL_FAM6_WESTMERE_EP:
 +	case INTEL_FAM6_WESTMERE_EX:
 +
 +	case INTEL_FAM6_SANDYBRIDGE:
 +	case INTEL_FAM6_SANDYBRIDGE_X:
 +
 +	case INTEL_FAM6_IVYBRIDGE:
 +	case INTEL_FAM6_IVYBRIDGE_X:
 +
 +	case INTEL_FAM6_HASWELL_CORE:
 +	case INTEL_FAM6_HASWELL_X:
 +	case INTEL_FAM6_HASWELL_ULT:
 +	case INTEL_FAM6_HASWELL_GT3E:
 +
 +	case INTEL_FAM6_BROADWELL_CORE:
 +	case INTEL_FAM6_BROADWELL_XEON_D:
 +	case INTEL_FAM6_BROADWELL_GT3E:
 +	case INTEL_FAM6_BROADWELL_X:
 +
 +	case INTEL_FAM6_ATOM_SILVERMONT1:
 +	case INTEL_FAM6_ATOM_SILVERMONT2:
 +	case INTEL_FAM6_ATOM_AIRMONT:
  		if (idx == PERF_MSR_SMI)
  			return true;
  		break;
diff --cc arch/x86/include/asm/intel-family.h
index 6999f7d01a0d,2a01701609d5..627719475457
--- a/arch/x86/include/asm/intel-family.h
+++ b/arch/x86/include/asm/intel-family.h
@@@ -8,7 -8,7 +8,7 @@@
   * "Extreme" ones, like Broadwell-E.
   *
   * Things ending in "2" are usually because we have no better
-- * name for them.  There's no processor called "WESTMERE2".
++ * name for them.  There's no processor called "SILVERMONT2".
   */
  
  #define INTEL_FAM6_CORE_YONAH		0x0E