From: Tianling Shen Date: Mon, 18 Dec 2023 03:12:38 +0000 (+0800) Subject: sunxi: mark upstreamed patches as such X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=b16928aa96e0cd340924d3c3013f973f0a253f8e;p=openwrt%2Fstaging%2Fnbd.git sunxi: mark upstreamed patches as such Also sort them to start from 001. Signed-off-by: Tianling Shen --- diff --git a/target/linux/sunxi/patches-6.1/001-v6.2-dt-bindings-usb-Add-H616-compatible-string.patch b/target/linux/sunxi/patches-6.1/001-v6.2-dt-bindings-usb-Add-H616-compatible-string.patch new file mode 100644 index 0000000000..c24d479534 --- /dev/null +++ b/target/linux/sunxi/patches-6.1/001-v6.2-dt-bindings-usb-Add-H616-compatible-string.patch @@ -0,0 +1,38 @@ +From 28a1a6474c5053bae01bd29946b4d5ede539176b Mon Sep 17 00:00:00 2001 +From: Andre Przywara +Date: Mon, 31 Oct 2022 11:13:52 +0000 +Subject: [PATCH] dt-bindings: usb: Add H616 compatible string + +The Allwinner H616 contains four fully OHCI/EHCI compatible USB host +controllers, so just add their compatible strings to the list of +generic OHCI/EHCI controllers. + +Signed-off-by: Andre Przywara +Acked-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20221031111358.3387297-2-andre.przywara@arm.com +Signed-off-by: Jernej Skrabec +--- + Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 + + Documentation/devicetree/bindings/usb/generic-ohci.yaml | 1 + + 2 files changed, 2 insertions(+) + +--- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml ++++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml +@@ -30,6 +30,7 @@ properties: + - allwinner,sun4i-a10-ehci + - allwinner,sun50i-a64-ehci + - allwinner,sun50i-h6-ehci ++ - allwinner,sun50i-h616-ehci + - allwinner,sun5i-a13-ehci + - allwinner,sun6i-a31-ehci + - allwinner,sun7i-a20-ehci +--- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml ++++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml +@@ -20,6 +20,7 @@ properties: + - allwinner,sun4i-a10-ohci + - allwinner,sun50i-a64-ohci + - allwinner,sun50i-h6-ohci ++ - allwinner,sun50i-h616-ohci + - allwinner,sun5i-a13-ohci + - allwinner,sun6i-a31-ohci + - allwinner,sun7i-a20-ohci diff --git a/target/linux/sunxi/patches-6.1/002-v6.2-dt-bindings-phy-Add-special-clock-for-Allwinner-H616-PHY.patch b/target/linux/sunxi/patches-6.1/002-v6.2-dt-bindings-phy-Add-special-clock-for-Allwinner-H616-PHY.patch new file mode 100644 index 0000000000..5739172ceb --- /dev/null +++ b/target/linux/sunxi/patches-6.1/002-v6.2-dt-bindings-phy-Add-special-clock-for-Allwinner-H616-PHY.patch @@ -0,0 +1,79 @@ +From 6964affe65066651eca21e97247d3b7cac5153dc Mon Sep 17 00:00:00 2001 +From: Andre Przywara +Date: Mon, 31 Oct 2022 11:13:53 +0000 +Subject: [PATCH] dt-bindings: phy: Add special clock for Allwinner H616 PHY + +The USB PHY IP in the Allwinner H616 SoC requires a quirk that involves +some resources from port 2's PHY and HCI IP. In particular the PMU clock +for port 2 must be surely ungated before accessing the REG_HCI_PHY_CTL +register of port 2. To allow each USB port to be controlled +independently of port 2, we need a handle to that particular PMU clock +in the *PHY* node, as the HCI and PHY part might be handled by separate +drivers. + +Add that clock to the requirements of the H616 PHY binding, so that a +PHY driver can apply the quirk in isolation, without requiring help from +port 2's HCI driver. + +Signed-off-by: Andre Przywara +Reviewed-by: Rob Herring +Link: https://lore.kernel.org/r/20221031111358.3387297-3-andre.przywara@arm.com +Signed-off-by: Vinod Koul +--- + .../phy/allwinner,sun8i-h3-usb-phy.yaml | 26 +++++++++++++++++++ + 1 file changed, 26 insertions(+) + +--- a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml ++++ b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml +@@ -36,18 +36,22 @@ properties: + - const: pmu3 + + clocks: ++ minItems: 4 + items: + - description: USB OTG PHY bus clock + - description: USB Host 0 PHY bus clock + - description: USB Host 1 PHY bus clock + - description: USB Host 2 PHY bus clock ++ - description: PMU clock for host port 2 + + clock-names: ++ minItems: 4 + items: + - const: usb0_phy + - const: usb1_phy + - const: usb2_phy + - const: usb3_phy ++ - const: pmu2_clk + + resets: + items: +@@ -96,6 +100,28 @@ required: + - resets + - reset-names + ++allOf: ++ - if: ++ properties: ++ compatible: ++ contains: ++ enum: ++ - allwinner,sun50i-h616-usb-phy ++ then: ++ properties: ++ clocks: ++ minItems: 5 ++ ++ clock-names: ++ minItems: 5 ++ else: ++ properties: ++ clocks: ++ maxItems: 4 ++ ++ clock-names: ++ maxItems: 4 ++ + additionalProperties: false + + examples: diff --git a/target/linux/sunxi/patches-6.1/003-v6.2-arm64-dts-allwinner-h616-Add-USB-nodes.patch b/target/linux/sunxi/patches-6.1/003-v6.2-arm64-dts-allwinner-h616-Add-USB-nodes.patch new file mode 100644 index 0000000000..6dc1cf2f36 --- /dev/null +++ b/target/linux/sunxi/patches-6.1/003-v6.2-arm64-dts-allwinner-h616-Add-USB-nodes.patch @@ -0,0 +1,188 @@ +From f40cf244c3feb4e1a442f8029b691add2c65b3ab Mon Sep 17 00:00:00 2001 +From: Andre Przywara +Date: Mon, 31 Oct 2022 11:13:56 +0000 +Subject: [PATCH] arm64: dts: allwinner: h616: Add USB nodes + +Add the nodes for the MUSB and the four USB host controllers to the SoC +.dtsi, along with the PHY node needed to bind all of them together. + +EHCI/OHCI and MUSB are compatible to previous SoCs, but the PHY requires +some quirks (handled in the driver). + +Signed-off-by: Andre Przywara +Reviewed-by: Jernej Skrabec +Link: https://lore.kernel.org/r/20221031111358.3387297-6-andre.przywara@arm.com +Signed-off-by: Jernej Skrabec +--- + .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 160 ++++++++++++++++++ + 1 file changed, 160 insertions(+) + +--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +@@ -504,6 +504,166 @@ + }; + }; + ++ usbotg: usb@5100000 { ++ compatible = "allwinner,sun50i-h616-musb", ++ "allwinner,sun8i-h3-musb"; ++ reg = <0x05100000 0x0400>; ++ clocks = <&ccu CLK_BUS_OTG>; ++ resets = <&ccu RST_BUS_OTG>; ++ interrupts = ; ++ interrupt-names = "mc"; ++ phys = <&usbphy 0>; ++ phy-names = "usb"; ++ extcon = <&usbphy 0>; ++ status = "disabled"; ++ }; ++ ++ usbphy: phy@5100400 { ++ compatible = "allwinner,sun50i-h616-usb-phy"; ++ reg = <0x05100400 0x24>, ++ <0x05101800 0x14>, ++ <0x05200800 0x14>, ++ <0x05310800 0x14>, ++ <0x05311800 0x14>; ++ reg-names = "phy_ctrl", ++ "pmu0", ++ "pmu1", ++ "pmu2", ++ "pmu3"; ++ clocks = <&ccu CLK_USB_PHY0>, ++ <&ccu CLK_USB_PHY1>, ++ <&ccu CLK_USB_PHY2>, ++ <&ccu CLK_USB_PHY3>, ++ <&ccu CLK_BUS_EHCI2>; ++ clock-names = "usb0_phy", ++ "usb1_phy", ++ "usb2_phy", ++ "usb3_phy", ++ "pmu2_clk"; ++ resets = <&ccu RST_USB_PHY0>, ++ <&ccu RST_USB_PHY1>, ++ <&ccu RST_USB_PHY2>, ++ <&ccu RST_USB_PHY3>; ++ reset-names = "usb0_reset", ++ "usb1_reset", ++ "usb2_reset", ++ "usb3_reset"; ++ status = "disabled"; ++ #phy-cells = <1>; ++ }; ++ ++ ehci0: usb@5101000 { ++ compatible = "allwinner,sun50i-h616-ehci", ++ "generic-ehci"; ++ reg = <0x05101000 0x100>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_OHCI0>, ++ <&ccu CLK_BUS_EHCI0>, ++ <&ccu CLK_USB_OHCI0>; ++ resets = <&ccu RST_BUS_OHCI0>, ++ <&ccu RST_BUS_EHCI0>; ++ phys = <&usbphy 0>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ ohci0: usb@5101400 { ++ compatible = "allwinner,sun50i-h616-ohci", ++ "generic-ohci"; ++ reg = <0x05101400 0x100>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_OHCI0>, ++ <&ccu CLK_USB_OHCI0>; ++ resets = <&ccu RST_BUS_OHCI0>; ++ phys = <&usbphy 0>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ ehci1: usb@5200000 { ++ compatible = "allwinner,sun50i-h616-ehci", ++ "generic-ehci"; ++ reg = <0x05200000 0x100>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_OHCI1>, ++ <&ccu CLK_BUS_EHCI1>, ++ <&ccu CLK_USB_OHCI1>; ++ resets = <&ccu RST_BUS_OHCI1>, ++ <&ccu RST_BUS_EHCI1>; ++ phys = <&usbphy 1>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ ohci1: usb@5200400 { ++ compatible = "allwinner,sun50i-h616-ohci", ++ "generic-ohci"; ++ reg = <0x05200400 0x100>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_OHCI1>, ++ <&ccu CLK_USB_OHCI1>; ++ resets = <&ccu RST_BUS_OHCI1>; ++ phys = <&usbphy 1>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ ehci2: usb@5310000 { ++ compatible = "allwinner,sun50i-h616-ehci", ++ "generic-ehci"; ++ reg = <0x05310000 0x100>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_OHCI2>, ++ <&ccu CLK_BUS_EHCI2>, ++ <&ccu CLK_USB_OHCI2>; ++ resets = <&ccu RST_BUS_OHCI2>, ++ <&ccu RST_BUS_EHCI2>; ++ phys = <&usbphy 2>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ ohci2: usb@5310400 { ++ compatible = "allwinner,sun50i-h616-ohci", ++ "generic-ohci"; ++ reg = <0x05310400 0x100>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_OHCI2>, ++ <&ccu CLK_USB_OHCI2>; ++ resets = <&ccu RST_BUS_OHCI2>; ++ phys = <&usbphy 2>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ ehci3: usb@5311000 { ++ compatible = "allwinner,sun50i-h616-ehci", ++ "generic-ehci"; ++ reg = <0x05311000 0x100>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_OHCI3>, ++ <&ccu CLK_BUS_EHCI3>, ++ <&ccu CLK_USB_OHCI3>; ++ resets = <&ccu RST_BUS_OHCI3>, ++ <&ccu RST_BUS_EHCI3>; ++ phys = <&usbphy 3>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ ohci3: usb@5311400 { ++ compatible = "allwinner,sun50i-h616-ohci", ++ "generic-ohci"; ++ reg = <0x05311400 0x100>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_OHCI3>, ++ <&ccu CLK_USB_OHCI3>; ++ resets = <&ccu RST_BUS_OHCI3>; ++ phys = <&usbphy 3>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ + rtc: rtc@7000000 { + compatible = "allwinner,sun50i-h616-rtc"; + reg = <0x07000000 0x400>; diff --git a/target/linux/sunxi/patches-6.1/004-v6.2-arm64-dts-allwinner-h616-OrangePi-Zero-2-Add-USB-nodes.patch b/target/linux/sunxi/patches-6.1/004-v6.2-arm64-dts-allwinner-h616-OrangePi-Zero-2-Add-USB-nodes.patch new file mode 100644 index 0000000000..a544e482f3 --- /dev/null +++ b/target/linux/sunxi/patches-6.1/004-v6.2-arm64-dts-allwinner-h616-OrangePi-Zero-2-Add-USB-nodes.patch @@ -0,0 +1,81 @@ +From db5f028309ede13767e2ba356c1975ac37a4fd6c Mon Sep 17 00:00:00 2001 +From: Andre Przywara +Date: Mon, 31 Oct 2022 11:13:57 +0000 +Subject: [PATCH] arm64: dts: allwinner: h616: OrangePi Zero 2: Add USB nodes + +The OrangePi Zero 2 has one USB-A host port, VBUS is provided by +a GPIO controlled regulator. +The USB-C port is meant to power the board, but is also connected to +the USB 0 port, which we configure as an MUSB peripheral. + +Signed-off-by: Andre Przywara +Reviewed-by: Jernej Skrabec +Link: https://lore.kernel.org/r/20221031111358.3387297-7-andre.przywara@arm.com +Signed-off-by: Jernej Skrabec +--- + .../allwinner/sun50i-h616-orangepi-zero2.dts | 41 +++++++++++++++++++ + 1 file changed, 41 insertions(+) + +--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts +@@ -49,8 +49,24 @@ + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; ++ ++ reg_usb1_vbus: regulator-usb1-vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb1-vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <®_vcc5v>; ++ enable-active-high; ++ gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */ ++ }; ++}; ++ ++&ehci1 { ++ status = "okay"; + }; + ++/* USB 2 & 3 are on headers only. */ ++ + &emac0 { + pinctrl-names = "default"; + pinctrl-0 = <&ext_rgmii_pins>; +@@ -76,6 +92,10 @@ + status = "okay"; + }; + ++&ohci1 { ++ status = "okay"; ++}; ++ + &r_rsb { + status = "okay"; + +@@ -211,3 +231,24 @@ + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; + }; ++ ++&usbotg { ++ /* ++ * PHY0 pins are connected to a USB-C socket, but a role switch ++ * is not implemented: both CC pins are pulled to GND. ++ * The VBUS pins power the device, so a fixed peripheral mode ++ * is the best choice. ++ * The board can be powered via GPIOs, in this case port0 *can* ++ * act as a host (with a cable/adapter ignoring CC), as VBUS is ++ * then provided by the GPIOs. Any user of this setup would ++ * need to adjust the DT accordingly: dr_mode set to "host", ++ * enabling OHCI0 and EHCI0. ++ */ ++ dr_mode = "peripheral"; ++ status = "okay"; ++}; ++ ++&usbphy { ++ usb1_vbus-supply = <®_usb1_vbus>; ++ status = "okay"; ++}; diff --git a/target/linux/sunxi/patches-6.1/460-dt-bindings-usb-Add-H616-compatible-string.patch b/target/linux/sunxi/patches-6.1/460-dt-bindings-usb-Add-H616-compatible-string.patch deleted file mode 100644 index bab535705c..0000000000 --- a/target/linux/sunxi/patches-6.1/460-dt-bindings-usb-Add-H616-compatible-string.patch +++ /dev/null @@ -1,36 +0,0 @@ -From e4045c8125d88a9eb8b4f8f74b5c7955d5d9adc0 Mon Sep 17 00:00:00 2001 -From: Andre Przywara -Date: Thu, 17 Jun 2021 10:54:22 +0100 -Subject: [PATCH 5000/5006] dt-bindings: usb: Add H616 compatible string - -The Allwinner H616 contains four fully OHCI/EHCI compatible USB host -controllers, so just add their compatible strings to the list of -generic OHCI/EHCI controllers. - -Signed-off-by: Andre Przywara -Acked-by: Krzysztof Kozlowski ---- - Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 + - Documentation/devicetree/bindings/usb/generic-ohci.yaml | 1 + - 2 files changed, 2 insertions(+) - ---- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml -+++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml -@@ -30,6 +30,7 @@ properties: - - allwinner,sun4i-a10-ehci - - allwinner,sun50i-a64-ehci - - allwinner,sun50i-h6-ehci -+ - allwinner,sun50i-h616-ehci - - allwinner,sun5i-a13-ehci - - allwinner,sun6i-a31-ehci - - allwinner,sun7i-a20-ehci ---- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml -+++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml -@@ -20,6 +20,7 @@ properties: - - allwinner,sun4i-a10-ohci - - allwinner,sun50i-a64-ohci - - allwinner,sun50i-h6-ohci -+ - allwinner,sun50i-h616-ohci - - allwinner,sun5i-a13-ohci - - allwinner,sun6i-a31-ohci - - allwinner,sun7i-a20-ohci diff --git a/target/linux/sunxi/patches-6.1/461-dt-bindings-phy-Add-special-clock-for-Allwinner-H616.patch b/target/linux/sunxi/patches-6.1/461-dt-bindings-phy-Add-special-clock-for-Allwinner-H616.patch deleted file mode 100644 index 238683b3c5..0000000000 --- a/target/linux/sunxi/patches-6.1/461-dt-bindings-phy-Add-special-clock-for-Allwinner-H616.patch +++ /dev/null @@ -1,77 +0,0 @@ -From e2078ae0c559b6ac91db19262b56d8cf334354cb Mon Sep 17 00:00:00 2001 -From: Andre Przywara -Date: Mon, 12 Sep 2022 00:03:22 +0100 -Subject: [PATCH 5001/5006] dt-bindings: phy: Add special clock for Allwinner - H616 PHY - -The USB PHY IP in the Allwinner H616 SoC requires a quirk that involves -some resources from port 2's PHY and HCI IP. In particular the PMU clock -for port 2 must be surely ungated before accessing the REG_HCI_PHY_CTL -register of port 2. To allow each USB port to be controlled -independently of port 2, we need a handle to that particular PMU clock -in the *PHY* node, as the HCI and PHY part might be handled by separate -drivers. - -Add that clock to the requirements of the H616 PHY binding, so that a -PHY driver can apply the quirk in isolation, without requiring help from -port 2's HCI driver. - -Signed-off-by: Andre Przywara ---- - .../phy/allwinner,sun8i-h3-usb-phy.yaml | 26 +++++++++++++++++++ - 1 file changed, 26 insertions(+) - ---- a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml -+++ b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml -@@ -36,18 +36,22 @@ properties: - - const: pmu3 - - clocks: -+ minItems: 4 - items: - - description: USB OTG PHY bus clock - - description: USB Host 0 PHY bus clock - - description: USB Host 1 PHY bus clock - - description: USB Host 2 PHY bus clock -+ - description: PMU clock for host port 2 - - clock-names: -+ minItems: 4 - items: - - const: usb0_phy - - const: usb1_phy - - const: usb2_phy - - const: usb3_phy -+ - const: pmu2_clk - - resets: - items: -@@ -96,6 +100,28 @@ required: - - resets - - reset-names - -+allOf: -+ - if: -+ properties: -+ compatible: -+ contains: -+ enum: -+ - allwinner,sun50i-h616-usb-phy -+ then: -+ properties: -+ clocks: -+ minItems: 5 -+ -+ clock-names: -+ minItems: 5 -+ else: -+ properties: -+ clocks: -+ maxItems: 4 -+ -+ clock-names: -+ maxItems: 4 -+ - additionalProperties: false - - examples: diff --git a/target/linux/sunxi/patches-6.1/462-arm64-dts-allwinner-h616-Add-USB-nodes.patch b/target/linux/sunxi/patches-6.1/462-arm64-dts-allwinner-h616-Add-USB-nodes.patch deleted file mode 100644 index 9a31bea8bf..0000000000 --- a/target/linux/sunxi/patches-6.1/462-arm64-dts-allwinner-h616-Add-USB-nodes.patch +++ /dev/null @@ -1,185 +0,0 @@ -From 4cfd9d9350a57fc3ced240dbf61ca2f444283c50 Mon Sep 17 00:00:00 2001 -From: Andre Przywara -Date: Wed, 16 Jun 2021 18:20:47 +0100 -Subject: [PATCH 5004/5006] arm64: dts: allwinner: h616: Add USB nodes - -Add the nodes for the MUSB and the four USB host controllers to the SoC -.dtsi, along with the PHY node needed to bind all of them together. - -EHCI/OHCI and MUSB are compatible to previous SoCs, but the PHY requires -some quirks (handled in the driver). - -Signed-off-by: Andre Przywara ---- - .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 160 ++++++++++++++++++ - 1 file changed, 160 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -@@ -504,6 +504,166 @@ - }; - }; - -+ usbotg: usb@5100000 { -+ compatible = "allwinner,sun50i-h616-musb", -+ "allwinner,sun8i-h3-musb"; -+ reg = <0x05100000 0x0400>; -+ clocks = <&ccu CLK_BUS_OTG>; -+ resets = <&ccu RST_BUS_OTG>; -+ interrupts = ; -+ interrupt-names = "mc"; -+ phys = <&usbphy 0>; -+ phy-names = "usb"; -+ extcon = <&usbphy 0>; -+ status = "disabled"; -+ }; -+ -+ usbphy: phy@5100400 { -+ compatible = "allwinner,sun50i-h616-usb-phy"; -+ reg = <0x05100400 0x24>, -+ <0x05101800 0x14>, -+ <0x05200800 0x14>, -+ <0x05310800 0x14>, -+ <0x05311800 0x14>; -+ reg-names = "phy_ctrl", -+ "pmu0", -+ "pmu1", -+ "pmu2", -+ "pmu3"; -+ clocks = <&ccu CLK_USB_PHY0>, -+ <&ccu CLK_USB_PHY1>, -+ <&ccu CLK_USB_PHY2>, -+ <&ccu CLK_USB_PHY3>, -+ <&ccu CLK_BUS_EHCI2>; -+ clock-names = "usb0_phy", -+ "usb1_phy", -+ "usb2_phy", -+ "usb3_phy", -+ "pmu2_clk"; -+ resets = <&ccu RST_USB_PHY0>, -+ <&ccu RST_USB_PHY1>, -+ <&ccu RST_USB_PHY2>, -+ <&ccu RST_USB_PHY3>; -+ reset-names = "usb0_reset", -+ "usb1_reset", -+ "usb2_reset", -+ "usb3_reset"; -+ status = "disabled"; -+ #phy-cells = <1>; -+ }; -+ -+ ehci0: usb@5101000 { -+ compatible = "allwinner,sun50i-h616-ehci", -+ "generic-ehci"; -+ reg = <0x05101000 0x100>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_OHCI0>, -+ <&ccu CLK_BUS_EHCI0>, -+ <&ccu CLK_USB_OHCI0>; -+ resets = <&ccu RST_BUS_OHCI0>, -+ <&ccu RST_BUS_EHCI0>; -+ phys = <&usbphy 0>; -+ phy-names = "usb"; -+ status = "disabled"; -+ }; -+ -+ ohci0: usb@5101400 { -+ compatible = "allwinner,sun50i-h616-ohci", -+ "generic-ohci"; -+ reg = <0x05101400 0x100>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_OHCI0>, -+ <&ccu CLK_USB_OHCI0>; -+ resets = <&ccu RST_BUS_OHCI0>; -+ phys = <&usbphy 0>; -+ phy-names = "usb"; -+ status = "disabled"; -+ }; -+ -+ ehci1: usb@5200000 { -+ compatible = "allwinner,sun50i-h616-ehci", -+ "generic-ehci"; -+ reg = <0x05200000 0x100>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_OHCI1>, -+ <&ccu CLK_BUS_EHCI1>, -+ <&ccu CLK_USB_OHCI1>; -+ resets = <&ccu RST_BUS_OHCI1>, -+ <&ccu RST_BUS_EHCI1>; -+ phys = <&usbphy 1>; -+ phy-names = "usb"; -+ status = "disabled"; -+ }; -+ -+ ohci1: usb@5200400 { -+ compatible = "allwinner,sun50i-h616-ohci", -+ "generic-ohci"; -+ reg = <0x05200400 0x100>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_OHCI1>, -+ <&ccu CLK_USB_OHCI1>; -+ resets = <&ccu RST_BUS_OHCI1>; -+ phys = <&usbphy 1>; -+ phy-names = "usb"; -+ status = "disabled"; -+ }; -+ -+ ehci2: usb@5310000 { -+ compatible = "allwinner,sun50i-h616-ehci", -+ "generic-ehci"; -+ reg = <0x05310000 0x100>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_OHCI2>, -+ <&ccu CLK_BUS_EHCI2>, -+ <&ccu CLK_USB_OHCI2>; -+ resets = <&ccu RST_BUS_OHCI2>, -+ <&ccu RST_BUS_EHCI2>; -+ phys = <&usbphy 2>; -+ phy-names = "usb"; -+ status = "disabled"; -+ }; -+ -+ ohci2: usb@5310400 { -+ compatible = "allwinner,sun50i-h616-ohci", -+ "generic-ohci"; -+ reg = <0x05310400 0x100>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_OHCI2>, -+ <&ccu CLK_USB_OHCI2>; -+ resets = <&ccu RST_BUS_OHCI2>; -+ phys = <&usbphy 2>; -+ phy-names = "usb"; -+ status = "disabled"; -+ }; -+ -+ ehci3: usb@5311000 { -+ compatible = "allwinner,sun50i-h616-ehci", -+ "generic-ehci"; -+ reg = <0x05311000 0x100>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_OHCI3>, -+ <&ccu CLK_BUS_EHCI3>, -+ <&ccu CLK_USB_OHCI3>; -+ resets = <&ccu RST_BUS_OHCI3>, -+ <&ccu RST_BUS_EHCI3>; -+ phys = <&usbphy 3>; -+ phy-names = "usb"; -+ status = "disabled"; -+ }; -+ -+ ohci3: usb@5311400 { -+ compatible = "allwinner,sun50i-h616-ohci", -+ "generic-ohci"; -+ reg = <0x05311400 0x100>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_OHCI3>, -+ <&ccu CLK_USB_OHCI3>; -+ resets = <&ccu RST_BUS_OHCI3>; -+ phys = <&usbphy 3>; -+ phy-names = "usb"; -+ status = "disabled"; -+ }; -+ - rtc: rtc@7000000 { - compatible = "allwinner,sun50i-h616-rtc"; - reg = <0x07000000 0x400>; diff --git a/target/linux/sunxi/patches-6.1/463-arm64-dts-allwinner-h616-OrangePi-Zero-2-Add-USB-nod.patch b/target/linux/sunxi/patches-6.1/463-arm64-dts-allwinner-h616-OrangePi-Zero-2-Add-USB-nod.patch deleted file mode 100644 index 9ae5591cca..0000000000 --- a/target/linux/sunxi/patches-6.1/463-arm64-dts-allwinner-h616-OrangePi-Zero-2-Add-USB-nod.patch +++ /dev/null @@ -1,79 +0,0 @@ -From 1bc12a9ae690a22a525f9b71778022bb4533fec1 Mon Sep 17 00:00:00 2001 -From: Andre Przywara -Date: Wed, 16 Jun 2021 18:32:36 +0100 -Subject: [PATCH 5005/5006] arm64: dts: allwinner: h616: OrangePi Zero 2: Add - USB nodes - -The OrangePi Zero 2 has one USB-A host port, VBUS is provided by -a GPIO controlled regulator. -The USB-C port is meant to power the board, but is also connected to -the USB 0 port, which we configure as an MUSB peripheral. - -Signed-off-by: Andre Przywara ---- - .../allwinner/sun50i-h616-orangepi-zero2.dts | 41 +++++++++++++++++++ - 1 file changed, 41 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts -@@ -49,8 +49,24 @@ - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -+ -+ reg_usb1_vbus: regulator-usb1-vbus { -+ compatible = "regulator-fixed"; -+ regulator-name = "usb1-vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <®_vcc5v>; -+ enable-active-high; -+ gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */ -+ }; -+}; -+ -+&ehci1 { -+ status = "okay"; - }; - -+/* USB 2 & 3 are on headers only. */ -+ - &emac0 { - pinctrl-names = "default"; - pinctrl-0 = <&ext_rgmii_pins>; -@@ -76,6 +92,10 @@ - status = "okay"; - }; - -+&ohci1 { -+ status = "okay"; -+}; -+ - &r_rsb { - status = "okay"; - -@@ -211,3 +231,24 @@ - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; - }; -+ -+&usbotg { -+ /* -+ * PHY0 pins are connected to a USB-C socket, but a role switch -+ * is not implemented: both CC pins are pulled to GND. -+ * The VBUS pins power the device, so a fixed peripheral mode -+ * is the best choice. -+ * The board can be powered via GPIOs, in this case port0 *can* -+ * act as a host (with a cable/adapter ignoring CC), as VBUS is -+ * then provided by the GPIOs. Any user of this setup would -+ * need to adjust the DT accordingly: dr_mode set to "host", -+ * enabling OHCI0 and EHCI0. -+ */ -+ dr_mode = "peripheral"; -+ status = "okay"; -+}; -+ -+&usbphy { -+ usb1_vbus-supply = <®_usb1_vbus>; -+ status = "okay"; -+};