From: Hauke Mehrtens Date: Sat, 15 Aug 2020 17:34:00 +0000 (+0200) Subject: kernel: Add GigaDevice GD5F4GQ4xC SPI NAND flash X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=aefa9d39c3f6caea2d464100686496120568e10a;p=openwrt%2Fstaging%2Flinusw.git kernel: Add GigaDevice GD5F4GQ4xC SPI NAND flash This flash was found on the Imagination Technologies Creator Ci40 (Marduk). Signed-off-by: Hauke Mehrtens --- diff --git a/target/linux/generic/pending-5.4/445-mtd-spinand-gigadevice-Only-one-dummy-byte-in-QUA.patch b/target/linux/generic/pending-5.4/445-mtd-spinand-gigadevice-Only-one-dummy-byte-in-QUA.patch new file mode 100644 index 0000000000..0391094d27 --- /dev/null +++ b/target/linux/generic/pending-5.4/445-mtd-spinand-gigadevice-Only-one-dummy-byte-in-QUA.patch @@ -0,0 +1,39 @@ +From 5f312dcb38b8003d9711290366cd4b1def5daf3b Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Sun, 16 Aug 2020 14:43:35 +0200 +Subject: [PATCH v2 445/447] mtd: spinand: gigadevice: Only one dummy byte in + QUADIO + +The datasheet only lists one dummy byte in the 0xEH operation for the +following chips: +* GD5F1GQ4xExxG +* GD5F1GQ4xFxxG +* GD5F1GQ4UAYIG +* GD5F4GQ4UAYIG + +Fixes: c93c613214ac ("mtd: spinand: add support for GigaDevice GD5FxGQ4xA") +Signed-off-by: Hauke Mehrtens +--- + drivers/mtd/nand/spi/gigadevice.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/mtd/nand/spi/gigadevice.c ++++ b/drivers/mtd/nand/spi/gigadevice.c +@@ -21,7 +21,7 @@ + #define GD5FXGQ4UXFXXG_STATUS_ECC_UNCOR_ERROR (7 << 4) + + static SPINAND_OP_VARIANTS(read_cache_variants, +- SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), +@@ -29,7 +29,7 @@ static SPINAND_OP_VARIANTS(read_cache_va + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); + + static SPINAND_OP_VARIANTS(read_cache_variants_f, +- SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(0, 1, NULL, 0), diff --git a/target/linux/generic/pending-5.4/446-mtd-spinand-gigadevice-Add-QE-Bit.patch b/target/linux/generic/pending-5.4/446-mtd-spinand-gigadevice-Add-QE-Bit.patch new file mode 100644 index 0000000000..034cd2a8f0 --- /dev/null +++ b/target/linux/generic/pending-5.4/446-mtd-spinand-gigadevice-Add-QE-Bit.patch @@ -0,0 +1,67 @@ +From f72e99ada020a81e3e4ef79c0a83ede7e9d6c7b1 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Sun, 16 Aug 2020 14:42:17 +0200 +Subject: [PATCH v2 446/447] mtd: spinand: gigadevice: Add QE Bit + +The following GigaDevice chips have the QE BIT in the feature flags, I +checked the datasheets, but did not try this. +* GD5F1GQ4xExxG +* GD5F1GQ4xFxxG +* GD5F1GQ4UAYIG +* GD5F4GQ4UAYIG + +The Quad operations like 0xEB mention that the QE bit has to be set. + +Fixes: c93c613214ac ("mtd: spinand: add support for GigaDevice GD5FxGQ4xA") +Signed-off-by: Hauke Mehrtens +--- + drivers/mtd/nand/spi/gigadevice.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +--- a/drivers/mtd/nand/spi/gigadevice.c ++++ b/drivers/mtd/nand/spi/gigadevice.c +@@ -201,7 +201,7 @@ static const struct spinand_info gigadev + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), +- 0, ++ SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, + gd5fxgq4xa_ecc_get_status)), + SPINAND_INFO("GD5F2GQ4xA", 0xF2, +@@ -210,7 +210,7 @@ static const struct spinand_info gigadev + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), +- 0, ++ SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, + gd5fxgq4xa_ecc_get_status)), + SPINAND_INFO("GD5F4GQ4xA", 0xF4, +@@ -219,7 +219,7 @@ static const struct spinand_info gigadev + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), +- 0, ++ SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, + gd5fxgq4xa_ecc_get_status)), + SPINAND_INFO("GD5F1GQ4UExxG", 0xd1, +@@ -228,7 +228,7 @@ static const struct spinand_info gigadev + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), +- 0, ++ SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout, + gd5fxgq4uexxg_ecc_get_status)), + SPINAND_INFO("GD5F1GQ4UFxxG", 0xb148, +@@ -237,7 +237,7 @@ static const struct spinand_info gigadev + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f, + &write_cache_variants, + &update_cache_variants), +- 0, ++ SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout, + gd5fxgq4ufxxg_ecc_get_status)), + }; diff --git a/target/linux/generic/pending-5.4/447-mtd-spinand-gigadevice-Add-support-for-GD5F4GQ4xC.patch b/target/linux/generic/pending-5.4/447-mtd-spinand-gigadevice-Add-support-for-GD5F4GQ4xC.patch new file mode 100644 index 0000000000..e1fcb15d5a --- /dev/null +++ b/target/linux/generic/pending-5.4/447-mtd-spinand-gigadevice-Add-support-for-GD5F4GQ4xC.patch @@ -0,0 +1,87 @@ +From 30521ccfb4597f91b9e5c7967acef9c7c85e58a8 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Wed, 12 Aug 2020 22:50:26 +0200 +Subject: [PATCH v2 447/447] mtd: spinand: gigadevice: Add support for + GD5F4GQ4xC + +This adds support for the following 4GiB chips: +GD5F4GQ4RCYIG 1.8V +GD5F4GQ4UCYIG 3.3V + +The datasheet can be found here: +https://www.novitronic.ch/sixcms/media.php/2/DS-00173-GD5F4GQ4xCxIG-Rev1.574695.pdf + +The GD5F4GQ4UCYIGT (3.3V) version is used on the Imagination +Technologies Creator Ci40 (Marduk), the 1.8V version was not tested. + +This device only works in single SPI mode and not in dual or quad mode +for me on this board. + +Signed-off-by: Hauke Mehrtens +--- + drivers/mtd/nand/spi/gigadevice.c | 49 +++++++++++++++++++++++++++++++ + 1 file changed, 49 insertions(+) + +--- a/drivers/mtd/nand/spi/gigadevice.c ++++ b/drivers/mtd/nand/spi/gigadevice.c +@@ -132,6 +132,35 @@ static const struct mtd_ooblayout_ops gd + .free = gd5fxgq4_variant2_ooblayout_free, + }; + ++static int gd5fxgq4xc_ooblayout_256_ecc(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *oobregion) ++{ ++ if (section) ++ return -ERANGE; ++ ++ oobregion->offset = 128; ++ oobregion->length = 128; ++ ++ return 0; ++} ++ ++static int gd5fxgq4xc_ooblayout_256_free(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *oobregion) ++{ ++ if (section) ++ return -ERANGE; ++ ++ oobregion->offset = 1; ++ oobregion->length = 127; ++ ++ return 0; ++} ++ ++static const struct mtd_ooblayout_ops gd5fxgq4xc_oob_256_ops = { ++ .ecc = gd5fxgq4xc_ooblayout_256_ecc, ++ .free = gd5fxgq4xc_ooblayout_256_free, ++}; ++ + static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand, + u8 status) + { +@@ -222,6 +251,24 @@ static const struct spinand_info gigadev + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, + gd5fxgq4xa_ecc_get_status)), ++ SPINAND_INFO("GD5F4GQ4RC", 0xa468, ++ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&gd5fxgq4xc_oob_256_ops, ++ gd5fxgq4ufxxg_ecc_get_status)), ++ SPINAND_INFO("GD5F4GQ4UC", 0xb468, ++ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&gd5fxgq4xc_oob_256_ops, ++ gd5fxgq4ufxxg_ecc_get_status)), + SPINAND_INFO("GD5F1GQ4UExxG", 0xd1, + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512),