From: Rafał Miłecki <rafal@milecki.pl>
Date: Tue, 20 Feb 2024 11:00:34 +0000 (+0100)
Subject: mediatek: filogic: fix mt7981 DT nodenames
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=ae036c26fd4365b55ac4037e443650094c03aa02;p=openwrt%2Fstaging%2Fthess.git

mediatek: filogic: fix mt7981 DT nodenames

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
---

diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi
index ba832ea2aa..54cfd0b4b9 100644
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi
+++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi
@@ -47,7 +47,7 @@
 		clock-names = "ice_dbg";
 	};
 
-	clk40m: oscillator@0 {
+	clk40m: oscillator-40m {
 		compatible = "fixed-clock";
 		clock-frequency = <40000000>;
 		clock-output-names = "clkxtal";
@@ -132,7 +132,7 @@
 			memory-region = <&wmcpu_emi>;
 		};
 
-		infracfg: infracfg@10001000 {
+		infracfg: clock-controller@10001000 {
 			compatible = "mediatek,mt7981-infracfg", "syscon";
 			reg = <0 0x10001000 0 0x1000>;
 			#clock-cells = <1>;
@@ -143,7 +143,7 @@
 			reg = <0 0x10003000 0 0x10>;
 		};
 
-		topckgen: topckgen@1001b000 {
+		topckgen: clock-controller@1001b000 {
 			compatible = "mediatek,mt7981-topckgen", "syscon";
 			reg = <0 0x1001b000 0 0x1000>;
 			#clock-cells = <1>;
@@ -158,7 +158,7 @@
 			status = "disabled";
 		};
 
-		apmixedsys: apmixedsys@1001e000 {
+		apmixedsys: clock-controller@1001e000 {
 			compatible = "mediatek,mt7981-apmixedsys", "syscon";
 			reg = <0 0x1001e000 0 0x1000>;
 			#clock-cells = <1>;
@@ -577,7 +577,7 @@
 			};
 		};
 
-		ethsys: syscon@15000000 {
+		ethsys: clock-controller@15000000 {
 			compatible = "mediatek,mt7981-ethsys",
 				     "syscon";
 			reg = <0 0x15000000 0 0x1000>;