From: Dave Airlie <airlied@redhat.com>
Date: Fri, 9 Jan 2015 22:46:24 +0000 (+1000)
Subject: Merge tag 'drm-intel-next-2014-12-19' of git://anongit.freedesktop.org/drm-intel... 
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=adc31849b27fefeca6c225d3895143a2ec6970fa;p=openwrt%2Fstaging%2Fblogic.git

Merge tag 'drm-intel-next-2014-12-19' of git://anongit.freedesktop.org/drm-intel into drm-next

- plane handling refactoring from Matt Roper and Gustavo Padovan in prep for
  atomic updates
- fixes and more patches for the seqno to request transformation from John
- docbook for fbc from Rodrigo
- prep work for dual-link dsi from Gaurav Signh
- crc fixes from Ville
- special ggtt views infrastructure from Tvrtko Ursulin
- shadow patch copying for the cmd parser from Brad Volkin
- execlist and full ppgtt by default on gen8, for testing for now

* tag 'drm-intel-next-2014-12-19' of git://anongit.freedesktop.org/drm-intel: (131 commits)
  drm/i915: Update DRIVER_DATE to 20141219
  drm/i915: Hold runtime PM during plane commit
  drm/i915: Organize bind_vma funcs
  drm/i915: Organize INSTDONE report for future.
  drm/i915: Organize PDP regs report for future.
  drm/i915: Organize PPGTT init
  drm/i915: Organize Fence registers for future enablement.
  drm/i915: tame the chattermouth (v2)
  drm/i915: Warn about missing context state workarounds only once
  drm/i915: Use true PPGTT in Gen8+ when execlists are enabled
  drm/i915: Skip gunit save/restore for cherryview
  drm/i915/chv: Use timeout mode for RC6 on chv
  drm/i915: Add GPGPU_THREADS_DISPATCHED to the register whitelist
  drm/i915: Tidy up execbuffer command parsing code
  drm/i915: Mark shadow batch buffers as purgeable
  drm/i915: Use batch length instead of object size in command parser
  drm/i915: Use batch pools with the command parser
  drm/i915: Implement a framework for batch buffer pools
  drm/i915: fix use after free during eDP encoder destroying
  drm/i915/skl: Skylake also supports DP MST
  ...
---

adc31849b27fefeca6c225d3895143a2ec6970fa
diff --cc drivers/gpu/drm/i915/i915_gem.c
index 52adcb680be3,f678017c4d31..3044fb324c8e
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@@ -1222,11 -1223,10 +1221,11 @@@ int __i915_wait_request(struct drm_i915
  
  	WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
  
- 	if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
+ 	if (i915_gem_request_completed(req, true))
  		return 0;
  
 -	timeout_expire = timeout ? jiffies + nsecs_to_jiffies((u64)*timeout) : 0;
 +	timeout_expire = timeout ?
 +		jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0;
  
  	if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) {
  		gen6_rps_boost(dev_priv);
diff --cc drivers/gpu/drm/i915/i915_reg.h
index 172de3b3433b,1fdda4249bb1..40ca873a05ad
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@@ -31,20 -31,11 +31,22 @@@
  #define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
  #define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \
  			       (pipe) == PIPE_B ? (b) : (c))
+ #define _PORT3(port, a, b, c) ((port) == PORT_A ? (a) : \
+ 			       (port) == PORT_B ? (b) : (c))
  
 -#define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
 -#define _MASKED_BIT_DISABLE(a) ((a) << 16)
 +#define _MASKED_FIELD(mask, value) ({					   \
 +	if (__builtin_constant_p(mask))					   \
 +		BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
 +	if (__builtin_constant_p(value))				   \
 +		BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
 +	if (__builtin_constant_p(mask) && __builtin_constant_p(value))	   \
 +		BUILD_BUG_ON_MSG((value) & ~(mask),			   \
 +				 "Incorrect value for mask");		   \
 +	(mask) << 16 | (value); })
 +#define _MASKED_BIT_ENABLE(a)	({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
 +#define _MASKED_BIT_DISABLE(a)	(_MASKED_FIELD((a), 0))
 +
 +
  
  /* PCI config space */
  
diff --cc drivers/gpu/drm/i915/intel_ringbuffer.c
index c7bc93d28d84,3cad32a80108..12a36f0ca53d
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@@ -703,8 -710,24 +713,24 @@@ static int intel_ring_workarounds_emit(
  	return 0;
  }
  
+ static int intel_rcs_ctx_init(struct intel_engine_cs *ring,
+ 			      struct intel_context *ctx)
+ {
+ 	int ret;
+ 
+ 	ret = intel_ring_workarounds_emit(ring, ctx);
+ 	if (ret != 0)
+ 		return ret;
+ 
+ 	ret = i915_gem_render_state_init(ring);
+ 	if (ret)
+ 		DRM_ERROR("init render state: %d\n", ret);
+ 
+ 	return ret;
+ }
+ 
  static int wa_add(struct drm_i915_private *dev_priv,
 -		  const u32 addr, const u32 val, const u32 mask)
 +		  const u32 addr, const u32 mask, const u32 val)
  {
  	const u32 idx = dev_priv->workarounds.count;