From: Anatol Pomozov <anatol.pomozov@gmail.com>
Date: Wed, 5 Aug 2015 21:58:33 +0000 (-0700)
Subject: ASoC: rl6231: Simplify DMIC divider calculation expression
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=ac1125daf02b81cabb19f35963906335e3d4a155;p=openwrt%2Fstaging%2Fblogic.git

ASoC: rl6231: Simplify DMIC divider calculation expression

Existing implementation checks all divider values and tracks
'red' proximity value for the frequency.

But as divider array is monotonically increasing the first
divider that gives DMIC rate in 3MHz range is the best one
we should use. No need for 'red' zone tracking.

Additionally make sure that DMIC frequency is higher 1MHz.

Signed-off-by: Anatol Pomozov <anatol.pomozov@gmail.com>
Acked-by: Oder Chiou <oder_chiou@realtek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---

diff --git a/sound/soc/codecs/rl6231.c b/sound/soc/codecs/rl6231.c
index 57e51c16e021..aca479fa7670 100644
--- a/sound/soc/codecs/rl6231.c
+++ b/sound/soc/codecs/rl6231.c
@@ -62,31 +62,31 @@ int rl6231_get_pre_div(struct regmap *map, unsigned int reg, int sft)
 EXPORT_SYMBOL_GPL(rl6231_get_pre_div);
 
 /**
- * rl6231_calc_dmic_clk - Calculate the parameter of dmic.
+ * rl6231_calc_dmic_clk - Calculate the frequency divider parameter of dmic.
  *
  * @rate: base clock rate.
  *
- * Choose dmic clock between 1MHz and 3MHz.
- * It is better for clock to approximate 3MHz.
+ * Choose divider parameter that gives the highest possible DMIC frequency in
+ * 1MHz - 3MHz range.
  */
 int rl6231_calc_dmic_clk(int rate)
 {
-	int div[] = {2, 3, 4, 6, 8, 12}, idx = -EINVAL;
-	int i, red, bound, temp;
+	int div[] = {2, 3, 4, 6, 8, 12};
+	int i;
+
+	if (rate < 1000000 * div[0]) {
+		pr_warn("Base clock rate %d is too low\n", rate);
+		return -EINVAL;
+	}
 
-	red = 3000000 * 12;
 	for (i = 0; i < ARRAY_SIZE(div); i++) {
-		bound = div[i] * 3000000;
-		if (rate > bound)
-			continue;
-		temp = bound - rate;
-		if (temp < red) {
-			red = temp;
-			idx = i;
-		}
+		/* find divider that gives DMIC frequency below 3MHz */
+		if (3000000 * div[i] >= rate)
+			return i;
 	}
 
-	return idx;
+	pr_warn("Base clock rate %d is too high\n", rate);
+	return -EINVAL;
 }
 EXPORT_SYMBOL_GPL(rl6231_calc_dmic_clk);