From: NeilBrown Date: Wed, 6 Jun 2018 22:04:21 +0000 (+1000) Subject: staging: mt7621-spi: change mt7621_spi_wait_till_ready to take struct mt7621_spi X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=a83834c1c9ba446f694c0bc29bce25687bf06582;p=openwrt%2Fstaging%2Fblogic.git staging: mt7621-spi: change mt7621_spi_wait_till_ready to take struct mt7621_spi All callers have a 'struct mt7621_spi' and that is all mt7621_spi_wait_till_ready() needs. So just pass it instead of the spi_device. Signed-off-by: NeilBrown Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/staging/mt7621-spi/spi-mt7621.c b/drivers/staging/mt7621-spi/spi-mt7621.c index 37f299080410..d43576d2a3f9 100644 --- a/drivers/staging/mt7621-spi/spi-mt7621.c +++ b/drivers/staging/mt7621-spi/spi-mt7621.c @@ -155,9 +155,8 @@ static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed) return 0; } -static inline int mt7621_spi_wait_till_ready(struct spi_device *spi) +static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs) { - struct mt7621_spi *rs = spidev_to_mt7621_spi(spi); int i; for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) { @@ -187,7 +186,7 @@ static int mt7621_spi_transfer_half_duplex(struct spi_master *master, u32 data[9] = { 0 }; u32 val; - mt7621_spi_wait_till_ready(spi); + mt7621_spi_wait_till_ready(rs); list_for_each_entry(t, &m->transfers, transfer_list) { const u8 *buf = t->tx_buf; @@ -238,7 +237,7 @@ static int mt7621_spi_transfer_half_duplex(struct spi_master *master, val |= SPI_CTL_START; mt7621_spi_write(rs, MT7621_SPI_TRANS, val); - mt7621_spi_wait_till_ready(spi); + mt7621_spi_wait_till_ready(rs); mt7621_spi_set_cs(spi, 0); @@ -278,7 +277,7 @@ static int mt7621_spi_transfer_full_duplex(struct spi_master *master, u32 data[9] = { 0 }; u32 val = 0; - mt7621_spi_wait_till_ready(spi); + mt7621_spi_wait_till_ready(rs); list_for_each_entry(t, &m->transfers, transfer_list) { const u8 *buf = t->tx_buf; @@ -323,7 +322,7 @@ static int mt7621_spi_transfer_full_duplex(struct spi_master *master, val |= SPI_CTL_START; mt7621_spi_write(rs, MT7621_SPI_TRANS, val); - mt7621_spi_wait_till_ready(spi); + mt7621_spi_wait_till_ready(rs); mt7621_spi_set_cs(spi, 0);