From: Marek Vasut <marex@denx.de>
Date: Tue, 7 May 2019 15:55:12 +0000 (+0200)
Subject: ARM: dts: socfpga: Keep FPGA bridge entries in SPL DT
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=9e6ed1a3466ea35d98e074187abcbcfee550b448;p=project%2Fbcm63xx%2Fu-boot.git

ARM: dts: socfpga: Keep FPGA bridge entries in SPL DT

Keep the FPGA bridge entries in SPL DT to let do_bridge_reset() toggle
the bridges on/off as needed according to the handoff file.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
---

diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
index 39a8d9a3e7..ef215230c2 100644
--- a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
+++ b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
@@ -64,4 +64,28 @@
 			u-boot,dm-pre-reloc;
 		};
 	};
+
+	fpgabridge@0 {
+		u-boot,dm-pre-reloc;
+	};
+
+	fpgabridge@1 {
+		u-boot,dm-pre-reloc;
+	};
+
+	fpgabridge@2 {
+		u-boot,dm-pre-reloc;
+	};
+
+	fpgabridge@3 {
+		u-boot,dm-pre-reloc;
+	};
+
+	fpgabridge@4 {
+		u-boot,dm-pre-reloc;
+	};
+
+	fpgabridge@5 {
+		u-boot,dm-pre-reloc;
+	};
 };