From: Andrew Victor Date: Mon, 5 Feb 2007 10:42:07 +0000 (+0100) Subject: [ARM] 4124/1: Rename mach-at91rm9200 and arch-at91rm9200 directories X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=9d0412680e6c7b685ee466842047bcfb924d6dc5;p=openwrt%2Fstaging%2Fblogic.git [ARM] 4124/1: Rename mach-at91rm9200 and arch-at91rm9200 directories Now that Linux includes support for the Atmel AT91SAM9260 and AT91SAM9261 processors in addition to the original Atmel AT91RM9200 (with support for more AT91 processors pending), the "mach-at91rm9200" and "arch-at91rm9200" directories should be renamed to indicate their more generic nature. The following git commands should be run BEFORE applying this patch: git-mv arch/arm/mach-at91rm9200 arch/arm/mach-at91 git-mv include/asm-arm/arch-at91rm9200 include/asm-arm/arch-at91 Signed-off-by: Andrew Victor Signed-off-by: Russell King --- diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6783c2e5512d..9c7565c8f376 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -377,7 +377,7 @@ source "arch/arm/mach-aaec2000/Kconfig" source "arch/arm/mach-realview/Kconfig" -source "arch/arm/mach-at91rm9200/Kconfig" +source "arch/arm/mach-at91/Kconfig" source "arch/arm/mach-netx/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 000f1100b553..0205547fa45c 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -124,7 +124,7 @@ endif machine-$(CONFIG_ARCH_H720X) := h720x machine-$(CONFIG_ARCH_AAEC2000) := aaec2000 machine-$(CONFIG_ARCH_REALVIEW) := realview - machine-$(CONFIG_ARCH_AT91) := at91rm9200 + machine-$(CONFIG_ARCH_AT91) := at91 machine-$(CONFIG_ARCH_EP93XX) := ep93xx machine-$(CONFIG_ARCH_PNX4008) := pnx4008 machine-$(CONFIG_ARCH_NETX) := netx diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig new file mode 100644 index 000000000000..9f11db8af233 --- /dev/null +++ b/arch/arm/mach-at91/Kconfig @@ -0,0 +1,148 @@ +if ARCH_AT91 + +menu "Atmel AT91 System-on-Chip" + +choice + prompt "Atmel AT91 Processor" + +config ARCH_AT91RM9200 + bool "AT91RM9200" + +config ARCH_AT91SAM9260 + bool "AT91SAM9260" + +config ARCH_AT91SAM9261 + bool "AT91SAM9261" + +endchoice + +# ---------------------------------------------------------- + +if ARCH_AT91RM9200 + +comment "AT91RM9200 Board Type" + +config MACH_ONEARM + bool "Ajeco 1ARM Single Board Computer" + depends on ARCH_AT91RM9200 + help + Select this if you are using Ajeco's 1ARM Single Board Computer. + + +config ARCH_AT91RM9200DK + bool "Atmel AT91RM9200-DK Development board" + depends on ARCH_AT91RM9200 + help + Select this if you are using Atmel's AT91RM9200-DK Development board. + (Discontinued) + +config MACH_AT91RM9200EK + bool "Atmel AT91RM9200-EK Evaluation Kit" + depends on ARCH_AT91RM9200 + help + Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit. + + +config MACH_CSB337 + bool "Cogent CSB337" + depends on ARCH_AT91RM9200 + help + Select this if you are using Cogent's CSB337 board. + + +config MACH_CSB637 + bool "Cogent CSB637" + depends on ARCH_AT91RM9200 + help + Select this if you are using Cogent's CSB637 board. + + +config MACH_CARMEVA + bool "Conitec ARM&EVA" + depends on ARCH_AT91RM9200 + help + Select this if you are using Conitec's AT91RM9200-MCU-Module. + + +config MACH_ATEB9200 + bool "Embest ATEB9200" + depends on ARCH_AT91RM9200 + help + Select this if you are using Embest's ATEB9200 board. + + +config MACH_KB9200 + bool "KwikByte KB920x" + depends on ARCH_AT91RM9200 + help + Select this if you are using KwikByte's KB920x board. + + +config MACH_KAFA + bool "Sperry-Sun KAFA board" + depends on ARCH_AT91RM9200 + help + Select this if you are using Sperry-Sun's KAFA board. + +endif + +# ---------------------------------------------------------- + +if ARCH_AT91SAM9260 + +comment "AT91SAM9260 Board Type" + +config MACH_AT91SAM9260EK + bool "Atmel AT91SAM9260-EK Evaluation Kit" + depends on ARCH_AT91SAM9260 + help + Select this if you are using Atmel's AT91SAM9260-EK Evaluation Kit. + + +endif + +# ---------------------------------------------------------- + +if ARCH_AT91SAM9261 + +comment "AT91SAM9261 Board Type" + +config MACH_AT91SAM9261EK + bool "Atmel AT91SAM9261-EK Evaluation Kit" + depends on ARCH_AT91SAM9261 + help + Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit. + + +endif + +# ---------------------------------------------------------- + +comment "AT91 Board Options" + +config MTD_AT91_DATAFLASH_CARD + bool "Enable DataFlash Card support" + depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK) + help + Enable support for the DataFlash card. + +config MTD_NAND_AT91_BUSWIDTH_16 + bool "Enable 16-bit data bus interface to NAND flash" + depends on (MACH_AT91SAM9261EK || MACH_AT91SAM9260EK) + help + On AT91SAM926x boards both types of NAND flash can be present + (8 and 16 bit data bus width). + +# ---------------------------------------------------------- + +comment "AT91 Feature Selections" + +config AT91_PROGRAMMABLE_CLOCKS + bool "Programmable Clocks" + help + Select this if you need to program one or more of the PCK0..PCK3 + programmable clock outputs. + +endmenu + +endif diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile new file mode 100644 index 000000000000..cf777007847a --- /dev/null +++ b/arch/arm/mach-at91/Makefile @@ -0,0 +1,49 @@ +# +# Makefile for the linux kernel. +# + +obj-y := clock.o irq.o gpio.o +obj-m := +obj-n := +obj- := + +obj-$(CONFIG_PM) += pm.o + +# CPU-specific support +obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o +obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o +obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o + +# AT91RM9200 board-specific support +obj-$(CONFIG_MACH_ONEARM) += board-1arm.o +obj-$(CONFIG_ARCH_AT91RM9200DK) += board-dk.o +obj-$(CONFIG_MACH_AT91RM9200EK) += board-ek.o +obj-$(CONFIG_MACH_CSB337) += board-csb337.o +obj-$(CONFIG_MACH_CSB637) += board-csb637.o +obj-$(CONFIG_MACH_CARMEVA) += board-carmeva.o +obj-$(CONFIG_MACH_KB9200) += board-kb9202.o +obj-$(CONFIG_MACH_ATEB9200) += board-eb9200.o +obj-$(CONFIG_MACH_KAFA) += board-kafa.o + +# AT91SAM9260 board-specific support +obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o + +# AT91SAM9261 board-specific support +obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o + +# LEDs support +led-$(CONFIG_ARCH_AT91RM9200DK) += leds.o +led-$(CONFIG_MACH_AT91RM9200EK) += leds.o +led-$(CONFIG_MACH_CSB337) += leds.o +led-$(CONFIG_MACH_CSB637) += leds.o +led-$(CONFIG_MACH_KB9200) += leds.o +led-$(CONFIG_MACH_KAFA) += leds.o +obj-$(CONFIG_LEDS) += $(led-y) + +# VGA support +#obj-$(CONFIG_FB_S1D13XXX) += ics1523.o + + +ifeq ($(CONFIG_PM_DEBUG),y) +CFLAGS_pm.o += -DDEBUG +endif diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot new file mode 100644 index 000000000000..e667dcc7cd34 --- /dev/null +++ b/arch/arm/mach-at91/Makefile.boot @@ -0,0 +1,9 @@ +# Note: the following conditions must always be true: +# ZRELADDR == virt_to_phys(TEXTADDR) +# PARAMS_PHYS must be within 4MB of ZRELADDR +# INITRD_PHYS must be in RAM + + zreladdr-y := 0x20008000 +params_phys-y := 0x20000100 +initrd_phys-y := 0x20410000 + diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c new file mode 100644 index 000000000000..870d4a4eb806 --- /dev/null +++ b/arch/arm/mach-at91/at91rm9200.c @@ -0,0 +1,294 @@ +/* + * arch/arm/mach-at91/at91rm9200.c + * + * Copyright (C) 2005 SAN People + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#include + +#include +#include +#include +#include +#include + +#include "generic.h" +#include "clock.h" + +static struct map_desc at91rm9200_io_desc[] __initdata = { + { + .virtual = AT91_VA_BASE_SYS, + .pfn = __phys_to_pfn(AT91_BASE_SYS), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = AT91_VA_BASE_EMAC, + .pfn = __phys_to_pfn(AT91RM9200_BASE_EMAC), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE, + .pfn = __phys_to_pfn(AT91RM9200_SRAM_BASE), + .length = AT91RM9200_SRAM_SIZE, + .type = MT_DEVICE, + }, +}; + +/* -------------------------------------------------------------------- + * Clocks + * -------------------------------------------------------------------- */ + +/* + * The peripheral clocks. + */ +static struct clk udc_clk = { + .name = "udc_clk", + .pmc_mask = 1 << AT91RM9200_ID_UDP, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk ohci_clk = { + .name = "ohci_clk", + .pmc_mask = 1 << AT91RM9200_ID_UHP, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk ether_clk = { + .name = "ether_clk", + .pmc_mask = 1 << AT91RM9200_ID_EMAC, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk mmc_clk = { + .name = "mci_clk", + .pmc_mask = 1 << AT91RM9200_ID_MCI, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk twi_clk = { + .name = "twi_clk", + .pmc_mask = 1 << AT91RM9200_ID_TWI, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart0_clk = { + .name = "usart0_clk", + .pmc_mask = 1 << AT91RM9200_ID_US0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart1_clk = { + .name = "usart1_clk", + .pmc_mask = 1 << AT91RM9200_ID_US1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart2_clk = { + .name = "usart2_clk", + .pmc_mask = 1 << AT91RM9200_ID_US2, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart3_clk = { + .name = "usart3_clk", + .pmc_mask = 1 << AT91RM9200_ID_US3, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk spi_clk = { + .name = "spi_clk", + .pmc_mask = 1 << AT91RM9200_ID_SPI, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioA_clk = { + .name = "pioA_clk", + .pmc_mask = 1 << AT91RM9200_ID_PIOA, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioB_clk = { + .name = "pioB_clk", + .pmc_mask = 1 << AT91RM9200_ID_PIOB, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioC_clk = { + .name = "pioC_clk", + .pmc_mask = 1 << AT91RM9200_ID_PIOC, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioD_clk = { + .name = "pioD_clk", + .pmc_mask = 1 << AT91RM9200_ID_PIOD, + .type = CLK_TYPE_PERIPHERAL, +}; + +static struct clk *periph_clocks[] __initdata = { + &pioA_clk, + &pioB_clk, + &pioC_clk, + &pioD_clk, + &usart0_clk, + &usart1_clk, + &usart2_clk, + &usart3_clk, + &mmc_clk, + &udc_clk, + &twi_clk, + &spi_clk, + // ssc 0 .. ssc2 + // tc0 .. tc5 + &ohci_clk, + ðer_clk, + // irq0 .. irq6 +}; + +/* + * The four programmable clocks. + * You must configure pin multiplexing to bring these signals out. + */ +static struct clk pck0 = { + .name = "pck0", + .pmc_mask = AT91_PMC_PCK0, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 0, +}; +static struct clk pck1 = { + .name = "pck1", + .pmc_mask = AT91_PMC_PCK1, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 1, +}; +static struct clk pck2 = { + .name = "pck2", + .pmc_mask = AT91_PMC_PCK2, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 2, +}; +static struct clk pck3 = { + .name = "pck3", + .pmc_mask = AT91_PMC_PCK3, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 3, +}; + +static void __init at91rm9200_register_clocks(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) + clk_register(periph_clocks[i]); + + clk_register(&pck0); + clk_register(&pck1); + clk_register(&pck2); + clk_register(&pck3); +} + +/* -------------------------------------------------------------------- + * GPIO + * -------------------------------------------------------------------- */ + +static struct at91_gpio_bank at91rm9200_gpio[] = { + { + .id = AT91RM9200_ID_PIOA, + .offset = AT91_PIOA, + .clock = &pioA_clk, + }, { + .id = AT91RM9200_ID_PIOB, + .offset = AT91_PIOB, + .clock = &pioB_clk, + }, { + .id = AT91RM9200_ID_PIOC, + .offset = AT91_PIOC, + .clock = &pioC_clk, + }, { + .id = AT91RM9200_ID_PIOD, + .offset = AT91_PIOD, + .clock = &pioD_clk, + } +}; + +static void at91rm9200_reset(void) +{ + /* + * Perform a hardware reset with the use of the Watchdog timer. + */ + at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1); + at91_sys_write(AT91_ST_CR, AT91_ST_WDRST); +} + + +/* -------------------------------------------------------------------- + * AT91RM9200 processor initialization + * -------------------------------------------------------------------- */ +void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banks) +{ + /* Map peripherals */ + iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc)); + + at91_arch_reset = at91rm9200_reset; + at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1) + | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3) + | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5) + | (1 << AT91RM9200_ID_IRQ6); + + /* Init clock subsystem */ + at91_clock_init(main_clock); + + /* Register the processor-specific clocks */ + at91rm9200_register_clocks(); + + /* Initialize GPIO subsystem */ + at91_gpio_init(at91rm9200_gpio, banks); +} + + +/* -------------------------------------------------------------------- + * Interrupt initialization + * -------------------------------------------------------------------- */ + +/* + * The default interrupt priority levels (0 = lowest, 7 = highest). + */ +static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = { + 7, /* Advanced Interrupt Controller (FIQ) */ + 7, /* System Peripherals */ + 0, /* Parallel IO Controller A */ + 0, /* Parallel IO Controller B */ + 0, /* Parallel IO Controller C */ + 0, /* Parallel IO Controller D */ + 6, /* USART 0 */ + 6, /* USART 1 */ + 6, /* USART 2 */ + 6, /* USART 3 */ + 0, /* Multimedia Card Interface */ + 4, /* USB Device Port */ + 0, /* Two-Wire Interface */ + 6, /* Serial Peripheral Interface */ + 5, /* Serial Synchronous Controller 0 */ + 5, /* Serial Synchronous Controller 1 */ + 5, /* Serial Synchronous Controller 2 */ + 0, /* Timer Counter 0 */ + 0, /* Timer Counter 1 */ + 0, /* Timer Counter 2 */ + 0, /* Timer Counter 3 */ + 0, /* Timer Counter 4 */ + 0, /* Timer Counter 5 */ + 3, /* USB Host port */ + 3, /* Ethernet MAC */ + 0, /* Advanced Interrupt Controller (IRQ0) */ + 0, /* Advanced Interrupt Controller (IRQ1) */ + 0, /* Advanced Interrupt Controller (IRQ2) */ + 0, /* Advanced Interrupt Controller (IRQ3) */ + 0, /* Advanced Interrupt Controller (IRQ4) */ + 0, /* Advanced Interrupt Controller (IRQ5) */ + 0 /* Advanced Interrupt Controller (IRQ6) */ +}; + +void __init at91rm9200_init_interrupts(unsigned int priority[NR_AIC_IRQS]) +{ + if (!priority) + priority = at91rm9200_default_irq_priority; + + /* Initialize the AIC interrupt controller */ + at91_aic_init(priority); + + /* Enable GPIO interrupts */ + at91_gpio_irq_setup(); +} diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c new file mode 100644 index 000000000000..a06498ccc826 --- /dev/null +++ b/arch/arm/mach-at91/at91rm9200_devices.c @@ -0,0 +1,875 @@ +/* + * arch/arm/mach-at91/at91rm9200_devices.c + * + * Copyright (C) 2005 Thibaut VARENE + * Copyright (C) 2005 David Brownell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#include +#include + +#include + +#include +#include +#include +#include + +#include "generic.h" + +#define SZ_512 0x00000200 +#define SZ_256 0x00000100 +#define SZ_16 0x00000010 + +/* -------------------------------------------------------------------- + * USB Host + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) +static u64 ohci_dmamask = 0xffffffffUL; +static struct at91_usbh_data usbh_data; + +static struct resource usbh_resources[] = { + [0] = { + .start = AT91RM9200_UHP_BASE, + .end = AT91RM9200_UHP_BASE + SZ_1M - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91RM9200_ID_UHP, + .end = AT91RM9200_ID_UHP, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device at91rm9200_usbh_device = { + .name = "at91_ohci", + .id = -1, + .dev = { + .dma_mask = &ohci_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &usbh_data, + }, + .resource = usbh_resources, + .num_resources = ARRAY_SIZE(usbh_resources), +}; + +void __init at91_add_device_usbh(struct at91_usbh_data *data) +{ + if (!data) + return; + + usbh_data = *data; + platform_device_register(&at91rm9200_usbh_device); +} +#else +void __init at91_add_device_usbh(struct at91_usbh_data *data) {} +#endif + + +/* -------------------------------------------------------------------- + * USB Device (Gadget) + * -------------------------------------------------------------------- */ + +#ifdef CONFIG_USB_GADGET_AT91 +static struct at91_udc_data udc_data; + +static struct resource udc_resources[] = { + [0] = { + .start = AT91RM9200_BASE_UDP, + .end = AT91RM9200_BASE_UDP + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91RM9200_ID_UDP, + .end = AT91RM9200_ID_UDP, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device at91rm9200_udc_device = { + .name = "at91_udc", + .id = -1, + .dev = { + .platform_data = &udc_data, + }, + .resource = udc_resources, + .num_resources = ARRAY_SIZE(udc_resources), +}; + +void __init at91_add_device_udc(struct at91_udc_data *data) +{ + if (!data) + return; + + if (data->vbus_pin) { + at91_set_gpio_input(data->vbus_pin, 0); + at91_set_deglitch(data->vbus_pin, 1); + } + if (data->pullup_pin) + at91_set_gpio_output(data->pullup_pin, 0); + + udc_data = *data; + platform_device_register(&at91rm9200_udc_device); +} +#else +void __init at91_add_device_udc(struct at91_udc_data *data) {} +#endif + + +/* -------------------------------------------------------------------- + * Ethernet + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_ARM_AT91_ETHER) || defined(CONFIG_ARM_AT91_ETHER_MODULE) +static u64 eth_dmamask = 0xffffffffUL; +static struct at91_eth_data eth_data; + +static struct resource eth_resources[] = { + [0] = { + .start = AT91_VA_BASE_EMAC, + .end = AT91_VA_BASE_EMAC + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91RM9200_ID_EMAC, + .end = AT91RM9200_ID_EMAC, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device at91rm9200_eth_device = { + .name = "at91_ether", + .id = -1, + .dev = { + .dma_mask = ð_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = ð_data, + }, + .resource = eth_resources, + .num_resources = ARRAY_SIZE(eth_resources), +}; + +void __init at91_add_device_eth(struct at91_eth_data *data) +{ + if (!data) + return; + + if (data->phy_irq_pin) { + at91_set_gpio_input(data->phy_irq_pin, 0); + at91_set_deglitch(data->phy_irq_pin, 1); + } + + /* Pins used for MII and RMII */ + at91_set_A_periph(AT91_PIN_PA16, 0); /* EMDIO */ + at91_set_A_periph(AT91_PIN_PA15, 0); /* EMDC */ + at91_set_A_periph(AT91_PIN_PA14, 0); /* ERXER */ + at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */ + at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */ + at91_set_A_periph(AT91_PIN_PA11, 0); /* ECRS_ECRSDV */ + at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX1 */ + at91_set_A_periph(AT91_PIN_PA9, 0); /* ETX0 */ + at91_set_A_periph(AT91_PIN_PA8, 0); /* ETXEN */ + at91_set_A_periph(AT91_PIN_PA7, 0); /* ETXCK_EREFCK */ + + if (!data->is_rmii) { + at91_set_B_periph(AT91_PIN_PB19, 0); /* ERXCK */ + at91_set_B_periph(AT91_PIN_PB18, 0); /* ECOL */ + at91_set_B_periph(AT91_PIN_PB17, 0); /* ERXDV */ + at91_set_B_periph(AT91_PIN_PB16, 0); /* ERX3 */ + at91_set_B_periph(AT91_PIN_PB15, 0); /* ERX2 */ + at91_set_B_periph(AT91_PIN_PB14, 0); /* ETXER */ + at91_set_B_periph(AT91_PIN_PB13, 0); /* ETX3 */ + at91_set_B_periph(AT91_PIN_PB12, 0); /* ETX2 */ + } + + eth_data = *data; + platform_device_register(&at91rm9200_eth_device); +} +#else +void __init at91_add_device_eth(struct at91_eth_data *data) {} +#endif + + +/* -------------------------------------------------------------------- + * Compact Flash / PCMCIA + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) +static struct at91_cf_data cf_data; + +#define CF_BASE AT91_CHIPSELECT_4 + +static struct resource cf_resources[] = { + [0] = { + .start = CF_BASE, + /* ties up CS4, CS5 and CS6 */ + .end = CF_BASE + (0x30000000 - 1), + .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT, + }, +}; + +static struct platform_device at91rm9200_cf_device = { + .name = "at91_cf", + .id = -1, + .dev = { + .platform_data = &cf_data, + }, + .resource = cf_resources, + .num_resources = ARRAY_SIZE(cf_resources), +}; + +void __init at91_add_device_cf(struct at91_cf_data *data) +{ + unsigned int csa; + + if (!data) + return; + + data->chipselect = 4; /* can only use EBI ChipSelect 4 */ + + /* CF takes over CS4, CS5, CS6 */ + csa = at91_sys_read(AT91_EBI_CSA); + at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH); + + /* + * Static memory controller timing adjustments. + * REVISIT: these timings are in terms of MCK cycles, so + * when MCK changes (cpufreq etc) so must these values... + */ + at91_sys_write(AT91_SMC_CSR(4), + AT91_SMC_ACSS_STD + | AT91_SMC_DBW_16 + | AT91_SMC_BAT + | AT91_SMC_WSEN + | AT91_SMC_NWS_(32) /* wait states */ + | AT91_SMC_RWSETUP_(6) /* setup time */ + | AT91_SMC_RWHOLD_(4) /* hold time */ + ); + + /* input/irq */ + if (data->irq_pin) { + at91_set_gpio_input(data->irq_pin, 1); + at91_set_deglitch(data->irq_pin, 1); + } + at91_set_gpio_input(data->det_pin, 1); + at91_set_deglitch(data->det_pin, 1); + + /* outputs, initially off */ + if (data->vcc_pin) + at91_set_gpio_output(data->vcc_pin, 0); + at91_set_gpio_output(data->rst_pin, 0); + + /* force poweron defaults for these pins ... */ + at91_set_A_periph(AT91_PIN_PC9, 0); /* A25/CFRNW */ + at91_set_A_periph(AT91_PIN_PC10, 0); /* NCS4/CFCS */ + at91_set_A_periph(AT91_PIN_PC11, 0); /* NCS5/CFCE1 */ + at91_set_A_periph(AT91_PIN_PC12, 0); /* NCS6/CFCE2 */ + + /* nWAIT is _not_ a default setting */ + at91_set_A_periph(AT91_PIN_PC6, 1); /* nWAIT */ + + cf_data = *data; + platform_device_register(&at91rm9200_cf_device); +} +#else +void __init at91_add_device_cf(struct at91_cf_data *data) {} +#endif + + +/* -------------------------------------------------------------------- + * MMC / SD + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE) +static u64 mmc_dmamask = 0xffffffffUL; +static struct at91_mmc_data mmc_data; + +static struct resource mmc_resources[] = { + [0] = { + .start = AT91RM9200_BASE_MCI, + .end = AT91RM9200_BASE_MCI + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91RM9200_ID_MCI, + .end = AT91RM9200_ID_MCI, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device at91rm9200_mmc_device = { + .name = "at91_mci", + .id = -1, + .dev = { + .dma_mask = &mmc_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &mmc_data, + }, + .resource = mmc_resources, + .num_resources = ARRAY_SIZE(mmc_resources), +}; + +void __init at91_add_device_mmc(struct at91_mmc_data *data) +{ + if (!data) + return; + + /* input/irq */ + if (data->det_pin) { + at91_set_gpio_input(data->det_pin, 1); + at91_set_deglitch(data->det_pin, 1); + } + if (data->wp_pin) + at91_set_gpio_input(data->wp_pin, 1); + if (data->vcc_pin) + at91_set_gpio_output(data->vcc_pin, 0); + + /* CLK */ + at91_set_A_periph(AT91_PIN_PA27, 0); + + if (data->slot_b) { + /* CMD */ + at91_set_B_periph(AT91_PIN_PA8, 1); + + /* DAT0, maybe DAT1..DAT3 */ + at91_set_B_periph(AT91_PIN_PA9, 1); + if (data->wire4) { + at91_set_B_periph(AT91_PIN_PA10, 1); + at91_set_B_periph(AT91_PIN_PA11, 1); + at91_set_B_periph(AT91_PIN_PA12, 1); + } + } else { + /* CMD */ + at91_set_A_periph(AT91_PIN_PA28, 1); + + /* DAT0, maybe DAT1..DAT3 */ + at91_set_A_periph(AT91_PIN_PA29, 1); + if (data->wire4) { + at91_set_B_periph(AT91_PIN_PB3, 1); + at91_set_B_periph(AT91_PIN_PB4, 1); + at91_set_B_periph(AT91_PIN_PB5, 1); + } + } + + mmc_data = *data; + platform_device_register(&at91rm9200_mmc_device); +} +#else +void __init at91_add_device_mmc(struct at91_mmc_data *data) {} +#endif + + +/* -------------------------------------------------------------------- + * NAND / SmartMedia + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE) +static struct at91_nand_data nand_data; + +#define NAND_BASE AT91_CHIPSELECT_3 + +static struct resource nand_resources[] = { + { + .start = NAND_BASE, + .end = NAND_BASE + SZ_8M - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device at91rm9200_nand_device = { + .name = "at91_nand", + .id = -1, + .dev = { + .platform_data = &nand_data, + }, + .resource = nand_resources, + .num_resources = ARRAY_SIZE(nand_resources), +}; + +void __init at91_add_device_nand(struct at91_nand_data *data) +{ + unsigned int csa; + + if (!data) + return; + + /* enable the address range of CS3 */ + csa = at91_sys_read(AT91_EBI_CSA); + at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA); + + /* set the bus interface characteristics */ + at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN + | AT91_SMC_NWS_(5) + | AT91_SMC_TDF_(1) + | AT91_SMC_RWSETUP_(0) /* tDS Data Set up Time 30 - ns */ + | AT91_SMC_RWHOLD_(1) /* tDH Data Hold Time 20 - ns */ + ); + + /* enable pin */ + if (data->enable_pin) + at91_set_gpio_output(data->enable_pin, 1); + + /* ready/busy pin */ + if (data->rdy_pin) + at91_set_gpio_input(data->rdy_pin, 1); + + /* card detect pin */ + if (data->det_pin) + at91_set_gpio_input(data->det_pin, 1); + + at91_set_A_periph(AT91_PIN_PC1, 0); /* SMOE */ + at91_set_A_periph(AT91_PIN_PC3, 0); /* SMWE */ + + nand_data = *data; + platform_device_register(&at91rm9200_nand_device); +} +#else +void __init at91_add_device_nand(struct at91_nand_data *data) {} +#endif + + +/* -------------------------------------------------------------------- + * TWI (i2c) + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE) + +static struct resource twi_resources[] = { + [0] = { + .start = AT91RM9200_BASE_TWI, + .end = AT91RM9200_BASE_TWI + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91RM9200_ID_TWI, + .end = AT91RM9200_ID_TWI, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device at91rm9200_twi_device = { + .name = "at91_i2c", + .id = -1, + .resource = twi_resources, + .num_resources = ARRAY_SIZE(twi_resources), +}; + +void __init at91_add_device_i2c(void) +{ + /* pins used for TWI interface */ + at91_set_A_periph(AT91_PIN_PA25, 0); /* TWD */ + at91_set_multi_drive(AT91_PIN_PA25, 1); + + at91_set_A_periph(AT91_PIN_PA26, 0); /* TWCK */ + at91_set_multi_drive(AT91_PIN_PA26, 1); + + platform_device_register(&at91rm9200_twi_device); +} +#else +void __init at91_add_device_i2c(void) {} +#endif + + +/* -------------------------------------------------------------------- + * SPI + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_SPI_AT91) || defined(CONFIG_SPI_AT91_MODULE) || defined(CONFIG_AT91_SPI) || defined(CONFIG_AT91_SPI_MODULE) +static u64 spi_dmamask = 0xffffffffUL; + +static struct resource spi_resources[] = { + [0] = { + .start = AT91RM9200_BASE_SPI, + .end = AT91RM9200_BASE_SPI + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91RM9200_ID_SPI, + .end = AT91RM9200_ID_SPI, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device at91rm9200_spi_device = { + .name = "at91_spi", + .id = 0, + .dev = { + .dma_mask = &spi_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = spi_resources, + .num_resources = ARRAY_SIZE(spi_resources), +}; + +static const unsigned spi_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 }; + +void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) +{ + int i; + unsigned long cs_pin; + + at91_set_A_periph(AT91_PIN_PA0, 0); /* MISO */ + at91_set_A_periph(AT91_PIN_PA1, 0); /* MOSI */ + at91_set_A_periph(AT91_PIN_PA2, 0); /* SPCK */ + + /* Enable SPI chip-selects */ + for (i = 0; i < nr_devices; i++) { + if (devices[i].controller_data) + cs_pin = (unsigned long) devices[i].controller_data; + else + cs_pin = spi_standard_cs[devices[i].chip_select]; + +#ifdef CONFIG_SPI_AT91_MANUAL_CS + at91_set_gpio_output(cs_pin, 1); +#else + at91_set_A_periph(cs_pin, 0); +#endif + + /* pass chip-select pin to driver */ + devices[i].controller_data = (void *) cs_pin; + } + + spi_register_board_info(devices, nr_devices); + at91_clock_associate("spi_clk", &at91rm9200_spi_device.dev, "spi"); + platform_device_register(&at91rm9200_spi_device); +} +#else +void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {} +#endif + + +/* -------------------------------------------------------------------- + * RTC + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE) +static struct platform_device at91rm9200_rtc_device = { + .name = "at91_rtc", + .id = -1, + .num_resources = 0, +}; + +static void __init at91_add_device_rtc(void) +{ + platform_device_register(&at91rm9200_rtc_device); +} +#else +static void __init at91_add_device_rtc(void) {} +#endif + + +/* -------------------------------------------------------------------- + * Watchdog + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_AT91RM9200_WATCHDOG) || defined(CONFIG_AT91RM9200_WATCHDOG_MODULE) +static struct platform_device at91rm9200_wdt_device = { + .name = "at91_wdt", + .id = -1, + .num_resources = 0, +}; + +static void __init at91_add_device_watchdog(void) +{ + platform_device_register(&at91rm9200_wdt_device); +} +#else +static void __init at91_add_device_watchdog(void) {} +#endif + + +/* -------------------------------------------------------------------- + * LEDs + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_LEDS) +u8 at91_leds_cpu; +u8 at91_leds_timer; + +void __init at91_init_leds(u8 cpu_led, u8 timer_led) +{ + at91_leds_cpu = cpu_led; + at91_leds_timer = timer_led; +} +#else +void __init at91_init_leds(u8 cpu_led, u8 timer_led) {} +#endif + + +/* -------------------------------------------------------------------- + * UART + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_SERIAL_ATMEL) +static struct resource dbgu_resources[] = { + [0] = { + .start = AT91_VA_BASE_SYS + AT91_DBGU, + .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91_ID_SYS, + .end = AT91_ID_SYS, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct atmel_uart_data dbgu_data = { + .use_dma_tx = 0, + .use_dma_rx = 0, /* DBGU not capable of receive DMA */ + .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU), +}; + +static struct platform_device at91rm9200_dbgu_device = { + .name = "atmel_usart", + .id = 0, + .dev = { + .platform_data = &dbgu_data, + .coherent_dma_mask = 0xffffffff, + }, + .resource = dbgu_resources, + .num_resources = ARRAY_SIZE(dbgu_resources), +}; + +static inline void configure_dbgu_pins(void) +{ + at91_set_A_periph(AT91_PIN_PA30, 0); /* DRXD */ + at91_set_A_periph(AT91_PIN_PA31, 1); /* DTXD */ +} + +static struct resource uart0_resources[] = { + [0] = { + .start = AT91RM9200_BASE_US0, + .end = AT91RM9200_BASE_US0 + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91RM9200_ID_US0, + .end = AT91RM9200_ID_US0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct atmel_uart_data uart0_data = { + .use_dma_tx = 1, + .use_dma_rx = 1, +}; + +static struct platform_device at91rm9200_uart0_device = { + .name = "atmel_usart", + .id = 1, + .dev = { + .platform_data = &uart0_data, + .coherent_dma_mask = 0xffffffff, + }, + .resource = uart0_resources, + .num_resources = ARRAY_SIZE(uart0_resources), +}; + +static inline void configure_usart0_pins(void) +{ + at91_set_A_periph(AT91_PIN_PA17, 1); /* TXD0 */ + at91_set_A_periph(AT91_PIN_PA18, 0); /* RXD0 */ + at91_set_A_periph(AT91_PIN_PA20, 0); /* CTS0 */ + + /* + * AT91RM9200 Errata #39 - RTS0 is not internally connected to PA21. + * We need to drive the pin manually. Default is off (RTS is active low). + */ + at91_set_gpio_output(AT91_PIN_PA21, 1); +} + +static struct resource uart1_resources[] = { + [0] = { + .start = AT91RM9200_BASE_US1, + .end = AT91RM9200_BASE_US1 + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91RM9200_ID_US1, + .end = AT91RM9200_ID_US1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct atmel_uart_data uart1_data = { + .use_dma_tx = 1, + .use_dma_rx = 1, +}; + +static struct platform_device at91rm9200_uart1_device = { + .name = "atmel_usart", + .id = 2, + .dev = { + .platform_data = &uart1_data, + .coherent_dma_mask = 0xffffffff, + }, + .resource = uart1_resources, + .num_resources = ARRAY_SIZE(uart1_resources), +}; + +static inline void configure_usart1_pins(void) +{ + at91_set_A_periph(AT91_PIN_PB18, 0); /* RI1 */ + at91_set_A_periph(AT91_PIN_PB19, 0); /* DTR1 */ + at91_set_A_periph(AT91_PIN_PB20, 1); /* TXD1 */ + at91_set_A_periph(AT91_PIN_PB21, 0); /* RXD1 */ + at91_set_A_periph(AT91_PIN_PB23, 0); /* DCD1 */ + at91_set_A_periph(AT91_PIN_PB24, 0); /* CTS1 */ + at91_set_A_periph(AT91_PIN_PB25, 0); /* DSR1 */ + at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS1 */ +} + +static struct resource uart2_resources[] = { + [0] = { + .start = AT91RM9200_BASE_US2, + .end = AT91RM9200_BASE_US2 + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91RM9200_ID_US2, + .end = AT91RM9200_ID_US2, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct atmel_uart_data uart2_data = { + .use_dma_tx = 1, + .use_dma_rx = 1, +}; + +static struct platform_device at91rm9200_uart2_device = { + .name = "atmel_usart", + .id = 3, + .dev = { + .platform_data = &uart2_data, + .coherent_dma_mask = 0xffffffff, + }, + .resource = uart2_resources, + .num_resources = ARRAY_SIZE(uart2_resources), +}; + +static inline void configure_usart2_pins(void) +{ + at91_set_A_periph(AT91_PIN_PA22, 0); /* RXD2 */ + at91_set_A_periph(AT91_PIN_PA23, 1); /* TXD2 */ +} + +static struct resource uart3_resources[] = { + [0] = { + .start = AT91RM9200_BASE_US3, + .end = AT91RM9200_BASE_US3 + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91RM9200_ID_US3, + .end = AT91RM9200_ID_US3, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct atmel_uart_data uart3_data = { + .use_dma_tx = 1, + .use_dma_rx = 1, +}; + +static struct platform_device at91rm9200_uart3_device = { + .name = "atmel_usart", + .id = 4, + .dev = { + .platform_data = &uart3_data, + .coherent_dma_mask = 0xffffffff, + }, + .resource = uart3_resources, + .num_resources = ARRAY_SIZE(uart3_resources), +}; + +static inline void configure_usart3_pins(void) +{ + at91_set_B_periph(AT91_PIN_PA5, 1); /* TXD3 */ + at91_set_B_periph(AT91_PIN_PA6, 0); /* RXD3 */ +} + +struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ +struct platform_device *atmel_default_console_device; /* the serial console device */ + +void __init at91_init_serial(struct at91_uart_config *config) +{ + int i; + + /* Fill in list of supported UARTs */ + for (i = 0; i < config->nr_tty; i++) { + switch (config->tty_map[i]) { + case 0: + configure_usart0_pins(); + at91_uarts[i] = &at91rm9200_uart0_device; + at91_clock_associate("usart0_clk", &at91rm9200_uart0_device.dev, "usart"); + break; + case 1: + configure_usart1_pins(); + at91_uarts[i] = &at91rm9200_uart1_device; + at91_clock_associate("usart1_clk", &at91rm9200_uart1_device.dev, "usart"); + break; + case 2: + configure_usart2_pins(); + at91_uarts[i] = &at91rm9200_uart2_device; + at91_clock_associate("usart2_clk", &at91rm9200_uart2_device.dev, "usart"); + break; + case 3: + configure_usart3_pins(); + at91_uarts[i] = &at91rm9200_uart3_device; + at91_clock_associate("usart3_clk", &at91rm9200_uart3_device.dev, "usart"); + break; + case 4: + configure_dbgu_pins(); + at91_uarts[i] = &at91rm9200_dbgu_device; + at91_clock_associate("mck", &at91rm9200_dbgu_device.dev, "usart"); + break; + default: + continue; + } + at91_uarts[i]->id = i; /* update ID number to mapped ID */ + } + + /* Set serial console device */ + if (config->console_tty < ATMEL_MAX_UART) + atmel_default_console_device = at91_uarts[config->console_tty]; + if (!atmel_default_console_device) + printk(KERN_INFO "AT91: No default serial console defined.\n"); +} + +void __init at91_add_device_serial(void) +{ + int i; + + for (i = 0; i < ATMEL_MAX_UART; i++) { + if (at91_uarts[i]) + platform_device_register(at91_uarts[i]); + } +} +#else +void __init at91_init_serial(struct at91_uart_config *config) {} +void __init at91_add_device_serial(void) {} +#endif + + +/* -------------------------------------------------------------------- */ + +/* + * These devices are always present and don't need any board-specific + * setup. + */ +static int __init at91_add_standard_devices(void) +{ + at91_add_device_rtc(); + at91_add_device_watchdog(); + return 0; +} + +arch_initcall(at91_add_standard_devices); diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c new file mode 100644 index 000000000000..949199a244c7 --- /dev/null +++ b/arch/arm/mach-at91/at91rm9200_time.c @@ -0,0 +1,146 @@ +/* + * linux/arch/arm/mach-at91/at91rm9200_time.c + * + * Copyright (C) 2003 SAN People + * Copyright (C) 2003 ATMEL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +static unsigned long last_crtr; + +/* + * The ST_CRTR is updated asynchronously to the master clock. It is therefore + * necessary to read it twice (with the same value) to ensure accuracy. + */ +static inline unsigned long read_CRTR(void) { + unsigned long x1, x2; + + do { + x1 = at91_sys_read(AT91_ST_CRTR); + x2 = at91_sys_read(AT91_ST_CRTR); + } while (x1 != x2); + + return x1; +} + +/* + * Returns number of microseconds since last timer interrupt. Note that interrupts + * will have been disabled by do_gettimeofday() + * 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy. + * 'tick' is usecs per jiffy (linux/timex.h). + */ +static unsigned long at91rm9200_gettimeoffset(void) +{ + unsigned long elapsed; + + elapsed = (read_CRTR() - last_crtr) & AT91_ST_ALMV; + + return (unsigned long)(elapsed * (tick_nsec / 1000)) / LATCH; +} + +/* + * IRQ handler for the timer. + */ +static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id) +{ + if (at91_sys_read(AT91_ST_SR) & AT91_ST_PITS) { /* This is a shared interrupt */ + write_seqlock(&xtime_lock); + + while (((read_CRTR() - last_crtr) & AT91_ST_ALMV) >= LATCH) { + timer_tick(); + last_crtr = (last_crtr + LATCH) & AT91_ST_ALMV; + } + + write_sequnlock(&xtime_lock); + + return IRQ_HANDLED; + } + else + return IRQ_NONE; /* not handled */ +} + +static struct irqaction at91rm9200_timer_irq = { + .name = "at91_tick", + .flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER, + .handler = at91rm9200_timer_interrupt +}; + +void at91rm9200_timer_reset(void) +{ + last_crtr = 0; + + /* Real time counter incremented every 30.51758 microseconds */ + at91_sys_write(AT91_ST_RTMR, 1); + + /* Set Period Interval timer */ + at91_sys_write(AT91_ST_PIMR, LATCH); + + /* Clear any pending interrupts */ + (void) at91_sys_read(AT91_ST_SR); + + /* Enable Period Interval Timer interrupt */ + at91_sys_write(AT91_ST_IER, AT91_ST_PITS); +} + +/* + * Set up timer interrupt. + */ +void __init at91rm9200_timer_init(void) +{ + /* Disable all timer interrupts */ + at91_sys_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS); + (void) at91_sys_read(AT91_ST_SR); /* Clear any pending interrupts */ + + /* Make IRQs happen for the system timer */ + setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq); + + /* Change the kernel's 'tick' value to 10009 usec. (the default is 10000) */ + tick_usec = (LATCH * 1000000) / CLOCK_TICK_RATE; + + /* Initialize and enable the timer interrupt */ + at91rm9200_timer_reset(); +} + +#ifdef CONFIG_PM +static void at91rm9200_timer_suspend(void) +{ + /* disable Period Interval Timer interrupt */ + at91_sys_write(AT91_ST_IDR, AT91_ST_PITS); +} +#else +#define at91rm9200_timer_suspend NULL +#endif + +struct sys_timer at91rm9200_timer = { + .init = at91rm9200_timer_init, + .offset = at91rm9200_gettimeoffset, + .suspend = at91rm9200_timer_suspend, + .resume = at91rm9200_timer_reset, +}; + diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c new file mode 100644 index 000000000000..ffc4c0944740 --- /dev/null +++ b/arch/arm/mach-at91/at91sam9260.c @@ -0,0 +1,295 @@ +/* + * arch/arm/mach-at91/at91sam9260.c + * + * Copyright (C) 2006 SAN People + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#include + +#include +#include +#include +#include +#include + +#include "generic.h" +#include "clock.h" + +static struct map_desc at91sam9260_io_desc[] __initdata = { + { + .virtual = AT91_VA_BASE_SYS, + .pfn = __phys_to_pfn(AT91_BASE_SYS), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE, + .pfn = __phys_to_pfn(AT91SAM9260_SRAM0_BASE), + .length = AT91SAM9260_SRAM0_SIZE, + .type = MT_DEVICE, + }, { + .virtual = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE - AT91SAM9260_SRAM1_SIZE, + .pfn = __phys_to_pfn(AT91SAM9260_SRAM1_BASE), + .length = AT91SAM9260_SRAM1_SIZE, + .type = MT_DEVICE, + }, +}; + +/* -------------------------------------------------------------------- + * Clocks + * -------------------------------------------------------------------- */ + +/* + * The peripheral clocks. + */ +static struct clk pioA_clk = { + .name = "pioA_clk", + .pmc_mask = 1 << AT91SAM9260_ID_PIOA, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioB_clk = { + .name = "pioB_clk", + .pmc_mask = 1 << AT91SAM9260_ID_PIOB, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioC_clk = { + .name = "pioC_clk", + .pmc_mask = 1 << AT91SAM9260_ID_PIOC, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk adc_clk = { + .name = "adc_clk", + .pmc_mask = 1 << AT91SAM9260_ID_ADC, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart0_clk = { + .name = "usart0_clk", + .pmc_mask = 1 << AT91SAM9260_ID_US0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart1_clk = { + .name = "usart1_clk", + .pmc_mask = 1 << AT91SAM9260_ID_US1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart2_clk = { + .name = "usart2_clk", + .pmc_mask = 1 << AT91SAM9260_ID_US2, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk mmc_clk = { + .name = "mci_clk", + .pmc_mask = 1 << AT91SAM9260_ID_MCI, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk udc_clk = { + .name = "udc_clk", + .pmc_mask = 1 << AT91SAM9260_ID_UDP, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk twi_clk = { + .name = "twi_clk", + .pmc_mask = 1 << AT91SAM9260_ID_TWI, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk spi0_clk = { + .name = "spi0_clk", + .pmc_mask = 1 << AT91SAM9260_ID_SPI0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk spi1_clk = { + .name = "spi1_clk", + .pmc_mask = 1 << AT91SAM9260_ID_SPI1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk ohci_clk = { + .name = "ohci_clk", + .pmc_mask = 1 << AT91SAM9260_ID_UHP, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk ether_clk = { + .name = "ether_clk", + .pmc_mask = 1 << AT91SAM9260_ID_EMAC, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk isi_clk = { + .name = "isi_clk", + .pmc_mask = 1 << AT91SAM9260_ID_ISI, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart3_clk = { + .name = "usart3_clk", + .pmc_mask = 1 << AT91SAM9260_ID_US3, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart4_clk = { + .name = "usart4_clk", + .pmc_mask = 1 << AT91SAM9260_ID_US4, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart5_clk = { + .name = "usart5_clk", + .pmc_mask = 1 << AT91SAM9260_ID_US5, + .type = CLK_TYPE_PERIPHERAL, +}; + +static struct clk *periph_clocks[] __initdata = { + &pioA_clk, + &pioB_clk, + &pioC_clk, + &adc_clk, + &usart0_clk, + &usart1_clk, + &usart2_clk, + &mmc_clk, + &udc_clk, + &twi_clk, + &spi0_clk, + &spi1_clk, + // ssc + // tc0 .. tc2 + &ohci_clk, + ðer_clk, + &isi_clk, + &usart3_clk, + &usart4_clk, + &usart5_clk, + // tc3 .. tc5 + // irq0 .. irq2 +}; + +/* + * The two programmable clocks. + * You must configure pin multiplexing to bring these signals out. + */ +static struct clk pck0 = { + .name = "pck0", + .pmc_mask = AT91_PMC_PCK0, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 0, +}; +static struct clk pck1 = { + .name = "pck1", + .pmc_mask = AT91_PMC_PCK1, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 1, +}; + +static void __init at91sam9260_register_clocks(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) + clk_register(periph_clocks[i]); + + clk_register(&pck0); + clk_register(&pck1); +} + +/* -------------------------------------------------------------------- + * GPIO + * -------------------------------------------------------------------- */ + +static struct at91_gpio_bank at91sam9260_gpio[] = { + { + .id = AT91SAM9260_ID_PIOA, + .offset = AT91_PIOA, + .clock = &pioA_clk, + }, { + .id = AT91SAM9260_ID_PIOB, + .offset = AT91_PIOB, + .clock = &pioB_clk, + }, { + .id = AT91SAM9260_ID_PIOC, + .offset = AT91_PIOC, + .clock = &pioC_clk, + } +}; + +static void at91sam9260_reset(void) +{ + at91_sys_write(AT91_RSTC_CR, (0xA5 << 24) | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); +} + + +/* -------------------------------------------------------------------- + * AT91SAM9260 processor initialization + * -------------------------------------------------------------------- */ + +void __init at91sam9260_initialize(unsigned long main_clock) +{ + /* Map peripherals */ + iotable_init(at91sam9260_io_desc, ARRAY_SIZE(at91sam9260_io_desc)); + + at91_arch_reset = at91sam9260_reset; + at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1) + | (1 << AT91SAM9260_ID_IRQ2); + + /* Init clock subsystem */ + at91_clock_init(main_clock); + + /* Register the processor-specific clocks */ + at91sam9260_register_clocks(); + + /* Register GPIO subsystem */ + at91_gpio_init(at91sam9260_gpio, 3); +} + +/* -------------------------------------------------------------------- + * Interrupt initialization + * -------------------------------------------------------------------- */ + +/* + * The default interrupt priority levels (0 = lowest, 7 = highest). + */ +static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = { + 7, /* Advanced Interrupt Controller */ + 7, /* System Peripherals */ + 0, /* Parallel IO Controller A */ + 0, /* Parallel IO Controller B */ + 0, /* Parallel IO Controller C */ + 0, /* Analog-to-Digital Converter */ + 6, /* USART 0 */ + 6, /* USART 1 */ + 6, /* USART 2 */ + 0, /* Multimedia Card Interface */ + 4, /* USB Device Port */ + 0, /* Two-Wire Interface */ + 6, /* Serial Peripheral Interface 0 */ + 6, /* Serial Peripheral Interface 1 */ + 5, /* Serial Synchronous Controller */ + 0, + 0, + 0, /* Timer Counter 0 */ + 0, /* Timer Counter 1 */ + 0, /* Timer Counter 2 */ + 3, /* USB Host port */ + 3, /* Ethernet */ + 0, /* Image Sensor Interface */ + 6, /* USART 3 */ + 6, /* USART 4 */ + 6, /* USART 5 */ + 0, /* Timer Counter 3 */ + 0, /* Timer Counter 4 */ + 0, /* Timer Counter 5 */ + 0, /* Advanced Interrupt Controller */ + 0, /* Advanced Interrupt Controller */ + 0, /* Advanced Interrupt Controller */ +}; + +void __init at91sam9260_init_interrupts(unsigned int priority[NR_AIC_IRQS]) +{ + if (!priority) + priority = at91sam9260_default_irq_priority; + + /* Initialize the AIC interrupt controller */ + at91_aic_init(priority); + + /* Enable GPIO interrupts */ + at91_gpio_irq_setup(); +} diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c new file mode 100644 index 000000000000..4adff70b9ba0 --- /dev/null +++ b/arch/arm/mach-at91/at91sam9260_devices.c @@ -0,0 +1,867 @@ +/* + * arch/arm/mach-at91/at91sam9260_devices.c + * + * Copyright (C) 2006 Atmel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#include +#include + +#include + +#include +#include +#include +#include +#include + +#include "generic.h" + +#define SZ_512 0x00000200 +#define SZ_256 0x00000100 +#define SZ_16 0x00000010 + +/* -------------------------------------------------------------------- + * USB Host + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) +static u64 ohci_dmamask = 0xffffffffUL; +static struct at91_usbh_data usbh_data; + +static struct resource usbh_resources[] = { + [0] = { + .start = AT91SAM9260_UHP_BASE, + .end = AT91SAM9260_UHP_BASE + SZ_1M - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9260_ID_UHP, + .end = AT91SAM9260_ID_UHP, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device at91_usbh_device = { + .name = "at91_ohci", + .id = -1, + .dev = { + .dma_mask = &ohci_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &usbh_data, + }, + .resource = usbh_resources, + .num_resources = ARRAY_SIZE(usbh_resources), +}; + +void __init at91_add_device_usbh(struct at91_usbh_data *data) +{ + if (!data) + return; + + usbh_data = *data; + platform_device_register(&at91_usbh_device); +} +#else +void __init at91_add_device_usbh(struct at91_usbh_data *data) {} +#endif + + +/* -------------------------------------------------------------------- + * USB Device (Gadget) + * -------------------------------------------------------------------- */ + +#ifdef CONFIG_USB_GADGET_AT91 +static struct at91_udc_data udc_data; + +static struct resource udc_resources[] = { + [0] = { + .start = AT91SAM9260_BASE_UDP, + .end = AT91SAM9260_BASE_UDP + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9260_ID_UDP, + .end = AT91SAM9260_ID_UDP, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device at91_udc_device = { + .name = "at91_udc", + .id = -1, + .dev = { + .platform_data = &udc_data, + }, + .resource = udc_resources, + .num_resources = ARRAY_SIZE(udc_resources), +}; + +void __init at91_add_device_udc(struct at91_udc_data *data) +{ + if (!data) + return; + + if (data->vbus_pin) { + at91_set_gpio_input(data->vbus_pin, 0); + at91_set_deglitch(data->vbus_pin, 1); + } + + /* Pullup pin is handled internally by USB device peripheral */ + + udc_data = *data; + platform_device_register(&at91_udc_device); +} +#else +void __init at91_add_device_udc(struct at91_udc_data *data) {} +#endif + + +/* -------------------------------------------------------------------- + * Ethernet + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE) +static u64 eth_dmamask = 0xffffffffUL; +static struct at91_eth_data eth_data; + +static struct resource eth_resources[] = { + [0] = { + .start = AT91SAM9260_BASE_EMAC, + .end = AT91SAM9260_BASE_EMAC + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9260_ID_EMAC, + .end = AT91SAM9260_ID_EMAC, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device at91sam9260_eth_device = { + .name = "macb", + .id = -1, + .dev = { + .dma_mask = ð_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = ð_data, + }, + .resource = eth_resources, + .num_resources = ARRAY_SIZE(eth_resources), +}; + +void __init at91_add_device_eth(struct at91_eth_data *data) +{ + if (!data) + return; + + if (data->phy_irq_pin) { + at91_set_gpio_input(data->phy_irq_pin, 0); + at91_set_deglitch(data->phy_irq_pin, 1); + } + + /* Pins used for MII and RMII */ + at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */ + at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */ + at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */ + at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */ + at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */ + at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */ + at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */ + at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */ + at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */ + at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */ + + if (!data->is_rmii) { + at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */ + at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */ + at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */ + at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */ + at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */ + at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */ + at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */ + at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */ + } + + eth_data = *data; + platform_device_register(&at91sam9260_eth_device); +} +#else +void __init at91_add_device_eth(struct at91_eth_data *data) {} +#endif + + +/* -------------------------------------------------------------------- + * MMC / SD + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE) +static u64 mmc_dmamask = 0xffffffffUL; +static struct at91_mmc_data mmc_data; + +static struct resource mmc_resources[] = { + [0] = { + .start = AT91SAM9260_BASE_MCI, + .end = AT91SAM9260_BASE_MCI + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9260_ID_MCI, + .end = AT91SAM9260_ID_MCI, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device at91sam9260_mmc_device = { + .name = "at91_mci", + .id = -1, + .dev = { + .dma_mask = &mmc_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &mmc_data, + }, + .resource = mmc_resources, + .num_resources = ARRAY_SIZE(mmc_resources), +}; + +void __init at91_add_device_mmc(struct at91_mmc_data *data) +{ + if (!data) + return; + + /* input/irq */ + if (data->det_pin) { + at91_set_gpio_input(data->det_pin, 1); + at91_set_deglitch(data->det_pin, 1); + } + if (data->wp_pin) + at91_set_gpio_input(data->wp_pin, 1); + if (data->vcc_pin) + at91_set_gpio_output(data->vcc_pin, 0); + + /* CLK */ + at91_set_A_periph(AT91_PIN_PA8, 0); + + if (data->slot_b) { + /* CMD */ + at91_set_B_periph(AT91_PIN_PA1, 1); + + /* DAT0, maybe DAT1..DAT3 */ + at91_set_B_periph(AT91_PIN_PA0, 1); + if (data->wire4) { + at91_set_B_periph(AT91_PIN_PA5, 1); + at91_set_B_periph(AT91_PIN_PA4, 1); + at91_set_B_periph(AT91_PIN_PA3, 1); + } + } else { + /* CMD */ + at91_set_A_periph(AT91_PIN_PA7, 1); + + /* DAT0, maybe DAT1..DAT3 */ + at91_set_A_periph(AT91_PIN_PA6, 1); + if (data->wire4) { + at91_set_A_periph(AT91_PIN_PA9, 1); + at91_set_A_periph(AT91_PIN_PA10, 1); + at91_set_A_periph(AT91_PIN_PA11, 1); + } + } + + mmc_data = *data; + platform_device_register(&at91sam9260_mmc_device); +} +#else +void __init at91_add_device_mmc(struct at91_mmc_data *data) {} +#endif + + +/* -------------------------------------------------------------------- + * NAND / SmartMedia + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE) +static struct at91_nand_data nand_data; + +#define NAND_BASE AT91_CHIPSELECT_3 + +static struct resource nand_resources[] = { + { + .start = NAND_BASE, + .end = NAND_BASE + SZ_8M - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device at91sam9260_nand_device = { + .name = "at91_nand", + .id = -1, + .dev = { + .platform_data = &nand_data, + }, + .resource = nand_resources, + .num_resources = ARRAY_SIZE(nand_resources), +}; + +void __init at91_add_device_nand(struct at91_nand_data *data) +{ + unsigned long csa, mode; + + if (!data) + return; + + csa = at91_sys_read(AT91_MATRIX_EBICSA); + at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC); + + /* set the bus interface characteristics */ + at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) + | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); + + at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5) + | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5)); + + at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7)); + + if (data->bus_width_16) + mode = AT91_SMC_DBW_16; + else + mode = AT91_SMC_DBW_8; + at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1)); + + /* enable pin */ + if (data->enable_pin) + at91_set_gpio_output(data->enable_pin, 1); + + /* ready/busy pin */ + if (data->rdy_pin) + at91_set_gpio_input(data->rdy_pin, 1); + + /* card detect pin */ + if (data->det_pin) + at91_set_gpio_input(data->det_pin, 1); + + nand_data = *data; + platform_device_register(&at91sam9260_nand_device); +} +#else +void __init at91_add_device_nand(struct at91_nand_data *data) {} +#endif + + +/* -------------------------------------------------------------------- + * TWI (i2c) + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE) + +static struct resource twi_resources[] = { + [0] = { + .start = AT91SAM9260_BASE_TWI, + .end = AT91SAM9260_BASE_TWI + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9260_ID_TWI, + .end = AT91SAM9260_ID_TWI, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device at91sam9260_twi_device = { + .name = "at91_i2c", + .id = -1, + .resource = twi_resources, + .num_resources = ARRAY_SIZE(twi_resources), +}; + +void __init at91_add_device_i2c(void) +{ + /* pins used for TWI interface */ + at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */ + at91_set_multi_drive(AT91_PIN_PA23, 1); + + at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */ + at91_set_multi_drive(AT91_PIN_PA24, 1); + + platform_device_register(&at91sam9260_twi_device); +} +#else +void __init at91_add_device_i2c(void) {} +#endif + + +/* -------------------------------------------------------------------- + * SPI + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE) +static u64 spi_dmamask = 0xffffffffUL; + +static struct resource spi0_resources[] = { + [0] = { + .start = AT91SAM9260_BASE_SPI0, + .end = AT91SAM9260_BASE_SPI0 + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9260_ID_SPI0, + .end = AT91SAM9260_ID_SPI0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device at91sam9260_spi0_device = { + .name = "atmel_spi", + .id = 0, + .dev = { + .dma_mask = &spi_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = spi0_resources, + .num_resources = ARRAY_SIZE(spi0_resources), +}; + +static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PC11, AT91_PIN_PC16, AT91_PIN_PC17 }; + +static struct resource spi1_resources[] = { + [0] = { + .start = AT91SAM9260_BASE_SPI1, + .end = AT91SAM9260_BASE_SPI1 + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9260_ID_SPI1, + .end = AT91SAM9260_ID_SPI1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device at91sam9260_spi1_device = { + .name = "atmel_spi", + .id = 1, + .dev = { + .dma_mask = &spi_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = spi1_resources, + .num_resources = ARRAY_SIZE(spi1_resources), +}; + +static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PC5, AT91_PIN_PC4, AT91_PIN_PC3 }; + +void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) +{ + int i; + unsigned long cs_pin; + short enable_spi0 = 0; + short enable_spi1 = 0; + + /* Choose SPI chip-selects */ + for (i = 0; i < nr_devices; i++) { + if (devices[i].controller_data) + cs_pin = (unsigned long) devices[i].controller_data; + else if (devices[i].bus_num == 0) + cs_pin = spi0_standard_cs[devices[i].chip_select]; + else + cs_pin = spi1_standard_cs[devices[i].chip_select]; + + if (devices[i].bus_num == 0) + enable_spi0 = 1; + else + enable_spi1 = 1; + + /* enable chip-select pin */ + at91_set_gpio_output(cs_pin, 1); + + /* pass chip-select pin to driver */ + devices[i].controller_data = (void *) cs_pin; + } + + spi_register_board_info(devices, nr_devices); + + /* Configure SPI bus(es) */ + if (enable_spi0) { + at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ + at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ + at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI1_SPCK */ + + at91_clock_associate("spi0_clk", &at91sam9260_spi0_device.dev, "spi_clk"); + platform_device_register(&at91sam9260_spi0_device); + } + if (enable_spi1) { + at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI1_MISO */ + at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI1_MOSI */ + at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI1_SPCK */ + + at91_clock_associate("spi1_clk", &at91sam9260_spi1_device.dev, "spi_clk"); + platform_device_register(&at91sam9260_spi1_device); + } +} +#else +void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {} +#endif + + +/* -------------------------------------------------------------------- + * LEDs + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_LEDS) +u8 at91_leds_cpu; +u8 at91_leds_timer; + +void __init at91_init_leds(u8 cpu_led, u8 timer_led) +{ + at91_leds_cpu = cpu_led; + at91_leds_timer = timer_led; +} +#else +void __init at91_init_leds(u8 cpu_led, u8 timer_led) {} +#endif + + +/* -------------------------------------------------------------------- + * UART + * -------------------------------------------------------------------- */ +#if defined(CONFIG_SERIAL_ATMEL) +static struct resource dbgu_resources[] = { + [0] = { + .start = AT91_VA_BASE_SYS + AT91_DBGU, + .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91_ID_SYS, + .end = AT91_ID_SYS, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct atmel_uart_data dbgu_data = { + .use_dma_tx = 0, + .use_dma_rx = 0, /* DBGU not capable of receive DMA */ + .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU), +}; + +static struct platform_device at91sam9260_dbgu_device = { + .name = "atmel_usart", + .id = 0, + .dev = { + .platform_data = &dbgu_data, + .coherent_dma_mask = 0xffffffff, + }, + .resource = dbgu_resources, + .num_resources = ARRAY_SIZE(dbgu_resources), +}; + +static inline void configure_dbgu_pins(void) +{ + at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */ + at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */ +} + +static struct resource uart0_resources[] = { + [0] = { + .start = AT91SAM9260_BASE_US0, + .end = AT91SAM9260_BASE_US0 + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9260_ID_US0, + .end = AT91SAM9260_ID_US0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct atmel_uart_data uart0_data = { + .use_dma_tx = 1, + .use_dma_rx = 1, +}; + +static struct platform_device at91sam9260_uart0_device = { + .name = "atmel_usart", + .id = 1, + .dev = { + .platform_data = &uart0_data, + .coherent_dma_mask = 0xffffffff, + }, + .resource = uart0_resources, + .num_resources = ARRAY_SIZE(uart0_resources), +}; + +static inline void configure_usart0_pins(void) +{ + at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */ + at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */ + at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS0 */ + at91_set_A_periph(AT91_PIN_PB27, 0); /* CTS0 */ + at91_set_A_periph(AT91_PIN_PB24, 0); /* DTR0 */ + at91_set_A_periph(AT91_PIN_PB22, 0); /* DSR0 */ + at91_set_A_periph(AT91_PIN_PB23, 0); /* DCD0 */ + at91_set_A_periph(AT91_PIN_PB25, 0); /* RI0 */ +} + +static struct resource uart1_resources[] = { + [0] = { + .start = AT91SAM9260_BASE_US1, + .end = AT91SAM9260_BASE_US1 + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9260_ID_US1, + .end = AT91SAM9260_ID_US1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct atmel_uart_data uart1_data = { + .use_dma_tx = 1, + .use_dma_rx = 1, +}; + +static struct platform_device at91sam9260_uart1_device = { + .name = "atmel_usart", + .id = 2, + .dev = { + .platform_data = &uart1_data, + .coherent_dma_mask = 0xffffffff, + }, + .resource = uart1_resources, + .num_resources = ARRAY_SIZE(uart1_resources), +}; + +static inline void configure_usart1_pins(void) +{ + at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */ + at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */ + at91_set_A_periph(AT91_PIN_PB28, 0); /* RTS1 */ + at91_set_A_periph(AT91_PIN_PB29, 0); /* CTS1 */ +} + +static struct resource uart2_resources[] = { + [0] = { + .start = AT91SAM9260_BASE_US2, + .end = AT91SAM9260_BASE_US2 + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9260_ID_US2, + .end = AT91SAM9260_ID_US2, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct atmel_uart_data uart2_data = { + .use_dma_tx = 1, + .use_dma_rx = 1, +}; + +static struct platform_device at91sam9260_uart2_device = { + .name = "atmel_usart", + .id = 3, + .dev = { + .platform_data = &uart2_data, + .coherent_dma_mask = 0xffffffff, + }, + .resource = uart2_resources, + .num_resources = ARRAY_SIZE(uart2_resources), +}; + +static inline void configure_usart2_pins(void) +{ + at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */ + at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */ +} + +static struct resource uart3_resources[] = { + [0] = { + .start = AT91SAM9260_BASE_US3, + .end = AT91SAM9260_BASE_US3 + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9260_ID_US3, + .end = AT91SAM9260_ID_US3, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct atmel_uart_data uart3_data = { + .use_dma_tx = 1, + .use_dma_rx = 1, +}; + +static struct platform_device at91sam9260_uart3_device = { + .name = "atmel_usart", + .id = 4, + .dev = { + .platform_data = &uart3_data, + .coherent_dma_mask = 0xffffffff, + }, + .resource = uart3_resources, + .num_resources = ARRAY_SIZE(uart3_resources), +}; + +static inline void configure_usart3_pins(void) +{ + at91_set_A_periph(AT91_PIN_PB10, 1); /* TXD3 */ + at91_set_A_periph(AT91_PIN_PB11, 0); /* RXD3 */ +} + +static struct resource uart4_resources[] = { + [0] = { + .start = AT91SAM9260_BASE_US4, + .end = AT91SAM9260_BASE_US4 + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9260_ID_US4, + .end = AT91SAM9260_ID_US4, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct atmel_uart_data uart4_data = { + .use_dma_tx = 1, + .use_dma_rx = 1, +}; + +static struct platform_device at91sam9260_uart4_device = { + .name = "atmel_usart", + .id = 5, + .dev = { + .platform_data = &uart4_data, + .coherent_dma_mask = 0xffffffff, + }, + .resource = uart4_resources, + .num_resources = ARRAY_SIZE(uart4_resources), +}; + +static inline void configure_usart4_pins(void) +{ + at91_set_B_periph(AT91_PIN_PA31, 1); /* TXD4 */ + at91_set_B_periph(AT91_PIN_PA30, 0); /* RXD4 */ +} + +static struct resource uart5_resources[] = { + [0] = { + .start = AT91SAM9260_BASE_US5, + .end = AT91SAM9260_BASE_US5 + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9260_ID_US5, + .end = AT91SAM9260_ID_US5, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct atmel_uart_data uart5_data = { + .use_dma_tx = 1, + .use_dma_rx = 1, +}; + +static struct platform_device at91sam9260_uart5_device = { + .name = "atmel_usart", + .id = 6, + .dev = { + .platform_data = &uart5_data, + .coherent_dma_mask = 0xffffffff, + }, + .resource = uart5_resources, + .num_resources = ARRAY_SIZE(uart5_resources), +}; + +static inline void configure_usart5_pins(void) +{ + at91_set_A_periph(AT91_PIN_PB12, 1); /* TXD5 */ + at91_set_A_periph(AT91_PIN_PB13, 0); /* RXD5 */ +} + +struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ +struct platform_device *atmel_default_console_device; /* the serial console device */ + +void __init at91_init_serial(struct at91_uart_config *config) +{ + int i; + + /* Fill in list of supported UARTs */ + for (i = 0; i < config->nr_tty; i++) { + switch (config->tty_map[i]) { + case 0: + configure_usart0_pins(); + at91_uarts[i] = &at91sam9260_uart0_device; + at91_clock_associate("usart0_clk", &at91sam9260_uart0_device.dev, "usart"); + break; + case 1: + configure_usart1_pins(); + at91_uarts[i] = &at91sam9260_uart1_device; + at91_clock_associate("usart1_clk", &at91sam9260_uart1_device.dev, "usart"); + break; + case 2: + configure_usart2_pins(); + at91_uarts[i] = &at91sam9260_uart2_device; + at91_clock_associate("usart2_clk", &at91sam9260_uart2_device.dev, "usart"); + break; + case 3: + configure_usart3_pins(); + at91_uarts[i] = &at91sam9260_uart3_device; + at91_clock_associate("usart3_clk", &at91sam9260_uart3_device.dev, "usart"); + break; + case 4: + configure_usart4_pins(); + at91_uarts[i] = &at91sam9260_uart4_device; + at91_clock_associate("usart4_clk", &at91sam9260_uart4_device.dev, "usart"); + break; + case 5: + configure_usart5_pins(); + at91_uarts[i] = &at91sam9260_uart5_device; + at91_clock_associate("usart5_clk", &at91sam9260_uart5_device.dev, "usart"); + break; + case 6: + configure_dbgu_pins(); + at91_uarts[i] = &at91sam9260_dbgu_device; + at91_clock_associate("mck", &at91sam9260_dbgu_device.dev, "usart"); + break; + default: + continue; + } + at91_uarts[i]->id = i; /* update ID number to mapped ID */ + } + + /* Set serial console device */ + if (config->console_tty < ATMEL_MAX_UART) + atmel_default_console_device = at91_uarts[config->console_tty]; + if (!atmel_default_console_device) + printk(KERN_INFO "AT91: No default serial console defined.\n"); +} + +void __init at91_add_device_serial(void) +{ + int i; + + for (i = 0; i < ATMEL_MAX_UART; i++) { + if (at91_uarts[i]) + platform_device_register(at91_uarts[i]); + } +} +#else +void __init at91_init_serial(struct at91_uart_config *config) {} +void __init at91_add_device_serial(void) {} +#endif + + +/* -------------------------------------------------------------------- */ +/* + * These devices are always present and don't need any board-specific + * setup. + */ +static int __init at91_add_standard_devices(void) +{ + return 0; +} + +arch_initcall(at91_add_standard_devices); diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c new file mode 100644 index 000000000000..47e02ff7e872 --- /dev/null +++ b/arch/arm/mach-at91/at91sam9261.c @@ -0,0 +1,290 @@ +/* + * arch/arm/mach-at91/at91sam9261.c + * + * Copyright (C) 2005 SAN People + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#include + +#include +#include +#include +#include +#include + +#include "generic.h" +#include "clock.h" + +static struct map_desc at91sam9261_io_desc[] __initdata = { + { + .virtual = AT91_VA_BASE_SYS, + .pfn = __phys_to_pfn(AT91_BASE_SYS), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = AT91_IO_VIRT_BASE - AT91SAM9261_SRAM_SIZE, + .pfn = __phys_to_pfn(AT91SAM9261_SRAM_BASE), + .length = AT91SAM9261_SRAM_SIZE, + .type = MT_DEVICE, + }, +}; + +/* -------------------------------------------------------------------- + * Clocks + * -------------------------------------------------------------------- */ + +/* + * The peripheral clocks. + */ +static struct clk pioA_clk = { + .name = "pioA_clk", + .pmc_mask = 1 << AT91SAM9261_ID_PIOA, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioB_clk = { + .name = "pioB_clk", + .pmc_mask = 1 << AT91SAM9261_ID_PIOB, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioC_clk = { + .name = "pioC_clk", + .pmc_mask = 1 << AT91SAM9261_ID_PIOC, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart0_clk = { + .name = "usart0_clk", + .pmc_mask = 1 << AT91SAM9261_ID_US0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart1_clk = { + .name = "usart1_clk", + .pmc_mask = 1 << AT91SAM9261_ID_US1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart2_clk = { + .name = "usart2_clk", + .pmc_mask = 1 << AT91SAM9261_ID_US2, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk mmc_clk = { + .name = "mci_clk", + .pmc_mask = 1 << AT91SAM9261_ID_MCI, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk udc_clk = { + .name = "udc_clk", + .pmc_mask = 1 << AT91SAM9261_ID_UDP, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk twi_clk = { + .name = "twi_clk", + .pmc_mask = 1 << AT91SAM9261_ID_TWI, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk spi0_clk = { + .name = "spi0_clk", + .pmc_mask = 1 << AT91SAM9261_ID_SPI0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk spi1_clk = { + .name = "spi1_clk", + .pmc_mask = 1 << AT91SAM9261_ID_SPI1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk ohci_clk = { + .name = "ohci_clk", + .pmc_mask = 1 << AT91SAM9261_ID_UHP, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk lcdc_clk = { + .name = "lcdc_clk", + .pmc_mask = 1 << AT91SAM9261_ID_LCDC, + .type = CLK_TYPE_PERIPHERAL, +}; + +static struct clk *periph_clocks[] __initdata = { + &pioA_clk, + &pioB_clk, + &pioC_clk, + &usart0_clk, + &usart1_clk, + &usart2_clk, + &mmc_clk, + &udc_clk, + &twi_clk, + &spi0_clk, + &spi1_clk, + // ssc 0 .. ssc2 + // tc0 .. tc2 + &ohci_clk, + &lcdc_clk, + // irq0 .. irq2 +}; + +/* + * The four programmable clocks. + * You must configure pin multiplexing to bring these signals out. + */ +static struct clk pck0 = { + .name = "pck0", + .pmc_mask = AT91_PMC_PCK0, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 0, +}; +static struct clk pck1 = { + .name = "pck1", + .pmc_mask = AT91_PMC_PCK1, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 1, +}; +static struct clk pck2 = { + .name = "pck2", + .pmc_mask = AT91_PMC_PCK2, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 2, +}; +static struct clk pck3 = { + .name = "pck3", + .pmc_mask = AT91_PMC_PCK3, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 3, +}; + +/* HClocks */ +static struct clk hck0 = { + .name = "hck0", + .pmc_mask = AT91_PMC_HCK0, + .type = CLK_TYPE_SYSTEM, + .id = 0, +}; +static struct clk hck1 = { + .name = "hck1", + .pmc_mask = AT91_PMC_HCK1, + .type = CLK_TYPE_SYSTEM, + .id = 1, +}; + +static void __init at91sam9261_register_clocks(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) + clk_register(periph_clocks[i]); + + clk_register(&pck0); + clk_register(&pck1); + clk_register(&pck2); + clk_register(&pck3); + + clk_register(&hck0); + clk_register(&hck1); +} + +/* -------------------------------------------------------------------- + * GPIO + * -------------------------------------------------------------------- */ + +static struct at91_gpio_bank at91sam9261_gpio[] = { + { + .id = AT91SAM9261_ID_PIOA, + .offset = AT91_PIOA, + .clock = &pioA_clk, + }, { + .id = AT91SAM9261_ID_PIOB, + .offset = AT91_PIOB, + .clock = &pioB_clk, + }, { + .id = AT91SAM9261_ID_PIOC, + .offset = AT91_PIOC, + .clock = &pioC_clk, + } +}; + +static void at91sam9261_reset(void) +{ + at91_sys_write(AT91_RSTC_CR, (0xA5 << 24) | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); +} + + +/* -------------------------------------------------------------------- + * AT91SAM9261 processor initialization + * -------------------------------------------------------------------- */ + +void __init at91sam9261_initialize(unsigned long main_clock) +{ + /* Map peripherals */ + iotable_init(at91sam9261_io_desc, ARRAY_SIZE(at91sam9261_io_desc)); + + at91_arch_reset = at91sam9261_reset; + at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1) + | (1 << AT91SAM9261_ID_IRQ2); + + /* Init clock subsystem */ + at91_clock_init(main_clock); + + /* Register the processor-specific clocks */ + at91sam9261_register_clocks(); + + /* Register GPIO subsystem */ + at91_gpio_init(at91sam9261_gpio, 3); +} + +/* -------------------------------------------------------------------- + * Interrupt initialization + * -------------------------------------------------------------------- */ + +/* + * The default interrupt priority levels (0 = lowest, 7 = highest). + */ +static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = { + 7, /* Advanced Interrupt Controller */ + 7, /* System Peripherals */ + 0, /* Parallel IO Controller A */ + 0, /* Parallel IO Controller B */ + 0, /* Parallel IO Controller C */ + 0, + 6, /* USART 0 */ + 6, /* USART 1 */ + 6, /* USART 2 */ + 0, /* Multimedia Card Interface */ + 4, /* USB Device Port */ + 0, /* Two-Wire Interface */ + 6, /* Serial Peripheral Interface 0 */ + 6, /* Serial Peripheral Interface 1 */ + 5, /* Serial Synchronous Controller 0 */ + 5, /* Serial Synchronous Controller 1 */ + 5, /* Serial Synchronous Controller 2 */ + 0, /* Timer Counter 0 */ + 0, /* Timer Counter 1 */ + 0, /* Timer Counter 2 */ + 3, /* USB Host port */ + 3, /* LCD Controller */ + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, /* Advanced Interrupt Controller */ + 0, /* Advanced Interrupt Controller */ + 0, /* Advanced Interrupt Controller */ +}; + +void __init at91sam9261_init_interrupts(unsigned int priority[NR_AIC_IRQS]) +{ + if (!priority) + priority = at91sam9261_default_irq_priority; + + /* Initialize the AIC interrupt controller */ + at91_aic_init(priority); + + /* Enable GPIO interrupts */ + at91_gpio_irq_setup(); +} diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c new file mode 100644 index 000000000000..3249de08d1f3 --- /dev/null +++ b/arch/arm/mach-at91/at91sam9261_devices.c @@ -0,0 +1,741 @@ +/* + * arch/arm/mach-at91/at91sam9261_devices.c + * + * Copyright (C) 2005 Thibaut VARENE + * Copyright (C) 2005 David Brownell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#include +#include + +#include + +#include +#include +#include +#include +#include + +#include "generic.h" + +#define SZ_512 0x00000200 +#define SZ_256 0x00000100 +#define SZ_16 0x00000010 + +/* -------------------------------------------------------------------- + * USB Host + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) +static u64 ohci_dmamask = 0xffffffffUL; +static struct at91_usbh_data usbh_data; + +static struct resource usbh_resources[] = { + [0] = { + .start = AT91SAM9261_UHP_BASE, + .end = AT91SAM9261_UHP_BASE + SZ_1M - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9261_ID_UHP, + .end = AT91SAM9261_ID_UHP, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device at91sam9261_usbh_device = { + .name = "at91_ohci", + .id = -1, + .dev = { + .dma_mask = &ohci_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &usbh_data, + }, + .resource = usbh_resources, + .num_resources = ARRAY_SIZE(usbh_resources), +}; + +void __init at91_add_device_usbh(struct at91_usbh_data *data) +{ + if (!data) + return; + + usbh_data = *data; + platform_device_register(&at91sam9261_usbh_device); +} +#else +void __init at91_add_device_usbh(struct at91_usbh_data *data) {} +#endif + + +/* -------------------------------------------------------------------- + * USB Device (Gadget) + * -------------------------------------------------------------------- */ + +#ifdef CONFIG_USB_GADGET_AT91 +static struct at91_udc_data udc_data; + +static struct resource udc_resources[] = { + [0] = { + .start = AT91SAM9261_BASE_UDP, + .end = AT91SAM9261_BASE_UDP + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9261_ID_UDP, + .end = AT91SAM9261_ID_UDP, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device at91sam9261_udc_device = { + .name = "at91_udc", + .id = -1, + .dev = { + .platform_data = &udc_data, + }, + .resource = udc_resources, + .num_resources = ARRAY_SIZE(udc_resources), +}; + +void __init at91_add_device_udc(struct at91_udc_data *data) +{ + unsigned long x; + + if (!data) + return; + + if (data->vbus_pin) { + at91_set_gpio_input(data->vbus_pin, 0); + at91_set_deglitch(data->vbus_pin, 1); + } + + /* Pullup pin is handled internally */ + x = at91_sys_read(AT91_MATRIX_USBPUCR); + at91_sys_write(AT91_MATRIX_USBPUCR, x | AT91_MATRIX_USBPUCR_PUON); + + udc_data = *data; + platform_device_register(&at91sam9261_udc_device); +} +#else +void __init at91_add_device_udc(struct at91_udc_data *data) {} +#endif + +/* -------------------------------------------------------------------- + * MMC / SD + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE) +static u64 mmc_dmamask = 0xffffffffUL; +static struct at91_mmc_data mmc_data; + +static struct resource mmc_resources[] = { + [0] = { + .start = AT91SAM9261_BASE_MCI, + .end = AT91SAM9261_BASE_MCI + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9261_ID_MCI, + .end = AT91SAM9261_ID_MCI, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device at91sam9261_mmc_device = { + .name = "at91_mci", + .id = -1, + .dev = { + .dma_mask = &mmc_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &mmc_data, + }, + .resource = mmc_resources, + .num_resources = ARRAY_SIZE(mmc_resources), +}; + +void __init at91_add_device_mmc(struct at91_mmc_data *data) +{ + if (!data) + return; + + /* input/irq */ + if (data->det_pin) { + at91_set_gpio_input(data->det_pin, 1); + at91_set_deglitch(data->det_pin, 1); + } + if (data->wp_pin) + at91_set_gpio_input(data->wp_pin, 1); + if (data->vcc_pin) + at91_set_gpio_output(data->vcc_pin, 0); + + /* CLK */ + at91_set_B_periph(AT91_PIN_PA2, 0); + + /* CMD */ + at91_set_B_periph(AT91_PIN_PA1, 1); + + /* DAT0, maybe DAT1..DAT3 */ + at91_set_B_periph(AT91_PIN_PA0, 1); + if (data->wire4) { + at91_set_B_periph(AT91_PIN_PA4, 1); + at91_set_B_periph(AT91_PIN_PA5, 1); + at91_set_B_periph(AT91_PIN_PA6, 1); + } + + mmc_data = *data; + platform_device_register(&at91sam9261_mmc_device); +} +#else +void __init at91_add_device_mmc(struct at91_mmc_data *data) {} +#endif + + +/* -------------------------------------------------------------------- + * NAND / SmartMedia + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE) +static struct at91_nand_data nand_data; + +#define NAND_BASE AT91_CHIPSELECT_3 + +static struct resource nand_resources[] = { + { + .start = NAND_BASE, + .end = NAND_BASE + SZ_256M - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device at91_nand_device = { + .name = "at91_nand", + .id = -1, + .dev = { + .platform_data = &nand_data, + }, + .resource = nand_resources, + .num_resources = ARRAY_SIZE(nand_resources), +}; + +void __init at91_add_device_nand(struct at91_nand_data *data) +{ + unsigned long csa, mode; + + if (!data) + return; + + csa = at91_sys_read(AT91_MATRIX_EBICSA); + at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC); + + /* set the bus interface characteristics */ + at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) + | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); + + at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5) + | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5)); + + at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7)); + + if (data->bus_width_16) + mode = AT91_SMC_DBW_16; + else + mode = AT91_SMC_DBW_8; + at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1)); + + /* enable pin */ + if (data->enable_pin) + at91_set_gpio_output(data->enable_pin, 1); + + /* ready/busy pin */ + if (data->rdy_pin) + at91_set_gpio_input(data->rdy_pin, 1); + + /* card detect pin */ + if (data->det_pin) + at91_set_gpio_input(data->det_pin, 1); + + at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */ + at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */ + + nand_data = *data; + platform_device_register(&at91_nand_device); +} + +#else +void __init at91_add_device_nand(struct at91_nand_data *data) {} +#endif + + +/* -------------------------------------------------------------------- + * TWI (i2c) + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE) + +static struct resource twi_resources[] = { + [0] = { + .start = AT91SAM9261_BASE_TWI, + .end = AT91SAM9261_BASE_TWI + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9261_ID_TWI, + .end = AT91SAM9261_ID_TWI, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device at91sam9261_twi_device = { + .name = "at91_i2c", + .id = -1, + .resource = twi_resources, + .num_resources = ARRAY_SIZE(twi_resources), +}; + +void __init at91_add_device_i2c(void) +{ + /* pins used for TWI interface */ + at91_set_A_periph(AT91_PIN_PA7, 0); /* TWD */ + at91_set_multi_drive(AT91_PIN_PA7, 1); + + at91_set_A_periph(AT91_PIN_PA8, 0); /* TWCK */ + at91_set_multi_drive(AT91_PIN_PA8, 1); + + platform_device_register(&at91sam9261_twi_device); +} +#else +void __init at91_add_device_i2c(void) {} +#endif + + +/* -------------------------------------------------------------------- + * SPI + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE) +static u64 spi_dmamask = 0xffffffffUL; + +static struct resource spi0_resources[] = { + [0] = { + .start = AT91SAM9261_BASE_SPI0, + .end = AT91SAM9261_BASE_SPI0 + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9261_ID_SPI0, + .end = AT91SAM9261_ID_SPI0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device at91sam9261_spi0_device = { + .name = "atmel_spi", + .id = 0, + .dev = { + .dma_mask = &spi_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = spi0_resources, + .num_resources = ARRAY_SIZE(spi0_resources), +}; + +static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 }; + +static struct resource spi1_resources[] = { + [0] = { + .start = AT91SAM9261_BASE_SPI1, + .end = AT91SAM9261_BASE_SPI1 + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9261_ID_SPI1, + .end = AT91SAM9261_ID_SPI1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device at91sam9261_spi1_device = { + .name = "atmel_spi", + .id = 1, + .dev = { + .dma_mask = &spi_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = spi1_resources, + .num_resources = ARRAY_SIZE(spi1_resources), +}; + +static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB28, AT91_PIN_PA24, AT91_PIN_PA25, AT91_PIN_PA26 }; + +void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) +{ + int i; + unsigned long cs_pin; + short enable_spi0 = 0; + short enable_spi1 = 0; + + /* Choose SPI chip-selects */ + for (i = 0; i < nr_devices; i++) { + if (devices[i].controller_data) + cs_pin = (unsigned long) devices[i].controller_data; + else if (devices[i].bus_num == 0) + cs_pin = spi0_standard_cs[devices[i].chip_select]; + else + cs_pin = spi1_standard_cs[devices[i].chip_select]; + + if (devices[i].bus_num == 0) + enable_spi0 = 1; + else + enable_spi1 = 1; + + /* enable chip-select pin */ + at91_set_gpio_output(cs_pin, 1); + + /* pass chip-select pin to driver */ + devices[i].controller_data = (void *) cs_pin; + } + + spi_register_board_info(devices, nr_devices); + + /* Configure SPI bus(es) */ + if (enable_spi0) { + at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ + at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ + at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ + + at91_clock_associate("spi0_clk", &at91sam9261_spi0_device.dev, "spi_clk"); + platform_device_register(&at91sam9261_spi0_device); + } + if (enable_spi1) { + at91_set_A_periph(AT91_PIN_PB30, 0); /* SPI1_MISO */ + at91_set_A_periph(AT91_PIN_PB31, 0); /* SPI1_MOSI */ + at91_set_A_periph(AT91_PIN_PB29, 0); /* SPI1_SPCK */ + + at91_clock_associate("spi1_clk", &at91sam9261_spi1_device.dev, "spi_clk"); + platform_device_register(&at91sam9261_spi1_device); + } +} +#else +void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {} +#endif + + +/* -------------------------------------------------------------------- + * LCD Controller + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_FB_AT91) || defined(CONFIG_FB_AT91_MODULE) +static u64 lcdc_dmamask = 0xffffffffUL; +static struct at91fb_info lcdc_data; + +static struct resource lcdc_resources[] = { + [0] = { + .start = AT91SAM9261_LCDC_BASE, + .end = AT91SAM9261_LCDC_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9261_ID_LCDC, + .end = AT91SAM9261_ID_LCDC, + .flags = IORESOURCE_IRQ, + }, +#if defined(CONFIG_FB_INTSRAM) + [2] = { + .start = AT91SAM9261_SRAM_BASE, + .end = AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +#endif +}; + +static struct platform_device at91_lcdc_device = { + .name = "at91-fb", + .id = 0, + .dev = { + .dma_mask = &lcdc_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &lcdc_data, + }, + .resource = lcdc_resources, + .num_resources = ARRAY_SIZE(lcdc_resources), +}; + +void __init at91_add_device_lcdc(struct at91fb_info *data) +{ + if (!data) { + return; + } + + at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */ + at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */ + at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */ + at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */ + at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */ + at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */ + at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */ + at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */ + at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */ + at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */ + at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */ + at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */ + at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */ + at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */ + at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */ + at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */ + at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */ + at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */ + at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */ + at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */ + at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */ + at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */ + + lcdc_data = *data; + platform_device_register(&at91_lcdc_device); +} +#else +void __init at91_add_device_lcdc(struct at91fb_info *data) {} +#endif + + +/* -------------------------------------------------------------------- + * LEDs + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_LEDS) +u8 at91_leds_cpu; +u8 at91_leds_timer; + +void __init at91_init_leds(u8 cpu_led, u8 timer_led) +{ + at91_leds_cpu = cpu_led; + at91_leds_timer = timer_led; +} +#else +void __init at91_init_leds(u8 cpu_led, u8 timer_led) {} +#endif + + +/* -------------------------------------------------------------------- + * UART + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_SERIAL_ATMEL) +static struct resource dbgu_resources[] = { + [0] = { + .start = AT91_VA_BASE_SYS + AT91_DBGU, + .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91_ID_SYS, + .end = AT91_ID_SYS, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct atmel_uart_data dbgu_data = { + .use_dma_tx = 0, + .use_dma_rx = 0, /* DBGU not capable of receive DMA */ + .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU), +}; + +static struct platform_device at91sam9261_dbgu_device = { + .name = "atmel_usart", + .id = 0, + .dev = { + .platform_data = &dbgu_data, + .coherent_dma_mask = 0xffffffff, + }, + .resource = dbgu_resources, + .num_resources = ARRAY_SIZE(dbgu_resources), +}; + +static inline void configure_dbgu_pins(void) +{ + at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */ + at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */ +} + +static struct resource uart0_resources[] = { + [0] = { + .start = AT91SAM9261_BASE_US0, + .end = AT91SAM9261_BASE_US0 + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9261_ID_US0, + .end = AT91SAM9261_ID_US0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct atmel_uart_data uart0_data = { + .use_dma_tx = 1, + .use_dma_rx = 1, +}; + +static struct platform_device at91sam9261_uart0_device = { + .name = "atmel_usart", + .id = 1, + .dev = { + .platform_data = &uart0_data, + .coherent_dma_mask = 0xffffffff, + }, + .resource = uart0_resources, + .num_resources = ARRAY_SIZE(uart0_resources), +}; + +static inline void configure_usart0_pins(void) +{ + at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */ + at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */ + at91_set_A_periph(AT91_PIN_PC10, 0); /* RTS0 */ + at91_set_A_periph(AT91_PIN_PC11, 0); /* CTS0 */ +} + +static struct resource uart1_resources[] = { + [0] = { + .start = AT91SAM9261_BASE_US1, + .end = AT91SAM9261_BASE_US1 + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9261_ID_US1, + .end = AT91SAM9261_ID_US1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct atmel_uart_data uart1_data = { + .use_dma_tx = 1, + .use_dma_rx = 1, +}; + +static struct platform_device at91sam9261_uart1_device = { + .name = "atmel_usart", + .id = 2, + .dev = { + .platform_data = &uart1_data, + .coherent_dma_mask = 0xffffffff, + }, + .resource = uart1_resources, + .num_resources = ARRAY_SIZE(uart1_resources), +}; + +static inline void configure_usart1_pins(void) +{ + at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */ + at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */ +} + +static struct resource uart2_resources[] = { + [0] = { + .start = AT91SAM9261_BASE_US2, + .end = AT91SAM9261_BASE_US2 + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9261_ID_US2, + .end = AT91SAM9261_ID_US2, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct atmel_uart_data uart2_data = { + .use_dma_tx = 1, + .use_dma_rx = 1, +}; + +static struct platform_device at91sam9261_uart2_device = { + .name = "atmel_usart", + .id = 3, + .dev = { + .platform_data = &uart2_data, + .coherent_dma_mask = 0xffffffff, + }, + .resource = uart2_resources, + .num_resources = ARRAY_SIZE(uart2_resources), +}; + +static inline void configure_usart2_pins(void) +{ + at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */ + at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */ +} + +struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ +struct platform_device *atmel_default_console_device; /* the serial console device */ + +void __init at91_init_serial(struct at91_uart_config *config) +{ + int i; + + /* Fill in list of supported UARTs */ + for (i = 0; i < config->nr_tty; i++) { + switch (config->tty_map[i]) { + case 0: + configure_usart0_pins(); + at91_uarts[i] = &at91sam9261_uart0_device; + at91_clock_associate("usart0_clk", &at91sam9261_uart0_device.dev, "usart"); + break; + case 1: + configure_usart1_pins(); + at91_uarts[i] = &at91sam9261_uart1_device; + at91_clock_associate("usart1_clk", &at91sam9261_uart1_device.dev, "usart"); + break; + case 2: + configure_usart2_pins(); + at91_uarts[i] = &at91sam9261_uart2_device; + at91_clock_associate("usart2_clk", &at91sam9261_uart2_device.dev, "usart"); + break; + case 3: + configure_dbgu_pins(); + at91_uarts[i] = &at91sam9261_dbgu_device; + at91_clock_associate("mck", &at91sam9261_dbgu_device.dev, "usart"); + break; + default: + continue; + } + at91_uarts[i]->id = i; /* update ID number to mapped ID */ + } + + /* Set serial console device */ + if (config->console_tty < ATMEL_MAX_UART) + atmel_default_console_device = at91_uarts[config->console_tty]; + if (!atmel_default_console_device) + printk(KERN_INFO "AT91: No default serial console defined.\n"); +} + +void __init at91_add_device_serial(void) +{ + int i; + + for (i = 0; i < ATMEL_MAX_UART; i++) { + if (at91_uarts[i]) + platform_device_register(at91_uarts[i]); + } +} +#else +void __init at91_init_serial(struct at91_uart_config *config) {} +void __init at91_add_device_serial(void) {} +#endif + + +/* -------------------------------------------------------------------- */ + +/* + * These devices are always present and don't need any board-specific + * setup. + */ +static int __init at91_add_standard_devices(void) +{ + return 0; +} + +arch_initcall(at91_add_standard_devices); diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c new file mode 100644 index 000000000000..59cbbe1e8161 --- /dev/null +++ b/arch/arm/mach-at91/at91sam926x_time.c @@ -0,0 +1,114 @@ +/* + * linux/arch/arm/mach-at91/at91sam926x_time.c + * + * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France + * Revision 2005 M. Nicolas Diremdjian, ATMEL Rousset, France + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + + +#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV) +#define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20) + +/* + * Returns number of microseconds since last timer interrupt. Note that interrupts + * will have been disabled by do_gettimeofday() + * 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy. + * 'tick' is usecs per jiffy (linux/timex.h). + */ +static unsigned long at91sam926x_gettimeoffset(void) +{ + unsigned long elapsed; + unsigned long t = at91_sys_read(AT91_PIT_PIIR); + + elapsed = (PIT_PICNT(t) * LATCH) + PIT_CPIV(t); /* hardware clock cycles */ + + return (unsigned long)(elapsed * 1000000) / LATCH; +} + +/* + * IRQ handler for the timer. + */ +static irqreturn_t at91sam926x_timer_interrupt(int irq, void *dev_id) +{ + volatile long nr_ticks; + + if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS) { /* This is a shared interrupt */ + write_seqlock(&xtime_lock); + + /* Get number to ticks performed before interrupt and clear PIT interrupt */ + nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); + do { + timer_tick(); + nr_ticks--; + } while (nr_ticks); + + write_sequnlock(&xtime_lock); + return IRQ_HANDLED; + } else + return IRQ_NONE; /* not handled */ +} + +static struct irqaction at91sam926x_timer_irq = { + .name = "at91_tick", + .flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER, + .handler = at91sam926x_timer_interrupt +}; + +void at91sam926x_timer_reset(void) +{ + /* Disable timer */ + at91_sys_write(AT91_PIT_MR, 0); + + /* Clear any pending interrupts */ + (void) at91_sys_read(AT91_PIT_PIVR); + + /* Set Period Interval timer and enable its interrupt */ + at91_sys_write(AT91_PIT_MR, (LATCH & AT91_PIT_PIV) | AT91_PIT_PITIEN | AT91_PIT_PITEN); +} + +/* + * Set up timer interrupt. + */ +void __init at91sam926x_timer_init(void) +{ + /* Initialize and enable the timer */ + at91sam926x_timer_reset(); + + /* Make IRQs happen for the system timer. */ + setup_irq(AT91_ID_SYS, &at91sam926x_timer_irq); +} + +#ifdef CONFIG_PM +static void at91sam926x_timer_suspend(void) +{ + /* Disable timer */ + at91_sys_write(AT91_PIT_MR, 0); +} +#else +#define at91sam926x_timer_suspend NULL +#endif + +struct sys_timer at91sam926x_timer = { + .init = at91sam926x_timer_init, + .offset = at91sam926x_gettimeoffset, + .suspend = at91sam926x_timer_suspend, + .resume = at91sam926x_timer_reset, +}; + diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c new file mode 100644 index 000000000000..2d3d4b6f7b02 --- /dev/null +++ b/arch/arm/mach-at91/board-1arm.c @@ -0,0 +1,102 @@ +/* + * linux/arch/arm/mach-at91/board-1arm.c + * + * Copyright (C) 2005 SAN People + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "generic.h" + + +/* + * Serial port configuration. + * 0 .. 3 = USART0 .. USART3 + * 4 = DBGU + */ +static struct at91_uart_config __initdata onearm_uart_config = { + .console_tty = 0, /* ttyS0 */ + .nr_tty = 3, + .tty_map = { 4, 0, 1, -1, -1 }, /* ttyS0, ..., ttyS4 */ +}; + +static void __init onearm_map_io(void) +{ + /* Initialize processor: 18.432 MHz crystal */ + at91rm9200_initialize(18432000, AT91RM9200_PQFP); + + /* Setup the serial ports and console */ + at91_init_serial(&onearm_uart_config); +} + +static void __init onearm_init_irq(void) +{ + at91rm9200_init_interrupts(NULL); +} + +static struct at91_eth_data __initdata onearm_eth_data = { + .phy_irq_pin = AT91_PIN_PC4, + .is_rmii = 1, +}; + +static struct at91_usbh_data __initdata onearm_usbh_data = { + .ports = 1, +}; + +static struct at91_udc_data __initdata onearm_udc_data = { + .vbus_pin = AT91_PIN_PC2, + .pullup_pin = AT91_PIN_PC3, +}; + +static void __init onearm_board_init(void) +{ + /* Serial */ + at91_add_device_serial(); + /* Ethernet */ + at91_add_device_eth(&onearm_eth_data); + /* USB Host */ + at91_add_device_usbh(&onearm_usbh_data); + /* USB Device */ + at91_add_device_udc(&onearm_udc_data); +} + +MACHINE_START(ONEARM, "Ajeco 1ARM single board computer") + /* Maintainer: Lennert Buytenhek */ + .phys_io = AT91_BASE_SYS, + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, + .boot_params = AT91_SDRAM_BASE + 0x100, + .timer = &at91rm9200_timer, + .map_io = onearm_map_io, + .init_irq = onearm_init_irq, + .init_machine = onearm_board_init, +MACHINE_END diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c new file mode 100644 index 000000000000..a0815322f685 --- /dev/null +++ b/arch/arm/mach-at91/board-carmeva.c @@ -0,0 +1,149 @@ +/* + * linux/arch/arm/mach-at91/board-carmeva.c + * + * Copyright (c) 2005 Peer Georgi + * Conitec Datasystems + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "generic.h" + + +/* + * Serial port configuration. + * 0 .. 3 = USART0 .. USART3 + * 4 = DBGU + */ +static struct at91_uart_config __initdata carmeva_uart_config = { + .console_tty = 0, /* ttyS0 */ + .nr_tty = 2, + .tty_map = { 4, 1, -1, -1, -1 } /* ttyS0, ..., ttyS4 */ +}; + +static void __init carmeva_map_io(void) +{ + /* Initialize processor: 20.000 MHz crystal */ + at91rm9200_initialize(20000000, AT91RM9200_BGA); + + /* Setup the serial ports and console */ + at91_init_serial(&carmeva_uart_config); +} + +static void __init carmeva_init_irq(void) +{ + at91rm9200_init_interrupts(NULL); +} + +static struct at91_eth_data __initdata carmeva_eth_data = { + .phy_irq_pin = AT91_PIN_PC4, + .is_rmii = 1, +}; + +static struct at91_usbh_data __initdata carmeva_usbh_data = { + .ports = 2, +}; + +static struct at91_udc_data __initdata carmeva_udc_data = { + .vbus_pin = AT91_PIN_PD12, + .pullup_pin = AT91_PIN_PD9, +}; + +/* FIXME: user dependend */ +// static struct at91_cf_data __initdata carmeva_cf_data = { +// .det_pin = AT91_PIN_PB0, +// .rst_pin = AT91_PIN_PC5, + // .irq_pin = ... not connected + // .vcc_pin = ... always powered +// }; + +static struct at91_mmc_data __initdata carmeva_mmc_data = { + .slot_b = 0, + .wire4 = 1, + .det_pin = AT91_PIN_PB10, + .wp_pin = AT91_PIN_PC14, +}; + +static struct spi_board_info carmeva_spi_devices[] = { + { /* DataFlash chip */ + .modalias = "mtd_dataflash", + .chip_select = 0, + .max_speed_hz = 10 * 1000 * 1000, + }, + { /* User accessable spi - cs1 (250KHz) */ + .modalias = "spi-cs1", + .chip_select = 1, + .max_speed_hz = 250 * 1000, + }, + { /* User accessable spi - cs2 (1MHz) */ + .modalias = "spi-cs2", + .chip_select = 2, + .max_speed_hz = 1 * 1000 * 1000, + }, + { /* User accessable spi - cs3 (10MHz) */ + .modalias = "spi-cs3", + .chip_select = 3, + .max_speed_hz = 10 * 1000 * 1000, + }, +}; + +static void __init carmeva_board_init(void) +{ + /* Serial */ + at91_add_device_serial(); + /* Ethernet */ + at91_add_device_eth(&carmeva_eth_data); + /* USB Host */ + at91_add_device_usbh(&carmeva_usbh_data); + /* USB Device */ + at91_add_device_udc(&carmeva_udc_data); + /* I2C */ + at91_add_device_i2c(); + /* SPI */ + at91_add_device_spi(carmeva_spi_devices, ARRAY_SIZE(carmeva_spi_devices)); + /* Compact Flash */ +// at91_add_device_cf(&carmeva_cf_data); + /* MMC */ + at91_add_device_mmc(&carmeva_mmc_data); +} + +MACHINE_START(CARMEVA, "Carmeva") + /* Maintainer: Conitec Datasystems */ + .phys_io = AT91_BASE_SYS, + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, + .boot_params = AT91_SDRAM_BASE + 0x100, + .timer = &at91rm9200_timer, + .map_io = carmeva_map_io, + .init_irq = carmeva_init_irq, + .init_machine = carmeva_board_init, +MACHINE_END diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c new file mode 100644 index 000000000000..45d6d9b8f5e9 --- /dev/null +++ b/arch/arm/mach-at91/board-csb337.c @@ -0,0 +1,145 @@ +/* + * linux/arch/arm/mach-at91/board-csb337.c + * + * Copyright (C) 2005 SAN People + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "generic.h" + + +/* + * Serial port configuration. + * 0 .. 3 = USART0 .. USART3 + * 4 = DBGU + */ +static struct at91_uart_config __initdata csb337_uart_config = { + .console_tty = 0, /* ttyS0 */ + .nr_tty = 2, + .tty_map = { 4, 1, -1, -1, -1 } /* ttyS0, ..., ttyS4 */ +}; + +static void __init csb337_map_io(void) +{ + /* Initialize processor: 3.6864 MHz crystal */ + at91rm9200_initialize(3686400, AT91RM9200_BGA); + + /* Setup the LEDs */ + at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1); + + /* Setup the serial ports and console */ + at91_init_serial(&csb337_uart_config); +} + +static void __init csb337_init_irq(void) +{ + at91rm9200_init_interrupts(NULL); +} + +static struct at91_eth_data __initdata csb337_eth_data = { + .phy_irq_pin = AT91_PIN_PC2, + .is_rmii = 0, +}; + +static struct at91_usbh_data __initdata csb337_usbh_data = { + .ports = 2, +}; + +static struct at91_udc_data __initdata csb337_udc_data = { + // this has no VBUS sensing pin + .pullup_pin = AT91_PIN_PA24, +}; + +static struct at91_cf_data __initdata csb337_cf_data = { + /* + * connector P4 on the CSB 337 mates to + * connector P8 on the CSB 300CF + */ + + /* CSB337 specific */ + .det_pin = AT91_PIN_PC3, + + /* CSB300CF specific */ + .irq_pin = AT91_PIN_PA19, + .vcc_pin = AT91_PIN_PD0, + .rst_pin = AT91_PIN_PD2, +}; + +static struct at91_mmc_data __initdata csb337_mmc_data = { + .det_pin = AT91_PIN_PD5, + .slot_b = 0, + .wire4 = 1, + .wp_pin = AT91_PIN_PD6, +}; + +static struct spi_board_info csb337_spi_devices[] = { + { /* CAN controller */ + .modalias = "sak82c900", + .chip_select = 0, + .max_speed_hz = 6 * 1000 * 1000, + }, +}; + +static void __init csb337_board_init(void) +{ + /* Serial */ + at91_add_device_serial(); + /* Ethernet */ + at91_add_device_eth(&csb337_eth_data); + /* USB Host */ + at91_add_device_usbh(&csb337_usbh_data); + /* USB Device */ + at91_add_device_udc(&csb337_udc_data); + /* I2C */ + at91_add_device_i2c(); + /* Compact Flash */ + at91_set_gpio_input(AT91_PIN_PB22, 1); /* IOIS16 */ + at91_add_device_cf(&csb337_cf_data); + /* SPI */ + at91_add_device_spi(csb337_spi_devices, ARRAY_SIZE(csb337_spi_devices)); + /* MMC */ + at91_add_device_mmc(&csb337_mmc_data); +} + +MACHINE_START(CSB337, "Cogent CSB337") + /* Maintainer: Bill Gatliff */ + .phys_io = AT91_BASE_SYS, + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, + .boot_params = AT91_SDRAM_BASE + 0x100, + .timer = &at91rm9200_timer, + .map_io = csb337_map_io, + .init_irq = csb337_init_irq, + .init_machine = csb337_board_init, +MACHINE_END diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c new file mode 100644 index 000000000000..774609479c74 --- /dev/null +++ b/arch/arm/mach-at91/board-csb637.c @@ -0,0 +1,109 @@ +/* + * linux/arch/arm/mach-at91/board-csb637.c + * + * Copyright (C) 2005 SAN People + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "generic.h" + + +/* + * Serial port configuration. + * 0 .. 3 = USART0 .. USART3 + * 4 = DBGU + */ +static struct at91_uart_config __initdata csb637_uart_config = { + .console_tty = 0, /* ttyS0 */ + .nr_tty = 2, + .tty_map = { 4, 1, -1, -1, -1 } /* ttyS0, ..., ttyS4 */ +}; + +static void __init csb637_map_io(void) +{ + /* Initialize processor: 3.6864 MHz crystal */ + at91rm9200_initialize(3686400, AT91RM9200_BGA); + + /* Setup the LEDs */ + at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2); + + /* Setup the serial ports and console */ + at91_init_serial(&csb637_uart_config); +} + +static void __init csb637_init_irq(void) +{ + at91rm9200_init_interrupts(NULL); +} + +static struct at91_eth_data __initdata csb637_eth_data = { + .phy_irq_pin = AT91_PIN_PC0, + .is_rmii = 0, +}; + +static struct at91_usbh_data __initdata csb637_usbh_data = { + .ports = 2, +}; + +static struct at91_udc_data __initdata csb637_udc_data = { + .vbus_pin = AT91_PIN_PB28, + .pullup_pin = AT91_PIN_PB1, +}; + +static void __init csb637_board_init(void) +{ + /* Serial */ + at91_add_device_serial(); + /* Ethernet */ + at91_add_device_eth(&csb637_eth_data); + /* USB Host */ + at91_add_device_usbh(&csb637_usbh_data); + /* USB Device */ + at91_add_device_udc(&csb637_udc_data); + /* I2C */ + at91_add_device_i2c(); + /* SPI */ + at91_add_device_spi(NULL, 0); +} + +MACHINE_START(CSB637, "Cogent CSB637") + /* Maintainer: Bill Gatliff */ + .phys_io = AT91_BASE_SYS, + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, + .boot_params = AT91_SDRAM_BASE + 0x100, + .timer = &at91rm9200_timer, + .map_io = csb637_map_io, + .init_irq = csb637_init_irq, + .init_machine = csb637_board_init, +MACHINE_END diff --git a/arch/arm/mach-at91/board-dk.c b/arch/arm/mach-at91/board-dk.c new file mode 100644 index 000000000000..7401dbe1b474 --- /dev/null +++ b/arch/arm/mach-at91/board-dk.c @@ -0,0 +1,216 @@ +/* + * linux/arch/arm/mach-at91/board-dk.c + * + * Copyright (C) 2005 SAN People + * + * Epson S1D framebuffer glue code is: + * Copyright (C) 2005 Thibaut VARENE + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "generic.h" + + +/* + * Serial port configuration. + * 0 .. 3 = USART0 .. USART3 + * 4 = DBGU + */ +static struct at91_uart_config __initdata dk_uart_config = { + .console_tty = 0, /* ttyS0 */ + .nr_tty = 2, + .tty_map = { 4, 1, -1, -1, -1 } /* ttyS0, ..., ttyS4 */ +}; + +static void __init dk_map_io(void) +{ + /* Initialize processor: 18.432 MHz crystal */ + at91rm9200_initialize(18432000, AT91RM9200_BGA); + + /* Setup the LEDs */ + at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2); + + /* Setup the serial ports and console */ + at91_init_serial(&dk_uart_config); +} + +static void __init dk_init_irq(void) +{ + at91rm9200_init_interrupts(NULL); +} + +static struct at91_eth_data __initdata dk_eth_data = { + .phy_irq_pin = AT91_PIN_PC4, + .is_rmii = 1, +}; + +static struct at91_usbh_data __initdata dk_usbh_data = { + .ports = 2, +}; + +static struct at91_udc_data __initdata dk_udc_data = { + .vbus_pin = AT91_PIN_PD4, + .pullup_pin = AT91_PIN_PD5, +}; + +static struct at91_cf_data __initdata dk_cf_data = { + .det_pin = AT91_PIN_PB0, + .rst_pin = AT91_PIN_PC5, + // .irq_pin = ... not connected + // .vcc_pin = ... always powered +}; + +static struct at91_mmc_data __initdata dk_mmc_data = { + .slot_b = 0, + .wire4 = 1, +}; + +static struct spi_board_info dk_spi_devices[] = { + { /* DataFlash chip */ + .modalias = "mtd_dataflash", + .chip_select = 0, + .max_speed_hz = 15 * 1000 * 1000, + }, + { /* UR6HCPS2-SP40 PS2-to-SPI adapter */ + .modalias = "ur6hcps2", + .chip_select = 1, + .max_speed_hz = 250 * 1000, + }, + { /* TLV1504 ADC, 4 channels, 10 bits; one is a temp sensor */ + .modalias = "tlv1504", + .chip_select = 2, + .max_speed_hz = 20 * 1000 * 1000, + }, +#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD + { /* DataFlash card */ + .modalias = "mtd_dataflash", + .chip_select = 3, + .max_speed_hz = 15 * 1000 * 1000, + } +#endif +}; + +static struct mtd_partition __initdata dk_nand_partition[] = { + { + .name = "NAND Partition 1", + .offset = 0, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct mtd_partition *nand_partitions(int size, int *num_partitions) +{ + *num_partitions = ARRAY_SIZE(dk_nand_partition); + return dk_nand_partition; +} + +static struct at91_nand_data __initdata dk_nand_data = { + .ale = 22, + .cle = 21, + .det_pin = AT91_PIN_PB1, + .rdy_pin = AT91_PIN_PC2, + // .enable_pin = ... not there + .partition_info = nand_partitions, +}; + +#define DK_FLASH_BASE AT91_CHIPSELECT_0 +#define DK_FLASH_SIZE 0x200000 + +static struct physmap_flash_data dk_flash_data = { + .width = 2, +}; + +static struct resource dk_flash_resource = { + .start = DK_FLASH_BASE, + .end = DK_FLASH_BASE + DK_FLASH_SIZE - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device dk_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &dk_flash_data, + }, + .resource = &dk_flash_resource, + .num_resources = 1, +}; + + +static void __init dk_board_init(void) +{ + /* Serial */ + at91_add_device_serial(); + /* Ethernet */ + at91_add_device_eth(&dk_eth_data); + /* USB Host */ + at91_add_device_usbh(&dk_usbh_data); + /* USB Device */ + at91_add_device_udc(&dk_udc_data); + at91_set_multi_drive(dk_udc_data.pullup_pin, 1); /* pullup_pin is connected to reset */ + /* Compact Flash */ + at91_add_device_cf(&dk_cf_data); + /* I2C */ + at91_add_device_i2c(); + /* SPI */ + at91_add_device_spi(dk_spi_devices, ARRAY_SIZE(dk_spi_devices)); +#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD + /* DataFlash card */ + at91_set_gpio_output(AT91_PIN_PB7, 0); +#else + /* MMC */ + at91_set_gpio_output(AT91_PIN_PB7, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */ + at91_add_device_mmc(&dk_mmc_data); +#endif + /* NAND */ + at91_add_device_nand(&dk_nand_data); + /* NOR Flash */ + platform_device_register(&dk_flash); + /* VGA */ +// dk_add_device_video(); +} + +MACHINE_START(AT91RM9200DK, "Atmel AT91RM9200-DK") + /* Maintainer: SAN People/Atmel */ + .phys_io = AT91_BASE_SYS, + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, + .boot_params = AT91_SDRAM_BASE + 0x100, + .timer = &at91rm9200_timer, + .map_io = dk_map_io, + .init_irq = dk_init_irq, + .init_machine = dk_board_init, +MACHINE_END diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c new file mode 100644 index 000000000000..56d5ef63e04e --- /dev/null +++ b/arch/arm/mach-at91/board-eb9200.c @@ -0,0 +1,123 @@ +/* + * linux/arch/arm/mach-at91/board-eb9200.c + * + * Copyright (C) 2005 SAN People, adapted for ATEB9200 from Embest + * by Andrew Patrikalakis + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "generic.h" + + +/* + * Serial port configuration. + * 0 .. 3 = USART0 .. USART3 + * 4 = DBGU + */ +static struct at91_uart_config __initdata eb9200_uart_config = { + .console_tty = 0, /* ttyS0 */ + .nr_tty = 2, + .tty_map = { 4, 1, -1, -1, -1 } /* ttyS0, ..., ttyS4 */ +}; + +static void __init eb9200_map_io(void) +{ + /* Initialize processor: 18.432 MHz crystal */ + at91rm9200_initialize(18432000, AT91RM9200_BGA); + + /* Setup the serial ports and console */ + at91_init_serial(&eb9200_uart_config); +} + +static void __init eb9200_init_irq(void) +{ + at91rm9200_init_interrupts(NULL); +} + +static struct at91_eth_data __initdata eb9200_eth_data = { + .phy_irq_pin = AT91_PIN_PC4, + .is_rmii = 1, +}; + +static struct at91_usbh_data __initdata eb9200_usbh_data = { + .ports = 2, +}; + +static struct at91_udc_data __initdata eb9200_udc_data = { + .vbus_pin = AT91_PIN_PD4, + .pullup_pin = AT91_PIN_PD5, +}; + +static struct at91_cf_data __initdata eb9200_cf_data = { + .det_pin = AT91_PIN_PB0, + .rst_pin = AT91_PIN_PC5, + // .irq_pin = ... not connected + // .vcc_pin = ... always powered +}; + +static struct at91_mmc_data __initdata eb9200_mmc_data = { + .slot_b = 0, + .wire4 = 1, +}; + +static void __init eb9200_board_init(void) +{ + /* Serial */ + at91_add_device_serial(); + /* Ethernet */ + at91_add_device_eth(&eb9200_eth_data); + /* USB Host */ + at91_add_device_usbh(&eb9200_usbh_data); + /* USB Device */ + at91_add_device_udc(&eb9200_udc_data); + /* I2C */ + at91_add_device_i2c(); + /* Compact Flash */ + at91_add_device_cf(&eb9200_cf_data); + /* SPI */ + at91_add_device_spi(NULL, 0); + /* MMC */ + /* only supports 1 or 4 bit interface, not wired through to SPI */ + at91_add_device_mmc(&eb9200_mmc_data); +} + +MACHINE_START(ATEB9200, "Embest ATEB9200") + .phys_io = AT91_BASE_SYS, + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, + .boot_params = AT91_SDRAM_BASE + 0x100, + .timer = &at91rm9200_timer, + .map_io = eb9200_map_io, + .init_irq = eb9200_init_irq, + .init_machine = eb9200_board_init, +MACHINE_END diff --git a/arch/arm/mach-at91/board-ek.c b/arch/arm/mach-at91/board-ek.c new file mode 100644 index 000000000000..0f589dd7d1a9 --- /dev/null +++ b/arch/arm/mach-at91/board-ek.c @@ -0,0 +1,174 @@ +/* + * linux/arch/arm/mach-at91/board-ek.c + * + * Copyright (C) 2005 SAN People + * + * Epson S1D framebuffer glue code is: + * Copyright (C) 2005 Thibaut VARENE + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "generic.h" + + +/* + * Serial port configuration. + * 0 .. 3 = USART0 .. USART3 + * 4 = DBGU + */ +static struct at91_uart_config __initdata ek_uart_config = { + .console_tty = 0, /* ttyS0 */ + .nr_tty = 2, + .tty_map = { 4, 1, -1, -1, -1 } /* ttyS0, ..., ttyS4 */ +}; + +static void __init ek_map_io(void) +{ + /* Initialize processor: 18.432 MHz crystal */ + at91rm9200_initialize(18432000, AT91RM9200_BGA); + + /* Setup the LEDs */ + at91_init_leds(AT91_PIN_PB1, AT91_PIN_PB2); + + /* Setup the serial ports and console */ + at91_init_serial(&ek_uart_config); +} + +static void __init ek_init_irq(void) +{ + at91rm9200_init_interrupts(NULL); +} + +static struct at91_eth_data __initdata ek_eth_data = { + .phy_irq_pin = AT91_PIN_PC4, + .is_rmii = 1, +}; + +static struct at91_usbh_data __initdata ek_usbh_data = { + .ports = 2, +}; + +static struct at91_udc_data __initdata ek_udc_data = { + .vbus_pin = AT91_PIN_PD4, + .pullup_pin = AT91_PIN_PD5, +}; + +static struct at91_mmc_data __initdata ek_mmc_data = { + .det_pin = AT91_PIN_PB27, + .slot_b = 0, + .wire4 = 1, + .wp_pin = AT91_PIN_PA17, +}; + +static struct spi_board_info ek_spi_devices[] = { + { /* DataFlash chip */ + .modalias = "mtd_dataflash", + .chip_select = 0, + .max_speed_hz = 15 * 1000 * 1000, + }, +#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD + { /* DataFlash card */ + .modalias = "mtd_dataflash", + .chip_select = 3, + .max_speed_hz = 15 * 1000 * 1000, + }, +#endif +}; + +#define EK_FLASH_BASE AT91_CHIPSELECT_0 +#define EK_FLASH_SIZE 0x200000 + +static struct physmap_flash_data ek_flash_data = { + .width = 2, +}; + +static struct resource ek_flash_resource = { + .start = EK_FLASH_BASE, + .end = EK_FLASH_BASE + EK_FLASH_SIZE - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device ek_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &ek_flash_data, + }, + .resource = &ek_flash_resource, + .num_resources = 1, +}; + + +static void __init ek_board_init(void) +{ + /* Serial */ + at91_add_device_serial(); + /* Ethernet */ + at91_add_device_eth(&ek_eth_data); + /* USB Host */ + at91_add_device_usbh(&ek_usbh_data); + /* USB Device */ + at91_add_device_udc(&ek_udc_data); + at91_set_multi_drive(ek_udc_data.pullup_pin, 1); /* pullup_pin is connected to reset */ + /* I2C */ + at91_add_device_i2c(); + /* SPI */ + at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); +#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD + /* DataFlash card */ + at91_set_gpio_output(AT91_PIN_PB22, 0); +#else + /* MMC */ + at91_set_gpio_output(AT91_PIN_PB22, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */ + at91_add_device_mmc(&ek_mmc_data); +#endif + /* NOR Flash */ + platform_device_register(&ek_flash); + /* VGA */ +// ek_add_device_video(); +} + +MACHINE_START(AT91RM9200EK, "Atmel AT91RM9200-EK") + /* Maintainer: SAN People/Atmel */ + .phys_io = AT91_BASE_SYS, + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, + .boot_params = AT91_SDRAM_BASE + 0x100, + .timer = &at91rm9200_timer, + .map_io = ek_map_io, + .init_irq = ek_init_irq, + .init_machine = ek_board_init, +MACHINE_END diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c new file mode 100644 index 000000000000..c77d84ce9cae --- /dev/null +++ b/arch/arm/mach-at91/board-kafa.c @@ -0,0 +1,109 @@ +/* + * linux/arch/arm/mach-at91/board-kafa.c + * + * Copyright (C) 2006 Sperry-Sun + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "generic.h" + + +/* + * Serial port configuration. + * 0 .. 3 = USART0 .. USART3 + * 4 = DBGU + */ +static struct at91_uart_config __initdata kafa_uart_config = { + .console_tty = 0, /* ttyS0 */ + .nr_tty = 2, + .tty_map = { 4, 0, -1, -1, -1 } /* ttyS0, ..., ttyS4 */ +}; + +static void __init kafa_map_io(void) +{ + /* Initialize processor: 18.432 MHz crystal */ + at91rm9200_initialize(18432000, AT91RM9200_PQFP); + + /* Set up the LEDs */ + at91_init_leds(AT91_PIN_PB4, AT91_PIN_PB4); + + /* Setup the serial ports and console */ + at91_init_serial(&kafa_uart_config); +} + +static void __init kafa_init_irq(void) +{ + at91rm9200_init_interrupts(NULL); +} + +static struct at91_eth_data __initdata kafa_eth_data = { + .phy_irq_pin = AT91_PIN_PC4, + .is_rmii = 0, +}; + +static struct at91_usbh_data __initdata kafa_usbh_data = { + .ports = 1, +}; + +static struct at91_udc_data __initdata kafa_udc_data = { + .vbus_pin = AT91_PIN_PB6, + .pullup_pin = AT91_PIN_PB7, +}; + +static void __init kafa_board_init(void) +{ + /* Serial */ + at91_add_device_serial(); + /* Ethernet */ + at91_add_device_eth(&kafa_eth_data); + /* USB Host */ + at91_add_device_usbh(&kafa_usbh_data); + /* USB Device */ + at91_add_device_udc(&kafa_udc_data); + /* I2C */ + at91_add_device_i2c(); + /* SPI */ + at91_add_device_spi(NULL, 0); +} + +MACHINE_START(KAFA, "Sperry-Sun KAFA") + /* Maintainer: Sergei Sharonov */ + .phys_io = AT91_BASE_SYS, + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, + .boot_params = AT91_SDRAM_BASE + 0x100, + .timer = &at91rm9200_timer, + .map_io = kafa_map_io, + .init_irq = kafa_init_irq, + .init_machine = kafa_board_init, +MACHINE_END diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c new file mode 100644 index 000000000000..17e68f5efb13 --- /dev/null +++ b/arch/arm/mach-at91/board-kb9202.c @@ -0,0 +1,143 @@ +/* + * linux/arch/arm/mach-at91/board-kb9202.c + * + * Copyright (c) 2005 kb_admin + * KwikByte, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "generic.h" + + +/* + * Serial port configuration. + * 0 .. 3 = USART0 .. USART3 + * 4 = DBGU + */ +static struct at91_uart_config __initdata kb9202_uart_config = { + .console_tty = 0, /* ttyS0 */ + .nr_tty = 3, + .tty_map = { 4, 0, 1, -1, -1 } /* ttyS0, ..., ttyS4 */ +}; + +static void __init kb9202_map_io(void) +{ + /* Initialize processor: 10 MHz crystal */ + at91rm9200_initialize(10000000, AT91RM9200_PQFP); + + /* Set up the LEDs */ + at91_init_leds(AT91_PIN_PC19, AT91_PIN_PC18); + + /* Setup the serial ports and console */ + at91_init_serial(&kb9202_uart_config); +} + +static void __init kb9202_init_irq(void) +{ + at91rm9200_init_interrupts(NULL); +} + +static struct at91_eth_data __initdata kb9202_eth_data = { + .phy_irq_pin = AT91_PIN_PB29, + .is_rmii = 0, +}; + +static struct at91_usbh_data __initdata kb9202_usbh_data = { + .ports = 1, +}; + +static struct at91_udc_data __initdata kb9202_udc_data = { + .vbus_pin = AT91_PIN_PB24, + .pullup_pin = AT91_PIN_PB22, +}; + +static struct at91_mmc_data __initdata kb9202_mmc_data = { + .det_pin = AT91_PIN_PB2, + .slot_b = 0, + .wire4 = 1, +}; + +static struct mtd_partition __initdata kb9202_nand_partition[] = { + { + .name = "nand_fs", + .offset = 0, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct mtd_partition *nand_partitions(int size, int *num_partitions) +{ + *num_partitions = ARRAY_SIZE(kb9202_nand_partition); + return kb9202_nand_partition; +} + +static struct at91_nand_data __initdata kb9202_nand_data = { + .ale = 22, + .cle = 21, + // .det_pin = ... not there + .rdy_pin = AT91_PIN_PC29, + .enable_pin = AT91_PIN_PC28, + .partition_info = nand_partitions, +}; + +static void __init kb9202_board_init(void) +{ + /* Serial */ + at91_add_device_serial(); + /* Ethernet */ + at91_add_device_eth(&kb9202_eth_data); + /* USB Host */ + at91_add_device_usbh(&kb9202_usbh_data); + /* USB Device */ + at91_add_device_udc(&kb9202_udc_data); + /* MMC */ + at91_add_device_mmc(&kb9202_mmc_data); + /* I2C */ + at91_add_device_i2c(); + /* SPI */ + at91_add_device_spi(NULL, 0); + /* NAND */ + at91_add_device_nand(&kb9202_nand_data); +} + +MACHINE_START(KB9200, "KB920x") + /* Maintainer: KwikByte, Inc. */ + .phys_io = AT91_BASE_SYS, + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, + .boot_params = AT91_SDRAM_BASE + 0x100, + .timer = &at91rm9200_timer, + .map_io = kb9202_map_io, + .init_irq = kb9202_init_irq, + .init_machine = kb9202_board_init, +MACHINE_END diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c new file mode 100644 index 000000000000..6ae272d224e5 --- /dev/null +++ b/arch/arm/mach-at91/board-sam9260ek.c @@ -0,0 +1,202 @@ +/* + * linux/arch/arm/mach-at91/board-ek.c + * + * Copyright (C) 2005 SAN People + * Copyright (C) 2006 Atmel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "generic.h" + + +/* + * Serial port configuration. + * 0 .. 5 = USART0 .. USART5 + * 6 = DBGU + */ +static struct at91_uart_config __initdata ek_uart_config = { + .console_tty = 0, /* ttyS0 */ + .nr_tty = 3, + .tty_map = { 6, 0, 1, -1, -1, -1, -1 } /* ttyS0, ..., ttyS6 */ +}; + +static void __init ek_map_io(void) +{ + /* Initialize processor: 18.432 MHz crystal */ + at91sam9260_initialize(18432000); + + /* Setup the serial ports and console */ + at91_init_serial(&ek_uart_config); +} + +static void __init ek_init_irq(void) +{ + at91sam9260_init_interrupts(NULL); +} + + +/* + * USB Host port + */ +static struct at91_usbh_data __initdata ek_usbh_data = { + .ports = 2, +}; + +/* + * USB Device port + */ +static struct at91_udc_data __initdata ek_udc_data = { + .vbus_pin = AT91_PIN_PC5, + .pullup_pin = 0, /* pull-up driven by UDC */ +}; + + +/* + * SPI devices. + */ +static struct spi_board_info ek_spi_devices[] = { +#if !defined(CONFIG_MMC_AT91) + { /* DataFlash chip */ + .modalias = "mtd_dataflash", + .chip_select = 1, + .max_speed_hz = 15 * 1000 * 1000, + .bus_num = 0, + }, +#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD) + { /* DataFlash card */ + .modalias = "mtd_dataflash", + .chip_select = 0, + .max_speed_hz = 15 * 1000 * 1000, + .bus_num = 0, + }, +#endif +#endif +#if defined(CONFIG_SND_AT73C213) + { /* AT73C213 DAC */ + .modalias = "snd_at73c213", + .chip_select = 0, + .max_speed_hz = 10 * 1000 * 1000, + .bus_num = 1, + }, +#endif +}; + + +/* + * MACB Ethernet device + */ +static struct __initdata at91_eth_data ek_macb_data = { + .phy_irq_pin = AT91_PIN_PA7, + .is_rmii = 1, +}; + + +/* + * NAND flash + */ +static struct mtd_partition __initdata ek_nand_partition[] = { + { + .name = "Partition 1", + .offset = 0, + .size = 256 * 1024, + }, + { + .name = "Partition 2", + .offset = 256 * 1024, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct mtd_partition *nand_partitions(int size, int *num_partitions) +{ + *num_partitions = ARRAY_SIZE(ek_nand_partition); + return ek_nand_partition; +} + +static struct at91_nand_data __initdata ek_nand_data = { + .ale = 21, + .cle = 22, +// .det_pin = ... not connected + .rdy_pin = AT91_PIN_PC13, + .enable_pin = AT91_PIN_PC14, + .partition_info = nand_partitions, +#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16) + .bus_width_16 = 1, +#else + .bus_width_16 = 0, +#endif +}; + + +/* + * MCI (SD/MMC) + */ +static struct at91_mmc_data __initdata ek_mmc_data = { + .slot_b = 1, + .wire4 = 1, +// .det_pin = ... not connected +// .wp_pin = ... not connected +// .vcc_pin = ... not connected +}; + +static void __init ek_board_init(void) +{ + /* Serial */ + at91_add_device_serial(); + /* USB Host */ + at91_add_device_usbh(&ek_usbh_data); + /* USB Device */ + at91_add_device_udc(&ek_udc_data); + /* SPI */ + at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); + /* NAND */ + at91_add_device_nand(&ek_nand_data); + /* Ethernet */ + at91_add_device_eth(&ek_macb_data); + /* MMC */ + at91_add_device_mmc(&ek_mmc_data); +} + +MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK") + /* Maintainer: Atmel */ + .phys_io = AT91_BASE_SYS, + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, + .boot_params = AT91_SDRAM_BASE + 0x100, + .timer = &at91sam926x_timer, + .map_io = ek_map_io, + .init_irq = ek_init_irq, + .init_machine = ek_board_init, +MACHINE_END diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c new file mode 100644 index 000000000000..25d626348e6d --- /dev/null +++ b/arch/arm/mach-at91/board-sam9261ek.c @@ -0,0 +1,259 @@ +/* + * linux/arch/arm/mach-at91/board-ek.c + * + * Copyright (C) 2005 SAN People + * Copyright (C) 2006 Atmel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "generic.h" + + +/* + * Serial port configuration. + * 0 .. 2 = USART0 .. USART2 + * 3 = DBGU + */ +static struct at91_uart_config __initdata ek_uart_config = { + .console_tty = 0, /* ttyS0 */ + .nr_tty = 1, + .tty_map = { 3, -1, -1, -1 } /* ttyS0, ..., ttyS3 */ +}; + +static void __init ek_map_io(void) +{ + /* Initialize processor: 18.432 MHz crystal */ + at91sam9261_initialize(18432000); + + /* Setup the serial ports and console */ + at91_init_serial(&ek_uart_config); +} + +static void __init ek_init_irq(void) +{ + at91sam9261_init_interrupts(NULL); +} + + +/* + * DM9000 ethernet device + */ +#if defined(CONFIG_DM9000) +static struct resource at91sam9261_dm9000_resource[] = { + [0] = { + .start = AT91_CHIPSELECT_2, + .end = AT91_CHIPSELECT_2 + 3, + .flags = IORESOURCE_MEM + }, + [1] = { + .start = AT91_CHIPSELECT_2 + 0x44, + .end = AT91_CHIPSELECT_2 + 0xFF, + .flags = IORESOURCE_MEM + }, + [2] = { + .start = AT91_PIN_PC11, + .end = AT91_PIN_PC11, + .flags = IORESOURCE_IRQ + } +}; + +static struct dm9000_plat_data dm9000_platdata = { + .flags = DM9000_PLATF_16BITONLY, +}; + +static struct platform_device at91sam9261_dm9000_device = { + .name = "dm9000", + .id = 0, + .num_resources = ARRAY_SIZE(at91sam9261_dm9000_resource), + .resource = at91sam9261_dm9000_resource, + .dev = { + .platform_data = &dm9000_platdata, + } +}; + +static void __init ek_add_device_dm9000(void) +{ + /* + * Configure Chip-Select 2 on SMC for the DM9000. + * Note: These timings were calculated for MASTER_CLOCK = 100000000 + * according to the DM9000 timings. + */ + at91_sys_write(AT91_SMC_SETUP(2), AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC_PULSE(2), AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) | AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8)); + at91_sys_write(AT91_SMC_CYCLE(2), AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16)); + at91_sys_write(AT91_SMC_MODE(2), AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | AT91_SMC_TDF_(1)); + + /* Configure Reset signal as output */ + at91_set_gpio_output(AT91_PIN_PC10, 0); + + /* Configure Interrupt pin as input, no pull-up */ + at91_set_gpio_input(AT91_PIN_PC11, 0); + + platform_device_register(&at91sam9261_dm9000_device); +} +#else +static void __init ek_add_device_dm9000(void) {} +#endif /* CONFIG_DM9000 */ + + +/* + * USB Host Port + */ +static struct at91_usbh_data __initdata ek_usbh_data = { + .ports = 2, +}; + + +/* + * USB Device Port + */ +static struct at91_udc_data __initdata ek_udc_data = { + .vbus_pin = AT91_PIN_PB29, + .pullup_pin = 0, /* pull-up driven by UDC */ +}; + + +/* + * MCI (SD/MMC) + */ +static struct at91_mmc_data __initdata ek_mmc_data = { + .wire4 = 1, +// .det_pin = ... not connected +// .wp_pin = ... not connected +// .vcc_pin = ... not connected +}; + + +/* + * NAND flash + */ +static struct mtd_partition __initdata ek_nand_partition[] = { + { + .name = "Partition 1", + .offset = 0, + .size = 256 * 1024, + }, + { + .name = "Partition 2", + .offset = 256 * 1024 , + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct mtd_partition *nand_partitions(int size, int *num_partitions) +{ + *num_partitions = ARRAY_SIZE(ek_nand_partition); + return ek_nand_partition; +} + +static struct at91_nand_data __initdata ek_nand_data = { + .ale = 22, + .cle = 21, +// .det_pin = ... not connected + .rdy_pin = AT91_PIN_PC15, + .enable_pin = AT91_PIN_PC14, + .partition_info = nand_partitions, +#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16) + .bus_width_16 = 1, +#else + .bus_width_16 = 0, +#endif +}; + +/* + * SPI devices + */ +static struct spi_board_info ek_spi_devices[] = { + { /* DataFlash chip */ + .modalias = "mtd_dataflash", + .chip_select = 0, + .max_speed_hz = 15 * 1000 * 1000, + .bus_num = 0, + }, +#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD) + { /* DataFlash card - jumper (J12) configurable to CS3 or CS0 */ + .modalias = "mtd_dataflash", + .chip_select = 3, + .max_speed_hz = 15 * 1000 * 1000, + .bus_num = 0, + }, +#elif defined(CONFIG_SND_AT73C213) + { /* AT73C213 DAC */ + .modalias = "snd_at73c213", + .chip_select = 3, + .max_speed_hz = 10 * 1000 * 1000, + .bus_num = 0, + }, +#endif +}; + + +static void __init ek_board_init(void) +{ + /* Serial */ + at91_add_device_serial(); + /* USB Host */ + at91_add_device_usbh(&ek_usbh_data); + /* USB Device */ + at91_add_device_udc(&ek_udc_data); + /* I2C */ + at91_add_device_i2c(); + /* NAND */ + at91_add_device_nand(&ek_nand_data); + /* DM9000 ethernet */ + ek_add_device_dm9000(); + + /* spi0 and mmc/sd share the same PIO pins */ +#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE) + /* SPI */ + at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); +#else + /* MMC */ + at91_add_device_mmc(&ek_mmc_data); +#endif +} + +MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK") + /* Maintainer: Atmel */ + .phys_io = AT91_BASE_SYS, + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, + .boot_params = AT91_SDRAM_BASE + 0x100, + .timer = &at91sam926x_timer, + .map_io = ek_map_io, + .init_irq = ek_init_irq, + .init_machine = ek_board_init, +MACHINE_END diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c new file mode 100644 index 000000000000..baab095f6e32 --- /dev/null +++ b/arch/arm/mach-at91/clock.c @@ -0,0 +1,644 @@ +/* + * linux/arch/arm/mach-at91/clock.c + * + * Copyright (C) 2005 David Brownell + * Copyright (C) 2005 Ivan Kokshaysky + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "clock.h" + + +/* + * There's a lot more which can be done with clocks, including cpufreq + * integration, slow clock mode support (for system suspend), letting + * PLLB be used at other rates (on boards that don't need USB), etc. + */ + +#define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY) +#define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE) +#define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL) +#define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM) + + +static LIST_HEAD(clocks); +static DEFINE_SPINLOCK(clk_lock); + +static u32 at91_pllb_usb_init; + +/* + * Four primary clock sources: two crystal oscillators (32K, main), and + * two PLLs. PLLA usually runs the master clock; and PLLB must run at + * 48 MHz (unless no USB function clocks are needed). The main clock and + * both PLLs are turned off to run in "slow clock mode" (system suspend). + */ +static struct clk clk32k = { + .name = "clk32k", + .rate_hz = AT91_SLOW_CLOCK, + .users = 1, /* always on */ + .id = 0, + .type = CLK_TYPE_PRIMARY, +}; +static struct clk main_clk = { + .name = "main", + .pmc_mask = AT91_PMC_MOSCS, /* in PMC_SR */ + .id = 1, + .type = CLK_TYPE_PRIMARY, +}; +static struct clk plla = { + .name = "plla", + .parent = &main_clk, + .pmc_mask = AT91_PMC_LOCKA, /* in PMC_SR */ + .id = 2, + .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL, +}; + +static void pllb_mode(struct clk *clk, int is_on) +{ + u32 value; + + if (is_on) { + is_on = AT91_PMC_LOCKB; + value = at91_pllb_usb_init; + } else + value = 0; + + // REVISIT: Add work-around for AT91RM9200 Errata #26 ? + at91_sys_write(AT91_CKGR_PLLBR, value); + + do { + cpu_relax(); + } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on); +} + +static struct clk pllb = { + .name = "pllb", + .parent = &main_clk, + .pmc_mask = AT91_PMC_LOCKB, /* in PMC_SR */ + .mode = pllb_mode, + .id = 3, + .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL, +}; + +static void pmc_sys_mode(struct clk *clk, int is_on) +{ + if (is_on) + at91_sys_write(AT91_PMC_SCER, clk->pmc_mask); + else + at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask); +} + +/* USB function clocks (PLLB must be 48 MHz) */ +static struct clk udpck = { + .name = "udpck", + .parent = &pllb, + .mode = pmc_sys_mode, +}; +static struct clk uhpck = { + .name = "uhpck", + .parent = &pllb, + .mode = pmc_sys_mode, +}; + + +/* + * The master clock is divided from the CPU clock (by 1-4). It's used for + * memory, interfaces to on-chip peripherals, the AIC, and sometimes more + * (e.g baud rate generation). It's sourced from one of the primary clocks. + */ +static struct clk mck = { + .name = "mck", + .pmc_mask = AT91_PMC_MCKRDY, /* in PMC_SR */ +}; + +static void pmc_periph_mode(struct clk *clk, int is_on) +{ + if (is_on) + at91_sys_write(AT91_PMC_PCER, clk->pmc_mask); + else + at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask); +} + +static struct clk __init *at91_css_to_clk(unsigned long css) +{ + switch (css) { + case AT91_PMC_CSS_SLOW: + return &clk32k; + case AT91_PMC_CSS_MAIN: + return &main_clk; + case AT91_PMC_CSS_PLLA: + return &plla; + case AT91_PMC_CSS_PLLB: + return &pllb; + } + + return NULL; +} + +/* + * Associate a particular clock with a function (eg, "uart") and device. + * The drivers can then request the same 'function' with several different + * devices and not care about which clock name to use. + */ +void __init at91_clock_associate(const char *id, struct device *dev, const char *func) +{ + struct clk *clk = clk_get(NULL, id); + + if (!dev || !clk || !IS_ERR(clk_get(dev, func))) + return; + + clk->function = func; + clk->dev = dev; +} + +/* clocks cannot be de-registered no refcounting necessary */ +struct clk *clk_get(struct device *dev, const char *id) +{ + struct clk *clk; + + list_for_each_entry(clk, &clocks, node) { + if (strcmp(id, clk->name) == 0) + return clk; + if (clk->function && (dev == clk->dev) && strcmp(id, clk->function) == 0) + return clk; + } + + return ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL(clk_get); + +void clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_put); + +static void __clk_enable(struct clk *clk) +{ + if (clk->parent) + __clk_enable(clk->parent); + if (clk->users++ == 0 && clk->mode) + clk->mode(clk, 1); +} + +int clk_enable(struct clk *clk) +{ + unsigned long flags; + + spin_lock_irqsave(&clk_lock, flags); + __clk_enable(clk); + spin_unlock_irqrestore(&clk_lock, flags); + return 0; +} +EXPORT_SYMBOL(clk_enable); + +static void __clk_disable(struct clk *clk) +{ + BUG_ON(clk->users == 0); + if (--clk->users == 0 && clk->mode) + clk->mode(clk, 0); + if (clk->parent) + __clk_disable(clk->parent); +} + +void clk_disable(struct clk *clk) +{ + unsigned long flags; + + spin_lock_irqsave(&clk_lock, flags); + __clk_disable(clk); + spin_unlock_irqrestore(&clk_lock, flags); +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + unsigned long flags; + unsigned long rate; + + spin_lock_irqsave(&clk_lock, flags); + for (;;) { + rate = clk->rate_hz; + if (rate || !clk->parent) + break; + clk = clk->parent; + } + spin_unlock_irqrestore(&clk_lock, flags); + return rate; +} +EXPORT_SYMBOL(clk_get_rate); + +/*------------------------------------------------------------------------*/ + +#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS + +/* + * For now, only the programmable clocks support reparenting (MCK could + * do this too, with care) or rate changing (the PLLs could do this too, + * ditto MCK but that's more for cpufreq). Drivers may reparent to get + * a better rate match; we don't. + */ + +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned long flags; + unsigned prescale; + unsigned long actual; + + if (!clk_is_programmable(clk)) + return -EINVAL; + spin_lock_irqsave(&clk_lock, flags); + + actual = clk->parent->rate_hz; + for (prescale = 0; prescale < 7; prescale++) { + if (actual && actual <= rate) + break; + actual >>= 1; + } + + spin_unlock_irqrestore(&clk_lock, flags); + return (prescale < 7) ? actual : -ENOENT; +} +EXPORT_SYMBOL(clk_round_rate); + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long flags; + unsigned prescale; + unsigned long actual; + + if (!clk_is_programmable(clk)) + return -EINVAL; + if (clk->users) + return -EBUSY; + spin_lock_irqsave(&clk_lock, flags); + + actual = clk->parent->rate_hz; + for (prescale = 0; prescale < 7; prescale++) { + if (actual && actual <= rate) { + u32 pckr; + + pckr = at91_sys_read(AT91_PMC_PCKR(clk->id)); + pckr &= AT91_PMC_CSS_PLLB; /* clock selection */ + pckr |= prescale << 2; + at91_sys_write(AT91_PMC_PCKR(clk->id), pckr); + clk->rate_hz = actual; + break; + } + actual >>= 1; + } + + spin_unlock_irqrestore(&clk_lock, flags); + return (prescale < 7) ? actual : -ENOENT; +} +EXPORT_SYMBOL(clk_set_rate); + +struct clk *clk_get_parent(struct clk *clk) +{ + return clk->parent; +} +EXPORT_SYMBOL(clk_get_parent); + +int clk_set_parent(struct clk *clk, struct clk *parent) +{ + unsigned long flags; + + if (clk->users) + return -EBUSY; + if (!clk_is_primary(parent) || !clk_is_programmable(clk)) + return -EINVAL; + spin_lock_irqsave(&clk_lock, flags); + + clk->rate_hz = parent->rate_hz; + clk->parent = parent; + at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id); + + spin_unlock_irqrestore(&clk_lock, flags); + return 0; +} +EXPORT_SYMBOL(clk_set_parent); + +/* establish PCK0..PCK3 parentage and rate */ +static void init_programmable_clock(struct clk *clk) +{ + struct clk *parent; + u32 pckr; + + pckr = at91_sys_read(AT91_PMC_PCKR(clk->id)); + parent = at91_css_to_clk(pckr & AT91_PMC_CSS); + clk->parent = parent; + clk->rate_hz = parent->rate_hz / (1 << ((pckr >> 2) & 3)); +} + +#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */ + +/*------------------------------------------------------------------------*/ + +#ifdef CONFIG_DEBUG_FS + +static int at91_clk_show(struct seq_file *s, void *unused) +{ + u32 scsr, pcsr, sr; + struct clk *clk; + unsigned i; + + seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR)); + seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR)); + + seq_printf(s, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR)); + seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR)); + seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR)); + seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR)); + + seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR)); + for (i = 0; i < 4; i++) + seq_printf(s, "PCK%d = %8x\n", i, at91_sys_read(AT91_PMC_PCKR(i))); + seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR)); + + seq_printf(s, "\n"); + + list_for_each_entry(clk, &clocks, node) { + char *state; + + if (clk->mode == pmc_sys_mode) + state = (scsr & clk->pmc_mask) ? "on" : "off"; + else if (clk->mode == pmc_periph_mode) + state = (pcsr & clk->pmc_mask) ? "on" : "off"; + else if (clk->pmc_mask) + state = (sr & clk->pmc_mask) ? "on" : "off"; + else if (clk == &clk32k || clk == &main_clk) + state = "on"; + else + state = ""; + + seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n", + clk->name, clk->users, state, clk_get_rate(clk), + clk->parent ? clk->parent->name : ""); + } + return 0; +} + +static int at91_clk_open(struct inode *inode, struct file *file) +{ + return single_open(file, at91_clk_show, NULL); +} + +static struct file_operations at91_clk_operations = { + .open = at91_clk_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int __init at91_clk_debugfs_init(void) +{ + /* /sys/kernel/debug/at91_clk */ + (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations); + + return 0; +} +postcore_initcall(at91_clk_debugfs_init); + +#endif + +/*------------------------------------------------------------------------*/ + +/* Register a new clock */ +int __init clk_register(struct clk *clk) +{ + if (clk_is_peripheral(clk)) { + clk->parent = &mck; + clk->mode = pmc_periph_mode; + list_add_tail(&clk->node, &clocks); + } + else if (clk_is_sys(clk)) { + clk->parent = &mck; + clk->mode = pmc_sys_mode; + + list_add_tail(&clk->node, &clocks); + } +#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS + else if (clk_is_programmable(clk)) { + clk->mode = pmc_sys_mode; + init_programmable_clock(clk); + list_add_tail(&clk->node, &clocks); + } +#endif + + return 0; +} + + +/*------------------------------------------------------------------------*/ + +static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg) +{ + unsigned mul, div; + + div = reg & 0xff; + mul = (reg >> 16) & 0x7ff; + if (div && mul) { + freq /= div; + freq *= mul + 1; + } else + freq = 0; + + return freq; +} + +static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg) +{ + if (pll == &pllb && (reg & AT91_PMC_USB96M)) + return freq / 2; + else + return freq; +} + +static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq) +{ + unsigned i, div = 0, mul = 0, diff = 1 << 30; + unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; + + /* PLL output max 240 MHz (or 180 MHz per errata) */ + if (out_freq > 240000000) + goto fail; + + for (i = 1; i < 256; i++) { + int diff1; + unsigned input, mul1; + + /* + * PLL input between 1MHz and 32MHz per spec, but lower + * frequences seem necessary in some cases so allow 100K. + */ + input = main_freq / i; + if (input < 100000) + continue; + if (input > 32000000) + continue; + + mul1 = out_freq / input; + if (mul1 > 2048) + continue; + if (mul1 < 2) + goto fail; + + diff1 = out_freq - input * mul1; + if (diff1 < 0) + diff1 = -diff1; + if (diff > diff1) { + diff = diff1; + div = i; + mul = mul1; + if (diff == 0) + break; + } + } + if (i == 256 && diff > (out_freq >> 5)) + goto fail; + return ret | ((mul - 1) << 16) | div; +fail: + return 0; +} + +/* + * Several unused clocks may be active. Turn them off. + */ +static void __init at91_periphclk_reset(void) +{ + unsigned long reg; + struct clk *clk; + + reg = at91_sys_read(AT91_PMC_PCSR); + + list_for_each_entry(clk, &clocks, node) { + if (clk->mode != pmc_periph_mode) + continue; + + if (clk->users > 0) + reg &= ~clk->pmc_mask; + } + + at91_sys_write(AT91_PMC_PCDR, reg); +} + +static struct clk *const standard_pmc_clocks[] __initdata = { + /* four primary clocks */ + &clk32k, + &main_clk, + &plla, + &pllb, + + /* PLLB children (USB) */ + &udpck, + &uhpck, + + /* MCK */ + &mck +}; + +int __init at91_clock_init(unsigned long main_clock) +{ + unsigned tmp, freq, mckr; + int i; + + /* + * When the bootloader initialized the main oscillator correctly, + * there's no problem using the cycle counter. But if it didn't, + * or when using oscillator bypass mode, we must be told the speed + * of the main clock. + */ + if (!main_clock) { + do { + tmp = at91_sys_read(AT91_CKGR_MCFR); + } while (!(tmp & AT91_PMC_MAINRDY)); + main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); + } + main_clk.rate_hz = main_clock; + + /* report if PLLA is more than mildly overclocked */ + plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); + if (plla.rate_hz > 209000000) + pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); + + /* + * USB clock init: choose 48 MHz PLLB value, turn all clocks off, + * disable 48MHz clock during usb peripheral suspend. + * + * REVISIT: assumes MCK doesn't derive from PLLB! + */ + at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; + pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); + if (cpu_is_at91rm9200()) { + uhpck.pmc_mask = AT91RM9200_PMC_UHP; + udpck.pmc_mask = AT91RM9200_PMC_UDP; + at91_sys_write(AT91_PMC_SCDR, AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP); + at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP); + } else if (cpu_is_at91sam9260()) { + uhpck.pmc_mask = AT91SAM926x_PMC_UHP; + udpck.pmc_mask = AT91SAM926x_PMC_UDP; + at91_sys_write(AT91_PMC_SCDR, AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP); + } else if (cpu_is_at91sam9261()) { + uhpck.pmc_mask = (AT91SAM926x_PMC_UHP | AT91_PMC_HCK0); + udpck.pmc_mask = AT91SAM926x_PMC_UDP; + at91_sys_write(AT91_PMC_SCDR, AT91SAM926x_PMC_UHP | AT91_PMC_HCK0 | AT91SAM926x_PMC_UDP); + } + at91_sys_write(AT91_CKGR_PLLBR, 0); + + udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); + uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); + + /* + * MCK and CPU derive from one of those primary clocks. + * For now, assume this parentage won't change. + */ + mckr = at91_sys_read(AT91_PMC_MCKR); + mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); + freq = mck.parent->rate_hz; + freq /= (1 << ((mckr >> 2) & 3)); /* prescale */ + mck.rate_hz = freq / (1 + ((mckr >> 8) & 3)); /* mdiv */ + + /* Register the PMC's standard clocks */ + for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) + list_add_tail(&standard_pmc_clocks[i]->node, &clocks); + + /* MCK and CPU clock are "always on" */ + clk_enable(&mck); + + printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", + freq / 1000000, (unsigned) mck.rate_hz / 1000000, + (unsigned) main_clock / 1000000, + ((unsigned) main_clock % 1000000) / 1000); + + /* disable all programmable clocks */ + at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK0 | AT91_PMC_PCK1 | AT91_PMC_PCK2 | AT91_PMC_PCK3); + + /* disable all other unused peripheral clocks */ + at91_periphclk_reset(); + + return 0; +} diff --git a/arch/arm/mach-at91/clock.h b/arch/arm/mach-at91/clock.h new file mode 100644 index 000000000000..1ba3b95ff359 --- /dev/null +++ b/arch/arm/mach-at91/clock.h @@ -0,0 +1,31 @@ +/* + * linux/arch/arm/mach-at91/clock.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#define CLK_TYPE_PRIMARY 0x1 +#define CLK_TYPE_PLL 0x2 +#define CLK_TYPE_PROGRAMMABLE 0x4 +#define CLK_TYPE_PERIPHERAL 0x8 +#define CLK_TYPE_SYSTEM 0x10 + + +struct clk { + struct list_head node; + const char *name; /* unique clock name */ + const char *function; /* function of the clock */ + struct device *dev; /* device associated with function */ + unsigned long rate_hz; + struct clk *parent; + u32 pmc_mask; + void (*mode)(struct clk *, int); + unsigned id:2; /* PCK0..3, or 32k/main/a/b */ + unsigned type; /* clock type */ + u16 users; +}; + + +extern int __init clk_register(struct clk *clk); diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h new file mode 100644 index 000000000000..10ee37bf6d4d --- /dev/null +++ b/arch/arm/mach-at91/generic.h @@ -0,0 +1,49 @@ +/* + * linux/arch/arm/mach-at91/generic.h + * + * Copyright (C) 2005 David Brownell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + + /* Processors */ +extern void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banks); +extern void __init at91sam9260_initialize(unsigned long main_clock); +extern void __init at91sam9261_initialize(unsigned long main_clock); + + /* Interrupts */ +extern void __init at91rm9200_init_interrupts(unsigned int priority[]); +extern void __init at91sam9260_init_interrupts(unsigned int priority[]); +extern void __init at91sam9261_init_interrupts(unsigned int priority[]); +extern void __init at91_aic_init(unsigned int priority[]); + + /* Timer */ +struct sys_timer; +extern struct sys_timer at91rm9200_timer; +extern struct sys_timer at91sam926x_timer; + + /* Clocks */ +extern int __init at91_clock_init(unsigned long main_clock); +struct device; +extern void __init at91_clock_associate(const char *id, struct device *dev, const char *func); + + /* Power Management */ +extern void at91_irq_suspend(void); +extern void at91_irq_resume(void); + + /* GPIO */ +#define AT91RM9200_PQFP 3 /* AT91RM9200 PQFP package has 3 banks */ +#define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */ + +struct at91_gpio_bank { + unsigned short id; /* peripheral ID */ + unsigned long offset; /* offset from system peripheral base */ + struct clk *clock; /* associated clock */ +}; +extern void __init at91_gpio_init(struct at91_gpio_bank *, int nr_banks); +extern void __init at91_gpio_irq_setup(void); + +extern void (*at91_arch_reset)(void); +extern int at91_extern_irq; diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c new file mode 100644 index 000000000000..9b7495cd555d --- /dev/null +++ b/arch/arm/mach-at91/gpio.c @@ -0,0 +1,414 @@ +/* + * linux/arch/arm/mach-at91/gpio.c + * + * Copyright (C) 2005 HP Labs + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "generic.h" + + +static struct at91_gpio_bank *gpio; +static int gpio_banks; + + +static inline void __iomem *pin_to_controller(unsigned pin) +{ + void __iomem *sys_base = (void __iomem *) AT91_VA_BASE_SYS; + + pin -= PIN_BASE; + pin /= 32; + if (likely(pin < gpio_banks)) + return sys_base + gpio[pin].offset; + + return NULL; +} + +static inline unsigned pin_to_mask(unsigned pin) +{ + pin -= PIN_BASE; + return 1 << (pin % 32); +} + + +/*--------------------------------------------------------------------------*/ + +/* Not all hardware capabilities are exposed through these calls; they + * only encapsulate the most common features and modes. (So if you + * want to change signals in groups, do it directly.) + * + * Bootloaders will usually handle some of the pin multiplexing setup. + * The intent is certainly that by the time Linux is fully booted, all + * pins should have been fully initialized. These setup calls should + * only be used by board setup routines, or possibly in driver probe(). + * + * For bootloaders doing all that setup, these calls could be inlined + * as NOPs so Linux won't duplicate any setup code + */ + + +/* + * mux the pin to the "A" internal peripheral role. + */ +int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup) +{ + void __iomem *pio = pin_to_controller(pin); + unsigned mask = pin_to_mask(pin); + + if (!pio) + return -EINVAL; + + __raw_writel(mask, pio + PIO_IDR); + __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); + __raw_writel(mask, pio + PIO_ASR); + __raw_writel(mask, pio + PIO_PDR); + return 0; +} +EXPORT_SYMBOL(at91_set_A_periph); + + +/* + * mux the pin to the "B" internal peripheral role. + */ +int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup) +{ + void __iomem *pio = pin_to_controller(pin); + unsigned mask = pin_to_mask(pin); + + if (!pio) + return -EINVAL; + + __raw_writel(mask, pio + PIO_IDR); + __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); + __raw_writel(mask, pio + PIO_BSR); + __raw_writel(mask, pio + PIO_PDR); + return 0; +} +EXPORT_SYMBOL(at91_set_B_periph); + + +/* + * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and + * configure it for an input. + */ +int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup) +{ + void __iomem *pio = pin_to_controller(pin); + unsigned mask = pin_to_mask(pin); + + if (!pio) + return -EINVAL; + + __raw_writel(mask, pio + PIO_IDR); + __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); + __raw_writel(mask, pio + PIO_ODR); + __raw_writel(mask, pio + PIO_PER); + return 0; +} +EXPORT_SYMBOL(at91_set_gpio_input); + + +/* + * mux the pin to the gpio controller (instead of "A" or "B" peripheral), + * and configure it for an output. + */ +int __init_or_module at91_set_gpio_output(unsigned pin, int value) +{ + void __iomem *pio = pin_to_controller(pin); + unsigned mask = pin_to_mask(pin); + + if (!pio) + return -EINVAL; + + __raw_writel(mask, pio + PIO_IDR); + __raw_writel(mask, pio + PIO_PUDR); + __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); + __raw_writel(mask, pio + PIO_OER); + __raw_writel(mask, pio + PIO_PER); + return 0; +} +EXPORT_SYMBOL(at91_set_gpio_output); + + +/* + * enable/disable the glitch filter; mostly used with IRQ handling. + */ +int __init_or_module at91_set_deglitch(unsigned pin, int is_on) +{ + void __iomem *pio = pin_to_controller(pin); + unsigned mask = pin_to_mask(pin); + + if (!pio) + return -EINVAL; + __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); + return 0; +} +EXPORT_SYMBOL(at91_set_deglitch); + +/* + * enable/disable the multi-driver; This is only valid for output and + * allows the output pin to run as an open collector output. + */ +int __init_or_module at91_set_multi_drive(unsigned pin, int is_on) +{ + void __iomem *pio = pin_to_controller(pin); + unsigned mask = pin_to_mask(pin); + + if (!pio) + return -EINVAL; + + __raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR)); + return 0; +} +EXPORT_SYMBOL(at91_set_multi_drive); + +/*--------------------------------------------------------------------------*/ + +/* + * assuming the pin is muxed as a gpio output, set its value. + */ +int at91_set_gpio_value(unsigned pin, int value) +{ + void __iomem *pio = pin_to_controller(pin); + unsigned mask = pin_to_mask(pin); + + if (!pio) + return -EINVAL; + __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); + return 0; +} +EXPORT_SYMBOL(at91_set_gpio_value); + + +/* + * read the pin's value (works even if it's not muxed as a gpio). + */ +int at91_get_gpio_value(unsigned pin) +{ + void __iomem *pio = pin_to_controller(pin); + unsigned mask = pin_to_mask(pin); + u32 pdsr; + + if (!pio) + return -EINVAL; + pdsr = __raw_readl(pio + PIO_PDSR); + return (pdsr & mask) != 0; +} +EXPORT_SYMBOL(at91_get_gpio_value); + +/*--------------------------------------------------------------------------*/ + +#ifdef CONFIG_PM + +static u32 wakeups[MAX_GPIO_BANKS]; +static u32 backups[MAX_GPIO_BANKS]; + +static int gpio_irq_set_wake(unsigned pin, unsigned state) +{ + unsigned mask = pin_to_mask(pin); + unsigned bank = (pin - PIN_BASE) / 32; + + if (unlikely(bank >= MAX_GPIO_BANKS)) + return -EINVAL; + + if (state) + wakeups[bank] |= mask; + else + wakeups[bank] &= ~mask; + + set_irq_wake(gpio[bank].id, state); + + return 0; +} + +void at91_gpio_suspend(void) +{ + int i; + + for (i = 0; i < gpio_banks; i++) { + u32 pio = gpio[i].offset; + + backups[i] = at91_sys_read(pio + PIO_IMR); + at91_sys_write(pio + PIO_IDR, backups[i]); + at91_sys_write(pio + PIO_IER, wakeups[i]); + + if (!wakeups[i]) + clk_disable(gpio[i].clock); + else { +#ifdef CONFIG_PM_DEBUG + printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]); +#endif + } + } +} + +void at91_gpio_resume(void) +{ + int i; + + for (i = 0; i < gpio_banks; i++) { + u32 pio = gpio[i].offset; + + if (!wakeups[i]) + clk_enable(gpio[i].clock); + + at91_sys_write(pio + PIO_IDR, wakeups[i]); + at91_sys_write(pio + PIO_IER, backups[i]); + } +} + +#else +#define gpio_irq_set_wake NULL +#endif + + +/* Several AIC controller irqs are dispatched through this GPIO handler. + * To use any AT91_PIN_* as an externally triggered IRQ, first call + * at91_set_gpio_input() then maybe enable its glitch filter. + * Then just request_irq() with the pin ID; it works like any ARM IRQ + * handler, though it always triggers on rising and falling edges. + * + * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after + * configuring them with at91_set_a_periph() or at91_set_b_periph(). + * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering. + */ + +static void gpio_irq_mask(unsigned pin) +{ + void __iomem *pio = pin_to_controller(pin); + unsigned mask = pin_to_mask(pin); + + if (pio) + __raw_writel(mask, pio + PIO_IDR); +} + +static void gpio_irq_unmask(unsigned pin) +{ + void __iomem *pio = pin_to_controller(pin); + unsigned mask = pin_to_mask(pin); + + if (pio) + __raw_writel(mask, pio + PIO_IER); +} + +static int gpio_irq_type(unsigned pin, unsigned type) +{ + return (type == IRQT_BOTHEDGE) ? 0 : -EINVAL; +} + +static struct irq_chip gpio_irqchip = { + .name = "GPIO", + .mask = gpio_irq_mask, + .unmask = gpio_irq_unmask, + .set_type = gpio_irq_type, + .set_wake = gpio_irq_set_wake, +}; + +static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) +{ + unsigned pin; + struct irq_desc *gpio; + void __iomem *pio; + u32 isr; + + pio = get_irq_chip_data(irq); + + /* temporarily mask (level sensitive) parent IRQ */ + desc->chip->ack(irq); + for (;;) { + /* reading ISR acks the pending (edge triggered) GPIO interrupt */ + isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR); + if (!isr) + break; + + pin = (unsigned) get_irq_data(irq); + gpio = &irq_desc[pin]; + + while (isr) { + if (isr & 1) { + if (unlikely(gpio->depth)) { + /* + * The core ARM interrupt handler lazily disables IRQs so + * another IRQ must be generated before it actually gets + * here to be disabled on the GPIO controller. + */ + gpio_irq_mask(pin); + } + else + desc_handle_irq(pin, gpio); + } + pin++; + gpio++; + isr >>= 1; + } + } + desc->chip->unmask(irq); + /* now it may re-trigger */ +} + +/*--------------------------------------------------------------------------*/ + +/* + * Called from the processor-specific init to enable GPIO interrupt support. + */ +void __init at91_gpio_irq_setup(void) +{ + unsigned pioc, pin; + + for (pioc = 0, pin = PIN_BASE; + pioc < gpio_banks; + pioc++) { + void __iomem *controller; + unsigned id = gpio[pioc].id; + unsigned i; + + clk_enable(gpio[pioc].clock); /* enable PIO controller's clock */ + + controller = (void __iomem *) AT91_VA_BASE_SYS + gpio[pioc].offset; + __raw_writel(~0, controller + PIO_IDR); + + set_irq_data(id, (void *) pin); + set_irq_chip_data(id, controller); + + for (i = 0; i < 32; i++, pin++) { + /* + * Can use the "simple" and not "edge" handler since it's + * shorter, and the AIC handles interupts sanely. + */ + set_irq_chip(pin, &gpio_irqchip); + set_irq_handler(pin, handle_simple_irq); + set_irq_flags(pin, IRQF_VALID); + } + + set_irq_chained_handler(id, gpio_irq_handler); + } + pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks); +} + +/* + * Called from the processor-specific init to enable GPIO pin support. + */ +void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks) +{ + BUG_ON(nr_banks > MAX_GPIO_BANKS); + + gpio = data; + gpio_banks = nr_banks; +} diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c new file mode 100644 index 000000000000..78a5cdb746dc --- /dev/null +++ b/arch/arm/mach-at91/irq.c @@ -0,0 +1,168 @@ +/* + * linux/arch/arm/mach-at91/irq.c + * + * Copyright (C) 2004 SAN People + * Copyright (C) 2004 ATMEL + * Copyright (C) Rick Bronson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + + +static void at91_aic_mask_irq(unsigned int irq) +{ + /* Disable interrupt on AIC */ + at91_sys_write(AT91_AIC_IDCR, 1 << irq); +} + +static void at91_aic_unmask_irq(unsigned int irq) +{ + /* Enable interrupt on AIC */ + at91_sys_write(AT91_AIC_IECR, 1 << irq); +} + +unsigned int at91_extern_irq; + +#define is_extern_irq(irq) ((1 << (irq)) & at91_extern_irq) + +static int at91_aic_set_type(unsigned irq, unsigned type) +{ + unsigned int smr, srctype; + + switch (type) { + case IRQT_HIGH: + srctype = AT91_AIC_SRCTYPE_HIGH; + break; + case IRQT_RISING: + srctype = AT91_AIC_SRCTYPE_RISING; + break; + case IRQT_LOW: + if ((irq == AT91_ID_FIQ) || is_extern_irq(irq)) /* only supported on external interrupts */ + srctype = AT91_AIC_SRCTYPE_LOW; + else + return -EINVAL; + break; + case IRQT_FALLING: + if ((irq == AT91_ID_FIQ) || is_extern_irq(irq)) /* only supported on external interrupts */ + srctype = AT91_AIC_SRCTYPE_FALLING; + else + return -EINVAL; + break; + default: + return -EINVAL; + } + + smr = at91_sys_read(AT91_AIC_SMR(irq)) & ~AT91_AIC_SRCTYPE; + at91_sys_write(AT91_AIC_SMR(irq), smr | srctype); + return 0; +} + +#ifdef CONFIG_PM + +static u32 wakeups; +static u32 backups; + +static int at91_aic_set_wake(unsigned irq, unsigned value) +{ + if (unlikely(irq >= 32)) + return -EINVAL; + + if (value) + wakeups |= (1 << irq); + else + wakeups &= ~(1 << irq); + + return 0; +} + +void at91_irq_suspend(void) +{ + backups = at91_sys_read(AT91_AIC_IMR); + at91_sys_write(AT91_AIC_IDCR, backups); + at91_sys_write(AT91_AIC_IECR, wakeups); +} + +void at91_irq_resume(void) +{ + at91_sys_write(AT91_AIC_IDCR, wakeups); + at91_sys_write(AT91_AIC_IECR, backups); +} + +#else +#define at91_aic_set_wake NULL +#endif + +static struct irq_chip at91_aic_chip = { + .name = "AIC", + .ack = at91_aic_mask_irq, + .mask = at91_aic_mask_irq, + .unmask = at91_aic_unmask_irq, + .set_type = at91_aic_set_type, + .set_wake = at91_aic_set_wake, +}; + +/* + * Initialize the AIC interrupt controller. + */ +void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS]) +{ + unsigned int i; + + /* + * The IVR is used by macro get_irqnr_and_base to read and verify. + * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred. + */ + for (i = 0; i < NR_AIC_IRQS; i++) { + /* Put irq number in Source Vector Register: */ + at91_sys_write(AT91_AIC_SVR(i), i); + /* Active Low interrupt, with the specified priority */ + at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]); + + set_irq_chip(i, &at91_aic_chip); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID | IRQF_PROBE); + + /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */ + if (i < 8) + at91_sys_write(AT91_AIC_EOICR, 0); + } + + /* + * Spurious Interrupt ID in Spurious Vector Register is NR_AIC_IRQS + * When there is no current interrupt, the IRQ Vector Register reads the value stored in AIC_SPU + */ + at91_sys_write(AT91_AIC_SPU, NR_AIC_IRQS); + + /* No debugging in AIC: Debug (Protect) Control Register */ + at91_sys_write(AT91_AIC_DCR, 0); + + /* Disable and clear all interrupts initially */ + at91_sys_write(AT91_AIC_IDCR, 0xFFFFFFFF); + at91_sys_write(AT91_AIC_ICCR, 0xFFFFFFFF); +} diff --git a/arch/arm/mach-at91/leds.c b/arch/arm/mach-at91/leds.c new file mode 100644 index 000000000000..1a333730466e --- /dev/null +++ b/arch/arm/mach-at91/leds.c @@ -0,0 +1,99 @@ +/* + * LED driver for Atmel AT91-based boards. + * + * Copyright (C) SAN People (Pty) Ltd + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. +*/ + +#include +#include +#include + +#include +#include +#include +#include + + +static inline void at91_led_on(unsigned int led) +{ + at91_set_gpio_value(led, 0); +} + +static inline void at91_led_off(unsigned int led) +{ + at91_set_gpio_value(led, 1); +} + +static inline void at91_led_toggle(unsigned int led) +{ + unsigned long is_off = at91_get_gpio_value(led); + if (is_off) + at91_led_on(led); + else + at91_led_off(led); +} + + +/* + * Handle LED events. + */ +static void at91_leds_event(led_event_t evt) +{ + unsigned long flags; + + local_irq_save(flags); + + switch(evt) { + case led_start: /* System startup */ + at91_led_on(at91_leds_cpu); + break; + + case led_stop: /* System stop / suspend */ + at91_led_off(at91_leds_cpu); + break; + +#ifdef CONFIG_LEDS_TIMER + case led_timer: /* Every 50 timer ticks */ + at91_led_toggle(at91_leds_timer); + break; +#endif + +#ifdef CONFIG_LEDS_CPU + case led_idle_start: /* Entering idle state */ + at91_led_off(at91_leds_cpu); + break; + + case led_idle_end: /* Exit idle state */ + at91_led_on(at91_leds_cpu); + break; +#endif + + default: + break; + } + + local_irq_restore(flags); +} + + +static int __init leds_init(void) +{ + if (!at91_leds_timer || !at91_leds_cpu) + return -ENODEV; + + /* Enable PIO to access the LEDs */ + at91_set_gpio_output(at91_leds_timer, 1); + at91_set_gpio_output(at91_leds_cpu, 1); + + leds_event = at91_leds_event; + + leds_event(led_start); + return 0; +} + +__initcall(leds_init); diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c new file mode 100644 index 000000000000..e095b1fe8d8a --- /dev/null +++ b/arch/arm/mach-at91/pm.c @@ -0,0 +1,227 @@ +/* + * arch/arm/mach-at91/pm.c + * AT91 Power Management + * + * Copyright (C) 2005 David Brownell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "generic.h" + + +static int at91_pm_valid_state(suspend_state_t state) +{ + switch (state) { + case PM_SUSPEND_ON: + case PM_SUSPEND_STANDBY: + case PM_SUSPEND_MEM: + return 1; + + default: + return 0; + } +} + + +static suspend_state_t target_state; + +/* + * Called after processes are frozen, but before we shutdown devices. + */ +static int at91_pm_prepare(suspend_state_t state) +{ + target_state = state; + return 0; +} + +/* + * Verify that all the clocks are correct before entering + * slow-clock mode. + */ +static int at91_pm_verify_clocks(void) +{ + unsigned long scsr; + int i; + + scsr = at91_sys_read(AT91_PMC_SCSR); + + /* USB must not be using PLLB */ + if (cpu_is_at91rm9200()) { + if ((scsr & (AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP)) != 0) { + pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n"); + return 0; + } + } else if (cpu_is_at91sam9260()) { +#warning "Check SAM9260 USB clocks" + } else if (cpu_is_at91sam9261()) { +#warning "Check SAM9261 USB clocks" + } + +#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS + /* PCK0..PCK3 must be disabled, or configured to use clk32k */ + for (i = 0; i < 4; i++) { + u32 css; + + if ((scsr & (AT91_PMC_PCK0 << i)) == 0) + continue; + + css = at91_sys_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS; + if (css != AT91_PMC_CSS_SLOW) { + pr_debug("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css); + return 0; + } + } +#endif + + return 1; +} + +/* + * Call this from platform driver suspend() to see how deeply to suspend. + * For example, some controllers (like OHCI) need one of the PLL clocks + * in order to act as a wakeup source, and those are not available when + * going into slow clock mode. + * + * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have + * the very same problem (but not using at91 main_clk), and it'd be better + * to add one generic API rather than lots of platform-specific ones. + */ +int at91_suspend_entering_slow_clock(void) +{ + return (target_state == PM_SUSPEND_MEM); +} +EXPORT_SYMBOL(at91_suspend_entering_slow_clock); + + +static void (*slow_clock)(void); + + +static int at91_pm_enter(suspend_state_t state) +{ + at91_gpio_suspend(); + at91_irq_suspend(); + + pr_debug("AT91: PM - wake mask %08x, pm state %d\n", + /* remember all the always-wake irqs */ + (at91_sys_read(AT91_PMC_PCSR) + | (1 << AT91_ID_FIQ) + | (1 << AT91_ID_SYS) + | (at91_extern_irq)) + & at91_sys_read(AT91_AIC_IMR), + state); + + switch (state) { + /* + * Suspend-to-RAM is like STANDBY plus slow clock mode, so + * drivers must suspend more deeply: only the master clock + * controller may be using the main oscillator. + */ + case PM_SUSPEND_MEM: + /* + * Ensure that clocks are in a valid state. + */ + if (!at91_pm_verify_clocks()) + goto error; + + /* + * Enter slow clock mode by switching over to clk32k and + * turning off the main oscillator; reverse on wakeup. + */ + if (slow_clock) { + slow_clock(); + break; + } else { + /* DEVELOPMENT ONLY */ + pr_info("AT91: PM - no slow clock mode yet ...\n"); + /* FALLTHROUGH leaving master clock alone */ + } + + /* + * STANDBY mode has *all* drivers suspended; ignores irqs not + * marked as 'wakeup' event sources; and reduces DRAM power. + * But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and + * nothing fancy done with main or cpu clocks. + */ + case PM_SUSPEND_STANDBY: + /* + * NOTE: the Wait-for-Interrupt instruction needs to be + * in icache so the SDRAM stays in self-refresh mode until + * the wakeup IRQ occurs. + */ + asm("b 1f; .align 5; 1:"); + asm("mcr p15, 0, r0, c7, c10, 4"); /* drain write buffer */ + at91_sys_write(AT91_SDRAMC_SRR, 1); /* self-refresh mode */ + /* fall though to next state */ + + case PM_SUSPEND_ON: + asm("mcr p15, 0, r0, c7, c0, 4"); /* wait for interrupt */ + break; + + default: + pr_debug("AT91: PM - bogus suspend state %d\n", state); + goto error; + } + + pr_debug("AT91: PM - wakeup %08x\n", + at91_sys_read(AT91_AIC_IPR) & at91_sys_read(AT91_AIC_IMR)); + +error: + target_state = PM_SUSPEND_ON; + at91_irq_resume(); + at91_gpio_resume(); + return 0; +} + + +static struct pm_ops at91_pm_ops ={ + .pm_disk_mode = 0, + .valid = at91_pm_valid_state, + .prepare = at91_pm_prepare, + .enter = at91_pm_enter, +}; + +static int __init at91_pm_init(void) +{ + printk("AT91: Power Management\n"); + +#ifdef CONFIG_AT91_PM_SLOW_CLOCK + /* REVISIT allocations of SRAM should be dynamically managed. + * FIQ handlers and other components will want SRAM/TCM too... + */ + slow_clock = (void *) (AT91_VA_BASE_SRAM + (3 * SZ_4K)); + memcpy(slow_clock, at91rm9200_slow_clock, at91rm9200_slow_clock_sz); +#endif + + /* Disable SDRAM low-power mode. Cannot be used with self-refresh. */ + at91_sys_write(AT91_SDRAMC_LPR, 0); + + pm_set_ops(&at91_pm_ops); + + return 0; +} +arch_initcall(at91_pm_init); diff --git a/arch/arm/mach-at91rm9200/Kconfig b/arch/arm/mach-at91rm9200/Kconfig deleted file mode 100644 index 9f11db8af233..000000000000 --- a/arch/arm/mach-at91rm9200/Kconfig +++ /dev/null @@ -1,148 +0,0 @@ -if ARCH_AT91 - -menu "Atmel AT91 System-on-Chip" - -choice - prompt "Atmel AT91 Processor" - -config ARCH_AT91RM9200 - bool "AT91RM9200" - -config ARCH_AT91SAM9260 - bool "AT91SAM9260" - -config ARCH_AT91SAM9261 - bool "AT91SAM9261" - -endchoice - -# ---------------------------------------------------------- - -if ARCH_AT91RM9200 - -comment "AT91RM9200 Board Type" - -config MACH_ONEARM - bool "Ajeco 1ARM Single Board Computer" - depends on ARCH_AT91RM9200 - help - Select this if you are using Ajeco's 1ARM Single Board Computer. - - -config ARCH_AT91RM9200DK - bool "Atmel AT91RM9200-DK Development board" - depends on ARCH_AT91RM9200 - help - Select this if you are using Atmel's AT91RM9200-DK Development board. - (Discontinued) - -config MACH_AT91RM9200EK - bool "Atmel AT91RM9200-EK Evaluation Kit" - depends on ARCH_AT91RM9200 - help - Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit. - - -config MACH_CSB337 - bool "Cogent CSB337" - depends on ARCH_AT91RM9200 - help - Select this if you are using Cogent's CSB337 board. - - -config MACH_CSB637 - bool "Cogent CSB637" - depends on ARCH_AT91RM9200 - help - Select this if you are using Cogent's CSB637 board. - - -config MACH_CARMEVA - bool "Conitec ARM&EVA" - depends on ARCH_AT91RM9200 - help - Select this if you are using Conitec's AT91RM9200-MCU-Module. - - -config MACH_ATEB9200 - bool "Embest ATEB9200" - depends on ARCH_AT91RM9200 - help - Select this if you are using Embest's ATEB9200 board. - - -config MACH_KB9200 - bool "KwikByte KB920x" - depends on ARCH_AT91RM9200 - help - Select this if you are using KwikByte's KB920x board. - - -config MACH_KAFA - bool "Sperry-Sun KAFA board" - depends on ARCH_AT91RM9200 - help - Select this if you are using Sperry-Sun's KAFA board. - -endif - -# ---------------------------------------------------------- - -if ARCH_AT91SAM9260 - -comment "AT91SAM9260 Board Type" - -config MACH_AT91SAM9260EK - bool "Atmel AT91SAM9260-EK Evaluation Kit" - depends on ARCH_AT91SAM9260 - help - Select this if you are using Atmel's AT91SAM9260-EK Evaluation Kit. - - -endif - -# ---------------------------------------------------------- - -if ARCH_AT91SAM9261 - -comment "AT91SAM9261 Board Type" - -config MACH_AT91SAM9261EK - bool "Atmel AT91SAM9261-EK Evaluation Kit" - depends on ARCH_AT91SAM9261 - help - Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit. - - -endif - -# ---------------------------------------------------------- - -comment "AT91 Board Options" - -config MTD_AT91_DATAFLASH_CARD - bool "Enable DataFlash Card support" - depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK) - help - Enable support for the DataFlash card. - -config MTD_NAND_AT91_BUSWIDTH_16 - bool "Enable 16-bit data bus interface to NAND flash" - depends on (MACH_AT91SAM9261EK || MACH_AT91SAM9260EK) - help - On AT91SAM926x boards both types of NAND flash can be present - (8 and 16 bit data bus width). - -# ---------------------------------------------------------- - -comment "AT91 Feature Selections" - -config AT91_PROGRAMMABLE_CLOCKS - bool "Programmable Clocks" - help - Select this if you need to program one or more of the PCK0..PCK3 - programmable clock outputs. - -endmenu - -endif diff --git a/arch/arm/mach-at91rm9200/Makefile b/arch/arm/mach-at91rm9200/Makefile deleted file mode 100644 index cf777007847a..000000000000 --- a/arch/arm/mach-at91rm9200/Makefile +++ /dev/null @@ -1,49 +0,0 @@ -# -# Makefile for the linux kernel. -# - -obj-y := clock.o irq.o gpio.o -obj-m := -obj-n := -obj- := - -obj-$(CONFIG_PM) += pm.o - -# CPU-specific support -obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o -obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o -obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o - -# AT91RM9200 board-specific support -obj-$(CONFIG_MACH_ONEARM) += board-1arm.o -obj-$(CONFIG_ARCH_AT91RM9200DK) += board-dk.o -obj-$(CONFIG_MACH_AT91RM9200EK) += board-ek.o -obj-$(CONFIG_MACH_CSB337) += board-csb337.o -obj-$(CONFIG_MACH_CSB637) += board-csb637.o -obj-$(CONFIG_MACH_CARMEVA) += board-carmeva.o -obj-$(CONFIG_MACH_KB9200) += board-kb9202.o -obj-$(CONFIG_MACH_ATEB9200) += board-eb9200.o -obj-$(CONFIG_MACH_KAFA) += board-kafa.o - -# AT91SAM9260 board-specific support -obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o - -# AT91SAM9261 board-specific support -obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o - -# LEDs support -led-$(CONFIG_ARCH_AT91RM9200DK) += leds.o -led-$(CONFIG_MACH_AT91RM9200EK) += leds.o -led-$(CONFIG_MACH_CSB337) += leds.o -led-$(CONFIG_MACH_CSB637) += leds.o -led-$(CONFIG_MACH_KB9200) += leds.o -led-$(CONFIG_MACH_KAFA) += leds.o -obj-$(CONFIG_LEDS) += $(led-y) - -# VGA support -#obj-$(CONFIG_FB_S1D13XXX) += ics1523.o - - -ifeq ($(CONFIG_PM_DEBUG),y) -CFLAGS_pm.o += -DDEBUG -endif diff --git a/arch/arm/mach-at91rm9200/Makefile.boot b/arch/arm/mach-at91rm9200/Makefile.boot deleted file mode 100644 index e667dcc7cd34..000000000000 --- a/arch/arm/mach-at91rm9200/Makefile.boot +++ /dev/null @@ -1,9 +0,0 @@ -# Note: the following conditions must always be true: -# ZRELADDR == virt_to_phys(TEXTADDR) -# PARAMS_PHYS must be within 4MB of ZRELADDR -# INITRD_PHYS must be in RAM - - zreladdr-y := 0x20008000 -params_phys-y := 0x20000100 -initrd_phys-y := 0x20410000 - diff --git a/arch/arm/mach-at91rm9200/at91rm9200.c b/arch/arm/mach-at91rm9200/at91rm9200.c deleted file mode 100644 index a92e9a495b07..000000000000 --- a/arch/arm/mach-at91rm9200/at91rm9200.c +++ /dev/null @@ -1,294 +0,0 @@ -/* - * arch/arm/mach-at91rm9200/at91rm9200.c - * - * Copyright (C) 2005 SAN People - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ - -#include - -#include -#include -#include -#include -#include - -#include "generic.h" -#include "clock.h" - -static struct map_desc at91rm9200_io_desc[] __initdata = { - { - .virtual = AT91_VA_BASE_SYS, - .pfn = __phys_to_pfn(AT91_BASE_SYS), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = AT91_VA_BASE_EMAC, - .pfn = __phys_to_pfn(AT91RM9200_BASE_EMAC), - .length = SZ_16K, - .type = MT_DEVICE, - }, { - .virtual = AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE, - .pfn = __phys_to_pfn(AT91RM9200_SRAM_BASE), - .length = AT91RM9200_SRAM_SIZE, - .type = MT_DEVICE, - }, -}; - -/* -------------------------------------------------------------------- - * Clocks - * -------------------------------------------------------------------- */ - -/* - * The peripheral clocks. - */ -static struct clk udc_clk = { - .name = "udc_clk", - .pmc_mask = 1 << AT91RM9200_ID_UDP, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk ohci_clk = { - .name = "ohci_clk", - .pmc_mask = 1 << AT91RM9200_ID_UHP, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk ether_clk = { - .name = "ether_clk", - .pmc_mask = 1 << AT91RM9200_ID_EMAC, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk mmc_clk = { - .name = "mci_clk", - .pmc_mask = 1 << AT91RM9200_ID_MCI, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk twi_clk = { - .name = "twi_clk", - .pmc_mask = 1 << AT91RM9200_ID_TWI, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk usart0_clk = { - .name = "usart0_clk", - .pmc_mask = 1 << AT91RM9200_ID_US0, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk usart1_clk = { - .name = "usart1_clk", - .pmc_mask = 1 << AT91RM9200_ID_US1, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk usart2_clk = { - .name = "usart2_clk", - .pmc_mask = 1 << AT91RM9200_ID_US2, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk usart3_clk = { - .name = "usart3_clk", - .pmc_mask = 1 << AT91RM9200_ID_US3, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk spi_clk = { - .name = "spi_clk", - .pmc_mask = 1 << AT91RM9200_ID_SPI, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk pioA_clk = { - .name = "pioA_clk", - .pmc_mask = 1 << AT91RM9200_ID_PIOA, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk pioB_clk = { - .name = "pioB_clk", - .pmc_mask = 1 << AT91RM9200_ID_PIOB, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk pioC_clk = { - .name = "pioC_clk", - .pmc_mask = 1 << AT91RM9200_ID_PIOC, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk pioD_clk = { - .name = "pioD_clk", - .pmc_mask = 1 << AT91RM9200_ID_PIOD, - .type = CLK_TYPE_PERIPHERAL, -}; - -static struct clk *periph_clocks[] __initdata = { - &pioA_clk, - &pioB_clk, - &pioC_clk, - &pioD_clk, - &usart0_clk, - &usart1_clk, - &usart2_clk, - &usart3_clk, - &mmc_clk, - &udc_clk, - &twi_clk, - &spi_clk, - // ssc 0 .. ssc2 - // tc0 .. tc5 - &ohci_clk, - ðer_clk, - // irq0 .. irq6 -}; - -/* - * The four programmable clocks. - * You must configure pin multiplexing to bring these signals out. - */ -static struct clk pck0 = { - .name = "pck0", - .pmc_mask = AT91_PMC_PCK0, - .type = CLK_TYPE_PROGRAMMABLE, - .id = 0, -}; -static struct clk pck1 = { - .name = "pck1", - .pmc_mask = AT91_PMC_PCK1, - .type = CLK_TYPE_PROGRAMMABLE, - .id = 1, -}; -static struct clk pck2 = { - .name = "pck2", - .pmc_mask = AT91_PMC_PCK2, - .type = CLK_TYPE_PROGRAMMABLE, - .id = 2, -}; -static struct clk pck3 = { - .name = "pck3", - .pmc_mask = AT91_PMC_PCK3, - .type = CLK_TYPE_PROGRAMMABLE, - .id = 3, -}; - -static void __init at91rm9200_register_clocks(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) - clk_register(periph_clocks[i]); - - clk_register(&pck0); - clk_register(&pck1); - clk_register(&pck2); - clk_register(&pck3); -} - -/* -------------------------------------------------------------------- - * GPIO - * -------------------------------------------------------------------- */ - -static struct at91_gpio_bank at91rm9200_gpio[] = { - { - .id = AT91RM9200_ID_PIOA, - .offset = AT91_PIOA, - .clock = &pioA_clk, - }, { - .id = AT91RM9200_ID_PIOB, - .offset = AT91_PIOB, - .clock = &pioB_clk, - }, { - .id = AT91RM9200_ID_PIOC, - .offset = AT91_PIOC, - .clock = &pioC_clk, - }, { - .id = AT91RM9200_ID_PIOD, - .offset = AT91_PIOD, - .clock = &pioD_clk, - } -}; - -static void at91rm9200_reset(void) -{ - /* - * Perform a hardware reset with the use of the Watchdog timer. - */ - at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1); - at91_sys_write(AT91_ST_CR, AT91_ST_WDRST); -} - - -/* -------------------------------------------------------------------- - * AT91RM9200 processor initialization - * -------------------------------------------------------------------- */ -void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banks) -{ - /* Map peripherals */ - iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc)); - - at91_arch_reset = at91rm9200_reset; - at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1) - | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3) - | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5) - | (1 << AT91RM9200_ID_IRQ6); - - /* Init clock subsystem */ - at91_clock_init(main_clock); - - /* Register the processor-specific clocks */ - at91rm9200_register_clocks(); - - /* Initialize GPIO subsystem */ - at91_gpio_init(at91rm9200_gpio, banks); -} - - -/* -------------------------------------------------------------------- - * Interrupt initialization - * -------------------------------------------------------------------- */ - -/* - * The default interrupt priority levels (0 = lowest, 7 = highest). - */ -static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = { - 7, /* Advanced Interrupt Controller (FIQ) */ - 7, /* System Peripherals */ - 0, /* Parallel IO Controller A */ - 0, /* Parallel IO Controller B */ - 0, /* Parallel IO Controller C */ - 0, /* Parallel IO Controller D */ - 6, /* USART 0 */ - 6, /* USART 1 */ - 6, /* USART 2 */ - 6, /* USART 3 */ - 0, /* Multimedia Card Interface */ - 4, /* USB Device Port */ - 0, /* Two-Wire Interface */ - 6, /* Serial Peripheral Interface */ - 5, /* Serial Synchronous Controller 0 */ - 5, /* Serial Synchronous Controller 1 */ - 5, /* Serial Synchronous Controller 2 */ - 0, /* Timer Counter 0 */ - 0, /* Timer Counter 1 */ - 0, /* Timer Counter 2 */ - 0, /* Timer Counter 3 */ - 0, /* Timer Counter 4 */ - 0, /* Timer Counter 5 */ - 3, /* USB Host port */ - 3, /* Ethernet MAC */ - 0, /* Advanced Interrupt Controller (IRQ0) */ - 0, /* Advanced Interrupt Controller (IRQ1) */ - 0, /* Advanced Interrupt Controller (IRQ2) */ - 0, /* Advanced Interrupt Controller (IRQ3) */ - 0, /* Advanced Interrupt Controller (IRQ4) */ - 0, /* Advanced Interrupt Controller (IRQ5) */ - 0 /* Advanced Interrupt Controller (IRQ6) */ -}; - -void __init at91rm9200_init_interrupts(unsigned int priority[NR_AIC_IRQS]) -{ - if (!priority) - priority = at91rm9200_default_irq_priority; - - /* Initialize the AIC interrupt controller */ - at91_aic_init(priority); - - /* Enable GPIO interrupts */ - at91_gpio_irq_setup(); -} diff --git a/arch/arm/mach-at91rm9200/at91rm9200_devices.c b/arch/arm/mach-at91rm9200/at91rm9200_devices.c deleted file mode 100644 index 57fac7203fe4..000000000000 --- a/arch/arm/mach-at91rm9200/at91rm9200_devices.c +++ /dev/null @@ -1,875 +0,0 @@ -/* - * arch/arm/mach-at91rm9200/at91rm9200_devices.c - * - * Copyright (C) 2005 Thibaut VARENE - * Copyright (C) 2005 David Brownell - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ -#include -#include - -#include - -#include -#include -#include -#include - -#include "generic.h" - -#define SZ_512 0x00000200 -#define SZ_256 0x00000100 -#define SZ_16 0x00000010 - -/* -------------------------------------------------------------------- - * USB Host - * -------------------------------------------------------------------- */ - -#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) -static u64 ohci_dmamask = 0xffffffffUL; -static struct at91_usbh_data usbh_data; - -static struct resource usbh_resources[] = { - [0] = { - .start = AT91RM9200_UHP_BASE, - .end = AT91RM9200_UHP_BASE + SZ_1M - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91RM9200_ID_UHP, - .end = AT91RM9200_ID_UHP, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device at91rm9200_usbh_device = { - .name = "at91_ohci", - .id = -1, - .dev = { - .dma_mask = &ohci_dmamask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &usbh_data, - }, - .resource = usbh_resources, - .num_resources = ARRAY_SIZE(usbh_resources), -}; - -void __init at91_add_device_usbh(struct at91_usbh_data *data) -{ - if (!data) - return; - - usbh_data = *data; - platform_device_register(&at91rm9200_usbh_device); -} -#else -void __init at91_add_device_usbh(struct at91_usbh_data *data) {} -#endif - - -/* -------------------------------------------------------------------- - * USB Device (Gadget) - * -------------------------------------------------------------------- */ - -#ifdef CONFIG_USB_GADGET_AT91 -static struct at91_udc_data udc_data; - -static struct resource udc_resources[] = { - [0] = { - .start = AT91RM9200_BASE_UDP, - .end = AT91RM9200_BASE_UDP + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91RM9200_ID_UDP, - .end = AT91RM9200_ID_UDP, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device at91rm9200_udc_device = { - .name = "at91_udc", - .id = -1, - .dev = { - .platform_data = &udc_data, - }, - .resource = udc_resources, - .num_resources = ARRAY_SIZE(udc_resources), -}; - -void __init at91_add_device_udc(struct at91_udc_data *data) -{ - if (!data) - return; - - if (data->vbus_pin) { - at91_set_gpio_input(data->vbus_pin, 0); - at91_set_deglitch(data->vbus_pin, 1); - } - if (data->pullup_pin) - at91_set_gpio_output(data->pullup_pin, 0); - - udc_data = *data; - platform_device_register(&at91rm9200_udc_device); -} -#else -void __init at91_add_device_udc(struct at91_udc_data *data) {} -#endif - - -/* -------------------------------------------------------------------- - * Ethernet - * -------------------------------------------------------------------- */ - -#if defined(CONFIG_ARM_AT91_ETHER) || defined(CONFIG_ARM_AT91_ETHER_MODULE) -static u64 eth_dmamask = 0xffffffffUL; -static struct at91_eth_data eth_data; - -static struct resource eth_resources[] = { - [0] = { - .start = AT91_VA_BASE_EMAC, - .end = AT91_VA_BASE_EMAC + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91RM9200_ID_EMAC, - .end = AT91RM9200_ID_EMAC, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device at91rm9200_eth_device = { - .name = "at91_ether", - .id = -1, - .dev = { - .dma_mask = ð_dmamask, - .coherent_dma_mask = 0xffffffff, - .platform_data = ð_data, - }, - .resource = eth_resources, - .num_resources = ARRAY_SIZE(eth_resources), -}; - -void __init at91_add_device_eth(struct at91_eth_data *data) -{ - if (!data) - return; - - if (data->phy_irq_pin) { - at91_set_gpio_input(data->phy_irq_pin, 0); - at91_set_deglitch(data->phy_irq_pin, 1); - } - - /* Pins used for MII and RMII */ - at91_set_A_periph(AT91_PIN_PA16, 0); /* EMDIO */ - at91_set_A_periph(AT91_PIN_PA15, 0); /* EMDC */ - at91_set_A_periph(AT91_PIN_PA14, 0); /* ERXER */ - at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */ - at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */ - at91_set_A_periph(AT91_PIN_PA11, 0); /* ECRS_ECRSDV */ - at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX1 */ - at91_set_A_periph(AT91_PIN_PA9, 0); /* ETX0 */ - at91_set_A_periph(AT91_PIN_PA8, 0); /* ETXEN */ - at91_set_A_periph(AT91_PIN_PA7, 0); /* ETXCK_EREFCK */ - - if (!data->is_rmii) { - at91_set_B_periph(AT91_PIN_PB19, 0); /* ERXCK */ - at91_set_B_periph(AT91_PIN_PB18, 0); /* ECOL */ - at91_set_B_periph(AT91_PIN_PB17, 0); /* ERXDV */ - at91_set_B_periph(AT91_PIN_PB16, 0); /* ERX3 */ - at91_set_B_periph(AT91_PIN_PB15, 0); /* ERX2 */ - at91_set_B_periph(AT91_PIN_PB14, 0); /* ETXER */ - at91_set_B_periph(AT91_PIN_PB13, 0); /* ETX3 */ - at91_set_B_periph(AT91_PIN_PB12, 0); /* ETX2 */ - } - - eth_data = *data; - platform_device_register(&at91rm9200_eth_device); -} -#else -void __init at91_add_device_eth(struct at91_eth_data *data) {} -#endif - - -/* -------------------------------------------------------------------- - * Compact Flash / PCMCIA - * -------------------------------------------------------------------- */ - -#if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) -static struct at91_cf_data cf_data; - -#define CF_BASE AT91_CHIPSELECT_4 - -static struct resource cf_resources[] = { - [0] = { - .start = CF_BASE, - /* ties up CS4, CS5 and CS6 */ - .end = CF_BASE + (0x30000000 - 1), - .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT, - }, -}; - -static struct platform_device at91rm9200_cf_device = { - .name = "at91_cf", - .id = -1, - .dev = { - .platform_data = &cf_data, - }, - .resource = cf_resources, - .num_resources = ARRAY_SIZE(cf_resources), -}; - -void __init at91_add_device_cf(struct at91_cf_data *data) -{ - unsigned int csa; - - if (!data) - return; - - data->chipselect = 4; /* can only use EBI ChipSelect 4 */ - - /* CF takes over CS4, CS5, CS6 */ - csa = at91_sys_read(AT91_EBI_CSA); - at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH); - - /* - * Static memory controller timing adjustments. - * REVISIT: these timings are in terms of MCK cycles, so - * when MCK changes (cpufreq etc) so must these values... - */ - at91_sys_write(AT91_SMC_CSR(4), - AT91_SMC_ACSS_STD - | AT91_SMC_DBW_16 - | AT91_SMC_BAT - | AT91_SMC_WSEN - | AT91_SMC_NWS_(32) /* wait states */ - | AT91_SMC_RWSETUP_(6) /* setup time */ - | AT91_SMC_RWHOLD_(4) /* hold time */ - ); - - /* input/irq */ - if (data->irq_pin) { - at91_set_gpio_input(data->irq_pin, 1); - at91_set_deglitch(data->irq_pin, 1); - } - at91_set_gpio_input(data->det_pin, 1); - at91_set_deglitch(data->det_pin, 1); - - /* outputs, initially off */ - if (data->vcc_pin) - at91_set_gpio_output(data->vcc_pin, 0); - at91_set_gpio_output(data->rst_pin, 0); - - /* force poweron defaults for these pins ... */ - at91_set_A_periph(AT91_PIN_PC9, 0); /* A25/CFRNW */ - at91_set_A_periph(AT91_PIN_PC10, 0); /* NCS4/CFCS */ - at91_set_A_periph(AT91_PIN_PC11, 0); /* NCS5/CFCE1 */ - at91_set_A_periph(AT91_PIN_PC12, 0); /* NCS6/CFCE2 */ - - /* nWAIT is _not_ a default setting */ - at91_set_A_periph(AT91_PIN_PC6, 1); /* nWAIT */ - - cf_data = *data; - platform_device_register(&at91rm9200_cf_device); -} -#else -void __init at91_add_device_cf(struct at91_cf_data *data) {} -#endif - - -/* -------------------------------------------------------------------- - * MMC / SD - * -------------------------------------------------------------------- */ - -#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE) -static u64 mmc_dmamask = 0xffffffffUL; -static struct at91_mmc_data mmc_data; - -static struct resource mmc_resources[] = { - [0] = { - .start = AT91RM9200_BASE_MCI, - .end = AT91RM9200_BASE_MCI + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91RM9200_ID_MCI, - .end = AT91RM9200_ID_MCI, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device at91rm9200_mmc_device = { - .name = "at91_mci", - .id = -1, - .dev = { - .dma_mask = &mmc_dmamask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &mmc_data, - }, - .resource = mmc_resources, - .num_resources = ARRAY_SIZE(mmc_resources), -}; - -void __init at91_add_device_mmc(struct at91_mmc_data *data) -{ - if (!data) - return; - - /* input/irq */ - if (data->det_pin) { - at91_set_gpio_input(data->det_pin, 1); - at91_set_deglitch(data->det_pin, 1); - } - if (data->wp_pin) - at91_set_gpio_input(data->wp_pin, 1); - if (data->vcc_pin) - at91_set_gpio_output(data->vcc_pin, 0); - - /* CLK */ - at91_set_A_periph(AT91_PIN_PA27, 0); - - if (data->slot_b) { - /* CMD */ - at91_set_B_periph(AT91_PIN_PA8, 1); - - /* DAT0, maybe DAT1..DAT3 */ - at91_set_B_periph(AT91_PIN_PA9, 1); - if (data->wire4) { - at91_set_B_periph(AT91_PIN_PA10, 1); - at91_set_B_periph(AT91_PIN_PA11, 1); - at91_set_B_periph(AT91_PIN_PA12, 1); - } - } else { - /* CMD */ - at91_set_A_periph(AT91_PIN_PA28, 1); - - /* DAT0, maybe DAT1..DAT3 */ - at91_set_A_periph(AT91_PIN_PA29, 1); - if (data->wire4) { - at91_set_B_periph(AT91_PIN_PB3, 1); - at91_set_B_periph(AT91_PIN_PB4, 1); - at91_set_B_periph(AT91_PIN_PB5, 1); - } - } - - mmc_data = *data; - platform_device_register(&at91rm9200_mmc_device); -} -#else -void __init at91_add_device_mmc(struct at91_mmc_data *data) {} -#endif - - -/* -------------------------------------------------------------------- - * NAND / SmartMedia - * -------------------------------------------------------------------- */ - -#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE) -static struct at91_nand_data nand_data; - -#define NAND_BASE AT91_CHIPSELECT_3 - -static struct resource nand_resources[] = { - { - .start = NAND_BASE, - .end = NAND_BASE + SZ_8M - 1, - .flags = IORESOURCE_MEM, - } -}; - -static struct platform_device at91rm9200_nand_device = { - .name = "at91_nand", - .id = -1, - .dev = { - .platform_data = &nand_data, - }, - .resource = nand_resources, - .num_resources = ARRAY_SIZE(nand_resources), -}; - -void __init at91_add_device_nand(struct at91_nand_data *data) -{ - unsigned int csa; - - if (!data) - return; - - /* enable the address range of CS3 */ - csa = at91_sys_read(AT91_EBI_CSA); - at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA); - - /* set the bus interface characteristics */ - at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN - | AT91_SMC_NWS_(5) - | AT91_SMC_TDF_(1) - | AT91_SMC_RWSETUP_(0) /* tDS Data Set up Time 30 - ns */ - | AT91_SMC_RWHOLD_(1) /* tDH Data Hold Time 20 - ns */ - ); - - /* enable pin */ - if (data->enable_pin) - at91_set_gpio_output(data->enable_pin, 1); - - /* ready/busy pin */ - if (data->rdy_pin) - at91_set_gpio_input(data->rdy_pin, 1); - - /* card detect pin */ - if (data->det_pin) - at91_set_gpio_input(data->det_pin, 1); - - at91_set_A_periph(AT91_PIN_PC1, 0); /* SMOE */ - at91_set_A_periph(AT91_PIN_PC3, 0); /* SMWE */ - - nand_data = *data; - platform_device_register(&at91rm9200_nand_device); -} -#else -void __init at91_add_device_nand(struct at91_nand_data *data) {} -#endif - - -/* -------------------------------------------------------------------- - * TWI (i2c) - * -------------------------------------------------------------------- */ - -#if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE) - -static struct resource twi_resources[] = { - [0] = { - .start = AT91RM9200_BASE_TWI, - .end = AT91RM9200_BASE_TWI + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91RM9200_ID_TWI, - .end = AT91RM9200_ID_TWI, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device at91rm9200_twi_device = { - .name = "at91_i2c", - .id = -1, - .resource = twi_resources, - .num_resources = ARRAY_SIZE(twi_resources), -}; - -void __init at91_add_device_i2c(void) -{ - /* pins used for TWI interface */ - at91_set_A_periph(AT91_PIN_PA25, 0); /* TWD */ - at91_set_multi_drive(AT91_PIN_PA25, 1); - - at91_set_A_periph(AT91_PIN_PA26, 0); /* TWCK */ - at91_set_multi_drive(AT91_PIN_PA26, 1); - - platform_device_register(&at91rm9200_twi_device); -} -#else -void __init at91_add_device_i2c(void) {} -#endif - - -/* -------------------------------------------------------------------- - * SPI - * -------------------------------------------------------------------- */ - -#if defined(CONFIG_SPI_AT91) || defined(CONFIG_SPI_AT91_MODULE) || defined(CONFIG_AT91_SPI) || defined(CONFIG_AT91_SPI_MODULE) -static u64 spi_dmamask = 0xffffffffUL; - -static struct resource spi_resources[] = { - [0] = { - .start = AT91RM9200_BASE_SPI, - .end = AT91RM9200_BASE_SPI + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91RM9200_ID_SPI, - .end = AT91RM9200_ID_SPI, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device at91rm9200_spi_device = { - .name = "at91_spi", - .id = 0, - .dev = { - .dma_mask = &spi_dmamask, - .coherent_dma_mask = 0xffffffff, - }, - .resource = spi_resources, - .num_resources = ARRAY_SIZE(spi_resources), -}; - -static const unsigned spi_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 }; - -void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) -{ - int i; - unsigned long cs_pin; - - at91_set_A_periph(AT91_PIN_PA0, 0); /* MISO */ - at91_set_A_periph(AT91_PIN_PA1, 0); /* MOSI */ - at91_set_A_periph(AT91_PIN_PA2, 0); /* SPCK */ - - /* Enable SPI chip-selects */ - for (i = 0; i < nr_devices; i++) { - if (devices[i].controller_data) - cs_pin = (unsigned long) devices[i].controller_data; - else - cs_pin = spi_standard_cs[devices[i].chip_select]; - -#ifdef CONFIG_SPI_AT91_MANUAL_CS - at91_set_gpio_output(cs_pin, 1); -#else - at91_set_A_periph(cs_pin, 0); -#endif - - /* pass chip-select pin to driver */ - devices[i].controller_data = (void *) cs_pin; - } - - spi_register_board_info(devices, nr_devices); - at91_clock_associate("spi_clk", &at91rm9200_spi_device.dev, "spi"); - platform_device_register(&at91rm9200_spi_device); -} -#else -void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {} -#endif - - -/* -------------------------------------------------------------------- - * RTC - * -------------------------------------------------------------------- */ - -#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE) -static struct platform_device at91rm9200_rtc_device = { - .name = "at91_rtc", - .id = -1, - .num_resources = 0, -}; - -static void __init at91_add_device_rtc(void) -{ - platform_device_register(&at91rm9200_rtc_device); -} -#else -static void __init at91_add_device_rtc(void) {} -#endif - - -/* -------------------------------------------------------------------- - * Watchdog - * -------------------------------------------------------------------- */ - -#if defined(CONFIG_AT91RM9200_WATCHDOG) || defined(CONFIG_AT91RM9200_WATCHDOG_MODULE) -static struct platform_device at91rm9200_wdt_device = { - .name = "at91_wdt", - .id = -1, - .num_resources = 0, -}; - -static void __init at91_add_device_watchdog(void) -{ - platform_device_register(&at91rm9200_wdt_device); -} -#else -static void __init at91_add_device_watchdog(void) {} -#endif - - -/* -------------------------------------------------------------------- - * LEDs - * -------------------------------------------------------------------- */ - -#if defined(CONFIG_LEDS) -u8 at91_leds_cpu; -u8 at91_leds_timer; - -void __init at91_init_leds(u8 cpu_led, u8 timer_led) -{ - at91_leds_cpu = cpu_led; - at91_leds_timer = timer_led; -} -#else -void __init at91_init_leds(u8 cpu_led, u8 timer_led) {} -#endif - - -/* -------------------------------------------------------------------- - * UART - * -------------------------------------------------------------------- */ - -#if defined(CONFIG_SERIAL_ATMEL) -static struct resource dbgu_resources[] = { - [0] = { - .start = AT91_VA_BASE_SYS + AT91_DBGU, - .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91_ID_SYS, - .end = AT91_ID_SYS, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct atmel_uart_data dbgu_data = { - .use_dma_tx = 0, - .use_dma_rx = 0, /* DBGU not capable of receive DMA */ - .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU), -}; - -static struct platform_device at91rm9200_dbgu_device = { - .name = "atmel_usart", - .id = 0, - .dev = { - .platform_data = &dbgu_data, - .coherent_dma_mask = 0xffffffff, - }, - .resource = dbgu_resources, - .num_resources = ARRAY_SIZE(dbgu_resources), -}; - -static inline void configure_dbgu_pins(void) -{ - at91_set_A_periph(AT91_PIN_PA30, 0); /* DRXD */ - at91_set_A_periph(AT91_PIN_PA31, 1); /* DTXD */ -} - -static struct resource uart0_resources[] = { - [0] = { - .start = AT91RM9200_BASE_US0, - .end = AT91RM9200_BASE_US0 + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91RM9200_ID_US0, - .end = AT91RM9200_ID_US0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct atmel_uart_data uart0_data = { - .use_dma_tx = 1, - .use_dma_rx = 1, -}; - -static struct platform_device at91rm9200_uart0_device = { - .name = "atmel_usart", - .id = 1, - .dev = { - .platform_data = &uart0_data, - .coherent_dma_mask = 0xffffffff, - }, - .resource = uart0_resources, - .num_resources = ARRAY_SIZE(uart0_resources), -}; - -static inline void configure_usart0_pins(void) -{ - at91_set_A_periph(AT91_PIN_PA17, 1); /* TXD0 */ - at91_set_A_periph(AT91_PIN_PA18, 0); /* RXD0 */ - at91_set_A_periph(AT91_PIN_PA20, 0); /* CTS0 */ - - /* - * AT91RM9200 Errata #39 - RTS0 is not internally connected to PA21. - * We need to drive the pin manually. Default is off (RTS is active low). - */ - at91_set_gpio_output(AT91_PIN_PA21, 1); -} - -static struct resource uart1_resources[] = { - [0] = { - .start = AT91RM9200_BASE_US1, - .end = AT91RM9200_BASE_US1 + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91RM9200_ID_US1, - .end = AT91RM9200_ID_US1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct atmel_uart_data uart1_data = { - .use_dma_tx = 1, - .use_dma_rx = 1, -}; - -static struct platform_device at91rm9200_uart1_device = { - .name = "atmel_usart", - .id = 2, - .dev = { - .platform_data = &uart1_data, - .coherent_dma_mask = 0xffffffff, - }, - .resource = uart1_resources, - .num_resources = ARRAY_SIZE(uart1_resources), -}; - -static inline void configure_usart1_pins(void) -{ - at91_set_A_periph(AT91_PIN_PB18, 0); /* RI1 */ - at91_set_A_periph(AT91_PIN_PB19, 0); /* DTR1 */ - at91_set_A_periph(AT91_PIN_PB20, 1); /* TXD1 */ - at91_set_A_periph(AT91_PIN_PB21, 0); /* RXD1 */ - at91_set_A_periph(AT91_PIN_PB23, 0); /* DCD1 */ - at91_set_A_periph(AT91_PIN_PB24, 0); /* CTS1 */ - at91_set_A_periph(AT91_PIN_PB25, 0); /* DSR1 */ - at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS1 */ -} - -static struct resource uart2_resources[] = { - [0] = { - .start = AT91RM9200_BASE_US2, - .end = AT91RM9200_BASE_US2 + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91RM9200_ID_US2, - .end = AT91RM9200_ID_US2, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct atmel_uart_data uart2_data = { - .use_dma_tx = 1, - .use_dma_rx = 1, -}; - -static struct platform_device at91rm9200_uart2_device = { - .name = "atmel_usart", - .id = 3, - .dev = { - .platform_data = &uart2_data, - .coherent_dma_mask = 0xffffffff, - }, - .resource = uart2_resources, - .num_resources = ARRAY_SIZE(uart2_resources), -}; - -static inline void configure_usart2_pins(void) -{ - at91_set_A_periph(AT91_PIN_PA22, 0); /* RXD2 */ - at91_set_A_periph(AT91_PIN_PA23, 1); /* TXD2 */ -} - -static struct resource uart3_resources[] = { - [0] = { - .start = AT91RM9200_BASE_US3, - .end = AT91RM9200_BASE_US3 + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91RM9200_ID_US3, - .end = AT91RM9200_ID_US3, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct atmel_uart_data uart3_data = { - .use_dma_tx = 1, - .use_dma_rx = 1, -}; - -static struct platform_device at91rm9200_uart3_device = { - .name = "atmel_usart", - .id = 4, - .dev = { - .platform_data = &uart3_data, - .coherent_dma_mask = 0xffffffff, - }, - .resource = uart3_resources, - .num_resources = ARRAY_SIZE(uart3_resources), -}; - -static inline void configure_usart3_pins(void) -{ - at91_set_B_periph(AT91_PIN_PA5, 1); /* TXD3 */ - at91_set_B_periph(AT91_PIN_PA6, 0); /* RXD3 */ -} - -struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ -struct platform_device *atmel_default_console_device; /* the serial console device */ - -void __init at91_init_serial(struct at91_uart_config *config) -{ - int i; - - /* Fill in list of supported UARTs */ - for (i = 0; i < config->nr_tty; i++) { - switch (config->tty_map[i]) { - case 0: - configure_usart0_pins(); - at91_uarts[i] = &at91rm9200_uart0_device; - at91_clock_associate("usart0_clk", &at91rm9200_uart0_device.dev, "usart"); - break; - case 1: - configure_usart1_pins(); - at91_uarts[i] = &at91rm9200_uart1_device; - at91_clock_associate("usart1_clk", &at91rm9200_uart1_device.dev, "usart"); - break; - case 2: - configure_usart2_pins(); - at91_uarts[i] = &at91rm9200_uart2_device; - at91_clock_associate("usart2_clk", &at91rm9200_uart2_device.dev, "usart"); - break; - case 3: - configure_usart3_pins(); - at91_uarts[i] = &at91rm9200_uart3_device; - at91_clock_associate("usart3_clk", &at91rm9200_uart3_device.dev, "usart"); - break; - case 4: - configure_dbgu_pins(); - at91_uarts[i] = &at91rm9200_dbgu_device; - at91_clock_associate("mck", &at91rm9200_dbgu_device.dev, "usart"); - break; - default: - continue; - } - at91_uarts[i]->id = i; /* update ID number to mapped ID */ - } - - /* Set serial console device */ - if (config->console_tty < ATMEL_MAX_UART) - atmel_default_console_device = at91_uarts[config->console_tty]; - if (!atmel_default_console_device) - printk(KERN_INFO "AT91: No default serial console defined.\n"); -} - -void __init at91_add_device_serial(void) -{ - int i; - - for (i = 0; i < ATMEL_MAX_UART; i++) { - if (at91_uarts[i]) - platform_device_register(at91_uarts[i]); - } -} -#else -void __init at91_init_serial(struct at91_uart_config *config) {} -void __init at91_add_device_serial(void) {} -#endif - - -/* -------------------------------------------------------------------- */ - -/* - * These devices are always present and don't need any board-specific - * setup. - */ -static int __init at91_add_standard_devices(void) -{ - at91_add_device_rtc(); - at91_add_device_watchdog(); - return 0; -} - -arch_initcall(at91_add_standard_devices); diff --git a/arch/arm/mach-at91rm9200/at91rm9200_time.c b/arch/arm/mach-at91rm9200/at91rm9200_time.c deleted file mode 100644 index b999e192a7e9..000000000000 --- a/arch/arm/mach-at91rm9200/at91rm9200_time.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * linux/arch/arm/mach-at91rm9200/at91rm9200_time.c - * - * Copyright (C) 2003 SAN People - * Copyright (C) 2003 ATMEL - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -static unsigned long last_crtr; - -/* - * The ST_CRTR is updated asynchronously to the master clock. It is therefore - * necessary to read it twice (with the same value) to ensure accuracy. - */ -static inline unsigned long read_CRTR(void) { - unsigned long x1, x2; - - do { - x1 = at91_sys_read(AT91_ST_CRTR); - x2 = at91_sys_read(AT91_ST_CRTR); - } while (x1 != x2); - - return x1; -} - -/* - * Returns number of microseconds since last timer interrupt. Note that interrupts - * will have been disabled by do_gettimeofday() - * 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy. - * 'tick' is usecs per jiffy (linux/timex.h). - */ -static unsigned long at91rm9200_gettimeoffset(void) -{ - unsigned long elapsed; - - elapsed = (read_CRTR() - last_crtr) & AT91_ST_ALMV; - - return (unsigned long)(elapsed * (tick_nsec / 1000)) / LATCH; -} - -/* - * IRQ handler for the timer. - */ -static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id) -{ - if (at91_sys_read(AT91_ST_SR) & AT91_ST_PITS) { /* This is a shared interrupt */ - write_seqlock(&xtime_lock); - - while (((read_CRTR() - last_crtr) & AT91_ST_ALMV) >= LATCH) { - timer_tick(); - last_crtr = (last_crtr + LATCH) & AT91_ST_ALMV; - } - - write_sequnlock(&xtime_lock); - - return IRQ_HANDLED; - } - else - return IRQ_NONE; /* not handled */ -} - -static struct irqaction at91rm9200_timer_irq = { - .name = "at91_tick", - .flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER, - .handler = at91rm9200_timer_interrupt -}; - -void at91rm9200_timer_reset(void) -{ - last_crtr = 0; - - /* Real time counter incremented every 30.51758 microseconds */ - at91_sys_write(AT91_ST_RTMR, 1); - - /* Set Period Interval timer */ - at91_sys_write(AT91_ST_PIMR, LATCH); - - /* Clear any pending interrupts */ - (void) at91_sys_read(AT91_ST_SR); - - /* Enable Period Interval Timer interrupt */ - at91_sys_write(AT91_ST_IER, AT91_ST_PITS); -} - -/* - * Set up timer interrupt. - */ -void __init at91rm9200_timer_init(void) -{ - /* Disable all timer interrupts */ - at91_sys_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS); - (void) at91_sys_read(AT91_ST_SR); /* Clear any pending interrupts */ - - /* Make IRQs happen for the system timer */ - setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq); - - /* Change the kernel's 'tick' value to 10009 usec. (the default is 10000) */ - tick_usec = (LATCH * 1000000) / CLOCK_TICK_RATE; - - /* Initialize and enable the timer interrupt */ - at91rm9200_timer_reset(); -} - -#ifdef CONFIG_PM -static void at91rm9200_timer_suspend(void) -{ - /* disable Period Interval Timer interrupt */ - at91_sys_write(AT91_ST_IDR, AT91_ST_PITS); -} -#else -#define at91rm9200_timer_suspend NULL -#endif - -struct sys_timer at91rm9200_timer = { - .init = at91rm9200_timer_init, - .offset = at91rm9200_gettimeoffset, - .suspend = at91rm9200_timer_suspend, - .resume = at91rm9200_timer_reset, -}; - diff --git a/arch/arm/mach-at91rm9200/at91sam9260.c b/arch/arm/mach-at91rm9200/at91sam9260.c deleted file mode 100644 index b14871adc300..000000000000 --- a/arch/arm/mach-at91rm9200/at91sam9260.c +++ /dev/null @@ -1,295 +0,0 @@ -/* - * arch/arm/mach-at91rm9200/at91sam9260.c - * - * Copyright (C) 2006 SAN People - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ - -#include - -#include -#include -#include -#include -#include - -#include "generic.h" -#include "clock.h" - -static struct map_desc at91sam9260_io_desc[] __initdata = { - { - .virtual = AT91_VA_BASE_SYS, - .pfn = __phys_to_pfn(AT91_BASE_SYS), - .length = SZ_16K, - .type = MT_DEVICE, - }, { - .virtual = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE, - .pfn = __phys_to_pfn(AT91SAM9260_SRAM0_BASE), - .length = AT91SAM9260_SRAM0_SIZE, - .type = MT_DEVICE, - }, { - .virtual = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE - AT91SAM9260_SRAM1_SIZE, - .pfn = __phys_to_pfn(AT91SAM9260_SRAM1_BASE), - .length = AT91SAM9260_SRAM1_SIZE, - .type = MT_DEVICE, - }, -}; - -/* -------------------------------------------------------------------- - * Clocks - * -------------------------------------------------------------------- */ - -/* - * The peripheral clocks. - */ -static struct clk pioA_clk = { - .name = "pioA_clk", - .pmc_mask = 1 << AT91SAM9260_ID_PIOA, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk pioB_clk = { - .name = "pioB_clk", - .pmc_mask = 1 << AT91SAM9260_ID_PIOB, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk pioC_clk = { - .name = "pioC_clk", - .pmc_mask = 1 << AT91SAM9260_ID_PIOC, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk adc_clk = { - .name = "adc_clk", - .pmc_mask = 1 << AT91SAM9260_ID_ADC, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk usart0_clk = { - .name = "usart0_clk", - .pmc_mask = 1 << AT91SAM9260_ID_US0, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk usart1_clk = { - .name = "usart1_clk", - .pmc_mask = 1 << AT91SAM9260_ID_US1, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk usart2_clk = { - .name = "usart2_clk", - .pmc_mask = 1 << AT91SAM9260_ID_US2, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk mmc_clk = { - .name = "mci_clk", - .pmc_mask = 1 << AT91SAM9260_ID_MCI, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk udc_clk = { - .name = "udc_clk", - .pmc_mask = 1 << AT91SAM9260_ID_UDP, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk twi_clk = { - .name = "twi_clk", - .pmc_mask = 1 << AT91SAM9260_ID_TWI, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk spi0_clk = { - .name = "spi0_clk", - .pmc_mask = 1 << AT91SAM9260_ID_SPI0, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk spi1_clk = { - .name = "spi1_clk", - .pmc_mask = 1 << AT91SAM9260_ID_SPI1, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk ohci_clk = { - .name = "ohci_clk", - .pmc_mask = 1 << AT91SAM9260_ID_UHP, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk ether_clk = { - .name = "ether_clk", - .pmc_mask = 1 << AT91SAM9260_ID_EMAC, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk isi_clk = { - .name = "isi_clk", - .pmc_mask = 1 << AT91SAM9260_ID_ISI, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk usart3_clk = { - .name = "usart3_clk", - .pmc_mask = 1 << AT91SAM9260_ID_US3, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk usart4_clk = { - .name = "usart4_clk", - .pmc_mask = 1 << AT91SAM9260_ID_US4, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk usart5_clk = { - .name = "usart5_clk", - .pmc_mask = 1 << AT91SAM9260_ID_US5, - .type = CLK_TYPE_PERIPHERAL, -}; - -static struct clk *periph_clocks[] __initdata = { - &pioA_clk, - &pioB_clk, - &pioC_clk, - &adc_clk, - &usart0_clk, - &usart1_clk, - &usart2_clk, - &mmc_clk, - &udc_clk, - &twi_clk, - &spi0_clk, - &spi1_clk, - // ssc - // tc0 .. tc2 - &ohci_clk, - ðer_clk, - &isi_clk, - &usart3_clk, - &usart4_clk, - &usart5_clk, - // tc3 .. tc5 - // irq0 .. irq2 -}; - -/* - * The two programmable clocks. - * You must configure pin multiplexing to bring these signals out. - */ -static struct clk pck0 = { - .name = "pck0", - .pmc_mask = AT91_PMC_PCK0, - .type = CLK_TYPE_PROGRAMMABLE, - .id = 0, -}; -static struct clk pck1 = { - .name = "pck1", - .pmc_mask = AT91_PMC_PCK1, - .type = CLK_TYPE_PROGRAMMABLE, - .id = 1, -}; - -static void __init at91sam9260_register_clocks(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) - clk_register(periph_clocks[i]); - - clk_register(&pck0); - clk_register(&pck1); -} - -/* -------------------------------------------------------------------- - * GPIO - * -------------------------------------------------------------------- */ - -static struct at91_gpio_bank at91sam9260_gpio[] = { - { - .id = AT91SAM9260_ID_PIOA, - .offset = AT91_PIOA, - .clock = &pioA_clk, - }, { - .id = AT91SAM9260_ID_PIOB, - .offset = AT91_PIOB, - .clock = &pioB_clk, - }, { - .id = AT91SAM9260_ID_PIOC, - .offset = AT91_PIOC, - .clock = &pioC_clk, - } -}; - -static void at91sam9260_reset(void) -{ - at91_sys_write(AT91_RSTC_CR, (0xA5 << 24) | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); -} - - -/* -------------------------------------------------------------------- - * AT91SAM9260 processor initialization - * -------------------------------------------------------------------- */ - -void __init at91sam9260_initialize(unsigned long main_clock) -{ - /* Map peripherals */ - iotable_init(at91sam9260_io_desc, ARRAY_SIZE(at91sam9260_io_desc)); - - at91_arch_reset = at91sam9260_reset; - at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1) - | (1 << AT91SAM9260_ID_IRQ2); - - /* Init clock subsystem */ - at91_clock_init(main_clock); - - /* Register the processor-specific clocks */ - at91sam9260_register_clocks(); - - /* Register GPIO subsystem */ - at91_gpio_init(at91sam9260_gpio, 3); -} - -/* -------------------------------------------------------------------- - * Interrupt initialization - * -------------------------------------------------------------------- */ - -/* - * The default interrupt priority levels (0 = lowest, 7 = highest). - */ -static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = { - 7, /* Advanced Interrupt Controller */ - 7, /* System Peripherals */ - 0, /* Parallel IO Controller A */ - 0, /* Parallel IO Controller B */ - 0, /* Parallel IO Controller C */ - 0, /* Analog-to-Digital Converter */ - 6, /* USART 0 */ - 6, /* USART 1 */ - 6, /* USART 2 */ - 0, /* Multimedia Card Interface */ - 4, /* USB Device Port */ - 0, /* Two-Wire Interface */ - 6, /* Serial Peripheral Interface 0 */ - 6, /* Serial Peripheral Interface 1 */ - 5, /* Serial Synchronous Controller */ - 0, - 0, - 0, /* Timer Counter 0 */ - 0, /* Timer Counter 1 */ - 0, /* Timer Counter 2 */ - 3, /* USB Host port */ - 3, /* Ethernet */ - 0, /* Image Sensor Interface */ - 6, /* USART 3 */ - 6, /* USART 4 */ - 6, /* USART 5 */ - 0, /* Timer Counter 3 */ - 0, /* Timer Counter 4 */ - 0, /* Timer Counter 5 */ - 0, /* Advanced Interrupt Controller */ - 0, /* Advanced Interrupt Controller */ - 0, /* Advanced Interrupt Controller */ -}; - -void __init at91sam9260_init_interrupts(unsigned int priority[NR_AIC_IRQS]) -{ - if (!priority) - priority = at91sam9260_default_irq_priority; - - /* Initialize the AIC interrupt controller */ - at91_aic_init(priority); - - /* Enable GPIO interrupts */ - at91_gpio_irq_setup(); -} diff --git a/arch/arm/mach-at91rm9200/at91sam9260_devices.c b/arch/arm/mach-at91rm9200/at91sam9260_devices.c deleted file mode 100644 index f338f78eb943..000000000000 --- a/arch/arm/mach-at91rm9200/at91sam9260_devices.c +++ /dev/null @@ -1,867 +0,0 @@ -/* - * arch/arm/mach-at91rm9200/at91sam9260_devices.c - * - * Copyright (C) 2006 Atmel - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ -#include -#include - -#include - -#include -#include -#include -#include -#include - -#include "generic.h" - -#define SZ_512 0x00000200 -#define SZ_256 0x00000100 -#define SZ_16 0x00000010 - -/* -------------------------------------------------------------------- - * USB Host - * -------------------------------------------------------------------- */ - -#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) -static u64 ohci_dmamask = 0xffffffffUL; -static struct at91_usbh_data usbh_data; - -static struct resource usbh_resources[] = { - [0] = { - .start = AT91SAM9260_UHP_BASE, - .end = AT91SAM9260_UHP_BASE + SZ_1M - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91SAM9260_ID_UHP, - .end = AT91SAM9260_ID_UHP, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device at91_usbh_device = { - .name = "at91_ohci", - .id = -1, - .dev = { - .dma_mask = &ohci_dmamask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &usbh_data, - }, - .resource = usbh_resources, - .num_resources = ARRAY_SIZE(usbh_resources), -}; - -void __init at91_add_device_usbh(struct at91_usbh_data *data) -{ - if (!data) - return; - - usbh_data = *data; - platform_device_register(&at91_usbh_device); -} -#else -void __init at91_add_device_usbh(struct at91_usbh_data *data) {} -#endif - - -/* -------------------------------------------------------------------- - * USB Device (Gadget) - * -------------------------------------------------------------------- */ - -#ifdef CONFIG_USB_GADGET_AT91 -static struct at91_udc_data udc_data; - -static struct resource udc_resources[] = { - [0] = { - .start = AT91SAM9260_BASE_UDP, - .end = AT91SAM9260_BASE_UDP + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91SAM9260_ID_UDP, - .end = AT91SAM9260_ID_UDP, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device at91_udc_device = { - .name = "at91_udc", - .id = -1, - .dev = { - .platform_data = &udc_data, - }, - .resource = udc_resources, - .num_resources = ARRAY_SIZE(udc_resources), -}; - -void __init at91_add_device_udc(struct at91_udc_data *data) -{ - if (!data) - return; - - if (data->vbus_pin) { - at91_set_gpio_input(data->vbus_pin, 0); - at91_set_deglitch(data->vbus_pin, 1); - } - - /* Pullup pin is handled internally by USB device peripheral */ - - udc_data = *data; - platform_device_register(&at91_udc_device); -} -#else -void __init at91_add_device_udc(struct at91_udc_data *data) {} -#endif - - -/* -------------------------------------------------------------------- - * Ethernet - * -------------------------------------------------------------------- */ - -#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE) -static u64 eth_dmamask = 0xffffffffUL; -static struct at91_eth_data eth_data; - -static struct resource eth_resources[] = { - [0] = { - .start = AT91SAM9260_BASE_EMAC, - .end = AT91SAM9260_BASE_EMAC + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91SAM9260_ID_EMAC, - .end = AT91SAM9260_ID_EMAC, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device at91sam9260_eth_device = { - .name = "macb", - .id = -1, - .dev = { - .dma_mask = ð_dmamask, - .coherent_dma_mask = 0xffffffff, - .platform_data = ð_data, - }, - .resource = eth_resources, - .num_resources = ARRAY_SIZE(eth_resources), -}; - -void __init at91_add_device_eth(struct at91_eth_data *data) -{ - if (!data) - return; - - if (data->phy_irq_pin) { - at91_set_gpio_input(data->phy_irq_pin, 0); - at91_set_deglitch(data->phy_irq_pin, 1); - } - - /* Pins used for MII and RMII */ - at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */ - at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */ - at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */ - at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */ - at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */ - at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */ - at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */ - at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */ - at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */ - at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */ - - if (!data->is_rmii) { - at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */ - at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */ - at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */ - at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */ - at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */ - at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */ - at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */ - at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */ - } - - eth_data = *data; - platform_device_register(&at91sam9260_eth_device); -} -#else -void __init at91_add_device_eth(struct at91_eth_data *data) {} -#endif - - -/* -------------------------------------------------------------------- - * MMC / SD - * -------------------------------------------------------------------- */ - -#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE) -static u64 mmc_dmamask = 0xffffffffUL; -static struct at91_mmc_data mmc_data; - -static struct resource mmc_resources[] = { - [0] = { - .start = AT91SAM9260_BASE_MCI, - .end = AT91SAM9260_BASE_MCI + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91SAM9260_ID_MCI, - .end = AT91SAM9260_ID_MCI, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device at91sam9260_mmc_device = { - .name = "at91_mci", - .id = -1, - .dev = { - .dma_mask = &mmc_dmamask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &mmc_data, - }, - .resource = mmc_resources, - .num_resources = ARRAY_SIZE(mmc_resources), -}; - -void __init at91_add_device_mmc(struct at91_mmc_data *data) -{ - if (!data) - return; - - /* input/irq */ - if (data->det_pin) { - at91_set_gpio_input(data->det_pin, 1); - at91_set_deglitch(data->det_pin, 1); - } - if (data->wp_pin) - at91_set_gpio_input(data->wp_pin, 1); - if (data->vcc_pin) - at91_set_gpio_output(data->vcc_pin, 0); - - /* CLK */ - at91_set_A_periph(AT91_PIN_PA8, 0); - - if (data->slot_b) { - /* CMD */ - at91_set_B_periph(AT91_PIN_PA1, 1); - - /* DAT0, maybe DAT1..DAT3 */ - at91_set_B_periph(AT91_PIN_PA0, 1); - if (data->wire4) { - at91_set_B_periph(AT91_PIN_PA5, 1); - at91_set_B_periph(AT91_PIN_PA4, 1); - at91_set_B_periph(AT91_PIN_PA3, 1); - } - } else { - /* CMD */ - at91_set_A_periph(AT91_PIN_PA7, 1); - - /* DAT0, maybe DAT1..DAT3 */ - at91_set_A_periph(AT91_PIN_PA6, 1); - if (data->wire4) { - at91_set_A_periph(AT91_PIN_PA9, 1); - at91_set_A_periph(AT91_PIN_PA10, 1); - at91_set_A_periph(AT91_PIN_PA11, 1); - } - } - - mmc_data = *data; - platform_device_register(&at91sam9260_mmc_device); -} -#else -void __init at91_add_device_mmc(struct at91_mmc_data *data) {} -#endif - - -/* -------------------------------------------------------------------- - * NAND / SmartMedia - * -------------------------------------------------------------------- */ - -#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE) -static struct at91_nand_data nand_data; - -#define NAND_BASE AT91_CHIPSELECT_3 - -static struct resource nand_resources[] = { - { - .start = NAND_BASE, - .end = NAND_BASE + SZ_8M - 1, - .flags = IORESOURCE_MEM, - } -}; - -static struct platform_device at91sam9260_nand_device = { - .name = "at91_nand", - .id = -1, - .dev = { - .platform_data = &nand_data, - }, - .resource = nand_resources, - .num_resources = ARRAY_SIZE(nand_resources), -}; - -void __init at91_add_device_nand(struct at91_nand_data *data) -{ - unsigned long csa, mode; - - if (!data) - return; - - csa = at91_sys_read(AT91_MATRIX_EBICSA); - at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC); - - /* set the bus interface characteristics */ - at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) - | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); - - at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5) - | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5)); - - at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7)); - - if (data->bus_width_16) - mode = AT91_SMC_DBW_16; - else - mode = AT91_SMC_DBW_8; - at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1)); - - /* enable pin */ - if (data->enable_pin) - at91_set_gpio_output(data->enable_pin, 1); - - /* ready/busy pin */ - if (data->rdy_pin) - at91_set_gpio_input(data->rdy_pin, 1); - - /* card detect pin */ - if (data->det_pin) - at91_set_gpio_input(data->det_pin, 1); - - nand_data = *data; - platform_device_register(&at91sam9260_nand_device); -} -#else -void __init at91_add_device_nand(struct at91_nand_data *data) {} -#endif - - -/* -------------------------------------------------------------------- - * TWI (i2c) - * -------------------------------------------------------------------- */ - -#if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE) - -static struct resource twi_resources[] = { - [0] = { - .start = AT91SAM9260_BASE_TWI, - .end = AT91SAM9260_BASE_TWI + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91SAM9260_ID_TWI, - .end = AT91SAM9260_ID_TWI, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device at91sam9260_twi_device = { - .name = "at91_i2c", - .id = -1, - .resource = twi_resources, - .num_resources = ARRAY_SIZE(twi_resources), -}; - -void __init at91_add_device_i2c(void) -{ - /* pins used for TWI interface */ - at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */ - at91_set_multi_drive(AT91_PIN_PA23, 1); - - at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */ - at91_set_multi_drive(AT91_PIN_PA24, 1); - - platform_device_register(&at91sam9260_twi_device); -} -#else -void __init at91_add_device_i2c(void) {} -#endif - - -/* -------------------------------------------------------------------- - * SPI - * -------------------------------------------------------------------- */ - -#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE) -static u64 spi_dmamask = 0xffffffffUL; - -static struct resource spi0_resources[] = { - [0] = { - .start = AT91SAM9260_BASE_SPI0, - .end = AT91SAM9260_BASE_SPI0 + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91SAM9260_ID_SPI0, - .end = AT91SAM9260_ID_SPI0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device at91sam9260_spi0_device = { - .name = "atmel_spi", - .id = 0, - .dev = { - .dma_mask = &spi_dmamask, - .coherent_dma_mask = 0xffffffff, - }, - .resource = spi0_resources, - .num_resources = ARRAY_SIZE(spi0_resources), -}; - -static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PC11, AT91_PIN_PC16, AT91_PIN_PC17 }; - -static struct resource spi1_resources[] = { - [0] = { - .start = AT91SAM9260_BASE_SPI1, - .end = AT91SAM9260_BASE_SPI1 + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91SAM9260_ID_SPI1, - .end = AT91SAM9260_ID_SPI1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device at91sam9260_spi1_device = { - .name = "atmel_spi", - .id = 1, - .dev = { - .dma_mask = &spi_dmamask, - .coherent_dma_mask = 0xffffffff, - }, - .resource = spi1_resources, - .num_resources = ARRAY_SIZE(spi1_resources), -}; - -static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PC5, AT91_PIN_PC4, AT91_PIN_PC3 }; - -void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) -{ - int i; - unsigned long cs_pin; - short enable_spi0 = 0; - short enable_spi1 = 0; - - /* Choose SPI chip-selects */ - for (i = 0; i < nr_devices; i++) { - if (devices[i].controller_data) - cs_pin = (unsigned long) devices[i].controller_data; - else if (devices[i].bus_num == 0) - cs_pin = spi0_standard_cs[devices[i].chip_select]; - else - cs_pin = spi1_standard_cs[devices[i].chip_select]; - - if (devices[i].bus_num == 0) - enable_spi0 = 1; - else - enable_spi1 = 1; - - /* enable chip-select pin */ - at91_set_gpio_output(cs_pin, 1); - - /* pass chip-select pin to driver */ - devices[i].controller_data = (void *) cs_pin; - } - - spi_register_board_info(devices, nr_devices); - - /* Configure SPI bus(es) */ - if (enable_spi0) { - at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ - at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ - at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI1_SPCK */ - - at91_clock_associate("spi0_clk", &at91sam9260_spi0_device.dev, "spi_clk"); - platform_device_register(&at91sam9260_spi0_device); - } - if (enable_spi1) { - at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI1_MISO */ - at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI1_MOSI */ - at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI1_SPCK */ - - at91_clock_associate("spi1_clk", &at91sam9260_spi1_device.dev, "spi_clk"); - platform_device_register(&at91sam9260_spi1_device); - } -} -#else -void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {} -#endif - - -/* -------------------------------------------------------------------- - * LEDs - * -------------------------------------------------------------------- */ - -#if defined(CONFIG_LEDS) -u8 at91_leds_cpu; -u8 at91_leds_timer; - -void __init at91_init_leds(u8 cpu_led, u8 timer_led) -{ - at91_leds_cpu = cpu_led; - at91_leds_timer = timer_led; -} -#else -void __init at91_init_leds(u8 cpu_led, u8 timer_led) {} -#endif - - -/* -------------------------------------------------------------------- - * UART - * -------------------------------------------------------------------- */ -#if defined(CONFIG_SERIAL_ATMEL) -static struct resource dbgu_resources[] = { - [0] = { - .start = AT91_VA_BASE_SYS + AT91_DBGU, - .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91_ID_SYS, - .end = AT91_ID_SYS, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct atmel_uart_data dbgu_data = { - .use_dma_tx = 0, - .use_dma_rx = 0, /* DBGU not capable of receive DMA */ - .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU), -}; - -static struct platform_device at91sam9260_dbgu_device = { - .name = "atmel_usart", - .id = 0, - .dev = { - .platform_data = &dbgu_data, - .coherent_dma_mask = 0xffffffff, - }, - .resource = dbgu_resources, - .num_resources = ARRAY_SIZE(dbgu_resources), -}; - -static inline void configure_dbgu_pins(void) -{ - at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */ - at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */ -} - -static struct resource uart0_resources[] = { - [0] = { - .start = AT91SAM9260_BASE_US0, - .end = AT91SAM9260_BASE_US0 + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91SAM9260_ID_US0, - .end = AT91SAM9260_ID_US0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct atmel_uart_data uart0_data = { - .use_dma_tx = 1, - .use_dma_rx = 1, -}; - -static struct platform_device at91sam9260_uart0_device = { - .name = "atmel_usart", - .id = 1, - .dev = { - .platform_data = &uart0_data, - .coherent_dma_mask = 0xffffffff, - }, - .resource = uart0_resources, - .num_resources = ARRAY_SIZE(uart0_resources), -}; - -static inline void configure_usart0_pins(void) -{ - at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */ - at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */ - at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS0 */ - at91_set_A_periph(AT91_PIN_PB27, 0); /* CTS0 */ - at91_set_A_periph(AT91_PIN_PB24, 0); /* DTR0 */ - at91_set_A_periph(AT91_PIN_PB22, 0); /* DSR0 */ - at91_set_A_periph(AT91_PIN_PB23, 0); /* DCD0 */ - at91_set_A_periph(AT91_PIN_PB25, 0); /* RI0 */ -} - -static struct resource uart1_resources[] = { - [0] = { - .start = AT91SAM9260_BASE_US1, - .end = AT91SAM9260_BASE_US1 + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91SAM9260_ID_US1, - .end = AT91SAM9260_ID_US1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct atmel_uart_data uart1_data = { - .use_dma_tx = 1, - .use_dma_rx = 1, -}; - -static struct platform_device at91sam9260_uart1_device = { - .name = "atmel_usart", - .id = 2, - .dev = { - .platform_data = &uart1_data, - .coherent_dma_mask = 0xffffffff, - }, - .resource = uart1_resources, - .num_resources = ARRAY_SIZE(uart1_resources), -}; - -static inline void configure_usart1_pins(void) -{ - at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */ - at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */ - at91_set_A_periph(AT91_PIN_PB28, 0); /* RTS1 */ - at91_set_A_periph(AT91_PIN_PB29, 0); /* CTS1 */ -} - -static struct resource uart2_resources[] = { - [0] = { - .start = AT91SAM9260_BASE_US2, - .end = AT91SAM9260_BASE_US2 + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91SAM9260_ID_US2, - .end = AT91SAM9260_ID_US2, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct atmel_uart_data uart2_data = { - .use_dma_tx = 1, - .use_dma_rx = 1, -}; - -static struct platform_device at91sam9260_uart2_device = { - .name = "atmel_usart", - .id = 3, - .dev = { - .platform_data = &uart2_data, - .coherent_dma_mask = 0xffffffff, - }, - .resource = uart2_resources, - .num_resources = ARRAY_SIZE(uart2_resources), -}; - -static inline void configure_usart2_pins(void) -{ - at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */ - at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */ -} - -static struct resource uart3_resources[] = { - [0] = { - .start = AT91SAM9260_BASE_US3, - .end = AT91SAM9260_BASE_US3 + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91SAM9260_ID_US3, - .end = AT91SAM9260_ID_US3, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct atmel_uart_data uart3_data = { - .use_dma_tx = 1, - .use_dma_rx = 1, -}; - -static struct platform_device at91sam9260_uart3_device = { - .name = "atmel_usart", - .id = 4, - .dev = { - .platform_data = &uart3_data, - .coherent_dma_mask = 0xffffffff, - }, - .resource = uart3_resources, - .num_resources = ARRAY_SIZE(uart3_resources), -}; - -static inline void configure_usart3_pins(void) -{ - at91_set_A_periph(AT91_PIN_PB10, 1); /* TXD3 */ - at91_set_A_periph(AT91_PIN_PB11, 0); /* RXD3 */ -} - -static struct resource uart4_resources[] = { - [0] = { - .start = AT91SAM9260_BASE_US4, - .end = AT91SAM9260_BASE_US4 + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91SAM9260_ID_US4, - .end = AT91SAM9260_ID_US4, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct atmel_uart_data uart4_data = { - .use_dma_tx = 1, - .use_dma_rx = 1, -}; - -static struct platform_device at91sam9260_uart4_device = { - .name = "atmel_usart", - .id = 5, - .dev = { - .platform_data = &uart4_data, - .coherent_dma_mask = 0xffffffff, - }, - .resource = uart4_resources, - .num_resources = ARRAY_SIZE(uart4_resources), -}; - -static inline void configure_usart4_pins(void) -{ - at91_set_B_periph(AT91_PIN_PA31, 1); /* TXD4 */ - at91_set_B_periph(AT91_PIN_PA30, 0); /* RXD4 */ -} - -static struct resource uart5_resources[] = { - [0] = { - .start = AT91SAM9260_BASE_US5, - .end = AT91SAM9260_BASE_US5 + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91SAM9260_ID_US5, - .end = AT91SAM9260_ID_US5, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct atmel_uart_data uart5_data = { - .use_dma_tx = 1, - .use_dma_rx = 1, -}; - -static struct platform_device at91sam9260_uart5_device = { - .name = "atmel_usart", - .id = 6, - .dev = { - .platform_data = &uart5_data, - .coherent_dma_mask = 0xffffffff, - }, - .resource = uart5_resources, - .num_resources = ARRAY_SIZE(uart5_resources), -}; - -static inline void configure_usart5_pins(void) -{ - at91_set_A_periph(AT91_PIN_PB12, 1); /* TXD5 */ - at91_set_A_periph(AT91_PIN_PB13, 0); /* RXD5 */ -} - -struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ -struct platform_device *atmel_default_console_device; /* the serial console device */ - -void __init at91_init_serial(struct at91_uart_config *config) -{ - int i; - - /* Fill in list of supported UARTs */ - for (i = 0; i < config->nr_tty; i++) { - switch (config->tty_map[i]) { - case 0: - configure_usart0_pins(); - at91_uarts[i] = &at91sam9260_uart0_device; - at91_clock_associate("usart0_clk", &at91sam9260_uart0_device.dev, "usart"); - break; - case 1: - configure_usart1_pins(); - at91_uarts[i] = &at91sam9260_uart1_device; - at91_clock_associate("usart1_clk", &at91sam9260_uart1_device.dev, "usart"); - break; - case 2: - configure_usart2_pins(); - at91_uarts[i] = &at91sam9260_uart2_device; - at91_clock_associate("usart2_clk", &at91sam9260_uart2_device.dev, "usart"); - break; - case 3: - configure_usart3_pins(); - at91_uarts[i] = &at91sam9260_uart3_device; - at91_clock_associate("usart3_clk", &at91sam9260_uart3_device.dev, "usart"); - break; - case 4: - configure_usart4_pins(); - at91_uarts[i] = &at91sam9260_uart4_device; - at91_clock_associate("usart4_clk", &at91sam9260_uart4_device.dev, "usart"); - break; - case 5: - configure_usart5_pins(); - at91_uarts[i] = &at91sam9260_uart5_device; - at91_clock_associate("usart5_clk", &at91sam9260_uart5_device.dev, "usart"); - break; - case 6: - configure_dbgu_pins(); - at91_uarts[i] = &at91sam9260_dbgu_device; - at91_clock_associate("mck", &at91sam9260_dbgu_device.dev, "usart"); - break; - default: - continue; - } - at91_uarts[i]->id = i; /* update ID number to mapped ID */ - } - - /* Set serial console device */ - if (config->console_tty < ATMEL_MAX_UART) - atmel_default_console_device = at91_uarts[config->console_tty]; - if (!atmel_default_console_device) - printk(KERN_INFO "AT91: No default serial console defined.\n"); -} - -void __init at91_add_device_serial(void) -{ - int i; - - for (i = 0; i < ATMEL_MAX_UART; i++) { - if (at91_uarts[i]) - platform_device_register(at91_uarts[i]); - } -} -#else -void __init at91_init_serial(struct at91_uart_config *config) {} -void __init at91_add_device_serial(void) {} -#endif - - -/* -------------------------------------------------------------------- */ -/* - * These devices are always present and don't need any board-specific - * setup. - */ -static int __init at91_add_standard_devices(void) -{ - return 0; -} - -arch_initcall(at91_add_standard_devices); diff --git a/arch/arm/mach-at91rm9200/at91sam9261.c b/arch/arm/mach-at91rm9200/at91sam9261.c deleted file mode 100644 index d242bb885c6d..000000000000 --- a/arch/arm/mach-at91rm9200/at91sam9261.c +++ /dev/null @@ -1,290 +0,0 @@ -/* - * arch/arm/mach-at91rm9200/at91sam9261.c - * - * Copyright (C) 2005 SAN People - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ - -#include - -#include -#include -#include -#include -#include - -#include "generic.h" -#include "clock.h" - -static struct map_desc at91sam9261_io_desc[] __initdata = { - { - .virtual = AT91_VA_BASE_SYS, - .pfn = __phys_to_pfn(AT91_BASE_SYS), - .length = SZ_16K, - .type = MT_DEVICE, - }, { - .virtual = AT91_IO_VIRT_BASE - AT91SAM9261_SRAM_SIZE, - .pfn = __phys_to_pfn(AT91SAM9261_SRAM_BASE), - .length = AT91SAM9261_SRAM_SIZE, - .type = MT_DEVICE, - }, -}; - -/* -------------------------------------------------------------------- - * Clocks - * -------------------------------------------------------------------- */ - -/* - * The peripheral clocks. - */ -static struct clk pioA_clk = { - .name = "pioA_clk", - .pmc_mask = 1 << AT91SAM9261_ID_PIOA, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk pioB_clk = { - .name = "pioB_clk", - .pmc_mask = 1 << AT91SAM9261_ID_PIOB, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk pioC_clk = { - .name = "pioC_clk", - .pmc_mask = 1 << AT91SAM9261_ID_PIOC, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk usart0_clk = { - .name = "usart0_clk", - .pmc_mask = 1 << AT91SAM9261_ID_US0, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk usart1_clk = { - .name = "usart1_clk", - .pmc_mask = 1 << AT91SAM9261_ID_US1, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk usart2_clk = { - .name = "usart2_clk", - .pmc_mask = 1 << AT91SAM9261_ID_US2, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk mmc_clk = { - .name = "mci_clk", - .pmc_mask = 1 << AT91SAM9261_ID_MCI, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk udc_clk = { - .name = "udc_clk", - .pmc_mask = 1 << AT91SAM9261_ID_UDP, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk twi_clk = { - .name = "twi_clk", - .pmc_mask = 1 << AT91SAM9261_ID_TWI, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk spi0_clk = { - .name = "spi0_clk", - .pmc_mask = 1 << AT91SAM9261_ID_SPI0, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk spi1_clk = { - .name = "spi1_clk", - .pmc_mask = 1 << AT91SAM9261_ID_SPI1, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk ohci_clk = { - .name = "ohci_clk", - .pmc_mask = 1 << AT91SAM9261_ID_UHP, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk lcdc_clk = { - .name = "lcdc_clk", - .pmc_mask = 1 << AT91SAM9261_ID_LCDC, - .type = CLK_TYPE_PERIPHERAL, -}; - -static struct clk *periph_clocks[] __initdata = { - &pioA_clk, - &pioB_clk, - &pioC_clk, - &usart0_clk, - &usart1_clk, - &usart2_clk, - &mmc_clk, - &udc_clk, - &twi_clk, - &spi0_clk, - &spi1_clk, - // ssc 0 .. ssc2 - // tc0 .. tc2 - &ohci_clk, - &lcdc_clk, - // irq0 .. irq2 -}; - -/* - * The four programmable clocks. - * You must configure pin multiplexing to bring these signals out. - */ -static struct clk pck0 = { - .name = "pck0", - .pmc_mask = AT91_PMC_PCK0, - .type = CLK_TYPE_PROGRAMMABLE, - .id = 0, -}; -static struct clk pck1 = { - .name = "pck1", - .pmc_mask = AT91_PMC_PCK1, - .type = CLK_TYPE_PROGRAMMABLE, - .id = 1, -}; -static struct clk pck2 = { - .name = "pck2", - .pmc_mask = AT91_PMC_PCK2, - .type = CLK_TYPE_PROGRAMMABLE, - .id = 2, -}; -static struct clk pck3 = { - .name = "pck3", - .pmc_mask = AT91_PMC_PCK3, - .type = CLK_TYPE_PROGRAMMABLE, - .id = 3, -}; - -/* HClocks */ -static struct clk hck0 = { - .name = "hck0", - .pmc_mask = AT91_PMC_HCK0, - .type = CLK_TYPE_SYSTEM, - .id = 0, -}; -static struct clk hck1 = { - .name = "hck1", - .pmc_mask = AT91_PMC_HCK1, - .type = CLK_TYPE_SYSTEM, - .id = 1, -}; - -static void __init at91sam9261_register_clocks(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) - clk_register(periph_clocks[i]); - - clk_register(&pck0); - clk_register(&pck1); - clk_register(&pck2); - clk_register(&pck3); - - clk_register(&hck0); - clk_register(&hck1); -} - -/* -------------------------------------------------------------------- - * GPIO - * -------------------------------------------------------------------- */ - -static struct at91_gpio_bank at91sam9261_gpio[] = { - { - .id = AT91SAM9261_ID_PIOA, - .offset = AT91_PIOA, - .clock = &pioA_clk, - }, { - .id = AT91SAM9261_ID_PIOB, - .offset = AT91_PIOB, - .clock = &pioB_clk, - }, { - .id = AT91SAM9261_ID_PIOC, - .offset = AT91_PIOC, - .clock = &pioC_clk, - } -}; - -static void at91sam9261_reset(void) -{ - at91_sys_write(AT91_RSTC_CR, (0xA5 << 24) | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); -} - - -/* -------------------------------------------------------------------- - * AT91SAM9261 processor initialization - * -------------------------------------------------------------------- */ - -void __init at91sam9261_initialize(unsigned long main_clock) -{ - /* Map peripherals */ - iotable_init(at91sam9261_io_desc, ARRAY_SIZE(at91sam9261_io_desc)); - - at91_arch_reset = at91sam9261_reset; - at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1) - | (1 << AT91SAM9261_ID_IRQ2); - - /* Init clock subsystem */ - at91_clock_init(main_clock); - - /* Register the processor-specific clocks */ - at91sam9261_register_clocks(); - - /* Register GPIO subsystem */ - at91_gpio_init(at91sam9261_gpio, 3); -} - -/* -------------------------------------------------------------------- - * Interrupt initialization - * -------------------------------------------------------------------- */ - -/* - * The default interrupt priority levels (0 = lowest, 7 = highest). - */ -static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = { - 7, /* Advanced Interrupt Controller */ - 7, /* System Peripherals */ - 0, /* Parallel IO Controller A */ - 0, /* Parallel IO Controller B */ - 0, /* Parallel IO Controller C */ - 0, - 6, /* USART 0 */ - 6, /* USART 1 */ - 6, /* USART 2 */ - 0, /* Multimedia Card Interface */ - 4, /* USB Device Port */ - 0, /* Two-Wire Interface */ - 6, /* Serial Peripheral Interface 0 */ - 6, /* Serial Peripheral Interface 1 */ - 5, /* Serial Synchronous Controller 0 */ - 5, /* Serial Synchronous Controller 1 */ - 5, /* Serial Synchronous Controller 2 */ - 0, /* Timer Counter 0 */ - 0, /* Timer Counter 1 */ - 0, /* Timer Counter 2 */ - 3, /* USB Host port */ - 3, /* LCD Controller */ - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, /* Advanced Interrupt Controller */ - 0, /* Advanced Interrupt Controller */ - 0, /* Advanced Interrupt Controller */ -}; - -void __init at91sam9261_init_interrupts(unsigned int priority[NR_AIC_IRQS]) -{ - if (!priority) - priority = at91sam9261_default_irq_priority; - - /* Initialize the AIC interrupt controller */ - at91_aic_init(priority); - - /* Enable GPIO interrupts */ - at91_gpio_irq_setup(); -} diff --git a/arch/arm/mach-at91rm9200/at91sam9261_devices.c b/arch/arm/mach-at91rm9200/at91sam9261_devices.c deleted file mode 100644 index ed1d79081b35..000000000000 --- a/arch/arm/mach-at91rm9200/at91sam9261_devices.c +++ /dev/null @@ -1,741 +0,0 @@ -/* - * arch/arm/mach-at91rm9200/at91sam9261_devices.c - * - * Copyright (C) 2005 Thibaut VARENE - * Copyright (C) 2005 David Brownell - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ -#include -#include - -#include - -#include -#include -#include -#include -#include - -#include "generic.h" - -#define SZ_512 0x00000200 -#define SZ_256 0x00000100 -#define SZ_16 0x00000010 - -/* -------------------------------------------------------------------- - * USB Host - * -------------------------------------------------------------------- */ - -#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) -static u64 ohci_dmamask = 0xffffffffUL; -static struct at91_usbh_data usbh_data; - -static struct resource usbh_resources[] = { - [0] = { - .start = AT91SAM9261_UHP_BASE, - .end = AT91SAM9261_UHP_BASE + SZ_1M - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91SAM9261_ID_UHP, - .end = AT91SAM9261_ID_UHP, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device at91sam9261_usbh_device = { - .name = "at91_ohci", - .id = -1, - .dev = { - .dma_mask = &ohci_dmamask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &usbh_data, - }, - .resource = usbh_resources, - .num_resources = ARRAY_SIZE(usbh_resources), -}; - -void __init at91_add_device_usbh(struct at91_usbh_data *data) -{ - if (!data) - return; - - usbh_data = *data; - platform_device_register(&at91sam9261_usbh_device); -} -#else -void __init at91_add_device_usbh(struct at91_usbh_data *data) {} -#endif - - -/* -------------------------------------------------------------------- - * USB Device (Gadget) - * -------------------------------------------------------------------- */ - -#ifdef CONFIG_USB_GADGET_AT91 -static struct at91_udc_data udc_data; - -static struct resource udc_resources[] = { - [0] = { - .start = AT91SAM9261_BASE_UDP, - .end = AT91SAM9261_BASE_UDP + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91SAM9261_ID_UDP, - .end = AT91SAM9261_ID_UDP, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device at91sam9261_udc_device = { - .name = "at91_udc", - .id = -1, - .dev = { - .platform_data = &udc_data, - }, - .resource = udc_resources, - .num_resources = ARRAY_SIZE(udc_resources), -}; - -void __init at91_add_device_udc(struct at91_udc_data *data) -{ - unsigned long x; - - if (!data) - return; - - if (data->vbus_pin) { - at91_set_gpio_input(data->vbus_pin, 0); - at91_set_deglitch(data->vbus_pin, 1); - } - - /* Pullup pin is handled internally */ - x = at91_sys_read(AT91_MATRIX_USBPUCR); - at91_sys_write(AT91_MATRIX_USBPUCR, x | AT91_MATRIX_USBPUCR_PUON); - - udc_data = *data; - platform_device_register(&at91sam9261_udc_device); -} -#else -void __init at91_add_device_udc(struct at91_udc_data *data) {} -#endif - -/* -------------------------------------------------------------------- - * MMC / SD - * -------------------------------------------------------------------- */ - -#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE) -static u64 mmc_dmamask = 0xffffffffUL; -static struct at91_mmc_data mmc_data; - -static struct resource mmc_resources[] = { - [0] = { - .start = AT91SAM9261_BASE_MCI, - .end = AT91SAM9261_BASE_MCI + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91SAM9261_ID_MCI, - .end = AT91SAM9261_ID_MCI, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device at91sam9261_mmc_device = { - .name = "at91_mci", - .id = -1, - .dev = { - .dma_mask = &mmc_dmamask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &mmc_data, - }, - .resource = mmc_resources, - .num_resources = ARRAY_SIZE(mmc_resources), -}; - -void __init at91_add_device_mmc(struct at91_mmc_data *data) -{ - if (!data) - return; - - /* input/irq */ - if (data->det_pin) { - at91_set_gpio_input(data->det_pin, 1); - at91_set_deglitch(data->det_pin, 1); - } - if (data->wp_pin) - at91_set_gpio_input(data->wp_pin, 1); - if (data->vcc_pin) - at91_set_gpio_output(data->vcc_pin, 0); - - /* CLK */ - at91_set_B_periph(AT91_PIN_PA2, 0); - - /* CMD */ - at91_set_B_periph(AT91_PIN_PA1, 1); - - /* DAT0, maybe DAT1..DAT3 */ - at91_set_B_periph(AT91_PIN_PA0, 1); - if (data->wire4) { - at91_set_B_periph(AT91_PIN_PA4, 1); - at91_set_B_periph(AT91_PIN_PA5, 1); - at91_set_B_periph(AT91_PIN_PA6, 1); - } - - mmc_data = *data; - platform_device_register(&at91sam9261_mmc_device); -} -#else -void __init at91_add_device_mmc(struct at91_mmc_data *data) {} -#endif - - -/* -------------------------------------------------------------------- - * NAND / SmartMedia - * -------------------------------------------------------------------- */ - -#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE) -static struct at91_nand_data nand_data; - -#define NAND_BASE AT91_CHIPSELECT_3 - -static struct resource nand_resources[] = { - { - .start = NAND_BASE, - .end = NAND_BASE + SZ_256M - 1, - .flags = IORESOURCE_MEM, - } -}; - -static struct platform_device at91_nand_device = { - .name = "at91_nand", - .id = -1, - .dev = { - .platform_data = &nand_data, - }, - .resource = nand_resources, - .num_resources = ARRAY_SIZE(nand_resources), -}; - -void __init at91_add_device_nand(struct at91_nand_data *data) -{ - unsigned long csa, mode; - - if (!data) - return; - - csa = at91_sys_read(AT91_MATRIX_EBICSA); - at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC); - - /* set the bus interface characteristics */ - at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) - | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); - - at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5) - | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5)); - - at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7)); - - if (data->bus_width_16) - mode = AT91_SMC_DBW_16; - else - mode = AT91_SMC_DBW_8; - at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1)); - - /* enable pin */ - if (data->enable_pin) - at91_set_gpio_output(data->enable_pin, 1); - - /* ready/busy pin */ - if (data->rdy_pin) - at91_set_gpio_input(data->rdy_pin, 1); - - /* card detect pin */ - if (data->det_pin) - at91_set_gpio_input(data->det_pin, 1); - - at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */ - at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */ - - nand_data = *data; - platform_device_register(&at91_nand_device); -} - -#else -void __init at91_add_device_nand(struct at91_nand_data *data) {} -#endif - - -/* -------------------------------------------------------------------- - * TWI (i2c) - * -------------------------------------------------------------------- */ - -#if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE) - -static struct resource twi_resources[] = { - [0] = { - .start = AT91SAM9261_BASE_TWI, - .end = AT91SAM9261_BASE_TWI + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91SAM9261_ID_TWI, - .end = AT91SAM9261_ID_TWI, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device at91sam9261_twi_device = { - .name = "at91_i2c", - .id = -1, - .resource = twi_resources, - .num_resources = ARRAY_SIZE(twi_resources), -}; - -void __init at91_add_device_i2c(void) -{ - /* pins used for TWI interface */ - at91_set_A_periph(AT91_PIN_PA7, 0); /* TWD */ - at91_set_multi_drive(AT91_PIN_PA7, 1); - - at91_set_A_periph(AT91_PIN_PA8, 0); /* TWCK */ - at91_set_multi_drive(AT91_PIN_PA8, 1); - - platform_device_register(&at91sam9261_twi_device); -} -#else -void __init at91_add_device_i2c(void) {} -#endif - - -/* -------------------------------------------------------------------- - * SPI - * -------------------------------------------------------------------- */ - -#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE) -static u64 spi_dmamask = 0xffffffffUL; - -static struct resource spi0_resources[] = { - [0] = { - .start = AT91SAM9261_BASE_SPI0, - .end = AT91SAM9261_BASE_SPI0 + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91SAM9261_ID_SPI0, - .end = AT91SAM9261_ID_SPI0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device at91sam9261_spi0_device = { - .name = "atmel_spi", - .id = 0, - .dev = { - .dma_mask = &spi_dmamask, - .coherent_dma_mask = 0xffffffff, - }, - .resource = spi0_resources, - .num_resources = ARRAY_SIZE(spi0_resources), -}; - -static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 }; - -static struct resource spi1_resources[] = { - [0] = { - .start = AT91SAM9261_BASE_SPI1, - .end = AT91SAM9261_BASE_SPI1 + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91SAM9261_ID_SPI1, - .end = AT91SAM9261_ID_SPI1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device at91sam9261_spi1_device = { - .name = "atmel_spi", - .id = 1, - .dev = { - .dma_mask = &spi_dmamask, - .coherent_dma_mask = 0xffffffff, - }, - .resource = spi1_resources, - .num_resources = ARRAY_SIZE(spi1_resources), -}; - -static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB28, AT91_PIN_PA24, AT91_PIN_PA25, AT91_PIN_PA26 }; - -void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) -{ - int i; - unsigned long cs_pin; - short enable_spi0 = 0; - short enable_spi1 = 0; - - /* Choose SPI chip-selects */ - for (i = 0; i < nr_devices; i++) { - if (devices[i].controller_data) - cs_pin = (unsigned long) devices[i].controller_data; - else if (devices[i].bus_num == 0) - cs_pin = spi0_standard_cs[devices[i].chip_select]; - else - cs_pin = spi1_standard_cs[devices[i].chip_select]; - - if (devices[i].bus_num == 0) - enable_spi0 = 1; - else - enable_spi1 = 1; - - /* enable chip-select pin */ - at91_set_gpio_output(cs_pin, 1); - - /* pass chip-select pin to driver */ - devices[i].controller_data = (void *) cs_pin; - } - - spi_register_board_info(devices, nr_devices); - - /* Configure SPI bus(es) */ - if (enable_spi0) { - at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ - at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ - at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ - - at91_clock_associate("spi0_clk", &at91sam9261_spi0_device.dev, "spi_clk"); - platform_device_register(&at91sam9261_spi0_device); - } - if (enable_spi1) { - at91_set_A_periph(AT91_PIN_PB30, 0); /* SPI1_MISO */ - at91_set_A_periph(AT91_PIN_PB31, 0); /* SPI1_MOSI */ - at91_set_A_periph(AT91_PIN_PB29, 0); /* SPI1_SPCK */ - - at91_clock_associate("spi1_clk", &at91sam9261_spi1_device.dev, "spi_clk"); - platform_device_register(&at91sam9261_spi1_device); - } -} -#else -void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {} -#endif - - -/* -------------------------------------------------------------------- - * LCD Controller - * -------------------------------------------------------------------- */ - -#if defined(CONFIG_FB_AT91) || defined(CONFIG_FB_AT91_MODULE) -static u64 lcdc_dmamask = 0xffffffffUL; -static struct at91fb_info lcdc_data; - -static struct resource lcdc_resources[] = { - [0] = { - .start = AT91SAM9261_LCDC_BASE, - .end = AT91SAM9261_LCDC_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91SAM9261_ID_LCDC, - .end = AT91SAM9261_ID_LCDC, - .flags = IORESOURCE_IRQ, - }, -#if defined(CONFIG_FB_INTSRAM) - [2] = { - .start = AT91SAM9261_SRAM_BASE, - .end = AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE - 1, - .flags = IORESOURCE_MEM, - }, -#endif -}; - -static struct platform_device at91_lcdc_device = { - .name = "at91-fb", - .id = 0, - .dev = { - .dma_mask = &lcdc_dmamask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &lcdc_data, - }, - .resource = lcdc_resources, - .num_resources = ARRAY_SIZE(lcdc_resources), -}; - -void __init at91_add_device_lcdc(struct at91fb_info *data) -{ - if (!data) { - return; - } - - at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */ - at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */ - at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */ - at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */ - at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */ - at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */ - at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */ - at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */ - at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */ - at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */ - at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */ - at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */ - at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */ - at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */ - at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */ - at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */ - at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */ - at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */ - at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */ - at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */ - at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */ - at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */ - - lcdc_data = *data; - platform_device_register(&at91_lcdc_device); -} -#else -void __init at91_add_device_lcdc(struct at91fb_info *data) {} -#endif - - -/* -------------------------------------------------------------------- - * LEDs - * -------------------------------------------------------------------- */ - -#if defined(CONFIG_LEDS) -u8 at91_leds_cpu; -u8 at91_leds_timer; - -void __init at91_init_leds(u8 cpu_led, u8 timer_led) -{ - at91_leds_cpu = cpu_led; - at91_leds_timer = timer_led; -} -#else -void __init at91_init_leds(u8 cpu_led, u8 timer_led) {} -#endif - - -/* -------------------------------------------------------------------- - * UART - * -------------------------------------------------------------------- */ - -#if defined(CONFIG_SERIAL_ATMEL) -static struct resource dbgu_resources[] = { - [0] = { - .start = AT91_VA_BASE_SYS + AT91_DBGU, - .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91_ID_SYS, - .end = AT91_ID_SYS, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct atmel_uart_data dbgu_data = { - .use_dma_tx = 0, - .use_dma_rx = 0, /* DBGU not capable of receive DMA */ - .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU), -}; - -static struct platform_device at91sam9261_dbgu_device = { - .name = "atmel_usart", - .id = 0, - .dev = { - .platform_data = &dbgu_data, - .coherent_dma_mask = 0xffffffff, - }, - .resource = dbgu_resources, - .num_resources = ARRAY_SIZE(dbgu_resources), -}; - -static inline void configure_dbgu_pins(void) -{ - at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */ - at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */ -} - -static struct resource uart0_resources[] = { - [0] = { - .start = AT91SAM9261_BASE_US0, - .end = AT91SAM9261_BASE_US0 + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91SAM9261_ID_US0, - .end = AT91SAM9261_ID_US0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct atmel_uart_data uart0_data = { - .use_dma_tx = 1, - .use_dma_rx = 1, -}; - -static struct platform_device at91sam9261_uart0_device = { - .name = "atmel_usart", - .id = 1, - .dev = { - .platform_data = &uart0_data, - .coherent_dma_mask = 0xffffffff, - }, - .resource = uart0_resources, - .num_resources = ARRAY_SIZE(uart0_resources), -}; - -static inline void configure_usart0_pins(void) -{ - at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */ - at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */ - at91_set_A_periph(AT91_PIN_PC10, 0); /* RTS0 */ - at91_set_A_periph(AT91_PIN_PC11, 0); /* CTS0 */ -} - -static struct resource uart1_resources[] = { - [0] = { - .start = AT91SAM9261_BASE_US1, - .end = AT91SAM9261_BASE_US1 + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91SAM9261_ID_US1, - .end = AT91SAM9261_ID_US1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct atmel_uart_data uart1_data = { - .use_dma_tx = 1, - .use_dma_rx = 1, -}; - -static struct platform_device at91sam9261_uart1_device = { - .name = "atmel_usart", - .id = 2, - .dev = { - .platform_data = &uart1_data, - .coherent_dma_mask = 0xffffffff, - }, - .resource = uart1_resources, - .num_resources = ARRAY_SIZE(uart1_resources), -}; - -static inline void configure_usart1_pins(void) -{ - at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */ - at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */ -} - -static struct resource uart2_resources[] = { - [0] = { - .start = AT91SAM9261_BASE_US2, - .end = AT91SAM9261_BASE_US2 + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AT91SAM9261_ID_US2, - .end = AT91SAM9261_ID_US2, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct atmel_uart_data uart2_data = { - .use_dma_tx = 1, - .use_dma_rx = 1, -}; - -static struct platform_device at91sam9261_uart2_device = { - .name = "atmel_usart", - .id = 3, - .dev = { - .platform_data = &uart2_data, - .coherent_dma_mask = 0xffffffff, - }, - .resource = uart2_resources, - .num_resources = ARRAY_SIZE(uart2_resources), -}; - -static inline void configure_usart2_pins(void) -{ - at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */ - at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */ -} - -struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ -struct platform_device *atmel_default_console_device; /* the serial console device */ - -void __init at91_init_serial(struct at91_uart_config *config) -{ - int i; - - /* Fill in list of supported UARTs */ - for (i = 0; i < config->nr_tty; i++) { - switch (config->tty_map[i]) { - case 0: - configure_usart0_pins(); - at91_uarts[i] = &at91sam9261_uart0_device; - at91_clock_associate("usart0_clk", &at91sam9261_uart0_device.dev, "usart"); - break; - case 1: - configure_usart1_pins(); - at91_uarts[i] = &at91sam9261_uart1_device; - at91_clock_associate("usart1_clk", &at91sam9261_uart1_device.dev, "usart"); - break; - case 2: - configure_usart2_pins(); - at91_uarts[i] = &at91sam9261_uart2_device; - at91_clock_associate("usart2_clk", &at91sam9261_uart2_device.dev, "usart"); - break; - case 3: - configure_dbgu_pins(); - at91_uarts[i] = &at91sam9261_dbgu_device; - at91_clock_associate("mck", &at91sam9261_dbgu_device.dev, "usart"); - break; - default: - continue; - } - at91_uarts[i]->id = i; /* update ID number to mapped ID */ - } - - /* Set serial console device */ - if (config->console_tty < ATMEL_MAX_UART) - atmel_default_console_device = at91_uarts[config->console_tty]; - if (!atmel_default_console_device) - printk(KERN_INFO "AT91: No default serial console defined.\n"); -} - -void __init at91_add_device_serial(void) -{ - int i; - - for (i = 0; i < ATMEL_MAX_UART; i++) { - if (at91_uarts[i]) - platform_device_register(at91_uarts[i]); - } -} -#else -void __init at91_init_serial(struct at91_uart_config *config) {} -void __init at91_add_device_serial(void) {} -#endif - - -/* -------------------------------------------------------------------- */ - -/* - * These devices are always present and don't need any board-specific - * setup. - */ -static int __init at91_add_standard_devices(void) -{ - return 0; -} - -arch_initcall(at91_add_standard_devices); diff --git a/arch/arm/mach-at91rm9200/at91sam926x_time.c b/arch/arm/mach-at91rm9200/at91sam926x_time.c deleted file mode 100644 index 99df5f6ee42e..000000000000 --- a/arch/arm/mach-at91rm9200/at91sam926x_time.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * linux/arch/arm/mach-at91rm9200/at91sam926x_time.c - * - * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France - * Revision 2005 M. Nicolas Diremdjian, ATMEL Rousset, France - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - - -#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV) -#define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20) - -/* - * Returns number of microseconds since last timer interrupt. Note that interrupts - * will have been disabled by do_gettimeofday() - * 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy. - * 'tick' is usecs per jiffy (linux/timex.h). - */ -static unsigned long at91sam926x_gettimeoffset(void) -{ - unsigned long elapsed; - unsigned long t = at91_sys_read(AT91_PIT_PIIR); - - elapsed = (PIT_PICNT(t) * LATCH) + PIT_CPIV(t); /* hardware clock cycles */ - - return (unsigned long)(elapsed * 1000000) / LATCH; -} - -/* - * IRQ handler for the timer. - */ -static irqreturn_t at91sam926x_timer_interrupt(int irq, void *dev_id) -{ - volatile long nr_ticks; - - if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS) { /* This is a shared interrupt */ - write_seqlock(&xtime_lock); - - /* Get number to ticks performed before interrupt and clear PIT interrupt */ - nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); - do { - timer_tick(); - nr_ticks--; - } while (nr_ticks); - - write_sequnlock(&xtime_lock); - return IRQ_HANDLED; - } else - return IRQ_NONE; /* not handled */ -} - -static struct irqaction at91sam926x_timer_irq = { - .name = "at91_tick", - .flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER, - .handler = at91sam926x_timer_interrupt -}; - -void at91sam926x_timer_reset(void) -{ - /* Disable timer */ - at91_sys_write(AT91_PIT_MR, 0); - - /* Clear any pending interrupts */ - (void) at91_sys_read(AT91_PIT_PIVR); - - /* Set Period Interval timer and enable its interrupt */ - at91_sys_write(AT91_PIT_MR, (LATCH & AT91_PIT_PIV) | AT91_PIT_PITIEN | AT91_PIT_PITEN); -} - -/* - * Set up timer interrupt. - */ -void __init at91sam926x_timer_init(void) -{ - /* Initialize and enable the timer */ - at91sam926x_timer_reset(); - - /* Make IRQs happen for the system timer. */ - setup_irq(AT91_ID_SYS, &at91sam926x_timer_irq); -} - -#ifdef CONFIG_PM -static void at91sam926x_timer_suspend(void) -{ - /* Disable timer */ - at91_sys_write(AT91_PIT_MR, 0); -} -#else -#define at91sam926x_timer_suspend NULL -#endif - -struct sys_timer at91sam926x_timer = { - .init = at91sam926x_timer_init, - .offset = at91sam926x_gettimeoffset, - .suspend = at91sam926x_timer_suspend, - .resume = at91sam926x_timer_reset, -}; - diff --git a/arch/arm/mach-at91rm9200/board-1arm.c b/arch/arm/mach-at91rm9200/board-1arm.c deleted file mode 100644 index 971c3e2d8e36..000000000000 --- a/arch/arm/mach-at91rm9200/board-1arm.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * linux/arch/arm/mach-at91rm9200/board-1arm.c - * - * Copyright (C) 2005 SAN People - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include "generic.h" - - -/* - * Serial port configuration. - * 0 .. 3 = USART0 .. USART3 - * 4 = DBGU - */ -static struct at91_uart_config __initdata onearm_uart_config = { - .console_tty = 0, /* ttyS0 */ - .nr_tty = 3, - .tty_map = { 4, 0, 1, -1, -1 }, /* ttyS0, ..., ttyS4 */ -}; - -static void __init onearm_map_io(void) -{ - /* Initialize processor: 18.432 MHz crystal */ - at91rm9200_initialize(18432000, AT91RM9200_PQFP); - - /* Setup the serial ports and console */ - at91_init_serial(&onearm_uart_config); -} - -static void __init onearm_init_irq(void) -{ - at91rm9200_init_interrupts(NULL); -} - -static struct at91_eth_data __initdata onearm_eth_data = { - .phy_irq_pin = AT91_PIN_PC4, - .is_rmii = 1, -}; - -static struct at91_usbh_data __initdata onearm_usbh_data = { - .ports = 1, -}; - -static struct at91_udc_data __initdata onearm_udc_data = { - .vbus_pin = AT91_PIN_PC2, - .pullup_pin = AT91_PIN_PC3, -}; - -static void __init onearm_board_init(void) -{ - /* Serial */ - at91_add_device_serial(); - /* Ethernet */ - at91_add_device_eth(&onearm_eth_data); - /* USB Host */ - at91_add_device_usbh(&onearm_usbh_data); - /* USB Device */ - at91_add_device_udc(&onearm_udc_data); -} - -MACHINE_START(ONEARM, "Ajeco 1ARM single board computer") - /* Maintainer: Lennert Buytenhek */ - .phys_io = AT91_BASE_SYS, - .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, - .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91rm9200_timer, - .map_io = onearm_map_io, - .init_irq = onearm_init_irq, - .init_machine = onearm_board_init, -MACHINE_END diff --git a/arch/arm/mach-at91rm9200/board-carmeva.c b/arch/arm/mach-at91rm9200/board-carmeva.c deleted file mode 100644 index 654f0379550a..000000000000 --- a/arch/arm/mach-at91rm9200/board-carmeva.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * linux/arch/arm/mach-at91rm9200/board-carmeva.c - * - * Copyright (c) 2005 Peer Georgi - * Conitec Datasystems - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include "generic.h" - - -/* - * Serial port configuration. - * 0 .. 3 = USART0 .. USART3 - * 4 = DBGU - */ -static struct at91_uart_config __initdata carmeva_uart_config = { - .console_tty = 0, /* ttyS0 */ - .nr_tty = 2, - .tty_map = { 4, 1, -1, -1, -1 } /* ttyS0, ..., ttyS4 */ -}; - -static void __init carmeva_map_io(void) -{ - /* Initialize processor: 20.000 MHz crystal */ - at91rm9200_initialize(20000000, AT91RM9200_BGA); - - /* Setup the serial ports and console */ - at91_init_serial(&carmeva_uart_config); -} - -static void __init carmeva_init_irq(void) -{ - at91rm9200_init_interrupts(NULL); -} - -static struct at91_eth_data __initdata carmeva_eth_data = { - .phy_irq_pin = AT91_PIN_PC4, - .is_rmii = 1, -}; - -static struct at91_usbh_data __initdata carmeva_usbh_data = { - .ports = 2, -}; - -static struct at91_udc_data __initdata carmeva_udc_data = { - .vbus_pin = AT91_PIN_PD12, - .pullup_pin = AT91_PIN_PD9, -}; - -/* FIXME: user dependend */ -// static struct at91_cf_data __initdata carmeva_cf_data = { -// .det_pin = AT91_PIN_PB0, -// .rst_pin = AT91_PIN_PC5, - // .irq_pin = ... not connected - // .vcc_pin = ... always powered -// }; - -static struct at91_mmc_data __initdata carmeva_mmc_data = { - .slot_b = 0, - .wire4 = 1, - .det_pin = AT91_PIN_PB10, - .wp_pin = AT91_PIN_PC14, -}; - -static struct spi_board_info carmeva_spi_devices[] = { - { /* DataFlash chip */ - .modalias = "mtd_dataflash", - .chip_select = 0, - .max_speed_hz = 10 * 1000 * 1000, - }, - { /* User accessable spi - cs1 (250KHz) */ - .modalias = "spi-cs1", - .chip_select = 1, - .max_speed_hz = 250 * 1000, - }, - { /* User accessable spi - cs2 (1MHz) */ - .modalias = "spi-cs2", - .chip_select = 2, - .max_speed_hz = 1 * 1000 * 1000, - }, - { /* User accessable spi - cs3 (10MHz) */ - .modalias = "spi-cs3", - .chip_select = 3, - .max_speed_hz = 10 * 1000 * 1000, - }, -}; - -static void __init carmeva_board_init(void) -{ - /* Serial */ - at91_add_device_serial(); - /* Ethernet */ - at91_add_device_eth(&carmeva_eth_data); - /* USB Host */ - at91_add_device_usbh(&carmeva_usbh_data); - /* USB Device */ - at91_add_device_udc(&carmeva_udc_data); - /* I2C */ - at91_add_device_i2c(); - /* SPI */ - at91_add_device_spi(carmeva_spi_devices, ARRAY_SIZE(carmeva_spi_devices)); - /* Compact Flash */ -// at91_add_device_cf(&carmeva_cf_data); - /* MMC */ - at91_add_device_mmc(&carmeva_mmc_data); -} - -MACHINE_START(CARMEVA, "Carmeva") - /* Maintainer: Conitec Datasystems */ - .phys_io = AT91_BASE_SYS, - .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, - .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91rm9200_timer, - .map_io = carmeva_map_io, - .init_irq = carmeva_init_irq, - .init_machine = carmeva_board_init, -MACHINE_END diff --git a/arch/arm/mach-at91rm9200/board-csb337.c b/arch/arm/mach-at91rm9200/board-csb337.c deleted file mode 100644 index b8bb8052607a..000000000000 --- a/arch/arm/mach-at91rm9200/board-csb337.c +++ /dev/null @@ -1,145 +0,0 @@ -/* - * linux/arch/arm/mach-at91rm9200/board-csb337.c - * - * Copyright (C) 2005 SAN People - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include "generic.h" - - -/* - * Serial port configuration. - * 0 .. 3 = USART0 .. USART3 - * 4 = DBGU - */ -static struct at91_uart_config __initdata csb337_uart_config = { - .console_tty = 0, /* ttyS0 */ - .nr_tty = 2, - .tty_map = { 4, 1, -1, -1, -1 } /* ttyS0, ..., ttyS4 */ -}; - -static void __init csb337_map_io(void) -{ - /* Initialize processor: 3.6864 MHz crystal */ - at91rm9200_initialize(3686400, AT91RM9200_BGA); - - /* Setup the LEDs */ - at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1); - - /* Setup the serial ports and console */ - at91_init_serial(&csb337_uart_config); -} - -static void __init csb337_init_irq(void) -{ - at91rm9200_init_interrupts(NULL); -} - -static struct at91_eth_data __initdata csb337_eth_data = { - .phy_irq_pin = AT91_PIN_PC2, - .is_rmii = 0, -}; - -static struct at91_usbh_data __initdata csb337_usbh_data = { - .ports = 2, -}; - -static struct at91_udc_data __initdata csb337_udc_data = { - // this has no VBUS sensing pin - .pullup_pin = AT91_PIN_PA24, -}; - -static struct at91_cf_data __initdata csb337_cf_data = { - /* - * connector P4 on the CSB 337 mates to - * connector P8 on the CSB 300CF - */ - - /* CSB337 specific */ - .det_pin = AT91_PIN_PC3, - - /* CSB300CF specific */ - .irq_pin = AT91_PIN_PA19, - .vcc_pin = AT91_PIN_PD0, - .rst_pin = AT91_PIN_PD2, -}; - -static struct at91_mmc_data __initdata csb337_mmc_data = { - .det_pin = AT91_PIN_PD5, - .slot_b = 0, - .wire4 = 1, - .wp_pin = AT91_PIN_PD6, -}; - -static struct spi_board_info csb337_spi_devices[] = { - { /* CAN controller */ - .modalias = "sak82c900", - .chip_select = 0, - .max_speed_hz = 6 * 1000 * 1000, - }, -}; - -static void __init csb337_board_init(void) -{ - /* Serial */ - at91_add_device_serial(); - /* Ethernet */ - at91_add_device_eth(&csb337_eth_data); - /* USB Host */ - at91_add_device_usbh(&csb337_usbh_data); - /* USB Device */ - at91_add_device_udc(&csb337_udc_data); - /* I2C */ - at91_add_device_i2c(); - /* Compact Flash */ - at91_set_gpio_input(AT91_PIN_PB22, 1); /* IOIS16 */ - at91_add_device_cf(&csb337_cf_data); - /* SPI */ - at91_add_device_spi(csb337_spi_devices, ARRAY_SIZE(csb337_spi_devices)); - /* MMC */ - at91_add_device_mmc(&csb337_mmc_data); -} - -MACHINE_START(CSB337, "Cogent CSB337") - /* Maintainer: Bill Gatliff */ - .phys_io = AT91_BASE_SYS, - .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, - .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91rm9200_timer, - .map_io = csb337_map_io, - .init_irq = csb337_init_irq, - .init_machine = csb337_board_init, -MACHINE_END diff --git a/arch/arm/mach-at91rm9200/board-csb637.c b/arch/arm/mach-at91rm9200/board-csb637.c deleted file mode 100644 index a29fa0e822ce..000000000000 --- a/arch/arm/mach-at91rm9200/board-csb637.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * linux/arch/arm/mach-at91rm9200/board-csb637.c - * - * Copyright (C) 2005 SAN People - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include "generic.h" - - -/* - * Serial port configuration. - * 0 .. 3 = USART0 .. USART3 - * 4 = DBGU - */ -static struct at91_uart_config __initdata csb637_uart_config = { - .console_tty = 0, /* ttyS0 */ - .nr_tty = 2, - .tty_map = { 4, 1, -1, -1, -1 } /* ttyS0, ..., ttyS4 */ -}; - -static void __init csb637_map_io(void) -{ - /* Initialize processor: 3.6864 MHz crystal */ - at91rm9200_initialize(3686400, AT91RM9200_BGA); - - /* Setup the LEDs */ - at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2); - - /* Setup the serial ports and console */ - at91_init_serial(&csb637_uart_config); -} - -static void __init csb637_init_irq(void) -{ - at91rm9200_init_interrupts(NULL); -} - -static struct at91_eth_data __initdata csb637_eth_data = { - .phy_irq_pin = AT91_PIN_PC0, - .is_rmii = 0, -}; - -static struct at91_usbh_data __initdata csb637_usbh_data = { - .ports = 2, -}; - -static struct at91_udc_data __initdata csb637_udc_data = { - .vbus_pin = AT91_PIN_PB28, - .pullup_pin = AT91_PIN_PB1, -}; - -static void __init csb637_board_init(void) -{ - /* Serial */ - at91_add_device_serial(); - /* Ethernet */ - at91_add_device_eth(&csb637_eth_data); - /* USB Host */ - at91_add_device_usbh(&csb637_usbh_data); - /* USB Device */ - at91_add_device_udc(&csb637_udc_data); - /* I2C */ - at91_add_device_i2c(); - /* SPI */ - at91_add_device_spi(NULL, 0); -} - -MACHINE_START(CSB637, "Cogent CSB637") - /* Maintainer: Bill Gatliff */ - .phys_io = AT91_BASE_SYS, - .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, - .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91rm9200_timer, - .map_io = csb637_map_io, - .init_irq = csb637_init_irq, - .init_machine = csb637_board_init, -MACHINE_END diff --git a/arch/arm/mach-at91rm9200/board-dk.c b/arch/arm/mach-at91rm9200/board-dk.c deleted file mode 100644 index 7522bf91bce8..000000000000 --- a/arch/arm/mach-at91rm9200/board-dk.c +++ /dev/null @@ -1,216 +0,0 @@ -/* - * linux/arch/arm/mach-at91rm9200/board-dk.c - * - * Copyright (C) 2005 SAN People - * - * Epson S1D framebuffer glue code is: - * Copyright (C) 2005 Thibaut VARENE - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include "generic.h" - - -/* - * Serial port configuration. - * 0 .. 3 = USART0 .. USART3 - * 4 = DBGU - */ -static struct at91_uart_config __initdata dk_uart_config = { - .console_tty = 0, /* ttyS0 */ - .nr_tty = 2, - .tty_map = { 4, 1, -1, -1, -1 } /* ttyS0, ..., ttyS4 */ -}; - -static void __init dk_map_io(void) -{ - /* Initialize processor: 18.432 MHz crystal */ - at91rm9200_initialize(18432000, AT91RM9200_BGA); - - /* Setup the LEDs */ - at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2); - - /* Setup the serial ports and console */ - at91_init_serial(&dk_uart_config); -} - -static void __init dk_init_irq(void) -{ - at91rm9200_init_interrupts(NULL); -} - -static struct at91_eth_data __initdata dk_eth_data = { - .phy_irq_pin = AT91_PIN_PC4, - .is_rmii = 1, -}; - -static struct at91_usbh_data __initdata dk_usbh_data = { - .ports = 2, -}; - -static struct at91_udc_data __initdata dk_udc_data = { - .vbus_pin = AT91_PIN_PD4, - .pullup_pin = AT91_PIN_PD5, -}; - -static struct at91_cf_data __initdata dk_cf_data = { - .det_pin = AT91_PIN_PB0, - .rst_pin = AT91_PIN_PC5, - // .irq_pin = ... not connected - // .vcc_pin = ... always powered -}; - -static struct at91_mmc_data __initdata dk_mmc_data = { - .slot_b = 0, - .wire4 = 1, -}; - -static struct spi_board_info dk_spi_devices[] = { - { /* DataFlash chip */ - .modalias = "mtd_dataflash", - .chip_select = 0, - .max_speed_hz = 15 * 1000 * 1000, - }, - { /* UR6HCPS2-SP40 PS2-to-SPI adapter */ - .modalias = "ur6hcps2", - .chip_select = 1, - .max_speed_hz = 250 * 1000, - }, - { /* TLV1504 ADC, 4 channels, 10 bits; one is a temp sensor */ - .modalias = "tlv1504", - .chip_select = 2, - .max_speed_hz = 20 * 1000 * 1000, - }, -#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD - { /* DataFlash card */ - .modalias = "mtd_dataflash", - .chip_select = 3, - .max_speed_hz = 15 * 1000 * 1000, - } -#endif -}; - -static struct mtd_partition __initdata dk_nand_partition[] = { - { - .name = "NAND Partition 1", - .offset = 0, - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct mtd_partition *nand_partitions(int size, int *num_partitions) -{ - *num_partitions = ARRAY_SIZE(dk_nand_partition); - return dk_nand_partition; -} - -static struct at91_nand_data __initdata dk_nand_data = { - .ale = 22, - .cle = 21, - .det_pin = AT91_PIN_PB1, - .rdy_pin = AT91_PIN_PC2, - // .enable_pin = ... not there - .partition_info = nand_partitions, -}; - -#define DK_FLASH_BASE AT91_CHIPSELECT_0 -#define DK_FLASH_SIZE 0x200000 - -static struct physmap_flash_data dk_flash_data = { - .width = 2, -}; - -static struct resource dk_flash_resource = { - .start = DK_FLASH_BASE, - .end = DK_FLASH_BASE + DK_FLASH_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device dk_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &dk_flash_data, - }, - .resource = &dk_flash_resource, - .num_resources = 1, -}; - - -static void __init dk_board_init(void) -{ - /* Serial */ - at91_add_device_serial(); - /* Ethernet */ - at91_add_device_eth(&dk_eth_data); - /* USB Host */ - at91_add_device_usbh(&dk_usbh_data); - /* USB Device */ - at91_add_device_udc(&dk_udc_data); - at91_set_multi_drive(dk_udc_data.pullup_pin, 1); /* pullup_pin is connected to reset */ - /* Compact Flash */ - at91_add_device_cf(&dk_cf_data); - /* I2C */ - at91_add_device_i2c(); - /* SPI */ - at91_add_device_spi(dk_spi_devices, ARRAY_SIZE(dk_spi_devices)); -#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD - /* DataFlash card */ - at91_set_gpio_output(AT91_PIN_PB7, 0); -#else - /* MMC */ - at91_set_gpio_output(AT91_PIN_PB7, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */ - at91_add_device_mmc(&dk_mmc_data); -#endif - /* NAND */ - at91_add_device_nand(&dk_nand_data); - /* NOR Flash */ - platform_device_register(&dk_flash); - /* VGA */ -// dk_add_device_video(); -} - -MACHINE_START(AT91RM9200DK, "Atmel AT91RM9200-DK") - /* Maintainer: SAN People/Atmel */ - .phys_io = AT91_BASE_SYS, - .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, - .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91rm9200_timer, - .map_io = dk_map_io, - .init_irq = dk_init_irq, - .init_machine = dk_board_init, -MACHINE_END diff --git a/arch/arm/mach-at91rm9200/board-eb9200.c b/arch/arm/mach-at91rm9200/board-eb9200.c deleted file mode 100644 index 80b72cf7264c..000000000000 --- a/arch/arm/mach-at91rm9200/board-eb9200.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * linux/arch/arm/mach-at91rm9200/board-eb9200.c - * - * Copyright (C) 2005 SAN People, adapted for ATEB9200 from Embest - * by Andrew Patrikalakis - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include "generic.h" - - -/* - * Serial port configuration. - * 0 .. 3 = USART0 .. USART3 - * 4 = DBGU - */ -static struct at91_uart_config __initdata eb9200_uart_config = { - .console_tty = 0, /* ttyS0 */ - .nr_tty = 2, - .tty_map = { 4, 1, -1, -1, -1 } /* ttyS0, ..., ttyS4 */ -}; - -static void __init eb9200_map_io(void) -{ - /* Initialize processor: 18.432 MHz crystal */ - at91rm9200_initialize(18432000, AT91RM9200_BGA); - - /* Setup the serial ports and console */ - at91_init_serial(&eb9200_uart_config); -} - -static void __init eb9200_init_irq(void) -{ - at91rm9200_init_interrupts(NULL); -} - -static struct at91_eth_data __initdata eb9200_eth_data = { - .phy_irq_pin = AT91_PIN_PC4, - .is_rmii = 1, -}; - -static struct at91_usbh_data __initdata eb9200_usbh_data = { - .ports = 2, -}; - -static struct at91_udc_data __initdata eb9200_udc_data = { - .vbus_pin = AT91_PIN_PD4, - .pullup_pin = AT91_PIN_PD5, -}; - -static struct at91_cf_data __initdata eb9200_cf_data = { - .det_pin = AT91_PIN_PB0, - .rst_pin = AT91_PIN_PC5, - // .irq_pin = ... not connected - // .vcc_pin = ... always powered -}; - -static struct at91_mmc_data __initdata eb9200_mmc_data = { - .slot_b = 0, - .wire4 = 1, -}; - -static void __init eb9200_board_init(void) -{ - /* Serial */ - at91_add_device_serial(); - /* Ethernet */ - at91_add_device_eth(&eb9200_eth_data); - /* USB Host */ - at91_add_device_usbh(&eb9200_usbh_data); - /* USB Device */ - at91_add_device_udc(&eb9200_udc_data); - /* I2C */ - at91_add_device_i2c(); - /* Compact Flash */ - at91_add_device_cf(&eb9200_cf_data); - /* SPI */ - at91_add_device_spi(NULL, 0); - /* MMC */ - /* only supports 1 or 4 bit interface, not wired through to SPI */ - at91_add_device_mmc(&eb9200_mmc_data); -} - -MACHINE_START(ATEB9200, "Embest ATEB9200") - .phys_io = AT91_BASE_SYS, - .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, - .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91rm9200_timer, - .map_io = eb9200_map_io, - .init_irq = eb9200_init_irq, - .init_machine = eb9200_board_init, -MACHINE_END diff --git a/arch/arm/mach-at91rm9200/board-ek.c b/arch/arm/mach-at91rm9200/board-ek.c deleted file mode 100644 index c4fdb415f20e..000000000000 --- a/arch/arm/mach-at91rm9200/board-ek.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * linux/arch/arm/mach-at91rm9200/board-ek.c - * - * Copyright (C) 2005 SAN People - * - * Epson S1D framebuffer glue code is: - * Copyright (C) 2005 Thibaut VARENE - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include "generic.h" - - -/* - * Serial port configuration. - * 0 .. 3 = USART0 .. USART3 - * 4 = DBGU - */ -static struct at91_uart_config __initdata ek_uart_config = { - .console_tty = 0, /* ttyS0 */ - .nr_tty = 2, - .tty_map = { 4, 1, -1, -1, -1 } /* ttyS0, ..., ttyS4 */ -}; - -static void __init ek_map_io(void) -{ - /* Initialize processor: 18.432 MHz crystal */ - at91rm9200_initialize(18432000, AT91RM9200_BGA); - - /* Setup the LEDs */ - at91_init_leds(AT91_PIN_PB1, AT91_PIN_PB2); - - /* Setup the serial ports and console */ - at91_init_serial(&ek_uart_config); -} - -static void __init ek_init_irq(void) -{ - at91rm9200_init_interrupts(NULL); -} - -static struct at91_eth_data __initdata ek_eth_data = { - .phy_irq_pin = AT91_PIN_PC4, - .is_rmii = 1, -}; - -static struct at91_usbh_data __initdata ek_usbh_data = { - .ports = 2, -}; - -static struct at91_udc_data __initdata ek_udc_data = { - .vbus_pin = AT91_PIN_PD4, - .pullup_pin = AT91_PIN_PD5, -}; - -static struct at91_mmc_data __initdata ek_mmc_data = { - .det_pin = AT91_PIN_PB27, - .slot_b = 0, - .wire4 = 1, - .wp_pin = AT91_PIN_PA17, -}; - -static struct spi_board_info ek_spi_devices[] = { - { /* DataFlash chip */ - .modalias = "mtd_dataflash", - .chip_select = 0, - .max_speed_hz = 15 * 1000 * 1000, - }, -#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD - { /* DataFlash card */ - .modalias = "mtd_dataflash", - .chip_select = 3, - .max_speed_hz = 15 * 1000 * 1000, - }, -#endif -}; - -#define EK_FLASH_BASE AT91_CHIPSELECT_0 -#define EK_FLASH_SIZE 0x200000 - -static struct physmap_flash_data ek_flash_data = { - .width = 2, -}; - -static struct resource ek_flash_resource = { - .start = EK_FLASH_BASE, - .end = EK_FLASH_BASE + EK_FLASH_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device ek_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &ek_flash_data, - }, - .resource = &ek_flash_resource, - .num_resources = 1, -}; - - -static void __init ek_board_init(void) -{ - /* Serial */ - at91_add_device_serial(); - /* Ethernet */ - at91_add_device_eth(&ek_eth_data); - /* USB Host */ - at91_add_device_usbh(&ek_usbh_data); - /* USB Device */ - at91_add_device_udc(&ek_udc_data); - at91_set_multi_drive(ek_udc_data.pullup_pin, 1); /* pullup_pin is connected to reset */ - /* I2C */ - at91_add_device_i2c(); - /* SPI */ - at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); -#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD - /* DataFlash card */ - at91_set_gpio_output(AT91_PIN_PB22, 0); -#else - /* MMC */ - at91_set_gpio_output(AT91_PIN_PB22, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */ - at91_add_device_mmc(&ek_mmc_data); -#endif - /* NOR Flash */ - platform_device_register(&ek_flash); - /* VGA */ -// ek_add_device_video(); -} - -MACHINE_START(AT91RM9200EK, "Atmel AT91RM9200-EK") - /* Maintainer: SAN People/Atmel */ - .phys_io = AT91_BASE_SYS, - .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, - .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91rm9200_timer, - .map_io = ek_map_io, - .init_irq = ek_init_irq, - .init_machine = ek_board_init, -MACHINE_END diff --git a/arch/arm/mach-at91rm9200/board-kafa.c b/arch/arm/mach-at91rm9200/board-kafa.c deleted file mode 100644 index 6ef3c4879829..000000000000 --- a/arch/arm/mach-at91rm9200/board-kafa.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * linux/arch/arm/mach-at91rm9200/board-kafa.c - * - * Copyright (C) 2006 Sperry-Sun - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include "generic.h" - - -/* - * Serial port configuration. - * 0 .. 3 = USART0 .. USART3 - * 4 = DBGU - */ -static struct at91_uart_config __initdata kafa_uart_config = { - .console_tty = 0, /* ttyS0 */ - .nr_tty = 2, - .tty_map = { 4, 0, -1, -1, -1 } /* ttyS0, ..., ttyS4 */ -}; - -static void __init kafa_map_io(void) -{ - /* Initialize processor: 18.432 MHz crystal */ - at91rm9200_initialize(18432000, AT91RM9200_PQFP); - - /* Set up the LEDs */ - at91_init_leds(AT91_PIN_PB4, AT91_PIN_PB4); - - /* Setup the serial ports and console */ - at91_init_serial(&kafa_uart_config); -} - -static void __init kafa_init_irq(void) -{ - at91rm9200_init_interrupts(NULL); -} - -static struct at91_eth_data __initdata kafa_eth_data = { - .phy_irq_pin = AT91_PIN_PC4, - .is_rmii = 0, -}; - -static struct at91_usbh_data __initdata kafa_usbh_data = { - .ports = 1, -}; - -static struct at91_udc_data __initdata kafa_udc_data = { - .vbus_pin = AT91_PIN_PB6, - .pullup_pin = AT91_PIN_PB7, -}; - -static void __init kafa_board_init(void) -{ - /* Serial */ - at91_add_device_serial(); - /* Ethernet */ - at91_add_device_eth(&kafa_eth_data); - /* USB Host */ - at91_add_device_usbh(&kafa_usbh_data); - /* USB Device */ - at91_add_device_udc(&kafa_udc_data); - /* I2C */ - at91_add_device_i2c(); - /* SPI */ - at91_add_device_spi(NULL, 0); -} - -MACHINE_START(KAFA, "Sperry-Sun KAFA") - /* Maintainer: Sergei Sharonov */ - .phys_io = AT91_BASE_SYS, - .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, - .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91rm9200_timer, - .map_io = kafa_map_io, - .init_irq = kafa_init_irq, - .init_machine = kafa_board_init, -MACHINE_END diff --git a/arch/arm/mach-at91rm9200/board-kb9202.c b/arch/arm/mach-at91rm9200/board-kb9202.c deleted file mode 100644 index 759d8191854f..000000000000 --- a/arch/arm/mach-at91rm9200/board-kb9202.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * linux/arch/arm/mach-at91rm9200/board-kb9202.c - * - * Copyright (c) 2005 kb_admin - * KwikByte, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include "generic.h" - - -/* - * Serial port configuration. - * 0 .. 3 = USART0 .. USART3 - * 4 = DBGU - */ -static struct at91_uart_config __initdata kb9202_uart_config = { - .console_tty = 0, /* ttyS0 */ - .nr_tty = 3, - .tty_map = { 4, 0, 1, -1, -1 } /* ttyS0, ..., ttyS4 */ -}; - -static void __init kb9202_map_io(void) -{ - /* Initialize processor: 10 MHz crystal */ - at91rm9200_initialize(10000000, AT91RM9200_PQFP); - - /* Set up the LEDs */ - at91_init_leds(AT91_PIN_PC19, AT91_PIN_PC18); - - /* Setup the serial ports and console */ - at91_init_serial(&kb9202_uart_config); -} - -static void __init kb9202_init_irq(void) -{ - at91rm9200_init_interrupts(NULL); -} - -static struct at91_eth_data __initdata kb9202_eth_data = { - .phy_irq_pin = AT91_PIN_PB29, - .is_rmii = 0, -}; - -static struct at91_usbh_data __initdata kb9202_usbh_data = { - .ports = 1, -}; - -static struct at91_udc_data __initdata kb9202_udc_data = { - .vbus_pin = AT91_PIN_PB24, - .pullup_pin = AT91_PIN_PB22, -}; - -static struct at91_mmc_data __initdata kb9202_mmc_data = { - .det_pin = AT91_PIN_PB2, - .slot_b = 0, - .wire4 = 1, -}; - -static struct mtd_partition __initdata kb9202_nand_partition[] = { - { - .name = "nand_fs", - .offset = 0, - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct mtd_partition *nand_partitions(int size, int *num_partitions) -{ - *num_partitions = ARRAY_SIZE(kb9202_nand_partition); - return kb9202_nand_partition; -} - -static struct at91_nand_data __initdata kb9202_nand_data = { - .ale = 22, - .cle = 21, - // .det_pin = ... not there - .rdy_pin = AT91_PIN_PC29, - .enable_pin = AT91_PIN_PC28, - .partition_info = nand_partitions, -}; - -static void __init kb9202_board_init(void) -{ - /* Serial */ - at91_add_device_serial(); - /* Ethernet */ - at91_add_device_eth(&kb9202_eth_data); - /* USB Host */ - at91_add_device_usbh(&kb9202_usbh_data); - /* USB Device */ - at91_add_device_udc(&kb9202_udc_data); - /* MMC */ - at91_add_device_mmc(&kb9202_mmc_data); - /* I2C */ - at91_add_device_i2c(); - /* SPI */ - at91_add_device_spi(NULL, 0); - /* NAND */ - at91_add_device_nand(&kb9202_nand_data); -} - -MACHINE_START(KB9200, "KB920x") - /* Maintainer: KwikByte, Inc. */ - .phys_io = AT91_BASE_SYS, - .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, - .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91rm9200_timer, - .map_io = kb9202_map_io, - .init_irq = kb9202_init_irq, - .init_machine = kb9202_board_init, -MACHINE_END diff --git a/arch/arm/mach-at91rm9200/board-sam9260ek.c b/arch/arm/mach-at91rm9200/board-sam9260ek.c deleted file mode 100644 index 37c7a7d195c3..000000000000 --- a/arch/arm/mach-at91rm9200/board-sam9260ek.c +++ /dev/null @@ -1,202 +0,0 @@ -/* - * linux/arch/arm/mach-at91rm9200/board-ek.c - * - * Copyright (C) 2005 SAN People - * Copyright (C) 2006 Atmel - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include "generic.h" - - -/* - * Serial port configuration. - * 0 .. 5 = USART0 .. USART5 - * 6 = DBGU - */ -static struct at91_uart_config __initdata ek_uart_config = { - .console_tty = 0, /* ttyS0 */ - .nr_tty = 3, - .tty_map = { 6, 0, 1, -1, -1, -1, -1 } /* ttyS0, ..., ttyS6 */ -}; - -static void __init ek_map_io(void) -{ - /* Initialize processor: 18.432 MHz crystal */ - at91sam9260_initialize(18432000); - - /* Setup the serial ports and console */ - at91_init_serial(&ek_uart_config); -} - -static void __init ek_init_irq(void) -{ - at91sam9260_init_interrupts(NULL); -} - - -/* - * USB Host port - */ -static struct at91_usbh_data __initdata ek_usbh_data = { - .ports = 2, -}; - -/* - * USB Device port - */ -static struct at91_udc_data __initdata ek_udc_data = { - .vbus_pin = AT91_PIN_PC5, - .pullup_pin = 0, /* pull-up driven by UDC */ -}; - - -/* - * SPI devices. - */ -static struct spi_board_info ek_spi_devices[] = { -#if !defined(CONFIG_MMC_AT91) - { /* DataFlash chip */ - .modalias = "mtd_dataflash", - .chip_select = 1, - .max_speed_hz = 15 * 1000 * 1000, - .bus_num = 0, - }, -#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD) - { /* DataFlash card */ - .modalias = "mtd_dataflash", - .chip_select = 0, - .max_speed_hz = 15 * 1000 * 1000, - .bus_num = 0, - }, -#endif -#endif -#if defined(CONFIG_SND_AT73C213) - { /* AT73C213 DAC */ - .modalias = "snd_at73c213", - .chip_select = 0, - .max_speed_hz = 10 * 1000 * 1000, - .bus_num = 1, - }, -#endif -}; - - -/* - * MACB Ethernet device - */ -static struct __initdata at91_eth_data ek_macb_data = { - .phy_irq_pin = AT91_PIN_PA7, - .is_rmii = 1, -}; - - -/* - * NAND flash - */ -static struct mtd_partition __initdata ek_nand_partition[] = { - { - .name = "Partition 1", - .offset = 0, - .size = 256 * 1024, - }, - { - .name = "Partition 2", - .offset = 256 * 1024, - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct mtd_partition *nand_partitions(int size, int *num_partitions) -{ - *num_partitions = ARRAY_SIZE(ek_nand_partition); - return ek_nand_partition; -} - -static struct at91_nand_data __initdata ek_nand_data = { - .ale = 21, - .cle = 22, -// .det_pin = ... not connected - .rdy_pin = AT91_PIN_PC13, - .enable_pin = AT91_PIN_PC14, - .partition_info = nand_partitions, -#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16) - .bus_width_16 = 1, -#else - .bus_width_16 = 0, -#endif -}; - - -/* - * MCI (SD/MMC) - */ -static struct at91_mmc_data __initdata ek_mmc_data = { - .slot_b = 1, - .wire4 = 1, -// .det_pin = ... not connected -// .wp_pin = ... not connected -// .vcc_pin = ... not connected -}; - -static void __init ek_board_init(void) -{ - /* Serial */ - at91_add_device_serial(); - /* USB Host */ - at91_add_device_usbh(&ek_usbh_data); - /* USB Device */ - at91_add_device_udc(&ek_udc_data); - /* SPI */ - at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); - /* NAND */ - at91_add_device_nand(&ek_nand_data); - /* Ethernet */ - at91_add_device_eth(&ek_macb_data); - /* MMC */ - at91_add_device_mmc(&ek_mmc_data); -} - -MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK") - /* Maintainer: Atmel */ - .phys_io = AT91_BASE_SYS, - .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, - .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91sam926x_timer, - .map_io = ek_map_io, - .init_irq = ek_init_irq, - .init_machine = ek_board_init, -MACHINE_END diff --git a/arch/arm/mach-at91rm9200/board-sam9261ek.c b/arch/arm/mach-at91rm9200/board-sam9261ek.c deleted file mode 100644 index 30b490d8886b..000000000000 --- a/arch/arm/mach-at91rm9200/board-sam9261ek.c +++ /dev/null @@ -1,259 +0,0 @@ -/* - * linux/arch/arm/mach-at91rm9200/board-ek.c - * - * Copyright (C) 2005 SAN People - * Copyright (C) 2006 Atmel - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include "generic.h" - - -/* - * Serial port configuration. - * 0 .. 2 = USART0 .. USART2 - * 3 = DBGU - */ -static struct at91_uart_config __initdata ek_uart_config = { - .console_tty = 0, /* ttyS0 */ - .nr_tty = 1, - .tty_map = { 3, -1, -1, -1 } /* ttyS0, ..., ttyS3 */ -}; - -static void __init ek_map_io(void) -{ - /* Initialize processor: 18.432 MHz crystal */ - at91sam9261_initialize(18432000); - - /* Setup the serial ports and console */ - at91_init_serial(&ek_uart_config); -} - -static void __init ek_init_irq(void) -{ - at91sam9261_init_interrupts(NULL); -} - - -/* - * DM9000 ethernet device - */ -#if defined(CONFIG_DM9000) -static struct resource at91sam9261_dm9000_resource[] = { - [0] = { - .start = AT91_CHIPSELECT_2, - .end = AT91_CHIPSELECT_2 + 3, - .flags = IORESOURCE_MEM - }, - [1] = { - .start = AT91_CHIPSELECT_2 + 0x44, - .end = AT91_CHIPSELECT_2 + 0xFF, - .flags = IORESOURCE_MEM - }, - [2] = { - .start = AT91_PIN_PC11, - .end = AT91_PIN_PC11, - .flags = IORESOURCE_IRQ - } -}; - -static struct dm9000_plat_data dm9000_platdata = { - .flags = DM9000_PLATF_16BITONLY, -}; - -static struct platform_device at91sam9261_dm9000_device = { - .name = "dm9000", - .id = 0, - .num_resources = ARRAY_SIZE(at91sam9261_dm9000_resource), - .resource = at91sam9261_dm9000_resource, - .dev = { - .platform_data = &dm9000_platdata, - } -}; - -static void __init ek_add_device_dm9000(void) -{ - /* - * Configure Chip-Select 2 on SMC for the DM9000. - * Note: These timings were calculated for MASTER_CLOCK = 100000000 - * according to the DM9000 timings. - */ - at91_sys_write(AT91_SMC_SETUP(2), AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(2), AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) | AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8)); - at91_sys_write(AT91_SMC_CYCLE(2), AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16)); - at91_sys_write(AT91_SMC_MODE(2), AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | AT91_SMC_TDF_(1)); - - /* Configure Reset signal as output */ - at91_set_gpio_output(AT91_PIN_PC10, 0); - - /* Configure Interrupt pin as input, no pull-up */ - at91_set_gpio_input(AT91_PIN_PC11, 0); - - platform_device_register(&at91sam9261_dm9000_device); -} -#else -static void __init ek_add_device_dm9000(void) {} -#endif /* CONFIG_DM9000 */ - - -/* - * USB Host Port - */ -static struct at91_usbh_data __initdata ek_usbh_data = { - .ports = 2, -}; - - -/* - * USB Device Port - */ -static struct at91_udc_data __initdata ek_udc_data = { - .vbus_pin = AT91_PIN_PB29, - .pullup_pin = 0, /* pull-up driven by UDC */ -}; - - -/* - * MCI (SD/MMC) - */ -static struct at91_mmc_data __initdata ek_mmc_data = { - .wire4 = 1, -// .det_pin = ... not connected -// .wp_pin = ... not connected -// .vcc_pin = ... not connected -}; - - -/* - * NAND flash - */ -static struct mtd_partition __initdata ek_nand_partition[] = { - { - .name = "Partition 1", - .offset = 0, - .size = 256 * 1024, - }, - { - .name = "Partition 2", - .offset = 256 * 1024 , - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct mtd_partition *nand_partitions(int size, int *num_partitions) -{ - *num_partitions = ARRAY_SIZE(ek_nand_partition); - return ek_nand_partition; -} - -static struct at91_nand_data __initdata ek_nand_data = { - .ale = 22, - .cle = 21, -// .det_pin = ... not connected - .rdy_pin = AT91_PIN_PC15, - .enable_pin = AT91_PIN_PC14, - .partition_info = nand_partitions, -#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16) - .bus_width_16 = 1, -#else - .bus_width_16 = 0, -#endif -}; - -/* - * SPI devices - */ -static struct spi_board_info ek_spi_devices[] = { - { /* DataFlash chip */ - .modalias = "mtd_dataflash", - .chip_select = 0, - .max_speed_hz = 15 * 1000 * 1000, - .bus_num = 0, - }, -#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD) - { /* DataFlash card - jumper (J12) configurable to CS3 or CS0 */ - .modalias = "mtd_dataflash", - .chip_select = 3, - .max_speed_hz = 15 * 1000 * 1000, - .bus_num = 0, - }, -#elif defined(CONFIG_SND_AT73C213) - { /* AT73C213 DAC */ - .modalias = "snd_at73c213", - .chip_select = 3, - .max_speed_hz = 10 * 1000 * 1000, - .bus_num = 0, - }, -#endif -}; - - -static void __init ek_board_init(void) -{ - /* Serial */ - at91_add_device_serial(); - /* USB Host */ - at91_add_device_usbh(&ek_usbh_data); - /* USB Device */ - at91_add_device_udc(&ek_udc_data); - /* I2C */ - at91_add_device_i2c(); - /* NAND */ - at91_add_device_nand(&ek_nand_data); - /* DM9000 ethernet */ - ek_add_device_dm9000(); - - /* spi0 and mmc/sd share the same PIO pins */ -#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE) - /* SPI */ - at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); -#else - /* MMC */ - at91_add_device_mmc(&ek_mmc_data); -#endif -} - -MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK") - /* Maintainer: Atmel */ - .phys_io = AT91_BASE_SYS, - .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, - .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91sam926x_timer, - .map_io = ek_map_io, - .init_irq = ek_init_irq, - .init_machine = ek_board_init, -MACHINE_END diff --git a/arch/arm/mach-at91rm9200/clock.c b/arch/arm/mach-at91rm9200/clock.c deleted file mode 100644 index 4dee21fefe5a..000000000000 --- a/arch/arm/mach-at91rm9200/clock.c +++ /dev/null @@ -1,644 +0,0 @@ -/* - * linux/arch/arm/mach-at91rm9200/clock.c - * - * Copyright (C) 2005 David Brownell - * Copyright (C) 2005 Ivan Kokshaysky - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include "clock.h" - - -/* - * There's a lot more which can be done with clocks, including cpufreq - * integration, slow clock mode support (for system suspend), letting - * PLLB be used at other rates (on boards that don't need USB), etc. - */ - -#define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY) -#define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE) -#define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL) -#define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM) - - -static LIST_HEAD(clocks); -static DEFINE_SPINLOCK(clk_lock); - -static u32 at91_pllb_usb_init; - -/* - * Four primary clock sources: two crystal oscillators (32K, main), and - * two PLLs. PLLA usually runs the master clock; and PLLB must run at - * 48 MHz (unless no USB function clocks are needed). The main clock and - * both PLLs are turned off to run in "slow clock mode" (system suspend). - */ -static struct clk clk32k = { - .name = "clk32k", - .rate_hz = AT91_SLOW_CLOCK, - .users = 1, /* always on */ - .id = 0, - .type = CLK_TYPE_PRIMARY, -}; -static struct clk main_clk = { - .name = "main", - .pmc_mask = AT91_PMC_MOSCS, /* in PMC_SR */ - .id = 1, - .type = CLK_TYPE_PRIMARY, -}; -static struct clk plla = { - .name = "plla", - .parent = &main_clk, - .pmc_mask = AT91_PMC_LOCKA, /* in PMC_SR */ - .id = 2, - .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL, -}; - -static void pllb_mode(struct clk *clk, int is_on) -{ - u32 value; - - if (is_on) { - is_on = AT91_PMC_LOCKB; - value = at91_pllb_usb_init; - } else - value = 0; - - // REVISIT: Add work-around for AT91RM9200 Errata #26 ? - at91_sys_write(AT91_CKGR_PLLBR, value); - - do { - cpu_relax(); - } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on); -} - -static struct clk pllb = { - .name = "pllb", - .parent = &main_clk, - .pmc_mask = AT91_PMC_LOCKB, /* in PMC_SR */ - .mode = pllb_mode, - .id = 3, - .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL, -}; - -static void pmc_sys_mode(struct clk *clk, int is_on) -{ - if (is_on) - at91_sys_write(AT91_PMC_SCER, clk->pmc_mask); - else - at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask); -} - -/* USB function clocks (PLLB must be 48 MHz) */ -static struct clk udpck = { - .name = "udpck", - .parent = &pllb, - .mode = pmc_sys_mode, -}; -static struct clk uhpck = { - .name = "uhpck", - .parent = &pllb, - .mode = pmc_sys_mode, -}; - - -/* - * The master clock is divided from the CPU clock (by 1-4). It's used for - * memory, interfaces to on-chip peripherals, the AIC, and sometimes more - * (e.g baud rate generation). It's sourced from one of the primary clocks. - */ -static struct clk mck = { - .name = "mck", - .pmc_mask = AT91_PMC_MCKRDY, /* in PMC_SR */ -}; - -static void pmc_periph_mode(struct clk *clk, int is_on) -{ - if (is_on) - at91_sys_write(AT91_PMC_PCER, clk->pmc_mask); - else - at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask); -} - -static struct clk __init *at91_css_to_clk(unsigned long css) -{ - switch (css) { - case AT91_PMC_CSS_SLOW: - return &clk32k; - case AT91_PMC_CSS_MAIN: - return &main_clk; - case AT91_PMC_CSS_PLLA: - return &plla; - case AT91_PMC_CSS_PLLB: - return &pllb; - } - - return NULL; -} - -/* - * Associate a particular clock with a function (eg, "uart") and device. - * The drivers can then request the same 'function' with several different - * devices and not care about which clock name to use. - */ -void __init at91_clock_associate(const char *id, struct device *dev, const char *func) -{ - struct clk *clk = clk_get(NULL, id); - - if (!dev || !clk || !IS_ERR(clk_get(dev, func))) - return; - - clk->function = func; - clk->dev = dev; -} - -/* clocks cannot be de-registered no refcounting necessary */ -struct clk *clk_get(struct device *dev, const char *id) -{ - struct clk *clk; - - list_for_each_entry(clk, &clocks, node) { - if (strcmp(id, clk->name) == 0) - return clk; - if (clk->function && (dev == clk->dev) && strcmp(id, clk->function) == 0) - return clk; - } - - return ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(clk_get); - -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); - -static void __clk_enable(struct clk *clk) -{ - if (clk->parent) - __clk_enable(clk->parent); - if (clk->users++ == 0 && clk->mode) - clk->mode(clk, 1); -} - -int clk_enable(struct clk *clk) -{ - unsigned long flags; - - spin_lock_irqsave(&clk_lock, flags); - __clk_enable(clk); - spin_unlock_irqrestore(&clk_lock, flags); - return 0; -} -EXPORT_SYMBOL(clk_enable); - -static void __clk_disable(struct clk *clk) -{ - BUG_ON(clk->users == 0); - if (--clk->users == 0 && clk->mode) - clk->mode(clk, 0); - if (clk->parent) - __clk_disable(clk->parent); -} - -void clk_disable(struct clk *clk) -{ - unsigned long flags; - - spin_lock_irqsave(&clk_lock, flags); - __clk_disable(clk); - spin_unlock_irqrestore(&clk_lock, flags); -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - unsigned long flags; - unsigned long rate; - - spin_lock_irqsave(&clk_lock, flags); - for (;;) { - rate = clk->rate_hz; - if (rate || !clk->parent) - break; - clk = clk->parent; - } - spin_unlock_irqrestore(&clk_lock, flags); - return rate; -} -EXPORT_SYMBOL(clk_get_rate); - -/*------------------------------------------------------------------------*/ - -#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS - -/* - * For now, only the programmable clocks support reparenting (MCK could - * do this too, with care) or rate changing (the PLLs could do this too, - * ditto MCK but that's more for cpufreq). Drivers may reparent to get - * a better rate match; we don't. - */ - -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - unsigned long flags; - unsigned prescale; - unsigned long actual; - - if (!clk_is_programmable(clk)) - return -EINVAL; - spin_lock_irqsave(&clk_lock, flags); - - actual = clk->parent->rate_hz; - for (prescale = 0; prescale < 7; prescale++) { - if (actual && actual <= rate) - break; - actual >>= 1; - } - - spin_unlock_irqrestore(&clk_lock, flags); - return (prescale < 7) ? actual : -ENOENT; -} -EXPORT_SYMBOL(clk_round_rate); - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned long flags; - unsigned prescale; - unsigned long actual; - - if (!clk_is_programmable(clk)) - return -EINVAL; - if (clk->users) - return -EBUSY; - spin_lock_irqsave(&clk_lock, flags); - - actual = clk->parent->rate_hz; - for (prescale = 0; prescale < 7; prescale++) { - if (actual && actual <= rate) { - u32 pckr; - - pckr = at91_sys_read(AT91_PMC_PCKR(clk->id)); - pckr &= AT91_PMC_CSS_PLLB; /* clock selection */ - pckr |= prescale << 2; - at91_sys_write(AT91_PMC_PCKR(clk->id), pckr); - clk->rate_hz = actual; - break; - } - actual >>= 1; - } - - spin_unlock_irqrestore(&clk_lock, flags); - return (prescale < 7) ? actual : -ENOENT; -} -EXPORT_SYMBOL(clk_set_rate); - -struct clk *clk_get_parent(struct clk *clk) -{ - return clk->parent; -} -EXPORT_SYMBOL(clk_get_parent); - -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - unsigned long flags; - - if (clk->users) - return -EBUSY; - if (!clk_is_primary(parent) || !clk_is_programmable(clk)) - return -EINVAL; - spin_lock_irqsave(&clk_lock, flags); - - clk->rate_hz = parent->rate_hz; - clk->parent = parent; - at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id); - - spin_unlock_irqrestore(&clk_lock, flags); - return 0; -} -EXPORT_SYMBOL(clk_set_parent); - -/* establish PCK0..PCK3 parentage and rate */ -static void init_programmable_clock(struct clk *clk) -{ - struct clk *parent; - u32 pckr; - - pckr = at91_sys_read(AT91_PMC_PCKR(clk->id)); - parent = at91_css_to_clk(pckr & AT91_PMC_CSS); - clk->parent = parent; - clk->rate_hz = parent->rate_hz / (1 << ((pckr >> 2) & 3)); -} - -#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */ - -/*------------------------------------------------------------------------*/ - -#ifdef CONFIG_DEBUG_FS - -static int at91_clk_show(struct seq_file *s, void *unused) -{ - u32 scsr, pcsr, sr; - struct clk *clk; - unsigned i; - - seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR)); - seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR)); - - seq_printf(s, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR)); - seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR)); - seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR)); - seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR)); - - seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR)); - for (i = 0; i < 4; i++) - seq_printf(s, "PCK%d = %8x\n", i, at91_sys_read(AT91_PMC_PCKR(i))); - seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR)); - - seq_printf(s, "\n"); - - list_for_each_entry(clk, &clocks, node) { - char *state; - - if (clk->mode == pmc_sys_mode) - state = (scsr & clk->pmc_mask) ? "on" : "off"; - else if (clk->mode == pmc_periph_mode) - state = (pcsr & clk->pmc_mask) ? "on" : "off"; - else if (clk->pmc_mask) - state = (sr & clk->pmc_mask) ? "on" : "off"; - else if (clk == &clk32k || clk == &main_clk) - state = "on"; - else - state = ""; - - seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n", - clk->name, clk->users, state, clk_get_rate(clk), - clk->parent ? clk->parent->name : ""); - } - return 0; -} - -static int at91_clk_open(struct inode *inode, struct file *file) -{ - return single_open(file, at91_clk_show, NULL); -} - -static struct file_operations at91_clk_operations = { - .open = at91_clk_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static int __init at91_clk_debugfs_init(void) -{ - /* /sys/kernel/debug/at91_clk */ - (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations); - - return 0; -} -postcore_initcall(at91_clk_debugfs_init); - -#endif - -/*------------------------------------------------------------------------*/ - -/* Register a new clock */ -int __init clk_register(struct clk *clk) -{ - if (clk_is_peripheral(clk)) { - clk->parent = &mck; - clk->mode = pmc_periph_mode; - list_add_tail(&clk->node, &clocks); - } - else if (clk_is_sys(clk)) { - clk->parent = &mck; - clk->mode = pmc_sys_mode; - - list_add_tail(&clk->node, &clocks); - } -#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS - else if (clk_is_programmable(clk)) { - clk->mode = pmc_sys_mode; - init_programmable_clock(clk); - list_add_tail(&clk->node, &clocks); - } -#endif - - return 0; -} - - -/*------------------------------------------------------------------------*/ - -static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg) -{ - unsigned mul, div; - - div = reg & 0xff; - mul = (reg >> 16) & 0x7ff; - if (div && mul) { - freq /= div; - freq *= mul + 1; - } else - freq = 0; - - return freq; -} - -static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg) -{ - if (pll == &pllb && (reg & AT91_PMC_USB96M)) - return freq / 2; - else - return freq; -} - -static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq) -{ - unsigned i, div = 0, mul = 0, diff = 1 << 30; - unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; - - /* PLL output max 240 MHz (or 180 MHz per errata) */ - if (out_freq > 240000000) - goto fail; - - for (i = 1; i < 256; i++) { - int diff1; - unsigned input, mul1; - - /* - * PLL input between 1MHz and 32MHz per spec, but lower - * frequences seem necessary in some cases so allow 100K. - */ - input = main_freq / i; - if (input < 100000) - continue; - if (input > 32000000) - continue; - - mul1 = out_freq / input; - if (mul1 > 2048) - continue; - if (mul1 < 2) - goto fail; - - diff1 = out_freq - input * mul1; - if (diff1 < 0) - diff1 = -diff1; - if (diff > diff1) { - diff = diff1; - div = i; - mul = mul1; - if (diff == 0) - break; - } - } - if (i == 256 && diff > (out_freq >> 5)) - goto fail; - return ret | ((mul - 1) << 16) | div; -fail: - return 0; -} - -/* - * Several unused clocks may be active. Turn them off. - */ -static void __init at91_periphclk_reset(void) -{ - unsigned long reg; - struct clk *clk; - - reg = at91_sys_read(AT91_PMC_PCSR); - - list_for_each_entry(clk, &clocks, node) { - if (clk->mode != pmc_periph_mode) - continue; - - if (clk->users > 0) - reg &= ~clk->pmc_mask; - } - - at91_sys_write(AT91_PMC_PCDR, reg); -} - -static struct clk *const standard_pmc_clocks[] __initdata = { - /* four primary clocks */ - &clk32k, - &main_clk, - &plla, - &pllb, - - /* PLLB children (USB) */ - &udpck, - &uhpck, - - /* MCK */ - &mck -}; - -int __init at91_clock_init(unsigned long main_clock) -{ - unsigned tmp, freq, mckr; - int i; - - /* - * When the bootloader initialized the main oscillator correctly, - * there's no problem using the cycle counter. But if it didn't, - * or when using oscillator bypass mode, we must be told the speed - * of the main clock. - */ - if (!main_clock) { - do { - tmp = at91_sys_read(AT91_CKGR_MCFR); - } while (!(tmp & AT91_PMC_MAINRDY)); - main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); - } - main_clk.rate_hz = main_clock; - - /* report if PLLA is more than mildly overclocked */ - plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); - if (plla.rate_hz > 209000000) - pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); - - /* - * USB clock init: choose 48 MHz PLLB value, turn all clocks off, - * disable 48MHz clock during usb peripheral suspend. - * - * REVISIT: assumes MCK doesn't derive from PLLB! - */ - at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; - pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); - if (cpu_is_at91rm9200()) { - uhpck.pmc_mask = AT91RM9200_PMC_UHP; - udpck.pmc_mask = AT91RM9200_PMC_UDP; - at91_sys_write(AT91_PMC_SCDR, AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP); - at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP); - } else if (cpu_is_at91sam9260()) { - uhpck.pmc_mask = AT91SAM926x_PMC_UHP; - udpck.pmc_mask = AT91SAM926x_PMC_UDP; - at91_sys_write(AT91_PMC_SCDR, AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP); - } else if (cpu_is_at91sam9261()) { - uhpck.pmc_mask = (AT91SAM926x_PMC_UHP | AT91_PMC_HCK0); - udpck.pmc_mask = AT91SAM926x_PMC_UDP; - at91_sys_write(AT91_PMC_SCDR, AT91SAM926x_PMC_UHP | AT91_PMC_HCK0 | AT91SAM926x_PMC_UDP); - } - at91_sys_write(AT91_CKGR_PLLBR, 0); - - udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); - uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); - - /* - * MCK and CPU derive from one of those primary clocks. - * For now, assume this parentage won't change. - */ - mckr = at91_sys_read(AT91_PMC_MCKR); - mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); - freq = mck.parent->rate_hz; - freq /= (1 << ((mckr >> 2) & 3)); /* prescale */ - mck.rate_hz = freq / (1 + ((mckr >> 8) & 3)); /* mdiv */ - - /* Register the PMC's standard clocks */ - for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) - list_add_tail(&standard_pmc_clocks[i]->node, &clocks); - - /* MCK and CPU clock are "always on" */ - clk_enable(&mck); - - printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", - freq / 1000000, (unsigned) mck.rate_hz / 1000000, - (unsigned) main_clock / 1000000, - ((unsigned) main_clock % 1000000) / 1000); - - /* disable all programmable clocks */ - at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK0 | AT91_PMC_PCK1 | AT91_PMC_PCK2 | AT91_PMC_PCK3); - - /* disable all other unused peripheral clocks */ - at91_periphclk_reset(); - - return 0; -} diff --git a/arch/arm/mach-at91rm9200/clock.h b/arch/arm/mach-at91rm9200/clock.h deleted file mode 100644 index b5c7a2eb2d1d..000000000000 --- a/arch/arm/mach-at91rm9200/clock.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * linux/arch/arm/mach-at91rm9200/clock.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#define CLK_TYPE_PRIMARY 0x1 -#define CLK_TYPE_PLL 0x2 -#define CLK_TYPE_PROGRAMMABLE 0x4 -#define CLK_TYPE_PERIPHERAL 0x8 -#define CLK_TYPE_SYSTEM 0x10 - - -struct clk { - struct list_head node; - const char *name; /* unique clock name */ - const char *function; /* function of the clock */ - struct device *dev; /* device associated with function */ - unsigned long rate_hz; - struct clk *parent; - u32 pmc_mask; - void (*mode)(struct clk *, int); - unsigned id:2; /* PCK0..3, or 32k/main/a/b */ - unsigned type; /* clock type */ - u16 users; -}; - - -extern int __init clk_register(struct clk *clk); diff --git a/arch/arm/mach-at91rm9200/generic.h b/arch/arm/mach-at91rm9200/generic.h deleted file mode 100644 index 8c4d5a77d485..000000000000 --- a/arch/arm/mach-at91rm9200/generic.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * linux/arch/arm/mach-at91rm9200/generic.h - * - * Copyright (C) 2005 David Brownell - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - - /* Processors */ -extern void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banks); -extern void __init at91sam9260_initialize(unsigned long main_clock); -extern void __init at91sam9261_initialize(unsigned long main_clock); - - /* Interrupts */ -extern void __init at91rm9200_init_interrupts(unsigned int priority[]); -extern void __init at91sam9260_init_interrupts(unsigned int priority[]); -extern void __init at91sam9261_init_interrupts(unsigned int priority[]); -extern void __init at91_aic_init(unsigned int priority[]); - - /* Timer */ -struct sys_timer; -extern struct sys_timer at91rm9200_timer; -extern struct sys_timer at91sam926x_timer; - - /* Clocks */ -extern int __init at91_clock_init(unsigned long main_clock); -struct device; -extern void __init at91_clock_associate(const char *id, struct device *dev, const char *func); - - /* Power Management */ -extern void at91_irq_suspend(void); -extern void at91_irq_resume(void); - - /* GPIO */ -#define AT91RM9200_PQFP 3 /* AT91RM9200 PQFP package has 3 banks */ -#define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */ - -struct at91_gpio_bank { - unsigned short id; /* peripheral ID */ - unsigned long offset; /* offset from system peripheral base */ - struct clk *clock; /* associated clock */ -}; -extern void __init at91_gpio_init(struct at91_gpio_bank *, int nr_banks); -extern void __init at91_gpio_irq_setup(void); - -extern void (*at91_arch_reset)(void); -extern int at91_extern_irq; diff --git a/arch/arm/mach-at91rm9200/gpio.c b/arch/arm/mach-at91rm9200/gpio.c deleted file mode 100644 index af22659c8a28..000000000000 --- a/arch/arm/mach-at91rm9200/gpio.c +++ /dev/null @@ -1,414 +0,0 @@ -/* - * linux/arch/arm/mach-at91rm9200/gpio.c - * - * Copyright (C) 2005 HP Labs - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "generic.h" - - -static struct at91_gpio_bank *gpio; -static int gpio_banks; - - -static inline void __iomem *pin_to_controller(unsigned pin) -{ - void __iomem *sys_base = (void __iomem *) AT91_VA_BASE_SYS; - - pin -= PIN_BASE; - pin /= 32; - if (likely(pin < gpio_banks)) - return sys_base + gpio[pin].offset; - - return NULL; -} - -static inline unsigned pin_to_mask(unsigned pin) -{ - pin -= PIN_BASE; - return 1 << (pin % 32); -} - - -/*--------------------------------------------------------------------------*/ - -/* Not all hardware capabilities are exposed through these calls; they - * only encapsulate the most common features and modes. (So if you - * want to change signals in groups, do it directly.) - * - * Bootloaders will usually handle some of the pin multiplexing setup. - * The intent is certainly that by the time Linux is fully booted, all - * pins should have been fully initialized. These setup calls should - * only be used by board setup routines, or possibly in driver probe(). - * - * For bootloaders doing all that setup, these calls could be inlined - * as NOPs so Linux won't duplicate any setup code - */ - - -/* - * mux the pin to the "A" internal peripheral role. - */ -int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup) -{ - void __iomem *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); - - if (!pio) - return -EINVAL; - - __raw_writel(mask, pio + PIO_IDR); - __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); - __raw_writel(mask, pio + PIO_ASR); - __raw_writel(mask, pio + PIO_PDR); - return 0; -} -EXPORT_SYMBOL(at91_set_A_periph); - - -/* - * mux the pin to the "B" internal peripheral role. - */ -int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup) -{ - void __iomem *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); - - if (!pio) - return -EINVAL; - - __raw_writel(mask, pio + PIO_IDR); - __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); - __raw_writel(mask, pio + PIO_BSR); - __raw_writel(mask, pio + PIO_PDR); - return 0; -} -EXPORT_SYMBOL(at91_set_B_periph); - - -/* - * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and - * configure it for an input. - */ -int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup) -{ - void __iomem *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); - - if (!pio) - return -EINVAL; - - __raw_writel(mask, pio + PIO_IDR); - __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); - __raw_writel(mask, pio + PIO_ODR); - __raw_writel(mask, pio + PIO_PER); - return 0; -} -EXPORT_SYMBOL(at91_set_gpio_input); - - -/* - * mux the pin to the gpio controller (instead of "A" or "B" peripheral), - * and configure it for an output. - */ -int __init_or_module at91_set_gpio_output(unsigned pin, int value) -{ - void __iomem *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); - - if (!pio) - return -EINVAL; - - __raw_writel(mask, pio + PIO_IDR); - __raw_writel(mask, pio + PIO_PUDR); - __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); - __raw_writel(mask, pio + PIO_OER); - __raw_writel(mask, pio + PIO_PER); - return 0; -} -EXPORT_SYMBOL(at91_set_gpio_output); - - -/* - * enable/disable the glitch filter; mostly used with IRQ handling. - */ -int __init_or_module at91_set_deglitch(unsigned pin, int is_on) -{ - void __iomem *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); - - if (!pio) - return -EINVAL; - __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); - return 0; -} -EXPORT_SYMBOL(at91_set_deglitch); - -/* - * enable/disable the multi-driver; This is only valid for output and - * allows the output pin to run as an open collector output. - */ -int __init_or_module at91_set_multi_drive(unsigned pin, int is_on) -{ - void __iomem *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); - - if (!pio) - return -EINVAL; - - __raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR)); - return 0; -} -EXPORT_SYMBOL(at91_set_multi_drive); - -/*--------------------------------------------------------------------------*/ - -/* - * assuming the pin is muxed as a gpio output, set its value. - */ -int at91_set_gpio_value(unsigned pin, int value) -{ - void __iomem *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); - - if (!pio) - return -EINVAL; - __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); - return 0; -} -EXPORT_SYMBOL(at91_set_gpio_value); - - -/* - * read the pin's value (works even if it's not muxed as a gpio). - */ -int at91_get_gpio_value(unsigned pin) -{ - void __iomem *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); - u32 pdsr; - - if (!pio) - return -EINVAL; - pdsr = __raw_readl(pio + PIO_PDSR); - return (pdsr & mask) != 0; -} -EXPORT_SYMBOL(at91_get_gpio_value); - -/*--------------------------------------------------------------------------*/ - -#ifdef CONFIG_PM - -static u32 wakeups[MAX_GPIO_BANKS]; -static u32 backups[MAX_GPIO_BANKS]; - -static int gpio_irq_set_wake(unsigned pin, unsigned state) -{ - unsigned mask = pin_to_mask(pin); - unsigned bank = (pin - PIN_BASE) / 32; - - if (unlikely(bank >= MAX_GPIO_BANKS)) - return -EINVAL; - - if (state) - wakeups[bank] |= mask; - else - wakeups[bank] &= ~mask; - - set_irq_wake(gpio[bank].id, state); - - return 0; -} - -void at91_gpio_suspend(void) -{ - int i; - - for (i = 0; i < gpio_banks; i++) { - u32 pio = gpio[i].offset; - - backups[i] = at91_sys_read(pio + PIO_IMR); - at91_sys_write(pio + PIO_IDR, backups[i]); - at91_sys_write(pio + PIO_IER, wakeups[i]); - - if (!wakeups[i]) - clk_disable(gpio[i].clock); - else { -#ifdef CONFIG_PM_DEBUG - printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]); -#endif - } - } -} - -void at91_gpio_resume(void) -{ - int i; - - for (i = 0; i < gpio_banks; i++) { - u32 pio = gpio[i].offset; - - if (!wakeups[i]) - clk_enable(gpio[i].clock); - - at91_sys_write(pio + PIO_IDR, wakeups[i]); - at91_sys_write(pio + PIO_IER, backups[i]); - } -} - -#else -#define gpio_irq_set_wake NULL -#endif - - -/* Several AIC controller irqs are dispatched through this GPIO handler. - * To use any AT91_PIN_* as an externally triggered IRQ, first call - * at91_set_gpio_input() then maybe enable its glitch filter. - * Then just request_irq() with the pin ID; it works like any ARM IRQ - * handler, though it always triggers on rising and falling edges. - * - * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after - * configuring them with at91_set_a_periph() or at91_set_b_periph(). - * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering. - */ - -static void gpio_irq_mask(unsigned pin) -{ - void __iomem *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); - - if (pio) - __raw_writel(mask, pio + PIO_IDR); -} - -static void gpio_irq_unmask(unsigned pin) -{ - void __iomem *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); - - if (pio) - __raw_writel(mask, pio + PIO_IER); -} - -static int gpio_irq_type(unsigned pin, unsigned type) -{ - return (type == IRQT_BOTHEDGE) ? 0 : -EINVAL; -} - -static struct irq_chip gpio_irqchip = { - .name = "GPIO", - .mask = gpio_irq_mask, - .unmask = gpio_irq_unmask, - .set_type = gpio_irq_type, - .set_wake = gpio_irq_set_wake, -}; - -static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) -{ - unsigned pin; - struct irq_desc *gpio; - void __iomem *pio; - u32 isr; - - pio = get_irq_chip_data(irq); - - /* temporarily mask (level sensitive) parent IRQ */ - desc->chip->ack(irq); - for (;;) { - /* reading ISR acks the pending (edge triggered) GPIO interrupt */ - isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR); - if (!isr) - break; - - pin = (unsigned) get_irq_data(irq); - gpio = &irq_desc[pin]; - - while (isr) { - if (isr & 1) { - if (unlikely(gpio->depth)) { - /* - * The core ARM interrupt handler lazily disables IRQs so - * another IRQ must be generated before it actually gets - * here to be disabled on the GPIO controller. - */ - gpio_irq_mask(pin); - } - else - desc_handle_irq(pin, gpio); - } - pin++; - gpio++; - isr >>= 1; - } - } - desc->chip->unmask(irq); - /* now it may re-trigger */ -} - -/*--------------------------------------------------------------------------*/ - -/* - * Called from the processor-specific init to enable GPIO interrupt support. - */ -void __init at91_gpio_irq_setup(void) -{ - unsigned pioc, pin; - - for (pioc = 0, pin = PIN_BASE; - pioc < gpio_banks; - pioc++) { - void __iomem *controller; - unsigned id = gpio[pioc].id; - unsigned i; - - clk_enable(gpio[pioc].clock); /* enable PIO controller's clock */ - - controller = (void __iomem *) AT91_VA_BASE_SYS + gpio[pioc].offset; - __raw_writel(~0, controller + PIO_IDR); - - set_irq_data(id, (void *) pin); - set_irq_chip_data(id, controller); - - for (i = 0; i < 32; i++, pin++) { - /* - * Can use the "simple" and not "edge" handler since it's - * shorter, and the AIC handles interupts sanely. - */ - set_irq_chip(pin, &gpio_irqchip); - set_irq_handler(pin, handle_simple_irq); - set_irq_flags(pin, IRQF_VALID); - } - - set_irq_chained_handler(id, gpio_irq_handler); - } - pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks); -} - -/* - * Called from the processor-specific init to enable GPIO pin support. - */ -void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks) -{ - BUG_ON(nr_banks > MAX_GPIO_BANKS); - - gpio = data; - gpio_banks = nr_banks; -} diff --git a/arch/arm/mach-at91rm9200/irq.c b/arch/arm/mach-at91rm9200/irq.c deleted file mode 100644 index 2148daafd29c..000000000000 --- a/arch/arm/mach-at91rm9200/irq.c +++ /dev/null @@ -1,168 +0,0 @@ -/* - * linux/arch/arm/mach-at91rm9200/irq.c - * - * Copyright (C) 2004 SAN People - * Copyright (C) 2004 ATMEL - * Copyright (C) Rick Bronson - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include - - -static void at91_aic_mask_irq(unsigned int irq) -{ - /* Disable interrupt on AIC */ - at91_sys_write(AT91_AIC_IDCR, 1 << irq); -} - -static void at91_aic_unmask_irq(unsigned int irq) -{ - /* Enable interrupt on AIC */ - at91_sys_write(AT91_AIC_IECR, 1 << irq); -} - -unsigned int at91_extern_irq; - -#define is_extern_irq(irq) ((1 << (irq)) & at91_extern_irq) - -static int at91_aic_set_type(unsigned irq, unsigned type) -{ - unsigned int smr, srctype; - - switch (type) { - case IRQT_HIGH: - srctype = AT91_AIC_SRCTYPE_HIGH; - break; - case IRQT_RISING: - srctype = AT91_AIC_SRCTYPE_RISING; - break; - case IRQT_LOW: - if ((irq == AT91_ID_FIQ) || is_extern_irq(irq)) /* only supported on external interrupts */ - srctype = AT91_AIC_SRCTYPE_LOW; - else - return -EINVAL; - break; - case IRQT_FALLING: - if ((irq == AT91_ID_FIQ) || is_extern_irq(irq)) /* only supported on external interrupts */ - srctype = AT91_AIC_SRCTYPE_FALLING; - else - return -EINVAL; - break; - default: - return -EINVAL; - } - - smr = at91_sys_read(AT91_AIC_SMR(irq)) & ~AT91_AIC_SRCTYPE; - at91_sys_write(AT91_AIC_SMR(irq), smr | srctype); - return 0; -} - -#ifdef CONFIG_PM - -static u32 wakeups; -static u32 backups; - -static int at91_aic_set_wake(unsigned irq, unsigned value) -{ - if (unlikely(irq >= 32)) - return -EINVAL; - - if (value) - wakeups |= (1 << irq); - else - wakeups &= ~(1 << irq); - - return 0; -} - -void at91_irq_suspend(void) -{ - backups = at91_sys_read(AT91_AIC_IMR); - at91_sys_write(AT91_AIC_IDCR, backups); - at91_sys_write(AT91_AIC_IECR, wakeups); -} - -void at91_irq_resume(void) -{ - at91_sys_write(AT91_AIC_IDCR, wakeups); - at91_sys_write(AT91_AIC_IECR, backups); -} - -#else -#define at91_aic_set_wake NULL -#endif - -static struct irq_chip at91_aic_chip = { - .name = "AIC", - .ack = at91_aic_mask_irq, - .mask = at91_aic_mask_irq, - .unmask = at91_aic_unmask_irq, - .set_type = at91_aic_set_type, - .set_wake = at91_aic_set_wake, -}; - -/* - * Initialize the AIC interrupt controller. - */ -void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS]) -{ - unsigned int i; - - /* - * The IVR is used by macro get_irqnr_and_base to read and verify. - * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred. - */ - for (i = 0; i < NR_AIC_IRQS; i++) { - /* Put irq number in Source Vector Register: */ - at91_sys_write(AT91_AIC_SVR(i), i); - /* Active Low interrupt, with the specified priority */ - at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]); - - set_irq_chip(i, &at91_aic_chip); - set_irq_handler(i, handle_level_irq); - set_irq_flags(i, IRQF_VALID | IRQF_PROBE); - - /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */ - if (i < 8) - at91_sys_write(AT91_AIC_EOICR, 0); - } - - /* - * Spurious Interrupt ID in Spurious Vector Register is NR_AIC_IRQS - * When there is no current interrupt, the IRQ Vector Register reads the value stored in AIC_SPU - */ - at91_sys_write(AT91_AIC_SPU, NR_AIC_IRQS); - - /* No debugging in AIC: Debug (Protect) Control Register */ - at91_sys_write(AT91_AIC_DCR, 0); - - /* Disable and clear all interrupts initially */ - at91_sys_write(AT91_AIC_IDCR, 0xFFFFFFFF); - at91_sys_write(AT91_AIC_ICCR, 0xFFFFFFFF); -} diff --git a/arch/arm/mach-at91rm9200/leds.c b/arch/arm/mach-at91rm9200/leds.c deleted file mode 100644 index 1a333730466e..000000000000 --- a/arch/arm/mach-at91rm9200/leds.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * LED driver for Atmel AT91-based boards. - * - * Copyright (C) SAN People (Pty) Ltd - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. -*/ - -#include -#include -#include - -#include -#include -#include -#include - - -static inline void at91_led_on(unsigned int led) -{ - at91_set_gpio_value(led, 0); -} - -static inline void at91_led_off(unsigned int led) -{ - at91_set_gpio_value(led, 1); -} - -static inline void at91_led_toggle(unsigned int led) -{ - unsigned long is_off = at91_get_gpio_value(led); - if (is_off) - at91_led_on(led); - else - at91_led_off(led); -} - - -/* - * Handle LED events. - */ -static void at91_leds_event(led_event_t evt) -{ - unsigned long flags; - - local_irq_save(flags); - - switch(evt) { - case led_start: /* System startup */ - at91_led_on(at91_leds_cpu); - break; - - case led_stop: /* System stop / suspend */ - at91_led_off(at91_leds_cpu); - break; - -#ifdef CONFIG_LEDS_TIMER - case led_timer: /* Every 50 timer ticks */ - at91_led_toggle(at91_leds_timer); - break; -#endif - -#ifdef CONFIG_LEDS_CPU - case led_idle_start: /* Entering idle state */ - at91_led_off(at91_leds_cpu); - break; - - case led_idle_end: /* Exit idle state */ - at91_led_on(at91_leds_cpu); - break; -#endif - - default: - break; - } - - local_irq_restore(flags); -} - - -static int __init leds_init(void) -{ - if (!at91_leds_timer || !at91_leds_cpu) - return -ENODEV; - - /* Enable PIO to access the LEDs */ - at91_set_gpio_output(at91_leds_timer, 1); - at91_set_gpio_output(at91_leds_cpu, 1); - - leds_event = at91_leds_event; - - leds_event(led_start); - return 0; -} - -__initcall(leds_init); diff --git a/arch/arm/mach-at91rm9200/pm.c b/arch/arm/mach-at91rm9200/pm.c deleted file mode 100644 index 67aa5572a3ea..000000000000 --- a/arch/arm/mach-at91rm9200/pm.c +++ /dev/null @@ -1,227 +0,0 @@ -/* - * arch/arm/mach-at91rm9200/pm.c - * AT91 Power Management - * - * Copyright (C) 2005 David Brownell - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "generic.h" - - -static int at91_pm_valid_state(suspend_state_t state) -{ - switch (state) { - case PM_SUSPEND_ON: - case PM_SUSPEND_STANDBY: - case PM_SUSPEND_MEM: - return 1; - - default: - return 0; - } -} - - -static suspend_state_t target_state; - -/* - * Called after processes are frozen, but before we shutdown devices. - */ -static int at91_pm_prepare(suspend_state_t state) -{ - target_state = state; - return 0; -} - -/* - * Verify that all the clocks are correct before entering - * slow-clock mode. - */ -static int at91_pm_verify_clocks(void) -{ - unsigned long scsr; - int i; - - scsr = at91_sys_read(AT91_PMC_SCSR); - - /* USB must not be using PLLB */ - if (cpu_is_at91rm9200()) { - if ((scsr & (AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP)) != 0) { - pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n"); - return 0; - } - } else if (cpu_is_at91sam9260()) { -#warning "Check SAM9260 USB clocks" - } else if (cpu_is_at91sam9261()) { -#warning "Check SAM9261 USB clocks" - } - -#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS - /* PCK0..PCK3 must be disabled, or configured to use clk32k */ - for (i = 0; i < 4; i++) { - u32 css; - - if ((scsr & (AT91_PMC_PCK0 << i)) == 0) - continue; - - css = at91_sys_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS; - if (css != AT91_PMC_CSS_SLOW) { - pr_debug("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css); - return 0; - } - } -#endif - - return 1; -} - -/* - * Call this from platform driver suspend() to see how deeply to suspend. - * For example, some controllers (like OHCI) need one of the PLL clocks - * in order to act as a wakeup source, and those are not available when - * going into slow clock mode. - * - * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have - * the very same problem (but not using at91 main_clk), and it'd be better - * to add one generic API rather than lots of platform-specific ones. - */ -int at91_suspend_entering_slow_clock(void) -{ - return (target_state == PM_SUSPEND_MEM); -} -EXPORT_SYMBOL(at91_suspend_entering_slow_clock); - - -static void (*slow_clock)(void); - - -static int at91_pm_enter(suspend_state_t state) -{ - at91_gpio_suspend(); - at91_irq_suspend(); - - pr_debug("AT91: PM - wake mask %08x, pm state %d\n", - /* remember all the always-wake irqs */ - (at91_sys_read(AT91_PMC_PCSR) - | (1 << AT91_ID_FIQ) - | (1 << AT91_ID_SYS) - | (at91_extern_irq)) - & at91_sys_read(AT91_AIC_IMR), - state); - - switch (state) { - /* - * Suspend-to-RAM is like STANDBY plus slow clock mode, so - * drivers must suspend more deeply: only the master clock - * controller may be using the main oscillator. - */ - case PM_SUSPEND_MEM: - /* - * Ensure that clocks are in a valid state. - */ - if (!at91_pm_verify_clocks()) - goto error; - - /* - * Enter slow clock mode by switching over to clk32k and - * turning off the main oscillator; reverse on wakeup. - */ - if (slow_clock) { - slow_clock(); - break; - } else { - /* DEVELOPMENT ONLY */ - pr_info("AT91: PM - no slow clock mode yet ...\n"); - /* FALLTHROUGH leaving master clock alone */ - } - - /* - * STANDBY mode has *all* drivers suspended; ignores irqs not - * marked as 'wakeup' event sources; and reduces DRAM power. - * But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and - * nothing fancy done with main or cpu clocks. - */ - case PM_SUSPEND_STANDBY: - /* - * NOTE: the Wait-for-Interrupt instruction needs to be - * in icache so the SDRAM stays in self-refresh mode until - * the wakeup IRQ occurs. - */ - asm("b 1f; .align 5; 1:"); - asm("mcr p15, 0, r0, c7, c10, 4"); /* drain write buffer */ - at91_sys_write(AT91_SDRAMC_SRR, 1); /* self-refresh mode */ - /* fall though to next state */ - - case PM_SUSPEND_ON: - asm("mcr p15, 0, r0, c7, c0, 4"); /* wait for interrupt */ - break; - - default: - pr_debug("AT91: PM - bogus suspend state %d\n", state); - goto error; - } - - pr_debug("AT91: PM - wakeup %08x\n", - at91_sys_read(AT91_AIC_IPR) & at91_sys_read(AT91_AIC_IMR)); - -error: - target_state = PM_SUSPEND_ON; - at91_irq_resume(); - at91_gpio_resume(); - return 0; -} - - -static struct pm_ops at91_pm_ops ={ - .pm_disk_mode = 0, - .valid = at91_pm_valid_state, - .prepare = at91_pm_prepare, - .enter = at91_pm_enter, -}; - -static int __init at91_pm_init(void) -{ - printk("AT91: Power Management\n"); - -#ifdef CONFIG_AT91_PM_SLOW_CLOCK - /* REVISIT allocations of SRAM should be dynamically managed. - * FIQ handlers and other components will want SRAM/TCM too... - */ - slow_clock = (void *) (AT91_VA_BASE_SRAM + (3 * SZ_4K)); - memcpy(slow_clock, at91rm9200_slow_clock, at91rm9200_slow_clock_sz); -#endif - - /* Disable SDRAM low-power mode. Cannot be used with self-refresh. */ - at91_sys_write(AT91_SDRAMC_LPR, 0); - - pm_set_ops(&at91_pm_ops); - - return 0; -} -arch_initcall(at91_pm_init); diff --git a/arch/avr32/mach-at32ap/clock.c b/arch/avr32/mach-at32ap/clock.c index 3d0d1097389f..ecbd4a21e432 100644 --- a/arch/avr32/mach-at32ap/clock.c +++ b/arch/avr32/mach-at32ap/clock.c @@ -3,7 +3,7 @@ * * Copyright (C) 2006 Atmel Corporation * - * Based on arch/arm/mach-at91rm9200/clock.c + * Based on arch/arm/mach-at91/clock.c * Copyright (C) 2005 David Brownell * Copyright (C) 2005 Ivan Kokshaysky * diff --git a/arch/avr32/mach-at32ap/clock.h b/arch/avr32/mach-at32ap/clock.h index f953f044ba4d..bb8e1f295835 100644 --- a/arch/avr32/mach-at32ap/clock.h +++ b/arch/avr32/mach-at32ap/clock.h @@ -3,7 +3,7 @@ * * Copyright (C) 2006 Atmel Corporation * - * Based on arch/arm/mach-at91rm9200/clock.c + * Based on arch/arm/mach-at91/clock.c * Copyright (C) 2005 David Brownell * Copyright (C) 2005 Ivan Kokshaysky * diff --git a/include/asm-arm/arch-at91/at91_aic.h b/include/asm-arm/arch-at91/at91_aic.h new file mode 100644 index 000000000000..df44c12a12d4 --- /dev/null +++ b/include/asm-arm/arch-at91/at91_aic.h @@ -0,0 +1,53 @@ +/* + * include/asm-arm/arch-at91/at91_aic.h + * + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) SAN People + * + * Advanced Interrupt Controller (AIC) - System peripherals registers. + * Based on AT91RM9200 datasheet revision E. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_AIC_H +#define AT91_AIC_H + +#define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */ +#define AT91_AIC_PRIOR (7 << 0) /* Priority Level */ +#define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */ +#define AT91_AIC_SRCTYPE_LOW (0 << 5) +#define AT91_AIC_SRCTYPE_FALLING (1 << 5) +#define AT91_AIC_SRCTYPE_HIGH (2 << 5) +#define AT91_AIC_SRCTYPE_RISING (3 << 5) + +#define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */ +#define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */ +#define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */ +#define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */ +#define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */ + +#define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */ +#define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */ +#define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */ +#define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */ +#define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */ + +#define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */ +#define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */ +#define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */ +#define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */ +#define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */ +#define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */ +#define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */ +#define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */ +#define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */ + +#define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */ +#define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */ +#define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */ + +#endif diff --git a/include/asm-arm/arch-at91/at91_dbgu.h b/include/asm-arm/arch-at91/at91_dbgu.h new file mode 100644 index 000000000000..1002a808ad91 --- /dev/null +++ b/include/asm-arm/arch-at91/at91_dbgu.h @@ -0,0 +1,45 @@ +/* + * include/asm-arm/arch-at91/at91_dbgu.h + * + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) SAN People + * + * Debug Unit (DBGU) - System peripherals registers. + * Based on AT91RM9200 datasheet revision E. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_DBGU_H +#define AT91_DBGU_H + +#define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */ +#define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */ +#define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */ +#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */ +#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */ +#define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable Register */ +#define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask Register */ +#define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */ +#define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding Register */ +#define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding Register */ +#define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator Register */ + +#define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */ +#define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */ +#define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */ +#define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */ +#define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */ +#define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */ +#define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */ +#define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */ +#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */ +#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */ + +#define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */ +#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */ + +#endif diff --git a/include/asm-arm/arch-at91/at91_ecc.h b/include/asm-arm/arch-at91/at91_ecc.h new file mode 100644 index 000000000000..ff93df516d6d --- /dev/null +++ b/include/asm-arm/arch-at91/at91_ecc.h @@ -0,0 +1,38 @@ +/* + * include/asm-arm/arch-at91/at91_ecc.h + * + * Error Corrected Code Controller (ECC) - System peripherals regsters. + * Based on AT91SAM9260 datasheet revision B. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef AT91_ECC_H +#define AT91_ECC_H + +#define AT91_ECC_CR (AT91_ECC + 0x00) /* Control register */ +#define AT91_ECC_RST (1 << 0) /* Reset parity */ + +#define AT91_ECC_MR (AT91_ECC + 0x04) /* Mode register */ +#define AT91_ECC_PAGESIZE (3 << 0) /* Page Size */ +#define AT91_ECC_PAGESIZE_528 (0) +#define AT91_ECC_PAGESIZE_1056 (1) +#define AT91_ECC_PAGESIZE_2112 (2) +#define AT91_ECC_PAGESIZE_4224 (3) + +#define AT91_ECC_SR (AT91_ECC + 0x08) /* Status register */ +#define AT91_ECC_RECERR (1 << 0) /* Recoverable Error */ +#define AT91_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */ +#define AT91_ECC_MULERR (1 << 2) /* Multiple Errors */ + +#define AT91_ECC_PR (AT91_ECC + 0x0c) /* Parity register */ +#define AT91_ECC_BITADDR (0xf << 0) /* Bit Error Address */ +#define AT91_ECC_WORDADDR (0xfff << 4) /* Word Error Address */ + +#define AT91_ECC_NPR (AT91_ECC + 0x10) /* NParity register */ +#define AT91_ECC_NPARITY (0xffff << 0) /* NParity */ + +#endif diff --git a/include/asm-arm/arch-at91/at91_lcdc.h b/include/asm-arm/arch-at91/at91_lcdc.h new file mode 100644 index 000000000000..ab040a40d37b --- /dev/null +++ b/include/asm-arm/arch-at91/at91_lcdc.h @@ -0,0 +1,148 @@ +/* + * include/asm-arm/arch-at91/at91_lcdc.h + * + * LCD Controller (LCDC). + * Based on AT91SAM9261 datasheet revision E. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_LCDC_H +#define AT91_LCDC_H + +#define AT91_LCDC_DMABADDR1 0x00 /* DMA Base Address Register 1 */ +#define AT91_LCDC_DMABADDR2 0x04 /* DMA Base Address Register 2 */ +#define AT91_LCDC_DMAFRMPT1 0x08 /* DMA Frame Pointer Register 1 */ +#define AT91_LCDC_DMAFRMPT2 0x0c /* DMA Frame Pointer Register 2 */ +#define AT91_LCDC_DMAFRMADD1 0x10 /* DMA Frame Address Register 1 */ +#define AT91_LCDC_DMAFRMADD2 0x14 /* DMA Frame Address Register 2 */ + +#define AT91_LCDC_DMAFRMCFG 0x18 /* DMA Frame Configuration Register */ +#define AT91_LCDC_FRSIZE (0x7fffff << 0) /* Frame Size */ +#define AT91_LCDC_BLENGTH (0x7f << 24) /* Burst Length */ + +#define AT91_LCDC_DMACON 0x1c /* DMA Control Register */ +#define AT91_LCDC_DMAEN (0x1 << 0) /* DMA Enable */ +#define AT91_LCDC_DMARST (0x1 << 1) /* DMA Reset */ +#define AT91_LCDC_DMABUSY (0x1 << 2) /* DMA Busy */ + +#define AT91_LCDC_LCDCON1 0x0800 /* LCD Control Register 1 */ +#define AT91_LCDC_BYPASS (1 << 0) /* Bypass lcd_dotck divider */ +#define AT91_LCDC_CLKVAL (0x1ff << 12) /* Clock Divider */ +#define AT91_LCDC_LINCNT (0x7ff << 21) /* Line Counter */ + +#define AT91_LCDC_LCDCON2 0x0804 /* LCD Control Register 2 */ +#define AT91_LCDC_DISTYPE (3 << 0) /* Display Type */ +#define AT91_LCDC_DISTYPE_STNMONO (0 << 0) +#define AT91_LCDC_DISTYPE_STNCOLOR (1 << 0) +#define AT91_LCDC_DISTYPE_TFT (2 << 0) +#define AT91_LCDC_SCANMOD (1 << 2) /* Scan Mode */ +#define AT91_LCDC_SCANMOD_SINGLE (0 << 2) +#define AT91_LCDC_SCANMOD_DUAL (1 << 2) +#define AT91_LCDC_IFWIDTH (3 << 3) /*Interface Width */ +#define AT91_LCDC_IFWIDTH_4 (0 << 3) +#define AT91_LCDC_IFWIDTH_8 (1 << 3) +#define AT91_LCDC_IFWIDTH_16 (2 << 3) +#define AT91_LCDC_PIXELSIZE (7 << 5) /* Bits per pixel */ +#define AT91_LCDC_PIXELSIZE_1 (0 << 5) +#define AT91_LCDC_PIXELSIZE_2 (1 << 5) +#define AT91_LCDC_PIXELSIZE_4 (2 << 5) +#define AT91_LCDC_PIXELSIZE_8 (3 << 5) +#define AT91_LCDC_PIXELSIZE_16 (4 << 5) +#define AT91_LCDC_PIXELSIZE_24 (5 << 5) +#define AT91_LCDC_INVVD (1 << 8) /* LCD Data polarity */ +#define AT91_LCDC_INVVD_NORMAL (0 << 8) +#define AT91_LCDC_INVVD_INVERTED (1 << 8) +#define AT91_LCDC_INVFRAME (1 << 9 ) /* LCD VSync polarity */ +#define AT91_LCDC_INVFRAME_NORMAL (0 << 9) +#define AT91_LCDC_INVFRAME_INVERTED (1 << 9) +#define AT91_LCDC_INVLINE (1 << 10) /* LCD HSync polarity */ +#define AT91_LCDC_INVLINE_NORMAL (0 << 10) +#define AT91_LCDC_INVLINE_INVERTED (1 << 10) +#define AT91_LCDC_INVCLK (1 << 11) /* LCD dotclk polarity */ +#define AT91_LCDC_INVCLK_NORMAL (0 << 11) +#define AT91_LCDC_INVCLK_INVERTED (1 << 11) +#define AT91_LCDC_INVDVAL (1 << 12) /* LCD dval polarity */ +#define AT91_LCDC_INVDVAL_NORMAL (0 << 12) +#define AT91_LCDC_INVDVAL_INVERTED (1 << 12) +#define AT91_LCDC_CLKMOD (1 << 15) /* LCD dotclk mode */ +#define AT91_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15) +#define AT91_LCDC_CLKMOD_ALWAYSACTIVE (1 << 15) +#define AT91_LCDC_MEMOR (1 << 31) /* Memory Ordering Format */ +#define AT91_LCDC_MEMOR_BIG (0 << 31) +#define AT91_LCDC_MEMOR_LITTLE (1 << 31) + +#define AT91_LCDC_TIM1 0x0808 /* LCD Timing Register 1 */ +#define AT91_LCDC_VFP (0xff << 0) /* Vertical Front Porch */ +#define AT91_LCDC_VBP (0xff << 8) /* Vertical Back Porch */ +#define AT91_LCDC_VPW (0x3f << 16) /* Vertical Synchronization Pulse Width */ +#define AT91_LCDC_VHDLY (0xf << 24) /* Vertical to Horizontal Delay */ + +#define AT91_LCDC_TIM2 0x080c /* LCD Timing Register 2 */ +#define AT91_LCDC_HBP (0xff << 0) /* Horizontal Back Porch */ +#define AT91_LCDC_HPW (0x3f << 8) /* Horizontal Synchronization Pulse Width */ +#define AT91_LCDC_HFP (0x7ff << 21) /* Horizontal Front Porch */ + +#define AT91_LCDC_LCDFRMCFG 0x0810 /* LCD Frame Configuration Register */ +#define AT91_LCDC_LINEVAL (0x7ff << 0) /* Vertical Size of LCD Module */ +#define AT91_LCDC_HOZVAL (0x7ff << 21) /* Horizontal Size of LCD Module */ + +#define AT91_LCDC_FIFO 0x0814 /* LCD FIFO Register */ +#define AT91_LCDC_FIFOTH (0xffff) /* FIFO Threshold */ + +#define AT91_LCDC_DP1_2 0x081c /* Dithering Pattern DP1_2 Register */ +#define AT91_LCDC_DP4_7 0x0820 /* Dithering Pattern DP4_7 Register */ +#define AT91_LCDC_DP3_5 0x0824 /* Dithering Pattern DP3_5 Register */ +#define AT91_LCDC_DP2_3 0x0828 /* Dithering Pattern DP2_3 Register */ +#define AT91_LCDC_DP5_7 0x082c /* Dithering Pattern DP5_7 Register */ +#define AT91_LCDC_DP3_4 0x0830 /* Dithering Pattern DP3_4 Register */ +#define AT91_LCDC_DP4_5 0x0834 /* Dithering Pattern DP4_5 Register */ +#define AT91_LCDC_DP6_7 0x0838 /* Dithering Pattern DP6_7 Register */ +#define AT91_LCDC_DP1_2_VAL (0xff) +#define AT91_LCDC_DP4_7_VAL (0xfffffff) +#define AT91_LCDC_DP3_5_VAL (0xfffff) +#define AT91_LCDC_DP2_3_VAL (0xfff) +#define AT91_LCDC_DP5_7_VAL (0xfffffff) +#define AT91_LCDC_DP3_4_VAL (0xffff) +#define AT91_LCDC_DP4_5_VAL (0xfffff) +#define AT91_LCDC_DP6_7_VAL (0xfffffff) + +#define AT91_LCDC_PWRCON 0x083c /* Power Control Register */ +#define AT91_LCDC_PWR (1 << 0) /* LCD Module Power Control */ +#define AT91_LCDC_GUARDT (0x7f << 1) /* Delay in Frame Period */ +#define AT91_LCDC_BUSY (1 << 31) /* LCD Busy */ + +#define AT91_LCDC_CONTRAST_CTR 0x0840 /* Contrast Control Register */ +#define AT91_LCDC_PS (3 << 0) /* Contrast Counter Prescaler */ +#define AT91_LCDC_PS_DIV1 (0 << 0) +#define AT91_LCDC_PS_DIV2 (1 << 0) +#define AT91_LCDC_PS_DIV4 (2 << 0) +#define AT91_LCDC_PS_DIV8 (3 << 0) +#define AT91_LCDC_POL (1 << 2) /* Polarity of output Pulse */ +#define AT91_LCDC_POL_NEGATIVE (0 << 2) +#define AT91_LCDC_POL_POSITIVE (1 << 2) +#define AT91_LCDC_ENA (1 << 3) /* PWM generator Control */ +#define AT91_LCDC_ENA_PWMDISABLE (0 << 3) +#define AT91_LCDC_ENA_PWMENABLE (1 << 3) + +#define AT91_LCDC_CONTRAST_VAL 0x0844 /* Contrast Value Register */ +#define AT91_LCDC_CVAL (0xff) /* PWM compare value */ + +#define AT91_LCDC_IER 0x0848 /* Interrupt Enable Register */ +#define AT91_LCDC_IDR 0x084c /* Interrupt Disable Register */ +#define AT91_LCDC_IMR 0x0850 /* Interrupt Mask Register */ +#define AT91_LCDC_ISR 0x0854 /* Interrupt Enable Register */ +#define AT91_LCDC_ICR 0x0858 /* Interrupt Clear Register */ +#define AT91_LCDC_LNI (1 << 0) /* Line Interrupt */ +#define AT91_LCDC_LSTLNI (1 << 1) /* Last Line Interrupt */ +#define AT91_LCDC_EOFI (1 << 2) /* DMA End Of Frame Interrupt */ +#define AT91_LCDC_UFLWI (1 << 4) /* FIFO Underflow Interrupt */ +#define AT91_LCDC_OWRI (1 << 5) /* FIFO Overwrite Interrupt */ +#define AT91_LCDC_MERI (1 << 6) /* DMA Memory Error Interrupt */ + +#define AT91_LCDC_LUT_(n) (0x0c00 + ((n)*4)) /* Palette Entry 0..255 */ + +#endif diff --git a/include/asm-arm/arch-at91/at91_mci.h b/include/asm-arm/arch-at91/at91_mci.h new file mode 100644 index 000000000000..40a9876b661a --- /dev/null +++ b/include/asm-arm/arch-at91/at91_mci.h @@ -0,0 +1,106 @@ +/* + * include/asm-arm/arch-at91/at91_mci.h + * + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) SAN People + * + * MultiMedia Card Interface (MCI) registers. + * Based on AT91RM9200 datasheet revision F. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_MCI_H +#define AT91_MCI_H + +#define AT91_MCI_CR 0x00 /* Control Register */ +#define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */ +#define AT91_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */ +#define AT91_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */ +#define AT91_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */ +#define AT91_MCI_SWRST (1 << 7) /* Software Reset */ + +#define AT91_MCI_MR 0x04 /* Mode Register */ +#define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */ +#define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */ +#define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ +#define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ +#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ + +#define AT91_MCI_DTOR 0x08 /* Data Timeout Register */ +#define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */ +#define AT91_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */ +#define AT91_MCI_DTOMUL_1 (0 << 4) +#define AT91_MCI_DTOMUL_16 (1 << 4) +#define AT91_MCI_DTOMUL_128 (2 << 4) +#define AT91_MCI_DTOMUL_256 (3 << 4) +#define AT91_MCI_DTOMUL_1K (4 << 4) +#define AT91_MCI_DTOMUL_4K (5 << 4) +#define AT91_MCI_DTOMUL_64K (6 << 4) +#define AT91_MCI_DTOMUL_1M (7 << 4) + +#define AT91_MCI_SDCR 0x0c /* SD Card Register */ +#define AT91_MCI_SDCSEL (3 << 0) /* SD Card Selector */ +#define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */ + +#define AT91_MCI_ARGR 0x10 /* Argument Register */ + +#define AT91_MCI_CMDR 0x14 /* Command Register */ +#define AT91_MCI_CMDNB (0x3f << 0) /* Command Number */ +#define AT91_MCI_RSPTYP (3 << 6) /* Response Type */ +#define AT91_MCI_RSPTYP_NONE (0 << 6) +#define AT91_MCI_RSPTYP_48 (1 << 6) +#define AT91_MCI_RSPTYP_136 (2 << 6) +#define AT91_MCI_SPCMD (7 << 8) /* Special Command */ +#define AT91_MCI_SPCMD_NONE (0 << 8) +#define AT91_MCI_SPCMD_INIT (1 << 8) +#define AT91_MCI_SPCMD_SYNC (2 << 8) +#define AT91_MCI_SPCMD_ICMD (4 << 8) +#define AT91_MCI_SPCMD_IRESP (5 << 8) +#define AT91_MCI_OPDCMD (1 << 11) /* Open Drain Command */ +#define AT91_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */ +#define AT91_MCI_TRCMD (3 << 16) /* Transfer Command */ +#define AT91_MCI_TRCMD_NONE (0 << 16) +#define AT91_MCI_TRCMD_START (1 << 16) +#define AT91_MCI_TRCMD_STOP (2 << 16) +#define AT91_MCI_TRDIR (1 << 18) /* Transfer Direction */ +#define AT91_MCI_TRTYP (3 << 19) /* Transfer Type */ +#define AT91_MCI_TRTYP_BLOCK (0 << 19) +#define AT91_MCI_TRTYP_MULTIPLE (1 << 19) +#define AT91_MCI_TRTYP_STREAM (2 << 19) + +#define AT91_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */ +#define AT91_MCR_RDR 0x30 /* Receive Data Register */ +#define AT91_MCR_TDR 0x34 /* Transmit Data Register */ + +#define AT91_MCI_SR 0x40 /* Status Register */ +#define AT91_MCI_CMDRDY (1 << 0) /* Command Ready */ +#define AT91_MCI_RXRDY (1 << 1) /* Receiver Ready */ +#define AT91_MCI_TXRDY (1 << 2) /* Transmit Ready */ +#define AT91_MCI_BLKE (1 << 3) /* Data Block Ended */ +#define AT91_MCI_DTIP (1 << 4) /* Data Transfer in Progress */ +#define AT91_MCI_NOTBUSY (1 << 5) /* Data Not Busy */ +#define AT91_MCI_ENDRX (1 << 6) /* End of RX Buffer */ +#define AT91_MCI_ENDTX (1 << 7) /* End fo TX Buffer */ +#define AT91_MCI_SDIOIRQA (1 << 8) /* SDIO Interrupt for Slot A */ +#define At91_MCI_SDIOIRQB (1 << 9) /* SDIO Interrupt for Slot B [AT91RM9200 only] */ +#define AT91_MCI_RXBUFF (1 << 14) /* RX Buffer Full */ +#define AT91_MCI_TXBUFE (1 << 15) /* TX Buffer Empty */ +#define AT91_MCI_RINDE (1 << 16) /* Response Index Error */ +#define AT91_MCI_RDIRE (1 << 17) /* Response Direction Error */ +#define AT91_MCI_RCRCE (1 << 18) /* Response CRC Error */ +#define AT91_MCI_RENDE (1 << 19) /* Response End Bit Error */ +#define AT91_MCI_RTOE (1 << 20) /* Reponse Time-out Error */ +#define AT91_MCI_DCRCE (1 << 21) /* Data CRC Error */ +#define AT91_MCI_DTOE (1 << 22) /* Data Time-out Error */ +#define AT91_MCI_OVRE (1 << 30) /* Overrun */ +#define AT91_MCI_UNRE (1 << 31) /* Underrun */ + +#define AT91_MCI_IER 0x44 /* Interrupt Enable Register */ +#define AT91_MCI_IDR 0x48 /* Interrupt Disable Register */ +#define AT91_MCI_IMR 0x4c /* Interrupt Mask Register */ + +#endif diff --git a/include/asm-arm/arch-at91/at91_pdc.h b/include/asm-arm/arch-at91/at91_pdc.h new file mode 100644 index 000000000000..a54adf52c65d --- /dev/null +++ b/include/asm-arm/arch-at91/at91_pdc.h @@ -0,0 +1,36 @@ +/* + * include/asm-arm/arch-at91/at91_pdc.h + * + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) SAN People + * + * Peripheral Data Controller (PDC) registers. + * Based on AT91RM9200 datasheet revision E. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_PDC_H +#define AT91_PDC_H + +#define AT91_PDC_RPR 0x100 /* Receive Pointer Register */ +#define AT91_PDC_RCR 0x104 /* Receive Counter Register */ +#define AT91_PDC_TPR 0x108 /* Transmit Pointer Register */ +#define AT91_PDC_TCR 0x10c /* Transmit Counter Register */ +#define AT91_PDC_RNPR 0x110 /* Receive Next Pointer Register */ +#define AT91_PDC_RNCR 0x114 /* Receive Next Counter Register */ +#define AT91_PDC_TNPR 0x118 /* Transmit Next Pointer Register */ +#define AT91_PDC_TNCR 0x11c /* Transmit Next Counter Register */ + +#define AT91_PDC_PTCR 0x120 /* Transfer Control Register */ +#define AT91_PDC_RXTEN (1 << 0) /* Receiver Transfer Enable */ +#define AT91_PDC_RXTDIS (1 << 1) /* Receiver Transfer Disable */ +#define AT91_PDC_TXTEN (1 << 8) /* Transmitter Transfer Enable */ +#define AT91_PDC_TXTDIS (1 << 9) /* Transmitter Transfer Disable */ + +#define AT91_PDC_PTSR 0x124 /* Transfer Status Register */ + +#endif diff --git a/include/asm-arm/arch-at91/at91_pio.h b/include/asm-arm/arch-at91/at91_pio.h new file mode 100644 index 000000000000..84c3866d309f --- /dev/null +++ b/include/asm-arm/arch-at91/at91_pio.h @@ -0,0 +1,49 @@ +/* + * include/asm-arm/arch-at91/at91_pio.h + * + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) SAN People + * + * Parallel I/O Controller (PIO) - System peripherals registers. + * Based on AT91RM9200 datasheet revision E. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_PIO_H +#define AT91_PIO_H + +#define PIO_PER 0x00 /* Enable Register */ +#define PIO_PDR 0x04 /* Disable Register */ +#define PIO_PSR 0x08 /* Status Register */ +#define PIO_OER 0x10 /* Output Enable Register */ +#define PIO_ODR 0x14 /* Output Disable Register */ +#define PIO_OSR 0x18 /* Output Status Register */ +#define PIO_IFER 0x20 /* Glitch Input Filter Enable */ +#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */ +#define PIO_IFSR 0x28 /* Glitch Input Filter Status */ +#define PIO_SODR 0x30 /* Set Output Data Register */ +#define PIO_CODR 0x34 /* Clear Output Data Register */ +#define PIO_ODSR 0x38 /* Output Data Status Register */ +#define PIO_PDSR 0x3c /* Pin Data Status Register */ +#define PIO_IER 0x40 /* Interrupt Enable Register */ +#define PIO_IDR 0x44 /* Interrupt Disable Register */ +#define PIO_IMR 0x48 /* Interrupt Mask Register */ +#define PIO_ISR 0x4c /* Interrupt Status Register */ +#define PIO_MDER 0x50 /* Multi-driver Enable Register */ +#define PIO_MDDR 0x54 /* Multi-driver Disable Register */ +#define PIO_MDSR 0x58 /* Multi-driver Status Register */ +#define PIO_PUDR 0x60 /* Pull-up Disable Register */ +#define PIO_PUER 0x64 /* Pull-up Enable Register */ +#define PIO_PUSR 0x68 /* Pull-up Status Register */ +#define PIO_ASR 0x70 /* Peripheral A Select Register */ +#define PIO_BSR 0x74 /* Peripheral B Select Register */ +#define PIO_ABSR 0x78 /* AB Status Register */ +#define PIO_OWER 0xa0 /* Output Write Enable Register */ +#define PIO_OWDR 0xa4 /* Output Write Disable Register */ +#define PIO_OWSR 0xa8 /* Output Write Status Register */ + +#endif diff --git a/include/asm-arm/arch-at91/at91_pit.h b/include/asm-arm/arch-at91/at91_pit.h new file mode 100644 index 000000000000..5026325a5ae4 --- /dev/null +++ b/include/asm-arm/arch-at91/at91_pit.h @@ -0,0 +1,29 @@ +/* + * include/asm-arm/arch-at91/at91_pit.h + * + * Periodic Interval Timer (PIT) - System peripherals regsters. + * Based on AT91SAM9261 datasheet revision D. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_PIT_H +#define AT91_PIT_H + +#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */ +#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */ +#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */ +#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */ + +#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */ +#define AT91_PIT_PITS (1 << 0) /* Timer Status */ + +#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */ +#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */ +#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */ +#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */ + +#endif diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h new file mode 100644 index 000000000000..33ff5b6798ee --- /dev/null +++ b/include/asm-arm/arch-at91/at91_pmc.h @@ -0,0 +1,92 @@ +/* + * include/asm-arm/arch-at91/at91_pmc.h + * + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) SAN People + * + * Power Management Controller (PMC) - System peripherals registers. + * Based on AT91RM9200 datasheet revision E. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_PMC_H +#define AT91_PMC_H + +#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ +#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ + +#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */ +#define AT91_PMC_PCK (1 << 0) /* Processor Clock */ +#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ +#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ +#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ +#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ +#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ +#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ +#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ +#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ +#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ +#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ +#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ + +#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */ +#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ +#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ + +#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register */ +#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ +#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */ +#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ + +#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ +#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ +#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ + +#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */ +#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */ +#define AT91_PMC_DIV (0xff << 0) /* Divider */ +#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ +#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ +#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ +#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ + +#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ +#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ +#define AT91_PMC_CSS_SLOW (0 << 0) +#define AT91_PMC_CSS_MAIN (1 << 0) +#define AT91_PMC_CSS_PLLA (2 << 0) +#define AT91_PMC_CSS_PLLB (3 << 0) +#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ +#define AT91_PMC_PRES_1 (0 << 2) +#define AT91_PMC_PRES_2 (1 << 2) +#define AT91_PMC_PRES_4 (2 << 2) +#define AT91_PMC_PRES_8 (3 << 2) +#define AT91_PMC_PRES_16 (4 << 2) +#define AT91_PMC_PRES_32 (5 << 2) +#define AT91_PMC_PRES_64 (6 << 2) +#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ +#define AT91_PMC_MDIV_1 (0 << 8) +#define AT91_PMC_MDIV_2 (1 << 8) +#define AT91_PMC_MDIV_3 (2 << 8) +#define AT91_PMC_MDIV_4 (3 << 8) + +#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ + +#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ +#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ +#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ +#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ +#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ +#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ +#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ +#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ +#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ +#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ +#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ +#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ + +#endif diff --git a/include/asm-arm/arch-at91/at91_rstc.h b/include/asm-arm/arch-at91/at91_rstc.h new file mode 100644 index 000000000000..0b7afbc015a2 --- /dev/null +++ b/include/asm-arm/arch-at91/at91_rstc.h @@ -0,0 +1,39 @@ +/* + * include/asm-arm/arch-at91/at91_rstc.h + * + * Reset Controller (RSTC) - System peripherals regsters. + * Based on AT91SAM9261 datasheet revision D. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_RSTC_H +#define AT91_RSTC_H + +#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */ +#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ +#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ +#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ +#define AT91_RSTC_KEY (0xff << 24) /* KEY Password */ + +#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */ +#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ +#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ +#define AT91_RSTC_RSTTYP_GENERAL (0 << 8) +#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8) +#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8) +#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8) +#define AT91_RSTC_RSTTYP_USER (4 << 8) +#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */ +#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */ + +#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */ +#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */ +#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ +#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */ +#define AT91_RSTC_KEY (0xff << 24) /* KEY Password */ + +#endif diff --git a/include/asm-arm/arch-at91/at91_rtc.h b/include/asm-arm/arch-at91/at91_rtc.h new file mode 100644 index 000000000000..af9bd28174c0 --- /dev/null +++ b/include/asm-arm/arch-at91/at91_rtc.h @@ -0,0 +1,75 @@ +/* + * include/asm-arm/arch-at91/at91_rtc.h + * + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) SAN People + * + * Real Time Clock (RTC) - System peripheral registers. + * Based on AT91RM9200 datasheet revision E. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_RTC_H +#define AT91_RTC_H + +#define AT91_RTC_CR (AT91_RTC + 0x00) /* Control Register */ +#define AT91_RTC_UPDTIM (1 << 0) /* Update Request Time Register */ +#define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */ +#define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */ +#define AT91_RTC_TIMEVSEL_MINUTE (0 << 8) +#define AT91_RTC_TIMEVSEL_HOUR (1 << 8) +#define AT91_RTC_TIMEVSEL_DAY24 (2 << 8) +#define AT91_RTC_TIMEVSEL_DAY12 (3 << 8) +#define AT91_RTC_CALEVSEL (3 << 16) /* Calendar Event Selection */ +#define AT91_RTC_CALEVSEL_WEEK (0 << 16) +#define AT91_RTC_CALEVSEL_MONTH (1 << 16) +#define AT91_RTC_CALEVSEL_YEAR (2 << 16) + +#define AT91_RTC_MR (AT91_RTC + 0x04) /* Mode Register */ +#define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */ + +#define AT91_RTC_TIMR (AT91_RTC + 0x08) /* Time Register */ +#define AT91_RTC_SEC (0x7f << 0) /* Current Second */ +#define AT91_RTC_MIN (0x7f << 8) /* Current Minute */ +#define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */ +#define AT91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */ + +#define AT91_RTC_CALR (AT91_RTC + 0x0c) /* Calendar Register */ +#define AT91_RTC_CENT (0x7f << 0) /* Current Century */ +#define AT91_RTC_YEAR (0xff << 8) /* Current Year */ +#define AT91_RTC_MONTH (0x1f << 16) /* Current Month */ +#define AT91_RTC_DAY (7 << 21) /* Current Day */ +#define AT91_RTC_DATE (0x3f << 24) /* Current Date */ + +#define AT91_RTC_TIMALR (AT91_RTC + 0x10) /* Time Alarm Register */ +#define AT91_RTC_SECEN (1 << 7) /* Second Alarm Enable */ +#define AT91_RTC_MINEN (1 << 15) /* Minute Alarm Enable */ +#define AT91_RTC_HOUREN (1 << 23) /* Hour Alarm Enable */ + +#define AT91_RTC_CALALR (AT91_RTC + 0x14) /* Calendar Alarm Register */ +#define AT91_RTC_MTHEN (1 << 23) /* Month Alarm Enable */ +#define AT91_RTC_DATEEN (1 << 31) /* Date Alarm Enable */ + +#define AT91_RTC_SR (AT91_RTC + 0x18) /* Status Register */ +#define AT91_RTC_ACKUPD (1 << 0) /* Acknowledge for Update */ +#define AT91_RTC_ALARM (1 << 1) /* Alarm Flag */ +#define AT91_RTC_SECEV (1 << 2) /* Second Event */ +#define AT91_RTC_TIMEV (1 << 3) /* Time Event */ +#define AT91_RTC_CALEV (1 << 4) /* Calendar Event */ + +#define AT91_RTC_SCCR (AT91_RTC + 0x1c) /* Status Clear Command Register */ +#define AT91_RTC_IER (AT91_RTC + 0x20) /* Interrupt Enable Register */ +#define AT91_RTC_IDR (AT91_RTC + 0x24) /* Interrupt Disable Register */ +#define AT91_RTC_IMR (AT91_RTC + 0x28) /* Interrupt Mask Register */ + +#define AT91_RTC_VER (AT91_RTC + 0x2c) /* Valid Entry Register */ +#define AT91_RTC_NVTIM (1 << 0) /* Non valid Time */ +#define AT91_RTC_NVCAL (1 << 1) /* Non valid Calendar */ +#define AT91_RTC_NVTIMALR (1 << 2) /* Non valid Time Alarm */ +#define AT91_RTC_NVCALALR (1 << 3) /* Non valid Calendar Alarm */ + +#endif diff --git a/include/asm-arm/arch-at91/at91_rtt.h b/include/asm-arm/arch-at91/at91_rtt.h new file mode 100644 index 000000000000..bae1103fbbb2 --- /dev/null +++ b/include/asm-arm/arch-at91/at91_rtt.h @@ -0,0 +1,32 @@ +/* + * include/asm-arm/arch-at91/at91_rtt.h + * + * Real-time Timer (RTT) - System peripherals regsters. + * Based on AT91SAM9261 datasheet revision D. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_RTT_H +#define AT91_RTT_H + +#define AT91_RTT_MR (AT91_RTT + 0x00) /* Real-time Mode Register */ +#define AT91_RTT_RTPRES (0xffff << 0) /* Real-time Timer Prescaler Value */ +#define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */ +#define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */ +#define AT91_RTT_RTTRST (1 << 18) /* Real Time Timer Restart */ + +#define AT91_RTT_AR (AT91_RTT + 0x04) /* Real-time Alarm Register */ +#define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */ + +#define AT91_RTT_VR (AT91_RTT + 0x08) /* Real-time Value Register */ +#define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */ + +#define AT91_RTT_SR (AT91_RTT + 0x0c) /* Real-time Status Register */ +#define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */ +#define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */ + +#endif diff --git a/include/asm-arm/arch-at91/at91_shdwc.h b/include/asm-arm/arch-at91/at91_shdwc.h new file mode 100644 index 000000000000..795fcc266228 --- /dev/null +++ b/include/asm-arm/arch-at91/at91_shdwc.h @@ -0,0 +1,33 @@ +/* + * include/asm-arm/arch-at91/at91_shdwc.h + * + * Shutdown Controller (SHDWC) - System peripherals regsters. + * Based on AT91SAM9261 datasheet revision D. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_SHDWC_H +#define AT91_SHDWC_H + +#define AT91_SHDW_CR (AT91_SHDWC + 0x00) /* Shut Down Control Register */ +#define AT91_SHDW_SHDW (1 << 0) /* Processor Reset */ +#define AT91_SHDW_KEY (0xff << 24) /* KEY Password */ + +#define AT91_SHDW_MR (AT91_SHDWC + 0x04) /* Shut Down Mode Register */ +#define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */ +#define AT91_SHDW_WKMODE0_NONE 0 +#define AT91_SHDW_WKMODE0_HIGH 1 +#define AT91_SHDW_WKMODE0_LOW 2 +#define AT91_SHDW_WKMODE0_ANYLEVEL 3 +#define AT91_SHDW_CPTWK0 (0xf << 4) /* Counter On Wake Up 0 */ +#define AT91_SHDW_RTTWKEN (1 << 16) /* Real Time Timer Wake-up Enable */ + +#define AT91_SHDW_SR (AT91_SHDWC + 0x08) /* Shut Down Status Register */ +#define AT91_SHDW_WAKEUP0 (1 << 0) /* Wake-up 0 Status */ +#define AT91_SHDW_RTTWK (1 << 16) /* Real-time Timer Wake-up */ + +#endif diff --git a/include/asm-arm/arch-at91/at91_spi.h b/include/asm-arm/arch-at91/at91_spi.h new file mode 100644 index 000000000000..f9b9a8464997 --- /dev/null +++ b/include/asm-arm/arch-at91/at91_spi.h @@ -0,0 +1,81 @@ +/* + * include/asm-arm/arch-at91/at91_spi.h + * + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) SAN People + * + * Serial Peripheral Interface (SPI) registers. + * Based on AT91RM9200 datasheet revision E. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_SPI_H +#define AT91_SPI_H + +#define AT91_SPI_CR 0x00 /* Control Register */ +#define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */ +#define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */ +#define AT91_SPI_SWRST (1 << 7) /* SPI Software Reset */ +#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */ + +#define AT91_SPI_MR 0x04 /* Mode Register */ +#define AT91_SPI_MSTR (1 << 0) /* Master/Slave Mode */ +#define AT91_SPI_PS (1 << 1) /* Peripheral Select */ +#define AT91_SPI_PS_FIXED (0 << 1) +#define AT91_SPI_PS_VARIABLE (1 << 1) +#define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */ +#define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */ +#define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */ +#define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */ +#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ +#define AT91_SPI_DLYBCS (0xff << 24) /* Delay Between Chip Selects */ + +#define AT91_SPI_RDR 0x08 /* Receive Data Register */ +#define AT91_SPI_RD (0xffff << 0) /* Receive Data */ +#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ + +#define AT91_SPI_TDR 0x0c /* Transmit Data Register */ +#define AT91_SPI_TD (0xffff << 0) /* Transmit Data */ +#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ +#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */ + +#define AT91_SPI_SR 0x10 /* Status Register */ +#define AT91_SPI_RDRF (1 << 0) /* Receive Data Register Full */ +#define AT91_SPI_TDRE (1 << 1) /* Transmit Data Register Full */ +#define AT91_SPI_MODF (1 << 2) /* Mode Fault Error */ +#define AT91_SPI_OVRES (1 << 3) /* Overrun Error Status */ +#define AT91_SPI_ENDRX (1 << 4) /* End of RX buffer */ +#define AT91_SPI_ENDTX (1 << 5) /* End of TX buffer */ +#define AT91_SPI_RXBUFF (1 << 6) /* RX Buffer Full */ +#define AT91_SPI_TXBUFE (1 << 7) /* TX Buffer Empty */ +#define AT91_SPI_NSSR (1 << 8) /* NSS Rising [SAM9261 only] */ +#define AT91_SPI_TXEMPTY (1 << 9) /* Transmission Register Empty [SAM9261 only] */ +#define AT91_SPI_SPIENS (1 << 16) /* SPI Enable Status */ + +#define AT91_SPI_IER 0x14 /* Interrupt Enable Register */ +#define AT91_SPI_IDR 0x18 /* Interrupt Disable Register */ +#define AT91_SPI_IMR 0x1c /* Interrupt Mask Register */ + +#define AT91_SPI_CSR(n) (0x30 + ((n) * 4)) /* Chip Select Registers 0-3 */ +#define AT91_SPI_CPOL (1 << 0) /* Clock Polarity */ +#define AT91_SPI_NCPHA (1 << 1) /* Clock Phase */ +#define AT91_SPI_CSAAT (1 << 3) /* Chip Select Active After Transfer [SAM9261 only] */ +#define AT91_SPI_BITS (0xf << 4) /* Bits Per Transfer */ +#define AT91_SPI_BITS_8 (0 << 4) +#define AT91_SPI_BITS_9 (1 << 4) +#define AT91_SPI_BITS_10 (2 << 4) +#define AT91_SPI_BITS_11 (3 << 4) +#define AT91_SPI_BITS_12 (4 << 4) +#define AT91_SPI_BITS_13 (5 << 4) +#define AT91_SPI_BITS_14 (6 << 4) +#define AT91_SPI_BITS_15 (7 << 4) +#define AT91_SPI_BITS_16 (8 << 4) +#define AT91_SPI_SCBR (0xff << 8) /* Serial Clock Baud Rate */ +#define AT91_SPI_DLYBS (0xff << 16) /* Delay before SPCK */ +#define AT91_SPI_DLYBCT (0xff << 24) /* Delay between Consecutive Transfers */ + +#endif diff --git a/include/asm-arm/arch-at91/at91_ssc.h b/include/asm-arm/arch-at91/at91_ssc.h new file mode 100644 index 000000000000..0ecc73460b50 --- /dev/null +++ b/include/asm-arm/arch-at91/at91_ssc.h @@ -0,0 +1,106 @@ +/* + * include/asm-arm/arch-at91/at91_ssc.h + * + * Copyright (C) SAN People + * + * Serial Synchronous Controller (SSC) registers. + * Based on AT91RM9200 datasheet revision E. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_SSC_H +#define AT91_SSC_H + +#define AT91_SSC_CR 0x00 /* Control Register */ +#define AT91_SSC_RXEN (1 << 0) /* Receive Enable */ +#define AT91_SSC_RXDIS (1 << 1) /* Receive Disable */ +#define AT91_SSC_TXEN (1 << 8) /* Transmit Enable */ +#define AT91_SSC_TXDIS (1 << 9) /* Transmit Disable */ +#define AT91_SSC_SWRST (1 << 15) /* Software Reset */ + +#define AT91_SSC_CMR 0x04 /* Clock Mode Register */ +#define AT91_SSC_CMR_DIV (0xfff << 0) /* Clock Divider */ + +#define AT91_SSC_RCMR 0x10 /* Receive Clock Mode Register */ +#define AT91_SSC_CKS (3 << 0) /* Clock Selection */ +#define AT91_SSC_CKS_DIV (0 << 0) +#define AT91_SSC_CKS_CLOCK (1 << 0) +#define AT91_SSC_CKS_PIN (2 << 0) +#define AT91_SSC_CKO (7 << 2) /* Clock Output Mode Selection */ +#define AT91_SSC_CKO_NONE (0 << 2) +#define AT91_SSC_CKO_CONTINUOUS (1 << 2) +#define AT91_SSC_CKI (1 << 5) /* Clock Inversion */ +#define AT91_SSC_CKI_FALLING (0 << 5) +#define AT91_SSC_CK_RISING (1 << 5) +#define AT91_SSC_CKG (1 << 6) /* Receive Clock Gating Selection [AT91SAM9261 only] */ +#define AT91_SSC_CKG_NONE (0 << 6) +#define AT91_SSC_CKG_RFLOW (1 << 6) +#define AT91_SSC_CKG_RFHIGH (2 << 6) +#define AT91_SSC_START (0xf << 8) /* Start Selection */ +#define AT91_SSC_START_CONTINUOUS (0 << 8) +#define AT91_SSC_START_TX_RX (1 << 8) +#define AT91_SSC_START_LOW_RF (2 << 8) +#define AT91_SSC_START_HIGH_RF (3 << 8) +#define AT91_SSC_START_FALLING_RF (4 << 8) +#define AT91_SSC_START_RISING_RF (5 << 8) +#define AT91_SSC_START_LEVEL_RF (6 << 8) +#define AT91_SSC_START_EDGE_RF (7 << 8) +#define AT91_SSC_STOP (1 << 12) /* Receive Stop Selection [AT91SAM9261 only] */ +#define AT91_SSC_STTDLY (0xff << 16) /* Start Delay */ +#define AT91_SSC_PERIOD (0xff << 24) /* Period Divider Selection */ + +#define AT91_SSC_RFMR 0x14 /* Receive Frame Mode Register */ +#define AT91_SSC_DATALEN (0x1f << 0) /* Data Length */ +#define AT91_SSC_LOOP (1 << 5) /* Loop Mode */ +#define AT91_SSC_MSBF (1 << 7) /* Most Significant Bit First */ +#define AT91_SSC_DATNB (0xf << 8) /* Data Number per Frame */ +#define AT91_SSC_FSLEN (0xf << 16) /* Frame Sync Length */ +#define AT91_SSC_FSOS (7 << 20) /* Frame Sync Output Selection */ +#define AT91_SSC_FSOS_NONE (0 << 20) +#define AT91_SSC_FSOS_NEGATIVE (1 << 20) +#define AT91_SSC_FSOS_POSITIVE (2 << 20) +#define AT91_SSC_FSOS_LOW (3 << 20) +#define AT91_SSC_FSOS_HIGH (4 << 20) +#define AT91_SSC_FSOS_TOGGLE (5 << 20) +#define AT91_SSC_FSEDGE (1 << 24) /* Frame Sync Edge Detection */ +#define AT91_SSC_FSEDGE_POSITIVE (0 << 24) +#define AT91_SSC_FSEDGE_NEGATIVE (1 << 24) + +#define AT91_SSC_TCMR 0x18 /* Transmit Clock Mode Register */ +#define AT91_SSC_TFMR 0x1c /* Transmit Fram Mode Register */ +#define AT91_SSC_DATDEF (1 << 5) /* Data Default Value */ +#define AT91_SSC_FSDEN (1 << 23) /* Frame Sync Data Enable */ + +#define AT91_SSC_RHR 0x20 /* Receive Holding Register */ +#define AT91_SSC_THR 0x24 /* Transmit Holding Register */ +#define AT91_SSC_RSHR 0x30 /* Receive Sync Holding Register */ +#define AT91_SSC_TSHR 0x34 /* Transmit Sync Holding Register */ + +#define AT91_SSC_RC0R 0x38 /* Receive Compare 0 Register [AT91SAM9261 only] */ +#define AT91_SSC_RC1R 0x3c /* Receive Compare 1 Register [AT91SAM9261 only] */ + +#define AT91_SSC_SR 0x40 /* Status Register */ +#define AT91_SSC_TXRDY (1 << 0) /* Transmit Ready */ +#define AT91_SSC_TXEMPTY (1 << 1) /* Transmit Empty */ +#define AT91_SSC_ENDTX (1 << 2) /* End of Transmission */ +#define AT91_SSC_TXBUFE (1 << 3) /* Transmit Buffer Empty */ +#define AT91_SSC_RXRDY (1 << 4) /* Receive Ready */ +#define AT91_SSC_OVRUN (1 << 5) /* Receive Overrun */ +#define AT91_SSC_ENDRX (1 << 6) /* End of Reception */ +#define AT91_SSC_RXBUFF (1 << 7) /* Receive Buffer Full */ +#define AT91_SSC_CP0 (1 << 8) /* Compare 0 [AT91SAM9261 only] */ +#define AT91_SSC_CP1 (1 << 9) /* Compare 1 [AT91SAM9261 only] */ +#define AT91_SSC_TXSYN (1 << 10) /* Transmit Sync */ +#define AT91_SSC_RXSYN (1 << 11) /* Receive Sync */ +#define AT91_SSC_TXENA (1 << 16) /* Transmit Enable */ +#define AT91_SSC_RXENA (1 << 17) /* Receive Enable */ + +#define AT91_SSC_IER 0x44 /* Interrupt Enable Register */ +#define AT91_SSC_IDR 0x48 /* Interrupt Disable Register */ +#define AT91_SSC_IMR 0x4c /* Interrupt Mask Register */ + +#endif diff --git a/include/asm-arm/arch-at91/at91_st.h b/include/asm-arm/arch-at91/at91_st.h new file mode 100644 index 000000000000..30446e2ea772 --- /dev/null +++ b/include/asm-arm/arch-at91/at91_st.h @@ -0,0 +1,49 @@ +/* + * include/asm-arm/arch-at91/at91_st.h + * + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) SAN People + * + * System Timer (ST) - System peripherals registers. + * Based on AT91RM9200 datasheet revision E. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_ST_H +#define AT91_ST_H + +#define AT91_ST_CR (AT91_ST + 0x00) /* Control Register */ +#define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */ + +#define AT91_ST_PIMR (AT91_ST + 0x04) /* Period Interval Mode Register */ +#define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */ + +#define AT91_ST_WDMR (AT91_ST + 0x08) /* Watchdog Mode Register */ +#define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */ +#define AT91_ST_RSTEN (1 << 16) /* Reset Enable */ +#define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */ + +#define AT91_ST_RTMR (AT91_ST + 0x0c) /* Real-time Mode Register */ +#define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */ + +#define AT91_ST_SR (AT91_ST + 0x10) /* Status Register */ +#define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */ +#define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */ +#define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */ +#define AT91_ST_ALMS (1 << 3) /* Alarm Status */ + +#define AT91_ST_IER (AT91_ST + 0x14) /* Interrupt Enable Register */ +#define AT91_ST_IDR (AT91_ST + 0x18) /* Interrupt Disable Register */ +#define AT91_ST_IMR (AT91_ST + 0x1c) /* Interrupt Mask Register */ + +#define AT91_ST_RTAR (AT91_ST + 0x20) /* Real-time Alarm Register */ +#define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */ + +#define AT91_ST_CRTR (AT91_ST + 0x24) /* Current Real-time Register */ +#define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */ + +#endif diff --git a/include/asm-arm/arch-at91/at91_tc.h b/include/asm-arm/arch-at91/at91_tc.h new file mode 100644 index 000000000000..b85d3faeef5c --- /dev/null +++ b/include/asm-arm/arch-at91/at91_tc.h @@ -0,0 +1,146 @@ +/* + * include/asm-arm/arch-at91/at91_tc.h + * + * Copyright (C) SAN People + * + * Timer/Counter Unit (TC) registers. + * Based on AT91RM9200 datasheet revision E. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_TC_H +#define AT91_TC_H + +#define AT91_TC_BCR 0xc0 /* TC Block Control Register */ +#define AT91_TC_SYNC (1 << 0) /* Synchro Command */ + +#define AT91_TC_BMR 0xc4 /* TC Block Mode Register */ +#define AT91_TC_TC0XC0S (3 << 0) /* External Clock Signal 0 Selection */ +#define AT91_TC_TC0XC0S_TCLK0 (0 << 0) +#define AT91_TC_TC0XC0S_NONE (1 << 0) +#define AT91_TC_TC0XC0S_TIOA1 (2 << 0) +#define AT91_TC_TC0XC0S_TIOA2 (3 << 0) +#define AT91_TC_TC1XC1S (3 << 2) /* External Clock Signal 1 Selection */ +#define AT91_TC_TC1XC1S_TCLK1 (0 << 2) +#define AT91_TC_TC1XC1S_NONE (1 << 2) +#define AT91_TC_TC1XC1S_TIOA0 (2 << 2) +#define AT91_TC_TC1XC1S_TIOA2 (3 << 2) +#define AT91_TC_TC2XC2S (3 << 4) /* External Clock Signal 2 Selection */ +#define AT91_TC_TC2XC2S_TCLK2 (0 << 4) +#define AT91_TC_TC2XC2S_NONE (1 << 4) +#define AT91_TC_TC2XC2S_TIOA0 (2 << 4) +#define AT91_TC_TC2XC2S_TIOA1 (3 << 4) + + +#define AT91_TC_CCR 0x00 /* Channel Control Register */ +#define AT91_TC_CLKEN (1 << 0) /* Counter Clock Enable Command */ +#define AT91_TC_CLKDIS (1 << 1) /* Counter CLock Disable Command */ +#define AT91_TC_SWTRG (1 << 2) /* Software Trigger Command */ + +#define AT91_TC_CMR 0x04 /* Channel Mode Register */ +#define AT91_TC_TCCLKS (7 << 0) /* Capture/Waveform Mode: Clock Selection */ +#define AT91_TC_TIMER_CLOCK1 (0 << 0) +#define AT91_TC_TIMER_CLOCK2 (1 << 0) +#define AT91_TC_TIMER_CLOCK3 (2 << 0) +#define AT91_TC_TIMER_CLOCK4 (3 << 0) +#define AT91_TC_TIMER_CLOCK5 (4 << 0) +#define AT91_TC_XC0 (5 << 0) +#define AT91_TC_XC1 (6 << 0) +#define AT91_TC_XC2 (7 << 0) +#define AT91_TC_CLKI (1 << 3) /* Capture/Waveform Mode: Clock Invert */ +#define AT91_TC_BURST (3 << 4) /* Capture/Waveform Mode: Burst Signal Selection */ +#define AT91_TC_LDBSTOP (1 << 6) /* Capture Mode: Counter Clock Stopped with TB Loading */ +#define AT91_TC_LDBDIS (1 << 7) /* Capture Mode: Counter Clock Disable with RB Loading */ +#define AT91_TC_ETRGEDG (3 << 8) /* Capture Mode: External Trigger Edge Selection */ +#define AT91_TC_ABETRG (1 << 10) /* Capture Mode: TIOA or TIOB External Trigger Selection */ +#define AT91_TC_CPCTRG (1 << 14) /* Capture Mode: RC Compare Trigger Enable */ +#define AT91_TC_WAVE (1 << 15) /* Capture/Waveform mode */ +#define AT91_TC_LDRA (3 << 16) /* Capture Mode: RA Loading Selection */ +#define AT91_TC_LDRB (3 << 18) /* Capture Mode: RB Loading Selection */ + +#define AT91_TC_CPCSTOP (1 << 6) /* Waveform Mode: Counter Clock Stopped with RC Compare */ +#define AT91_TC_CPCDIS (1 << 7) /* Waveform Mode: Counter Clock Disable with RC Compare */ +#define AT91_TC_EEVTEDG (3 << 8) /* Waveform Mode: External Event Edge Selection */ +#define AT91_TC_EEVTEDG_NONE (0 << 8) +#define AT91_TC_EEVTEDG_RISING (1 << 8) +#define AT91_TC_EEVTEDG_FALLING (2 << 8) +#define AT91_TC_EEVTEDG_BOTH (3 << 8) +#define AT91_TC_EEVT (3 << 10) /* Waveform Mode: External Event Selection */ +#define AT91_TC_EEVT_TIOB (0 << 10) +#define AT91_TC_EEVT_XC0 (1 << 10) +#define AT91_TC_EEVT_XC1 (2 << 10) +#define AT91_TC_EEVT_XC2 (3 << 10) +#define AT91_TC_ENETRG (1 << 12) /* Waveform Mode: External Event Trigger Enable */ +#define AT91_TC_WAVESEL (3 << 13) /* Waveform Mode: Waveform Selection */ +#define AT91_TC_WAVESEL_UP (0 << 13) +#define AT91_TC_WAVESEL_UP_AUTO (2 << 13) +#define AT91_TC_WAVESEL_UPDOWN (1 << 13) +#define AT91_TC_WAVESEL_UPDOWN_AUTO (3 << 13) +#define AT91_TC_ACPA (3 << 16) /* Waveform Mode: RA Compare Effect on TIOA */ +#define AT91_TC_ACPA_NONE (0 << 16) +#define AT91_TC_ACPA_SET (1 << 16) +#define AT91_TC_ACPA_CLEAR (2 << 16) +#define AT91_TC_ACPA_TOGGLE (3 << 16) +#define AT91_TC_ACPC (3 << 18) /* Waveform Mode: RC Compre Effect on TIOA */ +#define AT91_TC_ACPC_NONE (0 << 18) +#define AT91_TC_ACPC_SET (1 << 18) +#define AT91_TC_ACPC_CLEAR (2 << 18) +#define AT91_TC_ACPC_TOGGLE (3 << 18) +#define AT91_TC_AEEVT (3 << 20) /* Waveform Mode: External Event Effect on TIOA */ +#define AT91_TC_AEEVT_NONE (0 << 20) +#define AT91_TC_AEEVT_SET (1 << 20) +#define AT91_TC_AEEVT_CLEAR (2 << 20) +#define AT91_TC_AEEVT_TOGGLE (3 << 20) +#define AT91_TC_ASWTRG (3 << 22) /* Waveform Mode: Software Trigger Effect on TIOA */ +#define AT91_TC_ASWTRG_NONE (0 << 22) +#define AT91_TC_ASWTRG_SET (1 << 22) +#define AT91_TC_ASWTRG_CLEAR (2 << 22) +#define AT91_TC_ASWTRG_TOGGLE (3 << 22) +#define AT91_TC_BCPB (3 << 24) /* Waveform Mode: RB Compare Effect on TIOB */ +#define AT91_TC_BCPB_NONE (0 << 24) +#define AT91_TC_BCPB_SET (1 << 24) +#define AT91_TC_BCPB_CLEAR (2 << 24) +#define AT91_TC_BCPB_TOGGLE (3 << 24) +#define AT91_TC_BCPC (3 << 26) /* Waveform Mode: RC Compare Effect on TIOB */ +#define AT91_TC_BCPC_NONE (0 << 26) +#define AT91_TC_BCPC_SET (1 << 26) +#define AT91_TC_BCPC_CLEAR (2 << 26) +#define AT91_TC_BCPC_TOGGLE (3 << 26) +#define AT91_TC_BEEVT (3 << 28) /* Waveform Mode: External Event Effect on TIOB */ +#define AT91_TC_BEEVT_NONE (0 << 28) +#define AT91_TC_BEEVT_SET (1 << 28) +#define AT91_TC_BEEVT_CLEAR (2 << 28) +#define AT91_TC_BEEVT_TOGGLE (3 << 28) +#define AT91_TC_BSWTRG (3 << 30) /* Waveform Mode: Software Trigger Effect on TIOB */ +#define AT91_TC_BSWTRG_NONE (0 << 30) +#define AT91_TC_BSWTRG_SET (1 << 30) +#define AT91_TC_BSWTRG_CLEAR (2 << 30) +#define AT91_TC_BSWTRG_TOGGLE (3 << 30) + +#define AT91_TC_CV 0x10 /* Counter Value */ +#define AT91_TC_RA 0x14 /* Register A */ +#define AT91_TC_RB 0x18 /* Register B */ +#define AT91_TC_RC 0x1c /* Register C */ + +#define AT91_TC_SR 0x20 /* Status Register */ +#define AT91_TC_COVFS (1 << 0) /* Counter Overflow Status */ +#define AT91_TC_LOVRS (1 << 1) /* Load Overrun Status */ +#define AT91_TC_CPAS (1 << 2) /* RA Compare Status */ +#define AT91_TC_CPBS (1 << 3) /* RB Compare Status */ +#define AT91_TC_CPCS (1 << 4) /* RC Compare Status */ +#define AT91_TC_LDRAS (1 << 5) /* RA Loading Status */ +#define AT91_TC_LDRBS (1 << 6) /* RB Loading Status */ +#define AT91_TC_ETRGS (1 << 7) /* External Trigger Status */ +#define AT91_TC_CLKSTA (1 << 16) /* Clock Enabling Status */ +#define AT91_TC_MTIOA (1 << 17) /* TIOA Mirror */ +#define AT91_TC_MTIOB (1 << 18) /* TIOB Mirror */ + +#define AT91_TC_IER 0x24 /* Interrupt Enable Register */ +#define AT91_TC_IDR 0x28 /* Interrupt Disable Register */ +#define AT91_TC_IMR 0x2c /* Interrupt Mask Register */ + +#endif diff --git a/include/asm-arm/arch-at91/at91_twi.h b/include/asm-arm/arch-at91/at91_twi.h new file mode 100644 index 000000000000..ca9a90733456 --- /dev/null +++ b/include/asm-arm/arch-at91/at91_twi.h @@ -0,0 +1,57 @@ +/* + * include/asm-arm/arch-at91/at91_twi.h + * + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) SAN People + * + * Two-wire Interface (TWI) registers. + * Based on AT91RM9200 datasheet revision E. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_TWI_H +#define AT91_TWI_H + +#define AT91_TWI_CR 0x00 /* Control Register */ +#define AT91_TWI_START (1 << 0) /* Send a Start Condition */ +#define AT91_TWI_STOP (1 << 1) /* Send a Stop Condition */ +#define AT91_TWI_MSEN (1 << 2) /* Master Transfer Enable */ +#define AT91_TWI_MSDIS (1 << 3) /* Master Transfer Disable */ +#define AT91_TWI_SWRST (1 << 7) /* Software Reset */ + +#define AT91_TWI_MMR 0x04 /* Master Mode Register */ +#define AT91_TWI_IADRSZ (3 << 8) /* Internal Device Address Size */ +#define AT91_TWI_IADRSZ_NO (0 << 8) +#define AT91_TWI_IADRSZ_1 (1 << 8) +#define AT91_TWI_IADRSZ_2 (2 << 8) +#define AT91_TWI_IADRSZ_3 (3 << 8) +#define AT91_TWI_MREAD (1 << 12) /* Master Read Direction */ +#define AT91_TWI_DADR (0x7f << 16) /* Device Address */ + +#define AT91_TWI_IADR 0x0c /* Internal Address Register */ + +#define AT91_TWI_CWGR 0x10 /* Clock Waveform Generator Register */ +#define AT91_TWI_CLDIV (0xff << 0) /* Clock Low Divisor */ +#define AT91_TWI_CHDIV (0xff << 8) /* Clock High Divisor */ +#define AT91_TWI_CKDIV (7 << 16) /* Clock Divider */ + +#define AT91_TWI_SR 0x20 /* Status Register */ +#define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */ +#define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */ +#define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */ +#define AT91_TWI_OVRE (1 << 6) /* Overrun Error [AT91RM9200 only] */ +#define AT91_TWI_UNRE (1 << 7) /* Underrun Error [AT91RM9200 only] */ +#define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */ + +#define AT91_TWI_IER 0x24 /* Interrupt Enable Register */ +#define AT91_TWI_IDR 0x28 /* Interrupt Disable Register */ +#define AT91_TWI_IMR 0x2c /* Interrupt Mask Register */ +#define AT91_TWI_RHR 0x30 /* Receive Holding Register */ +#define AT91_TWI_THR 0x34 /* Transmit Holding Register */ + +#endif + diff --git a/include/asm-arm/arch-at91/at91_wdt.h b/include/asm-arm/arch-at91/at91_wdt.h new file mode 100644 index 000000000000..7251a344c740 --- /dev/null +++ b/include/asm-arm/arch-at91/at91_wdt.h @@ -0,0 +1,34 @@ +/* + * include/asm-arm/arch-at91/at91_wdt.h + * + * Watchdog Timer (WDT) - System peripherals regsters. + * Based on AT91SAM9261 datasheet revision D. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_WDT_H +#define AT91_WDT_H + +#define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */ +#define AT91_WDT_WDRSTT (1 << 0) /* Restart */ +#define AT91_WDT_KEY (0xff << 24) /* KEY Password */ + +#define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */ +#define AT91_WDT_WDV (0xfff << 0) /* Counter Value */ +#define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */ +#define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */ +#define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */ +#define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */ +#define AT91_WDT_WDD (0xfff << 16) /* Delta Value */ +#define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */ +#define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */ + +#define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */ +#define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */ +#define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */ + +#endif diff --git a/include/asm-arm/arch-at91/at91rm9200.h b/include/asm-arm/arch-at91/at91rm9200.h new file mode 100644 index 000000000000..a12ac8ab2ad0 --- /dev/null +++ b/include/asm-arm/arch-at91/at91rm9200.h @@ -0,0 +1,291 @@ +/* + * include/asm-arm/arch-at91/at91rm9200.h + * + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) SAN People + * + * Common definitions. + * Based on AT91RM9200 datasheet revision E. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91RM9200_H +#define AT91RM9200_H + +/* + * Peripheral identifiers/interrupts. + */ +#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define AT91_ID_SYS 1 /* System Peripheral */ +#define AT91RM9200_ID_PIOA 2 /* Parallel IO Controller A */ +#define AT91RM9200_ID_PIOB 3 /* Parallel IO Controller B */ +#define AT91RM9200_ID_PIOC 4 /* Parallel IO Controller C */ +#define AT91RM9200_ID_PIOD 5 /* Parallel IO Controller D */ +#define AT91RM9200_ID_US0 6 /* USART 0 */ +#define AT91RM9200_ID_US1 7 /* USART 1 */ +#define AT91RM9200_ID_US2 8 /* USART 2 */ +#define AT91RM9200_ID_US3 9 /* USART 3 */ +#define AT91RM9200_ID_MCI 10 /* Multimedia Card Interface */ +#define AT91RM9200_ID_UDP 11 /* USB Device Port */ +#define AT91RM9200_ID_TWI 12 /* Two-Wire Interface */ +#define AT91RM9200_ID_SPI 13 /* Serial Peripheral Interface */ +#define AT91RM9200_ID_SSC0 14 /* Serial Synchronous Controller 0 */ +#define AT91RM9200_ID_SSC1 15 /* Serial Synchronous Controller 1 */ +#define AT91RM9200_ID_SSC2 16 /* Serial Synchronous Controller 2 */ +#define AT91RM9200_ID_TC0 17 /* Timer Counter 0 */ +#define AT91RM9200_ID_TC1 18 /* Timer Counter 1 */ +#define AT91RM9200_ID_TC2 19 /* Timer Counter 2 */ +#define AT91RM9200_ID_TC3 20 /* Timer Counter 3 */ +#define AT91RM9200_ID_TC4 21 /* Timer Counter 4 */ +#define AT91RM9200_ID_TC5 22 /* Timer Counter 5 */ +#define AT91RM9200_ID_UHP 23 /* USB Host port */ +#define AT91RM9200_ID_EMAC 24 /* Ethernet MAC */ +#define AT91RM9200_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */ +#define AT91RM9200_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */ +#define AT91RM9200_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */ +#define AT91RM9200_ID_IRQ3 28 /* Advanced Interrupt Controller (IRQ3) */ +#define AT91RM9200_ID_IRQ4 29 /* Advanced Interrupt Controller (IRQ4) */ +#define AT91RM9200_ID_IRQ5 30 /* Advanced Interrupt Controller (IRQ5) */ +#define AT91RM9200_ID_IRQ6 31 /* Advanced Interrupt Controller (IRQ6) */ + + +/* + * Peripheral physical base addresses. + */ +#define AT91RM9200_BASE_TCB0 0xfffa0000 +#define AT91RM9200_BASE_TC0 0xfffa0000 +#define AT91RM9200_BASE_TC1 0xfffa0040 +#define AT91RM9200_BASE_TC2 0xfffa0080 +#define AT91RM9200_BASE_TCB1 0xfffa4000 +#define AT91RM9200_BASE_TC3 0xfffa4000 +#define AT91RM9200_BASE_TC4 0xfffa4040 +#define AT91RM9200_BASE_TC5 0xfffa4080 +#define AT91RM9200_BASE_UDP 0xfffb0000 +#define AT91RM9200_BASE_MCI 0xfffb4000 +#define AT91RM9200_BASE_TWI 0xfffb8000 +#define AT91RM9200_BASE_EMAC 0xfffbc000 +#define AT91RM9200_BASE_US0 0xfffc0000 +#define AT91RM9200_BASE_US1 0xfffc4000 +#define AT91RM9200_BASE_US2 0xfffc8000 +#define AT91RM9200_BASE_US3 0xfffcc000 +#define AT91RM9200_BASE_SSC0 0xfffd0000 +#define AT91RM9200_BASE_SSC1 0xfffd4000 +#define AT91RM9200_BASE_SSC2 0xfffd8000 +#define AT91RM9200_BASE_SPI 0xfffe0000 +#define AT91_BASE_SYS 0xfffff000 + + +/* + * System Peripherals (offset from AT91_BASE_SYS) + */ +#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */ +#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) /* Debug Unit */ +#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) /* PIO Controller A */ +#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) /* PIO Controller B */ +#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) /* PIO Controller C */ +#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) /* PIO Controller D */ +#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */ +#define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */ +#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */ +#define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */ + +#define AT91_MATRIX 0 /* not supported */ + +/* + * Internal Memory. + */ +#define AT91RM9200_ROM_BASE 0x00100000 /* Internal ROM base address */ +#define AT91RM9200_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ + +#define AT91RM9200_SRAM_BASE 0x00200000 /* Internal SRAM base address */ +#define AT91RM9200_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */ + +#define AT91RM9200_UHP_BASE 0x00300000 /* USB Host controller */ + + +#if 0 +/* + * PIO pin definitions (peripheral A/B multiplexing). + */ +#define AT91_PA0_MISO (1 << 0) /* A: SPI Master-In Slave-Out */ +#define AT91_PA0_PCK3 (1 << 0) /* B: PMC Programmable Clock Output 3 */ +#define AT91_PA1_MOSI (1 << 1) /* A: SPI Master-Out Slave-In */ +#define AT91_PA1_PCK0 (1 << 1) /* B: PMC Programmable Clock Output 0 */ +#define AT91_PA2_SPCK (1 << 2) /* A: SPI Serial Clock */ +#define AT91_PA2_IRQ4 (1 << 2) /* B: External Interrupt 4 */ +#define AT91_PA3_NPCS0 (1 << 3) /* A: SPI Peripheral Chip Select 0 */ +#define AT91_PA3_IRQ5 (1 << 3) /* B: External Interrupt 5 */ +#define AT91_PA4_NPCS1 (1 << 4) /* A: SPI Peripheral Chip Select 1 */ +#define AT91_PA4_PCK1 (1 << 4) /* B: PMC Programmable Clock Output 1 */ +#define AT91_PA5_NPCS2 (1 << 5) /* A: SPI Peripheral Chip Select 2 */ +#define AT91_PA5_TXD3 (1 << 5) /* B: USART Transmit Data 3 */ +#define AT91_PA6_NPCS3 (1 << 6) /* A: SPI Peripheral Chip Select 3 */ +#define AT91_PA6_RXD3 (1 << 6) /* B: USART Receive Data 3 */ +#define AT91_PA7_ETXCK_EREFCK (1 << 7) /* A: Ethernet Reference Clock / Transmit Clock */ +#define AT91_PA7_PCK2 (1 << 7) /* B: PMC Programmable Clock Output 2 */ +#define AT91_PA8_ETXEN (1 << 8) /* A: Ethernet Transmit Enable */ +#define AT91_PA8_MCCDB (1 << 8) /* B: MMC Multimedia Card B Command */ +#define AT91_PA9_ETX0 (1 << 9) /* A: Ethernet Transmit Data 0 */ +#define AT91_PA9_MCDB0 (1 << 9) /* B: MMC Multimedia Card B Data 0 */ +#define AT91_PA10_ETX1 (1 << 10) /* A: Ethernet Transmit Data 1 */ +#define AT91_PA10_MCDB1 (1 << 10) /* B: MMC Multimedia Card B Data 1 */ +#define AT91_PA11_ECRS_ECRSDV (1 << 11) /* A: Ethernet Carrier Sense / Data Valid */ +#define AT91_PA11_MCDB2 (1 << 11) /* B: MMC Multimedia Card B Data 2 */ +#define AT91_PA12_ERX0 (1 << 12) /* A: Ethernet Receive Data 0 */ +#define AT91_PA12_MCDB3 (1 << 12) /* B: MMC Multimedia Card B Data 3 */ +#define AT91_PA13_ERX1 (1 << 13) /* A: Ethernet Receive Data 1 */ +#define AT91_PA13_TCLK0 (1 << 13) /* B: TC External Clock Input 0 */ +#define AT91_PA14_ERXER (1 << 14) /* A: Ethernet Receive Error */ +#define AT91_PA14_TCLK1 (1 << 14) /* B: TC External Clock Input 1 */ +#define AT91_PA15_EMDC (1 << 15) /* A: Ethernet Management Data Clock */ +#define AT91_PA15_TCLK2 (1 << 15) /* B: TC External Clock Input 2 */ +#define AT91_PA16_EMDIO (1 << 16) /* A: Ethernet Management Data I/O */ +#define AT91_PA16_IRQ6 (1 << 16) /* B: External Interrupt 6 */ +#define AT91_PA17_TXD0 (1 << 17) /* A: USART Transmit Data 0 */ +#define AT91_PA17_TIOA0 (1 << 17) /* B: TC I/O Line A 0 */ +#define AT91_PA18_RXD0 (1 << 18) /* A: USART Receive Data 0 */ +#define AT91_PA18_TIOB0 (1 << 18) /* B: TC I/O Line B 0 */ +#define AT91_PA19_SCK0 (1 << 19) /* A: USART Serial Clock 0 */ +#define AT91_PA19_TIOA1 (1 << 19) /* B: TC I/O Line A 1 */ +#define AT91_PA20_CTS0 (1 << 20) /* A: USART Clear To Send 0 */ +#define AT91_PA20_TIOB1 (1 << 20) /* B: TC I/O Line B 1 */ +#define AT91_PA21_RTS0 (1 << 21) /* A: USART Ready To Send 0 */ +#define AT91_PA21_TIOA2 (1 << 21) /* B: TC I/O Line A 2 */ +#define AT91_PA22_RXD2 (1 << 22) /* A: USART Receive Data 2 */ +#define AT91_PA22_TIOB2 (1 << 22) /* B: TC I/O Line B 2 */ +#define AT91_PA23_TXD2 (1 << 23) /* A: USART Transmit Data 2 */ +#define AT91_PA23_IRQ3 (1 << 23) /* B: External Interrupt 3 */ +#define AT91_PA24_SCK2 (1 << 24) /* A: USART Serial Clock 2 */ +#define AT91_PA24_PCK1 (1 << 24) /* B: PMC Programmable Clock Output 1 */ +#define AT91_PA25_TWD (1 << 25) /* A: TWI Two-wire Serial Data */ +#define AT91_PA25_IRQ2 (1 << 25) /* B: External Interrupt 2 */ +#define AT91_PA26_TWCK (1 << 26) /* A: TWI Two-wire Serial Clock */ +#define AT91_PA26_IRQ1 (1 << 26) /* B: External Interrupt 1 */ +#define AT91_PA27_MCCK (1 << 27) /* A: MMC Multimedia Card Clock */ +#define AT91_PA27_TCLK3 (1 << 27) /* B: TC External Clock Input 3 */ +#define AT91_PA28_MCCDA (1 << 28) /* A: MMC Multimedia Card A Command */ +#define AT91_PA28_TCLK4 (1 << 28) /* B: TC External Clock Input 4 */ +#define AT91_PA29_MCDA0 (1 << 29) /* A: MMC Multimedia Card A Data 0 */ +#define AT91_PA29_TCLK5 (1 << 29) /* B: TC External Clock Input 5 */ +#define AT91_PA30_DRXD (1 << 30) /* A: DBGU Receive Data */ +#define AT91_PA30_CTS2 (1 << 30) /* B: USART Clear To Send 2 */ +#define AT91_PA31_DTXD (1 << 31) /* A: DBGU Transmit Data */ +#define AT91_PA31_RTS2 (1 << 31) /* B: USART Ready To Send 2 */ + +#define AT91_PB0_TF0 (1 << 0) /* A: SSC Transmit Frame Sync 0 */ +#define AT91_PB0_RTS3 (1 << 0) /* B: USART Ready To Send 3 */ +#define AT91_PB1_TK0 (1 << 1) /* A: SSC Transmit Clock 0 */ +#define AT91_PB1_CTS3 (1 << 1) /* B: USART Clear To Send 3 */ +#define AT91_PB2_TD0 (1 << 2) /* A: SSC Transmit Data 0 */ +#define AT91_PB2_SCK3 (1 << 2) /* B: USART Serial Clock 3 */ +#define AT91_PB3_RD0 (1 << 3) /* A: SSC Receive Data 0 */ +#define AT91_PB3_MCDA1 (1 << 3) /* B: MMC Multimedia Card A Data 1 */ +#define AT91_PB4_RK0 (1 << 4) /* A: SSC Receive Clock 0 */ +#define AT91_PB4_MCDA2 (1 << 4) /* B: MMC Multimedia Card A Data 2 */ +#define AT91_PB5_RF0 (1 << 5) /* A: SSC Receive Frame Sync 0 */ +#define AT91_PB5_MCDA3 (1 << 5) /* B: MMC Multimedia Card A Data 3 */ +#define AT91_PB6_TF1 (1 << 6) /* A: SSC Transmit Frame Sync 1 */ +#define AT91_PB6_TIOA3 (1 << 6) /* B: TC I/O Line A 3 */ +#define AT91_PB7_TK1 (1 << 7) /* A: SSC Transmit Clock 1 */ +#define AT91_PB7_TIOB3 (1 << 7) /* B: TC I/O Line B 3 */ +#define AT91_PB8_TD1 (1 << 8) /* A: SSC Transmit Data 1 */ +#define AT91_PB8_TIOA4 (1 << 8) /* B: TC I/O Line A 4 */ +#define AT91_PB9_RD1 (1 << 9) /* A: SSC Receive Data 1 */ +#define AT91_PB9_TIOB4 (1 << 9) /* B: TC I/O Line B 4 */ +#define AT91_PB10_RK1 (1 << 10) /* A: SSC Receive Clock 1 */ +#define AT91_PB10_TIOA5 (1 << 10) /* B: TC I/O Line A 5 */ +#define AT91_PB11_RF1 (1 << 11) /* A: SSC Receive Frame Sync 1 */ +#define AT91_PB11_TIOB5 (1 << 11) /* B: TC I/O Line B 5 */ +#define AT91_PB12_TF2 (1 << 12) /* A: SSC Transmit Frame Sync 2 */ +#define AT91_PB12_ETX2 (1 << 12) /* B: Ethernet Transmit Data 2 */ +#define AT91_PB13_TK2 (1 << 13) /* A: SSC Transmit Clock 3 */ +#define AT91_PB13_ETX3 (1 << 13) /* B: Ethernet Transmit Data 3 */ +#define AT91_PB14_TD2 (1 << 14) /* A: SSC Transmit Data 2 */ +#define AT91_PB14_ETXER (1 << 14) /* B: Ethernet Transmit Coding Error */ +#define AT91_PB15_RD2 (1 << 15) /* A: SSC Receive Data 2 */ +#define AT91_PB15_ERX2 (1 << 15) /* B: Ethernet Receive Data 2 */ +#define AT91_PB16_RK2 (1 << 16) /* A: SSC Receive Clock 2 */ +#define AT91_PB16_ERX3 (1 << 16) /* B: Ethernet Receive Data 3 */ +#define AT91_PB17_RF2 (1 << 17) /* A: SSC Receive Frame Sync 2 */ +#define AT91_PB17_ERXDV (1 << 17) /* B: Ethernet Receive Data Valid */ +#define AT91_PB18_RI1 (1 << 18) /* A: USART Ring Indicator 1 */ +#define AT91_PB18_ECOL (1 << 18) /* B: Ethernet Collision Detected */ +#define AT91_PB19_DTR1 (1 << 19) /* A: USART Data Terminal Ready 1 */ +#define AT91_PB19_ERXCK (1 << 19) /* B: Ethernet Receive Clock */ +#define AT91_PB20_TXD1 (1 << 20) /* A: USART Transmit Data 1 */ +#define AT91_PB21_RXD1 (1 << 21) /* A: USART Receive Data 1 */ +#define AT91_PB22_SCK1 (1 << 22) /* A: USART Serial Clock 1 */ +#define AT91_PB23_DCD1 (1 << 23) /* A: USART Data Carrier Detect 1 */ +#define AT91_PB24_CTS1 (1 << 24) /* A: USART Clear To Send 1 */ +#define AT91_PB25_DSR1 (1 << 25) /* A: USART Data Set Ready 1 */ +#define AT91_PB25_EF100 (1 << 25) /* B: Ethernet Force 100 Mbit */ +#define AT91_PB26_RTS1 (1 << 26) /* A: USART Ready To Send 1 */ +#define AT91_PB27_PCK0 (1 << 27) /* B: PMC Programmable Clock Output 0 */ +#define AT91_PB28_FIQ (1 << 28) /* A: Fast Interrupt */ +#define AT91_PB29_IRQ0 (1 << 29) /* A: External Interrupt 0 */ + +#define AT91_PC0_BFCK (1 << 0) /* A: Burst Flash Clock */ +#define AT91_PC1_BFRDY_SMOE (1 << 1) /* A: Burst Flash Ready / SmartMedia Output Enable */ +#define AT91_PC2_BFAVD (1 << 2) /* A: Burst Flash Address Valid */ +#define AT91_PC3_BFBAA_SMWE (1 << 3) /* A: Burst Flash Address Advance / SmartMedia Write Enable */ +#define AT91_PC4_BFOE (1 << 4) /* A: Burst Flash Output Enable */ +#define AT91_PC5_BFWE (1 << 5) /* A: Burst Flash Write Enable */ +#define AT91_PC6_NWAIT (1 << 6) /* A: SMC Wait Signal */ +#define AT91_PC7_A23 (1 << 7) /* A: Address Bus 23 */ +#define AT91_PC8_A24 (1 << 8) /* A: Address Bus 24 */ +#define AT91_PC9_A25_CFRNW (1 << 9) /* A: Address Bus 25 / Compact Flash Read Not Write */ +#define AT91_PC10_NCS4_CFCS (1 << 10) /* A: SMC Chip Select 4 / Compact Flash Chip Select */ +#define AT91_PC11_NCS5_CFCE1 (1 << 11) /* A: SMC Chip Select 5 / Compact Flash Chip Enable 1 */ +#define AT91_PC12_NCS6_CFCE2 (1 << 12) /* A: SMC Chip Select 6 / Compact Flash Chip Enable 2 */ +#define AT91_PC13_NCS7 (1 << 13) /* A: Chip Select 7 */ + +#define AT91_PD0_ETX0 (1 << 0) /* A: Ethernet Transmit Data 0 */ +#define AT91_PD1_ETX1 (1 << 1) /* A: Ethernet Transmit Data 1 */ +#define AT91_PD2_ETX2 (1 << 2) /* A: Ethernet Transmit Data 2 */ +#define AT91_PD3_ETX3 (1 << 3) /* A: Ethernet Transmit Data 3 */ +#define AT91_PD4_ETXEN (1 << 4) /* A: Ethernet Transmit Enable */ +#define AT91_PD5_ETXER (1 << 5) /* A: Ethernet Transmit Coding Error */ +#define AT91_PD6_DTXD (1 << 6) /* A: DBGU Transmit Data */ +#define AT91_PD7_PCK0 (1 << 7) /* A: PMC Programmable Clock Output 0 */ +#define AT91_PD7_TSYNC (1 << 7) /* B: ETM Trace Synchronization Signal */ +#define AT91_PD8_PCK1 (1 << 8) /* A: PMC Programmable Clock Output 1 */ +#define AT91_PD8_TCLK (1 << 8) /* B: ETM Trace Clock */ +#define AT91_PD9_PCK2 (1 << 9) /* A: PMC Programmable Clock Output 2 */ +#define AT91_PD9_TPS0 (1 << 9) /* B: ETM Trace ARM Pipeline Status 0 */ +#define AT91_PD10_PCK3 (1 << 10) /* A: PMC Programmable Clock Output 3 */ +#define AT91_PD10_TPS1 (1 << 10) /* B: ETM Trace ARM Pipeline Status 1 */ +#define AT91_PD11_TPS2 (1 << 11) /* B: ETM Trace ARM Pipeline Status 2 */ +#define AT91_PD12_TPK0 (1 << 12) /* B: ETM Trace Packet Port 0 */ +#define AT91_PD13_TPK1 (1 << 13) /* B: ETM Trace Packet Port 1 */ +#define AT91_PD14_TPK2 (1 << 14) /* B: ETM Trace Packet Port 2 */ +#define AT91_PD15_TD0 (1 << 15) /* A: SSC Transmit Data 0 */ +#define AT91_PD15_TPK3 (1 << 15) /* B: ETM Trace Packet Port 3 */ +#define AT91_PD16_TD1 (1 << 16) /* A: SSC Transmit Data 1 */ +#define AT91_PD16_TPK4 (1 << 16) /* B: ETM Trace Packet Port 4 */ +#define AT91_PD17_TD2 (1 << 17) /* A: SSC Transmit Data 2 */ +#define AT91_PD17_TPK5 (1 << 17) /* B: ETM Trace Packet Port 5 */ +#define AT91_PD18_NPCS1 (1 << 18) /* A: SPI Peripheral Chip Select 1 */ +#define AT91_PD18_TPK6 (1 << 18) /* B: ETM Trace Packet Port 6 */ +#define AT91_PD19_NPCS2 (1 << 19) /* A: SPI Peripheral Chip Select 2 */ +#define AT91_PD19_TPK7 (1 << 19) /* B: ETM Trace Packet Port 7 */ +#define AT91_PD20_NPCS3 (1 << 20) /* A: SPI Peripheral Chip Select 3 */ +#define AT91_PD20_TPK8 (1 << 20) /* B: ETM Trace Packet Port 8 */ +#define AT91_PD21_RTS0 (1 << 21) /* A: USART Ready To Send 0 */ +#define AT91_PD21_TPK9 (1 << 21) /* B: ETM Trace Packet Port 9 */ +#define AT91_PD22_RTS1 (1 << 22) /* A: USART Ready To Send 1 */ +#define AT91_PD22_TPK10 (1 << 22) /* B: ETM Trace Packet Port 10 */ +#define AT91_PD23_RTS2 (1 << 23) /* A: USART Ready To Send 2 */ +#define AT91_PD23_TPK11 (1 << 23) /* B: ETM Trace Packet Port 11 */ +#define AT91_PD24_RTS3 (1 << 24) /* A: USART Ready To Send 3 */ +#define AT91_PD24_TPK12 (1 << 24) /* B: ETM Trace Packet Port 12 */ +#define AT91_PD25_DTR1 (1 << 25) /* A: USART Data Terminal Ready 1 */ +#define AT91_PD25_TPK13 (1 << 25) /* B: ETM Trace Packet Port 13 */ +#define AT91_PD26_TPK14 (1 << 26) /* B: ETM Trace Packet Port 14 */ +#define AT91_PD27_TPK15 (1 << 27) /* B: ETM Trace Packet Port 15 */ +#endif + +#endif diff --git a/include/asm-arm/arch-at91/at91rm9200_emac.h b/include/asm-arm/arch-at91/at91rm9200_emac.h new file mode 100644 index 000000000000..0c417af5fe7f --- /dev/null +++ b/include/asm-arm/arch-at91/at91rm9200_emac.h @@ -0,0 +1,138 @@ +/* + * include/asm-arm/arch-at91/at91rm9200_emac.h + * + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) SAN People + * + * Ethernet MAC registers. + * Based on AT91RM9200 datasheet revision E. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91RM9200_EMAC_H +#define AT91RM9200_EMAC_H + +#define AT91_EMAC_CTL 0x00 /* Control Register */ +#define AT91_EMAC_LB (1 << 0) /* Loopback */ +#define AT91_EMAC_LBL (1 << 1) /* Loopback Local */ +#define AT91_EMAC_RE (1 << 2) /* Receive Enable */ +#define AT91_EMAC_TE (1 << 3) /* Transmit Enable */ +#define AT91_EMAC_MPE (1 << 4) /* Management Port Enable */ +#define AT91_EMAC_CSR (1 << 5) /* Clear Statistics Registers */ +#define AT91_EMAC_INCSTAT (1 << 6) /* Increment Statistics Registers */ +#define AT91_EMAC_WES (1 << 7) /* Write Enable for Statistics Registers */ +#define AT91_EMAC_BP (1 << 8) /* Back Pressure */ + +#define AT91_EMAC_CFG 0x04 /* Configuration Register */ +#define AT91_EMAC_SPD (1 << 0) /* Speed */ +#define AT91_EMAC_FD (1 << 1) /* Full Duplex */ +#define AT91_EMAC_BR (1 << 2) /* Bit Rate */ +#define AT91_EMAC_CAF (1 << 4) /* Copy All Frames */ +#define AT91_EMAC_NBC (1 << 5) /* No Broadcast */ +#define AT91_EMAC_MTI (1 << 6) /* Multicast Hash Enable */ +#define AT91_EMAC_UNI (1 << 7) /* Unicast Hash Enable */ +#define AT91_EMAC_BIG (1 << 8) /* Receive 1522 Bytes */ +#define AT91_EMAC_EAE (1 << 9) /* External Address Match Enable */ +#define AT91_EMAC_CLK (3 << 10) /* MDC Clock Divisor */ +#define AT91_EMAC_CLK_DIV8 (0 << 10) +#define AT91_EMAC_CLK_DIV16 (1 << 10) +#define AT91_EMAC_CLK_DIV32 (2 << 10) +#define AT91_EMAC_CLK_DIV64 (3 << 10) +#define AT91_EMAC_RTY (1 << 12) /* Retry Test */ +#define AT91_EMAC_RMII (1 << 13) /* Reduce MII (RMII) */ + +#define AT91_EMAC_SR 0x08 /* Status Register */ +#define AT91_EMAC_SR_LINK (1 << 0) /* Link */ +#define AT91_EMAC_SR_MDIO (1 << 1) /* MDIO pin */ +#define AT91_EMAC_SR_IDLE (1 << 2) /* PHY idle */ + +#define AT91_EMAC_TAR 0x0c /* Transmit Address Register */ + +#define AT91_EMAC_TCR 0x10 /* Transmit Control Register */ +#define AT91_EMAC_LEN (0x7ff << 0) /* Transmit Frame Length */ +#define AT91_EMAC_NCRC (1 << 15) /* No CRC */ + +#define AT91_EMAC_TSR 0x14 /* Transmit Status Register */ +#define AT91_EMAC_TSR_OVR (1 << 0) /* Transmit Buffer Overrun */ +#define AT91_EMAC_TSR_COL (1 << 1) /* Collision Occurred */ +#define AT91_EMAC_TSR_RLE (1 << 2) /* Retry Limit Exceeded */ +#define AT91_EMAC_TSR_IDLE (1 << 3) /* Transmitter Idle */ +#define AT91_EMAC_TSR_BNQ (1 << 4) /* Transmit Buffer not Queued */ +#define AT91_EMAC_TSR_COMP (1 << 5) /* Transmit Complete */ +#define AT91_EMAC_TSR_UND (1 << 6) /* Transmit Underrun */ + +#define AT91_EMAC_RBQP 0x18 /* Receive Buffer Queue Pointer */ + +#define AT91_EMAC_RSR 0x20 /* Receive Status Register */ +#define AT91_EMAC_RSR_BNA (1 << 0) /* Buffer Not Available */ +#define AT91_EMAC_RSR_REC (1 << 1) /* Frame Received */ +#define AT91_EMAC_RSR_OVR (1 << 2) /* RX Overrun */ + +#define AT91_EMAC_ISR 0x24 /* Interrupt Status Register */ +#define AT91_EMAC_DONE (1 << 0) /* Management Done */ +#define AT91_EMAC_RCOM (1 << 1) /* Receive Complete */ +#define AT91_EMAC_RBNA (1 << 2) /* Receive Buffer Not Available */ +#define AT91_EMAC_TOVR (1 << 3) /* Transmit Buffer Overrun */ +#define AT91_EMAC_TUND (1 << 4) /* Transmit Buffer Underrun */ +#define AT91_EMAC_RTRY (1 << 5) /* Retry Limit */ +#define AT91_EMAC_TBRE (1 << 6) /* Transmit Buffer Register Empty */ +#define AT91_EMAC_TCOM (1 << 7) /* Transmit Complete */ +#define AT91_EMAC_TIDLE (1 << 8) /* Transmit Idle */ +#define AT91_EMAC_LINK (1 << 9) /* Link */ +#define AT91_EMAC_ROVR (1 << 10) /* RX Overrun */ +#define AT91_EMAC_ABT (1 << 11) /* Abort */ + +#define AT91_EMAC_IER 0x28 /* Interrupt Enable Register */ +#define AT91_EMAC_IDR 0x2c /* Interrupt Disable Register */ +#define AT91_EMAC_IMR 0x30 /* Interrupt Mask Register */ + +#define AT91_EMAC_MAN 0x34 /* PHY Maintenance Register */ +#define AT91_EMAC_DATA (0xffff << 0) /* MDIO Data */ +#define AT91_EMAC_REGA (0x1f << 18) /* MDIO Register */ +#define AT91_EMAC_PHYA (0x1f << 23) /* MDIO PHY Address */ +#define AT91_EMAC_RW (3 << 28) /* Read/Write operation */ +#define AT91_EMAC_RW_W (1 << 28) +#define AT91_EMAC_RW_R (2 << 28) +#define AT91_EMAC_MAN_802_3 0x40020000 /* IEEE 802.3 value */ + +/* + * Statistics Registers. + */ +#define AT91_EMAC_FRA 0x40 /* Frames Transmitted OK */ +#define AT91_EMAC_SCOL 0x44 /* Single Collision Frame */ +#define AT91_EMAC_MCOL 0x48 /* Multiple Collision Frame */ +#define AT91_EMAC_OK 0x4c /* Frames Received OK */ +#define AT91_EMAC_SEQE 0x50 /* Frame Check Sequence Error */ +#define AT91_EMAC_ALE 0x54 /* Alignmemt Error */ +#define AT91_EMAC_DTE 0x58 /* Deffered Transmission Frame */ +#define AT91_EMAC_LCOL 0x5c /* Late Collision */ +#define AT91_EMAC_ECOL 0x60 /* Excessive Collision */ +#define AT91_EMAC_TUE 0x64 /* Transmit Underrun Error */ +#define AT91_EMAC_CSE 0x68 /* Carrier Sense Error */ +#define AT91_EMAC_DRFC 0x6c /* Discard RX Frame */ +#define AT91_EMAC_ROV 0x70 /* Receive Overrun */ +#define AT91_EMAC_CDE 0x74 /* Code Error */ +#define AT91_EMAC_ELR 0x78 /* Excessive Length Error */ +#define AT91_EMAC_RJB 0x7c /* Receive Jabber */ +#define AT91_EMAC_USF 0x80 /* Undersize Frame */ +#define AT91_EMAC_SQEE 0x84 /* SQE Test Error */ + +/* + * Address Registers. + */ +#define AT91_EMAC_HSL 0x90 /* Hash Address Low [31:0] */ +#define AT91_EMAC_HSH 0x94 /* Hash Address High [63:32] */ +#define AT91_EMAC_SA1L 0x98 /* Specific Address 1 Low, bytes 0-3 */ +#define AT91_EMAC_SA1H 0x9c /* Specific Address 1 High, bytes 4-5 */ +#define AT91_EMAC_SA2L 0xa0 /* Specific Address 2 Low, bytes 0-3 */ +#define AT91_EMAC_SA2H 0xa4 /* Specific Address 2 High, bytes 4-5 */ +#define AT91_EMAC_SA3L 0xa8 /* Specific Address 3 Low, bytes 0-3 */ +#define AT91_EMAC_SA3H 0xac /* Specific Address 3 High, bytes 4-5 */ +#define AT91_EMAC_SA4L 0xb0 /* Specific Address 4 Low, bytes 0-3 */ +#define AT91_EMAC_SA4H 0xb4 /* Specific Address 4 High, bytes 4-5 */ + +#endif diff --git a/include/asm-arm/arch-at91/at91rm9200_mc.h b/include/asm-arm/arch-at91/at91rm9200_mc.h new file mode 100644 index 000000000000..24d012939cc4 --- /dev/null +++ b/include/asm-arm/arch-at91/at91rm9200_mc.h @@ -0,0 +1,160 @@ +/* + * include/asm-arm/arch-at91/at91rm9200_mc.h + * + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) SAN People + * + * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals registers. + * Based on AT91RM9200 datasheet revision E. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91RM9200_MC_H +#define AT91RM9200_MC_H + +/* Memory Controller */ +#define AT91_MC_RCR (AT91_MC + 0x00) /* MC Remap Control Register */ +#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */ + +#define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */ +#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */ +#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */ +#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */ +#define AT91_MC_ABTSZ_BYTE (0 << 8) +#define AT91_MC_ABTSZ_HALFWORD (1 << 8) +#define AT91_MC_ABTSZ_WORD (2 << 8) +#define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */ +#define AT91_MC_ABTTYP_DATAREAD (0 << 10) +#define AT91_MC_ABTTYP_DATAWRITE (1 << 10) +#define AT91_MC_ABTTYP_FETCH (2 << 10) +#define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */ +#define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */ +#define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */ +#define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */ +#define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */ +#define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */ +#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */ +#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */ + +#define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */ + +#define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */ +#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */ +#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */ +#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */ +#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */ + +/* External Bus Interface (EBI) registers */ +#define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */ +#define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */ +#define AT91_EBI_CS0A_SMC (0 << 0) +#define AT91_EBI_CS0A_BFC (1 << 0) +#define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ +#define AT91_EBI_CS1A_SMC (0 << 1) +#define AT91_EBI_CS1A_SDRAMC (1 << 1) +#define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */ +#define AT91_EBI_CS3A_SMC (0 << 3) +#define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) +#define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */ +#define AT91_EBI_CS4A_SMC (0 << 4) +#define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4) +#define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */ +#define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */ + +/* Static Memory Controller (SMC) registers */ +#define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */ +#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */ +#define AT91_SMC_NWS_(x) ((x) << 0) +#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */ +#define AT91_SMC_TDF (0xf << 8) /* Data Float Time */ +#define AT91_SMC_TDF_(x) ((x) << 8) +#define AT91_SMC_BAT (1 << 12) /* Byte Access Type */ +#define AT91_SMC_DBW (3 << 13) /* Data Bus Width */ +#define AT91_SMC_DBW_16 (1 << 13) +#define AT91_SMC_DBW_8 (2 << 13) +#define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */ +#define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */ +#define AT91_SMC_ACSS_STD (0 << 16) +#define AT91_SMC_ACSS_1 (1 << 16) +#define AT91_SMC_ACSS_2 (2 << 16) +#define AT91_SMC_ACSS_3 (3 << 16) +#define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */ +#define AT91_SMC_RWSETUP_(x) ((x) << 24) +#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */ +#define AT91_SMC_RWHOLD_(x) ((x) << 28) + +/* SDRAM Controller registers */ +#define AT91_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */ +#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ +#define AT91_SDRAMC_MODE_NORMAL (0 << 0) +#define AT91_SDRAMC_MODE_NOP (1 << 0) +#define AT91_SDRAMC_MODE_PRECHARGE (2 << 0) +#define AT91_SDRAMC_MODE_LMR (3 << 0) +#define AT91_SDRAMC_MODE_REFRESH (4 << 0) +#define AT91_SDRAMC_DBW (1 << 4) /* Data Bus Width */ +#define AT91_SDRAMC_DBW_32 (0 << 4) +#define AT91_SDRAMC_DBW_16 (1 << 4) + +#define AT91_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */ +#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */ + +#define AT91_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */ +#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ +#define AT91_SDRAMC_NC_8 (0 << 0) +#define AT91_SDRAMC_NC_9 (1 << 0) +#define AT91_SDRAMC_NC_10 (2 << 0) +#define AT91_SDRAMC_NC_11 (3 << 0) +#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ +#define AT91_SDRAMC_NR_11 (0 << 2) +#define AT91_SDRAMC_NR_12 (1 << 2) +#define AT91_SDRAMC_NR_13 (2 << 2) +#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ +#define AT91_SDRAMC_NB_2 (0 << 4) +#define AT91_SDRAMC_NB_4 (1 << 4) +#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ +#define AT91_SDRAMC_CAS_2 (2 << 5) +#define AT91_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */ +#define AT91_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */ +#define AT91_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */ +#define AT91_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */ +#define AT91_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */ +#define AT91_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */ + +#define AT91_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */ +#define AT91_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */ +#define AT91_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */ +#define AT91_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */ +#define AT91_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */ +#define AT91_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */ + +/* Burst Flash Controller register */ +#define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */ +#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */ +#define AT91_BFC_BFCOM_DISABLED (0 << 0) +#define AT91_BFC_BFCOM_ASYNC (1 << 0) +#define AT91_BFC_BFCOM_BURST (2 << 0) +#define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */ +#define AT91_BFC_BFCC_MCK (1 << 2) +#define AT91_BFC_BFCC_DIV2 (2 << 2) +#define AT91_BFC_BFCC_DIV4 (3 << 2) +#define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */ +#define AT91_BFC_PAGES (7 << 8) /* Page Size */ +#define AT91_BFC_PAGES_NO_PAGE (0 << 8) +#define AT91_BFC_PAGES_16 (1 << 8) +#define AT91_BFC_PAGES_32 (2 << 8) +#define AT91_BFC_PAGES_64 (3 << 8) +#define AT91_BFC_PAGES_128 (4 << 8) +#define AT91_BFC_PAGES_256 (5 << 8) +#define AT91_BFC_PAGES_512 (6 << 8) +#define AT91_BFC_PAGES_1024 (7 << 8) +#define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */ +#define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */ +#define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */ +#define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */ +#define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */ + +#endif diff --git a/include/asm-arm/arch-at91/at91sam9260.h b/include/asm-arm/arch-at91/at91sam9260.h new file mode 100644 index 000000000000..73d93ae9243e --- /dev/null +++ b/include/asm-arm/arch-at91/at91sam9260.h @@ -0,0 +1,125 @@ +/* + * include/asm-arm/arch-at91/at91sam9260.h + * + * (C) 2006 Andrew Victor + * + * Common definitions. + * Based on AT91SAM9260 datasheet revision A (Preliminary). + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91SAM9260_H +#define AT91SAM9260_H + +/* + * Peripheral identifiers/interrupts. + */ +#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define AT91_ID_SYS 1 /* System Peripherals */ +#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */ +#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */ +#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */ +#define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */ +#define AT91SAM9260_ID_US0 6 /* USART 0 */ +#define AT91SAM9260_ID_US1 7 /* USART 1 */ +#define AT91SAM9260_ID_US2 8 /* USART 2 */ +#define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */ +#define AT91SAM9260_ID_UDP 10 /* USB Device Port */ +#define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */ +#define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */ +#define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */ +#define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */ +#define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */ +#define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */ +#define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */ +#define AT91SAM9260_ID_UHP 20 /* USB Host port */ +#define AT91SAM9260_ID_EMAC 21 /* Ethernet */ +#define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */ +#define AT91SAM9260_ID_US3 23 /* USART 3 */ +#define AT91SAM9260_ID_US4 24 /* USART 4 */ +#define AT91SAM9260_ID_US5 25 /* USART 5 */ +#define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */ +#define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */ +#define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */ +#define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ +#define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ +#define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ + + +/* + * User Peripheral physical base addresses. + */ +#define AT91SAM9260_BASE_TCB0 0xfffa0000 +#define AT91SAM9260_BASE_TC0 0xfffa0000 +#define AT91SAM9260_BASE_TC1 0xfffa0040 +#define AT91SAM9260_BASE_TC2 0xfffa0080 +#define AT91SAM9260_BASE_UDP 0xfffa4000 +#define AT91SAM9260_BASE_MCI 0xfffa8000 +#define AT91SAM9260_BASE_TWI 0xfffac000 +#define AT91SAM9260_BASE_US0 0xfffb0000 +#define AT91SAM9260_BASE_US1 0xfffb4000 +#define AT91SAM9260_BASE_US2 0xfffb8000 +#define AT91SAM9260_BASE_SSC 0xfffbc000 +#define AT91SAM9260_BASE_ISI 0xfffc0000 +#define AT91SAM9260_BASE_EMAC 0xfffc4000 +#define AT91SAM9260_BASE_SPI0 0xfffc8000 +#define AT91SAM9260_BASE_SPI1 0xfffcc000 +#define AT91SAM9260_BASE_US3 0xfffd0000 +#define AT91SAM9260_BASE_US4 0xfffd4000 +#define AT91SAM9260_BASE_US5 0xfffd8000 +#define AT91SAM9260_BASE_TCB1 0xfffdc000 +#define AT91SAM9260_BASE_TC3 0xfffdc000 +#define AT91SAM9260_BASE_TC4 0xfffdc040 +#define AT91SAM9260_BASE_TC5 0xfffdc080 +#define AT91SAM9260_BASE_ADC 0xfffe0000 +#define AT91_BASE_SYS 0xffffe800 + +/* + * System Peripherals (offset from AT91_BASE_SYS) + */ +#define AT91_ECC (0xffffe800 - AT91_BASE_SYS) +#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) +#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) +#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) +#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) +#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) +#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) +#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) +#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) +#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) +#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) +#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) +#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) +#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) +#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) +#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) +#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) + + +/* + * Internal Memory. + */ +#define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */ +#define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ + +#define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ +#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */ +#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ +#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */ + +#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */ + +#if 0 +/* + * PIO pin definitions (peripheral A/B multiplexing). + */ + +// TODO: Add + +#endif + +#endif diff --git a/include/asm-arm/arch-at91/at91sam9260_matrix.h b/include/asm-arm/arch-at91/at91sam9260_matrix.h new file mode 100644 index 000000000000..573e97a47d22 --- /dev/null +++ b/include/asm-arm/arch-at91/at91sam9260_matrix.h @@ -0,0 +1,78 @@ +/* + * include/asm-arm/arch-at91/at91sam9260_matrix.h + * + * Memory Controllers (MATRIX, EBI) - System peripherals registers. + * Based on AT91SAM9260 datasheet revision B. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91SAM9260_MATRIX_H +#define AT91SAM9260_MATRIX_H + +#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ +#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ +#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ +#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ +#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ +#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x04) /* Master Configuration Register 5 */ +#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ +#define AT91_MATRIX_ULBT_INFINITE (0 << 0) +#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_FOUR (2 << 0) +#define AT91_MATRIX_ULBT_EIGHT (3 << 0) +#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) + +#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ +#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ +#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ +#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ +#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ +#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ +#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ +#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) +#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ +#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ +#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) +#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) + +#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ +#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ +#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ +#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ +#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ +#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ +#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ +#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ +#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ +#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ +#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ + +#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ +#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ +#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ + +#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */ +#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ +#define AT91_MATRIX_CS1A_SMC (0 << 1) +#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) +#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ +#define AT91_MATRIX_CS3A_SMC (0 << 3) +#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) +#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ +#define AT91_MATRIX_CS4A_SMC (0 << 4) +#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) +#define AT91_MATRIX_CS5A (1 << 5 ) /* Chip Select 5 Assignment */ +#define AT91_MATRIX_CS5A_SMC (0 << 5) +#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) +#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ +#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ +#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) +#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) + +#endif diff --git a/include/asm-arm/arch-at91/at91sam9261.h b/include/asm-arm/arch-at91/at91sam9261.h new file mode 100644 index 000000000000..01b58ffe2e27 --- /dev/null +++ b/include/asm-arm/arch-at91/at91sam9261.h @@ -0,0 +1,292 @@ +/* + * include/asm-arm/arch-at91/at91sam9261.h + * + * Copyright (C) SAN People + * + * Common definitions. + * Based on AT91SAM9261 datasheet revision E. (Preliminary) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91SAM9261_H +#define AT91SAM9261_H + +/* + * Peripheral identifiers/interrupts. + */ +#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define AT91_ID_SYS 1 /* System Peripherals */ +#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */ +#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */ +#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */ +#define AT91SAM9261_ID_US0 6 /* USART 0 */ +#define AT91SAM9261_ID_US1 7 /* USART 1 */ +#define AT91SAM9261_ID_US2 8 /* USART 2 */ +#define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */ +#define AT91SAM9261_ID_UDP 10 /* USB Device Port */ +#define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */ +#define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */ +#define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */ +#define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */ +#define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */ +#define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */ +#define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */ +#define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */ +#define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */ +#define AT91SAM9261_ID_UHP 20 /* USB Host port */ +#define AT91SAM9261_ID_LCDC 21 /* LDC Controller */ +#define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ +#define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ +#define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ + + +/* + * User Peripheral physical base addresses. + */ +#define AT91SAM9261_BASE_TCB0 0xfffa0000 +#define AT91SAM9261_BASE_TC0 0xfffa0000 +#define AT91SAM9261_BASE_TC1 0xfffa0040 +#define AT91SAM9261_BASE_TC2 0xfffa0080 +#define AT91SAM9261_BASE_UDP 0xfffa4000 +#define AT91SAM9261_BASE_MCI 0xfffa8000 +#define AT91SAM9261_BASE_TWI 0xfffac000 +#define AT91SAM9261_BASE_US0 0xfffb0000 +#define AT91SAM9261_BASE_US1 0xfffb4000 +#define AT91SAM9261_BASE_US2 0xfffb8000 +#define AT91SAM9261_BASE_SSC0 0xfffbc000 +#define AT91SAM9261_BASE_SSC1 0xfffc0000 +#define AT91SAM9261_BASE_SSC2 0xfffc4000 +#define AT91SAM9261_BASE_SPI0 0xfffc8000 +#define AT91SAM9261_BASE_SPI1 0xfffcc000 +#define AT91_BASE_SYS 0xffffea00 + + +/* + * System Peripherals (offset from AT91_BASE_SYS) + */ +#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) +#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) +#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) +#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) +#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) +#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) +#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) +#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) +#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) +#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) +#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) +#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) +#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) +#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) +#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) + + +/* + * Internal Memory. + */ +#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */ +#define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */ + +#define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */ +#define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ + +#define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */ +#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */ + + +#if 0 +/* + * PIO pin definitions (peripheral A/B multiplexing). + */ +#define AT91_PA0_SPI0_MISO (1 << 0) /* A: SPI0 Master In Slave */ +#define AT91_PA0_MCDA0 (1 << 0) /* B: Multimedia Card A Data 0 */ +#define AT91_PA1_SPI0_MOSI (1 << 1) /* A: SPI0 Master Out Slave */ +#define AT91_PA1_MCCDA (1 << 1) /* B: Multimedia Card A Command */ +#define AT91_PA2_SPI0_SPCK (1 << 2) /* A: SPI0 Serial Clock */ +#define AT91_PA2_MCCK (1 << 2) /* B: Multimedia Card Clock */ +#define AT91_PA3_SPI0_NPCS0 (1 << 3) /* A: SPI0 Peripheral Chip Select 0 */ +#define AT91_PA4_SPI0_NPCS1 (1 << 4) /* A: SPI0 Peripheral Chip Select 1 */ +#define AT91_PA4_MCDA1 (1 << 4) /* B: Multimedia Card A Data 1 */ +#define AT91_PA5_SPI0_NPCS2 (1 << 5) /* A: SPI0 Peripheral Chip Select 2 */ +#define AT91_PA5_MCDA2 (1 << 5) /* B: Multimedia Card A Data 2 */ +#define AT91_PA6_SPI0_NPCS3 (1 << 6) /* A: SPI0 Peripheral Chip Select 3 */ +#define AT91_PA6_MCDA3 (1 << 6) /* B: Multimedia Card A Data 3 */ +#define AT91_PA7_TWD (1 << 7) /* A: TWI Two-wire Serial Data */ +#define AT91_PA7_PCK0 (1 << 7) /* B: PMC Programmable clock Output 0 */ +#define AT91_PA8_TWCK (1 << 8) /* A: TWI Two-wire Serial Clock */ +#define AT91_PA8_PCK1 (1 << 8) /* B: PMC Programmable clock Output 1 */ +#define AT91_PA9_DRXD (1 << 9) /* A: DBGU Debug Receive Data */ +#define AT91_PA9_PCK2 (1 << 9) /* B: PMC Programmable clock Output 2 */ +#define AT91_PA10_DTXD (1 << 10) /* A: DBGU Debug Transmit Data */ +#define AT91_PA10_PCK3 (1 << 10) /* B: PMC Programmable clock Output 3 */ +#define AT91_PA11_TSYNC (1 << 11) /* A: Trace Synchronization Signal */ +#define AT91_PA11_SCK1 (1 << 11) /* B: USART1 Serial Clock */ +#define AT91_PA12_TCLK (1 << 12) /* A: Trace Clock */ +#define AT91_PA12_RTS1 (1 << 12) /* B: USART1 Ready To Send */ +#define AT91_PA13_TPS0 (1 << 13) /* A: Trace ARM Pipeline Status 0 */ +#define AT91_PA13_CTS1 (1 << 13) /* B: USART1 Clear To Send */ +#define AT91_PA14_TPS1 (1 << 14) /* A: Trace ARM Pipeline Status 1 */ +#define AT91_PA14_SCK2 (1 << 14) /* B: USART2 Serial Clock */ +#define AT91_PA15_TPS2 (1 << 15) /* A: Trace ARM Pipeline Status 2 */ +#define AT91_PA15_RTS2 (1 << 15) /* B: USART2 Ready To Send */ +#define AT91_PA16_TPK0 (1 << 16) /* A: Trace Packet Port 0 */ +#define AT91_PA16_CTS2 (1 << 16) /* B: USART2 Clear To Send */ +#define AT91_PA17_TPK1 (1 << 17) /* A: Trace Packet Port 1 */ +#define AT91_PA17_TF1 (1 << 17) /* B: SSC1 Transmit Frame Sync */ +#define AT91_PA18_TPK2 (1 << 18) /* A: Trace Packet Port 2 */ +#define AT91_PA18_TK1 (1 << 18) /* B: SSC1 Transmit Clock */ +#define AT91_PA19_TPK3 (1 << 19) /* A: Trace Packet Port 3 */ +#define AT91_PA19_TD1 (1 << 19) /* B: SSC1 Transmit Data */ +#define AT91_PA20_TPK4 (1 << 20) /* A: Trace Packet Port 4 */ +#define AT91_PA20_RD1 (1 << 20) /* B: SSC1 Receive Data */ +#define AT91_PA21_TPK5 (1 << 21) /* A: Trace Packet Port 5 */ +#define AT91_PA21_RK1 (1 << 21) /* B: SSC1 Receive Clock */ +#define AT91_PA22_TPK6 (1 << 22) /* A: Trace Packet Port 6 */ +#define AT91_PA22_RF1 (1 << 22) /* B: SSC1 Receive Frame Sync */ +#define AT91_PA23_TPK7 (1 << 23) /* A: Trace Packet Port 7 */ +#define AT91_PA23_RTS0 (1 << 23) /* B: USART0 Ready To Send */ +#define AT91_PA24_TPK8 (1 << 24) /* A: Trace Packet Port 8 */ +#define AT91_PA24_SPI1_NPCS1 (1 << 24) /* B: SPI1 Peripheral Chip Select 1 */ +#define AT91_PA25_TPK9 (1 << 25) /* A: Trace Packet Port 9 */ +#define AT91_PA25_SPI1_NPCS2 (1 << 25) /* B: SPI1 Peripheral Chip Select 2 */ +#define AT91_PA26_TPK10 (1 << 26) /* A: Trace Packet Port 10 */ +#define AT91_PA26_SPI1_NPCS3 (1 << 26) /* B: SPI1 Peripheral Chip Select 3 */ +#define AT91_PA27_TPK11 (1 << 27) /* A: Trace Packet Port 11 */ +#define AT91_PA27_SPI0_NPCS1 (1 << 27) /* B: SPI0 Peripheral Chip Select 1 */ +#define AT91_PA28_TPK12 (1 << 28) /* A: Trace Packet Port 12 */ +#define AT91_PA28_SPI0_NPCS2 (1 << 28) /* B: SPI0 Peripheral Chip Select 2 */ +#define AT91_PA29_TPK13 (1 << 29) /* A: Trace Packet Port 13 */ +#define AT91_PA29_SPI0_NPCS3 (1 << 29) /* B: SPI0 Peripheral Chip Select 3 */ +#define AT91_PA30_TPK14 (1 << 30) /* A: Trace Packet Port 14 */ +#define AT91_PA30_A23 (1 << 30) /* B: Address Bus bit 23 */ +#define AT91_PA31_TPK15 (1 << 31) /* A: Trace Packet Port 15 */ +#define AT91_PA31_A24 (1 << 31) /* B: Address Bus bit 24 */ + +#define AT91_PB0_LCDVSYNC (1 << 0) /* A: LCD Vertical Synchronization */ +#define AT91_PB1_LCDHSYNC (1 << 1) /* A: LCD Horizontal Synchronization */ +#define AT91_PB2_LCDDOTCK (1 << 2) /* A: LCD Dot Clock */ +#define AT91_PB2_PCK0 (1 << 2) /* B: PMC Programmable clock Output 0 */ +#define AT91_PB3_LCDDEN (1 << 3) /* A: LCD Data Enable */ +#define AT91_PB4_LCDCC (1 << 4) /* A: LCD Contrast Control */ +#define AT91_PB4_LCDD2 (1 << 4) /* B: LCD Data Bus Bit 2 */ +#define AT91_PB5_LCDD0 (1 << 5) /* A: LCD Data Bus Bit 0 */ +#define AT91_PB5_LCDD3 (1 << 5) /* B: LCD Data Bus Bit 3 */ +#define AT91_PB6_LCDD1 (1 << 6) /* A: LCD Data Bus Bit 1 */ +#define AT91_PB6_LCDD4 (1 << 6) /* B: LCD Data Bus Bit 4 */ +#define AT91_PB7_LCDD2 (1 << 7) /* A: LCD Data Bus Bit 2 */ +#define AT91_PB7_LCDD5 (1 << 7) /* B: LCD Data Bus Bit 5 */ +#define AT91_PB8_LCDD3 (1 << 8) /* A: LCD Data Bus Bit 3 */ +#define AT91_PB8_LCDD6 (1 << 8) /* B: LCD Data Bus Bit 6 */ +#define AT91_PB9_LCDD4 (1 << 9) /* A: LCD Data Bus Bit 4 */ +#define AT91_PB9_LCDD7 (1 << 9) /* B: LCD Data Bus Bit 7 */ +#define AT91_PB10_LCDD5 (1 << 10) /* A: LCD Data Bus Bit 5 */ +#define AT91_PB10_LCDD10 (1 << 10) /* B: LCD Data Bus Bit 10 */ +#define AT91_PB11_LCDD6 (1 << 11) /* A: LCD Data Bus Bit 6 */ +#define AT91_PB11_LCDD11 (1 << 11) /* B: LCD Data Bus Bit 11 */ +#define AT91_PB12_LCDD7 (1 << 12) /* A: LCD Data Bus Bit 7 */ +#define AT91_PB12_LCDD12 (1 << 12) /* B: LCD Data Bus Bit 12 */ +#define AT91_PB13_LCDD8 (1 << 13) /* A: LCD Data Bus Bit 8 */ +#define AT91_PB13_LCDD13 (1 << 13) /* B: LCD Data Bus Bit 13 */ +#define AT91_PB14_LCDD9 (1 << 14) /* A: LCD Data Bus Bit 9 */ +#define AT91_PB14_LCDD14 (1 << 14) /* B: LCD Data Bus Bit 14 */ +#define AT91_PB15_LCDD10 (1 << 15) /* A: LCD Data Bus Bit 10 */ +#define AT91_PB15_LCDD15 (1 << 15) /* B: LCD Data Bus Bit 15 */ +#define AT91_PB16_LCDD11 (1 << 16) /* A: LCD Data Bus Bit 11 */ +#define AT91_PB16_LCDD19 (1 << 16) /* B: LCD Data Bus Bit 19 */ +#define AT91_PB17_LCDD12 (1 << 17) /* A: LCD Data Bus Bit 12 */ +#define AT91_PB17_LCDD20 (1 << 17) /* B: LCD Data Bus Bit 20 */ +#define AT91_PB18_LCDD13 (1 << 18) /* A: LCD Data Bus Bit 13 */ +#define AT91_PB18_LCDD21 (1 << 18) /* B: LCD Data Bus Bit 21 */ +#define AT91_PB19_LCDD14 (1 << 19) /* A: LCD Data Bus Bit 14 */ +#define AT91_PB19_LCDD22 (1 << 19) /* B: LCD Data Bus Bit 22 */ +#define AT91_PB20_LCDD15 (1 << 20) /* A: LCD Data Bus Bit 15 */ +#define AT91_PB20_LCDD23 (1 << 20) /* B: LCD Data Bus Bit 23 */ +#define AT91_PB21_TF0 (1 << 21) /* A: SSC0 Transmit Frame Sync */ +#define AT91_PB21_LCDD16 (1 << 21) /* B: LCD Data Bus Bit 16 */ +#define AT91_PB22_TK0 (1 << 22) /* A: SSC0 Transmit Clock */ +#define AT91_PB22_LCDD17 (1 << 22) /* B: LCD Data Bus Bit 17 */ +#define AT91_PB23_TD0 (1 << 23) /* A: SSC0 Transmit Data */ +#define AT91_PB23_LCDD18 (1 << 23) /* B: LCD Data Bus Bit 18 */ +#define AT91_PB24_RD0 (1 << 24) /* A: SSC0 Receive Data */ +#define AT91_PB24_LCDD19 (1 << 24) /* B: LCD Data Bus Bit 19 */ +#define AT91_PB25_RK0 (1 << 25) /* A: SSC0 Receive Clock */ +#define AT91_PB25_LCDD20 (1 << 25) /* B: LCD Data Bus Bit 20 */ +#define AT91_PB26_RF0 (1 << 26) /* A: SSC0 Receive Frame Sync */ +#define AT91_PB26_LCDD21 (1 << 26) /* B: LCD Data Bus Bit 21 */ +#define AT91_PB27_SPI1_NPCS1 (1 << 27) /* A: SPI1 Peripheral Chip Select 1 */ +#define AT91_PB27_LCDD22 (1 << 27) /* B: LCD Data Bus Bit 22 */ +#define AT91_PB28_SPI1_NPCS0 (1 << 28) /* A: SPI1 Peripheral Chip Select 0 */ +#define AT91_PB28_LCDD23 (1 << 28) /* B: LCD Data Bus Bit 23 */ +#define AT91_PB29_SPI1_SPCK (1 << 29) /* A: SPI1 Serial Clock */ +#define AT91_PB29_IRQ2 (1 << 29) /* B: Interrupt input 2 */ +#define AT91_PB30_SPI1_MISO (1 << 30) /* A: SPI1 Master In Slave */ +#define AT91_PB30_IRQ1 (1 << 30) /* B: Interrupt input 1 */ +#define AT91_PB31_SPI1_MOSI (1 << 31) /* A: SPI1 Master Out Slave */ +#define AT91_PB31_PCK2 (1 << 31) /* B: PMC Programmable clock Output 2 */ + +#define AT91_PC0_SMOE (1 << 0) /* A: SmartMedia Output Enable */ +#define AT91_PC0_NCS6 (1 << 0) /* B: Chip Select 6 */ +#define AT91_PC1_SMWE (1 << 1) /* A: SmartMedia Write Enable */ +#define AT91_PC1_NCS7 (1 << 1) /* B: Chip Select 7 */ +#define AT91_PC2_NWAIT (1 << 2) /* A: NWAIT */ +#define AT91_PC2_IRQ0 (1 << 2) /* B: Interrupt input 0 */ +#define AT91_PC3_A25_CFRNW (1 << 3) /* A: Address Bus[25] / Compact Flash Read Not Write */ +#define AT91_PC4_NCS4_CFCS0 (1 << 4) /* A: Chip Select 4 / CompactFlash Chip Select 0 */ +#define AT91_PC5_NCS5_CFCS1 (1 << 5) /* A: Chip Select 5 / CompactFlash Chip Select 1 */ +#define AT91_PC6_CFCE1 (1 << 6) /* A: CompactFlash Chip Enable 1 */ +#define AT91_PC7_CFCE2 (1 << 7) /* A: CompactFlash Chip Enable 2 */ +#define AT91_PC8_TXD0 (1 << 8) /* A: USART0 Transmit Data */ +#define AT91_PC8_PCK2 (1 << 8) /* B: PMC Programmable clock Output 2 */ +#define AT91_PC9_RXD0 (1 << 9) /* A: USART0 Receive Data */ +#define AT91_PC9_PCK3 (1 << 9) /* B: PMC Programmable clock Output 3 */ +#define AT91_PC10_RTS0 (1 << 10) /* A: USART0 Ready To Send */ +#define AT91_PC10_SCK0 (1 << 10) /* B: USART0 Serial Clock */ +#define AT91_PC11_CTS0 (1 << 11) /* A: USART0 Clear To Send */ +#define AT91_PC11_FIQ (1 << 11) /* B: AIC Fast Interrupt Input */ +#define AT91_PC12_TXD1 (1 << 12) /* A: USART1 Transmit Data */ +#define AT91_PC12_NCS6 (1 << 12) /* B: Chip Select 6 */ +#define AT91_PC13_RXD1 (1 << 13) /* A: USART1 Receive Data */ +#define AT91_PC13_NCS7 (1 << 13) /* B: Chip Select 7 */ +#define AT91_PC14_TXD2 (1 << 14) /* A: USART2 Transmit Data */ +#define AT91_PC14_SPI1_NPCS2 (1 << 14) /* B: SPI1 Peripheral Chip Select 2 */ +#define AT91_PC15_RXD2 (1 << 15) /* A: USART2 Receive Data */ +#define AT91_PC15_SPI1_NPCS3 (1 << 15) /* B: SPI1 Peripheral Chip Select 3 */ +#define AT91_PC16_D16 (1 << 16) /* A: Data Bus [16] */ +#define AT91_PC16_TCLK0 (1 << 16) /* B: Timer Counter 0 external clock input */ +#define AT91_PC17_D17 (1 << 17) /* A: Data Bus [17] */ +#define AT91_PC17_TCLK1 (1 << 17) /* B: Timer Counter 1 external clock input */ +#define AT91_PC18_D18 (1 << 18) /* A: Data Bus [18] */ +#define AT91_PC18_TCLK2 (1 << 18) /* B: Timer Counter 2 external clock input */ +#define AT91_PC19_D19 (1 << 19) /* A: Data Bus [19] */ +#define AT91_PC19_TIOA0 (1 << 19) /* B: Timer Counter 0 Multipurpose Timer I/O Pin A */ +#define AT91_PC20_D20 (1 << 20) /* A: Data Bus [20] */ +#define AT91_PC20_TIOB0 (1 << 20) /* B: Timer Counter 0 Multipurpose Timer I/O Pin B */ +#define AT91_PC21_D21 (1 << 21) /* A: Data Bus [21] */ +#define AT91_PC21_TIOA1 (1 << 21) /* B: Timer Counter 1 Multipurpose Timer I/O Pin A */ +#define AT91_PC22_D22 (1 << 22) /* A: Data Bus [22] */ +#define AT91_PC22_TIOB1 (1 << 22) /* B: Timer Counter 1 Multipurpose Timer I/O Pin B */ +#define AT91_PC23_D23 (1 << 23) /* A: Data Bus [23] */ +#define AT91_PC23_TIOA2 (1 << 23) /* B: Timer Counter 2 Multipurpose Timer I/O Pin A */ +#define AT91_PC24_D24 (1 << 24) /* A: Data Bus [24] */ +#define AT91_PC24_TIOB2 (1 << 24) /* B: Timer Counter 2 Multipurpose Timer I/O Pin B */ +#define AT91_PC25_D25 (1 << 25) /* A: Data Bus [25] */ +#define AT91_PC25_TF2 (1 << 25) /* B: SSC2 Transmit Frame Sync */ +#define AT91_PC26_D26 (1 << 26) /* A: Data Bus [26] */ +#define AT91_PC26_TK2 (1 << 26) /* B: SSC2 Transmit Clock */ +#define AT91_PC27_D27 (1 << 27) /* A: Data Bus [27] */ +#define AT91_PC27_TD2 (1 << 27) /* B: SSC2 Transmit Data */ +#define AT91_PC28_D28 (1 << 28) /* A: Data Bus [28] */ +#define AT91_PC28_RD2 (1 << 28) /* B: SSC2 Receive Data */ +#define AT91_PC29_D29 (1 << 29) /* A: Data Bus [29] */ +#define AT91_PC29_RK2 (1 << 29) /* B: SSC2 Receive Clock */ +#define AT91_PC30_D30 (1 << 30) /* A: Data Bus [30] */ +#define AT91_PC30_RF2 (1 << 30) /* B: SSC2 Receive Frame Sync */ +#define AT91_PC31_D31 (1 << 31) /* A: Data Bus [31] */ +#define AT91_PC31_PCK1 (1 << 31) /* B: PMC Programmable clock Output 1 */ +#endif + +#endif diff --git a/include/asm-arm/arch-at91/at91sam9261_matrix.h b/include/asm-arm/arch-at91/at91sam9261_matrix.h new file mode 100644 index 000000000000..6f072421be5b --- /dev/null +++ b/include/asm-arm/arch-at91/at91sam9261_matrix.h @@ -0,0 +1,62 @@ +/* + * include/asm-arm/arch-at91/at91sam9261_matrix.h + * + * Memory Controllers (MATRIX, EBI) - System peripherals registers. + * Based on AT91SAM9261 datasheet revision D. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91SAM9261_MATRIX_H +#define AT91SAM9261_MATRIX_H + +#define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */ +#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ +#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ + +#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */ +#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */ +#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C) /* Slave Configuration Register 2 */ +#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10) /* Slave Configuration Register 3 */ +#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14) /* Slave Configuration Register 4 */ +#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ +#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ +#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) +#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ + +#define AT91_MATRIX_TCR (AT91_MATRIX + 0x24) /* TCM Configuration Register */ +#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ +#define AT91_MATRIX_ITCM_0 (0 << 0) +#define AT91_MATRIX_ITCM_16 (5 << 0) +#define AT91_MATRIX_ITCM_32 (6 << 0) +#define AT91_MATRIX_ITCM_64 (7 << 0) +#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ +#define AT91_MATRIX_DTCM_0 (0 << 4) +#define AT91_MATRIX_DTCM_16 (5 << 4) +#define AT91_MATRIX_DTCM_32 (6 << 4) +#define AT91_MATRIX_DTCM_64 (7 << 4) + +#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */ +#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ +#define AT91_MATRIX_CS1A_SMC (0 << 1) +#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) +#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ +#define AT91_MATRIX_CS3A_SMC (0 << 3) +#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) +#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ +#define AT91_MATRIX_CS4A_SMC (0 << 4) +#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) +#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ +#define AT91_MATRIX_CS5A_SMC (0 << 5) +#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) +#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ + +#define AT91_MATRIX_USBPUCR (AT91_MATRIX + 0x34) /* USB Pad Pull-Up Control Register */ +#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */ + +#endif diff --git a/include/asm-arm/arch-at91/at91sam926x_mc.h b/include/asm-arm/arch-at91/at91sam926x_mc.h new file mode 100644 index 000000000000..355eee67ebca --- /dev/null +++ b/include/asm-arm/arch-at91/at91sam926x_mc.h @@ -0,0 +1,134 @@ +/* + * include/asm-arm/arch-at91/at91sam926x_mc.h + * + * Memory Controllers (SMC, SDRAMC) - System peripherals registers. + * Based on AT91SAM9261 datasheet revision D. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91SAM926x_MC_H +#define AT91SAM926x_MC_H + +/* SDRAM Controller (SDRAMC) registers */ +#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */ +#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ +#define AT91_SDRAMC_MODE_NORMAL 0 +#define AT91_SDRAMC_MODE_NOP 1 +#define AT91_SDRAMC_MODE_PRECHARGE 2 +#define AT91_SDRAMC_MODE_LMR 3 +#define AT91_SDRAMC_MODE_REFRESH 4 +#define AT91_SDRAMC_MODE_EXT_LMR 5 +#define AT91_SDRAMC_MODE_DEEP 6 + +#define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */ +#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */ + +#define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */ +#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ +#define AT91_SDRAMC_NC_8 (0 << 0) +#define AT91_SDRAMC_NC_9 (1 << 0) +#define AT91_SDRAMC_NC_10 (2 << 0) +#define AT91_SDRAMC_NC_11 (3 << 0) +#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ +#define AT91_SDRAMC_NR_11 (0 << 2) +#define AT91_SDRAMC_NR_12 (1 << 2) +#define AT91_SDRAMC_NR_13 (2 << 2) +#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ +#define AT91_SDRAMC_NB_2 (0 << 4) +#define AT91_SDRAMC_NB_4 (1 << 4) +#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ +#define AT91_SDRAMC_CAS_1 (1 << 5) +#define AT91_SDRAMC_CAS_2 (2 << 5) +#define AT91_SDRAMC_CAS_3 (3 << 5) +#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */ +#define AT91_SDRAMC_DBW_32 (0 << 7) +#define AT91_SDRAMC_DBW_16 (1 << 7) +#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */ +#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */ +#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */ +#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */ +#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */ +#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */ + +#define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */ +#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */ +#define AT91_SDRAMC_LPCB_DISABLE 0 +#define AT91_SDRAMC_LPCB_SELF_REFRESH 1 +#define AT91_SDRAMC_LPCB_POWER_DOWN 2 +#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3 +#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */ +#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ +#define AT91_SDRAMC_DS (3 << 10) /* Drive Strenght */ +#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ +#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12) +#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12) +#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12) + +#define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */ +#define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */ +#define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */ +#define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */ +#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */ + +#define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */ +#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */ +#define AT91_SDRAMC_MD_SDRAM 0 +#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 + + +/* Static Memory Controller (SMC) registers */ +#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ +#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ +#define AT91_SMC_NWESETUP_(x) ((x) << 0) +#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */ +#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8) +#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */ +#define AT91_SMC_NRDSETUP_(x) ((x) << 16) +#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */ +#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24) + +#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ +#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */ +#define AT91_SMC_NWEPULSE_(x) ((x) << 0) +#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */ +#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8) +#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */ +#define AT91_SMC_NRDPULSE_(x) ((x) << 16) +#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */ +#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24) + +#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ +#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */ +#define AT91_SMC_NWECYCLE_(x) ((x) << 0) +#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ +#define AT91_SMC_NRDCYCLE_(x) ((x) << 16) + +#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ +#define AT91_SMC_READMODE (1 << 0) /* Read Mode */ +#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ +#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ +#define AT91_SMC_EXNWMODE_DISABLE (0 << 4) +#define AT91_SMC_EXNWMODE_FROZEN (2 << 4) +#define AT91_SMC_EXNWMODE_READY (3 << 4) +#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ +#define AT91_SMC_BAT_SELECT (0 << 8) +#define AT91_SMC_BAT_WRITE (1 << 8) +#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */ +#define AT91_SMC_DBW_8 (0 << 12) +#define AT91_SMC_DBW_16 (1 << 12) +#define AT91_SMC_DBW_32 (2 << 12) +#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */ +#define AT91_SMC_TDF_(x) ((x) << 16) +#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */ +#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */ +#define AT91_SMC_PS (3 << 28) /* Page Size */ +#define AT91_SMC_PS_4 (0 << 28) +#define AT91_SMC_PS_8 (1 << 28) +#define AT91_SMC_PS_16 (2 << 28) +#define AT91_SMC_PS_32 (3 << 28) + +#endif diff --git a/include/asm-arm/arch-at91/board.h b/include/asm-arm/arch-at91/board.h new file mode 100644 index 000000000000..bf1afd0081b6 --- /dev/null +++ b/include/asm-arm/arch-at91/board.h @@ -0,0 +1,121 @@ +/* + * include/asm-arm/arch-at91/board.h + * + * Copyright (C) 2005 HP Labs + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* + * These are data structures found in platform_device.dev.platform_data, + * and describing board-specific data needed by drivers. For example, + * which pin is used for a given GPIO role. + * + * In 2.6, drivers should strongly avoid board-specific knowledge so + * that supporting new boards normally won't require driver patches. + * Most board-specific knowledge should be in arch/.../board-*.c files. + */ + +#ifndef __ASM_ARCH_BOARD_H +#define __ASM_ARCH_BOARD_H + +#include +#include +#include + + /* USB Device */ +struct at91_udc_data { + u8 vbus_pin; /* high == host powering us */ + u8 pullup_pin; /* high == D+ pulled up */ +}; +extern void __init at91_add_device_udc(struct at91_udc_data *data); + + /* Compact Flash */ +struct at91_cf_data { + u8 irq_pin; /* I/O IRQ */ + u8 det_pin; /* Card detect */ + u8 vcc_pin; /* power switching */ + u8 rst_pin; /* card reset */ + u8 chipselect; /* EBI Chip Select number */ +}; +extern void __init at91_add_device_cf(struct at91_cf_data *data); + + /* MMC / SD */ +struct at91_mmc_data { + u8 det_pin; /* card detect IRQ */ + unsigned slot_b:1; /* uses Slot B */ + unsigned wire4:1; /* (SD) supports DAT0..DAT3 */ + u8 wp_pin; /* (SD) writeprotect detect */ + u8 vcc_pin; /* power switching (high == on) */ +}; +extern void __init at91_add_device_mmc(struct at91_mmc_data *data); + + /* Ethernet */ +struct at91_eth_data { + u8 phy_irq_pin; /* PHY IRQ */ + u8 is_rmii; /* using RMII interface? */ +}; +extern void __init at91_add_device_eth(struct at91_eth_data *data); + +#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) +#define eth_platform_data at91_eth_data +#endif + + /* USB Host */ +struct at91_usbh_data { + u8 ports; /* number of ports on root hub */ +}; +extern void __init at91_add_device_usbh(struct at91_usbh_data *data); + + /* NAND / SmartMedia */ +struct at91_nand_data { + u8 enable_pin; /* chip enable */ + u8 det_pin; /* card detect */ + u8 rdy_pin; /* ready/busy */ + u8 ale; /* address line number connected to ALE */ + u8 cle; /* address line number connected to CLE */ + u8 bus_width_16; /* buswidth is 16 bit */ + struct mtd_partition* (*partition_info)(int, int*); +}; +extern void __init at91_add_device_nand(struct at91_nand_data *data); + + /* I2C*/ +extern void __init at91_add_device_i2c(void); + + /* SPI */ +extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices); + + /* Serial */ +struct at91_uart_config { + unsigned short console_tty; /* tty number of serial console */ + unsigned short nr_tty; /* number of serial tty's */ + short tty_map[]; /* map UART to tty number */ +}; +extern struct platform_device *atmel_default_console_device; +extern void __init at91_init_serial(struct at91_uart_config *config); + +struct atmel_uart_data { + short use_dma_tx; /* use transmit DMA? */ + short use_dma_rx; /* use receive DMA? */ + void __iomem *regs; /* virtual base address, if any */ +}; +extern void __init at91_add_device_serial(void); + + /* LEDs */ +extern u8 at91_leds_cpu; +extern u8 at91_leds_timer; +extern void __init at91_init_leds(u8 cpu_led, u8 timer_led); + +#endif diff --git a/include/asm-arm/arch-at91/cpu.h b/include/asm-arm/arch-at91/cpu.h new file mode 100644 index 000000000000..762eb41aa675 --- /dev/null +++ b/include/asm-arm/arch-at91/cpu.h @@ -0,0 +1,49 @@ +/* + * include/asm-arm/arch-at91/cpu.h + * + * Copyright (C) 2006 SAN People + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef __ASM_ARCH_CPU_H +#define __ASM_ARCH_CPU_H + +#include +#include + + +#define ARCH_ID_AT91RM9200 0x09290780 +#define ARCH_ID_AT91SAM9260 0x019803a0 +#define ARCH_ID_AT91SAM9261 0x019703a0 + + +static inline unsigned long at91_cpu_identify(void) +{ + return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); +} + + +#ifdef CONFIG_ARCH_AT91RM9200 +#define cpu_is_at91rm9200() (at91_cpu_identify() == ARCH_ID_AT91RM9200) +#else +#define cpu_is_at91rm9200() (0) +#endif + +#ifdef CONFIG_ARCH_AT91SAM9260 +#define cpu_is_at91sam9260() (at91_cpu_identify() == ARCH_ID_AT91SAM9260) +#else +#define cpu_is_at91sam9260() (0) +#endif + +#ifdef CONFIG_ARCH_AT91SAM9261 +#define cpu_is_at91sam9261() (at91_cpu_identify() == ARCH_ID_AT91SAM9261) +#else +#define cpu_is_at91sam9261() (0) +#endif + +#endif diff --git a/include/asm-arm/arch-at91/debug-macro.S b/include/asm-arm/arch-at91/debug-macro.S new file mode 100644 index 000000000000..20721ef1ed1b --- /dev/null +++ b/include/asm-arm/arch-at91/debug-macro.S @@ -0,0 +1,39 @@ +/* + * include/asm-arm/arch-at91/debug-macro.S + * + * Copyright (C) 2003-2005 SAN People + * + * Debugging macro include header + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + +#include +#include + + .macro addruart,rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + ldreq \rx, =AT91_BASE_SYS @ System peripherals (phys address) + ldrne \rx, =AT91_VA_BASE_SYS @ System peripherals (virt address) + .endm + + .macro senduart,rd,rx + strb \rd, [\rx, #AT91_DBGU_THR] @ Write to Transmitter Holding Register + .endm + + .macro waituart,rd,rx +1001: ldr \rd, [\rx, #AT91_DBGU_SR] @ Read Status Register + tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit + beq 1001b + .endm + + .macro busyuart,rd,rx +1001: ldr \rd, [\rx, #AT91_DBGU_SR] @ Read Status Register + tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete + beq 1001b + .endm + diff --git a/include/asm-arm/arch-at91/dma.h b/include/asm-arm/arch-at91/dma.h new file mode 100644 index 000000000000..774565412beb --- /dev/null +++ b/include/asm-arm/arch-at91/dma.h @@ -0,0 +1,19 @@ +/* + * include/asm-arm/arch-at91/dma.h + * + * Copyright (C) 2003 SAN People + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ diff --git a/include/asm-arm/arch-at91/entry-macro.S b/include/asm-arm/arch-at91/entry-macro.S new file mode 100644 index 000000000000..a6f33832a178 --- /dev/null +++ b/include/asm-arm/arch-at91/entry-macro.S @@ -0,0 +1,26 @@ +/* + * include/asm-arm/arch-at91/entry-macro.S + * + * Copyright (C) 2003-2005 SAN People + * + * Low-level IRQ helper macros for AT91RM9200 platforms + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include + + .macro disable_fiq + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \base, =(AT91_VA_BASE_SYS) @ base virtual address of SYS peripherals + ldr \irqnr, [\base, #AT91_AIC_IVR] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt) + ldr \irqstat, [\base, #AT91_AIC_ISR] @ read interrupt source number + teq \irqstat, #0 @ ISR is 0 when no current interrupt, or spurious interrupt + streq \tmp, [\base, #AT91_AIC_EOICR] @ not going to be handled further, then ACK it now. + .endm + diff --git a/include/asm-arm/arch-at91/gpio.h b/include/asm-arm/arch-at91/gpio.h new file mode 100644 index 000000000000..6d1a5eb34704 --- /dev/null +++ b/include/asm-arm/arch-at91/gpio.h @@ -0,0 +1,199 @@ +/* + * include/asm-arm/arch-at91/gpio.h + * + * Copyright (C) 2005 HP Labs + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef __ASM_ARCH_AT91RM9200_GPIO_H +#define __ASM_ARCH_AT91RM9200_GPIO_H + +#include + +#define PIN_BASE NR_AIC_IRQS + +#define MAX_GPIO_BANKS 4 + +/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */ + +#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0) +#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1) +#define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2) +#define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3) +#define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4) + +#define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5) +#define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6) +#define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7) +#define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8) +#define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9) + +#define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10) +#define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11) +#define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12) +#define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13) +#define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14) + +#define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15) +#define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16) +#define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17) +#define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18) +#define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19) + +#define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20) +#define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21) +#define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22) +#define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23) +#define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24) + +#define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25) +#define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26) +#define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27) +#define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28) +#define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29) + +#define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30) +#define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31) + +#define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0) +#define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1) +#define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2) +#define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3) +#define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4) + +#define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5) +#define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6) +#define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7) +#define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8) +#define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9) + +#define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10) +#define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11) +#define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12) +#define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13) +#define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14) + +#define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15) +#define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16) +#define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17) +#define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18) +#define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19) + +#define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20) +#define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21) +#define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22) +#define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23) +#define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24) + +#define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25) +#define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26) +#define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27) +#define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28) +#define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29) + +#define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30) +#define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31) + +#define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0) +#define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1) +#define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2) +#define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3) +#define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4) + +#define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5) +#define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6) +#define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7) +#define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8) +#define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9) + +#define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10) +#define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11) +#define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12) +#define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13) +#define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14) + +#define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15) +#define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16) +#define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17) +#define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18) +#define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19) + +#define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20) +#define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21) +#define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22) +#define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23) +#define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24) + +#define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25) +#define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26) +#define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27) +#define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28) +#define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29) + +#define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30) +#define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31) + +#define AT91_PIN_PD0 (PIN_BASE + 0x60 + 0) +#define AT91_PIN_PD1 (PIN_BASE + 0x60 + 1) +#define AT91_PIN_PD2 (PIN_BASE + 0x60 + 2) +#define AT91_PIN_PD3 (PIN_BASE + 0x60 + 3) +#define AT91_PIN_PD4 (PIN_BASE + 0x60 + 4) + +#define AT91_PIN_PD5 (PIN_BASE + 0x60 + 5) +#define AT91_PIN_PD6 (PIN_BASE + 0x60 + 6) +#define AT91_PIN_PD7 (PIN_BASE + 0x60 + 7) +#define AT91_PIN_PD8 (PIN_BASE + 0x60 + 8) +#define AT91_PIN_PD9 (PIN_BASE + 0x60 + 9) + +#define AT91_PIN_PD10 (PIN_BASE + 0x60 + 10) +#define AT91_PIN_PD11 (PIN_BASE + 0x60 + 11) +#define AT91_PIN_PD12 (PIN_BASE + 0x60 + 12) +#define AT91_PIN_PD13 (PIN_BASE + 0x60 + 13) +#define AT91_PIN_PD14 (PIN_BASE + 0x60 + 14) + +#define AT91_PIN_PD15 (PIN_BASE + 0x60 + 15) +#define AT91_PIN_PD16 (PIN_BASE + 0x60 + 16) +#define AT91_PIN_PD17 (PIN_BASE + 0x60 + 17) +#define AT91_PIN_PD18 (PIN_BASE + 0x60 + 18) +#define AT91_PIN_PD19 (PIN_BASE + 0x60 + 19) + +#define AT91_PIN_PD20 (PIN_BASE + 0x60 + 20) +#define AT91_PIN_PD21 (PIN_BASE + 0x60 + 21) +#define AT91_PIN_PD22 (PIN_BASE + 0x60 + 22) +#define AT91_PIN_PD23 (PIN_BASE + 0x60 + 23) +#define AT91_PIN_PD24 (PIN_BASE + 0x60 + 24) + +#define AT91_PIN_PD25 (PIN_BASE + 0x60 + 25) +#define AT91_PIN_PD26 (PIN_BASE + 0x60 + 26) +#define AT91_PIN_PD27 (PIN_BASE + 0x60 + 27) +#define AT91_PIN_PD28 (PIN_BASE + 0x60 + 28) +#define AT91_PIN_PD29 (PIN_BASE + 0x60 + 29) + +#define AT91_PIN_PD30 (PIN_BASE + 0x60 + 30) +#define AT91_PIN_PD31 (PIN_BASE + 0x60 + 31) + +#ifndef __ASSEMBLY__ +/* setup setup routines, called from board init or driver probe() */ +extern int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup); +extern int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup); +extern int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup); +extern int __init_or_module at91_set_gpio_output(unsigned pin, int value); +extern int __init_or_module at91_set_deglitch(unsigned pin, int is_on); +extern int __init_or_module at91_set_multi_drive(unsigned pin, int is_on); + +/* callable at any time */ +extern int at91_set_gpio_value(unsigned pin, int value); +extern int at91_get_gpio_value(unsigned pin); + +/* callable only from core power-management code */ +extern void at91_gpio_suspend(void); +extern void at91_gpio_resume(void); +#endif + +#endif + diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h new file mode 100644 index 000000000000..ccb7c7285b42 --- /dev/null +++ b/include/asm-arm/arch-at91/hardware.h @@ -0,0 +1,88 @@ +/* + * include/asm-arm/arch-at91/hardware.h + * + * Copyright (C) 2003 SAN People + * Copyright (C) 2003 ATMEL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include + +#if defined(CONFIG_ARCH_AT91RM9200) +#include +#elif defined(CONFIG_ARCH_AT91SAM9260) +#include +#elif defined(CONFIG_ARCH_AT91SAM9261) +#include +#else +#error "Unsupported AT91 processor" +#endif + + +/* + * Remap the peripherals from address 0xFFFA0000 .. 0xFFFFFFFF + * to 0xFEFA0000 .. 0xFF000000. (384Kb) + */ +#define AT91_IO_PHYS_BASE 0xFFFA0000 +#define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1) +#define AT91_IO_VIRT_BASE (0xFF000000 - AT91_IO_SIZE) + + /* Convert a physical IO address to virtual IO address */ +#define AT91_IO_P2V(x) ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE) + +/* + * Virtual to Physical Address mapping for IO devices. + */ +#define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS) +#define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91RM9200_BASE_EMAC) + + /* Internal SRAM is mapped below the IO devices */ +#define AT91_SRAM_MAX SZ_1M +#define AT91_VIRT_BASE (AT91_IO_VIRT_BASE - AT91_SRAM_MAX) + +/* Serial ports */ +#define ATMEL_MAX_UART 7 /* 6 USART3's and one DBGU port (SAM9260) */ + +/* External Memory Map */ +#define AT91_CHIPSELECT_0 0x10000000 +#define AT91_CHIPSELECT_1 0x20000000 +#define AT91_CHIPSELECT_2 0x30000000 +#define AT91_CHIPSELECT_3 0x40000000 +#define AT91_CHIPSELECT_4 0x50000000 +#define AT91_CHIPSELECT_5 0x60000000 +#define AT91_CHIPSELECT_6 0x70000000 +#define AT91_CHIPSELECT_7 0x80000000 + +/* SDRAM */ +#define AT91_SDRAM_BASE AT91_CHIPSELECT_1 + +/* Clocks */ +#define AT91_SLOW_CLOCK 32768 /* slow clock */ + +#ifndef __ASSEMBLY__ +#include + +static inline unsigned int at91_sys_read(unsigned int reg_offset) +{ + void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; + + return __raw_readl(addr + reg_offset); +} + +static inline void at91_sys_write(unsigned int reg_offset, unsigned long value) +{ + void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; + + __raw_writel(value, addr + reg_offset); +} +#endif + +#endif diff --git a/include/asm-arm/arch-at91/io.h b/include/asm-arm/arch-at91/io.h new file mode 100644 index 000000000000..401f327ec047 --- /dev/null +++ b/include/asm-arm/arch-at91/io.h @@ -0,0 +1,32 @@ +/* + * include/asm-arm/arch-at91/io.h + * + * Copyright (C) 2003 SAN People + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_IO_H +#define __ASM_ARCH_IO_H + +#include + +#define IO_SPACE_LIMIT 0xFFFFFFFF + +#define __io(a) ((void __iomem *)(a)) +#define __mem_pci(a) (a) + + +#endif diff --git a/include/asm-arm/arch-at91/irqs.h b/include/asm-arm/arch-at91/irqs.h new file mode 100644 index 000000000000..f041c98c5337 --- /dev/null +++ b/include/asm-arm/arch-at91/irqs.h @@ -0,0 +1,44 @@ +/* + * include/asm-arm/arch-at91/irqs.h + * + * Copyright (C) 2004 SAN People + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + +#include + +#define NR_AIC_IRQS 32 + + +/* + * Acknowledge interrupt with AIC after interrupt has been handled. + * (by kernel/irq.c) + */ +#define irq_finish(irq) do { at91_sys_write(AT91_AIC_EOICR, 0); } while (0) + + +/* + * IRQ interrupt symbols are the AT91xxx_ID_* symbols + * for IRQs handled directly through the AIC, or else the AT91_PIN_* + * symbols in gpio.h for ones handled indirectly as GPIOs. + * We make provision for 4 banks of GPIO. + */ +#define NR_IRQS (NR_AIC_IRQS + (4 * 32)) + +#endif diff --git a/include/asm-arm/arch-at91/memory.h b/include/asm-arm/arch-at91/memory.h new file mode 100644 index 000000000000..4835d6784509 --- /dev/null +++ b/include/asm-arm/arch-at91/memory.h @@ -0,0 +1,39 @@ +/* + * include/asm-arm/arch-at91/memory.h + * + * Copyright (C) 2004 SAN People + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#include + +#define PHYS_OFFSET (AT91_SDRAM_BASE) + + +/* + * Virtual view <-> DMA view memory address translations + * virt_to_bus: Used to translate the virtual address to an + * address suitable to be passed to set_dma_addr + * bus_to_virt: Used to convert an address for DMA operations + * to an address that the kernel can use. + */ +#define __virt_to_bus(x) __virt_to_phys(x) +#define __bus_to_virt(x) __phys_to_virt(x) + +#endif diff --git a/include/asm-arm/arch-at91/system.h b/include/asm-arm/arch-at91/system.h new file mode 100644 index 000000000000..6bf846098ea9 --- /dev/null +++ b/include/asm-arm/arch-at91/system.h @@ -0,0 +1,53 @@ +/* + * include/asm-arm/arch-at91/system.h + * + * Copyright (C) 2003 SAN People + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +#include +#include +#include + +static inline void arch_idle(void) +{ + /* + * Disable the processor clock. The processor will be automatically + * re-enabled by an interrupt or by a reset. + */ +// at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK); + + /* + * Set the processor (CP15) into 'Wait for Interrupt' mode. + * Unlike disabling the processor clock via the PMC (above) + * this allows the processor to be woken via JTAG. + */ + cpu_do_idle(); +} + +void (*at91_arch_reset)(void); + +static inline void arch_reset(char mode) +{ + /* call the CPU-specific reset function */ + if (at91_arch_reset) + (at91_arch_reset)(); +} + +#endif diff --git a/include/asm-arm/arch-at91/timex.h b/include/asm-arm/arch-at91/timex.h new file mode 100644 index 000000000000..b24e364997e1 --- /dev/null +++ b/include/asm-arm/arch-at91/timex.h @@ -0,0 +1,37 @@ +/* + * include/asm-arm/arch-at91/timex.h + * + * Copyright (C) 2003 SAN People + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_TIMEX_H +#define __ASM_ARCH_TIMEX_H + +#include + +#if defined(CONFIG_ARCH_AT91RM9200) + +#define CLOCK_TICK_RATE (AT91_SLOW_CLOCK) + +#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9261) + +#define AT91SAM9_MASTER_CLOCK 99300000 +#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) + +#endif + +#endif diff --git a/include/asm-arm/arch-at91/uncompress.h b/include/asm-arm/arch-at91/uncompress.h new file mode 100644 index 000000000000..a193d28304b6 --- /dev/null +++ b/include/asm-arm/arch-at91/uncompress.h @@ -0,0 +1,56 @@ +/* + * include/asm-arm/arch-at91/uncompress.h + * + * Copyright (C) 2003 SAN People + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_UNCOMPRESS_H +#define __ASM_ARCH_UNCOMPRESS_H + +#include +#include + +/* + * The following code assumes the serial port has already been + * initialized by the bootloader. If you didn't setup a port in + * your bootloader then nothing will appear (which might be desired). + * + * This does not append a newline + */ +static void putc(int c) +{ + void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ + + while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY)) + barrier(); + __raw_writel(c, sys + AT91_DBGU_THR); +} + +static inline void flush(void) +{ + void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ + + /* wait for transmission to complete */ + while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXEMPTY)) + barrier(); +} + +#define arch_decomp_setup() + +#define arch_decomp_wdog() + +#endif diff --git a/include/asm-arm/arch-at91/vmalloc.h b/include/asm-arm/arch-at91/vmalloc.h new file mode 100644 index 000000000000..bb05e70e932a --- /dev/null +++ b/include/asm-arm/arch-at91/vmalloc.h @@ -0,0 +1,26 @@ +/* + * include/asm-arm/arch-at91/vmalloc.h + * + * Copyright (C) 2003 SAN People + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_VMALLOC_H +#define __ASM_ARCH_VMALLOC_H + +#define VMALLOC_END (AT91_VIRT_BASE & PGDIR_MASK) + +#endif diff --git a/include/asm-arm/arch-at91rm9200/at91_aic.h b/include/asm-arm/arch-at91rm9200/at91_aic.h deleted file mode 100644 index 267e69812e26..000000000000 --- a/include/asm-arm/arch-at91rm9200/at91_aic.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/at91_aic.h - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * Advanced Interrupt Controller (AIC) - System peripherals registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_AIC_H -#define AT91_AIC_H - -#define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */ -#define AT91_AIC_PRIOR (7 << 0) /* Priority Level */ -#define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */ -#define AT91_AIC_SRCTYPE_LOW (0 << 5) -#define AT91_AIC_SRCTYPE_FALLING (1 << 5) -#define AT91_AIC_SRCTYPE_HIGH (2 << 5) -#define AT91_AIC_SRCTYPE_RISING (3 << 5) - -#define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */ -#define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */ -#define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */ -#define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */ -#define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */ - -#define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */ -#define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */ -#define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */ -#define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */ -#define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */ - -#define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */ -#define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */ -#define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */ -#define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */ -#define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */ -#define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */ -#define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */ -#define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */ -#define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */ - -#define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */ -#define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */ -#define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */ - -#endif diff --git a/include/asm-arm/arch-at91rm9200/at91_dbgu.h b/include/asm-arm/arch-at91rm9200/at91_dbgu.h deleted file mode 100644 index e4b8b27acfca..000000000000 --- a/include/asm-arm/arch-at91rm9200/at91_dbgu.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/at91_dbgu.h - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * Debug Unit (DBGU) - System peripherals registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_DBGU_H -#define AT91_DBGU_H - -#define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */ -#define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */ -#define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */ -#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */ -#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */ -#define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable Register */ -#define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask Register */ -#define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */ -#define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding Register */ -#define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding Register */ -#define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator Register */ - -#define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */ -#define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */ -#define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */ -#define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */ -#define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */ -#define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */ -#define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */ -#define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */ -#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */ -#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */ - -#define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */ -#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */ - -#endif diff --git a/include/asm-arm/arch-at91rm9200/at91_ecc.h b/include/asm-arm/arch-at91rm9200/at91_ecc.h deleted file mode 100644 index 5c564ede5c5d..000000000000 --- a/include/asm-arm/arch-at91rm9200/at91_ecc.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/at91_ecc.h - * - * Error Corrected Code Controller (ECC) - System peripherals regsters. - * Based on AT91SAM9260 datasheet revision B. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef AT91_ECC_H -#define AT91_ECC_H - -#define AT91_ECC_CR (AT91_ECC + 0x00) /* Control register */ -#define AT91_ECC_RST (1 << 0) /* Reset parity */ - -#define AT91_ECC_MR (AT91_ECC + 0x04) /* Mode register */ -#define AT91_ECC_PAGESIZE (3 << 0) /* Page Size */ -#define AT91_ECC_PAGESIZE_528 (0) -#define AT91_ECC_PAGESIZE_1056 (1) -#define AT91_ECC_PAGESIZE_2112 (2) -#define AT91_ECC_PAGESIZE_4224 (3) - -#define AT91_ECC_SR (AT91_ECC + 0x08) /* Status register */ -#define AT91_ECC_RECERR (1 << 0) /* Recoverable Error */ -#define AT91_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */ -#define AT91_ECC_MULERR (1 << 2) /* Multiple Errors */ - -#define AT91_ECC_PR (AT91_ECC + 0x0c) /* Parity register */ -#define AT91_ECC_BITADDR (0xf << 0) /* Bit Error Address */ -#define AT91_ECC_WORDADDR (0xfff << 4) /* Word Error Address */ - -#define AT91_ECC_NPR (AT91_ECC + 0x10) /* NParity register */ -#define AT91_ECC_NPARITY (0xffff << 0) /* NParity */ - -#endif diff --git a/include/asm-arm/arch-at91rm9200/at91_lcdc.h b/include/asm-arm/arch-at91rm9200/at91_lcdc.h deleted file mode 100644 index 9cbfcdd3c471..000000000000 --- a/include/asm-arm/arch-at91rm9200/at91_lcdc.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/at91_lcdc.h - * - * LCD Controller (LCDC). - * Based on AT91SAM9261 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_LCDC_H -#define AT91_LCDC_H - -#define AT91_LCDC_DMABADDR1 0x00 /* DMA Base Address Register 1 */ -#define AT91_LCDC_DMABADDR2 0x04 /* DMA Base Address Register 2 */ -#define AT91_LCDC_DMAFRMPT1 0x08 /* DMA Frame Pointer Register 1 */ -#define AT91_LCDC_DMAFRMPT2 0x0c /* DMA Frame Pointer Register 2 */ -#define AT91_LCDC_DMAFRMADD1 0x10 /* DMA Frame Address Register 1 */ -#define AT91_LCDC_DMAFRMADD2 0x14 /* DMA Frame Address Register 2 */ - -#define AT91_LCDC_DMAFRMCFG 0x18 /* DMA Frame Configuration Register */ -#define AT91_LCDC_FRSIZE (0x7fffff << 0) /* Frame Size */ -#define AT91_LCDC_BLENGTH (0x7f << 24) /* Burst Length */ - -#define AT91_LCDC_DMACON 0x1c /* DMA Control Register */ -#define AT91_LCDC_DMAEN (0x1 << 0) /* DMA Enable */ -#define AT91_LCDC_DMARST (0x1 << 1) /* DMA Reset */ -#define AT91_LCDC_DMABUSY (0x1 << 2) /* DMA Busy */ - -#define AT91_LCDC_LCDCON1 0x0800 /* LCD Control Register 1 */ -#define AT91_LCDC_BYPASS (1 << 0) /* Bypass lcd_dotck divider */ -#define AT91_LCDC_CLKVAL (0x1ff << 12) /* Clock Divider */ -#define AT91_LCDC_LINCNT (0x7ff << 21) /* Line Counter */ - -#define AT91_LCDC_LCDCON2 0x0804 /* LCD Control Register 2 */ -#define AT91_LCDC_DISTYPE (3 << 0) /* Display Type */ -#define AT91_LCDC_DISTYPE_STNMONO (0 << 0) -#define AT91_LCDC_DISTYPE_STNCOLOR (1 << 0) -#define AT91_LCDC_DISTYPE_TFT (2 << 0) -#define AT91_LCDC_SCANMOD (1 << 2) /* Scan Mode */ -#define AT91_LCDC_SCANMOD_SINGLE (0 << 2) -#define AT91_LCDC_SCANMOD_DUAL (1 << 2) -#define AT91_LCDC_IFWIDTH (3 << 3) /*Interface Width */ -#define AT91_LCDC_IFWIDTH_4 (0 << 3) -#define AT91_LCDC_IFWIDTH_8 (1 << 3) -#define AT91_LCDC_IFWIDTH_16 (2 << 3) -#define AT91_LCDC_PIXELSIZE (7 << 5) /* Bits per pixel */ -#define AT91_LCDC_PIXELSIZE_1 (0 << 5) -#define AT91_LCDC_PIXELSIZE_2 (1 << 5) -#define AT91_LCDC_PIXELSIZE_4 (2 << 5) -#define AT91_LCDC_PIXELSIZE_8 (3 << 5) -#define AT91_LCDC_PIXELSIZE_16 (4 << 5) -#define AT91_LCDC_PIXELSIZE_24 (5 << 5) -#define AT91_LCDC_INVVD (1 << 8) /* LCD Data polarity */ -#define AT91_LCDC_INVVD_NORMAL (0 << 8) -#define AT91_LCDC_INVVD_INVERTED (1 << 8) -#define AT91_LCDC_INVFRAME (1 << 9 ) /* LCD VSync polarity */ -#define AT91_LCDC_INVFRAME_NORMAL (0 << 9) -#define AT91_LCDC_INVFRAME_INVERTED (1 << 9) -#define AT91_LCDC_INVLINE (1 << 10) /* LCD HSync polarity */ -#define AT91_LCDC_INVLINE_NORMAL (0 << 10) -#define AT91_LCDC_INVLINE_INVERTED (1 << 10) -#define AT91_LCDC_INVCLK (1 << 11) /* LCD dotclk polarity */ -#define AT91_LCDC_INVCLK_NORMAL (0 << 11) -#define AT91_LCDC_INVCLK_INVERTED (1 << 11) -#define AT91_LCDC_INVDVAL (1 << 12) /* LCD dval polarity */ -#define AT91_LCDC_INVDVAL_NORMAL (0 << 12) -#define AT91_LCDC_INVDVAL_INVERTED (1 << 12) -#define AT91_LCDC_CLKMOD (1 << 15) /* LCD dotclk mode */ -#define AT91_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15) -#define AT91_LCDC_CLKMOD_ALWAYSACTIVE (1 << 15) -#define AT91_LCDC_MEMOR (1 << 31) /* Memory Ordering Format */ -#define AT91_LCDC_MEMOR_BIG (0 << 31) -#define AT91_LCDC_MEMOR_LITTLE (1 << 31) - -#define AT91_LCDC_TIM1 0x0808 /* LCD Timing Register 1 */ -#define AT91_LCDC_VFP (0xff << 0) /* Vertical Front Porch */ -#define AT91_LCDC_VBP (0xff << 8) /* Vertical Back Porch */ -#define AT91_LCDC_VPW (0x3f << 16) /* Vertical Synchronization Pulse Width */ -#define AT91_LCDC_VHDLY (0xf << 24) /* Vertical to Horizontal Delay */ - -#define AT91_LCDC_TIM2 0x080c /* LCD Timing Register 2 */ -#define AT91_LCDC_HBP (0xff << 0) /* Horizontal Back Porch */ -#define AT91_LCDC_HPW (0x3f << 8) /* Horizontal Synchronization Pulse Width */ -#define AT91_LCDC_HFP (0x7ff << 21) /* Horizontal Front Porch */ - -#define AT91_LCDC_LCDFRMCFG 0x0810 /* LCD Frame Configuration Register */ -#define AT91_LCDC_LINEVAL (0x7ff << 0) /* Vertical Size of LCD Module */ -#define AT91_LCDC_HOZVAL (0x7ff << 21) /* Horizontal Size of LCD Module */ - -#define AT91_LCDC_FIFO 0x0814 /* LCD FIFO Register */ -#define AT91_LCDC_FIFOTH (0xffff) /* FIFO Threshold */ - -#define AT91_LCDC_DP1_2 0x081c /* Dithering Pattern DP1_2 Register */ -#define AT91_LCDC_DP4_7 0x0820 /* Dithering Pattern DP4_7 Register */ -#define AT91_LCDC_DP3_5 0x0824 /* Dithering Pattern DP3_5 Register */ -#define AT91_LCDC_DP2_3 0x0828 /* Dithering Pattern DP2_3 Register */ -#define AT91_LCDC_DP5_7 0x082c /* Dithering Pattern DP5_7 Register */ -#define AT91_LCDC_DP3_4 0x0830 /* Dithering Pattern DP3_4 Register */ -#define AT91_LCDC_DP4_5 0x0834 /* Dithering Pattern DP4_5 Register */ -#define AT91_LCDC_DP6_7 0x0838 /* Dithering Pattern DP6_7 Register */ -#define AT91_LCDC_DP1_2_VAL (0xff) -#define AT91_LCDC_DP4_7_VAL (0xfffffff) -#define AT91_LCDC_DP3_5_VAL (0xfffff) -#define AT91_LCDC_DP2_3_VAL (0xfff) -#define AT91_LCDC_DP5_7_VAL (0xfffffff) -#define AT91_LCDC_DP3_4_VAL (0xffff) -#define AT91_LCDC_DP4_5_VAL (0xfffff) -#define AT91_LCDC_DP6_7_VAL (0xfffffff) - -#define AT91_LCDC_PWRCON 0x083c /* Power Control Register */ -#define AT91_LCDC_PWR (1 << 0) /* LCD Module Power Control */ -#define AT91_LCDC_GUARDT (0x7f << 1) /* Delay in Frame Period */ -#define AT91_LCDC_BUSY (1 << 31) /* LCD Busy */ - -#define AT91_LCDC_CONTRAST_CTR 0x0840 /* Contrast Control Register */ -#define AT91_LCDC_PS (3 << 0) /* Contrast Counter Prescaler */ -#define AT91_LCDC_PS_DIV1 (0 << 0) -#define AT91_LCDC_PS_DIV2 (1 << 0) -#define AT91_LCDC_PS_DIV4 (2 << 0) -#define AT91_LCDC_PS_DIV8 (3 << 0) -#define AT91_LCDC_POL (1 << 2) /* Polarity of output Pulse */ -#define AT91_LCDC_POL_NEGATIVE (0 << 2) -#define AT91_LCDC_POL_POSITIVE (1 << 2) -#define AT91_LCDC_ENA (1 << 3) /* PWM generator Control */ -#define AT91_LCDC_ENA_PWMDISABLE (0 << 3) -#define AT91_LCDC_ENA_PWMENABLE (1 << 3) - -#define AT91_LCDC_CONTRAST_VAL 0x0844 /* Contrast Value Register */ -#define AT91_LCDC_CVAL (0xff) /* PWM compare value */ - -#define AT91_LCDC_IER 0x0848 /* Interrupt Enable Register */ -#define AT91_LCDC_IDR 0x084c /* Interrupt Disable Register */ -#define AT91_LCDC_IMR 0x0850 /* Interrupt Mask Register */ -#define AT91_LCDC_ISR 0x0854 /* Interrupt Enable Register */ -#define AT91_LCDC_ICR 0x0858 /* Interrupt Clear Register */ -#define AT91_LCDC_LNI (1 << 0) /* Line Interrupt */ -#define AT91_LCDC_LSTLNI (1 << 1) /* Last Line Interrupt */ -#define AT91_LCDC_EOFI (1 << 2) /* DMA End Of Frame Interrupt */ -#define AT91_LCDC_UFLWI (1 << 4) /* FIFO Underflow Interrupt */ -#define AT91_LCDC_OWRI (1 << 5) /* FIFO Overwrite Interrupt */ -#define AT91_LCDC_MERI (1 << 6) /* DMA Memory Error Interrupt */ - -#define AT91_LCDC_LUT_(n) (0x0c00 + ((n)*4)) /* Palette Entry 0..255 */ - -#endif diff --git a/include/asm-arm/arch-at91rm9200/at91_mci.h b/include/asm-arm/arch-at91rm9200/at91_mci.h deleted file mode 100644 index 9a552cb743c0..000000000000 --- a/include/asm-arm/arch-at91rm9200/at91_mci.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/at91_mci.h - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * MultiMedia Card Interface (MCI) registers. - * Based on AT91RM9200 datasheet revision F. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_MCI_H -#define AT91_MCI_H - -#define AT91_MCI_CR 0x00 /* Control Register */ -#define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */ -#define AT91_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */ -#define AT91_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */ -#define AT91_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */ -#define AT91_MCI_SWRST (1 << 7) /* Software Reset */ - -#define AT91_MCI_MR 0x04 /* Mode Register */ -#define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */ -#define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */ -#define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ -#define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ -#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ - -#define AT91_MCI_DTOR 0x08 /* Data Timeout Register */ -#define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */ -#define AT91_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */ -#define AT91_MCI_DTOMUL_1 (0 << 4) -#define AT91_MCI_DTOMUL_16 (1 << 4) -#define AT91_MCI_DTOMUL_128 (2 << 4) -#define AT91_MCI_DTOMUL_256 (3 << 4) -#define AT91_MCI_DTOMUL_1K (4 << 4) -#define AT91_MCI_DTOMUL_4K (5 << 4) -#define AT91_MCI_DTOMUL_64K (6 << 4) -#define AT91_MCI_DTOMUL_1M (7 << 4) - -#define AT91_MCI_SDCR 0x0c /* SD Card Register */ -#define AT91_MCI_SDCSEL (3 << 0) /* SD Card Selector */ -#define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */ - -#define AT91_MCI_ARGR 0x10 /* Argument Register */ - -#define AT91_MCI_CMDR 0x14 /* Command Register */ -#define AT91_MCI_CMDNB (0x3f << 0) /* Command Number */ -#define AT91_MCI_RSPTYP (3 << 6) /* Response Type */ -#define AT91_MCI_RSPTYP_NONE (0 << 6) -#define AT91_MCI_RSPTYP_48 (1 << 6) -#define AT91_MCI_RSPTYP_136 (2 << 6) -#define AT91_MCI_SPCMD (7 << 8) /* Special Command */ -#define AT91_MCI_SPCMD_NONE (0 << 8) -#define AT91_MCI_SPCMD_INIT (1 << 8) -#define AT91_MCI_SPCMD_SYNC (2 << 8) -#define AT91_MCI_SPCMD_ICMD (4 << 8) -#define AT91_MCI_SPCMD_IRESP (5 << 8) -#define AT91_MCI_OPDCMD (1 << 11) /* Open Drain Command */ -#define AT91_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */ -#define AT91_MCI_TRCMD (3 << 16) /* Transfer Command */ -#define AT91_MCI_TRCMD_NONE (0 << 16) -#define AT91_MCI_TRCMD_START (1 << 16) -#define AT91_MCI_TRCMD_STOP (2 << 16) -#define AT91_MCI_TRDIR (1 << 18) /* Transfer Direction */ -#define AT91_MCI_TRTYP (3 << 19) /* Transfer Type */ -#define AT91_MCI_TRTYP_BLOCK (0 << 19) -#define AT91_MCI_TRTYP_MULTIPLE (1 << 19) -#define AT91_MCI_TRTYP_STREAM (2 << 19) - -#define AT91_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */ -#define AT91_MCR_RDR 0x30 /* Receive Data Register */ -#define AT91_MCR_TDR 0x34 /* Transmit Data Register */ - -#define AT91_MCI_SR 0x40 /* Status Register */ -#define AT91_MCI_CMDRDY (1 << 0) /* Command Ready */ -#define AT91_MCI_RXRDY (1 << 1) /* Receiver Ready */ -#define AT91_MCI_TXRDY (1 << 2) /* Transmit Ready */ -#define AT91_MCI_BLKE (1 << 3) /* Data Block Ended */ -#define AT91_MCI_DTIP (1 << 4) /* Data Transfer in Progress */ -#define AT91_MCI_NOTBUSY (1 << 5) /* Data Not Busy */ -#define AT91_MCI_ENDRX (1 << 6) /* End of RX Buffer */ -#define AT91_MCI_ENDTX (1 << 7) /* End fo TX Buffer */ -#define AT91_MCI_SDIOIRQA (1 << 8) /* SDIO Interrupt for Slot A */ -#define At91_MCI_SDIOIRQB (1 << 9) /* SDIO Interrupt for Slot B [AT91RM9200 only] */ -#define AT91_MCI_RXBUFF (1 << 14) /* RX Buffer Full */ -#define AT91_MCI_TXBUFE (1 << 15) /* TX Buffer Empty */ -#define AT91_MCI_RINDE (1 << 16) /* Response Index Error */ -#define AT91_MCI_RDIRE (1 << 17) /* Response Direction Error */ -#define AT91_MCI_RCRCE (1 << 18) /* Response CRC Error */ -#define AT91_MCI_RENDE (1 << 19) /* Response End Bit Error */ -#define AT91_MCI_RTOE (1 << 20) /* Reponse Time-out Error */ -#define AT91_MCI_DCRCE (1 << 21) /* Data CRC Error */ -#define AT91_MCI_DTOE (1 << 22) /* Data Time-out Error */ -#define AT91_MCI_OVRE (1 << 30) /* Overrun */ -#define AT91_MCI_UNRE (1 << 31) /* Underrun */ - -#define AT91_MCI_IER 0x44 /* Interrupt Enable Register */ -#define AT91_MCI_IDR 0x48 /* Interrupt Disable Register */ -#define AT91_MCI_IMR 0x4c /* Interrupt Mask Register */ - -#endif diff --git a/include/asm-arm/arch-at91rm9200/at91_pdc.h b/include/asm-arm/arch-at91rm9200/at91_pdc.h deleted file mode 100644 index 79d6e02fa45e..000000000000 --- a/include/asm-arm/arch-at91rm9200/at91_pdc.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/at91_pdc.h - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * Peripheral Data Controller (PDC) registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_PDC_H -#define AT91_PDC_H - -#define AT91_PDC_RPR 0x100 /* Receive Pointer Register */ -#define AT91_PDC_RCR 0x104 /* Receive Counter Register */ -#define AT91_PDC_TPR 0x108 /* Transmit Pointer Register */ -#define AT91_PDC_TCR 0x10c /* Transmit Counter Register */ -#define AT91_PDC_RNPR 0x110 /* Receive Next Pointer Register */ -#define AT91_PDC_RNCR 0x114 /* Receive Next Counter Register */ -#define AT91_PDC_TNPR 0x118 /* Transmit Next Pointer Register */ -#define AT91_PDC_TNCR 0x11c /* Transmit Next Counter Register */ - -#define AT91_PDC_PTCR 0x120 /* Transfer Control Register */ -#define AT91_PDC_RXTEN (1 << 0) /* Receiver Transfer Enable */ -#define AT91_PDC_RXTDIS (1 << 1) /* Receiver Transfer Disable */ -#define AT91_PDC_TXTEN (1 << 8) /* Transmitter Transfer Enable */ -#define AT91_PDC_TXTDIS (1 << 9) /* Transmitter Transfer Disable */ - -#define AT91_PDC_PTSR 0x124 /* Transfer Status Register */ - -#endif diff --git a/include/asm-arm/arch-at91rm9200/at91_pio.h b/include/asm-arm/arch-at91rm9200/at91_pio.h deleted file mode 100644 index 680eaa1f5915..000000000000 --- a/include/asm-arm/arch-at91rm9200/at91_pio.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/at91_pio.h - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * Parallel I/O Controller (PIO) - System peripherals registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_PIO_H -#define AT91_PIO_H - -#define PIO_PER 0x00 /* Enable Register */ -#define PIO_PDR 0x04 /* Disable Register */ -#define PIO_PSR 0x08 /* Status Register */ -#define PIO_OER 0x10 /* Output Enable Register */ -#define PIO_ODR 0x14 /* Output Disable Register */ -#define PIO_OSR 0x18 /* Output Status Register */ -#define PIO_IFER 0x20 /* Glitch Input Filter Enable */ -#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */ -#define PIO_IFSR 0x28 /* Glitch Input Filter Status */ -#define PIO_SODR 0x30 /* Set Output Data Register */ -#define PIO_CODR 0x34 /* Clear Output Data Register */ -#define PIO_ODSR 0x38 /* Output Data Status Register */ -#define PIO_PDSR 0x3c /* Pin Data Status Register */ -#define PIO_IER 0x40 /* Interrupt Enable Register */ -#define PIO_IDR 0x44 /* Interrupt Disable Register */ -#define PIO_IMR 0x48 /* Interrupt Mask Register */ -#define PIO_ISR 0x4c /* Interrupt Status Register */ -#define PIO_MDER 0x50 /* Multi-driver Enable Register */ -#define PIO_MDDR 0x54 /* Multi-driver Disable Register */ -#define PIO_MDSR 0x58 /* Multi-driver Status Register */ -#define PIO_PUDR 0x60 /* Pull-up Disable Register */ -#define PIO_PUER 0x64 /* Pull-up Enable Register */ -#define PIO_PUSR 0x68 /* Pull-up Status Register */ -#define PIO_ASR 0x70 /* Peripheral A Select Register */ -#define PIO_BSR 0x74 /* Peripheral B Select Register */ -#define PIO_ABSR 0x78 /* AB Status Register */ -#define PIO_OWER 0xa0 /* Output Write Enable Register */ -#define PIO_OWDR 0xa4 /* Output Write Disable Register */ -#define PIO_OWSR 0xa8 /* Output Write Status Register */ - -#endif diff --git a/include/asm-arm/arch-at91rm9200/at91_pit.h b/include/asm-arm/arch-at91rm9200/at91_pit.h deleted file mode 100644 index 4a30d009c588..000000000000 --- a/include/asm-arm/arch-at91rm9200/at91_pit.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/at91_pit.h - * - * Periodic Interval Timer (PIT) - System peripherals regsters. - * Based on AT91SAM9261 datasheet revision D. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_PIT_H -#define AT91_PIT_H - -#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */ -#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */ -#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */ -#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */ - -#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */ -#define AT91_PIT_PITS (1 << 0) /* Timer Status */ - -#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */ -#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */ -#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */ -#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */ - -#endif diff --git a/include/asm-arm/arch-at91rm9200/at91_pmc.h b/include/asm-arm/arch-at91rm9200/at91_pmc.h deleted file mode 100644 index c3b489d09b6c..000000000000 --- a/include/asm-arm/arch-at91rm9200/at91_pmc.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/at91_pmc.h - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * Power Management Controller (PMC) - System peripherals registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_PMC_H -#define AT91_PMC_H - -#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ -#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ - -#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */ -#define AT91_PMC_PCK (1 << 0) /* Processor Clock */ -#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ -#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ -#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ -#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ -#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ -#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ -#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ -#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ -#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ -#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ -#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ - -#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */ -#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ -#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ - -#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register */ -#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ -#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */ -#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ - -#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ -#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ -#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ - -#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */ -#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */ -#define AT91_PMC_DIV (0xff << 0) /* Divider */ -#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ -#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ -#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ -#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ - -#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ -#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ -#define AT91_PMC_CSS_SLOW (0 << 0) -#define AT91_PMC_CSS_MAIN (1 << 0) -#define AT91_PMC_CSS_PLLA (2 << 0) -#define AT91_PMC_CSS_PLLB (3 << 0) -#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ -#define AT91_PMC_PRES_1 (0 << 2) -#define AT91_PMC_PRES_2 (1 << 2) -#define AT91_PMC_PRES_4 (2 << 2) -#define AT91_PMC_PRES_8 (3 << 2) -#define AT91_PMC_PRES_16 (4 << 2) -#define AT91_PMC_PRES_32 (5 << 2) -#define AT91_PMC_PRES_64 (6 << 2) -#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ -#define AT91_PMC_MDIV_1 (0 << 8) -#define AT91_PMC_MDIV_2 (1 << 8) -#define AT91_PMC_MDIV_3 (2 << 8) -#define AT91_PMC_MDIV_4 (3 << 8) - -#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ - -#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ -#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ -#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ -#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ -#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ -#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ -#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ -#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ -#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ -#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ -#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ -#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ - -#endif diff --git a/include/asm-arm/arch-at91rm9200/at91_rstc.h b/include/asm-arm/arch-at91rm9200/at91_rstc.h deleted file mode 100644 index 237d3c40b318..000000000000 --- a/include/asm-arm/arch-at91rm9200/at91_rstc.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/at91_rstc.h - * - * Reset Controller (RSTC) - System peripherals regsters. - * Based on AT91SAM9261 datasheet revision D. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_RSTC_H -#define AT91_RSTC_H - -#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */ -#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ -#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ -#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ -#define AT91_RSTC_KEY (0xff << 24) /* KEY Password */ - -#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */ -#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ -#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ -#define AT91_RSTC_RSTTYP_GENERAL (0 << 8) -#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8) -#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8) -#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8) -#define AT91_RSTC_RSTTYP_USER (4 << 8) -#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */ -#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */ - -#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */ -#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */ -#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ -#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */ -#define AT91_RSTC_KEY (0xff << 24) /* KEY Password */ - -#endif diff --git a/include/asm-arm/arch-at91rm9200/at91_rtc.h b/include/asm-arm/arch-at91rm9200/at91_rtc.h deleted file mode 100644 index 095fe0883102..000000000000 --- a/include/asm-arm/arch-at91rm9200/at91_rtc.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/at91_rtc.h - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * Real Time Clock (RTC) - System peripheral registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_RTC_H -#define AT91_RTC_H - -#define AT91_RTC_CR (AT91_RTC + 0x00) /* Control Register */ -#define AT91_RTC_UPDTIM (1 << 0) /* Update Request Time Register */ -#define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */ -#define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */ -#define AT91_RTC_TIMEVSEL_MINUTE (0 << 8) -#define AT91_RTC_TIMEVSEL_HOUR (1 << 8) -#define AT91_RTC_TIMEVSEL_DAY24 (2 << 8) -#define AT91_RTC_TIMEVSEL_DAY12 (3 << 8) -#define AT91_RTC_CALEVSEL (3 << 16) /* Calendar Event Selection */ -#define AT91_RTC_CALEVSEL_WEEK (0 << 16) -#define AT91_RTC_CALEVSEL_MONTH (1 << 16) -#define AT91_RTC_CALEVSEL_YEAR (2 << 16) - -#define AT91_RTC_MR (AT91_RTC + 0x04) /* Mode Register */ -#define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */ - -#define AT91_RTC_TIMR (AT91_RTC + 0x08) /* Time Register */ -#define AT91_RTC_SEC (0x7f << 0) /* Current Second */ -#define AT91_RTC_MIN (0x7f << 8) /* Current Minute */ -#define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */ -#define AT91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */ - -#define AT91_RTC_CALR (AT91_RTC + 0x0c) /* Calendar Register */ -#define AT91_RTC_CENT (0x7f << 0) /* Current Century */ -#define AT91_RTC_YEAR (0xff << 8) /* Current Year */ -#define AT91_RTC_MONTH (0x1f << 16) /* Current Month */ -#define AT91_RTC_DAY (7 << 21) /* Current Day */ -#define AT91_RTC_DATE (0x3f << 24) /* Current Date */ - -#define AT91_RTC_TIMALR (AT91_RTC + 0x10) /* Time Alarm Register */ -#define AT91_RTC_SECEN (1 << 7) /* Second Alarm Enable */ -#define AT91_RTC_MINEN (1 << 15) /* Minute Alarm Enable */ -#define AT91_RTC_HOUREN (1 << 23) /* Hour Alarm Enable */ - -#define AT91_RTC_CALALR (AT91_RTC + 0x14) /* Calendar Alarm Register */ -#define AT91_RTC_MTHEN (1 << 23) /* Month Alarm Enable */ -#define AT91_RTC_DATEEN (1 << 31) /* Date Alarm Enable */ - -#define AT91_RTC_SR (AT91_RTC + 0x18) /* Status Register */ -#define AT91_RTC_ACKUPD (1 << 0) /* Acknowledge for Update */ -#define AT91_RTC_ALARM (1 << 1) /* Alarm Flag */ -#define AT91_RTC_SECEV (1 << 2) /* Second Event */ -#define AT91_RTC_TIMEV (1 << 3) /* Time Event */ -#define AT91_RTC_CALEV (1 << 4) /* Calendar Event */ - -#define AT91_RTC_SCCR (AT91_RTC + 0x1c) /* Status Clear Command Register */ -#define AT91_RTC_IER (AT91_RTC + 0x20) /* Interrupt Enable Register */ -#define AT91_RTC_IDR (AT91_RTC + 0x24) /* Interrupt Disable Register */ -#define AT91_RTC_IMR (AT91_RTC + 0x28) /* Interrupt Mask Register */ - -#define AT91_RTC_VER (AT91_RTC + 0x2c) /* Valid Entry Register */ -#define AT91_RTC_NVTIM (1 << 0) /* Non valid Time */ -#define AT91_RTC_NVCAL (1 << 1) /* Non valid Calendar */ -#define AT91_RTC_NVTIMALR (1 << 2) /* Non valid Time Alarm */ -#define AT91_RTC_NVCALALR (1 << 3) /* Non valid Calendar Alarm */ - -#endif diff --git a/include/asm-arm/arch-at91rm9200/at91_rtt.h b/include/asm-arm/arch-at91rm9200/at91_rtt.h deleted file mode 100644 index c6751ba3cccc..000000000000 --- a/include/asm-arm/arch-at91rm9200/at91_rtt.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/at91_rtt.h - * - * Real-time Timer (RTT) - System peripherals regsters. - * Based on AT91SAM9261 datasheet revision D. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_RTT_H -#define AT91_RTT_H - -#define AT91_RTT_MR (AT91_RTT + 0x00) /* Real-time Mode Register */ -#define AT91_RTT_RTPRES (0xffff << 0) /* Real-time Timer Prescaler Value */ -#define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */ -#define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */ -#define AT91_RTT_RTTRST (1 << 18) /* Real Time Timer Restart */ - -#define AT91_RTT_AR (AT91_RTT + 0x04) /* Real-time Alarm Register */ -#define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */ - -#define AT91_RTT_VR (AT91_RTT + 0x08) /* Real-time Value Register */ -#define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */ - -#define AT91_RTT_SR (AT91_RTT + 0x0c) /* Real-time Status Register */ -#define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */ -#define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */ - -#endif diff --git a/include/asm-arm/arch-at91rm9200/at91_shdwc.h b/include/asm-arm/arch-at91rm9200/at91_shdwc.h deleted file mode 100644 index 0439250553c9..000000000000 --- a/include/asm-arm/arch-at91rm9200/at91_shdwc.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/at91_shdwc.h - * - * Shutdown Controller (SHDWC) - System peripherals regsters. - * Based on AT91SAM9261 datasheet revision D. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_SHDWC_H -#define AT91_SHDWC_H - -#define AT91_SHDW_CR (AT91_SHDWC + 0x00) /* Shut Down Control Register */ -#define AT91_SHDW_SHDW (1 << 0) /* Processor Reset */ -#define AT91_SHDW_KEY (0xff << 24) /* KEY Password */ - -#define AT91_SHDW_MR (AT91_SHDWC + 0x04) /* Shut Down Mode Register */ -#define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */ -#define AT91_SHDW_WKMODE0_NONE 0 -#define AT91_SHDW_WKMODE0_HIGH 1 -#define AT91_SHDW_WKMODE0_LOW 2 -#define AT91_SHDW_WKMODE0_ANYLEVEL 3 -#define AT91_SHDW_CPTWK0 (0xf << 4) /* Counter On Wake Up 0 */ -#define AT91_SHDW_RTTWKEN (1 << 16) /* Real Time Timer Wake-up Enable */ - -#define AT91_SHDW_SR (AT91_SHDWC + 0x08) /* Shut Down Status Register */ -#define AT91_SHDW_WAKEUP0 (1 << 0) /* Wake-up 0 Status */ -#define AT91_SHDW_RTTWK (1 << 16) /* Real-time Timer Wake-up */ - -#endif diff --git a/include/asm-arm/arch-at91rm9200/at91_spi.h b/include/asm-arm/arch-at91rm9200/at91_spi.h deleted file mode 100644 index bec48ca89bba..000000000000 --- a/include/asm-arm/arch-at91rm9200/at91_spi.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/at91_spi.h - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * Serial Peripheral Interface (SPI) registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_SPI_H -#define AT91_SPI_H - -#define AT91_SPI_CR 0x00 /* Control Register */ -#define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */ -#define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */ -#define AT91_SPI_SWRST (1 << 7) /* SPI Software Reset */ -#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */ - -#define AT91_SPI_MR 0x04 /* Mode Register */ -#define AT91_SPI_MSTR (1 << 0) /* Master/Slave Mode */ -#define AT91_SPI_PS (1 << 1) /* Peripheral Select */ -#define AT91_SPI_PS_FIXED (0 << 1) -#define AT91_SPI_PS_VARIABLE (1 << 1) -#define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */ -#define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */ -#define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */ -#define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */ -#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ -#define AT91_SPI_DLYBCS (0xff << 24) /* Delay Between Chip Selects */ - -#define AT91_SPI_RDR 0x08 /* Receive Data Register */ -#define AT91_SPI_RD (0xffff << 0) /* Receive Data */ -#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ - -#define AT91_SPI_TDR 0x0c /* Transmit Data Register */ -#define AT91_SPI_TD (0xffff << 0) /* Transmit Data */ -#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ -#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */ - -#define AT91_SPI_SR 0x10 /* Status Register */ -#define AT91_SPI_RDRF (1 << 0) /* Receive Data Register Full */ -#define AT91_SPI_TDRE (1 << 1) /* Transmit Data Register Full */ -#define AT91_SPI_MODF (1 << 2) /* Mode Fault Error */ -#define AT91_SPI_OVRES (1 << 3) /* Overrun Error Status */ -#define AT91_SPI_ENDRX (1 << 4) /* End of RX buffer */ -#define AT91_SPI_ENDTX (1 << 5) /* End of TX buffer */ -#define AT91_SPI_RXBUFF (1 << 6) /* RX Buffer Full */ -#define AT91_SPI_TXBUFE (1 << 7) /* TX Buffer Empty */ -#define AT91_SPI_NSSR (1 << 8) /* NSS Rising [SAM9261 only] */ -#define AT91_SPI_TXEMPTY (1 << 9) /* Transmission Register Empty [SAM9261 only] */ -#define AT91_SPI_SPIENS (1 << 16) /* SPI Enable Status */ - -#define AT91_SPI_IER 0x14 /* Interrupt Enable Register */ -#define AT91_SPI_IDR 0x18 /* Interrupt Disable Register */ -#define AT91_SPI_IMR 0x1c /* Interrupt Mask Register */ - -#define AT91_SPI_CSR(n) (0x30 + ((n) * 4)) /* Chip Select Registers 0-3 */ -#define AT91_SPI_CPOL (1 << 0) /* Clock Polarity */ -#define AT91_SPI_NCPHA (1 << 1) /* Clock Phase */ -#define AT91_SPI_CSAAT (1 << 3) /* Chip Select Active After Transfer [SAM9261 only] */ -#define AT91_SPI_BITS (0xf << 4) /* Bits Per Transfer */ -#define AT91_SPI_BITS_8 (0 << 4) -#define AT91_SPI_BITS_9 (1 << 4) -#define AT91_SPI_BITS_10 (2 << 4) -#define AT91_SPI_BITS_11 (3 << 4) -#define AT91_SPI_BITS_12 (4 << 4) -#define AT91_SPI_BITS_13 (5 << 4) -#define AT91_SPI_BITS_14 (6 << 4) -#define AT91_SPI_BITS_15 (7 << 4) -#define AT91_SPI_BITS_16 (8 << 4) -#define AT91_SPI_SCBR (0xff << 8) /* Serial Clock Baud Rate */ -#define AT91_SPI_DLYBS (0xff << 16) /* Delay before SPCK */ -#define AT91_SPI_DLYBCT (0xff << 24) /* Delay between Consecutive Transfers */ - -#endif diff --git a/include/asm-arm/arch-at91rm9200/at91_ssc.h b/include/asm-arm/arch-at91rm9200/at91_ssc.h deleted file mode 100644 index 694bcaa8f7c2..000000000000 --- a/include/asm-arm/arch-at91rm9200/at91_ssc.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/at91_ssc.h - * - * Copyright (C) SAN People - * - * Serial Synchronous Controller (SSC) registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_SSC_H -#define AT91_SSC_H - -#define AT91_SSC_CR 0x00 /* Control Register */ -#define AT91_SSC_RXEN (1 << 0) /* Receive Enable */ -#define AT91_SSC_RXDIS (1 << 1) /* Receive Disable */ -#define AT91_SSC_TXEN (1 << 8) /* Transmit Enable */ -#define AT91_SSC_TXDIS (1 << 9) /* Transmit Disable */ -#define AT91_SSC_SWRST (1 << 15) /* Software Reset */ - -#define AT91_SSC_CMR 0x04 /* Clock Mode Register */ -#define AT91_SSC_CMR_DIV (0xfff << 0) /* Clock Divider */ - -#define AT91_SSC_RCMR 0x10 /* Receive Clock Mode Register */ -#define AT91_SSC_CKS (3 << 0) /* Clock Selection */ -#define AT91_SSC_CKS_DIV (0 << 0) -#define AT91_SSC_CKS_CLOCK (1 << 0) -#define AT91_SSC_CKS_PIN (2 << 0) -#define AT91_SSC_CKO (7 << 2) /* Clock Output Mode Selection */ -#define AT91_SSC_CKO_NONE (0 << 2) -#define AT91_SSC_CKO_CONTINUOUS (1 << 2) -#define AT91_SSC_CKI (1 << 5) /* Clock Inversion */ -#define AT91_SSC_CKI_FALLING (0 << 5) -#define AT91_SSC_CK_RISING (1 << 5) -#define AT91_SSC_CKG (1 << 6) /* Receive Clock Gating Selection [AT91SAM9261 only] */ -#define AT91_SSC_CKG_NONE (0 << 6) -#define AT91_SSC_CKG_RFLOW (1 << 6) -#define AT91_SSC_CKG_RFHIGH (2 << 6) -#define AT91_SSC_START (0xf << 8) /* Start Selection */ -#define AT91_SSC_START_CONTINUOUS (0 << 8) -#define AT91_SSC_START_TX_RX (1 << 8) -#define AT91_SSC_START_LOW_RF (2 << 8) -#define AT91_SSC_START_HIGH_RF (3 << 8) -#define AT91_SSC_START_FALLING_RF (4 << 8) -#define AT91_SSC_START_RISING_RF (5 << 8) -#define AT91_SSC_START_LEVEL_RF (6 << 8) -#define AT91_SSC_START_EDGE_RF (7 << 8) -#define AT91_SSC_STOP (1 << 12) /* Receive Stop Selection [AT91SAM9261 only] */ -#define AT91_SSC_STTDLY (0xff << 16) /* Start Delay */ -#define AT91_SSC_PERIOD (0xff << 24) /* Period Divider Selection */ - -#define AT91_SSC_RFMR 0x14 /* Receive Frame Mode Register */ -#define AT91_SSC_DATALEN (0x1f << 0) /* Data Length */ -#define AT91_SSC_LOOP (1 << 5) /* Loop Mode */ -#define AT91_SSC_MSBF (1 << 7) /* Most Significant Bit First */ -#define AT91_SSC_DATNB (0xf << 8) /* Data Number per Frame */ -#define AT91_SSC_FSLEN (0xf << 16) /* Frame Sync Length */ -#define AT91_SSC_FSOS (7 << 20) /* Frame Sync Output Selection */ -#define AT91_SSC_FSOS_NONE (0 << 20) -#define AT91_SSC_FSOS_NEGATIVE (1 << 20) -#define AT91_SSC_FSOS_POSITIVE (2 << 20) -#define AT91_SSC_FSOS_LOW (3 << 20) -#define AT91_SSC_FSOS_HIGH (4 << 20) -#define AT91_SSC_FSOS_TOGGLE (5 << 20) -#define AT91_SSC_FSEDGE (1 << 24) /* Frame Sync Edge Detection */ -#define AT91_SSC_FSEDGE_POSITIVE (0 << 24) -#define AT91_SSC_FSEDGE_NEGATIVE (1 << 24) - -#define AT91_SSC_TCMR 0x18 /* Transmit Clock Mode Register */ -#define AT91_SSC_TFMR 0x1c /* Transmit Fram Mode Register */ -#define AT91_SSC_DATDEF (1 << 5) /* Data Default Value */ -#define AT91_SSC_FSDEN (1 << 23) /* Frame Sync Data Enable */ - -#define AT91_SSC_RHR 0x20 /* Receive Holding Register */ -#define AT91_SSC_THR 0x24 /* Transmit Holding Register */ -#define AT91_SSC_RSHR 0x30 /* Receive Sync Holding Register */ -#define AT91_SSC_TSHR 0x34 /* Transmit Sync Holding Register */ - -#define AT91_SSC_RC0R 0x38 /* Receive Compare 0 Register [AT91SAM9261 only] */ -#define AT91_SSC_RC1R 0x3c /* Receive Compare 1 Register [AT91SAM9261 only] */ - -#define AT91_SSC_SR 0x40 /* Status Register */ -#define AT91_SSC_TXRDY (1 << 0) /* Transmit Ready */ -#define AT91_SSC_TXEMPTY (1 << 1) /* Transmit Empty */ -#define AT91_SSC_ENDTX (1 << 2) /* End of Transmission */ -#define AT91_SSC_TXBUFE (1 << 3) /* Transmit Buffer Empty */ -#define AT91_SSC_RXRDY (1 << 4) /* Receive Ready */ -#define AT91_SSC_OVRUN (1 << 5) /* Receive Overrun */ -#define AT91_SSC_ENDRX (1 << 6) /* End of Reception */ -#define AT91_SSC_RXBUFF (1 << 7) /* Receive Buffer Full */ -#define AT91_SSC_CP0 (1 << 8) /* Compare 0 [AT91SAM9261 only] */ -#define AT91_SSC_CP1 (1 << 9) /* Compare 1 [AT91SAM9261 only] */ -#define AT91_SSC_TXSYN (1 << 10) /* Transmit Sync */ -#define AT91_SSC_RXSYN (1 << 11) /* Receive Sync */ -#define AT91_SSC_TXENA (1 << 16) /* Transmit Enable */ -#define AT91_SSC_RXENA (1 << 17) /* Receive Enable */ - -#define AT91_SSC_IER 0x44 /* Interrupt Enable Register */ -#define AT91_SSC_IDR 0x48 /* Interrupt Disable Register */ -#define AT91_SSC_IMR 0x4c /* Interrupt Mask Register */ - -#endif diff --git a/include/asm-arm/arch-at91rm9200/at91_st.h b/include/asm-arm/arch-at91rm9200/at91_st.h deleted file mode 100644 index 2432ddfc6c47..000000000000 --- a/include/asm-arm/arch-at91rm9200/at91_st.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/at91_st.h - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * System Timer (ST) - System peripherals registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_ST_H -#define AT91_ST_H - -#define AT91_ST_CR (AT91_ST + 0x00) /* Control Register */ -#define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */ - -#define AT91_ST_PIMR (AT91_ST + 0x04) /* Period Interval Mode Register */ -#define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */ - -#define AT91_ST_WDMR (AT91_ST + 0x08) /* Watchdog Mode Register */ -#define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */ -#define AT91_ST_RSTEN (1 << 16) /* Reset Enable */ -#define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */ - -#define AT91_ST_RTMR (AT91_ST + 0x0c) /* Real-time Mode Register */ -#define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */ - -#define AT91_ST_SR (AT91_ST + 0x10) /* Status Register */ -#define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */ -#define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */ -#define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */ -#define AT91_ST_ALMS (1 << 3) /* Alarm Status */ - -#define AT91_ST_IER (AT91_ST + 0x14) /* Interrupt Enable Register */ -#define AT91_ST_IDR (AT91_ST + 0x18) /* Interrupt Disable Register */ -#define AT91_ST_IMR (AT91_ST + 0x1c) /* Interrupt Mask Register */ - -#define AT91_ST_RTAR (AT91_ST + 0x20) /* Real-time Alarm Register */ -#define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */ - -#define AT91_ST_CRTR (AT91_ST + 0x24) /* Current Real-time Register */ -#define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */ - -#endif diff --git a/include/asm-arm/arch-at91rm9200/at91_tc.h b/include/asm-arm/arch-at91rm9200/at91_tc.h deleted file mode 100644 index 8d06eb078e1d..000000000000 --- a/include/asm-arm/arch-at91rm9200/at91_tc.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/at91_tc.h - * - * Copyright (C) SAN People - * - * Timer/Counter Unit (TC) registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_TC_H -#define AT91_TC_H - -#define AT91_TC_BCR 0xc0 /* TC Block Control Register */ -#define AT91_TC_SYNC (1 << 0) /* Synchro Command */ - -#define AT91_TC_BMR 0xc4 /* TC Block Mode Register */ -#define AT91_TC_TC0XC0S (3 << 0) /* External Clock Signal 0 Selection */ -#define AT91_TC_TC0XC0S_TCLK0 (0 << 0) -#define AT91_TC_TC0XC0S_NONE (1 << 0) -#define AT91_TC_TC0XC0S_TIOA1 (2 << 0) -#define AT91_TC_TC0XC0S_TIOA2 (3 << 0) -#define AT91_TC_TC1XC1S (3 << 2) /* External Clock Signal 1 Selection */ -#define AT91_TC_TC1XC1S_TCLK1 (0 << 2) -#define AT91_TC_TC1XC1S_NONE (1 << 2) -#define AT91_TC_TC1XC1S_TIOA0 (2 << 2) -#define AT91_TC_TC1XC1S_TIOA2 (3 << 2) -#define AT91_TC_TC2XC2S (3 << 4) /* External Clock Signal 2 Selection */ -#define AT91_TC_TC2XC2S_TCLK2 (0 << 4) -#define AT91_TC_TC2XC2S_NONE (1 << 4) -#define AT91_TC_TC2XC2S_TIOA0 (2 << 4) -#define AT91_TC_TC2XC2S_TIOA1 (3 << 4) - - -#define AT91_TC_CCR 0x00 /* Channel Control Register */ -#define AT91_TC_CLKEN (1 << 0) /* Counter Clock Enable Command */ -#define AT91_TC_CLKDIS (1 << 1) /* Counter CLock Disable Command */ -#define AT91_TC_SWTRG (1 << 2) /* Software Trigger Command */ - -#define AT91_TC_CMR 0x04 /* Channel Mode Register */ -#define AT91_TC_TCCLKS (7 << 0) /* Capture/Waveform Mode: Clock Selection */ -#define AT91_TC_TIMER_CLOCK1 (0 << 0) -#define AT91_TC_TIMER_CLOCK2 (1 << 0) -#define AT91_TC_TIMER_CLOCK3 (2 << 0) -#define AT91_TC_TIMER_CLOCK4 (3 << 0) -#define AT91_TC_TIMER_CLOCK5 (4 << 0) -#define AT91_TC_XC0 (5 << 0) -#define AT91_TC_XC1 (6 << 0) -#define AT91_TC_XC2 (7 << 0) -#define AT91_TC_CLKI (1 << 3) /* Capture/Waveform Mode: Clock Invert */ -#define AT91_TC_BURST (3 << 4) /* Capture/Waveform Mode: Burst Signal Selection */ -#define AT91_TC_LDBSTOP (1 << 6) /* Capture Mode: Counter Clock Stopped with TB Loading */ -#define AT91_TC_LDBDIS (1 << 7) /* Capture Mode: Counter Clock Disable with RB Loading */ -#define AT91_TC_ETRGEDG (3 << 8) /* Capture Mode: External Trigger Edge Selection */ -#define AT91_TC_ABETRG (1 << 10) /* Capture Mode: TIOA or TIOB External Trigger Selection */ -#define AT91_TC_CPCTRG (1 << 14) /* Capture Mode: RC Compare Trigger Enable */ -#define AT91_TC_WAVE (1 << 15) /* Capture/Waveform mode */ -#define AT91_TC_LDRA (3 << 16) /* Capture Mode: RA Loading Selection */ -#define AT91_TC_LDRB (3 << 18) /* Capture Mode: RB Loading Selection */ - -#define AT91_TC_CPCSTOP (1 << 6) /* Waveform Mode: Counter Clock Stopped with RC Compare */ -#define AT91_TC_CPCDIS (1 << 7) /* Waveform Mode: Counter Clock Disable with RC Compare */ -#define AT91_TC_EEVTEDG (3 << 8) /* Waveform Mode: External Event Edge Selection */ -#define AT91_TC_EEVTEDG_NONE (0 << 8) -#define AT91_TC_EEVTEDG_RISING (1 << 8) -#define AT91_TC_EEVTEDG_FALLING (2 << 8) -#define AT91_TC_EEVTEDG_BOTH (3 << 8) -#define AT91_TC_EEVT (3 << 10) /* Waveform Mode: External Event Selection */ -#define AT91_TC_EEVT_TIOB (0 << 10) -#define AT91_TC_EEVT_XC0 (1 << 10) -#define AT91_TC_EEVT_XC1 (2 << 10) -#define AT91_TC_EEVT_XC2 (3 << 10) -#define AT91_TC_ENETRG (1 << 12) /* Waveform Mode: External Event Trigger Enable */ -#define AT91_TC_WAVESEL (3 << 13) /* Waveform Mode: Waveform Selection */ -#define AT91_TC_WAVESEL_UP (0 << 13) -#define AT91_TC_WAVESEL_UP_AUTO (2 << 13) -#define AT91_TC_WAVESEL_UPDOWN (1 << 13) -#define AT91_TC_WAVESEL_UPDOWN_AUTO (3 << 13) -#define AT91_TC_ACPA (3 << 16) /* Waveform Mode: RA Compare Effect on TIOA */ -#define AT91_TC_ACPA_NONE (0 << 16) -#define AT91_TC_ACPA_SET (1 << 16) -#define AT91_TC_ACPA_CLEAR (2 << 16) -#define AT91_TC_ACPA_TOGGLE (3 << 16) -#define AT91_TC_ACPC (3 << 18) /* Waveform Mode: RC Compre Effect on TIOA */ -#define AT91_TC_ACPC_NONE (0 << 18) -#define AT91_TC_ACPC_SET (1 << 18) -#define AT91_TC_ACPC_CLEAR (2 << 18) -#define AT91_TC_ACPC_TOGGLE (3 << 18) -#define AT91_TC_AEEVT (3 << 20) /* Waveform Mode: External Event Effect on TIOA */ -#define AT91_TC_AEEVT_NONE (0 << 20) -#define AT91_TC_AEEVT_SET (1 << 20) -#define AT91_TC_AEEVT_CLEAR (2 << 20) -#define AT91_TC_AEEVT_TOGGLE (3 << 20) -#define AT91_TC_ASWTRG (3 << 22) /* Waveform Mode: Software Trigger Effect on TIOA */ -#define AT91_TC_ASWTRG_NONE (0 << 22) -#define AT91_TC_ASWTRG_SET (1 << 22) -#define AT91_TC_ASWTRG_CLEAR (2 << 22) -#define AT91_TC_ASWTRG_TOGGLE (3 << 22) -#define AT91_TC_BCPB (3 << 24) /* Waveform Mode: RB Compare Effect on TIOB */ -#define AT91_TC_BCPB_NONE (0 << 24) -#define AT91_TC_BCPB_SET (1 << 24) -#define AT91_TC_BCPB_CLEAR (2 << 24) -#define AT91_TC_BCPB_TOGGLE (3 << 24) -#define AT91_TC_BCPC (3 << 26) /* Waveform Mode: RC Compare Effect on TIOB */ -#define AT91_TC_BCPC_NONE (0 << 26) -#define AT91_TC_BCPC_SET (1 << 26) -#define AT91_TC_BCPC_CLEAR (2 << 26) -#define AT91_TC_BCPC_TOGGLE (3 << 26) -#define AT91_TC_BEEVT (3 << 28) /* Waveform Mode: External Event Effect on TIOB */ -#define AT91_TC_BEEVT_NONE (0 << 28) -#define AT91_TC_BEEVT_SET (1 << 28) -#define AT91_TC_BEEVT_CLEAR (2 << 28) -#define AT91_TC_BEEVT_TOGGLE (3 << 28) -#define AT91_TC_BSWTRG (3 << 30) /* Waveform Mode: Software Trigger Effect on TIOB */ -#define AT91_TC_BSWTRG_NONE (0 << 30) -#define AT91_TC_BSWTRG_SET (1 << 30) -#define AT91_TC_BSWTRG_CLEAR (2 << 30) -#define AT91_TC_BSWTRG_TOGGLE (3 << 30) - -#define AT91_TC_CV 0x10 /* Counter Value */ -#define AT91_TC_RA 0x14 /* Register A */ -#define AT91_TC_RB 0x18 /* Register B */ -#define AT91_TC_RC 0x1c /* Register C */ - -#define AT91_TC_SR 0x20 /* Status Register */ -#define AT91_TC_COVFS (1 << 0) /* Counter Overflow Status */ -#define AT91_TC_LOVRS (1 << 1) /* Load Overrun Status */ -#define AT91_TC_CPAS (1 << 2) /* RA Compare Status */ -#define AT91_TC_CPBS (1 << 3) /* RB Compare Status */ -#define AT91_TC_CPCS (1 << 4) /* RC Compare Status */ -#define AT91_TC_LDRAS (1 << 5) /* RA Loading Status */ -#define AT91_TC_LDRBS (1 << 6) /* RB Loading Status */ -#define AT91_TC_ETRGS (1 << 7) /* External Trigger Status */ -#define AT91_TC_CLKSTA (1 << 16) /* Clock Enabling Status */ -#define AT91_TC_MTIOA (1 << 17) /* TIOA Mirror */ -#define AT91_TC_MTIOB (1 << 18) /* TIOB Mirror */ - -#define AT91_TC_IER 0x24 /* Interrupt Enable Register */ -#define AT91_TC_IDR 0x28 /* Interrupt Disable Register */ -#define AT91_TC_IMR 0x2c /* Interrupt Mask Register */ - -#endif diff --git a/include/asm-arm/arch-at91rm9200/at91_twi.h b/include/asm-arm/arch-at91rm9200/at91_twi.h deleted file mode 100644 index cda914f1e740..000000000000 --- a/include/asm-arm/arch-at91rm9200/at91_twi.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/at91_twi.h - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * Two-wire Interface (TWI) registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_TWI_H -#define AT91_TWI_H - -#define AT91_TWI_CR 0x00 /* Control Register */ -#define AT91_TWI_START (1 << 0) /* Send a Start Condition */ -#define AT91_TWI_STOP (1 << 1) /* Send a Stop Condition */ -#define AT91_TWI_MSEN (1 << 2) /* Master Transfer Enable */ -#define AT91_TWI_MSDIS (1 << 3) /* Master Transfer Disable */ -#define AT91_TWI_SWRST (1 << 7) /* Software Reset */ - -#define AT91_TWI_MMR 0x04 /* Master Mode Register */ -#define AT91_TWI_IADRSZ (3 << 8) /* Internal Device Address Size */ -#define AT91_TWI_IADRSZ_NO (0 << 8) -#define AT91_TWI_IADRSZ_1 (1 << 8) -#define AT91_TWI_IADRSZ_2 (2 << 8) -#define AT91_TWI_IADRSZ_3 (3 << 8) -#define AT91_TWI_MREAD (1 << 12) /* Master Read Direction */ -#define AT91_TWI_DADR (0x7f << 16) /* Device Address */ - -#define AT91_TWI_IADR 0x0c /* Internal Address Register */ - -#define AT91_TWI_CWGR 0x10 /* Clock Waveform Generator Register */ -#define AT91_TWI_CLDIV (0xff << 0) /* Clock Low Divisor */ -#define AT91_TWI_CHDIV (0xff << 8) /* Clock High Divisor */ -#define AT91_TWI_CKDIV (7 << 16) /* Clock Divider */ - -#define AT91_TWI_SR 0x20 /* Status Register */ -#define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */ -#define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */ -#define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */ -#define AT91_TWI_OVRE (1 << 6) /* Overrun Error [AT91RM9200 only] */ -#define AT91_TWI_UNRE (1 << 7) /* Underrun Error [AT91RM9200 only] */ -#define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */ - -#define AT91_TWI_IER 0x24 /* Interrupt Enable Register */ -#define AT91_TWI_IDR 0x28 /* Interrupt Disable Register */ -#define AT91_TWI_IMR 0x2c /* Interrupt Mask Register */ -#define AT91_TWI_RHR 0x30 /* Receive Holding Register */ -#define AT91_TWI_THR 0x34 /* Transmit Holding Register */ - -#endif - diff --git a/include/asm-arm/arch-at91rm9200/at91_wdt.h b/include/asm-arm/arch-at91rm9200/at91_wdt.h deleted file mode 100644 index ac63e775772c..000000000000 --- a/include/asm-arm/arch-at91rm9200/at91_wdt.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/at91_wdt.h - * - * Watchdog Timer (WDT) - System peripherals regsters. - * Based on AT91SAM9261 datasheet revision D. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_WDT_H -#define AT91_WDT_H - -#define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */ -#define AT91_WDT_WDRSTT (1 << 0) /* Restart */ -#define AT91_WDT_KEY (0xff << 24) /* KEY Password */ - -#define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */ -#define AT91_WDT_WDV (0xfff << 0) /* Counter Value */ -#define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */ -#define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */ -#define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */ -#define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */ -#define AT91_WDT_WDD (0xfff << 16) /* Delta Value */ -#define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */ -#define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */ - -#define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */ -#define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */ -#define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */ - -#endif diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200.h b/include/asm-arm/arch-at91rm9200/at91rm9200.h deleted file mode 100644 index c569b6a21a42..000000000000 --- a/include/asm-arm/arch-at91rm9200/at91rm9200.h +++ /dev/null @@ -1,291 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/at91rm9200.h - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * Common definitions. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91RM9200_H -#define AT91RM9200_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Peripheral */ -#define AT91RM9200_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91RM9200_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91RM9200_ID_PIOC 4 /* Parallel IO Controller C */ -#define AT91RM9200_ID_PIOD 5 /* Parallel IO Controller D */ -#define AT91RM9200_ID_US0 6 /* USART 0 */ -#define AT91RM9200_ID_US1 7 /* USART 1 */ -#define AT91RM9200_ID_US2 8 /* USART 2 */ -#define AT91RM9200_ID_US3 9 /* USART 3 */ -#define AT91RM9200_ID_MCI 10 /* Multimedia Card Interface */ -#define AT91RM9200_ID_UDP 11 /* USB Device Port */ -#define AT91RM9200_ID_TWI 12 /* Two-Wire Interface */ -#define AT91RM9200_ID_SPI 13 /* Serial Peripheral Interface */ -#define AT91RM9200_ID_SSC0 14 /* Serial Synchronous Controller 0 */ -#define AT91RM9200_ID_SSC1 15 /* Serial Synchronous Controller 1 */ -#define AT91RM9200_ID_SSC2 16 /* Serial Synchronous Controller 2 */ -#define AT91RM9200_ID_TC0 17 /* Timer Counter 0 */ -#define AT91RM9200_ID_TC1 18 /* Timer Counter 1 */ -#define AT91RM9200_ID_TC2 19 /* Timer Counter 2 */ -#define AT91RM9200_ID_TC3 20 /* Timer Counter 3 */ -#define AT91RM9200_ID_TC4 21 /* Timer Counter 4 */ -#define AT91RM9200_ID_TC5 22 /* Timer Counter 5 */ -#define AT91RM9200_ID_UHP 23 /* USB Host port */ -#define AT91RM9200_ID_EMAC 24 /* Ethernet MAC */ -#define AT91RM9200_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91RM9200_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91RM9200_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */ -#define AT91RM9200_ID_IRQ3 28 /* Advanced Interrupt Controller (IRQ3) */ -#define AT91RM9200_ID_IRQ4 29 /* Advanced Interrupt Controller (IRQ4) */ -#define AT91RM9200_ID_IRQ5 30 /* Advanced Interrupt Controller (IRQ5) */ -#define AT91RM9200_ID_IRQ6 31 /* Advanced Interrupt Controller (IRQ6) */ - - -/* - * Peripheral physical base addresses. - */ -#define AT91RM9200_BASE_TCB0 0xfffa0000 -#define AT91RM9200_BASE_TC0 0xfffa0000 -#define AT91RM9200_BASE_TC1 0xfffa0040 -#define AT91RM9200_BASE_TC2 0xfffa0080 -#define AT91RM9200_BASE_TCB1 0xfffa4000 -#define AT91RM9200_BASE_TC3 0xfffa4000 -#define AT91RM9200_BASE_TC4 0xfffa4040 -#define AT91RM9200_BASE_TC5 0xfffa4080 -#define AT91RM9200_BASE_UDP 0xfffb0000 -#define AT91RM9200_BASE_MCI 0xfffb4000 -#define AT91RM9200_BASE_TWI 0xfffb8000 -#define AT91RM9200_BASE_EMAC 0xfffbc000 -#define AT91RM9200_BASE_US0 0xfffc0000 -#define AT91RM9200_BASE_US1 0xfffc4000 -#define AT91RM9200_BASE_US2 0xfffc8000 -#define AT91RM9200_BASE_US3 0xfffcc000 -#define AT91RM9200_BASE_SSC0 0xfffd0000 -#define AT91RM9200_BASE_SSC1 0xfffd4000 -#define AT91RM9200_BASE_SSC2 0xfffd8000 -#define AT91RM9200_BASE_SPI 0xfffe0000 -#define AT91_BASE_SYS 0xfffff000 - - -/* - * System Peripherals (offset from AT91_BASE_SYS) - */ -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */ -#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) /* Debug Unit */ -#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) /* PIO Controller A */ -#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) /* PIO Controller B */ -#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) /* PIO Controller C */ -#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) /* PIO Controller D */ -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */ -#define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */ -#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */ -#define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */ - -#define AT91_MATRIX 0 /* not supported */ - -/* - * Internal Memory. - */ -#define AT91RM9200_ROM_BASE 0x00100000 /* Internal ROM base address */ -#define AT91RM9200_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ - -#define AT91RM9200_SRAM_BASE 0x00200000 /* Internal SRAM base address */ -#define AT91RM9200_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */ - -#define AT91RM9200_UHP_BASE 0x00300000 /* USB Host controller */ - - -#if 0 -/* - * PIO pin definitions (peripheral A/B multiplexing). - */ -#define AT91_PA0_MISO (1 << 0) /* A: SPI Master-In Slave-Out */ -#define AT91_PA0_PCK3 (1 << 0) /* B: PMC Programmable Clock Output 3 */ -#define AT91_PA1_MOSI (1 << 1) /* A: SPI Master-Out Slave-In */ -#define AT91_PA1_PCK0 (1 << 1) /* B: PMC Programmable Clock Output 0 */ -#define AT91_PA2_SPCK (1 << 2) /* A: SPI Serial Clock */ -#define AT91_PA2_IRQ4 (1 << 2) /* B: External Interrupt 4 */ -#define AT91_PA3_NPCS0 (1 << 3) /* A: SPI Peripheral Chip Select 0 */ -#define AT91_PA3_IRQ5 (1 << 3) /* B: External Interrupt 5 */ -#define AT91_PA4_NPCS1 (1 << 4) /* A: SPI Peripheral Chip Select 1 */ -#define AT91_PA4_PCK1 (1 << 4) /* B: PMC Programmable Clock Output 1 */ -#define AT91_PA5_NPCS2 (1 << 5) /* A: SPI Peripheral Chip Select 2 */ -#define AT91_PA5_TXD3 (1 << 5) /* B: USART Transmit Data 3 */ -#define AT91_PA6_NPCS3 (1 << 6) /* A: SPI Peripheral Chip Select 3 */ -#define AT91_PA6_RXD3 (1 << 6) /* B: USART Receive Data 3 */ -#define AT91_PA7_ETXCK_EREFCK (1 << 7) /* A: Ethernet Reference Clock / Transmit Clock */ -#define AT91_PA7_PCK2 (1 << 7) /* B: PMC Programmable Clock Output 2 */ -#define AT91_PA8_ETXEN (1 << 8) /* A: Ethernet Transmit Enable */ -#define AT91_PA8_MCCDB (1 << 8) /* B: MMC Multimedia Card B Command */ -#define AT91_PA9_ETX0 (1 << 9) /* A: Ethernet Transmit Data 0 */ -#define AT91_PA9_MCDB0 (1 << 9) /* B: MMC Multimedia Card B Data 0 */ -#define AT91_PA10_ETX1 (1 << 10) /* A: Ethernet Transmit Data 1 */ -#define AT91_PA10_MCDB1 (1 << 10) /* B: MMC Multimedia Card B Data 1 */ -#define AT91_PA11_ECRS_ECRSDV (1 << 11) /* A: Ethernet Carrier Sense / Data Valid */ -#define AT91_PA11_MCDB2 (1 << 11) /* B: MMC Multimedia Card B Data 2 */ -#define AT91_PA12_ERX0 (1 << 12) /* A: Ethernet Receive Data 0 */ -#define AT91_PA12_MCDB3 (1 << 12) /* B: MMC Multimedia Card B Data 3 */ -#define AT91_PA13_ERX1 (1 << 13) /* A: Ethernet Receive Data 1 */ -#define AT91_PA13_TCLK0 (1 << 13) /* B: TC External Clock Input 0 */ -#define AT91_PA14_ERXER (1 << 14) /* A: Ethernet Receive Error */ -#define AT91_PA14_TCLK1 (1 << 14) /* B: TC External Clock Input 1 */ -#define AT91_PA15_EMDC (1 << 15) /* A: Ethernet Management Data Clock */ -#define AT91_PA15_TCLK2 (1 << 15) /* B: TC External Clock Input 2 */ -#define AT91_PA16_EMDIO (1 << 16) /* A: Ethernet Management Data I/O */ -#define AT91_PA16_IRQ6 (1 << 16) /* B: External Interrupt 6 */ -#define AT91_PA17_TXD0 (1 << 17) /* A: USART Transmit Data 0 */ -#define AT91_PA17_TIOA0 (1 << 17) /* B: TC I/O Line A 0 */ -#define AT91_PA18_RXD0 (1 << 18) /* A: USART Receive Data 0 */ -#define AT91_PA18_TIOB0 (1 << 18) /* B: TC I/O Line B 0 */ -#define AT91_PA19_SCK0 (1 << 19) /* A: USART Serial Clock 0 */ -#define AT91_PA19_TIOA1 (1 << 19) /* B: TC I/O Line A 1 */ -#define AT91_PA20_CTS0 (1 << 20) /* A: USART Clear To Send 0 */ -#define AT91_PA20_TIOB1 (1 << 20) /* B: TC I/O Line B 1 */ -#define AT91_PA21_RTS0 (1 << 21) /* A: USART Ready To Send 0 */ -#define AT91_PA21_TIOA2 (1 << 21) /* B: TC I/O Line A 2 */ -#define AT91_PA22_RXD2 (1 << 22) /* A: USART Receive Data 2 */ -#define AT91_PA22_TIOB2 (1 << 22) /* B: TC I/O Line B 2 */ -#define AT91_PA23_TXD2 (1 << 23) /* A: USART Transmit Data 2 */ -#define AT91_PA23_IRQ3 (1 << 23) /* B: External Interrupt 3 */ -#define AT91_PA24_SCK2 (1 << 24) /* A: USART Serial Clock 2 */ -#define AT91_PA24_PCK1 (1 << 24) /* B: PMC Programmable Clock Output 1 */ -#define AT91_PA25_TWD (1 << 25) /* A: TWI Two-wire Serial Data */ -#define AT91_PA25_IRQ2 (1 << 25) /* B: External Interrupt 2 */ -#define AT91_PA26_TWCK (1 << 26) /* A: TWI Two-wire Serial Clock */ -#define AT91_PA26_IRQ1 (1 << 26) /* B: External Interrupt 1 */ -#define AT91_PA27_MCCK (1 << 27) /* A: MMC Multimedia Card Clock */ -#define AT91_PA27_TCLK3 (1 << 27) /* B: TC External Clock Input 3 */ -#define AT91_PA28_MCCDA (1 << 28) /* A: MMC Multimedia Card A Command */ -#define AT91_PA28_TCLK4 (1 << 28) /* B: TC External Clock Input 4 */ -#define AT91_PA29_MCDA0 (1 << 29) /* A: MMC Multimedia Card A Data 0 */ -#define AT91_PA29_TCLK5 (1 << 29) /* B: TC External Clock Input 5 */ -#define AT91_PA30_DRXD (1 << 30) /* A: DBGU Receive Data */ -#define AT91_PA30_CTS2 (1 << 30) /* B: USART Clear To Send 2 */ -#define AT91_PA31_DTXD (1 << 31) /* A: DBGU Transmit Data */ -#define AT91_PA31_RTS2 (1 << 31) /* B: USART Ready To Send 2 */ - -#define AT91_PB0_TF0 (1 << 0) /* A: SSC Transmit Frame Sync 0 */ -#define AT91_PB0_RTS3 (1 << 0) /* B: USART Ready To Send 3 */ -#define AT91_PB1_TK0 (1 << 1) /* A: SSC Transmit Clock 0 */ -#define AT91_PB1_CTS3 (1 << 1) /* B: USART Clear To Send 3 */ -#define AT91_PB2_TD0 (1 << 2) /* A: SSC Transmit Data 0 */ -#define AT91_PB2_SCK3 (1 << 2) /* B: USART Serial Clock 3 */ -#define AT91_PB3_RD0 (1 << 3) /* A: SSC Receive Data 0 */ -#define AT91_PB3_MCDA1 (1 << 3) /* B: MMC Multimedia Card A Data 1 */ -#define AT91_PB4_RK0 (1 << 4) /* A: SSC Receive Clock 0 */ -#define AT91_PB4_MCDA2 (1 << 4) /* B: MMC Multimedia Card A Data 2 */ -#define AT91_PB5_RF0 (1 << 5) /* A: SSC Receive Frame Sync 0 */ -#define AT91_PB5_MCDA3 (1 << 5) /* B: MMC Multimedia Card A Data 3 */ -#define AT91_PB6_TF1 (1 << 6) /* A: SSC Transmit Frame Sync 1 */ -#define AT91_PB6_TIOA3 (1 << 6) /* B: TC I/O Line A 3 */ -#define AT91_PB7_TK1 (1 << 7) /* A: SSC Transmit Clock 1 */ -#define AT91_PB7_TIOB3 (1 << 7) /* B: TC I/O Line B 3 */ -#define AT91_PB8_TD1 (1 << 8) /* A: SSC Transmit Data 1 */ -#define AT91_PB8_TIOA4 (1 << 8) /* B: TC I/O Line A 4 */ -#define AT91_PB9_RD1 (1 << 9) /* A: SSC Receive Data 1 */ -#define AT91_PB9_TIOB4 (1 << 9) /* B: TC I/O Line B 4 */ -#define AT91_PB10_RK1 (1 << 10) /* A: SSC Receive Clock 1 */ -#define AT91_PB10_TIOA5 (1 << 10) /* B: TC I/O Line A 5 */ -#define AT91_PB11_RF1 (1 << 11) /* A: SSC Receive Frame Sync 1 */ -#define AT91_PB11_TIOB5 (1 << 11) /* B: TC I/O Line B 5 */ -#define AT91_PB12_TF2 (1 << 12) /* A: SSC Transmit Frame Sync 2 */ -#define AT91_PB12_ETX2 (1 << 12) /* B: Ethernet Transmit Data 2 */ -#define AT91_PB13_TK2 (1 << 13) /* A: SSC Transmit Clock 3 */ -#define AT91_PB13_ETX3 (1 << 13) /* B: Ethernet Transmit Data 3 */ -#define AT91_PB14_TD2 (1 << 14) /* A: SSC Transmit Data 2 */ -#define AT91_PB14_ETXER (1 << 14) /* B: Ethernet Transmit Coding Error */ -#define AT91_PB15_RD2 (1 << 15) /* A: SSC Receive Data 2 */ -#define AT91_PB15_ERX2 (1 << 15) /* B: Ethernet Receive Data 2 */ -#define AT91_PB16_RK2 (1 << 16) /* A: SSC Receive Clock 2 */ -#define AT91_PB16_ERX3 (1 << 16) /* B: Ethernet Receive Data 3 */ -#define AT91_PB17_RF2 (1 << 17) /* A: SSC Receive Frame Sync 2 */ -#define AT91_PB17_ERXDV (1 << 17) /* B: Ethernet Receive Data Valid */ -#define AT91_PB18_RI1 (1 << 18) /* A: USART Ring Indicator 1 */ -#define AT91_PB18_ECOL (1 << 18) /* B: Ethernet Collision Detected */ -#define AT91_PB19_DTR1 (1 << 19) /* A: USART Data Terminal Ready 1 */ -#define AT91_PB19_ERXCK (1 << 19) /* B: Ethernet Receive Clock */ -#define AT91_PB20_TXD1 (1 << 20) /* A: USART Transmit Data 1 */ -#define AT91_PB21_RXD1 (1 << 21) /* A: USART Receive Data 1 */ -#define AT91_PB22_SCK1 (1 << 22) /* A: USART Serial Clock 1 */ -#define AT91_PB23_DCD1 (1 << 23) /* A: USART Data Carrier Detect 1 */ -#define AT91_PB24_CTS1 (1 << 24) /* A: USART Clear To Send 1 */ -#define AT91_PB25_DSR1 (1 << 25) /* A: USART Data Set Ready 1 */ -#define AT91_PB25_EF100 (1 << 25) /* B: Ethernet Force 100 Mbit */ -#define AT91_PB26_RTS1 (1 << 26) /* A: USART Ready To Send 1 */ -#define AT91_PB27_PCK0 (1 << 27) /* B: PMC Programmable Clock Output 0 */ -#define AT91_PB28_FIQ (1 << 28) /* A: Fast Interrupt */ -#define AT91_PB29_IRQ0 (1 << 29) /* A: External Interrupt 0 */ - -#define AT91_PC0_BFCK (1 << 0) /* A: Burst Flash Clock */ -#define AT91_PC1_BFRDY_SMOE (1 << 1) /* A: Burst Flash Ready / SmartMedia Output Enable */ -#define AT91_PC2_BFAVD (1 << 2) /* A: Burst Flash Address Valid */ -#define AT91_PC3_BFBAA_SMWE (1 << 3) /* A: Burst Flash Address Advance / SmartMedia Write Enable */ -#define AT91_PC4_BFOE (1 << 4) /* A: Burst Flash Output Enable */ -#define AT91_PC5_BFWE (1 << 5) /* A: Burst Flash Write Enable */ -#define AT91_PC6_NWAIT (1 << 6) /* A: SMC Wait Signal */ -#define AT91_PC7_A23 (1 << 7) /* A: Address Bus 23 */ -#define AT91_PC8_A24 (1 << 8) /* A: Address Bus 24 */ -#define AT91_PC9_A25_CFRNW (1 << 9) /* A: Address Bus 25 / Compact Flash Read Not Write */ -#define AT91_PC10_NCS4_CFCS (1 << 10) /* A: SMC Chip Select 4 / Compact Flash Chip Select */ -#define AT91_PC11_NCS5_CFCE1 (1 << 11) /* A: SMC Chip Select 5 / Compact Flash Chip Enable 1 */ -#define AT91_PC12_NCS6_CFCE2 (1 << 12) /* A: SMC Chip Select 6 / Compact Flash Chip Enable 2 */ -#define AT91_PC13_NCS7 (1 << 13) /* A: Chip Select 7 */ - -#define AT91_PD0_ETX0 (1 << 0) /* A: Ethernet Transmit Data 0 */ -#define AT91_PD1_ETX1 (1 << 1) /* A: Ethernet Transmit Data 1 */ -#define AT91_PD2_ETX2 (1 << 2) /* A: Ethernet Transmit Data 2 */ -#define AT91_PD3_ETX3 (1 << 3) /* A: Ethernet Transmit Data 3 */ -#define AT91_PD4_ETXEN (1 << 4) /* A: Ethernet Transmit Enable */ -#define AT91_PD5_ETXER (1 << 5) /* A: Ethernet Transmit Coding Error */ -#define AT91_PD6_DTXD (1 << 6) /* A: DBGU Transmit Data */ -#define AT91_PD7_PCK0 (1 << 7) /* A: PMC Programmable Clock Output 0 */ -#define AT91_PD7_TSYNC (1 << 7) /* B: ETM Trace Synchronization Signal */ -#define AT91_PD8_PCK1 (1 << 8) /* A: PMC Programmable Clock Output 1 */ -#define AT91_PD8_TCLK (1 << 8) /* B: ETM Trace Clock */ -#define AT91_PD9_PCK2 (1 << 9) /* A: PMC Programmable Clock Output 2 */ -#define AT91_PD9_TPS0 (1 << 9) /* B: ETM Trace ARM Pipeline Status 0 */ -#define AT91_PD10_PCK3 (1 << 10) /* A: PMC Programmable Clock Output 3 */ -#define AT91_PD10_TPS1 (1 << 10) /* B: ETM Trace ARM Pipeline Status 1 */ -#define AT91_PD11_TPS2 (1 << 11) /* B: ETM Trace ARM Pipeline Status 2 */ -#define AT91_PD12_TPK0 (1 << 12) /* B: ETM Trace Packet Port 0 */ -#define AT91_PD13_TPK1 (1 << 13) /* B: ETM Trace Packet Port 1 */ -#define AT91_PD14_TPK2 (1 << 14) /* B: ETM Trace Packet Port 2 */ -#define AT91_PD15_TD0 (1 << 15) /* A: SSC Transmit Data 0 */ -#define AT91_PD15_TPK3 (1 << 15) /* B: ETM Trace Packet Port 3 */ -#define AT91_PD16_TD1 (1 << 16) /* A: SSC Transmit Data 1 */ -#define AT91_PD16_TPK4 (1 << 16) /* B: ETM Trace Packet Port 4 */ -#define AT91_PD17_TD2 (1 << 17) /* A: SSC Transmit Data 2 */ -#define AT91_PD17_TPK5 (1 << 17) /* B: ETM Trace Packet Port 5 */ -#define AT91_PD18_NPCS1 (1 << 18) /* A: SPI Peripheral Chip Select 1 */ -#define AT91_PD18_TPK6 (1 << 18) /* B: ETM Trace Packet Port 6 */ -#define AT91_PD19_NPCS2 (1 << 19) /* A: SPI Peripheral Chip Select 2 */ -#define AT91_PD19_TPK7 (1 << 19) /* B: ETM Trace Packet Port 7 */ -#define AT91_PD20_NPCS3 (1 << 20) /* A: SPI Peripheral Chip Select 3 */ -#define AT91_PD20_TPK8 (1 << 20) /* B: ETM Trace Packet Port 8 */ -#define AT91_PD21_RTS0 (1 << 21) /* A: USART Ready To Send 0 */ -#define AT91_PD21_TPK9 (1 << 21) /* B: ETM Trace Packet Port 9 */ -#define AT91_PD22_RTS1 (1 << 22) /* A: USART Ready To Send 1 */ -#define AT91_PD22_TPK10 (1 << 22) /* B: ETM Trace Packet Port 10 */ -#define AT91_PD23_RTS2 (1 << 23) /* A: USART Ready To Send 2 */ -#define AT91_PD23_TPK11 (1 << 23) /* B: ETM Trace Packet Port 11 */ -#define AT91_PD24_RTS3 (1 << 24) /* A: USART Ready To Send 3 */ -#define AT91_PD24_TPK12 (1 << 24) /* B: ETM Trace Packet Port 12 */ -#define AT91_PD25_DTR1 (1 << 25) /* A: USART Data Terminal Ready 1 */ -#define AT91_PD25_TPK13 (1 << 25) /* B: ETM Trace Packet Port 13 */ -#define AT91_PD26_TPK14 (1 << 26) /* B: ETM Trace Packet Port 14 */ -#define AT91_PD27_TPK15 (1 << 27) /* B: ETM Trace Packet Port 15 */ -#endif - -#endif diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_emac.h b/include/asm-arm/arch-at91rm9200/at91rm9200_emac.h deleted file mode 100644 index fbc091e61e2f..000000000000 --- a/include/asm-arm/arch-at91rm9200/at91rm9200_emac.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/at91rm9200_emac.h - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * Ethernet MAC registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91RM9200_EMAC_H -#define AT91RM9200_EMAC_H - -#define AT91_EMAC_CTL 0x00 /* Control Register */ -#define AT91_EMAC_LB (1 << 0) /* Loopback */ -#define AT91_EMAC_LBL (1 << 1) /* Loopback Local */ -#define AT91_EMAC_RE (1 << 2) /* Receive Enable */ -#define AT91_EMAC_TE (1 << 3) /* Transmit Enable */ -#define AT91_EMAC_MPE (1 << 4) /* Management Port Enable */ -#define AT91_EMAC_CSR (1 << 5) /* Clear Statistics Registers */ -#define AT91_EMAC_INCSTAT (1 << 6) /* Increment Statistics Registers */ -#define AT91_EMAC_WES (1 << 7) /* Write Enable for Statistics Registers */ -#define AT91_EMAC_BP (1 << 8) /* Back Pressure */ - -#define AT91_EMAC_CFG 0x04 /* Configuration Register */ -#define AT91_EMAC_SPD (1 << 0) /* Speed */ -#define AT91_EMAC_FD (1 << 1) /* Full Duplex */ -#define AT91_EMAC_BR (1 << 2) /* Bit Rate */ -#define AT91_EMAC_CAF (1 << 4) /* Copy All Frames */ -#define AT91_EMAC_NBC (1 << 5) /* No Broadcast */ -#define AT91_EMAC_MTI (1 << 6) /* Multicast Hash Enable */ -#define AT91_EMAC_UNI (1 << 7) /* Unicast Hash Enable */ -#define AT91_EMAC_BIG (1 << 8) /* Receive 1522 Bytes */ -#define AT91_EMAC_EAE (1 << 9) /* External Address Match Enable */ -#define AT91_EMAC_CLK (3 << 10) /* MDC Clock Divisor */ -#define AT91_EMAC_CLK_DIV8 (0 << 10) -#define AT91_EMAC_CLK_DIV16 (1 << 10) -#define AT91_EMAC_CLK_DIV32 (2 << 10) -#define AT91_EMAC_CLK_DIV64 (3 << 10) -#define AT91_EMAC_RTY (1 << 12) /* Retry Test */ -#define AT91_EMAC_RMII (1 << 13) /* Reduce MII (RMII) */ - -#define AT91_EMAC_SR 0x08 /* Status Register */ -#define AT91_EMAC_SR_LINK (1 << 0) /* Link */ -#define AT91_EMAC_SR_MDIO (1 << 1) /* MDIO pin */ -#define AT91_EMAC_SR_IDLE (1 << 2) /* PHY idle */ - -#define AT91_EMAC_TAR 0x0c /* Transmit Address Register */ - -#define AT91_EMAC_TCR 0x10 /* Transmit Control Register */ -#define AT91_EMAC_LEN (0x7ff << 0) /* Transmit Frame Length */ -#define AT91_EMAC_NCRC (1 << 15) /* No CRC */ - -#define AT91_EMAC_TSR 0x14 /* Transmit Status Register */ -#define AT91_EMAC_TSR_OVR (1 << 0) /* Transmit Buffer Overrun */ -#define AT91_EMAC_TSR_COL (1 << 1) /* Collision Occurred */ -#define AT91_EMAC_TSR_RLE (1 << 2) /* Retry Limit Exceeded */ -#define AT91_EMAC_TSR_IDLE (1 << 3) /* Transmitter Idle */ -#define AT91_EMAC_TSR_BNQ (1 << 4) /* Transmit Buffer not Queued */ -#define AT91_EMAC_TSR_COMP (1 << 5) /* Transmit Complete */ -#define AT91_EMAC_TSR_UND (1 << 6) /* Transmit Underrun */ - -#define AT91_EMAC_RBQP 0x18 /* Receive Buffer Queue Pointer */ - -#define AT91_EMAC_RSR 0x20 /* Receive Status Register */ -#define AT91_EMAC_RSR_BNA (1 << 0) /* Buffer Not Available */ -#define AT91_EMAC_RSR_REC (1 << 1) /* Frame Received */ -#define AT91_EMAC_RSR_OVR (1 << 2) /* RX Overrun */ - -#define AT91_EMAC_ISR 0x24 /* Interrupt Status Register */ -#define AT91_EMAC_DONE (1 << 0) /* Management Done */ -#define AT91_EMAC_RCOM (1 << 1) /* Receive Complete */ -#define AT91_EMAC_RBNA (1 << 2) /* Receive Buffer Not Available */ -#define AT91_EMAC_TOVR (1 << 3) /* Transmit Buffer Overrun */ -#define AT91_EMAC_TUND (1 << 4) /* Transmit Buffer Underrun */ -#define AT91_EMAC_RTRY (1 << 5) /* Retry Limit */ -#define AT91_EMAC_TBRE (1 << 6) /* Transmit Buffer Register Empty */ -#define AT91_EMAC_TCOM (1 << 7) /* Transmit Complete */ -#define AT91_EMAC_TIDLE (1 << 8) /* Transmit Idle */ -#define AT91_EMAC_LINK (1 << 9) /* Link */ -#define AT91_EMAC_ROVR (1 << 10) /* RX Overrun */ -#define AT91_EMAC_ABT (1 << 11) /* Abort */ - -#define AT91_EMAC_IER 0x28 /* Interrupt Enable Register */ -#define AT91_EMAC_IDR 0x2c /* Interrupt Disable Register */ -#define AT91_EMAC_IMR 0x30 /* Interrupt Mask Register */ - -#define AT91_EMAC_MAN 0x34 /* PHY Maintenance Register */ -#define AT91_EMAC_DATA (0xffff << 0) /* MDIO Data */ -#define AT91_EMAC_REGA (0x1f << 18) /* MDIO Register */ -#define AT91_EMAC_PHYA (0x1f << 23) /* MDIO PHY Address */ -#define AT91_EMAC_RW (3 << 28) /* Read/Write operation */ -#define AT91_EMAC_RW_W (1 << 28) -#define AT91_EMAC_RW_R (2 << 28) -#define AT91_EMAC_MAN_802_3 0x40020000 /* IEEE 802.3 value */ - -/* - * Statistics Registers. - */ -#define AT91_EMAC_FRA 0x40 /* Frames Transmitted OK */ -#define AT91_EMAC_SCOL 0x44 /* Single Collision Frame */ -#define AT91_EMAC_MCOL 0x48 /* Multiple Collision Frame */ -#define AT91_EMAC_OK 0x4c /* Frames Received OK */ -#define AT91_EMAC_SEQE 0x50 /* Frame Check Sequence Error */ -#define AT91_EMAC_ALE 0x54 /* Alignmemt Error */ -#define AT91_EMAC_DTE 0x58 /* Deffered Transmission Frame */ -#define AT91_EMAC_LCOL 0x5c /* Late Collision */ -#define AT91_EMAC_ECOL 0x60 /* Excessive Collision */ -#define AT91_EMAC_TUE 0x64 /* Transmit Underrun Error */ -#define AT91_EMAC_CSE 0x68 /* Carrier Sense Error */ -#define AT91_EMAC_DRFC 0x6c /* Discard RX Frame */ -#define AT91_EMAC_ROV 0x70 /* Receive Overrun */ -#define AT91_EMAC_CDE 0x74 /* Code Error */ -#define AT91_EMAC_ELR 0x78 /* Excessive Length Error */ -#define AT91_EMAC_RJB 0x7c /* Receive Jabber */ -#define AT91_EMAC_USF 0x80 /* Undersize Frame */ -#define AT91_EMAC_SQEE 0x84 /* SQE Test Error */ - -/* - * Address Registers. - */ -#define AT91_EMAC_HSL 0x90 /* Hash Address Low [31:0] */ -#define AT91_EMAC_HSH 0x94 /* Hash Address High [63:32] */ -#define AT91_EMAC_SA1L 0x98 /* Specific Address 1 Low, bytes 0-3 */ -#define AT91_EMAC_SA1H 0x9c /* Specific Address 1 High, bytes 4-5 */ -#define AT91_EMAC_SA2L 0xa0 /* Specific Address 2 Low, bytes 0-3 */ -#define AT91_EMAC_SA2H 0xa4 /* Specific Address 2 High, bytes 4-5 */ -#define AT91_EMAC_SA3L 0xa8 /* Specific Address 3 Low, bytes 0-3 */ -#define AT91_EMAC_SA3H 0xac /* Specific Address 3 High, bytes 4-5 */ -#define AT91_EMAC_SA4L 0xb0 /* Specific Address 4 Low, bytes 0-3 */ -#define AT91_EMAC_SA4H 0xb4 /* Specific Address 4 High, bytes 4-5 */ - -#endif diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_mc.h b/include/asm-arm/arch-at91rm9200/at91rm9200_mc.h deleted file mode 100644 index 0c0d81480b3a..000000000000 --- a/include/asm-arm/arch-at91rm9200/at91rm9200_mc.h +++ /dev/null @@ -1,160 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/at91rm9200_mc.h - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91RM9200_MC_H -#define AT91RM9200_MC_H - -/* Memory Controller */ -#define AT91_MC_RCR (AT91_MC + 0x00) /* MC Remap Control Register */ -#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */ - -#define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */ -#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */ -#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */ -#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */ -#define AT91_MC_ABTSZ_BYTE (0 << 8) -#define AT91_MC_ABTSZ_HALFWORD (1 << 8) -#define AT91_MC_ABTSZ_WORD (2 << 8) -#define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */ -#define AT91_MC_ABTTYP_DATAREAD (0 << 10) -#define AT91_MC_ABTTYP_DATAWRITE (1 << 10) -#define AT91_MC_ABTTYP_FETCH (2 << 10) -#define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */ -#define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */ -#define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */ -#define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */ -#define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */ -#define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */ -#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */ -#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */ - -#define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */ - -#define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */ -#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */ -#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */ -#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */ -#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */ - -/* External Bus Interface (EBI) registers */ -#define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */ -#define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */ -#define AT91_EBI_CS0A_SMC (0 << 0) -#define AT91_EBI_CS0A_BFC (1 << 0) -#define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_EBI_CS1A_SMC (0 << 1) -#define AT91_EBI_CS1A_SDRAMC (1 << 1) -#define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */ -#define AT91_EBI_CS3A_SMC (0 << 3) -#define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */ -#define AT91_EBI_CS4A_SMC (0 << 4) -#define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4) -#define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */ -#define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */ - -/* Static Memory Controller (SMC) registers */ -#define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */ -#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */ -#define AT91_SMC_NWS_(x) ((x) << 0) -#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */ -#define AT91_SMC_TDF (0xf << 8) /* Data Float Time */ -#define AT91_SMC_TDF_(x) ((x) << 8) -#define AT91_SMC_BAT (1 << 12) /* Byte Access Type */ -#define AT91_SMC_DBW (3 << 13) /* Data Bus Width */ -#define AT91_SMC_DBW_16 (1 << 13) -#define AT91_SMC_DBW_8 (2 << 13) -#define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */ -#define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */ -#define AT91_SMC_ACSS_STD (0 << 16) -#define AT91_SMC_ACSS_1 (1 << 16) -#define AT91_SMC_ACSS_2 (2 << 16) -#define AT91_SMC_ACSS_3 (3 << 16) -#define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */ -#define AT91_SMC_RWSETUP_(x) ((x) << 24) -#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */ -#define AT91_SMC_RWHOLD_(x) ((x) << 28) - -/* SDRAM Controller registers */ -#define AT91_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */ -#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ -#define AT91_SDRAMC_MODE_NORMAL (0 << 0) -#define AT91_SDRAMC_MODE_NOP (1 << 0) -#define AT91_SDRAMC_MODE_PRECHARGE (2 << 0) -#define AT91_SDRAMC_MODE_LMR (3 << 0) -#define AT91_SDRAMC_MODE_REFRESH (4 << 0) -#define AT91_SDRAMC_DBW (1 << 4) /* Data Bus Width */ -#define AT91_SDRAMC_DBW_32 (0 << 4) -#define AT91_SDRAMC_DBW_16 (1 << 4) - -#define AT91_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */ -#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */ - -#define AT91_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */ -#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ -#define AT91_SDRAMC_NC_8 (0 << 0) -#define AT91_SDRAMC_NC_9 (1 << 0) -#define AT91_SDRAMC_NC_10 (2 << 0) -#define AT91_SDRAMC_NC_11 (3 << 0) -#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ -#define AT91_SDRAMC_NR_11 (0 << 2) -#define AT91_SDRAMC_NR_12 (1 << 2) -#define AT91_SDRAMC_NR_13 (2 << 2) -#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ -#define AT91_SDRAMC_NB_2 (0 << 4) -#define AT91_SDRAMC_NB_4 (1 << 4) -#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ -#define AT91_SDRAMC_CAS_2 (2 << 5) -#define AT91_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */ -#define AT91_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */ -#define AT91_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */ -#define AT91_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */ -#define AT91_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */ -#define AT91_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */ - -#define AT91_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */ -#define AT91_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */ -#define AT91_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */ -#define AT91_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */ -#define AT91_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */ -#define AT91_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */ - -/* Burst Flash Controller register */ -#define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */ -#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */ -#define AT91_BFC_BFCOM_DISABLED (0 << 0) -#define AT91_BFC_BFCOM_ASYNC (1 << 0) -#define AT91_BFC_BFCOM_BURST (2 << 0) -#define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */ -#define AT91_BFC_BFCC_MCK (1 << 2) -#define AT91_BFC_BFCC_DIV2 (2 << 2) -#define AT91_BFC_BFCC_DIV4 (3 << 2) -#define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */ -#define AT91_BFC_PAGES (7 << 8) /* Page Size */ -#define AT91_BFC_PAGES_NO_PAGE (0 << 8) -#define AT91_BFC_PAGES_16 (1 << 8) -#define AT91_BFC_PAGES_32 (2 << 8) -#define AT91_BFC_PAGES_64 (3 << 8) -#define AT91_BFC_PAGES_128 (4 << 8) -#define AT91_BFC_PAGES_256 (5 << 8) -#define AT91_BFC_PAGES_512 (6 << 8) -#define AT91_BFC_PAGES_1024 (7 << 8) -#define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */ -#define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */ -#define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */ -#define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */ -#define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */ - -#endif diff --git a/include/asm-arm/arch-at91rm9200/at91sam9260.h b/include/asm-arm/arch-at91rm9200/at91sam9260.h deleted file mode 100644 index 46f4dd65c035..000000000000 --- a/include/asm-arm/arch-at91rm9200/at91sam9260.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/at91sam9260.h - * - * (C) 2006 Andrew Victor - * - * Common definitions. - * Based on AT91SAM9260 datasheet revision A (Preliminary). - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9260_H -#define AT91SAM9260_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Peripherals */ -#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */ -#define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */ -#define AT91SAM9260_ID_US0 6 /* USART 0 */ -#define AT91SAM9260_ID_US1 7 /* USART 1 */ -#define AT91SAM9260_ID_US2 8 /* USART 2 */ -#define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */ -#define AT91SAM9260_ID_UDP 10 /* USB Device Port */ -#define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */ -#define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */ -#define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */ -#define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */ -#define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */ -#define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */ -#define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */ -#define AT91SAM9260_ID_UHP 20 /* USB Host port */ -#define AT91SAM9260_ID_EMAC 21 /* Ethernet */ -#define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */ -#define AT91SAM9260_ID_US3 23 /* USART 3 */ -#define AT91SAM9260_ID_US4 24 /* USART 4 */ -#define AT91SAM9260_ID_US5 25 /* USART 5 */ -#define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */ -#define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */ -#define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */ -#define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ - - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9260_BASE_TCB0 0xfffa0000 -#define AT91SAM9260_BASE_TC0 0xfffa0000 -#define AT91SAM9260_BASE_TC1 0xfffa0040 -#define AT91SAM9260_BASE_TC2 0xfffa0080 -#define AT91SAM9260_BASE_UDP 0xfffa4000 -#define AT91SAM9260_BASE_MCI 0xfffa8000 -#define AT91SAM9260_BASE_TWI 0xfffac000 -#define AT91SAM9260_BASE_US0 0xfffb0000 -#define AT91SAM9260_BASE_US1 0xfffb4000 -#define AT91SAM9260_BASE_US2 0xfffb8000 -#define AT91SAM9260_BASE_SSC 0xfffbc000 -#define AT91SAM9260_BASE_ISI 0xfffc0000 -#define AT91SAM9260_BASE_EMAC 0xfffc4000 -#define AT91SAM9260_BASE_SPI0 0xfffc8000 -#define AT91SAM9260_BASE_SPI1 0xfffcc000 -#define AT91SAM9260_BASE_US3 0xfffd0000 -#define AT91SAM9260_BASE_US4 0xfffd4000 -#define AT91SAM9260_BASE_US5 0xfffd8000 -#define AT91SAM9260_BASE_TCB1 0xfffdc000 -#define AT91SAM9260_BASE_TC3 0xfffdc000 -#define AT91SAM9260_BASE_TC4 0xfffdc040 -#define AT91SAM9260_BASE_TC5 0xfffdc080 -#define AT91SAM9260_BASE_ADC 0xfffe0000 -#define AT91_BASE_SYS 0xffffe800 - -/* - * System Peripherals (offset from AT91_BASE_SYS) - */ -#define AT91_ECC (0xffffe800 - AT91_BASE_SYS) -#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) -#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) -#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) -#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) -#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) - - -/* - * Internal Memory. - */ -#define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */ -#define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ - -#define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ -#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */ -#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ -#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */ - -#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */ - -#if 0 -/* - * PIO pin definitions (peripheral A/B multiplexing). - */ - -// TODO: Add - -#endif - -#endif diff --git a/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h b/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h deleted file mode 100644 index 78f6b4917b8b..000000000000 --- a/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91SAM9260 datasheet revision B. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9260_MATRIX_H -#define AT91SAM9260_MATRIX_H - -#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ -#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ -#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ -#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ -#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ -#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x04) /* Master Configuration Register 5 */ -#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91_MATRIX_ULBT_FOUR (2 << 0) -#define AT91_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) - -#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ -#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ -#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ -#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ -#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ -#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ -#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ -#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) -#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) - -#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ -#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ -#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ -#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ -#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ -#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ - -#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ -#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ - -#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */ -#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_CS1A_SMC (0 << 1) -#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_CS3A_SMC (0 << 3) -#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91_MATRIX_CS4A_SMC (0 << 4) -#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) -#define AT91_MATRIX_CS5A (1 << 5 ) /* Chip Select 5 Assignment */ -#define AT91_MATRIX_CS5A_SMC (0 << 5) -#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) -#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) - -#endif diff --git a/include/asm-arm/arch-at91rm9200/at91sam9261.h b/include/asm-arm/arch-at91rm9200/at91sam9261.h deleted file mode 100644 index 8d39672d5b82..000000000000 --- a/include/asm-arm/arch-at91rm9200/at91sam9261.h +++ /dev/null @@ -1,292 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/at91sam9261.h - * - * Copyright (C) SAN People - * - * Common definitions. - * Based on AT91SAM9261 datasheet revision E. (Preliminary) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9261_H -#define AT91SAM9261_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Peripherals */ -#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */ -#define AT91SAM9261_ID_US0 6 /* USART 0 */ -#define AT91SAM9261_ID_US1 7 /* USART 1 */ -#define AT91SAM9261_ID_US2 8 /* USART 2 */ -#define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */ -#define AT91SAM9261_ID_UDP 10 /* USB Device Port */ -#define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */ -#define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */ -#define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */ -#define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */ -#define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */ -#define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */ -#define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */ -#define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */ -#define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */ -#define AT91SAM9261_ID_UHP 20 /* USB Host port */ -#define AT91SAM9261_ID_LCDC 21 /* LDC Controller */ -#define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ - - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9261_BASE_TCB0 0xfffa0000 -#define AT91SAM9261_BASE_TC0 0xfffa0000 -#define AT91SAM9261_BASE_TC1 0xfffa0040 -#define AT91SAM9261_BASE_TC2 0xfffa0080 -#define AT91SAM9261_BASE_UDP 0xfffa4000 -#define AT91SAM9261_BASE_MCI 0xfffa8000 -#define AT91SAM9261_BASE_TWI 0xfffac000 -#define AT91SAM9261_BASE_US0 0xfffb0000 -#define AT91SAM9261_BASE_US1 0xfffb4000 -#define AT91SAM9261_BASE_US2 0xfffb8000 -#define AT91SAM9261_BASE_SSC0 0xfffbc000 -#define AT91SAM9261_BASE_SSC1 0xfffc0000 -#define AT91SAM9261_BASE_SSC2 0xfffc4000 -#define AT91SAM9261_BASE_SPI0 0xfffc8000 -#define AT91SAM9261_BASE_SPI1 0xfffcc000 -#define AT91_BASE_SYS 0xffffea00 - - -/* - * System Peripherals (offset from AT91_BASE_SYS) - */ -#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) -#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) -#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) -#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) - - -/* - * Internal Memory. - */ -#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */ - -#define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ - -#define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */ -#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */ - - -#if 0 -/* - * PIO pin definitions (peripheral A/B multiplexing). - */ -#define AT91_PA0_SPI0_MISO (1 << 0) /* A: SPI0 Master In Slave */ -#define AT91_PA0_MCDA0 (1 << 0) /* B: Multimedia Card A Data 0 */ -#define AT91_PA1_SPI0_MOSI (1 << 1) /* A: SPI0 Master Out Slave */ -#define AT91_PA1_MCCDA (1 << 1) /* B: Multimedia Card A Command */ -#define AT91_PA2_SPI0_SPCK (1 << 2) /* A: SPI0 Serial Clock */ -#define AT91_PA2_MCCK (1 << 2) /* B: Multimedia Card Clock */ -#define AT91_PA3_SPI0_NPCS0 (1 << 3) /* A: SPI0 Peripheral Chip Select 0 */ -#define AT91_PA4_SPI0_NPCS1 (1 << 4) /* A: SPI0 Peripheral Chip Select 1 */ -#define AT91_PA4_MCDA1 (1 << 4) /* B: Multimedia Card A Data 1 */ -#define AT91_PA5_SPI0_NPCS2 (1 << 5) /* A: SPI0 Peripheral Chip Select 2 */ -#define AT91_PA5_MCDA2 (1 << 5) /* B: Multimedia Card A Data 2 */ -#define AT91_PA6_SPI0_NPCS3 (1 << 6) /* A: SPI0 Peripheral Chip Select 3 */ -#define AT91_PA6_MCDA3 (1 << 6) /* B: Multimedia Card A Data 3 */ -#define AT91_PA7_TWD (1 << 7) /* A: TWI Two-wire Serial Data */ -#define AT91_PA7_PCK0 (1 << 7) /* B: PMC Programmable clock Output 0 */ -#define AT91_PA8_TWCK (1 << 8) /* A: TWI Two-wire Serial Clock */ -#define AT91_PA8_PCK1 (1 << 8) /* B: PMC Programmable clock Output 1 */ -#define AT91_PA9_DRXD (1 << 9) /* A: DBGU Debug Receive Data */ -#define AT91_PA9_PCK2 (1 << 9) /* B: PMC Programmable clock Output 2 */ -#define AT91_PA10_DTXD (1 << 10) /* A: DBGU Debug Transmit Data */ -#define AT91_PA10_PCK3 (1 << 10) /* B: PMC Programmable clock Output 3 */ -#define AT91_PA11_TSYNC (1 << 11) /* A: Trace Synchronization Signal */ -#define AT91_PA11_SCK1 (1 << 11) /* B: USART1 Serial Clock */ -#define AT91_PA12_TCLK (1 << 12) /* A: Trace Clock */ -#define AT91_PA12_RTS1 (1 << 12) /* B: USART1 Ready To Send */ -#define AT91_PA13_TPS0 (1 << 13) /* A: Trace ARM Pipeline Status 0 */ -#define AT91_PA13_CTS1 (1 << 13) /* B: USART1 Clear To Send */ -#define AT91_PA14_TPS1 (1 << 14) /* A: Trace ARM Pipeline Status 1 */ -#define AT91_PA14_SCK2 (1 << 14) /* B: USART2 Serial Clock */ -#define AT91_PA15_TPS2 (1 << 15) /* A: Trace ARM Pipeline Status 2 */ -#define AT91_PA15_RTS2 (1 << 15) /* B: USART2 Ready To Send */ -#define AT91_PA16_TPK0 (1 << 16) /* A: Trace Packet Port 0 */ -#define AT91_PA16_CTS2 (1 << 16) /* B: USART2 Clear To Send */ -#define AT91_PA17_TPK1 (1 << 17) /* A: Trace Packet Port 1 */ -#define AT91_PA17_TF1 (1 << 17) /* B: SSC1 Transmit Frame Sync */ -#define AT91_PA18_TPK2 (1 << 18) /* A: Trace Packet Port 2 */ -#define AT91_PA18_TK1 (1 << 18) /* B: SSC1 Transmit Clock */ -#define AT91_PA19_TPK3 (1 << 19) /* A: Trace Packet Port 3 */ -#define AT91_PA19_TD1 (1 << 19) /* B: SSC1 Transmit Data */ -#define AT91_PA20_TPK4 (1 << 20) /* A: Trace Packet Port 4 */ -#define AT91_PA20_RD1 (1 << 20) /* B: SSC1 Receive Data */ -#define AT91_PA21_TPK5 (1 << 21) /* A: Trace Packet Port 5 */ -#define AT91_PA21_RK1 (1 << 21) /* B: SSC1 Receive Clock */ -#define AT91_PA22_TPK6 (1 << 22) /* A: Trace Packet Port 6 */ -#define AT91_PA22_RF1 (1 << 22) /* B: SSC1 Receive Frame Sync */ -#define AT91_PA23_TPK7 (1 << 23) /* A: Trace Packet Port 7 */ -#define AT91_PA23_RTS0 (1 << 23) /* B: USART0 Ready To Send */ -#define AT91_PA24_TPK8 (1 << 24) /* A: Trace Packet Port 8 */ -#define AT91_PA24_SPI1_NPCS1 (1 << 24) /* B: SPI1 Peripheral Chip Select 1 */ -#define AT91_PA25_TPK9 (1 << 25) /* A: Trace Packet Port 9 */ -#define AT91_PA25_SPI1_NPCS2 (1 << 25) /* B: SPI1 Peripheral Chip Select 2 */ -#define AT91_PA26_TPK10 (1 << 26) /* A: Trace Packet Port 10 */ -#define AT91_PA26_SPI1_NPCS3 (1 << 26) /* B: SPI1 Peripheral Chip Select 3 */ -#define AT91_PA27_TPK11 (1 << 27) /* A: Trace Packet Port 11 */ -#define AT91_PA27_SPI0_NPCS1 (1 << 27) /* B: SPI0 Peripheral Chip Select 1 */ -#define AT91_PA28_TPK12 (1 << 28) /* A: Trace Packet Port 12 */ -#define AT91_PA28_SPI0_NPCS2 (1 << 28) /* B: SPI0 Peripheral Chip Select 2 */ -#define AT91_PA29_TPK13 (1 << 29) /* A: Trace Packet Port 13 */ -#define AT91_PA29_SPI0_NPCS3 (1 << 29) /* B: SPI0 Peripheral Chip Select 3 */ -#define AT91_PA30_TPK14 (1 << 30) /* A: Trace Packet Port 14 */ -#define AT91_PA30_A23 (1 << 30) /* B: Address Bus bit 23 */ -#define AT91_PA31_TPK15 (1 << 31) /* A: Trace Packet Port 15 */ -#define AT91_PA31_A24 (1 << 31) /* B: Address Bus bit 24 */ - -#define AT91_PB0_LCDVSYNC (1 << 0) /* A: LCD Vertical Synchronization */ -#define AT91_PB1_LCDHSYNC (1 << 1) /* A: LCD Horizontal Synchronization */ -#define AT91_PB2_LCDDOTCK (1 << 2) /* A: LCD Dot Clock */ -#define AT91_PB2_PCK0 (1 << 2) /* B: PMC Programmable clock Output 0 */ -#define AT91_PB3_LCDDEN (1 << 3) /* A: LCD Data Enable */ -#define AT91_PB4_LCDCC (1 << 4) /* A: LCD Contrast Control */ -#define AT91_PB4_LCDD2 (1 << 4) /* B: LCD Data Bus Bit 2 */ -#define AT91_PB5_LCDD0 (1 << 5) /* A: LCD Data Bus Bit 0 */ -#define AT91_PB5_LCDD3 (1 << 5) /* B: LCD Data Bus Bit 3 */ -#define AT91_PB6_LCDD1 (1 << 6) /* A: LCD Data Bus Bit 1 */ -#define AT91_PB6_LCDD4 (1 << 6) /* B: LCD Data Bus Bit 4 */ -#define AT91_PB7_LCDD2 (1 << 7) /* A: LCD Data Bus Bit 2 */ -#define AT91_PB7_LCDD5 (1 << 7) /* B: LCD Data Bus Bit 5 */ -#define AT91_PB8_LCDD3 (1 << 8) /* A: LCD Data Bus Bit 3 */ -#define AT91_PB8_LCDD6 (1 << 8) /* B: LCD Data Bus Bit 6 */ -#define AT91_PB9_LCDD4 (1 << 9) /* A: LCD Data Bus Bit 4 */ -#define AT91_PB9_LCDD7 (1 << 9) /* B: LCD Data Bus Bit 7 */ -#define AT91_PB10_LCDD5 (1 << 10) /* A: LCD Data Bus Bit 5 */ -#define AT91_PB10_LCDD10 (1 << 10) /* B: LCD Data Bus Bit 10 */ -#define AT91_PB11_LCDD6 (1 << 11) /* A: LCD Data Bus Bit 6 */ -#define AT91_PB11_LCDD11 (1 << 11) /* B: LCD Data Bus Bit 11 */ -#define AT91_PB12_LCDD7 (1 << 12) /* A: LCD Data Bus Bit 7 */ -#define AT91_PB12_LCDD12 (1 << 12) /* B: LCD Data Bus Bit 12 */ -#define AT91_PB13_LCDD8 (1 << 13) /* A: LCD Data Bus Bit 8 */ -#define AT91_PB13_LCDD13 (1 << 13) /* B: LCD Data Bus Bit 13 */ -#define AT91_PB14_LCDD9 (1 << 14) /* A: LCD Data Bus Bit 9 */ -#define AT91_PB14_LCDD14 (1 << 14) /* B: LCD Data Bus Bit 14 */ -#define AT91_PB15_LCDD10 (1 << 15) /* A: LCD Data Bus Bit 10 */ -#define AT91_PB15_LCDD15 (1 << 15) /* B: LCD Data Bus Bit 15 */ -#define AT91_PB16_LCDD11 (1 << 16) /* A: LCD Data Bus Bit 11 */ -#define AT91_PB16_LCDD19 (1 << 16) /* B: LCD Data Bus Bit 19 */ -#define AT91_PB17_LCDD12 (1 << 17) /* A: LCD Data Bus Bit 12 */ -#define AT91_PB17_LCDD20 (1 << 17) /* B: LCD Data Bus Bit 20 */ -#define AT91_PB18_LCDD13 (1 << 18) /* A: LCD Data Bus Bit 13 */ -#define AT91_PB18_LCDD21 (1 << 18) /* B: LCD Data Bus Bit 21 */ -#define AT91_PB19_LCDD14 (1 << 19) /* A: LCD Data Bus Bit 14 */ -#define AT91_PB19_LCDD22 (1 << 19) /* B: LCD Data Bus Bit 22 */ -#define AT91_PB20_LCDD15 (1 << 20) /* A: LCD Data Bus Bit 15 */ -#define AT91_PB20_LCDD23 (1 << 20) /* B: LCD Data Bus Bit 23 */ -#define AT91_PB21_TF0 (1 << 21) /* A: SSC0 Transmit Frame Sync */ -#define AT91_PB21_LCDD16 (1 << 21) /* B: LCD Data Bus Bit 16 */ -#define AT91_PB22_TK0 (1 << 22) /* A: SSC0 Transmit Clock */ -#define AT91_PB22_LCDD17 (1 << 22) /* B: LCD Data Bus Bit 17 */ -#define AT91_PB23_TD0 (1 << 23) /* A: SSC0 Transmit Data */ -#define AT91_PB23_LCDD18 (1 << 23) /* B: LCD Data Bus Bit 18 */ -#define AT91_PB24_RD0 (1 << 24) /* A: SSC0 Receive Data */ -#define AT91_PB24_LCDD19 (1 << 24) /* B: LCD Data Bus Bit 19 */ -#define AT91_PB25_RK0 (1 << 25) /* A: SSC0 Receive Clock */ -#define AT91_PB25_LCDD20 (1 << 25) /* B: LCD Data Bus Bit 20 */ -#define AT91_PB26_RF0 (1 << 26) /* A: SSC0 Receive Frame Sync */ -#define AT91_PB26_LCDD21 (1 << 26) /* B: LCD Data Bus Bit 21 */ -#define AT91_PB27_SPI1_NPCS1 (1 << 27) /* A: SPI1 Peripheral Chip Select 1 */ -#define AT91_PB27_LCDD22 (1 << 27) /* B: LCD Data Bus Bit 22 */ -#define AT91_PB28_SPI1_NPCS0 (1 << 28) /* A: SPI1 Peripheral Chip Select 0 */ -#define AT91_PB28_LCDD23 (1 << 28) /* B: LCD Data Bus Bit 23 */ -#define AT91_PB29_SPI1_SPCK (1 << 29) /* A: SPI1 Serial Clock */ -#define AT91_PB29_IRQ2 (1 << 29) /* B: Interrupt input 2 */ -#define AT91_PB30_SPI1_MISO (1 << 30) /* A: SPI1 Master In Slave */ -#define AT91_PB30_IRQ1 (1 << 30) /* B: Interrupt input 1 */ -#define AT91_PB31_SPI1_MOSI (1 << 31) /* A: SPI1 Master Out Slave */ -#define AT91_PB31_PCK2 (1 << 31) /* B: PMC Programmable clock Output 2 */ - -#define AT91_PC0_SMOE (1 << 0) /* A: SmartMedia Output Enable */ -#define AT91_PC0_NCS6 (1 << 0) /* B: Chip Select 6 */ -#define AT91_PC1_SMWE (1 << 1) /* A: SmartMedia Write Enable */ -#define AT91_PC1_NCS7 (1 << 1) /* B: Chip Select 7 */ -#define AT91_PC2_NWAIT (1 << 2) /* A: NWAIT */ -#define AT91_PC2_IRQ0 (1 << 2) /* B: Interrupt input 0 */ -#define AT91_PC3_A25_CFRNW (1 << 3) /* A: Address Bus[25] / Compact Flash Read Not Write */ -#define AT91_PC4_NCS4_CFCS0 (1 << 4) /* A: Chip Select 4 / CompactFlash Chip Select 0 */ -#define AT91_PC5_NCS5_CFCS1 (1 << 5) /* A: Chip Select 5 / CompactFlash Chip Select 1 */ -#define AT91_PC6_CFCE1 (1 << 6) /* A: CompactFlash Chip Enable 1 */ -#define AT91_PC7_CFCE2 (1 << 7) /* A: CompactFlash Chip Enable 2 */ -#define AT91_PC8_TXD0 (1 << 8) /* A: USART0 Transmit Data */ -#define AT91_PC8_PCK2 (1 << 8) /* B: PMC Programmable clock Output 2 */ -#define AT91_PC9_RXD0 (1 << 9) /* A: USART0 Receive Data */ -#define AT91_PC9_PCK3 (1 << 9) /* B: PMC Programmable clock Output 3 */ -#define AT91_PC10_RTS0 (1 << 10) /* A: USART0 Ready To Send */ -#define AT91_PC10_SCK0 (1 << 10) /* B: USART0 Serial Clock */ -#define AT91_PC11_CTS0 (1 << 11) /* A: USART0 Clear To Send */ -#define AT91_PC11_FIQ (1 << 11) /* B: AIC Fast Interrupt Input */ -#define AT91_PC12_TXD1 (1 << 12) /* A: USART1 Transmit Data */ -#define AT91_PC12_NCS6 (1 << 12) /* B: Chip Select 6 */ -#define AT91_PC13_RXD1 (1 << 13) /* A: USART1 Receive Data */ -#define AT91_PC13_NCS7 (1 << 13) /* B: Chip Select 7 */ -#define AT91_PC14_TXD2 (1 << 14) /* A: USART2 Transmit Data */ -#define AT91_PC14_SPI1_NPCS2 (1 << 14) /* B: SPI1 Peripheral Chip Select 2 */ -#define AT91_PC15_RXD2 (1 << 15) /* A: USART2 Receive Data */ -#define AT91_PC15_SPI1_NPCS3 (1 << 15) /* B: SPI1 Peripheral Chip Select 3 */ -#define AT91_PC16_D16 (1 << 16) /* A: Data Bus [16] */ -#define AT91_PC16_TCLK0 (1 << 16) /* B: Timer Counter 0 external clock input */ -#define AT91_PC17_D17 (1 << 17) /* A: Data Bus [17] */ -#define AT91_PC17_TCLK1 (1 << 17) /* B: Timer Counter 1 external clock input */ -#define AT91_PC18_D18 (1 << 18) /* A: Data Bus [18] */ -#define AT91_PC18_TCLK2 (1 << 18) /* B: Timer Counter 2 external clock input */ -#define AT91_PC19_D19 (1 << 19) /* A: Data Bus [19] */ -#define AT91_PC19_TIOA0 (1 << 19) /* B: Timer Counter 0 Multipurpose Timer I/O Pin A */ -#define AT91_PC20_D20 (1 << 20) /* A: Data Bus [20] */ -#define AT91_PC20_TIOB0 (1 << 20) /* B: Timer Counter 0 Multipurpose Timer I/O Pin B */ -#define AT91_PC21_D21 (1 << 21) /* A: Data Bus [21] */ -#define AT91_PC21_TIOA1 (1 << 21) /* B: Timer Counter 1 Multipurpose Timer I/O Pin A */ -#define AT91_PC22_D22 (1 << 22) /* A: Data Bus [22] */ -#define AT91_PC22_TIOB1 (1 << 22) /* B: Timer Counter 1 Multipurpose Timer I/O Pin B */ -#define AT91_PC23_D23 (1 << 23) /* A: Data Bus [23] */ -#define AT91_PC23_TIOA2 (1 << 23) /* B: Timer Counter 2 Multipurpose Timer I/O Pin A */ -#define AT91_PC24_D24 (1 << 24) /* A: Data Bus [24] */ -#define AT91_PC24_TIOB2 (1 << 24) /* B: Timer Counter 2 Multipurpose Timer I/O Pin B */ -#define AT91_PC25_D25 (1 << 25) /* A: Data Bus [25] */ -#define AT91_PC25_TF2 (1 << 25) /* B: SSC2 Transmit Frame Sync */ -#define AT91_PC26_D26 (1 << 26) /* A: Data Bus [26] */ -#define AT91_PC26_TK2 (1 << 26) /* B: SSC2 Transmit Clock */ -#define AT91_PC27_D27 (1 << 27) /* A: Data Bus [27] */ -#define AT91_PC27_TD2 (1 << 27) /* B: SSC2 Transmit Data */ -#define AT91_PC28_D28 (1 << 28) /* A: Data Bus [28] */ -#define AT91_PC28_RD2 (1 << 28) /* B: SSC2 Receive Data */ -#define AT91_PC29_D29 (1 << 29) /* A: Data Bus [29] */ -#define AT91_PC29_RK2 (1 << 29) /* B: SSC2 Receive Clock */ -#define AT91_PC30_D30 (1 << 30) /* A: Data Bus [30] */ -#define AT91_PC30_RF2 (1 << 30) /* B: SSC2 Receive Frame Sync */ -#define AT91_PC31_D31 (1 << 31) /* A: Data Bus [31] */ -#define AT91_PC31_PCK1 (1 << 31) /* B: PMC Programmable clock Output 1 */ -#endif - -#endif diff --git a/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h b/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h deleted file mode 100644 index ec88efabbe6c..000000000000 --- a/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91SAM9261 datasheet revision D. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9261_MATRIX_H -#define AT91SAM9261_MATRIX_H - -#define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */ -#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ - -#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */ -#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */ -#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C) /* Slave Configuration Register 2 */ -#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10) /* Slave Configuration Register 3 */ -#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14) /* Slave Configuration Register 4 */ -#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ - -#define AT91_MATRIX_TCR (AT91_MATRIX + 0x24) /* TCM Configuration Register */ -#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ -#define AT91_MATRIX_ITCM_0 (0 << 0) -#define AT91_MATRIX_ITCM_16 (5 << 0) -#define AT91_MATRIX_ITCM_32 (6 << 0) -#define AT91_MATRIX_ITCM_64 (7 << 0) -#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ -#define AT91_MATRIX_DTCM_0 (0 << 4) -#define AT91_MATRIX_DTCM_16 (5 << 4) -#define AT91_MATRIX_DTCM_32 (6 << 4) -#define AT91_MATRIX_DTCM_64 (7 << 4) - -#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */ -#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_CS1A_SMC (0 << 1) -#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_CS3A_SMC (0 << 3) -#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91_MATRIX_CS4A_SMC (0 << 4) -#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) -#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91_MATRIX_CS5A_SMC (0 << 5) -#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) -#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ - -#define AT91_MATRIX_USBPUCR (AT91_MATRIX + 0x34) /* USB Pad Pull-Up Control Register */ -#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */ - -#endif diff --git a/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h b/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h deleted file mode 100644 index 972e7531c7f4..000000000000 --- a/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/at91sam926x_mc.h - * - * Memory Controllers (SMC, SDRAMC) - System peripherals registers. - * Based on AT91SAM9261 datasheet revision D. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM926x_MC_H -#define AT91SAM926x_MC_H - -/* SDRAM Controller (SDRAMC) registers */ -#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */ -#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ -#define AT91_SDRAMC_MODE_NORMAL 0 -#define AT91_SDRAMC_MODE_NOP 1 -#define AT91_SDRAMC_MODE_PRECHARGE 2 -#define AT91_SDRAMC_MODE_LMR 3 -#define AT91_SDRAMC_MODE_REFRESH 4 -#define AT91_SDRAMC_MODE_EXT_LMR 5 -#define AT91_SDRAMC_MODE_DEEP 6 - -#define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */ -#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */ - -#define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */ -#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ -#define AT91_SDRAMC_NC_8 (0 << 0) -#define AT91_SDRAMC_NC_9 (1 << 0) -#define AT91_SDRAMC_NC_10 (2 << 0) -#define AT91_SDRAMC_NC_11 (3 << 0) -#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ -#define AT91_SDRAMC_NR_11 (0 << 2) -#define AT91_SDRAMC_NR_12 (1 << 2) -#define AT91_SDRAMC_NR_13 (2 << 2) -#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ -#define AT91_SDRAMC_NB_2 (0 << 4) -#define AT91_SDRAMC_NB_4 (1 << 4) -#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ -#define AT91_SDRAMC_CAS_1 (1 << 5) -#define AT91_SDRAMC_CAS_2 (2 << 5) -#define AT91_SDRAMC_CAS_3 (3 << 5) -#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */ -#define AT91_SDRAMC_DBW_32 (0 << 7) -#define AT91_SDRAMC_DBW_16 (1 << 7) -#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */ -#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */ -#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */ -#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */ -#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */ -#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */ - -#define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */ -#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */ -#define AT91_SDRAMC_LPCB_DISABLE 0 -#define AT91_SDRAMC_LPCB_SELF_REFRESH 1 -#define AT91_SDRAMC_LPCB_POWER_DOWN 2 -#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3 -#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */ -#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ -#define AT91_SDRAMC_DS (3 << 10) /* Drive Strenght */ -#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ -#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12) -#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12) -#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12) - -#define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */ -#define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */ -#define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */ -#define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */ -#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */ - -#define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */ -#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */ -#define AT91_SDRAMC_MD_SDRAM 0 -#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 - - -/* Static Memory Controller (SMC) registers */ -#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ -#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ -#define AT91_SMC_NWESETUP_(x) ((x) << 0) -#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */ -#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8) -#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */ -#define AT91_SMC_NRDSETUP_(x) ((x) << 16) -#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */ -#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24) - -#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ -#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */ -#define AT91_SMC_NWEPULSE_(x) ((x) << 0) -#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */ -#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8) -#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */ -#define AT91_SMC_NRDPULSE_(x) ((x) << 16) -#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */ -#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24) - -#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ -#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */ -#define AT91_SMC_NWECYCLE_(x) ((x) << 0) -#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ -#define AT91_SMC_NRDCYCLE_(x) ((x) << 16) - -#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ -#define AT91_SMC_READMODE (1 << 0) /* Read Mode */ -#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ -#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ -#define AT91_SMC_EXNWMODE_DISABLE (0 << 4) -#define AT91_SMC_EXNWMODE_FROZEN (2 << 4) -#define AT91_SMC_EXNWMODE_READY (3 << 4) -#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ -#define AT91_SMC_BAT_SELECT (0 << 8) -#define AT91_SMC_BAT_WRITE (1 << 8) -#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */ -#define AT91_SMC_DBW_8 (0 << 12) -#define AT91_SMC_DBW_16 (1 << 12) -#define AT91_SMC_DBW_32 (2 << 12) -#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */ -#define AT91_SMC_TDF_(x) ((x) << 16) -#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */ -#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */ -#define AT91_SMC_PS (3 << 28) /* Page Size */ -#define AT91_SMC_PS_4 (0 << 28) -#define AT91_SMC_PS_8 (1 << 28) -#define AT91_SMC_PS_16 (2 << 28) -#define AT91_SMC_PS_32 (3 << 28) - -#endif diff --git a/include/asm-arm/arch-at91rm9200/board.h b/include/asm-arm/arch-at91rm9200/board.h deleted file mode 100644 index f3a974ba3b51..000000000000 --- a/include/asm-arm/arch-at91rm9200/board.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/board.h - * - * Copyright (C) 2005 HP Labs - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -/* - * These are data structures found in platform_device.dev.platform_data, - * and describing board-specific data needed by drivers. For example, - * which pin is used for a given GPIO role. - * - * In 2.6, drivers should strongly avoid board-specific knowledge so - * that supporting new boards normally won't require driver patches. - * Most board-specific knowledge should be in arch/.../board-*.c files. - */ - -#ifndef __ASM_ARCH_BOARD_H -#define __ASM_ARCH_BOARD_H - -#include -#include -#include - - /* USB Device */ -struct at91_udc_data { - u8 vbus_pin; /* high == host powering us */ - u8 pullup_pin; /* high == D+ pulled up */ -}; -extern void __init at91_add_device_udc(struct at91_udc_data *data); - - /* Compact Flash */ -struct at91_cf_data { - u8 irq_pin; /* I/O IRQ */ - u8 det_pin; /* Card detect */ - u8 vcc_pin; /* power switching */ - u8 rst_pin; /* card reset */ - u8 chipselect; /* EBI Chip Select number */ -}; -extern void __init at91_add_device_cf(struct at91_cf_data *data); - - /* MMC / SD */ -struct at91_mmc_data { - u8 det_pin; /* card detect IRQ */ - unsigned slot_b:1; /* uses Slot B */ - unsigned wire4:1; /* (SD) supports DAT0..DAT3 */ - u8 wp_pin; /* (SD) writeprotect detect */ - u8 vcc_pin; /* power switching (high == on) */ -}; -extern void __init at91_add_device_mmc(struct at91_mmc_data *data); - - /* Ethernet */ -struct at91_eth_data { - u8 phy_irq_pin; /* PHY IRQ */ - u8 is_rmii; /* using RMII interface? */ -}; -extern void __init at91_add_device_eth(struct at91_eth_data *data); - -#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) -#define eth_platform_data at91_eth_data -#endif - - /* USB Host */ -struct at91_usbh_data { - u8 ports; /* number of ports on root hub */ -}; -extern void __init at91_add_device_usbh(struct at91_usbh_data *data); - - /* NAND / SmartMedia */ -struct at91_nand_data { - u8 enable_pin; /* chip enable */ - u8 det_pin; /* card detect */ - u8 rdy_pin; /* ready/busy */ - u8 ale; /* address line number connected to ALE */ - u8 cle; /* address line number connected to CLE */ - u8 bus_width_16; /* buswidth is 16 bit */ - struct mtd_partition* (*partition_info)(int, int*); -}; -extern void __init at91_add_device_nand(struct at91_nand_data *data); - - /* I2C*/ -extern void __init at91_add_device_i2c(void); - - /* SPI */ -extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices); - - /* Serial */ -struct at91_uart_config { - unsigned short console_tty; /* tty number of serial console */ - unsigned short nr_tty; /* number of serial tty's */ - short tty_map[]; /* map UART to tty number */ -}; -extern struct platform_device *atmel_default_console_device; -extern void __init at91_init_serial(struct at91_uart_config *config); - -struct atmel_uart_data { - short use_dma_tx; /* use transmit DMA? */ - short use_dma_rx; /* use receive DMA? */ - void __iomem *regs; /* virtual base address, if any */ -}; -extern void __init at91_add_device_serial(void); - - /* LEDs */ -extern u8 at91_leds_cpu; -extern u8 at91_leds_timer; -extern void __init at91_init_leds(u8 cpu_led, u8 timer_led); - -#endif diff --git a/include/asm-arm/arch-at91rm9200/cpu.h b/include/asm-arm/arch-at91rm9200/cpu.h deleted file mode 100644 index 6f8d09b08692..000000000000 --- a/include/asm-arm/arch-at91rm9200/cpu.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/cpu.h - * - * Copyright (C) 2006 SAN People - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ - -#ifndef __ASM_ARCH_CPU_H -#define __ASM_ARCH_CPU_H - -#include -#include - - -#define ARCH_ID_AT91RM9200 0x09290780 -#define ARCH_ID_AT91SAM9260 0x019803a0 -#define ARCH_ID_AT91SAM9261 0x019703a0 - - -static inline unsigned long at91_cpu_identify(void) -{ - return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); -} - - -#ifdef CONFIG_ARCH_AT91RM9200 -#define cpu_is_at91rm9200() (at91_cpu_identify() == ARCH_ID_AT91RM9200) -#else -#define cpu_is_at91rm9200() (0) -#endif - -#ifdef CONFIG_ARCH_AT91SAM9260 -#define cpu_is_at91sam9260() (at91_cpu_identify() == ARCH_ID_AT91SAM9260) -#else -#define cpu_is_at91sam9260() (0) -#endif - -#ifdef CONFIG_ARCH_AT91SAM9261 -#define cpu_is_at91sam9261() (at91_cpu_identify() == ARCH_ID_AT91SAM9261) -#else -#define cpu_is_at91sam9261() (0) -#endif - -#endif diff --git a/include/asm-arm/arch-at91rm9200/debug-macro.S b/include/asm-arm/arch-at91rm9200/debug-macro.S deleted file mode 100644 index 85cdadf26634..000000000000 --- a/include/asm-arm/arch-at91rm9200/debug-macro.S +++ /dev/null @@ -1,39 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/debug-macro.S - * - * Copyright (C) 2003-2005 SAN People - * - * Debugging macro include header - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - -#include -#include - - .macro addruart,rx - mrc p15, 0, \rx, c1, c0 - tst \rx, #1 @ MMU enabled? - ldreq \rx, =AT91_BASE_SYS @ System peripherals (phys address) - ldrne \rx, =AT91_VA_BASE_SYS @ System peripherals (virt address) - .endm - - .macro senduart,rd,rx - strb \rd, [\rx, #AT91_DBGU_THR] @ Write to Transmitter Holding Register - .endm - - .macro waituart,rd,rx -1001: ldr \rd, [\rx, #AT91_DBGU_SR] @ Read Status Register - tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit - beq 1001b - .endm - - .macro busyuart,rd,rx -1001: ldr \rd, [\rx, #AT91_DBGU_SR] @ Read Status Register - tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete - beq 1001b - .endm - diff --git a/include/asm-arm/arch-at91rm9200/dma.h b/include/asm-arm/arch-at91rm9200/dma.h deleted file mode 100644 index 22c1dfdd8da3..000000000000 --- a/include/asm-arm/arch-at91rm9200/dma.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/dma.h - * - * Copyright (C) 2003 SAN People - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ diff --git a/include/asm-arm/arch-at91rm9200/entry-macro.S b/include/asm-arm/arch-at91rm9200/entry-macro.S deleted file mode 100644 index 57248a796472..000000000000 --- a/include/asm-arm/arch-at91rm9200/entry-macro.S +++ /dev/null @@ -1,26 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/entry-macro.S - * - * Copyright (C) 2003-2005 SAN People - * - * Low-level IRQ helper macros for AT91RM9200 platforms - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include - - .macro disable_fiq - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \base, =(AT91_VA_BASE_SYS) @ base virtual address of SYS peripherals - ldr \irqnr, [\base, #AT91_AIC_IVR] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt) - ldr \irqstat, [\base, #AT91_AIC_ISR] @ read interrupt source number - teq \irqstat, #0 @ ISR is 0 when no current interrupt, or spurious interrupt - streq \tmp, [\base, #AT91_AIC_EOICR] @ not going to be handled further, then ACK it now. - .endm - diff --git a/include/asm-arm/arch-at91rm9200/gpio.h b/include/asm-arm/arch-at91rm9200/gpio.h deleted file mode 100644 index a011d27876a2..000000000000 --- a/include/asm-arm/arch-at91rm9200/gpio.h +++ /dev/null @@ -1,199 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/gpio.h - * - * Copyright (C) 2005 HP Labs - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ - -#ifndef __ASM_ARCH_AT91RM9200_GPIO_H -#define __ASM_ARCH_AT91RM9200_GPIO_H - -#include - -#define PIN_BASE NR_AIC_IRQS - -#define MAX_GPIO_BANKS 4 - -/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */ - -#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0) -#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1) -#define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2) -#define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3) -#define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4) - -#define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5) -#define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6) -#define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7) -#define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8) -#define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9) - -#define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10) -#define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11) -#define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12) -#define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13) -#define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14) - -#define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15) -#define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16) -#define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17) -#define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18) -#define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19) - -#define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20) -#define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21) -#define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22) -#define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23) -#define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24) - -#define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25) -#define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26) -#define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27) -#define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28) -#define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29) - -#define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30) -#define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31) - -#define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0) -#define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1) -#define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2) -#define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3) -#define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4) - -#define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5) -#define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6) -#define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7) -#define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8) -#define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9) - -#define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10) -#define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11) -#define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12) -#define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13) -#define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14) - -#define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15) -#define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16) -#define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17) -#define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18) -#define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19) - -#define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20) -#define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21) -#define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22) -#define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23) -#define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24) - -#define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25) -#define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26) -#define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27) -#define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28) -#define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29) - -#define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30) -#define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31) - -#define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0) -#define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1) -#define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2) -#define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3) -#define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4) - -#define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5) -#define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6) -#define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7) -#define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8) -#define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9) - -#define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10) -#define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11) -#define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12) -#define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13) -#define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14) - -#define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15) -#define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16) -#define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17) -#define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18) -#define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19) - -#define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20) -#define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21) -#define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22) -#define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23) -#define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24) - -#define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25) -#define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26) -#define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27) -#define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28) -#define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29) - -#define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30) -#define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31) - -#define AT91_PIN_PD0 (PIN_BASE + 0x60 + 0) -#define AT91_PIN_PD1 (PIN_BASE + 0x60 + 1) -#define AT91_PIN_PD2 (PIN_BASE + 0x60 + 2) -#define AT91_PIN_PD3 (PIN_BASE + 0x60 + 3) -#define AT91_PIN_PD4 (PIN_BASE + 0x60 + 4) - -#define AT91_PIN_PD5 (PIN_BASE + 0x60 + 5) -#define AT91_PIN_PD6 (PIN_BASE + 0x60 + 6) -#define AT91_PIN_PD7 (PIN_BASE + 0x60 + 7) -#define AT91_PIN_PD8 (PIN_BASE + 0x60 + 8) -#define AT91_PIN_PD9 (PIN_BASE + 0x60 + 9) - -#define AT91_PIN_PD10 (PIN_BASE + 0x60 + 10) -#define AT91_PIN_PD11 (PIN_BASE + 0x60 + 11) -#define AT91_PIN_PD12 (PIN_BASE + 0x60 + 12) -#define AT91_PIN_PD13 (PIN_BASE + 0x60 + 13) -#define AT91_PIN_PD14 (PIN_BASE + 0x60 + 14) - -#define AT91_PIN_PD15 (PIN_BASE + 0x60 + 15) -#define AT91_PIN_PD16 (PIN_BASE + 0x60 + 16) -#define AT91_PIN_PD17 (PIN_BASE + 0x60 + 17) -#define AT91_PIN_PD18 (PIN_BASE + 0x60 + 18) -#define AT91_PIN_PD19 (PIN_BASE + 0x60 + 19) - -#define AT91_PIN_PD20 (PIN_BASE + 0x60 + 20) -#define AT91_PIN_PD21 (PIN_BASE + 0x60 + 21) -#define AT91_PIN_PD22 (PIN_BASE + 0x60 + 22) -#define AT91_PIN_PD23 (PIN_BASE + 0x60 + 23) -#define AT91_PIN_PD24 (PIN_BASE + 0x60 + 24) - -#define AT91_PIN_PD25 (PIN_BASE + 0x60 + 25) -#define AT91_PIN_PD26 (PIN_BASE + 0x60 + 26) -#define AT91_PIN_PD27 (PIN_BASE + 0x60 + 27) -#define AT91_PIN_PD28 (PIN_BASE + 0x60 + 28) -#define AT91_PIN_PD29 (PIN_BASE + 0x60 + 29) - -#define AT91_PIN_PD30 (PIN_BASE + 0x60 + 30) -#define AT91_PIN_PD31 (PIN_BASE + 0x60 + 31) - -#ifndef __ASSEMBLY__ -/* setup setup routines, called from board init or driver probe() */ -extern int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup); -extern int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup); -extern int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup); -extern int __init_or_module at91_set_gpio_output(unsigned pin, int value); -extern int __init_or_module at91_set_deglitch(unsigned pin, int is_on); -extern int __init_or_module at91_set_multi_drive(unsigned pin, int is_on); - -/* callable at any time */ -extern int at91_set_gpio_value(unsigned pin, int value); -extern int at91_get_gpio_value(unsigned pin); - -/* callable only from core power-management code */ -extern void at91_gpio_suspend(void); -extern void at91_gpio_resume(void); -#endif - -#endif - diff --git a/include/asm-arm/arch-at91rm9200/hardware.h b/include/asm-arm/arch-at91rm9200/hardware.h deleted file mode 100644 index 9ea5bfe06320..000000000000 --- a/include/asm-arm/arch-at91rm9200/hardware.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/hardware.h - * - * Copyright (C) 2003 SAN People - * Copyright (C) 2003 ATMEL - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include - -#if defined(CONFIG_ARCH_AT91RM9200) -#include -#elif defined(CONFIG_ARCH_AT91SAM9260) -#include -#elif defined(CONFIG_ARCH_AT91SAM9261) -#include -#else -#error "Unsupported AT91 processor" -#endif - - -/* - * Remap the peripherals from address 0xFFFA0000 .. 0xFFFFFFFF - * to 0xFEFA0000 .. 0xFF000000. (384Kb) - */ -#define AT91_IO_PHYS_BASE 0xFFFA0000 -#define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1) -#define AT91_IO_VIRT_BASE (0xFF000000 - AT91_IO_SIZE) - - /* Convert a physical IO address to virtual IO address */ -#define AT91_IO_P2V(x) ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE) - -/* - * Virtual to Physical Address mapping for IO devices. - */ -#define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS) -#define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91RM9200_BASE_EMAC) - - /* Internal SRAM is mapped below the IO devices */ -#define AT91_SRAM_MAX SZ_1M -#define AT91_VIRT_BASE (AT91_IO_VIRT_BASE - AT91_SRAM_MAX) - -/* Serial ports */ -#define ATMEL_MAX_UART 7 /* 6 USART3's and one DBGU port (SAM9260) */ - -/* External Memory Map */ -#define AT91_CHIPSELECT_0 0x10000000 -#define AT91_CHIPSELECT_1 0x20000000 -#define AT91_CHIPSELECT_2 0x30000000 -#define AT91_CHIPSELECT_3 0x40000000 -#define AT91_CHIPSELECT_4 0x50000000 -#define AT91_CHIPSELECT_5 0x60000000 -#define AT91_CHIPSELECT_6 0x70000000 -#define AT91_CHIPSELECT_7 0x80000000 - -/* SDRAM */ -#define AT91_SDRAM_BASE AT91_CHIPSELECT_1 - -/* Clocks */ -#define AT91_SLOW_CLOCK 32768 /* slow clock */ - -#ifndef __ASSEMBLY__ -#include - -static inline unsigned int at91_sys_read(unsigned int reg_offset) -{ - void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; - - return __raw_readl(addr + reg_offset); -} - -static inline void at91_sys_write(unsigned int reg_offset, unsigned long value) -{ - void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; - - __raw_writel(value, addr + reg_offset); -} -#endif - -#endif diff --git a/include/asm-arm/arch-at91rm9200/io.h b/include/asm-arm/arch-at91rm9200/io.h deleted file mode 100644 index 88fd1bebcef3..000000000000 --- a/include/asm-arm/arch-at91rm9200/io.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/io.h - * - * Copyright (C) 2003 SAN People - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_IO_H -#define __ASM_ARCH_IO_H - -#include - -#define IO_SPACE_LIMIT 0xFFFFFFFF - -#define __io(a) ((void __iomem *)(a)) -#define __mem_pci(a) (a) - - -#endif diff --git a/include/asm-arm/arch-at91rm9200/irqs.h b/include/asm-arm/arch-at91rm9200/irqs.h deleted file mode 100644 index c0679eaefaf2..000000000000 --- a/include/asm-arm/arch-at91rm9200/irqs.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/irqs.h - * - * Copyright (C) 2004 SAN People - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - -#include - -#define NR_AIC_IRQS 32 - - -/* - * Acknowledge interrupt with AIC after interrupt has been handled. - * (by kernel/irq.c) - */ -#define irq_finish(irq) do { at91_sys_write(AT91_AIC_EOICR, 0); } while (0) - - -/* - * IRQ interrupt symbols are the AT91xxx_ID_* symbols - * for IRQs handled directly through the AIC, or else the AT91_PIN_* - * symbols in gpio.h for ones handled indirectly as GPIOs. - * We make provision for 4 banks of GPIO. - */ -#define NR_IRQS (NR_AIC_IRQS + (4 * 32)) - -#endif diff --git a/include/asm-arm/arch-at91rm9200/memory.h b/include/asm-arm/arch-at91rm9200/memory.h deleted file mode 100644 index f985069e6d01..000000000000 --- a/include/asm-arm/arch-at91rm9200/memory.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/memory.h - * - * Copyright (C) 2004 SAN People - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -#include - -#define PHYS_OFFSET (AT91_SDRAM_BASE) - - -/* - * Virtual view <-> DMA view memory address translations - * virt_to_bus: Used to translate the virtual address to an - * address suitable to be passed to set_dma_addr - * bus_to_virt: Used to convert an address for DMA operations - * to an address that the kernel can use. - */ -#define __virt_to_bus(x) __virt_to_phys(x) -#define __bus_to_virt(x) __phys_to_virt(x) - -#endif diff --git a/include/asm-arm/arch-at91rm9200/system.h b/include/asm-arm/arch-at91rm9200/system.h deleted file mode 100644 index 9c67130603b2..000000000000 --- a/include/asm-arm/arch-at91rm9200/system.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/system.h - * - * Copyright (C) 2003 SAN People - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_SYSTEM_H -#define __ASM_ARCH_SYSTEM_H - -#include -#include -#include - -static inline void arch_idle(void) -{ - /* - * Disable the processor clock. The processor will be automatically - * re-enabled by an interrupt or by a reset. - */ -// at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK); - - /* - * Set the processor (CP15) into 'Wait for Interrupt' mode. - * Unlike disabling the processor clock via the PMC (above) - * this allows the processor to be woken via JTAG. - */ - cpu_do_idle(); -} - -void (*at91_arch_reset)(void); - -static inline void arch_reset(char mode) -{ - /* call the CPU-specific reset function */ - if (at91_arch_reset) - (at91_arch_reset)(); -} - -#endif diff --git a/include/asm-arm/arch-at91rm9200/timex.h b/include/asm-arm/arch-at91rm9200/timex.h deleted file mode 100644 index faeca45a8d44..000000000000 --- a/include/asm-arm/arch-at91rm9200/timex.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/timex.h - * - * Copyright (C) 2003 SAN People - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_TIMEX_H -#define __ASM_ARCH_TIMEX_H - -#include - -#if defined(CONFIG_ARCH_AT91RM9200) - -#define CLOCK_TICK_RATE (AT91_SLOW_CLOCK) - -#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9261) - -#define AT91SAM9_MASTER_CLOCK 99300000 -#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) - -#endif - -#endif diff --git a/include/asm-arm/arch-at91rm9200/uncompress.h b/include/asm-arm/arch-at91rm9200/uncompress.h deleted file mode 100644 index 34b4b93fa015..000000000000 --- a/include/asm-arm/arch-at91rm9200/uncompress.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/uncompress.h - * - * Copyright (C) 2003 SAN People - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_UNCOMPRESS_H -#define __ASM_ARCH_UNCOMPRESS_H - -#include -#include - -/* - * The following code assumes the serial port has already been - * initialized by the bootloader. If you didn't setup a port in - * your bootloader then nothing will appear (which might be desired). - * - * This does not append a newline - */ -static void putc(int c) -{ - void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ - - while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY)) - barrier(); - __raw_writel(c, sys + AT91_DBGU_THR); -} - -static inline void flush(void) -{ - void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ - - /* wait for transmission to complete */ - while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXEMPTY)) - barrier(); -} - -#define arch_decomp_setup() - -#define arch_decomp_wdog() - -#endif diff --git a/include/asm-arm/arch-at91rm9200/vmalloc.h b/include/asm-arm/arch-at91rm9200/vmalloc.h deleted file mode 100644 index 0a23b8c562b9..000000000000 --- a/include/asm-arm/arch-at91rm9200/vmalloc.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/vmalloc.h - * - * Copyright (C) 2003 SAN People - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_VMALLOC_H -#define __ASM_ARCH_VMALLOC_H - -#define VMALLOC_END (AT91_VIRT_BASE & PGDIR_MASK) - -#endif diff --git a/include/asm-avr32/arch-at32ap/at91_pdc.h b/include/asm-avr32/arch-at32ap/at91_pdc.h index 79d6e02fa45e..a54adf52c65d 100644 --- a/include/asm-avr32/arch-at32ap/at91_pdc.h +++ b/include/asm-avr32/arch-at32ap/at91_pdc.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-at91rm9200/at91_pdc.h + * include/asm-arm/arch-at91/at91_pdc.h * * Copyright (C) 2005 Ivan Kokshaysky * Copyright (C) SAN People