From: Rui Salvaterra Date: Tue, 30 Mar 2021 22:59:49 +0000 (+0100) Subject: ramips/mt7621: drop the timer recalibration patch X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=9c3b2d7ff755216a93d0ffa7d0375007cb7d3294;p=openwrt%2Fstaging%2Fzorun.git ramips/mt7621: drop the timer recalibration patch We've been carrying this patch for many years [1], in order to fix a timer calibration issue on MT7621. Turns out, after retesting with a recent kernel (Linux 5.10), the system works perfectly fine without it (no rcu_sched stalls or inconsistent BogoMIPS values across CPUs). Manually refreshed: 322-mt7621-fix-cpu-clk-add-clkdev.patch 323-mt7621-memory-detect.patch [1] https://git.openwrt.org/?p=openwrt/openwrt.git;a=commitdiff;h=6f4a903533361a2906a4d94ac6f597cd9c6c47bc Suggested-by: Ilya Lipnitskiy Tested-by: Donald Hoskins Signed-off-by: Rui Salvaterra --- diff --git a/target/linux/ramips/patches-5.10/321-mt7621-timer.patch b/target/linux/ramips/patches-5.10/321-mt7621-timer.patch deleted file mode 100644 index 08d5935eb0..0000000000 --- a/target/linux/ramips/patches-5.10/321-mt7621-timer.patch +++ /dev/null @@ -1,87 +0,0 @@ ---- a/arch/mips/ralink/mt7621.c -+++ b/arch/mips/ralink/mt7621.c -@@ -9,6 +9,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -16,6 +17,7 @@ - #include - #include - #include -+#include - - #include - -@@ -161,6 +163,58 @@ bool plat_cpu_core_present(int core) - return true; - } - -+#define LPS_PREC 8 -+/* -+* Re-calibration lpj(loop-per-jiffy). -+* (derived from kernel/calibrate.c) -+*/ -+static int udelay_recal(void) -+{ -+ unsigned int i, lpj = 0; -+ unsigned long ticks, loopbit; -+ int lps_precision = LPS_PREC; -+ -+ lpj = (1<<12); -+ -+ while ((lpj <<= 1) != 0) { -+ /* wait for "start of" clock tick */ -+ ticks = jiffies; -+ while (ticks == jiffies) -+ /* nothing */; -+ -+ /* Go .. */ -+ ticks = jiffies; -+ __delay(lpj); -+ ticks = jiffies - ticks; -+ if (ticks) -+ break; -+ } -+ -+ /* -+ * Do a binary approximation to get lpj set to -+ * equal one clock (up to lps_precision bits) -+ */ -+ lpj >>= 1; -+ loopbit = lpj; -+ while (lps_precision-- && (loopbit >>= 1)) { -+ lpj |= loopbit; -+ ticks = jiffies; -+ while (ticks == jiffies) -+ /* nothing */; -+ ticks = jiffies; -+ __delay(lpj); -+ if (jiffies != ticks) /* longer than 1 tick */ -+ lpj &= ~loopbit; -+ } -+ printk(KERN_INFO "%d CPUs re-calibrate udelay(lpj = %d)\n", NR_CPUS, lpj); -+ -+ for(i=0; i< NR_CPUS; i++) -+ cpu_data[i].udelay_val = lpj; -+ -+ return 0; -+} -+device_initcall(udelay_recal); -+ - void prom_soc_init(struct ralink_soc_info *soc_info) - { - void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE); ---- a/arch/mips/ralink/Kconfig -+++ b/arch/mips/ralink/Kconfig -@@ -62,6 +62,7 @@ choice - select CLKSRC_MIPS_GIC - select HAVE_PCI if PCI_MT7621 - select SOC_BUS -+ select GENERIC_CLOCKEVENTS_BROADCAST - endchoice - - choice diff --git a/target/linux/ramips/patches-5.10/322-mt7621-fix-cpu-clk-add-clkdev.patch b/target/linux/ramips/patches-5.10/322-mt7621-fix-cpu-clk-add-clkdev.patch index 723c628790..be5fee54b2 100644 --- a/target/linux/ramips/patches-5.10/322-mt7621-fix-cpu-clk-add-clkdev.patch +++ b/target/linux/ramips/patches-5.10/322-mt7621-fix-cpu-clk-add-clkdev.patch @@ -36,10 +36,10 @@ #define MT7621_DDR2_SIZE_MAX 256 --- a/arch/mips/ralink/mt7621.c +++ b/arch/mips/ralink/mt7621.c -@@ -10,6 +10,10 @@ +@@ -9,6 +9,10 @@ + #include #include #include - #include +#include +#include +#include @@ -47,15 +47,15 @@ #include #include -@@ -18,6 +22,7 @@ +@@ -16,6 +20,7 @@ + #include #include #include - #include +#include #include -@@ -108,11 +113,89 @@ static struct rt2880_pmx_group mt7621_pi +@@ -106,11 +111,89 @@ static struct rt2880_pmx_group mt7621_pi { 0 } }; diff --git a/target/linux/ramips/patches-5.10/323-mt7621-memory-detect.patch b/target/linux/ramips/patches-5.10/323-mt7621-memory-detect.patch index 07c7588661..9f80d02638 100644 --- a/target/linux/ramips/patches-5.10/323-mt7621-memory-detect.patch +++ b/target/linux/ramips/patches-5.10/323-mt7621-memory-detect.patch @@ -44,10 +44,10 @@ Signed-off-by: Chuanhong Guo #define MT7621_CHIP_NAME1 0x20203132 --- a/arch/mips/ralink/mt7621.c +++ b/arch/mips/ralink/mt7621.c -@@ -10,11 +10,13 @@ +@@ -9,11 +9,13 @@ + #include #include #include - #include +#include #include #include @@ -58,7 +58,7 @@ Signed-off-by: Chuanhong Guo #include #include #include -@@ -57,6 +59,8 @@ +@@ -55,6 +57,8 @@ #define MT7621_GPIO_MODE_SDHCI_SHIFT 18 #define MT7621_GPIO_MODE_SDHCI_GPIO 1 @@ -67,7 +67,7 @@ Signed-off-by: Chuanhong Guo static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) }; static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) }; static struct rt2880_pmx_func uart3_grp[] = { -@@ -141,6 +145,26 @@ static struct clk *__init mt7621_add_sys +@@ -139,6 +143,26 @@ static struct clk *__init mt7621_add_sys return clk; } @@ -94,7 +94,7 @@ Signed-off-by: Chuanhong Guo void __init ralink_clk_init(void) { u32 syscfg, xtal_sel, clkcfg, clk_sel, curclk, ffiv, ffrac; -@@ -346,10 +370,7 @@ void prom_soc_init(struct ralink_soc_inf +@@ -292,10 +316,7 @@ void prom_soc_init(struct ralink_soc_inf (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK, (rev & CHIP_REV_ECO_MASK));