From: Hamish Guthrie <hcg@openwrt.org>
Date: Wed, 9 May 2007 08:52:32 +0000 (+0000)
Subject: Corrected inverted DCD/DTR logic
X-Git-Tag: reboot~29295
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=9b27055a6cb9ff18de3e9402b81ab674f491ba89;p=openwrt%2Fstaging%2Flynxis.git

Corrected inverted DCD/DTR logic

SVN-Revision: 7145
---

diff --git a/target/linux/at91-2.6/patches/008-fdl-serial.patch b/target/linux/at91-2.6/patches/008-fdl-serial.patch
index 2260ffb6fe..3796915972 100644
--- a/target/linux/at91-2.6/patches/008-fdl-serial.patch
+++ b/target/linux/at91-2.6/patches/008-fdl-serial.patch
@@ -10,9 +10,9 @@
 +			 * USART 0 - Drive DTR and RI pins manually
 +			 */
 +			if (mctrl & TIOCM_DTR)
-+				at91_set_gpio_value(AT91_PIN_PA19, 0);
++				at91_set_gpio_value(AT91_PIN_PB6, 0);
 +			else
-+				at91_set_gpio_value(AT91_PIN_PA19, 1);
++				at91_set_gpio_value(AT91_PIN_PB6, 1);
 +			if (mctrl & TIOCM_RI)
 +				at91_set_gpio_value(AT91_PIN_PB7, 0);
 +			else
@@ -25,9 +25,9 @@
 +		 */
 +		if (port->mapbase == AT91RM9200_BASE_US3) {
 +			if (mctrl & TIOCM_DTR)
-+				at91_set_gpio_value(AT91_PIN_PA24, 0);
++				at91_set_gpio_value(AT91_PIN_PB29, 0);
 +			else
-+				at91_set_gpio_value(AT91_PIN_PA24, 1);
++				at91_set_gpio_value(AT91_PIN_PB29, 1);
 +			if (mctrl & TIOCM_RI)
 +				at91_set_gpio_value(AT91_PIN_PB2, 0);
 +			else
@@ -60,10 +60,10 @@
 +	 * Read the GPIO's for the FDL VersaLink special case
 +	 */
 +	if (port->mapbase == AT91RM9200_BASE_US0)
-+		if (!(at91_get_gpio_value(AT91_PIN_PB6)))
++		if (!(at91_get_gpio_value(AT91_PIN_PA19)))
 +			ret |= TIOCM_CD;
 +	if (port->mapbase == AT91RM9200_BASE_US3)
-+		if (!(at91_get_gpio_value(AT91_PIN_PB29)))
++		if (!(at91_get_gpio_value(AT91_PIN_PA24)))
 +			ret |= TIOCM_CD;
 +
  	return ret;