From: Aaron Liu Date: Fri, 9 Aug 2019 15:34:40 +0000 (-0500) Subject: drm/amdgpu/powerplay: add power up/down SDMA interfaces for renoir X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=97222cfac7740ba93c2c17f15db5d7184c6ab836;p=openwrt%2Fstaging%2Fblogic.git drm/amdgpu/powerplay: add power up/down SDMA interfaces for renoir 1.Implement PowerUpSDMA/PowerDownSDMA interfaces in the swSMU for renoir 2.adjust smu ip block ahead of gfx&sdma ip block Signed-off-by: Aaron Liu Reviewed-by: Huang Rui Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 7fbc6d95d910..fa1bf53f7f91 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -760,10 +760,10 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); - amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); - amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); if (is_support_sw_smu(adev)) amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); + amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); + amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c index c35c8a273051..b9dee9934f0a 100644 --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c @@ -1263,6 +1263,9 @@ static int smu_hw_init(void *handle) return ret; } + if (adev->asic_type == CHIP_RENOIR) + smu_powergate_sdma(&adev->smu, false); + if (!smu->pm_enabled) return 0; @@ -1310,6 +1313,9 @@ static int smu_hw_fini(void *handle) struct smu_table_context *table_context = &smu->smu_table; int ret = 0; + if (adev->asic_type == CHIP_RENOIR) + smu_powergate_sdma(&adev->smu, true); + kfree(table_context->driver_pptable); table_context->driver_pptable = NULL; diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h index 61d453f83f88..536f547f01c5 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h @@ -473,6 +473,7 @@ struct smu_funcs int (*parse_pptable)(struct smu_context *smu); int (*populate_smc_pptable)(struct smu_context *smu); int (*check_fw_version)(struct smu_context *smu); + int (*powergate_sdma)(struct smu_context *smu, bool gate); int (*write_pptable)(struct smu_context *smu); int (*set_min_dcef_deep_sleep)(struct smu_context *smu); int (*set_tool_table_location)(struct smu_context *smu); @@ -549,6 +550,8 @@ struct smu_funcs ((smu)->funcs->check_fw_status ? (smu)->funcs->check_fw_status((smu)) : 0) #define smu_setup_pptable(smu) \ ((smu)->funcs->setup_pptable ? (smu)->funcs->setup_pptable((smu)) : 0) +#define smu_powergate_sdma(smu, gate) \ + ((smu)->funcs->powergate_sdma ? (smu)->funcs->powergate_sdma((smu), (gate)) : 0) #define smu_get_vbios_bootup_values(smu) \ ((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0) #define smu_get_clk_info_from_vbios(smu) \ diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c index fdafa2306c29..cba8507a02af 100644 --- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c +++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c @@ -101,7 +101,6 @@ static int smu_v12_0_send_msg_with_param(struct smu_context *smu, uint16_t msg, uint32_t param) { - struct amdgpu_device *adev = smu->adev; int ret = 0, index = 0; @@ -128,27 +127,55 @@ smu_v12_0_send_msg_with_param(struct smu_context *smu, uint16_t msg, return ret; } +static int smu_v12_0_check_fw_status(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + uint32_t mp1_fw_flags; + + mp1_fw_flags = RREG32_PCIE(MP1_Public | + (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); + + if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> + MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) + return 0; + + return -EIO; +} + static int smu_v12_0_check_fw_version(struct smu_context *smu) { - uint32_t smu_version = 0xff; + uint32_t smc_if_version = 0xff; int ret = 0; ret = smu_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion); if (ret) goto err; - ret = smu_read_smc_arg(smu, &smu_version); + ret = smu_read_smc_arg(smu, &smc_if_version); if (ret) goto err; - if (smu_version != smu->smc_if_version) + if (smc_if_version != smu->smc_if_version) ret = -EINVAL; err: return ret; } +static int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate) +{ + if (!(smu->adev->flags & AMD_IS_APU)) + return 0; + + if (gate) + return smu_send_smc_msg(smu, SMU_MSG_PowerDownSdma); + else + return smu_send_smc_msg(smu, SMU_MSG_PowerUpSdma); +} + static const struct smu_funcs smu_v12_0_funcs = { + .check_fw_status = smu_v12_0_check_fw_status, .check_fw_version = smu_v12_0_check_fw_version, + .powergate_sdma = smu_v12_0_powergate_sdma, .send_smc_msg = smu_v12_0_send_msg, .send_smc_msg_with_param = smu_v12_0_send_msg_with_param, .read_smc_arg = smu_v12_0_read_arg,