From: Chandni Cherukuri Date: Fri, 10 Aug 2018 05:47:58 +0000 (+0530) Subject: plat/arm/sgi: reorganize platform macros X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=91e6f26f96c0ce4088f2c1d5110bd82591e15678;p=project%2Fbcm63xx%2Fatf.git plat/arm/sgi: reorganize platform macros In preparation of adding support for upcoming SGI platforms, macros common to all the SGI platforms are moved into sgi_base_platform_def.h file. Macros that are specific to sgi575 platform remain in the platform_def.h file. In addition to this, the platform_def.h file is moved to sgi575 board directory. Also the ENT_CPU_SOURCES has been renamed to SGI_CPU_SOURCES and moved from sgi-common.mk to board specific makefile platform.mk Change-Id: Iccdd9f070f4feea232b9fbf4fdcc0ef2e8eccbf2 Signed-off-by: Chandni Cherukuri --- diff --git a/plat/arm/board/sgi575/include/platform_def.h b/plat/arm/board/sgi575/include/platform_def.h new file mode 100644 index 00000000..1870fc78 --- /dev/null +++ b/plat/arm/board/sgi575/include/platform_def.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include + +#define PLAT_ARM_CLUSTER_COUNT 2 +#define CSS_SGI_MAX_CPUS_PER_CLUSTER 4 +#define CSS_SGI_MAX_PE_PER_CPU 1 + +#define PLAT_CSS_MHU_BASE 0x45000000 + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/arm/board/sgi575/platform.mk b/plat/arm/board/sgi575/platform.mk index 078f393c..a18e45bb 100644 --- a/plat/arm/board/sgi575/platform.mk +++ b/plat/arm/board/sgi575/platform.mk @@ -6,9 +6,18 @@ include plat/arm/css/sgi/sgi-common.mk +SGI575_BASE = plat/arm/board/sgi575 + +PLAT_INCLUDES += -I${SGI575_BASE}/include/ + +SGI_CPU_SOURCES := lib/cpus/aarch64/cortex_a75.S + +BL1_SOURCES += ${SGI_CPU_SOURCES} + BL2_SOURCES += lib/utils/mem_region.c \ plat/arm/common/arm_nor_psci_mem_protect.c -BL31_SOURCES += drivers/cfi/v2m/v2m_flash.c \ +BL31_SOURCES += ${SGI_CPU_SOURCES} \ + drivers/cfi/v2m/v2m_flash.c \ lib/utils/mem_region.c \ plat/arm/common/arm_nor_psci_mem_protect.c diff --git a/plat/arm/css/sgi/include/platform_def.h b/plat/arm/css/sgi/include/platform_def.h deleted file mode 100644 index 62974905..00000000 --- a/plat/arm/css/sgi/include/platform_def.h +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef PLATFORM_DEF_H -#define PLATFORM_DEF_H - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define CSS_SGI_MAX_CPUS_PER_CLUSTER 4 - -/* CPU topology */ -#define PLAT_ARM_CLUSTER_COUNT 2 -#define CSS_SGI_MAX_PE_PER_CPU 1 -#define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \ - CSS_SGI_MAX_CPUS_PER_CLUSTER * \ - CSS_SGI_MAX_PE_PER_CPU) - -#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */ - -/* - * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the - * plat_arm_mmap array defined for each BL stage. - */ -#if defined(IMAGE_BL31) -# if ENABLE_SPM -# define PLAT_ARM_MMAP_ENTRIES 9 -# define MAX_XLAT_TABLES 7 -# define PLAT_SP_IMAGE_MMAP_REGIONS 7 -# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 -# else -# define PLAT_ARM_MMAP_ENTRIES 8 -# define MAX_XLAT_TABLES 5 -# endif -#elif defined(IMAGE_BL32) -# define PLAT_ARM_MMAP_ENTRIES 8 -# define MAX_XLAT_TABLES 5 -#elif !USE_ROMLIB -# define PLAT_ARM_MMAP_ENTRIES 11 -# define MAX_XLAT_TABLES 5 -#else -# define PLAT_ARM_MMAP_ENTRIES 12 -# define MAX_XLAT_TABLES 6 -#endif - -/* - * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size - * plus a little space for growth. - */ -#define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000 - -/* - * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page - */ - -#if USE_ROMLIB -#define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000 -#define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000 -#else -#define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0 -#define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0 -#endif - -/* - * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a - * little space for growth. - */ -#if TRUSTED_BOARD_BOOT -# define PLAT_ARM_MAX_BL2_SIZE 0x1D000 -#else -# define PLAT_ARM_MAX_BL2_SIZE 0x11000 -#endif - -/* - * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is - * calculated using the current BL31 PROGBITS debug size plus the sizes of - * BL2 and BL1-RW - */ -#define PLAT_ARM_MAX_BL31_SIZE 0x3B000 - -/* - * Size of cacheable stacks - */ -#if defined(IMAGE_BL1) -# if TRUSTED_BOARD_BOOT -# define PLATFORM_STACK_SIZE 0x1000 -# else -# define PLATFORM_STACK_SIZE 0x440 -# endif -#elif defined(IMAGE_BL2) -# if TRUSTED_BOARD_BOOT -# define PLATFORM_STACK_SIZE 0x1000 -# else -# define PLATFORM_STACK_SIZE 0x400 -# endif -#elif defined(IMAGE_BL2U) -# define PLATFORM_STACK_SIZE 0x400 -#elif defined(IMAGE_BL31) -# if ENABLE_SPM -# define PLATFORM_STACK_SIZE 0x500 -# else -# define PLATFORM_STACK_SIZE 0x400 -# endif -#elif defined(IMAGE_BL32) -# define PLATFORM_STACK_SIZE 0x440 -#endif - - -#define PLAT_ARM_NSTIMER_FRAME_ID 0 - -#define PLAT_CSS_MHU_BASE 0x45000000 - -#define PLAT_ARM_TRUSTED_ROM_BASE 0x0 -#define PLAT_ARM_TRUSTED_ROM_SIZE 0x00080000 /* 512KB */ - -#define PLAT_ARM_NSRAM_BASE 0x06000000 -#define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */ - -#define PLAT_MAX_PWR_LVL U(1) - -#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) -#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) - -#define CSS_SGI_DEVICE_BASE (0x20000000) -#define CSS_SGI_DEVICE_SIZE (0x20000000) -#define CSS_SGI_MAP_DEVICE MAP_REGION_FLAT( \ - CSS_SGI_DEVICE_BASE, \ - CSS_SGI_DEVICE_SIZE, \ - MT_DEVICE | MT_RW | MT_SECURE) - -/* GIC related constants */ -#define PLAT_ARM_GICD_BASE 0x30000000 -#define PLAT_ARM_GICC_BASE 0x2C000000 -#define PLAT_ARM_GICR_BASE 0x300C0000 - -/* Map the secure region for access from S-EL0 */ -#define PLAT_ARM_SECURE_MAP_DEVICE MAP_REGION_FLAT( \ - SOC_CSS_DEVICE_BASE, \ - SOC_CSS_DEVICE_SIZE, \ - MT_DEVICE | MT_RW | MT_SECURE | MT_USER) - -#if RAS_EXTENSION -/* Allocate 128KB for CPER buffers */ -#define PLAT_SP_BUF_BASE ULL(0x20000) - -#define PLAT_ARM_SP_IMAGE_STACK_BASE (ARM_SP_IMAGE_NS_BUF_BASE + \ - ARM_SP_IMAGE_NS_BUF_SIZE + \ - PLAT_SP_BUF_BASE) - -/* Platform specific SMC FID's used for RAS */ -#define SP_DMC_ERROR_INJECT_EVENT_AARCH64 0xC4000042 -#define SP_DMC_ERROR_INJECT_EVENT_AARCH32 0x84000042 - -#define SP_DMC_ERROR_OVERFLOW_EVENT_AARCH64 0xC4000043 -#define SP_DMC_ERROR_OVERFLOW_EVENT_AARCH32 0x84000043 - -#define SP_DMC_ERROR_ECC_EVENT_AARCH64 0xC4000044 -#define SP_DMC_ERROR_ECC_EVENT_AARCH32 0x84000044 - -/* ARM SDEI dynamic shared event numbers */ -#define SGI_SDEI_DS_EVENT_0 804 -#define SGI_SDEI_DS_EVENT_1 805 - -#define PLAT_ARM_PRIVATE_SDEI_EVENTS \ - SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ - SDEI_EXPLICIT_EVENT(SGI_SDEI_DS_EVENT_0, SDEI_MAPF_CRITICAL), \ - SDEI_EXPLICIT_EVENT(SGI_SDEI_DS_EVENT_1, SDEI_MAPF_CRITICAL), -#define PLAT_ARM_SHARED_SDEI_EVENTS - -#define ARM_SP_CPER_BUF_BASE (ARM_SP_IMAGE_NS_BUF_BASE + \ - ARM_SP_IMAGE_NS_BUF_SIZE) -#define ARM_SP_CPER_BUF_SIZE ULL(0x20000) -#define ARM_SP_CPER_BUF_MMAP MAP_REGION2( \ - ARM_SP_CPER_BUF_BASE, \ - ARM_SP_CPER_BUF_BASE, \ - ARM_SP_CPER_BUF_SIZE, \ - MT_RW_DATA | MT_NS | MT_USER, \ - PAGE_SIZE) - -#else -#define PLAT_ARM_SP_IMAGE_STACK_BASE (ARM_SP_IMAGE_NS_BUF_BASE + \ - ARM_SP_IMAGE_NS_BUF_SIZE) -#endif /* RAS_EXTENSION */ - -/* Platform ID address */ -#define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET) -#ifndef __ASSEMBLY__ -/* SSC_VERSION related accessors */ -/* Returns the part number of the platform */ -#define GET_SGI_PART_NUM \ - GET_SSC_VERSION_PART_NUM(mmio_read_32(SSC_VERSION)) -/* Returns the configuration number of the platform */ -#define GET_SGI_CONFIG_NUM \ - GET_SSC_VERSION_CONFIG(mmio_read_32(SSC_VERSION)) -#endif /* __ASSEMBLY__ */ - -/******************************************************************************* - * Memprotect definitions - ******************************************************************************/ -/* PSCI memory protect definitions: - * This variable is stored in a non-secure flash because some ARM reference - * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT - * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. - */ -#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ - V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) - - -#endif /* PLATFORM_DEF_H */ diff --git a/plat/arm/css/sgi/include/sgi_base_platform_def.h b/plat/arm/css/sgi/include/sgi_base_platform_def.h new file mode 100644 index 00000000..90eb3360 --- /dev/null +++ b/plat/arm/css/sgi/include/sgi_base_platform_def.h @@ -0,0 +1,212 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SGI_BASE_PLATFORM_DEF_H +#define SGI_BASE_PLATFORM_DEF_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \ + CSS_SGI_MAX_CPUS_PER_CLUSTER * \ + CSS_SGI_MAX_PE_PER_CPU) + +#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */ + +/* + * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the + * plat_arm_mmap array defined for each BL stage. + */ +#if defined(IMAGE_BL31) +# if ENABLE_SPM +# define PLAT_ARM_MMAP_ENTRIES 9 +# define MAX_XLAT_TABLES 7 +# define PLAT_SP_IMAGE_MMAP_REGIONS 7 +# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 +# else +# define PLAT_ARM_MMAP_ENTRIES 8 +# define MAX_XLAT_TABLES 5 +# endif +#elif defined(IMAGE_BL32) +# define PLAT_ARM_MMAP_ENTRIES 8 +# define MAX_XLAT_TABLES 5 +#elif !USE_ROMLIB +# define PLAT_ARM_MMAP_ENTRIES 11 +# define MAX_XLAT_TABLES 5 +#else +# define PLAT_ARM_MMAP_ENTRIES 12 +# define MAX_XLAT_TABLES 6 +#endif + +/* + * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size + * plus a little space for growth. + */ +#define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000 + +/* + * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page + */ + +#if USE_ROMLIB +#define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000 +#define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000 +#else +#define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0 +#define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0 +#endif + +/* + * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a + * little space for growth. + */ +#if TRUSTED_BOARD_BOOT +# define PLAT_ARM_MAX_BL2_SIZE 0x1D000 +#else +# define PLAT_ARM_MAX_BL2_SIZE 0x11000 +#endif + +/* + * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is + * calculated using the current BL31 PROGBITS debug size plus the sizes of + * BL2 and BL1-RW + */ +#define PLAT_ARM_MAX_BL31_SIZE 0x3B000 + +/* + * Size of cacheable stacks + */ +#if defined(IMAGE_BL1) +# if TRUSTED_BOARD_BOOT +# define PLATFORM_STACK_SIZE 0x1000 +# else +# define PLATFORM_STACK_SIZE 0x440 +# endif +#elif defined(IMAGE_BL2) +# if TRUSTED_BOARD_BOOT +# define PLATFORM_STACK_SIZE 0x1000 +# else +# define PLATFORM_STACK_SIZE 0x400 +# endif +#elif defined(IMAGE_BL2U) +# define PLATFORM_STACK_SIZE 0x400 +#elif defined(IMAGE_BL31) +# if ENABLE_SPM +# define PLATFORM_STACK_SIZE 0x500 +# else +# define PLATFORM_STACK_SIZE 0x400 +# endif +#elif defined(IMAGE_BL32) +# define PLATFORM_STACK_SIZE 0x440 +#endif + + +#define PLAT_ARM_NSTIMER_FRAME_ID 0 + +#define PLAT_ARM_TRUSTED_ROM_BASE 0x0 +#define PLAT_ARM_TRUSTED_ROM_SIZE 0x00080000 /* 512KB */ + +#define PLAT_ARM_NSRAM_BASE 0x06000000 +#define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */ + +#define PLAT_MAX_PWR_LVL U(1) + +#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) +#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) + +#define CSS_SGI_DEVICE_BASE (0x20000000) +#define CSS_SGI_DEVICE_SIZE (0x20000000) +#define CSS_SGI_MAP_DEVICE MAP_REGION_FLAT( \ + CSS_SGI_DEVICE_BASE, \ + CSS_SGI_DEVICE_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +/* GIC related constants */ +#define PLAT_ARM_GICD_BASE 0x30000000 +#define PLAT_ARM_GICC_BASE 0x2C000000 +#define PLAT_ARM_GICR_BASE 0x300C0000 + +/* Map the secure region for access from S-EL0 */ +#define PLAT_ARM_SECURE_MAP_DEVICE MAP_REGION_FLAT( \ + SOC_CSS_DEVICE_BASE, \ + SOC_CSS_DEVICE_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE | MT_USER) + +#if RAS_EXTENSION +/* Allocate 128KB for CPER buffers */ +#define PLAT_SP_BUF_BASE ULL(0x20000) + +#define PLAT_ARM_SP_IMAGE_STACK_BASE (ARM_SP_IMAGE_NS_BUF_BASE + \ + ARM_SP_IMAGE_NS_BUF_SIZE + \ + PLAT_SP_BUF_BASE) + +/* Platform specific SMC FID's used for RAS */ +#define SP_DMC_ERROR_INJECT_EVENT_AARCH64 0xC4000042 +#define SP_DMC_ERROR_INJECT_EVENT_AARCH32 0x84000042 + +#define SP_DMC_ERROR_OVERFLOW_EVENT_AARCH64 0xC4000043 +#define SP_DMC_ERROR_OVERFLOW_EVENT_AARCH32 0x84000043 + +#define SP_DMC_ERROR_ECC_EVENT_AARCH64 0xC4000044 +#define SP_DMC_ERROR_ECC_EVENT_AARCH32 0x84000044 + +/* ARM SDEI dynamic shared event numbers */ +#define SGI_SDEI_DS_EVENT_0 804 +#define SGI_SDEI_DS_EVENT_1 805 + +#define PLAT_ARM_PRIVATE_SDEI_EVENTS \ + SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ + SDEI_EXPLICIT_EVENT(SGI_SDEI_DS_EVENT_0, SDEI_MAPF_CRITICAL), \ + SDEI_EXPLICIT_EVENT(SGI_SDEI_DS_EVENT_1, SDEI_MAPF_CRITICAL), +#define PLAT_ARM_SHARED_SDEI_EVENTS + +#define ARM_SP_CPER_BUF_BASE (ARM_SP_IMAGE_NS_BUF_BASE + \ + ARM_SP_IMAGE_NS_BUF_SIZE) +#define ARM_SP_CPER_BUF_SIZE ULL(0x20000) +#define ARM_SP_CPER_BUF_MMAP MAP_REGION2( \ + ARM_SP_CPER_BUF_BASE, \ + ARM_SP_CPER_BUF_BASE, \ + ARM_SP_CPER_BUF_SIZE, \ + MT_RW_DATA | MT_NS | MT_USER, \ + PAGE_SIZE) + +#else +#define PLAT_ARM_SP_IMAGE_STACK_BASE (ARM_SP_IMAGE_NS_BUF_BASE + \ + ARM_SP_IMAGE_NS_BUF_SIZE) +#endif /* RAS_EXTENSION */ + +/* Platform ID address */ +#define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET) +#ifndef __ASSEMBLY__ +/* SSC_VERSION related accessors */ +/* Returns the part number of the platform */ +#define GET_SGI_PART_NUM \ + GET_SSC_VERSION_PART_NUM(mmio_read_32(SSC_VERSION)) +/* Returns the configuration number of the platform */ +#define GET_SGI_CONFIG_NUM \ + GET_SSC_VERSION_CONFIG(mmio_read_32(SSC_VERSION)) +#endif /* __ASSEMBLY__ */ + +/******************************************************************************* + * Memprotect definitions + ******************************************************************************/ +/* PSCI memory protect definitions: + * This variable is stored in a non-secure flash because some ARM reference + * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT + * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. + */ +#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ + V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) + + +#endif /* SGI_BASE_PLATFORM_DEF_H */ diff --git a/plat/arm/css/sgi/sgi-common.mk b/plat/arm/css/sgi/sgi-common.mk index 24f03dd4..b6383aa7 100644 --- a/plat/arm/css/sgi/sgi-common.mk +++ b/plat/arm/css/sgi/sgi-common.mk @@ -22,8 +22,6 @@ INTERCONNECT_SOURCES := ${CSS_ENT_BASE}/sgi_interconnect.c PLAT_INCLUDES += -I${CSS_ENT_BASE}/include -ENT_CPU_SOURCES := lib/cpus/aarch64/cortex_a75.S - ENT_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ drivers/arm/gic/v3/gicv3_main.c \ drivers/arm/gic/v3/gicv3_helpers.c \ @@ -36,15 +34,13 @@ PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat.c \ ${CSS_ENT_BASE}/aarch64/sgi_helper.S BL1_SOURCES += ${INTERCONNECT_SOURCES} \ - ${ENT_CPU_SOURCES} \ ${CSS_ENT_BASE}/sgi_bl1_setup.c \ ${CSS_ENT_BASE}/sgi_plat_config.c BL2_SOURCES += ${CSS_ENT_BASE}/sgi_security.c \ ${CSS_ENT_BASE}/sgi_image_load.c -BL31_SOURCES += ${ENT_CPU_SOURCES} \ - ${INTERCONNECT_SOURCES} \ +BL31_SOURCES += ${INTERCONNECT_SOURCES} \ ${ENT_GIC_SOURCES} \ ${CSS_ENT_BASE}/sgi_bl31_setup.c \ ${CSS_ENT_BASE}/sgi_topology.c \