From: Felix Fietkau Date: Thu, 4 Nov 2010 18:46:07 +0000 (+0000) Subject: ar71xx: Set eth1 MAC address from EEPROM for WNDR3700 X-Git-Tag: reboot~18475 X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=91b6c63adc6338572ec16006462f6e2de64f89a4;p=openwrt%2Fstaging%2Fxback.git ar71xx: Set eth1 MAC address from EEPROM for WNDR3700 The WNDR3700's art/caldata partition contains three MAC addresses at offsets 0, 6, and 12, used for eth0/wlan0 (shared), eth1, and wlan1, respectively. The existing code configures eth1's MAC address by adding 1 to eth0's instead of using the value stored in the EEPROM. This patch causes the stored value to be used directly. (On my WNDR3700s, the three stored addresses are all sequential anyway.) Signed-off-by: Mark Mentovai SVN-Revision: 23876 --- diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/mach-wndr3700.c b/target/linux/ar71xx/files/arch/mips/ar71xx/mach-wndr3700.c index 0d3e374fe2..52ddae5a1e 100644 --- a/target/linux/ar71xx/files/arch/mips/ar71xx/mach-wndr3700.c +++ b/target/linux/ar71xx/files/arch/mips/ar71xx/mach-wndr3700.c @@ -40,6 +40,9 @@ #define WNDR3700_BUTTONS_POLL_INTERVAL 20 +#define WNDR3700_ETH0_MAC_OFFSET 0 +#define WNDR3700_ETH1_MAC_OFFSET 0x6 + #define WNDR3700_WMAC0_MAC_OFFSET 0 #define WNDR3700_WMAC1_MAC_OFFSET 0xc #define WNDR3700_CALDATA0_OFFSET 0x1000 @@ -168,14 +171,16 @@ static void __init wndr3700_setup(void) { u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); - ar71xx_init_mac(ar71xx_eth0_data.mac_addr, art, 0); + ar71xx_init_mac(ar71xx_eth0_data.mac_addr, + art + WNDR3700_ETH0_MAC_OFFSET, 0); ar71xx_eth0_pll_data.pll_1000 = 0x11110000; ar71xx_eth0_data.mii_bus_dev = &wndr3700_rtl8366s_device.dev; ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ar71xx_eth0_data.speed = SPEED_1000; ar71xx_eth0_data.duplex = DUPLEX_FULL; - ar71xx_init_mac(ar71xx_eth1_data.mac_addr, art, 1); + ar71xx_init_mac(ar71xx_eth1_data.mac_addr, + art + WNDR3700_ETH1_MAC_OFFSET, 0); ar71xx_eth1_pll_data.pll_1000 = 0x11110000; ar71xx_eth1_data.mii_bus_dev = &wndr3700_rtl8366s_device.dev; ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;