From: Fabio Estevam Date: Mon, 18 Jul 2016 13:19:28 +0000 (-0300) Subject: mx6: clock: Fix the logic for reading axi_alt_sel X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=8f2e2f15ffa1bb03b6e6e189312426059f3215d1;p=project%2Fbcm63xx%2Fu-boot.git mx6: clock: Fix the logic for reading axi_alt_sel According to the IMX6DQRM Reference Manual, the description of bit 7 (axi_alt_sel) of the CCM_CBCDR register is: "AXI alternative clock select 0 pll2 396MHz PFD will be selected as alternative clock for AXI root clock 1 pll3 540MHz PFD will be selected as alternative clock for AXI root clock " The current logic is inverted, so fix it to match the reference manual. Signed-off-by: Fabio Estevam --- diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 9b4b69c55d..b3c9dcc969 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -433,9 +433,9 @@ static u32 get_axi_clk(void) if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) - root_freq = mxc_get_pll_pfd(PLL_BUS, 2); - else root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1); + else + root_freq = mxc_get_pll_pfd(PLL_BUS, 2); } else root_freq = get_periph_clk();