From: Daniel Golle Date: Tue, 15 Oct 2024 16:39:13 +0000 (+0100) Subject: generic: phy: aquantia: move accepted patches to backport-6.6 X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=8cc049cec244eeeaf6b312e7e5776cdb822a5da2;p=openwrt%2Fstaging%2Fansuel.git generic: phy: aquantia: move accepted patches to backport-6.6 Move patches accepted upstream from pending-6.6 to backport-6.6. Signed-off-by: Daniel Golle --- diff --git a/target/linux/generic/backport-6.6/837-v6.13-net-phy-aquantia-allow-forcing-order-of-MDI-pairs.patch b/target/linux/generic/backport-6.6/837-v6.13-net-phy-aquantia-allow-forcing-order-of-MDI-pairs.patch new file mode 100644 index 0000000000..9522bcaa45 --- /dev/null +++ b/target/linux/generic/backport-6.6/837-v6.13-net-phy-aquantia-allow-forcing-order-of-MDI-pairs.patch @@ -0,0 +1,107 @@ +From a2e1ba275eae96a8171deb19e9c7c2f5978fee7b Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Fri, 4 Oct 2024 17:18:16 +0100 +Subject: [PATCH] net: phy: aquantia: allow forcing order of MDI pairs + +Despite supporting Auto MDI-X, it looks like Aquantia only supports +swapping pair (1,2) with pair (3,6) like it used to be for MDI-X on +100MBit/s networks. + +When all 4 pairs are in use (for 1000MBit/s or faster) the link does not +come up with pair order is not configured correctly, either using +MDI_CFG pin or using the "PMA Receive Reserved Vendor Provisioning 1" +register. + +Normally, the order of MDI pairs being either ABCD or DCBA is configured +by pulling the MDI_CFG pin. + +However, some hardware designs require overriding the value configured +by that bootstrap pin. The PHY allows doing that by setting a bit in +"PMA Receive Reserved Vendor Provisioning 1" register which allows +ignoring the state of the MDI_CFG pin and another bit configuring +whether the order of MDI pairs should be normal (ABCD) or reverse +(DCBA). Pair polarity is not affected and remains identical in both +settings. + +Introduce property "marvell,mdi-cfg-order" which allows forcing either +normal or reverse order of the MDI pairs from DT. + +If the property isn't present, the behavior is unchanged and MDI pair +order configuration is untouched (ie. either the result of MDI_CFG pin +pull-up/pull-down, or pair order override already configured by the +bootloader before Linux is started). + +Forcing normal pair order is required on the Adtran SDG-8733A Wi-Fi 7 +residential gateway. + +Signed-off-by: Daniel Golle +Reviewed-by: Andrew Lunn +Link: https://patch.msgid.link/9ed760ff87d5fc456f31e407ead548bbb754497d.1728058550.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/aquantia/aquantia_main.c | 33 ++++++++++++++++++++++++ + 1 file changed, 33 insertions(+) + +--- a/drivers/net/phy/aquantia/aquantia_main.c ++++ b/drivers/net/phy/aquantia/aquantia_main.c +@@ -11,6 +11,7 @@ + #include + #include + #include ++#include + #include + + #include "aquantia.h" +@@ -70,6 +71,11 @@ + #define MDIO_AN_TX_VEND_INT_MASK2 0xd401 + #define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0) + ++#define PMAPMD_RSVD_VEND_PROV 0xe400 ++#define PMAPMD_RSVD_VEND_PROV_MDI_CONF GENMASK(1, 0) ++#define PMAPMD_RSVD_VEND_PROV_MDI_REVERSE BIT(0) ++#define PMAPMD_RSVD_VEND_PROV_MDI_FORCE BIT(1) ++ + #define MDIO_AN_RX_LP_STAT1 0xe820 + #define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15) + #define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14) +@@ -497,6 +503,29 @@ static int aqr107_wait_processor_intensi + return 0; + } + ++static int aqr107_config_mdi(struct phy_device *phydev) ++{ ++ struct device_node *np = phydev->mdio.dev.of_node; ++ u32 mdi_conf; ++ int ret; ++ ++ ret = of_property_read_u32(np, "marvell,mdi-cfg-order", &mdi_conf); ++ ++ /* Do nothing in case property "marvell,mdi-cfg-order" is not present */ ++ if (ret == -ENOENT) ++ return 0; ++ ++ if (ret) ++ return ret; ++ ++ if (mdi_conf & ~PMAPMD_RSVD_VEND_PROV_MDI_REVERSE) ++ return -EINVAL; ++ ++ return phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, PMAPMD_RSVD_VEND_PROV, ++ PMAPMD_RSVD_VEND_PROV_MDI_CONF, ++ mdi_conf | PMAPMD_RSVD_VEND_PROV_MDI_FORCE); ++} ++ + static int aqr107_config_init(struct phy_device *phydev) + { + struct aqr107_priv *priv = phydev->priv; +@@ -535,6 +564,10 @@ static int aqr107_config_init(struct phy + if (ret) + return ret; + ++ ret = aqr107_config_mdi(phydev); ++ if (ret) ++ return ret; ++ + /* Restore LED polarity state after reset */ + for_each_set_bit(led_active_low, &priv->leds_active_low, AQR_MAX_LEDS) { + ret = aqr_phy_led_active_low_set(phydev, index, led_active_low); diff --git a/target/linux/generic/backport-6.6/838-v6.13-net-phy-aquantia-fix-return-value-check-in-aqr107_co.patch b/target/linux/generic/backport-6.6/838-v6.13-net-phy-aquantia-fix-return-value-check-in-aqr107_co.patch new file mode 100644 index 0000000000..73be78a058 --- /dev/null +++ b/target/linux/generic/backport-6.6/838-v6.13-net-phy-aquantia-fix-return-value-check-in-aqr107_co.patch @@ -0,0 +1,31 @@ +From ce21b8fb255ebf0b49913fb4c62741d7eb05c6f6 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Fri, 11 Oct 2024 22:28:43 +0100 +Subject: [PATCH] net: phy: aquantia: fix return value check in + aqr107_config_mdi() + +of_property_read_u32() returns -EINVAL in case the property cannot be +found rather than -ENOENT. Fix the check to not abort probing in case +of the property being missing, and also in case CONFIG_OF is not set +which will result in -ENOSYS. + +Fixes: a2e1ba275eae ("net: phy: aquantia: allow forcing order of MDI pairs") +Reported-by: Jon Hunter +Closes: https://lore.kernel.org/all/114b4c03-5d16-42ed-945d-cf78eabea12b@nvidia.com/ +Suggested-by: Hans-Frieder Vogt +Signed-off-by: Daniel Golle +--- + drivers/net/phy/aquantia/aquantia_main.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/phy/aquantia/aquantia_main.c ++++ b/drivers/net/phy/aquantia/aquantia_main.c +@@ -512,7 +512,7 @@ static int aqr107_config_mdi(struct phy_ + ret = of_property_read_u32(np, "marvell,mdi-cfg-order", &mdi_conf); + + /* Do nothing in case property "marvell,mdi-cfg-order" is not present */ +- if (ret == -ENOENT) ++ if (ret == -EINVAL || ret == -ENOSYS) + return 0; + + if (ret) diff --git a/target/linux/generic/pending-6.6/751-net-phy-aquantia-fix-applying-active_low-bit-after-reset.patch b/target/linux/generic/pending-6.6/751-net-phy-aquantia-fix-applying-active_low-bit-after-reset.patch index 5c3494ae33..6d71b3d7a5 100644 --- a/target/linux/generic/pending-6.6/751-net-phy-aquantia-fix-applying-active_low-bit-after-reset.patch +++ b/target/linux/generic/pending-6.6/751-net-phy-aquantia-fix-applying-active_low-bit-after-reset.patch @@ -49,7 +49,7 @@ Reviewed-by: Russell King (Oracle) --- a/drivers/net/phy/aquantia/aquantia_main.c +++ b/drivers/net/phy/aquantia/aquantia_main.c -@@ -501,7 +501,7 @@ static int aqr107_config_init(struct phy +@@ -530,7 +530,7 @@ static int aqr107_config_init(struct phy { struct aqr107_priv *priv = phydev->priv; u32 led_active_low; @@ -58,7 +58,7 @@ Reviewed-by: Russell King (Oracle) /* Check that the PHY interface type is compatible */ if (phydev->interface != PHY_INTERFACE_MODE_SGMII && -@@ -537,10 +537,9 @@ static int aqr107_config_init(struct phy +@@ -570,10 +570,9 @@ static int aqr107_config_init(struct phy /* Restore LED polarity state after reset */ for_each_set_bit(led_active_low, &priv->leds_active_low, AQR_MAX_LEDS) { diff --git a/target/linux/generic/pending-6.6/752-net-phy-aquantia-allow-forcing-order-of-MDI-pairs.patch b/target/linux/generic/pending-6.6/752-net-phy-aquantia-allow-forcing-order-of-MDI-pairs.patch deleted file mode 100644 index f3ae893b32..0000000000 --- a/target/linux/generic/pending-6.6/752-net-phy-aquantia-allow-forcing-order-of-MDI-pairs.patch +++ /dev/null @@ -1,104 +0,0 @@ -From 49d46df79404a37685e0f32deb36506f5723e3a0 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Wed, 28 Aug 2024 23:52:09 +0100 -Subject: [PATCH] net: phy: aquantia: allow forcing order of MDI pairs - -Despite supporting Auto MDI-X, it looks like Aquantia only supports -swapping pair (1,2) with pair (3,6) like it used to be for MDI-X on -100MBit/s networks. - -When all 4 pairs are in use (for 1000MBit/s or faster) the link does not -come up with pair order is not configured correctly, either using -MDI_CFG pin or using the "PMA Receive Reserved Vendor Provisioning 1" -register. - -Normally, the order of MDI pairs being either ABCD or DCBA is configured -by pulling the MDI_CFG pin. - -However, some hardware designs require overriding the value configured -by that bootstrap pin. The PHY allows doing that by setting a bit in -"PMA Receive Reserved Vendor Provisioning 1" register which allows -ignoring the state of the MDI_CFG pin and another bit configuring -whether the order of MDI pairs should be normal (ABCD) or reverse -(DCBA). Pair polarity is not affected and remains identical in both -settings. - -Introduce property "marvell,mdi-cfg-order" which allows forcing either -normal or reverse order of the MDI pairs from DT. - -If the property isn't present, the behavior is unchanged and MDI pair -order configuration is untouched (ie. either the result of MDI_CFG pin -pull-up/pull-down, or pair order override already configured by the -bootloader before Linux is started). - -Forcing normal pair order is required on the Adtran SDG-8733A Wi-Fi 7 -residential gateway. - -Signed-off-by: Daniel Golle ---- - drivers/net/phy/aquantia/aquantia_main.c | 33 ++++++++++++++++++++++++ - 1 file changed, 33 insertions(+) - ---- a/drivers/net/phy/aquantia/aquantia_main.c -+++ b/drivers/net/phy/aquantia/aquantia_main.c -@@ -11,6 +11,7 @@ - #include - #include - #include -+#include - #include - - #include "aquantia.h" -@@ -70,6 +71,11 @@ - #define MDIO_AN_TX_VEND_INT_MASK2 0xd401 - #define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0) - -+#define PMAPMD_RSVD_VEND_PROV 0xe400 -+#define PMAPMD_RSVD_VEND_PROV_MDI_CONF GENMASK(1, 0) -+#define PMAPMD_RSVD_VEND_PROV_MDI_REVERSE BIT(0) -+#define PMAPMD_RSVD_VEND_PROV_MDI_FORCE BIT(1) -+ - #define MDIO_AN_RX_LP_STAT1 0xe820 - #define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15) - #define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14) -@@ -497,6 +503,29 @@ static int aqr107_wait_processor_intensi - return 0; - } - -+static int aqr107_config_mdi(struct phy_device *phydev) -+{ -+ struct device_node *np = phydev->mdio.dev.of_node; -+ u32 mdi_conf; -+ int ret; -+ -+ ret = of_property_read_u32(np, "marvell,mdi-cfg-order", &mdi_conf); -+ -+ /* Do nothing in case property "marvell,mdi-cfg-order" is not present */ -+ if (ret == -EINVAL) -+ return 0; -+ -+ if (ret) -+ return ret; -+ -+ if (mdi_conf & ~PMAPMD_RSVD_VEND_PROV_MDI_REVERSE) -+ return -EINVAL; -+ -+ return phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, PMAPMD_RSVD_VEND_PROV, -+ PMAPMD_RSVD_VEND_PROV_MDI_CONF, -+ mdi_conf | PMAPMD_RSVD_VEND_PROV_MDI_FORCE); -+} -+ - static int aqr107_config_init(struct phy_device *phydev) - { - struct aqr107_priv *priv = phydev->priv; -@@ -535,6 +564,10 @@ static int aqr107_config_init(struct phy - if (ret) - return ret; - -+ ret = aqr107_config_mdi(phydev); -+ if (ret) -+ return ret; -+ - /* Restore LED polarity state after reset */ - for_each_set_bit(led_active_low, &priv->leds_active_low, AQR_MAX_LEDS) { - ret = aqr_phy_led_active_low_set(phydev, led_active_low, true);