From: Imre Kaloz <kaloz@openwrt.org>
Date: Tue, 2 Sep 2008 11:28:57 +0000 (+0000)
Subject: final fix for BCM5354 USB cores, hopefully
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=88041e0f1bc250db408e50e3b4cd9030aef81c8b;p=openwrt%2Fstaging%2Fneocturne.git

final fix for BCM5354 USB cores, hopefully

SVN-Revision: 12499
---

diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/pcibios.c b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/pcibios.c
index 2d8549623a..0e993d1b95 100644
--- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/pcibios.c
+++ b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/pcibios.c
@@ -292,6 +292,7 @@ pcibios_enable_device(struct pci_dev *dev, int mask)
 	 * after calling pcibios_enable_device().
 	 */
 	if (sb_coreid(sbh) == SB_USB) {
+		printk(KERN_INFO "SB USB 1.1 init\n");
 		sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
 		sb_core_reset(sbh, 1 << 29, 0);
 	}
@@ -306,13 +307,22 @@ pcibios_enable_device(struct pci_dev *dev, int mask)
 	 *    phy components out of reset.
 	 */
 	else if (sb_coreid(sbh) == SB_USB20H) {
+		
+		uint corerev = sb_corerev(sbh);
+
+		printk(KERN_INFO "SB USB20H init\n");
+		printk(KERN_INFO "SB COREREV: %d\n", corerev);
+		
 		if (!sb_iscoreup(sbh)) {
+						
+			printk(KERN_INFO "SB USB20H resetting\n");
+
 			sb_core_reset(sbh, 0, 0);
 			writel(0x7FF, (ulong)regs + 0x200);
 			udelay(1);
 		}
 		/* PRxxxx: War for 5354 failures. */
-		if (sb_corerev(sbh) == 1) {
+		if (corerev == 1 || corerev == 2) {
 			uint32 tmp;
 
 			/* Change Flush control reg */
@@ -320,14 +330,14 @@ pcibios_enable_device(struct pci_dev *dev, int mask)
 			tmp &= ~8;
 			writel(tmp, (uintptr)regs + 0x400);
 			tmp = readl((uintptr)regs + 0x400);
-			printk("USB20H fcr: 0x%x\n", tmp);
+			printk(KERN_INFO "USB20H fcr: 0x%x\n", tmp);
 
 			/* Change Shim control reg */
 			tmp = readl((uintptr)regs + 0x304);
 			tmp &= ~0x100;
 			writel(tmp, (uintptr)regs + 0x304);
 			tmp = readl((uintptr)regs + 0x304);
-			printk("USB20H shim cr: 0x%x\n", tmp);
+			printk(KERN_INFO "USB20H shim cr: 0x%x\n", tmp);
 		}
 
 	} else