From: Antonio Nino Diaz Date: Mon, 24 Sep 2018 16:15:15 +0000 (+0100) Subject: poplar: Migrate to new interfaces X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=82fbaa33e830fa3cc71c1b9c15cec0ce115b3b99;p=project%2Fbcm63xx%2Fatf.git poplar: Migrate to new interfaces - Remove support for LOAD_IMAGE_V2=0. - Replace deprecated bl1_init_bl2_mem_layout(). - Migrate to bl2_early_platform_setup2(). - Migrate to bl31_early_platform_setup2(). - Use PLAT_VIRT_ADDR_SPACE_SIZE and PLAT_PHY_ADDR_SPACE_SIZE. - Remove references to removed build options. - Update Makefile paths. Change-Id: I52e02633365b3db4244f7ff0f99a6446eae619f0 Tested-by: Shawn Guo Signed-off-by: Antonio Nino Diaz --- diff --git a/plat/hisilicon/poplar/aarch64/platform_common.c b/plat/hisilicon/poplar/aarch64/platform_common.c index 54980650..d408209d 100644 --- a/plat/hisilicon/poplar/aarch64/platform_common.c +++ b/plat/hisilicon/poplar/aarch64/platform_common.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include @@ -29,23 +28,19 @@ TSP_SEC_MEM_SIZE, \ MT_MEMORY | MT_RW | MT_SECURE) -#if LOAD_IMAGE_V2 #ifdef SPD_opteed #define MAP_OPTEE_PAGEABLE MAP_REGION_FLAT( \ POPLAR_OPTEE_PAGEABLE_LOAD_BASE, \ POPLAR_OPTEE_PAGEABLE_LOAD_SIZE, \ MT_MEMORY | MT_RW | MT_SECURE) #endif -#endif static const mmap_region_t poplar_mmap[] = { MAP_DDR, MAP_DEVICE, MAP_TSP_MEM, -#if LOAD_IMAGE_V2 #ifdef SPD_opteed MAP_OPTEE_PAGEABLE, -#endif #endif {0} }; diff --git a/plat/hisilicon/poplar/bl1_plat_setup.c b/plat/hisilicon/poplar/bl1_plat_setup.c index f40bcf31..c2adc44e 100644 --- a/plat/hisilicon/poplar/bl1_plat_setup.c +++ b/plat/hisilicon/poplar/bl1_plat_setup.c @@ -25,35 +25,39 @@ /* Data structure which holds the extents of the trusted RAM for BL1 */ static meminfo_t bl1_tzram_layout; +static meminfo_t bl2_tzram_layout; -meminfo_t *bl1_plat_sec_mem_layout(void) +/* + * Cannot use default weak implementation in bl1_main.c because BL1 RW data is + * not at the top of the secure memory. + */ +int bl1_plat_handle_post_image_load(unsigned int image_id) { - return &bl1_tzram_layout; -} + image_desc_t *image_desc; + entry_point_info_t *ep_info; -#if LOAD_IMAGE_V2 -/******************************************************************************* - * Function that takes a memory layout into which BL2 has been loaded and - * populates a new memory layout for BL2 that ensures that BL1's data sections - * resident in secure RAM are not visible to BL2. - ******************************************************************************/ -void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout, - meminfo_t *bl2_mem_layout) -{ + if (image_id != BL2_IMAGE_ID) + return 0; + + /* Get the image descriptor */ + image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID); + assert(image_desc != NULL); + + /* Get the entry point info */ + ep_info = &image_desc->ep_info; - assert(bl1_mem_layout != NULL); - assert(bl2_mem_layout != NULL); + bl2_tzram_layout.total_base = BL2_BASE; + bl2_tzram_layout.total_size = BL32_LIMIT - BL2_BASE; - /* - * Cannot use default weak implementation in bl1main.c because - * BL1 RW data is not at the top of bl1_mem_layout - */ - bl2_mem_layout->total_base = BL2_BASE; - bl2_mem_layout->total_size = BL32_LIMIT - BL2_BASE; + flush_dcache_range((uintptr_t)&bl2_tzram_layout, sizeof(meminfo_t)); - flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t)); + ep_info->args.arg1 = (uintptr_t)&bl2_tzram_layout; + + VERBOSE("BL1: BL2 memory layout address = %p\n", + (void *)&bl2_tzram_layout); + + return 0; } -#endif /* LOAD_IMAGE_V2 */ void bl1_early_platform_setup(void) { @@ -64,17 +68,6 @@ void bl1_early_platform_setup(void) bl1_tzram_layout.total_base = BL1_RW_BASE; bl1_tzram_layout.total_size = BL1_RW_SIZE; -#if !LOAD_IMAGE_V2 - /* Calculate how much RAM BL1 is using and how much remains free */ - bl1_tzram_layout.free_base = BL1_RW_BASE; - bl1_tzram_layout.free_size = BL1_RW_SIZE; - - reserve_mem(&bl1_tzram_layout.free_base, - &bl1_tzram_layout.free_size, - BL1_RAM_BASE, - BL1_RAM_LIMIT - BL1_RAM_BASE); -#endif - INFO("BL1: 0x%lx - 0x%lx [size = %zu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT, BL1_RAM_LIMIT - BL1_RAM_BASE); } diff --git a/plat/hisilicon/poplar/bl2_plat_setup.c b/plat/hisilicon/poplar/bl2_plat_setup.c index 94d59ffb..a253d3fc 100644 --- a/plat/hisilicon/poplar/bl2_plat_setup.c +++ b/plat/hisilicon/poplar/bl2_plat_setup.c @@ -32,49 +32,11 @@ static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); -#if !LOAD_IMAGE_V2 - -/******************************************************************************* - * This structure represents the superset of information that is passed to - * BL31, e.g. while passing control to it from BL2, bl31_params - * and other platform specific params - ******************************************************************************/ -typedef struct bl2_to_bl31_params_mem { - bl31_params_t bl31_params; - image_info_t bl31_image_info; - image_info_t bl32_image_info; - image_info_t bl33_image_info; - entry_point_info_t bl33_ep_info; - entry_point_info_t bl32_ep_info; - entry_point_info_t bl31_ep_info; -} bl2_to_bl31_params_mem_t; - -static bl2_to_bl31_params_mem_t bl31_params_mem; - -meminfo_t *bl2_plat_sec_mem_layout(void) -{ - return &bl2_tzram_layout; -} - -#ifdef SCP_BL2_BASE -void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo) -{ - /* - * This platform has no SCP_BL2 yet - */ -} -#endif -#endif /* LOAD_IMAGE_V2 */ - /******************************************************************************* * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol. * Return 0 on success, -1 otherwise. ******************************************************************************/ -#if LOAD_IMAGE_V2 int plat_poplar_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info) -#else -int bl2_plat_handle_scp_bl2(struct image_info *scp_bl2_image_info) -#endif { /* * This platform has no SCP_BL2 yet @@ -138,7 +100,6 @@ uint32_t poplar_get_spsr_for_bl33_entry(void) } #endif /* AARCH32 */ -#if LOAD_IMAGE_V2 int poplar_bl2_handle_post_image_load(unsigned int image_id) { int err = 0; @@ -210,129 +171,10 @@ int bl2_plat_handle_post_image_load(unsigned int image_id) return poplar_bl2_handle_post_image_load(image_id); } -#else /* LOAD_IMAGE_V2 */ - -bl31_params_t *bl2_plat_get_bl31_params(void) -{ - bl31_params_t *bl2_to_bl31_params = NULL; - - /* - * Initialise the memory for all the arguments that needs to - * be passed to BL3-1 - */ - memset(&bl31_params_mem, 0, sizeof(bl2_to_bl31_params_mem_t)); - - /* Assign memory for TF related information */ - bl2_to_bl31_params = &bl31_params_mem.bl31_params; - SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0); - - /* Fill BL3-1 related information */ - bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info; - SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, - PARAM_IMAGE_BINARY, VERSION_1, 0); - - /* Fill BL3-2 related information if it exists */ -#ifdef BL32_BASE - bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info; - SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP, - VERSION_1, 0); - bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info; - SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY, - VERSION_1, 0); -#endif - - /* Fill BL3-3 related information */ - bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info; - SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info, - PARAM_EP, VERSION_1, 0); - - /* BL3-3 expects to receive the primary CPU MPID (through x0) */ - bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr(); - - bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info; - SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, - PARAM_IMAGE_BINARY, VERSION_1, 0); - - return bl2_to_bl31_params; -} - -struct entry_point_info *bl2_plat_get_bl31_ep_info(void) -{ -#if DEBUG - bl31_params_mem.bl31_ep_info.args.arg1 = POPLAR_BL31_PLAT_PARAM_VAL; -#endif - - return &bl31_params_mem.bl31_ep_info; -} - -void bl2_plat_set_bl31_ep_info(image_info_t *image, - entry_point_info_t *bl31_ep_info) -{ - SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE); - bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS); -} - -/******************************************************************************* - * Before calling this function BL32 is loaded in memory and its entrypoint - * is set by load_image. This is a placeholder for the platform to change - * the entrypoint of BL32 and set SPSR and security state. - * On Poplar we only set the security state of the entrypoint - ******************************************************************************/ -#ifdef BL32_BASE -void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info, - entry_point_info_t *bl32_ep_info) -{ - SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE); - /* - * The Secure Payload Dispatcher service is responsible for - * setting the SPSR prior to entry into the BL32 image. - */ - bl32_ep_info->spsr = 0; -} - -/******************************************************************************* - * Populate the extents of memory available for loading BL32 - ******************************************************************************/ -void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) -{ - /* - * Populate the extents of memory available for loading BL32. - */ - bl32_meminfo->total_base = BL32_BASE; - bl32_meminfo->free_base = BL32_BASE; - bl32_meminfo->total_size = - (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; - bl32_meminfo->free_size = - (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; -} -#endif /* BL32_BASE */ - -void bl2_plat_set_bl33_ep_info(image_info_t *image, - entry_point_info_t *bl33_ep_info) -{ - SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); - bl33_ep_info->spsr = poplar_get_spsr_for_bl33_entry(); - bl33_ep_info->args.arg2 = image->image_size; -} - -void bl2_plat_flush_bl31_params(void) -{ - flush_dcache_range((unsigned long)&bl31_params_mem, - sizeof(bl2_to_bl31_params_mem_t)); -} - -void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) -{ - bl33_meminfo->total_base = DDR_BASE; - bl33_meminfo->total_size = DDR_SIZE; - bl33_meminfo->free_base = DDR_BASE; - bl33_meminfo->free_size = DDR_SIZE; -} -#endif /* LOAD_IMAGE_V2 */ - -void bl2_early_platform_setup(meminfo_t *mem_layout) +void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) { + struct meminfo *mem_layout = (struct meminfo *)arg1; #if !POPLAR_RECOVERY struct mmc_device_info info; diff --git a/plat/hisilicon/poplar/bl31_plat_setup.c b/plat/hisilicon/poplar/bl31_plat_setup.c index ec72acdb..b45693f5 100644 --- a/plat/hisilicon/poplar/bl31_plat_setup.c +++ b/plat/hisilicon/poplar/bl31_plat_setup.c @@ -6,7 +6,6 @@ #include #include -#include #include #include #include @@ -67,65 +66,45 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) * while creating page tables. BL2 has flushed this information to memory, so * we are guaranteed to pick up good data. ******************************************************************************/ -#if LOAD_IMAGE_V2 -void bl31_early_platform_setup(void *from_bl2, - void *plat_params_from_bl2) -#else -void bl31_early_platform_setup(bl31_params_t *from_bl2, - void *plat_params_from_bl2) -#endif +void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) { + void *from_bl2; + + from_bl2 = (void *) arg0; + console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE); /* Init console for crash report */ plat_crash_console_init(); -#if LOAD_IMAGE_V2 - /* - * Check params passed from BL2 should not be NULL, - */ - bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; - - assert(params_from_bl2 != NULL); - assert(params_from_bl2->h.type == PARAM_BL_PARAMS); - assert(params_from_bl2->h.version >= VERSION_2); - - bl_params_node_t *bl_params = params_from_bl2->head; - - /* - * Copy BL33 and BL32 (if present), entry point information. - * They are stored in Secure RAM, in BL2's address space. - */ - while (bl_params) { - if (bl_params->image_id == BL32_IMAGE_ID) - bl32_image_ep_info = *bl_params->ep_info; - - if (bl_params->image_id == BL33_IMAGE_ID) - bl33_image_ep_info = *bl_params->ep_info; - - bl_params = bl_params->next_params_info; - } - - if (bl33_image_ep_info.pc == 0) - panic(); - -#else /* LOAD_IMAGE_V2 */ - /* * Check params passed from BL2 should not be NULL, */ + bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; + assert(params_from_bl2 != NULL); - assert(params_from_bl2->h.type == PARAM_BL31); - assert(params_from_bl2->h.version >= VERSION_1); + assert(params_from_bl2->h.type == PARAM_BL_PARAMS); + assert(params_from_bl2->h.version >= VERSION_2); + + bl_params_node_t *bl_params = params_from_bl2->head; /* - * Copy BL32 (if populated by BL2) and BL33 entry point information. + * Copy BL33 and BL32 (if present), entry point information. * They are stored in Secure RAM, in BL2's address space. */ - if (from_bl2->bl32_ep_info) - bl32_image_ep_info = *from_bl2->bl32_ep_info; - bl33_image_ep_info = *from_bl2->bl33_ep_info; -#endif /* LOAD_IMAGE_V2 */ + while (bl_params) { + if (bl_params->image_id == BL32_IMAGE_ID) + bl32_image_ep_info = *bl_params->ep_info; + + if (bl_params->image_id == BL33_IMAGE_ID) + bl33_image_ep_info = *bl_params->ep_info; + + bl_params = bl_params->next_params_info; + } + + if (bl33_image_ep_info.pc == 0) + panic(); } void bl31_platform_setup(void) diff --git a/plat/hisilicon/poplar/include/platform_def.h b/plat/hisilicon/poplar/include/platform_def.h index 824ca34b..99fd9963 100644 --- a/plat/hisilicon/poplar/include/platform_def.h +++ b/plat/hisilicon/poplar/include/platform_def.h @@ -88,13 +88,11 @@ #define BL32_DRAM_BASE 0x03000000 #define BL32_DRAM_LIMIT 0x04000000 -#if LOAD_IMAGE_V2 #ifdef SPD_opteed /* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */ #define POPLAR_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */ #define POPLAR_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - POPLAR_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x03C0_0000 */ #endif -#endif #if (POPLAR_TSP_RAM_LOCATION_ID == POPLAR_DRAM_ID) #define TSP_SEC_MEM_BASE BL32_DRAM_BASE @@ -122,7 +120,8 @@ #define PLAT_POPLAR_NS_IMAGE_OFFSET 0x37000000 /* Page table and MMU setup constants */ -#define ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) #define MAX_XLAT_TABLES (4) #define MAX_MMAP_REGIONS (16) diff --git a/plat/hisilicon/poplar/plat_pm.c b/plat/hisilicon/poplar/plat_pm.c index 3e43d4d3..e59cac94 100644 --- a/plat/hisilicon/poplar/plat_pm.c +++ b/plat/hisilicon/poplar/plat_pm.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include diff --git a/plat/hisilicon/poplar/platform.mk b/plat/hisilicon/poplar/platform.mk index 3cdbe599..9d2b6170 100644 --- a/plat/hisilicon/poplar/platform.mk +++ b/plat/hisilicon/poplar/platform.mk @@ -4,9 +4,6 @@ # SPDX-License-Identifier: BSD-3-Clause # -# Enable version2 of image loading -LOAD_IMAGE_V2 := 1 - # On Poplar, the TSP can execute from TZC secure area in DRAM. POPLAR_TSP_RAM_LOCATION ?= dram ifeq (${POPLAR_TSP_RAM_LOCATION}, dram) @@ -45,7 +42,6 @@ NEED_BL33 := yes COLD_BOOT_SINGLE_CPU := 1 PROGRAMMABLE_RESET_ADDRESS := 1 CTX_INCLUDE_FPREGS := 1 -ENABLE_PLAT_COMPAT := 0 ERRATA_A53_855873 := 1 ERRATA_A53_835769 := 1 ERRATA_A53_843419 := 1 @@ -53,9 +49,6 @@ ENABLE_SVE_FOR_NS := 0 WORKAROUND_CVE_2017_5715 := 0 -ARM_GIC_ARCH := 2 -$(eval $(call add_define,ARM_GIC_ARCH)) - PLAT_PL061_MAX_GPIOS := 104 $(eval $(call add_define,PLAT_PL061_MAX_GPIOS)) @@ -67,12 +60,13 @@ PLAT_INCLUDES := -Iplat/hisilicon/poplar/include \ -Iinclude/drivers/io PLAT_BL_COMMON_SOURCES := \ - lib/aarch64/xlat_tables.c \ + lib/xlat_tables/aarch64/xlat_tables.c \ + lib/xlat_tables/xlat_tables_common.c \ drivers/delay_timer/generic_delay_timer.c \ drivers/arm/gic/common/gic_common.c \ drivers/arm/gic/v2/gicv2_helpers.c \ drivers/delay_timer/delay_timer.c \ - drivers/arm/pl011/pl011_console.S \ + drivers/arm/pl011/aarch64/pl011_console.S \ drivers/arm/gic/v2/gicv2_main.c \ plat/arm/common/aarch64/arm_helpers.S \ plat/arm/common/arm_gicv2.c \ @@ -104,7 +98,6 @@ BL2_SOURCES += \ plat/hisilicon/poplar/bl2_plat_setup.c \ plat/hisilicon/poplar/plat_storage.c -ifeq (${LOAD_IMAGE_V2},1) BL2_SOURCES += \ plat/hisilicon/poplar/bl2_plat_mem_params_desc.c \ plat/hisilicon/poplar/poplar_image_load.c \ @@ -114,12 +107,11 @@ ifeq (${SPD},opteed) BL2_SOURCES += \ lib/optee/optee_utils.c endif -endif BL31_SOURCES += \ lib/cpus/aarch64/aem_generic.S \ lib/cpus/aarch64/cortex_a53.S \ - plat/common/aarch64/plat_psci_common.c \ + plat/common/plat_psci_common.c \ plat/hisilicon/poplar/bl31_plat_setup.c \ plat/hisilicon/poplar/plat_topology.c \ plat/hisilicon/poplar/plat_pm.c