From: Sergio Paracuellos Date: Sun, 4 Nov 2018 10:49:35 +0000 (+0100) Subject: staging: mt7621-pci: reagroup reset related macros all together X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=7bf10a7261c42aea8c6620038fc640683dab4603;p=openwrt%2Fstaging%2Fblogic.git staging: mt7621-pci: reagroup reset related macros all together Reset bits related macros are in different parts. Reagroup all of them together to improve readability. Signed-off-by: Sergio Paracuellos Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index c9ac92e1b660..28c3f0a91075 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -45,6 +45,9 @@ #define RALINK_PCI_CONFIG_DATA 0x24 #define RALINK_PCI_MEMBASE 0x28 #define RALINK_PCI_IOBASE 0x2C + +/* RALINK_RSTCTRL bits */ +#define RALINK_PCIE_RST BIT(23) #define RALINK_PCIE0_RST BIT(24) #define RALINK_PCIE1_RST BIT(25) #define RALINK_PCIE2_RST BIT(26) @@ -74,8 +77,6 @@ #define RALINK_GPIOMODE 0x60 #define RALINK_PCIE_CLK_GEN 0x7c #define RALINK_PCIE_CLK_GEN1 0x80 -//RALINK_RSTCTRL bit -#define RALINK_PCIE_RST BIT(23) #define MEMORY_BASE 0x0 static int pcie_link_status;