From: Mathias Kresin Date: Tue, 16 Feb 2021 18:34:48 +0000 (+0100) Subject: lantiq: ARV752DPW22: set the usb led trigger via devicetree X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=7995a937447221a757ca8a0330a46944eacff473;p=openwrt%2Fstaging%2Fansuel.git lantiq: ARV752DPW22: set the usb led trigger via devicetree Assign the usbdev trigger via devicetree and drop the userspace handling of the usb leds Add the PCI attached usb controller as trigger sources for the usb led as well. Signed-off-by: Mathias Kresin --- diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube.dtsi index ced3e3bcb4..bb3e9fb188 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube.dtsi +++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube.dtsi @@ -254,6 +254,8 @@ }; usb: usb@e101000 { + #address-cells = <1>; + #size-cells = <0>; compatible = "lantiq,danube-usb"; reg = <0xe101000 0x1000 0xe120000 0x3f000>; @@ -263,6 +265,11 @@ phys = <&usb_phy>; phy-names = "usb2-phy"; status = "disabled"; + + ehci_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; }; deu@e103100 { diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw22.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw22.dts index 72483e4749..00ac016a42 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw22.dts +++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw22.dts @@ -17,7 +17,6 @@ led-upgrade = &power_red; led-dsl = &internet_red; - led-usb = &umts; led-wifi = &wifi; }; @@ -78,6 +77,9 @@ umts: umts { label = "red:umts"; gpios = <&gpiomm 3 GPIO_ACTIVE_LOW>; + trigger-sources = <&ehci_port1>, + <&ehci_port2>, <&uhci_port2>; + linux,default-trigger = "usbport"; }; wifi: wifi { label = "red:wifi"; @@ -242,6 +244,30 @@ ralink,mtd-eeprom-swap; mtd-mac-address = <&boardconfig 0x16>; }; + + usb@0f,0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "pci1106,3038"; + reg = <0x7800 0 0 0 0>; /* 0000:00:0f.0: UHCI Host Controller */ + + uhci_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; + }; + + usb@0f,2 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "pci1106,3038"; + reg = <0x7a00 0 0 0 0>; /* 0000:00:0f.2: EHCI Host Controller*/ + + ehci_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; + }; }; &usb_phy {