From: Felix Fietkau Date: Tue, 26 Jan 2010 20:13:01 +0000 (+0000) Subject: gcc: fix up broken chunks of the 4.4.3+cs patch and clean it up a bit more X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=78cae39e724956b3a1b009f029a89729b313cb40;p=openwrt%2Fstaging%2Frobimarko.git gcc: fix up broken chunks of the 4.4.3+cs patch and clean it up a bit more SVN-Revision: 19349 --- diff --git a/toolchain/gcc/patches/4.4.3+cs/000-codesourcery_2009q3_68.patch b/toolchain/gcc/patches/4.4.3+cs/000-codesourcery_2009q3_68.patch index 88be9a85ff..32652dc599 100644 --- a/toolchain/gcc/patches/4.4.3+cs/000-codesourcery_2009q3_68.patch +++ b/toolchain/gcc/patches/4.4.3+cs/000-codesourcery_2009q3_68.patch @@ -1,6 +1,5 @@ -diff -Nur a/config/mh-mingw b/config/mh-mingw ---- a/config/mh-mingw 2008-11-21 14:54:41.000000000 +0100 -+++ b/config/mh-mingw 2010-01-25 09:50:28.945687353 +0100 +--- a/config/mh-mingw ++++ b/config/mh-mingw @@ -1,6 +1,8 @@ # Add -D__USE_MINGW_ACCESS to enable the built compiler to work on Windows # Vista (see PR33281 for details). @@ -12,10 +11,9 @@ diff -Nur a/config/mh-mingw b/config/mh-mingw +# CFLAGS += -D__USE_MINGW_ACCESS # Increase stack limit to same as Linux default. LDFLAGS += -Wl,--stack,8388608 -diff -Nur a/config/stdint.m4 b/config/stdint.m4 ---- a/config/stdint.m4 2007-04-12 15:06:43.000000000 +0200 -+++ b/config/stdint.m4 2010-01-25 09:50:28.945687353 +0100 -@@ -115,19 +115,19 @@ +--- a/config/stdint.m4 ++++ b/config/stdint.m4 +@@ -115,19 +115,19 @@ AC_MSG_RESULT($acx_cv_header_stdint $acx # Lacking an uintptr_t? Test size of void * case "$acx_cv_header_stdint:$ac_cv_type_uintptr_t" in @@ -40,9 +38,8 @@ diff -Nur a/config/stdint.m4 b/config/stdint.m4 AC_MSG_CHECKING(for type equivalent to int8_t) case "$ac_cv_sizeof_char" in -diff -Nur a/config/tls.m4 b/config/tls.m4 ---- a/config/tls.m4 2009-01-23 05:58:03.000000000 +0100 -+++ b/config/tls.m4 2010-01-25 09:50:28.945687353 +0100 +--- a/config/tls.m4 ++++ b/config/tls.m4 @@ -1,5 +1,6 @@ dnl Check whether the target supports TLS. AC_DEFUN([GCC_CHECK_TLS], [ @@ -50,7 +47,7 @@ diff -Nur a/config/tls.m4 b/config/tls.m4 GCC_ENABLE(tls, yes, [], [Use thread-local storage]) AC_CACHE_CHECK([whether the target supports thread-local storage], gcc_cv_have_tls, [ -@@ -66,7 +67,24 @@ +@@ -66,7 +67,24 @@ AC_DEFUN([GCC_CHECK_TLS], [ [dnl This is the cross-compiling case. Assume libc supports TLS if the dnl binutils and the compiler do. AC_LINK_IFELSE([__thread int a; int b; int main() { return a = b; }], @@ -76,10 +73,9 @@ diff -Nur a/config/tls.m4 b/config/tls.m4 ] )]) if test "$enable_tls $gcc_cv_have_tls" = "yes yes"; then -diff -Nur a/configure b/configure ---- a/configure 2009-04-25 06:10:29.000000000 +0200 -+++ b/configure 2010-01-25 09:50:28.945687353 +0100 -@@ -2277,7 +2277,7 @@ +--- a/configure ++++ b/configure +@@ -2277,7 +2277,7 @@ case "${target}" in noconfigdirs="$noconfigdirs target-newlib target-libgloss target-rda ${libgcj}" ;; *-*-vxworks*) @@ -88,10 +84,9 @@ diff -Nur a/configure b/configure ;; alpha*-dec-osf*) # ld works, but does not support shared libraries. -diff -Nur a/configure.ac b/configure.ac ---- a/configure.ac 2009-04-25 06:10:29.000000000 +0200 -+++ b/configure.ac 2010-01-25 09:50:28.945687353 +0100 -@@ -512,7 +512,7 @@ +--- a/configure.ac ++++ b/configure.ac +@@ -512,7 +512,7 @@ case "${target}" in noconfigdirs="$noconfigdirs target-newlib target-libgloss target-rda ${libgcj}" ;; *-*-vxworks*) @@ -100,10 +95,9 @@ diff -Nur a/configure.ac b/configure.ac ;; alpha*-dec-osf*) # ld works, but does not support shared libraries. -diff -Nur a/fixincludes/fixincl.tpl b/fixincludes/fixincl.tpl ---- a/fixincludes/fixincl.tpl 2008-09-06 21:57:26.000000000 +0200 -+++ b/fixincludes/fixincl.tpl 2010-01-25 09:50:28.945687353 +0100 -@@ -38,7 +38,7 @@ +--- a/fixincludes/fixincl.tpl ++++ b/fixincludes/fixincl.tpl +@@ -38,7 +38,7 @@ x=fixincl.x =] #ifndef SED_PROGRAM #define SED_PROGRAM "/usr/bin/sed" #endif @@ -112,9 +106,8 @@ diff -Nur a/fixincludes/fixincl.tpl b/fixincludes/fixincl.tpl [= FOR fix =] -diff -Nur a/fixincludes/fixincl.x b/fixincludes/fixincl.x ---- a/fixincludes/fixincl.x 2009-02-28 19:13:31.000000000 +0100 -+++ b/fixincludes/fixincl.x 2010-01-25 09:50:28.945687353 +0100 +--- a/fixincludes/fixincl.x ++++ b/fixincludes/fixincl.x @@ -2,11 +2,11 @@ * * DO NOT EDIT THIS FILE (fixincl.x) @@ -147,7 +140,7 @@ diff -Nur a/fixincludes/fixincl.x b/fixincludes/fixincl.x /* * * * * * * * * * * * * * * * * * * * * * * * * * * -@@ -2300,6 +2300,42 @@ +@@ -2300,6 +2300,42 @@ s/{ { 0, } }/{ { 0, 0, 0, 0, 0, 0 } }/\n /* * * * * * * * * * * * * * * * * * * * * * * * * * * @@ -190,7 +183,7 @@ diff -Nur a/fixincludes/fixincl.x b/fixincludes/fixincl.x * Description of Gnu_Types fix */ tSCC zGnu_TypesName[] = -@@ -5617,8 +5653,7 @@ +@@ -5617,8 +5653,7 @@ tSCC zSolaris_Mutex_Init_2List[] = * Machine/OS name selection pattern */ tSCC* apzSolaris_Mutex_Init_2Machs[] = { @@ -200,7 +193,7 @@ diff -Nur a/fixincludes/fixincl.x b/fixincludes/fixincl.x (const char*)NULL }; /* -@@ -5627,8 +5662,15 @@ +@@ -5627,8 +5662,15 @@ tSCC* apzSolaris_Mutex_Init_2Machs[] = { tSCC zSolaris_Mutex_Init_2Select0[] = "@\\(#\\)pthread.h[ \t]+1.[0-9]+[ \t]+[0-9/]+ SMI"; @@ -217,7 +210,7 @@ diff -Nur a/fixincludes/fixincl.x b/fixincludes/fixincl.x { TT_EGREP, zSolaris_Mutex_Init_2Select0, (regex_t*)NULL }, }; /* -@@ -5670,8 +5712,15 @@ +@@ -5670,8 +5712,15 @@ tSCC* apzSolaris_Rwlock_Init_1Machs[] = tSCC zSolaris_Rwlock_Init_1Select0[] = "@\\(#\\)pthread.h[ \t]+1.[0-9]+[ \t]+[0-9/]+ SMI"; @@ -234,7 +227,7 @@ diff -Nur a/fixincludes/fixincl.x b/fixincludes/fixincl.x { TT_EGREP, zSolaris_Rwlock_Init_1Select0, (regex_t*)NULL }, }; /* -@@ -5741,8 +5790,7 @@ +@@ -5741,8 +5790,7 @@ tSCC zSolaris_Once_Init_2List[] = * Machine/OS name selection pattern */ tSCC* apzSolaris_Once_Init_2Machs[] = { @@ -244,7 +237,7 @@ diff -Nur a/fixincludes/fixincl.x b/fixincludes/fixincl.x (const char*)NULL }; /* -@@ -5751,8 +5799,15 @@ +@@ -5751,8 +5799,15 @@ tSCC* apzSolaris_Once_Init_2Machs[] = { tSCC zSolaris_Once_Init_2Select0[] = "@\\(#\\)pthread.h[ \t]+1.[0-9]+[ \t]+[0-9/]+ SMI"; @@ -261,7 +254,7 @@ diff -Nur a/fixincludes/fixincl.x b/fixincludes/fixincl.x { TT_EGREP, zSolaris_Once_Init_2Select0, (regex_t*)NULL }, }; /* -@@ -7308,9 +7363,9 @@ +@@ -7308,9 +7363,9 @@ static const char* apzX11_SprintfPatch[] * * List of all fixes */ @@ -274,7 +267,7 @@ diff -Nur a/fixincludes/fixincl.x b/fixincludes/fixincl.x /* * Enumerate the fixes -@@ -7371,6 +7426,7 @@ +@@ -7371,6 +7426,7 @@ typedef enum { GLIBC_C99_INLINE_3_FIXIDX, GLIBC_C99_INLINE_4_FIXIDX, GLIBC_MUTEX_INIT_FIXIDX, @@ -282,7 +275,7 @@ diff -Nur a/fixincludes/fixincl.x b/fixincludes/fixincl.x GNU_TYPES_FIXIDX, HP_INLINE_FIXIDX, HP_SYSFILE_FIXIDX, -@@ -7774,6 +7830,11 @@ +@@ -7774,6 +7830,11 @@ tFixDesc fixDescList[ FIX_COUNT ] = { GLIBC_MUTEX_INIT_TEST_CT, FD_MACH_ONLY, aGlibc_Mutex_InitTests, apzGlibc_Mutex_InitPatch, 0 }, @@ -294,10 +287,9 @@ diff -Nur a/fixincludes/fixincl.x b/fixincludes/fixincl.x { zGnu_TypesName, zGnu_TypesList, apzGnu_TypesMachs, GNU_TYPES_TEST_CT, FD_MACH_IFNOT | FD_SUBROUTINE, -diff -Nur a/fixincludes/inclhack.def b/fixincludes/inclhack.def ---- a/fixincludes/inclhack.def 2009-02-28 19:13:31.000000000 +0100 -+++ b/fixincludes/inclhack.def 2010-01-25 09:50:28.955687088 +0100 -@@ -1302,6 +1302,21 @@ +--- a/fixincludes/inclhack.def ++++ b/fixincludes/inclhack.def +@@ -1302,6 +1302,21 @@ fix = { }; @@ -319,7 +311,7 @@ diff -Nur a/fixincludes/inclhack.def b/fixincludes/inclhack.def /* * Fix these files to use the types we think they should for * ptrdiff_t, size_t, and wchar_t. -@@ -2939,24 +2954,32 @@ +@@ -2939,24 +2954,32 @@ fix = { }; /* @@ -365,7 +357,7 @@ diff -Nur a/fixincludes/inclhack.def b/fixincludes/inclhack.def c_fix = format; c_fix_arg = "#if __STDC__ - 0 == 0 && !defined(_NO_LONGLONG)\n" "%0\n" -@@ -2967,6 +2990,7 @@ +@@ -2967,6 +2990,7 @@ fix = { "(|/\*.*\*/[ \t]*\\\\\n[ \t]*)\\{.*)" ",[ \t]*0\\}" "(|[ \t].*)$"; test_text = @@ -373,7 +365,7 @@ diff -Nur a/fixincludes/inclhack.def b/fixincludes/inclhack.def '#ident "@(#)pthread.h 1.26 98/04/12 SMI"'"\n" "#define PTHREAD_MUTEX_INITIALIZER\t{{{0},0}, {{{0}}}, 0}\n" "#define PTHREAD_COND_INITIALIZER\t{{{0}, 0}, 0}\t/* DEFAULTCV */\n" -@@ -2978,17 +3002,14 @@ +@@ -2978,17 +3002,14 @@ fix = { /* @@ -393,7 +385,7 @@ diff -Nur a/fixincludes/inclhack.def b/fixincludes/inclhack.def c_fix = format; c_fix_arg = "#if __STDC__ - 0 == 0 && !defined(_NO_LONGLONG)\n" "%0\n" -@@ -3024,24 +3045,14 @@ +@@ -3024,24 +3045,14 @@ fix = { /* @@ -421,10 +413,9 @@ diff -Nur a/fixincludes/inclhack.def b/fixincludes/inclhack.def c_fix = format; c_fix_arg = "#if __STDC__ - 0 == 0 && !defined(_NO_LONGLONG)\n" "%0\n" -diff -Nur a/fixincludes/server.c b/fixincludes/server.c ---- a/fixincludes/server.c 2005-08-15 02:50:43.000000000 +0200 -+++ b/fixincludes/server.c 2010-01-25 09:50:28.955687088 +0100 -@@ -266,7 +266,7 @@ +--- a/fixincludes/server.c ++++ b/fixincludes/server.c +@@ -266,7 +266,7 @@ run_shell (const char* pz_cmd) /* Make sure the process will pay attention to us, send the supplied command, and then have it output a special marker that we can find. */ @@ -433,9 +424,8 @@ diff -Nur a/fixincludes/server.c b/fixincludes/server.c p_cur_dir, pz_cmd, z_done); fflush (server_pair.pf_write); -diff -Nur a/fixincludes/tests/base/bits/string2.h b/fixincludes/tests/base/bits/string2.h ---- a/fixincludes/tests/base/bits/string2.h 2007-03-26 15:25:26.000000000 +0200 -+++ b/fixincludes/tests/base/bits/string2.h 2010-01-25 09:50:28.955687088 +0100 +--- a/fixincludes/tests/base/bits/string2.h ++++ b/fixincludes/tests/base/bits/string2.h @@ -16,3 +16,12 @@ # define __STRING_INLINE extern __inline # endif @@ -449,75 +439,218 @@ diff -Nur a/fixincludes/tests/base/bits/string2.h b/fixincludes/tests/base/bits/ +#endif + +#endif /* GLIBC_STRING2_MEMSET_CHECK */ -diff -Nur a/fixincludes/tests/base/sys/types.h b/fixincludes/tests/base/sys/types.h ---- a/fixincludes/tests/base/sys/types.h 2004-08-31 11:27:00.000000000 +0200 -+++ b/fixincludes/tests/base/sys/types.h 2010-01-25 09:50:28.955687088 +0100 -@@ -28,3 +28,4 @@ +--- a/fixincludes/tests/base/sys/types.h ++++ b/fixincludes/tests/base/sys/types.h +@@ -28,3 +28,4 @@ typedef __WCHAR_TYPE__ wchar_t; #endif /* ushort_t */ #endif /* GNU_TYPES_CHECK */ +#if !defined(__STRICT_ANSI__) && !defined(_NO_LONGLONG) -diff -Nur a/gcc/acinclude.m4 b/gcc/acinclude.m4 ---- a/gcc/acinclude.m4 2008-06-02 21:37:45.000000000 +0200 -+++ b/gcc/acinclude.m4 2010-01-25 09:50:28.955687088 +0100 -@@ -482,3 +482,53 @@ - AC_DEFUN([gcc_AC_BUILD_EXEEXT], [ - ac_executable_extensions="$build_exeext"]) - -+ -+# --with-license=PATH -+AC_DEFUN([CSL_AC_LICENSE],[ -+ AC_ARG_WITH(license, -+ AC_HELP_STRING([--with-license], -+ [the path to the installed license component]), -+ [case "$withval" in -+ (yes) AC_MSG_ERROR([license not specified]) ;; -+ (no) with_license= ;; -+ (*) ;; -+ esac], -+ [with_license=]) -+ AC_SUBST(licensedir, $with_license) -+]) -+ -+# --with-csl-license-feature=FOO -+AC_DEFUN([CSL_AC_LICENSE_FEATURE],[ -+ AC_ARG_WITH(csl-license-feature, -+ AC_HELP_STRING([--with-csl-license-feature=FEATURE], -+ [Use FEATURE to communicate with the license manager]), -+ [case "$withval" in -+ (yes) AC_MSG_ERROR([license feature not specified]) ;; -+ (no) CSL_LICENSE_FEATURE="" ;; -+ (*) CSL_LICENSE_FEATURE="$withval" ;; -+ esac], -+ CSL_LICENSE_FEATURE="" -+ ) -+ if test x"$CSL_LICENSE_FEATURE" != x; then -+ AC_DEFINE_UNQUOTED(CSL_LICENSE_FEATURE, "$CSL_LICENSE_FEATURE", -+ [Required license feature]) -+ fi -+]) -+ -+# --with-csl-license-version=VERSION -+AC_DEFUN([CSL_AC_LICENSE_VERSION],[ -+ AC_ARG_WITH(csl-license-version, -+ AC_HELP_STRING([--with-csl-license-version=VERSION], -+ [Use VERSION to communicate with the license manager]), -+ [case "$withval" in -+ (yes) AC_MSG_ERROR([license version not specified]) ;; -+ (no) CSL_LICENSE_VERSION="" ;; -+ (*) CSL_LICENSE_VERSION="$withval" ;; -+ esac], -+ CSL_LICENSE_VERSION="" -+ ) -+ if test x"$CSL_LICENSE_VERSION" != x; then -+ AC_DEFINE_UNQUOTED(CSL_LICENSE_VERSION, "$CSL_LICENSE_VERSION", -+ [Required license version]) -+ fi -+]) -diff -Nur a/gcc/addresses.h b/gcc/addresses.h ---- a/gcc/addresses.h 2007-07-26 10:37:01.000000000 +0200 -+++ b/gcc/addresses.h 2010-01-25 09:50:28.955687088 +0100 -@@ -78,3 +78,42 @@ +--- a/gcc/Makefile.in ++++ b/gcc/Makefile.in +@@ -327,6 +327,8 @@ GCC_FOR_TARGET = $(STAGE_CC_WRAPPER) ./x + # It also specifies -isystem ./include to find, e.g., stddef.h. + GCC_CFLAGS=$(CFLAGS_FOR_TARGET) $(INTERNAL_CFLAGS) $(T_CFLAGS) $(LOOSE_WARN) -Wold-style-definition $($@-warn) -isystem ./include $(TCFLAGS) + ++EGLIBC_CONFIGS = @EGLIBC_CONFIGS@ ++ + # --------------------------------------------------- + # Programs which produce files for the target machine + # --------------------------------------------------- +@@ -408,6 +410,9 @@ TARGET_SYSTEM_ROOT = @TARGET_SYSTEM_ROOT + + xmake_file=@xmake_file@ + tmake_file=@tmake_file@ ++TM_ENDIAN_CONFIG=@TM_ENDIAN_CONFIG@ ++TM_MULTILIB_CONFIG=@TM_MULTILIB_CONFIG@ ++TM_MULTILIB_EXCEPTIONS_CONFIG=@TM_MULTILIB_EXCEPTIONS_CONFIG@ + out_file=$(srcdir)/config/@out_file@ + out_object_file=@out_object_file@ + md_file=$(srcdir)/config/@md_file@ +@@ -1249,6 +1254,7 @@ OBJS-common = \ + tree-ssa-loop-manip.o \ + tree-ssa-loop-niter.o \ + tree-ssa-loop-prefetch.o \ ++ tree-ssa-loop-promote.o \ + tree-ssa-loop-unswitch.o \ + tree-ssa-loop.o \ + tree-ssa-math-opts.o \ +@@ -1258,6 +1264,7 @@ OBJS-common = \ + tree-ssa-pre.o \ + tree-ssa-propagate.o \ + tree-ssa-reassoc.o \ ++ tree-ssa-remove-local-statics.o \ + tree-ssa-sccvn.o \ + tree-ssa-sink.o \ + tree-ssa-structalias.o \ +@@ -1674,7 +1681,7 @@ libgcc-support: libgcc.mvars stmp-int-hd + $(MACHMODE_H) $(FPBIT) $(DPBIT) $(TPBIT) $(LIB2ADD) \ + $(LIB2ADD_ST) $(LIB2ADDEH) $(srcdir)/emutls.c gcov-iov.h $(SFP_MACHINE) + +-libgcc.mvars: config.status Makefile $(LIB2ADD) $(LIB2ADD_ST) specs \ ++libgcc.mvars: config.status Makefile $(LIB2ADD) $(LIB2ADD_ST) specs $(tmake_file) \ + xgcc$(exeext) + : > tmp-libgcc.mvars + echo LIB1ASMFUNCS = '$(LIB1ASMFUNCS)' >> tmp-libgcc.mvars +@@ -1728,7 +1735,7 @@ libgcc.mvars: config.status Makefile $(L + # driver program needs to select the library directory based on the + # switches. + multilib.h: s-mlib; @true +-s-mlib: $(srcdir)/genmultilib Makefile ++s-mlib: $(srcdir)/genmultilib Makefile $(tmakefile) + if test @enable_multilib@ = yes \ + || test -n "$(MULTILIB_OSDIRNAMES)"; then \ + $(SHELL) $(srcdir)/genmultilib \ +@@ -1739,10 +1746,11 @@ s-mlib: $(srcdir)/genmultilib Makefile + "$(MULTILIB_EXTRA_OPTS)" \ + "$(MULTILIB_EXCLUSIONS)" \ + "$(MULTILIB_OSDIRNAMES)" \ ++ "$(MULTILIB_ALIASES)" \ + "@enable_multilib@" \ + > tmp-mlib.h; \ + else \ +- $(SHELL) $(srcdir)/genmultilib '' '' '' '' '' '' '' no \ ++ $(SHELL) $(srcdir)/genmultilib '' '' '' '' '' '' '' '' no \ + > tmp-mlib.h; \ + fi + $(SHELL) $(srcdir)/../move-if-change tmp-mlib.h multilib.h +@@ -1816,7 +1824,7 @@ gcc.srcextra: gengtype-lex.c + + incpath.o: incpath.c incpath.h $(CONFIG_H) $(SYSTEM_H) $(CPPLIB_H) \ + intl.h prefix.h coretypes.h $(TM_H) cppdefault.h $(TARGET_H) \ +- $(MACHMODE_H) ++ $(MACHMODE_H) $(FLAGS_H) toplev.h + + c-decl.o : c-decl.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(TREE_H) \ + $(RTL_H) $(C_TREE_H) $(GGC_H) $(TARGET_H) $(FLAGS_H) $(FUNCTION_H) output.h \ +@@ -1900,7 +1908,7 @@ c-opts.o : c-opts.c $(CONFIG_H) $(SYSTEM + $(TREE_H) $(C_PRAGMA_H) $(FLAGS_H) $(TOPLEV_H) langhooks.h \ + $(TREE_INLINE_H) $(DIAGNOSTIC_H) intl.h debug.h $(C_COMMON_H) \ + opts.h options.h $(MKDEPS_H) incpath.h cppdefault.h $(TARGET_H) \ +- $(TM_P_H) $(VARRAY_H) ++ $(TM_P_H) $(VARRAY_H) $(C_TREE_H) + $(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) \ + $< $(OUTPUT_OPTION) @TARGET_SYSTEM_ROOT_DEFINE@ + +@@ -1953,7 +1961,8 @@ DRIVER_DEFINES = \ + -DTOOLDIR_BASE_PREFIX=\"$(libsubdir_to_prefix)$(prefix_to_exec_prefix)\" \ + @TARGET_SYSTEM_ROOT_DEFINE@ \ + $(VALGRIND_DRIVER_DEFINES) \ +- `test "X$${SHLIB_LINK}" = "X" || test "@enable_shared@" != "yes" || echo "-DENABLE_SHARED_LIBGCC"` ++ `test "X$${SHLIB_LINK}" = "X" || test "@enable_shared@" != "yes" || echo "-DENABLE_SHARED_LIBGCC"` \ ++ -DCONFIGURE_SPECS="\"@CONFIGURE_SPECS@\"" + + gcc.o: gcc.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) intl.h multilib.h \ + Makefile $(lang_specs_files) specs.h prefix.h $(GCC_H) $(FLAGS_H) \ +@@ -2176,6 +2185,9 @@ tree-ssa-pre.o : tree-ssa-pre.c $(TREE_F + alloc-pool.h $(BASIC_BLOCK_H) $(BITMAP_H) $(HASHTAB_H) $(GIMPLE_H) \ + $(TREE_INLINE_H) tree-iterator.h tree-ssa-sccvn.h $(PARAMS_H) \ + $(DBGCNT_H) ++tree-ssa-remove-local-statics.o: tree-ssa-remove-local-statics.c \ ++ coretypes.h $(CONFIG_H) $(SYSTEM_H) $(BASIC_BLOCK_H) tree.h tree-pass.h \ ++ $(TM_H) $(HASHTAB_H) $(BASIC_BLOCK_H) + tree-ssa-sccvn.o : tree-ssa-sccvn.c $(TREE_FLOW_H) $(CONFIG_H) \ + $(SYSTEM_H) $(TREE_H) $(GGC_H) $(DIAGNOSTIC_H) $(TIMEVAR_H) $(FIBHEAP_H) \ + $(TM_H) coretypes.h $(TREE_DUMP_H) tree-pass.h $(FLAGS_H) $(CFGLOOP_H) \ +@@ -2271,6 +2283,12 @@ tree-ssa-loop-prefetch.o: tree-ssa-loop- + $(CFGLOOP_H) $(PARAMS_H) langhooks.h $(BASIC_BLOCK_H) hard-reg-set.h \ + tree-chrec.h $(TOPLEV_H) langhooks.h $(TREE_INLINE_H) $(TREE_DATA_REF_H) \ + $(OPTABS_H) ++tree-ssa-loop-promote.o: tree-ssa-loop-promote.c \ ++ coretypes.h $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(TOPLEV_H) \ ++ $(RTL_H) $(TM_P_H) hard-reg-set.h $(OBSTACK_H) $(BASIC_BLOCK_H) \ ++ pointer-set.h intl.h $(TREE_H) $(GIMPLE_H) $(HASHTAB_H) $(DIAGNOSTIC_H) \ ++ $(TREE_FLOW_H) $(TREE_DUMP_H) $(CFGLOOP_H) $(FLAGS_H) $(TIMEVAR_H) \ ++ tree-pass.h $(TM_H) + tree-predcom.o: tree-predcom.c $(CONFIG_H) $(SYSTEM_H) $(TREE_H) $(TM_P_H) \ + $(CFGLOOP_H) $(TREE_FLOW_H) $(GGC_H) $(TREE_DATA_REF_H) $(SCEV_H) \ + $(PARAMS_H) $(DIAGNOSTIC_H) tree-pass.h $(TM_H) coretypes.h tree-affine.h \ +@@ -2865,7 +2883,7 @@ postreload.o : postreload.c $(CONFIG_H) + $(RTL_H) $(REAL_H) $(FLAGS_H) $(EXPR_H) $(OPTABS_H) reload.h $(REGS_H) \ + hard-reg-set.h insn-config.h $(BASIC_BLOCK_H) $(RECOG_H) output.h \ + $(FUNCTION_H) $(TOPLEV_H) cselib.h $(TM_P_H) except.h $(TREE_H) $(MACHMODE_H) \ +- $(OBSTACK_H) $(TIMEVAR_H) tree-pass.h $(DF_H) $(DBGCNT_H) ++ $(OBSTACK_H) $(TIMEVAR_H) tree-pass.h addresses.h $(DF_H) $(DBGCNT_H) + postreload-gcse.o : postreload-gcse.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \ + $(TM_H) $(RTL_H) $(REGS_H) hard-reg-set.h $(FLAGS_H) insn-config.h \ + $(RECOG_H) $(EXPR_H) $(BASIC_BLOCK_H) $(FUNCTION_H) output.h $(TOPLEV_H) \ +@@ -3582,7 +3600,7 @@ gcov-dump$(exeext): $(GCOV_DUMP_OBJS) $( + # be rebuilt. + + # Build the include directories. +-stmp-int-hdrs: $(STMP_FIXINC) $(USER_H) $(UNWIND_H) fixinc_list ++stmp-int-hdrs: $(STMP_FIXINC) $(USER_H) $(UNWIND_H) + # Copy in the headers provided with gcc. + # The sed command gets just the last file name component; + # this is necessary because VPATH could add a dirname. +@@ -3601,21 +3619,23 @@ stmp-int-hdrs: $(STMP_FIXINC) $(USER_H) + done + rm -f include/unwind.h + cp $(UNWIND_H) include/unwind.h +- set -e; for ml in `cat fixinc_list`; do \ +- sysroot_headers_suffix=`echo $${ml} | sed -e 's/;.*$$//'`; \ +- multi_dir=`echo $${ml} | sed -e 's/^[^;]*;//'`; \ +- fix_dir=include-fixed$${multi_dir}; \ +- if $(LIMITS_H_TEST) ; then \ +- cat $(srcdir)/limitx.h $(srcdir)/glimits.h $(srcdir)/limity.h > tmp-xlimits.h; \ +- else \ +- cat $(srcdir)/glimits.h > tmp-xlimits.h; \ +- fi; \ +- $(mkinstalldirs) $${fix_dir}; \ +- chmod a+rx $${fix_dir} || true; \ +- rm -f $${fix_dir}/limits.h; \ +- mv tmp-xlimits.h $${fix_dir}/limits.h; \ +- chmod a+r $${fix_dir}/limits.h; \ +- done ++ set -e; if [ -f fixinc_list ] ; then \ ++ for ml in `cat fixinc_list`; do \ ++ sysroot_headers_suffix=`echo $${ml} | sed -e 's/;.*$$//'`; \ ++ multi_dir=`echo $${ml} | sed -e 's/^[^;]*;//'`; \ ++ fix_dir=include-fixed$${multi_dir}; \ ++ if $(LIMITS_H_TEST) ; then \ ++ cat $(srcdir)/limitx.h $(srcdir)/glimits.h $(srcdir)/limity.h > tmp-xlimits.h; \ ++ else \ ++ cat $(srcdir)/glimits.h > tmp-xlimits.h; \ ++ fi; \ ++ $(mkinstalldirs) $${fix_dir}; \ ++ chmod a+rx $${fix_dir} || true; \ ++ rm -f $${fix_dir}/limits.h; \ ++ mv tmp-xlimits.h $${fix_dir}/limits.h; \ ++ chmod a+r $${fix_dir}/limits.h; \ ++ done; \ ++ fi + # Install the README + rm -f include-fixed/README + cp $(srcdir)/../fixincludes/README-fixinc include-fixed/README +@@ -4340,16 +4360,18 @@ real-install-headers-cp: + + # Install supporting files for fixincludes to be run later. + install-mkheaders: stmp-int-hdrs $(STMP_FIXPROTO) install-itoolsdirs \ +- macro_list fixinc_list ++ macro_list + $(INSTALL_DATA) $(srcdir)/gsyslimits.h \ + $(DESTDIR)$(itoolsdatadir)/gsyslimits.h + $(INSTALL_DATA) macro_list $(DESTDIR)$(itoolsdatadir)/macro_list +- $(INSTALL_DATA) fixinc_list $(DESTDIR)$(itoolsdatadir)/fixinc_list +- set -e; for ml in `cat fixinc_list`; do \ +- multi_dir=`echo $${ml} | sed -e 's/^[^;]*;//'`; \ +- $(mkinstalldirs) $(DESTDIR)$(itoolsdatadir)/include$${multi_dir}; \ +- $(INSTALL_DATA) include-fixed$${multidir}/limits.h $(DESTDIR)$(itoolsdatadir)/include$${multi_dir}/limits.h; \ +- done ++ set -e; if [ -f fixinc_list ] ; then \ ++ $(INSTALL_DATA) fixinc_list $(DESTDIR)$(itoolsdatadir)/fixinc_list; \ ++ for ml in `cat fixinc_list`; do \ ++ multi_dir=`echo $${ml} | sed -e 's/^[^;]*;//'`; \ ++ $(mkinstalldirs) $(DESTDIR)$(itoolsdatadir)/include$${multi_dir}; \ ++ $(INSTALL_DATA) include-fixed$${multidir}/limits.h $(DESTDIR)$(itoolsdatadir)/include$${multi_dir}/limits.h; \ ++ done; \ ++ fi + $(INSTALL_SCRIPT) $(srcdir)/../mkinstalldirs \ + $(DESTDIR)$(itoolsdir)/mkinstalldirs ; \ + if [ x$(STMP_FIXPROTO) != x ] ; then \ +--- a/gcc/addresses.h ++++ b/gcc/addresses.h +@@ -78,3 +78,42 @@ regno_ok_for_base_p (unsigned regno, enu return ok_for_base_p_1 (regno, mode, outer_code, index_code); } @@ -560,42 +693,9 @@ diff -Nur a/gcc/addresses.h b/gcc/addresses.h + + return ok_for_index_p_1 (regno, mode); +} -diff -Nur a/gcc/calls.c b/gcc/calls.c ---- a/gcc/calls.c 2009-02-20 12:19:34.000000000 +0100 -+++ b/gcc/calls.c 2010-01-25 09:50:28.955687088 +0100 -@@ -3803,7 +3803,7 @@ - cse'ing of library calls could delete a call and leave the pop. */ - NO_DEFER_POP; - valreg = (mem_value == 0 && outmode != VOIDmode -- ? hard_libcall_value (outmode) : NULL_RTX); -+ ? hard_libcall_value (outmode, orgfun) : NULL_RTX); - - /* Stack must be properly aligned now. */ - gcc_assert (!(stack_pointer_delta -@@ -4048,8 +4048,17 @@ - /* We need to make a save area. */ - unsigned int size = arg->locate.size.constant * BITS_PER_UNIT; - enum machine_mode save_mode = mode_for_size (size, MODE_INT, 1); -- rtx adr = memory_address (save_mode, XEXP (arg->stack_slot, 0)); -- rtx stack_area = gen_rtx_MEM (save_mode, adr); -+ rtx adr; -+ rtx stack_area; -+ -+ /* We can only use save_mode if the arg is sufficiently -+ aligned. */ -+ if (STRICT_ALIGNMENT -+ && GET_MODE_ALIGNMENT (save_mode) > arg->locate.boundary) -+ save_mode = BLKmode; -+ -+ adr = memory_address (save_mode, XEXP (arg->stack_slot, 0)); -+ stack_area = gen_rtx_MEM (save_mode, adr); - - if (save_mode == BLKmode) - { -diff -Nur a/gcc/c-common.c b/gcc/c-common.c ---- a/gcc/c-common.c 2009-03-30 19:42:27.000000000 +0200 -+++ b/gcc/c-common.c 2010-01-25 09:50:28.955687088 +0100 -@@ -33,7 +33,6 @@ +--- a/gcc/c-common.c ++++ b/gcc/c-common.c +@@ -33,7 +33,6 @@ along with GCC; see the file COPYING3. #include "varray.h" #include "expr.h" #include "c-common.h" @@ -603,7 +703,7 @@ diff -Nur a/gcc/c-common.c b/gcc/c-common.c #include "tm_p.h" #include "obstack.h" #include "cpplib.h" -@@ -42,6 +41,7 @@ +@@ -42,6 +41,7 @@ along with GCC; see the file COPYING3. #include "tree-inline.h" #include "c-tree.h" #include "toplev.h" @@ -611,7 +711,7 @@ diff -Nur a/gcc/c-common.c b/gcc/c-common.c #include "tree-iterator.h" #include "hashtab.h" #include "tree-mudflap.h" -@@ -497,6 +497,10 @@ +@@ -497,6 +497,10 @@ tree (*make_fname_decl) (tree, int); This is a count, since unevaluated expressions can nest. */ int skip_evaluation; @@ -622,7 +722,7 @@ diff -Nur a/gcc/c-common.c b/gcc/c-common.c /* Information about how a function name is generated. */ struct fname_var_t { -@@ -7522,6 +7526,68 @@ +@@ -7522,6 +7526,68 @@ c_parse_error (const char *gmsgid, enum #undef catenate_messages } @@ -691,10 +791,9 @@ diff -Nur a/gcc/c-common.c b/gcc/c-common.c /* Walk a gimplified function and warn for functions whose return value is ignored and attribute((warn_unused_result)) is set. This is done before inlining, so we don't have to worry about that. */ -diff -Nur a/gcc/c-common.h b/gcc/c-common.h ---- a/gcc/c-common.h 2009-03-30 19:42:27.000000000 +0200 -+++ b/gcc/c-common.h 2010-01-25 09:50:28.955687088 +0100 -@@ -658,6 +658,11 @@ +--- a/gcc/c-common.h ++++ b/gcc/c-common.h +@@ -658,6 +658,11 @@ extern int max_tinst_depth; extern int skip_evaluation; @@ -706,10 +805,9 @@ diff -Nur a/gcc/c-common.h b/gcc/c-common.h /* C types are partitioned into three subsets: object, function, and incomplete types. */ #define C_TYPE_OBJECT_P(type) \ -diff -Nur a/gcc/c-convert.c b/gcc/c-convert.c ---- a/gcc/c-convert.c 2009-02-20 16:20:38.000000000 +0100 -+++ b/gcc/c-convert.c 2010-01-25 09:50:28.955687088 +0100 -@@ -70,6 +70,7 @@ +--- a/gcc/c-convert.c ++++ b/gcc/c-convert.c +@@ -70,6 +70,7 @@ convert (tree type, tree expr) tree e = expr; enum tree_code code = TREE_CODE (type); const char *invalid_conv_diag; @@ -717,7 +815,7 @@ diff -Nur a/gcc/c-convert.c b/gcc/c-convert.c if (type == error_mark_node || expr == error_mark_node -@@ -85,6 +86,9 @@ +@@ -85,6 +86,9 @@ convert (tree type, tree expr) if (type == TREE_TYPE (expr)) return expr; @@ -727,10 +825,9 @@ diff -Nur a/gcc/c-convert.c b/gcc/c-convert.c if (TYPE_MAIN_VARIANT (type) == TYPE_MAIN_VARIANT (TREE_TYPE (expr))) return fold_convert (type, expr); -diff -Nur a/gcc/c-decl.c b/gcc/c-decl.c ---- a/gcc/c-decl.c 2009-02-20 16:20:38.000000000 +0100 -+++ b/gcc/c-decl.c 2010-01-25 09:50:28.955687088 +0100 -@@ -3994,6 +3994,7 @@ +--- a/gcc/c-decl.c ++++ b/gcc/c-decl.c +@@ -4001,6 +4001,7 @@ grokdeclarator (const struct c_declarato bool bitfield = width != NULL; tree element_type; struct c_arg_info *arg_info = 0; @@ -738,7 +835,7 @@ diff -Nur a/gcc/c-decl.c b/gcc/c-decl.c if (decl_context == FUNCDEF) funcdef_flag = true, decl_context = NORMAL; -@@ -4531,6 +4532,12 @@ +@@ -4538,6 +4539,12 @@ grokdeclarator (const struct c_declarato error ("%qs declared as function returning an array", name); type = integer_type_node; } @@ -751,7 +848,7 @@ diff -Nur a/gcc/c-decl.c b/gcc/c-decl.c /* Construct the function type and go to the next inner layer of declarator. */ -@@ -5044,6 +5051,7 @@ +@@ -5051,6 +5058,7 @@ grokparms (struct c_arg_info *arg_info, { tree parm, type, typelt; unsigned int parmno; @@ -759,7 +856,7 @@ diff -Nur a/gcc/c-decl.c b/gcc/c-decl.c /* If there is a parameter of incomplete type in a definition, this is an error. In a declaration this is valid, and a -@@ -5087,6 +5095,14 @@ +@@ -5094,6 +5102,14 @@ grokparms (struct c_arg_info *arg_info, } } @@ -774,7 +871,7 @@ diff -Nur a/gcc/c-decl.c b/gcc/c-decl.c if (DECL_NAME (parm) && TREE_USED (parm)) warn_if_shadowing (parm); } -@@ -8071,7 +8087,7 @@ +@@ -8080,7 +8096,7 @@ c_write_global_declarations (void) /* Don't waste time on further processing if -fsyntax-only or we've encountered errors. */ @@ -783,10 +880,205 @@ diff -Nur a/gcc/c-decl.c b/gcc/c-decl.c return; /* Close the external scope. */ -diff -Nur a/gcc/cfgexpand.c b/gcc/cfgexpand.c ---- a/gcc/cfgexpand.c 2009-07-11 21:06:26.000000000 +0200 -+++ b/gcc/cfgexpand.c 2010-01-25 09:50:28.955687088 +0100 -@@ -488,7 +488,8 @@ +--- a/gcc/c-opts.c ++++ b/gcc/c-opts.c +@@ -40,6 +40,7 @@ along with GCC; see the file COPYING3. + #include "mkdeps.h" + #include "target.h" + #include "tm_p.h" ++#include "c-tree.h" /* For c_cpp_error. */ + + #ifndef DOLLARS_IN_IDENTIFIERS + # define DOLLARS_IN_IDENTIFIERS true +@@ -201,6 +202,7 @@ c_common_init_options (unsigned int argc + { + static const unsigned int lang_flags[] = {CL_C, CL_ObjC, CL_CXX, CL_ObjCXX}; + unsigned int i, result; ++ struct cpp_callbacks *cb; + + /* This is conditionalized only because that is the way the front + ends used to do it. Maybe this should be unconditional? */ +@@ -216,6 +218,8 @@ c_common_init_options (unsigned int argc + + parse_in = cpp_create_reader (c_dialect_cxx () ? CLK_GNUCXX: CLK_GNUC89, + ident_hash, line_table); ++ cb = cpp_get_callbacks (parse_in); ++ cb->error = c_cpp_error; + + cpp_opts = cpp_get_options (parse_in); + cpp_opts->dollars_in_ident = DOLLARS_IN_IDENTIFIERS; +@@ -333,12 +337,12 @@ c_common_handle_option (size_t scode, co + or environment var dependency generation is used. */ + cpp_opts->deps.style = (code == OPT_M ? DEPS_SYSTEM: DEPS_USER); + flag_no_output = 1; +- cpp_opts->inhibit_warnings = 1; + break; + + case OPT_MD: + case OPT_MMD: + cpp_opts->deps.style = (code == OPT_MD ? DEPS_SYSTEM: DEPS_USER); ++ cpp_opts->deps.need_preprocessor_output = true; + deps_file = arg; + break; + +@@ -444,7 +448,6 @@ c_common_handle_option (size_t scode, co + break; + + case OPT_Werror: +- cpp_opts->warnings_are_errors = value; + global_dc->warning_as_error_requested = value; + break; + +@@ -503,10 +506,6 @@ c_common_handle_option (size_t scode, co + warn_strict_null_sentinel = value; + break; + +- case OPT_Wsystem_headers: +- cpp_opts->warn_system_headers = value; +- break; +- + case OPT_Wtraditional: + cpp_opts->warn_traditional = value; + break; +@@ -895,8 +894,6 @@ c_common_handle_option (size_t scode, co + c_common_post_options, so that a subsequent -Wno-endif-labels + is not overridden. */ + case OPT_pedantic_errors: +- cpp_opts->pedantic_errors = 1; +- /* Fall through. */ + case OPT_pedantic: + cpp_opts->pedantic = 1; + cpp_opts->warn_endif_labels = 1; +@@ -971,10 +968,6 @@ c_common_handle_option (size_t scode, co + flag_undef = 1; + break; + +- case OPT_w: +- cpp_opts->inhibit_warnings = 1; +- break; +- + case OPT_v: + verbose = true; + break; +@@ -1159,10 +1152,6 @@ c_common_post_options (const char **pfil + + input_location = UNKNOWN_LOCATION; + +- /* If an error has occurred in cpplib, note it so we fail +- immediately. */ +- errorcount += cpp_errors (parse_in); +- + *pfilename = this_input_filename + = cpp_read_main_file (parse_in, in_fnames[0]); + /* Don't do any compilation or preprocessing if there is no input file. */ +@@ -1274,7 +1263,8 @@ c_common_finish (void) + { + FILE *deps_stream = NULL; + +- if (cpp_opts->deps.style != DEPS_NONE) ++ /* Don't write the deps file if there are errors. */ ++ if (cpp_opts->deps.style != DEPS_NONE && errorcount == 0) + { + /* If -M or -MM was seen without -MF, default output to the + output stream. */ +@@ -1290,7 +1280,7 @@ c_common_finish (void) + + /* For performance, avoid tearing down cpplib's internal structures + with cpp_destroy (). */ +- errorcount += cpp_finish (parse_in, deps_stream); ++ cpp_finish (parse_in, deps_stream); + + if (deps_stream && deps_stream != out_stream + && (ferror (deps_stream) || fclose (deps_stream))) +--- a/gcc/c-ppoutput.c ++++ b/gcc/c-ppoutput.c +@@ -521,6 +521,7 @@ pp_file_change (const struct line_map *m + + if (map != NULL) + { ++ input_location = map->start_location; + if (print.first_time) + { + /* Avoid printing foo.i when the main file is foo.c. */ +--- a/gcc/c-tree.h ++++ b/gcc/c-tree.h +@@ -647,4 +647,8 @@ extern void c_write_global_declarations + extern void pedwarn_c90 (location_t, int opt, const char *, ...) ATTRIBUTE_GCC_CDIAG(3,4); + extern void pedwarn_c99 (location_t, int opt, const char *, ...) ATTRIBUTE_GCC_CDIAG(3,4); + ++extern bool c_cpp_error (cpp_reader *, int, location_t, unsigned int, ++ const char *, va_list *) ++ ATTRIBUTE_GCC_CDIAG(5,0); ++ + #endif /* ! GCC_C_TREE_H */ +--- a/gcc/c-typeck.c ++++ b/gcc/c-typeck.c +@@ -1765,6 +1765,7 @@ default_conversion (tree exp) + tree orig_exp; + tree type = TREE_TYPE (exp); + enum tree_code code = TREE_CODE (type); ++ tree promoted_type; + + /* Functions and arrays have been converted during parsing. */ + gcc_assert (code != FUNCTION_TYPE); +@@ -1801,6 +1802,10 @@ default_conversion (tree exp) + if (exp == error_mark_node) + return error_mark_node; + ++ promoted_type = targetm.promoted_type (type); ++ if (promoted_type) ++ return convert (promoted_type, exp); ++ + if (INTEGRAL_TYPE_P (type)) + return perform_integral_promotions (exp); + +--- a/gcc/c.opt ++++ b/gcc/c.opt +@@ -720,6 +720,10 @@ fpreprocessed + C ObjC C++ ObjC++ + Treat the input file as already preprocessed + ++fremove-local-statics ++C C++ Var(flag_remove_local_statics) Optimization ++Convert function-local static variables to automatic variables when it is safe to do so ++ + freplace-objc-classes + ObjC ObjC++ + Used in Fix-and-Continue mode to indicate that object files may be swapped in at runtime +--- a/gcc/calls.c ++++ b/gcc/calls.c +@@ -3806,7 +3806,7 @@ emit_library_call_value_1 (int retval, r + cse'ing of library calls could delete a call and leave the pop. */ + NO_DEFER_POP; + valreg = (mem_value == 0 && outmode != VOIDmode +- ? hard_libcall_value (outmode) : NULL_RTX); ++ ? hard_libcall_value (outmode, orgfun) : NULL_RTX); + + /* Stack must be properly aligned now. */ + gcc_assert (!(stack_pointer_delta +@@ -4051,8 +4051,17 @@ store_one_arg (struct arg_data *arg, rtx + /* We need to make a save area. */ + unsigned int size = arg->locate.size.constant * BITS_PER_UNIT; + enum machine_mode save_mode = mode_for_size (size, MODE_INT, 1); +- rtx adr = memory_address (save_mode, XEXP (arg->stack_slot, 0)); +- rtx stack_area = gen_rtx_MEM (save_mode, adr); ++ rtx adr; ++ rtx stack_area; ++ ++ /* We can only use save_mode if the arg is sufficiently ++ aligned. */ ++ if (STRICT_ALIGNMENT ++ && GET_MODE_ALIGNMENT (save_mode) > arg->locate.boundary) ++ save_mode = BLKmode; ++ ++ adr = memory_address (save_mode, XEXP (arg->stack_slot, 0)); ++ stack_area = gen_rtx_MEM (save_mode, adr); + + if (save_mode == BLKmode) + { +--- a/gcc/cfgexpand.c ++++ b/gcc/cfgexpand.c +@@ -488,7 +488,8 @@ get_decl_align_unit (tree decl) { unsigned int align; @@ -796,10 +1088,9 @@ diff -Nur a/gcc/cfgexpand.c b/gcc/cfgexpand.c if (align > MAX_SUPPORTED_STACK_ALIGNMENT) align = MAX_SUPPORTED_STACK_ALIGNMENT; -diff -Nur a/gcc/cgraph.c b/gcc/cgraph.c ---- a/gcc/cgraph.c 2008-11-16 23:31:58.000000000 +0100 -+++ b/gcc/cgraph.c 2010-01-25 09:50:28.955687088 +0100 -@@ -475,9 +475,11 @@ +--- a/gcc/cgraph.c ++++ b/gcc/cgraph.c +@@ -475,9 +475,11 @@ cgraph_node (tree decl) if (DECL_CONTEXT (decl) && TREE_CODE (DECL_CONTEXT (decl)) == FUNCTION_DECL) { node->origin = cgraph_node (DECL_CONTEXT (decl)); @@ -811,10 +1102,9 @@ diff -Nur a/gcc/cgraph.c b/gcc/cgraph.c } if (assembler_name_hash) { -diff -Nur a/gcc/cgraph.h b/gcc/cgraph.h ---- a/gcc/cgraph.h 2009-03-23 17:29:33.000000000 +0100 -+++ b/gcc/cgraph.h 2010-01-25 09:50:28.955687088 +0100 -@@ -185,6 +185,8 @@ +--- a/gcc/cgraph.h ++++ b/gcc/cgraph.h +@@ -185,6 +185,8 @@ struct cgraph_node GTY((chain_next ("%h. unsigned output : 1; /* Set for aliases once they got through assemble_alias. */ unsigned alias : 1; @@ -823,10 +1113,9 @@ diff -Nur a/gcc/cgraph.h b/gcc/cgraph.h /* In non-unit-at-a-time mode the function body of inline candidates is saved into clone before compiling so the function in original form can be -diff -Nur a/gcc/common.opt b/gcc/common.opt ---- a/gcc/common.opt 2009-03-28 18:28:45.000000000 +0100 -+++ b/gcc/common.opt 2010-01-25 09:50:28.955687088 +0100 -@@ -153,6 +153,10 @@ +--- a/gcc/common.opt ++++ b/gcc/common.opt +@@ -153,6 +153,10 @@ Wpadded Common Var(warn_padded) Warning Warn when padding is required to align structure members @@ -837,7 +1126,7 @@ diff -Nur a/gcc/common.opt b/gcc/common.opt Wshadow Common Var(warn_shadow) Warning Warn when one local variable shadows another -@@ -270,6 +274,12 @@ +@@ -270,6 +274,12 @@ Common Separate fabi-version= Common Joined UInteger Var(flag_abi_version) Init(2) @@ -850,7 +1139,7 @@ diff -Nur a/gcc/common.opt b/gcc/common.opt falign-functions Common Report Var(align_functions,0) Optimization UInteger Align the start of functions -@@ -467,6 +477,10 @@ +@@ -467,6 +477,10 @@ fearly-inlining Common Report Var(flag_early_inlining) Init(1) Optimization Perform early inlining @@ -861,7 +1150,7 @@ diff -Nur a/gcc/common.opt b/gcc/common.opt feliminate-dwarf2-dups Common Report Var(flag_eliminate_dwarf2_dups) Perform DWARF2 duplicate elimination -@@ -895,6 +909,10 @@ +@@ -895,6 +909,10 @@ fprofile-values Common Report Var(flag_profile_values) Insert code to profile values of expressions @@ -872,7 +1161,7 @@ diff -Nur a/gcc/common.opt b/gcc/common.opt frandom-seed Common -@@ -1227,6 +1245,15 @@ +@@ -1227,6 +1245,15 @@ ftree-pre Common Report Var(flag_tree_pre) Optimization Enable SSA-PRE optimization on trees @@ -888,154 +1177,473 @@ diff -Nur a/gcc/common.opt b/gcc/common.opt ftree-reassoc Common Report Var(flag_tree_reassoc) Init(1) Optimization Enable reassociation on tree level -diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c ---- a/gcc/config/arm/arm.c 2009-06-02 09:18:16.000000000 +0200 -+++ b/gcc/config/arm/arm.c 2010-01-25 09:50:28.975687047 +0100 -@@ -43,6 +43,7 @@ - #include "optabs.h" - #include "toplev.h" - #include "recog.h" -+#include "cgraph.h" - #include "ggc.h" - #include "except.h" - #include "c-pragma.h" -@@ -53,6 +54,8 @@ - #include "debug.h" - #include "langhooks.h" - #include "df.h" -+#include "intl.h" -+#include "params.h" - - /* Forward definitions of types. */ - typedef struct minipool_node Mnode; -@@ -110,6 +113,7 @@ - static unsigned long arm_isr_value (tree); - static unsigned long arm_compute_func_type (void); - static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *); -+static tree arm_handle_pcs_attribute (tree *, tree, tree, int, bool *); - static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *); - #if TARGET_DLLIMPORT_DECL_ATTRIBUTES - static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *); -@@ -123,6 +127,10 @@ - static int count_insns_for_constant (HOST_WIDE_INT, int); - static int arm_get_strip_length (int); - static bool arm_function_ok_for_sibcall (tree, tree); -+static bool arm_return_in_memory (const_tree, const_tree); -+static rtx arm_function_value (const_tree, const_tree, bool); -+static rtx arm_libcall_value (enum machine_mode, rtx); -+ - static void arm_internal_label (FILE *, const char *, unsigned long); - static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, - tree); -@@ -148,6 +156,9 @@ - static rtx emit_set_insn (rtx, rtx); - static int arm_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode, - tree, bool); -+static rtx aapcs_allocate_return_reg (enum machine_mode, const_tree, -+ const_tree); -+static int aapcs_select_return_coproc (const_tree, const_tree); - - #ifdef OBJECT_FORMAT_ELF - static void arm_elf_asm_constructor (rtx, int) ATTRIBUTE_UNUSED; -@@ -175,6 +186,7 @@ - static bool arm_output_ttype (rtx); - #endif - static void arm_dwarf_handle_frame_unspec (const char *, rtx, int); -+static rtx arm_dwarf_register_span(rtx); - - static tree arm_cxx_guard_type (void); - static bool arm_cxx_guard_mask_bit (void); -@@ -197,6 +209,15 @@ - static int arm_issue_rate (void); - static void arm_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED; - static bool arm_allocate_stack_slots_for_args (void); -+static bool arm_warn_func_result (void); -+static int arm_multipass_dfa_lookahead (void); -+static const char *arm_invalid_parameter_type (const_tree t); -+static const char *arm_invalid_return_type (const_tree t); -+static tree arm_promoted_type (const_tree t); -+static tree arm_convert_to_type (tree type, tree expr); -+static bool arm_scalar_mode_supported_p (enum machine_mode); -+static int arm_vector_min_alignment (const_tree type); -+static bool arm_vector_always_misalign(const_tree); - - - /* Initialize the GCC target structure. */ -@@ -256,6 +277,12 @@ - #undef TARGET_FUNCTION_OK_FOR_SIBCALL - #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall - -+#undef TARGET_FUNCTION_VALUE -+#define TARGET_FUNCTION_VALUE arm_function_value -+ -+#undef TARGET_LIBCALL_VALUE -+#define TARGET_LIBCALL_VALUE arm_libcall_value -+ - #undef TARGET_ASM_OUTPUT_MI_THUNK - #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk - #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK -@@ -299,6 +326,9 @@ - #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS - #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS arm_allocate_stack_slots_for_args - -+#undef TARGET_WARN_FUNC_RESULT -+#define TARGET_WARN_FUNC_RESULT arm_warn_func_result -+ - #undef TARGET_DEFAULT_SHORT_ENUMS - #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums - -@@ -353,6 +383,9 @@ - #undef TARGET_ASM_TTYPE - #define TARGET_ASM_TTYPE arm_output_ttype - -+#undef TARGET_CXX_TTYPE_REF_ENCODE -+#define TARGET_CXX_TTYPE_REF_ENCODE hook_cxx_ttype_ref_in_bit0 -+ - #undef TARGET_ARM_EABI_UNWINDER - #define TARGET_ARM_EABI_UNWINDER true - #endif /* TARGET_UNWIND_INFO */ -@@ -360,6 +393,9 @@ - #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC - #define TARGET_DWARF_HANDLE_FRAME_UNSPEC arm_dwarf_handle_frame_unspec - -+#undef TARGET_DWARF_REGISTER_SPAN -+#define TARGET_DWARF_REGISTER_SPAN arm_dwarf_register_span -+ - #undef TARGET_CANNOT_COPY_INSN_P - #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p - -@@ -398,6 +434,30 @@ - #define TARGET_ASM_OUTPUT_DWARF_DTPREL arm_output_dwarf_dtprel - #endif - -+#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD -+#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD arm_multipass_dfa_lookahead -+ -+#undef TARGET_INVALID_PARAMETER_TYPE -+#define TARGET_INVALID_PARAMETER_TYPE arm_invalid_parameter_type -+ -+#undef TARGET_INVALID_RETURN_TYPE -+#define TARGET_INVALID_RETURN_TYPE arm_invalid_return_type -+ -+#undef TARGET_PROMOTED_TYPE -+#define TARGET_PROMOTED_TYPE arm_promoted_type -+ -+#undef TARGET_CONVERT_TO_TYPE -+#define TARGET_CONVERT_TO_TYPE arm_convert_to_type -+ -+#undef TARGET_SCALAR_MODE_SUPPORTED_P -+#define TARGET_SCALAR_MODE_SUPPORTED_P arm_scalar_mode_supported_p -+ -+#undef TARGET_VECTOR_MIN_ALIGNMENT -+#define TARGET_VECTOR_MIN_ALIGNMENT arm_vector_min_alignment -+ -+#undef TARGET_VECTOR_ALWAYS_MISALIGN -+#define TARGET_VECTOR_ALWAYS_MISALIGN arm_vector_always_misalign -+ - struct gcc_target targetm = TARGET_INITIALIZER; +--- a/gcc/config.gcc ++++ b/gcc/config.gcc +@@ -1088,7 +1088,7 @@ i[34567]86-*-linux* | i[34567]86-*-kfree + tmake_file="${tmake_file} i386/t-linux64" + need_64bit_hwint=yes + case X"${with_cpu}" in +- Xgeneric|Xcore2|Xnocona|Xx86-64|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx) ++ Xgeneric|Xatom|Xcore2|Xnocona|Xx86-64|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx) + ;; + X) + if test x$with_cpu_64 = x; then +@@ -1097,7 +1097,7 @@ i[34567]86-*-linux* | i[34567]86-*-kfree + ;; + *) + echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2 +- echo "generic core2 nocona x86-64 amdfam10 barcelona k8 opteron athlon64 athlon-fx" 1>&2 ++ echo "generic atom core2 nocona x86-64 amdfam10 barcelona k8 opteron athlon64 athlon-fx" 1>&2 + exit 1 + ;; + esac +@@ -1202,7 +1202,7 @@ i[34567]86-*-solaris2*) + # libgcc/configure.ac instead. + need_64bit_hwint=yes + case X"${with_cpu}" in +- Xgeneric|Xcore2|Xnocona|Xx86-64|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx) ++ Xgeneric|Xatom|Xcore2|Xnocona|Xx86-64|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx) + ;; + X) + if test x$with_cpu_64 = x; then +@@ -1211,7 +1211,7 @@ i[34567]86-*-solaris2*) + ;; + *) + echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2 +- echo "generic core2 nocona x86-64 amdfam10 barcelona k8 opteron athlon64 athlon-fx" 1>&2 ++ echo "generic atom core2 nocona x86-64 amdfam10 barcelona k8 opteron athlon64 athlon-fx" 1>&2 + exit 1 + ;; + esac +@@ -1573,6 +1573,7 @@ mips64*-*-linux* | mipsisa64*-*-linux*) + tm_defines="${tm_defines} MIPS_ISA_DEFAULT=65" + ;; + esac ++ tmake_file="$tmake_file mips/t-crtfm" + gnu_ld=yes + gas=yes + test x$with_llsc != x || with_llsc=yes +@@ -1803,6 +1804,10 @@ powerpc-*-elf*) + tm_file="${tm_file} dbxelf.h elfos.h usegas.h svr4.h freebsd-spec.h rs6000/sysv4.h" + extra_options="${extra_options} rs6000/sysv4.opt" + tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcgas rs6000/t-ppccomm" ++ if test x$enable_powerpc_e500mc_elf = xyes; then ++ tm_file="${tm_file} rs6000/e500mc.h" ++ tmake_file="${tmake_file} rs6000/t-ppc-e500mc" ++ fi + ;; + powerpc-*-eabialtivec*) + tm_file="${tm_file} dbxelf.h elfos.h svr4.h freebsd-spec.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabialtivec.h" +@@ -2016,9 +2021,14 @@ sh-*-symbianelf* | sh[12346l]*-*-symbian + *) with_endian=big,little ;; + esac + fi ++ # TM_ENDIAN_CONFIG is used by t-sh to determine multilibs. ++ # First word : the default endian. ++ # Second word: the secondary endian (optional). + case ${with_endian} in +- big|little) tmake_file="${tmake_file} sh/t-1e" ;; +- big,little|little,big) ;; ++ big) TM_ENDIAN_CONFIG=mb ;; ++ little) TM_ENDIAN_CONFIG=ml ;; ++ big,little) TM_ENDIAN_CONFIG="mb ml" ;; ++ little,big) TM_ENDIAN_CONFIG="ml mb" ;; + *) echo "with_endian=${with_endian} not supported."; exit 1 ;; + esac + case ${with_endian} in +@@ -2125,7 +2135,7 @@ sh-*-symbianelf* | sh[12346l]*-*-symbian + *) echo "with_cpu=$with_cpu not supported"; exit 1 ;; + esac + sh_multilibs=${with_multilib_list} +- if test x${sh_multilibs} = x ; then ++ if test "$sh_multilibs" = "default" ; then + case ${target} in + sh64-superh-linux* | \ + sh[1234]*) sh_multilibs=${sh_cpu_target} ;; +@@ -2141,25 +2151,32 @@ sh-*-symbianelf* | sh[12346l]*-*-symbian + fi + target_cpu_default=SELECT_`echo ${sh_cpu_default}|tr abcdefghijklmnopqrstuvwxyz- ABCDEFGHIJKLMNOPQRSTUVWXYZ_` + tm_defines=${tm_defines}' SH_MULTILIB_CPU_DEFAULT=\"'`echo $sh_cpu_default|sed s/sh/m/`'\"' +- sh_multilibs=`echo $sh_multilibs,$sh_cpu_default | sed -e 's/[ ,/][ ,]*/ /g' -e 's/ $//' -e 's/^m/sh/' -e 's/ m/ sh/g' | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ_ abcdefghijklmnopqrstuvwxyz-` ++ tm_defines="$tm_defines SUPPORT_`echo $sh_cpu_default | sed 's/^m/sh/' | tr abcdefghijklmnopqrstuvwxyz- ABCDEFGHIJKLMNOPQRSTUVWXYZ_`=1" ++ sh_multilibs=`echo $sh_multilibs | sed -e 's/,/ /g' -e 's/^sh/m/i' -e 's/ sh/ m/gi' | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ_ abcdefghijklmnopqrstuvwxyz-` + for sh_multilib in ${sh_multilibs}; do + case ${sh_multilib} in +- sh1 | sh2 | sh2e | sh3 | sh3e | \ +- sh4 | sh4-single | sh4-single-only | sh4-nofpu | sh4-300 |\ +- sh4a | sh4a-single | sh4a-single-only | sh4a-nofpu | sh4al | \ +- sh2a | sh2a-single | sh2a-single-only | sh2a-nofpu | \ +- sh5-64media | sh5-64media-nofpu | \ +- sh5-32media | sh5-32media-nofpu | \ +- sh5-compact | sh5-compact-nofpu) +- tmake_file="${tmake_file} sh/t-mlib-${sh_multilib}" +- tm_defines="$tm_defines SUPPORT_`echo $sh_multilib|tr abcdefghijklmnopqrstuvwxyz- ABCDEFGHIJKLMNOPQRSTUVWXYZ_`=1" +- ;; ++ m1 | m2 | m2e | m3 | m3e | \ ++ m4 | m4-single | m4-single-only | m4-nofpu | m4-300 |\ ++ m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al | \ ++ m2a | m2a-single | m2a-single-only | m2a-nofpu | \ ++ m5-64media | m5-64media-nofpu | \ ++ m5-32media | m5-32media-nofpu | \ ++ m5-compact | m5-compact-nofpu) ++ # TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition ++ # It is passed to MULTIILIB_OPTIONS verbatim. ++ TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}" ++ tm_defines="$tm_defines SUPPORT_`echo $sh_multilib | sed 's/^m/sh/' | tr abcdefghijklmnopqrstuvwxyz- ABCDEFGHIJKLMNOPQRSTUVWXYZ_`=1" ++ ;; ++ \!*) # TM_MULTILIB_EXCEPTIONS_CONFIG is used by t-sh ++ # It is passed the MULTILIB_EXCEPTIONS verbatim. ++ TM_MULTILIB_EXCEPTIONS_CONFIG="${TM_MULTILIB_EXCEPTIONS_CONFIG} `echo $sh_multilib | sed 's/^!//'`" ;; + *) + echo "with_multilib_list=${sh_multilib} not supported." + exit 1 + ;; + esac + done ++ TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'` + if test x${enable_incomplete_targets} = xyes ; then + tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SH5_32MEDIA=1 SUPPORT_SH5_32MEDIA_NOFPU=1 SUPPORT_SH5_64MEDIA=1 SUPPORT_SH5_64MEDIA_NOFPU=1" + fi +@@ -2427,6 +2444,8 @@ i[34567]86-*-linux* | x86_64-*-linux*) + i[34567]86-*-* | x86_64-*-*) + tmake_file="${tmake_file} i386/t-gmm_malloc i386/t-i386" + ;; ++powerpc*-*-* | rs6000-*-*) ++ tm_file="${tm_file} rs6000/option-defaults.h" + esac + + # Support for --with-cpu and related options (and a few unrelated options, +@@ -2653,8 +2672,8 @@ case "${target}" in + | armv[23456] | armv2a | armv3m | armv4t | armv5t \ + | armv5te | armv6j |armv6k | armv6z | armv6zk | armv6-m \ + | armv7 | armv7-a | armv7-r | armv7-m \ +- | iwmmxt | ep9312) +- # OK ++ | iwmmxt | ep9312 | marvell-f ) ++ # OK + ;; + *) + echo "Unknown arch used in --with-arch=$with_arch" 1>&2 +@@ -2675,7 +2694,10 @@ case "${target}" in + + case "$with_fpu" in + "" \ +- | fpa | fpe2 | fpe3 | maverick | vfp | vfp3 | vfpv3 | vfpv3-d16 | neon ) ++ | fpa | fpe2 | fpe3 | maverick \ ++ | vfp | vfp3 | vfpv3 | vfpv3-fp16 | vfpv3-d16 \ ++ | vfpv3-d16-fp16 | vfpv4 | vfpv4-d16 | fpv4-sp-d16 \ ++ | neon | neon-fp16 | neon-vfpv4 ) + # OK + ;; + *) +@@ -2812,7 +2834,7 @@ case "${target}" in + esac + # OK + ;; +- "" | amdfam10 | barcelona | k8 | opteron | athlon64 | athlon-fx | nocona | core2 | generic) ++ "" | amdfam10 | barcelona | k8 | opteron | athlon64 | athlon-fx | nocona | core2 | atom | generic) + # OK + ;; + *) +@@ -2824,7 +2846,7 @@ case "${target}" in + ;; + + mips*-*-*) +- supported_defaults="abi arch float tune divide llsc mips-plt" ++ supported_defaults="abi arch arch_32 arch_64 float tune tune_32 tune_64 divide llsc mips-plt" + + case ${with_float} in + "" | soft | hard) +@@ -2889,12 +2911,20 @@ case "${target}" in + ;; + + powerpc*-*-* | rs6000-*-*) +- supported_defaults="cpu float tune" ++ supported_defaults="cpu cpu_32 cpu_64 float tune tune_32 tune_64" + +- for which in cpu tune; do ++ for which in cpu cpu_32 cpu_64 tune tune_32 tune_64; do + eval "val=\$with_$which" + case ${val} in + default32 | default64) ++ case $which in ++ cpu | tune) ++ ;; ++ *) ++ echo "$val only valid for --with-cpu and --with-tune." 1>&2 ++ exit 1 ++ ;; ++ esac + with_which="with_$which" + eval $with_which= + ;; +--- a/gcc/config.in ++++ b/gcc/config.in +@@ -108,6 +108,12 @@ + #endif + + ++/* Define to warn for use of native system header directories */ ++#ifndef USED_FOR_TARGET ++#undef ENABLE_POISON_SYSTEM_DIRECTORIES ++#endif ++ ++ + /* Define if you want all operations on RTL (the basic data structure of the + optimizer and back end) to be checked for dynamic type safety at runtime. + This is quite expensive. */ +@@ -821,6 +827,13 @@ + #endif + + ++/* Define if your assembler supports specifying the alignment of objects ++ allocated using the GAS .comm command. */ ++#ifndef USED_FOR_TARGET ++#undef HAVE_GAS_ALIGNED_COMM ++#endif ++ ++ + /* Define if your assembler supports .balign and .p2align. */ + #ifndef USED_FOR_TARGET + #undef HAVE_GAS_BALIGN_AND_P2ALIGN +--- a/gcc/config/arm/arm-cores.def ++++ b/gcc/config/arm/arm-cores.def +@@ -104,6 +104,7 @@ ARM_CORE("arm1022e", arm1022e, 5TE, + ARM_CORE("xscale", xscale, 5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE, xscale) + ARM_CORE("iwmmxt", iwmmxt, 5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT, xscale) + ARM_CORE("iwmmxt2", iwmmxt2, 5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT, xscale) ++ARM_CORE("marvell-f", marvell_f, 5TE, FL_LDSCHED | FL_VFPV2 | FL_MARVELL_F, 9e) + + /* V5TEJ Architecture Processors */ + ARM_CORE("arm926ej-s", arm926ejs, 5TEJ, FL_LDSCHED, 9e) +@@ -117,9 +118,13 @@ ARM_CORE("arm1176jzf-s", arm1176jzfs, 6 + ARM_CORE("mpcorenovfp", mpcorenovfp, 6K, FL_LDSCHED, 9e) + ARM_CORE("mpcore", mpcore, 6K, FL_LDSCHED | FL_VFPV2, 9e) + ARM_CORE("arm1156t2-s", arm1156t2s, 6T2, FL_LDSCHED, 9e) ++ ++/* V7 Architecture Processors */ ++ARM_CORE("cortex-a5", cortexa5, 7A, FL_LDSCHED, 9e) + ARM_CORE("cortex-a8", cortexa8, 7A, FL_LDSCHED, 9e) + ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, 9e) + ARM_CORE("cortex-r4", cortexr4, 7R, FL_LDSCHED, 9e) + ARM_CORE("cortex-r4f", cortexr4f, 7R, FL_LDSCHED, 9e) + ARM_CORE("cortex-m3", cortexm3, 7M, FL_LDSCHED, 9e) + ARM_CORE("cortex-m1", cortexm1, 6M, FL_LDSCHED, 9e) ++ARM_CORE("cortex-m0", cortexm0, 6M, FL_LDSCHED, 9e) +--- a/gcc/config/arm/arm-modes.def ++++ b/gcc/config/arm/arm-modes.def +@@ -25,6 +25,11 @@ + FIXME What format is this? */ + FLOAT_MODE (XF, 12, 0); + ++/* Half-precision floating point */ ++FLOAT_MODE (HF, 2, 0); ++ADJUST_FLOAT_FORMAT (HF, ((arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) ++ ? &arm_half_format : &ieee_half_format)); ++ + /* CCFPEmode should be used with floating inequalities, + CCFPmode should be used with floating equalities. + CC_NOOVmode should be used with SImode integer equalities. +@@ -62,6 +67,4 @@ VECTOR_MODES (FLOAT, 16); /* V + INT_MODE (EI, 24); + INT_MODE (OI, 32); + INT_MODE (CI, 48); +-/* ??? This should actually have 512 bits but the precision only has 9 +- bits. */ +-FRACTIONAL_INT_MODE (XI, 511, 64); ++INT_MODE (XI, 64); +--- a/gcc/config/arm/arm-protos.h ++++ b/gcc/config/arm/arm-protos.h +@@ -88,7 +88,7 @@ extern bool arm_cannot_force_const_mem ( + + extern int cirrus_memory_offset (rtx); + extern int arm_coproc_mem_operand (rtx, bool); +-extern int neon_vector_mem_operand (rtx, bool); ++extern int neon_vector_mem_operand (rtx, int); + extern int neon_struct_mem_operand (rtx); + extern int arm_no_early_store_addr_dep (rtx, rtx); + extern int arm_no_early_alu_shift_dep (rtx, rtx); +@@ -144,6 +144,7 @@ extern void arm_final_prescan_insn (rtx) + extern int arm_debugger_arg_offset (int, rtx); + extern bool arm_is_long_call_p (tree); + extern int arm_emit_vector_const (FILE *, rtx); ++extern void arm_emit_fp16_const (rtx c); + extern const char * arm_output_load_gr (rtx *); + extern const char *vfp_output_fstmd (rtx *); + extern void arm_set_return_address (rtx, rtx); +@@ -154,13 +155,15 @@ extern bool arm_output_addr_const_extra + + #if defined TREE_CODE + extern rtx arm_function_arg (CUMULATIVE_ARGS *, enum machine_mode, tree, int); ++extern void arm_function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode, ++ tree, bool); + extern void arm_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree); + extern bool arm_pad_arg_upward (enum machine_mode, const_tree); + extern bool arm_pad_reg_upward (enum machine_mode, tree, int); + extern bool arm_needs_doubleword_align (enum machine_mode, tree); +-extern rtx arm_function_value(const_tree, const_tree); + #endif + extern int arm_apply_result_size (void); ++extern rtx aapcs_libcall_value (enum machine_mode); + + #endif /* RTX_CODE */ + +--- a/gcc/config/arm/arm-tune.md ++++ b/gcc/config/arm/arm-tune.md +@@ -1,5 +1,5 @@ + ;; -*- buffer-read-only: t -*- + ;; Generated automatically by gentune.sh from arm-cores.def + (define_attr "tune" +- "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,cortexa8,cortexa9,cortexr4,cortexr4f,cortexm3,cortexm1" ++ "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,marvell_f,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,cortexa5,cortexa8,cortexa9,cortexr4,cortexr4f,cortexm3,cortexm1,cortexm0" + (const (symbol_ref "arm_tune"))) +--- a/gcc/config/arm/arm.c ++++ b/gcc/config/arm/arm.c +@@ -43,6 +43,7 @@ + #include "optabs.h" + #include "toplev.h" + #include "recog.h" ++#include "cgraph.h" + #include "ggc.h" + #include "except.h" + #include "c-pragma.h" +@@ -54,6 +55,8 @@ + #include "langhooks.h" + #include "df.h" + #include "libfuncs.h" ++#include "intl.h" ++#include "params.h" + + /* Forward definitions of types. */ + typedef struct minipool_node Mnode; +@@ -111,6 +114,7 @@ static unsigned long arm_compute_save_re + static unsigned long arm_isr_value (tree); + static unsigned long arm_compute_func_type (void); + static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *); ++static tree arm_handle_pcs_attribute (tree *, tree, tree, int, bool *); + static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *); + #if TARGET_DLLIMPORT_DECL_ATTRIBUTES + static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *); +@@ -124,6 +128,10 @@ static int arm_adjust_cost (rtx, rtx, rt + static int count_insns_for_constant (HOST_WIDE_INT, int); + static int arm_get_strip_length (int); + static bool arm_function_ok_for_sibcall (tree, tree); ++static bool arm_return_in_memory (const_tree, const_tree); ++static rtx arm_function_value (const_tree, const_tree, bool); ++static rtx arm_libcall_value (enum machine_mode, rtx); ++ + static void arm_internal_label (FILE *, const char *, unsigned long); + static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, + tree); +@@ -149,6 +157,9 @@ static void emit_constant_insn (rtx cond + static rtx emit_set_insn (rtx, rtx); + static int arm_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode, + tree, bool); ++static rtx aapcs_allocate_return_reg (enum machine_mode, const_tree, ++ const_tree); ++static int aapcs_select_return_coproc (const_tree, const_tree); + + #ifdef OBJECT_FORMAT_ELF + static void arm_elf_asm_constructor (rtx, int) ATTRIBUTE_UNUSED; +@@ -176,6 +187,7 @@ static void arm_unwind_emit (FILE *, rtx + static bool arm_output_ttype (rtx); + #endif + static void arm_dwarf_handle_frame_unspec (const char *, rtx, int); ++static rtx arm_dwarf_register_span(rtx); + + static tree arm_cxx_guard_type (void); + static bool arm_cxx_guard_mask_bit (void); +@@ -198,6 +210,15 @@ static bool arm_tls_symbol_p (rtx x); + static int arm_issue_rate (void); + static void arm_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED; + static bool arm_allocate_stack_slots_for_args (void); ++static bool arm_warn_func_result (void); ++static int arm_multipass_dfa_lookahead (void); ++static const char *arm_invalid_parameter_type (const_tree t); ++static const char *arm_invalid_return_type (const_tree t); ++static tree arm_promoted_type (const_tree t); ++static tree arm_convert_to_type (tree type, tree expr); ++static bool arm_scalar_mode_supported_p (enum machine_mode); ++static int arm_vector_min_alignment (const_tree type); ++static bool arm_vector_always_misalign(const_tree); + + + /* Initialize the GCC target structure. */ +@@ -257,6 +278,12 @@ static bool arm_allocate_stack_slots_for + #undef TARGET_FUNCTION_OK_FOR_SIBCALL + #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall + ++#undef TARGET_FUNCTION_VALUE ++#define TARGET_FUNCTION_VALUE arm_function_value ++ ++#undef TARGET_LIBCALL_VALUE ++#define TARGET_LIBCALL_VALUE arm_libcall_value ++ + #undef TARGET_ASM_OUTPUT_MI_THUNK + #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk + #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK +@@ -300,6 +327,9 @@ static bool arm_allocate_stack_slots_for + #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS + #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS arm_allocate_stack_slots_for_args + ++#undef TARGET_WARN_FUNC_RESULT ++#define TARGET_WARN_FUNC_RESULT arm_warn_func_result ++ + #undef TARGET_DEFAULT_SHORT_ENUMS + #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums + +@@ -354,6 +384,9 @@ static bool arm_allocate_stack_slots_for + #undef TARGET_ASM_TTYPE + #define TARGET_ASM_TTYPE arm_output_ttype + ++#undef TARGET_CXX_TTYPE_REF_ENCODE ++#define TARGET_CXX_TTYPE_REF_ENCODE hook_cxx_ttype_ref_in_bit0 ++ + #undef TARGET_ARM_EABI_UNWINDER + #define TARGET_ARM_EABI_UNWINDER true + #endif /* TARGET_UNWIND_INFO */ +@@ -361,6 +394,9 @@ static bool arm_allocate_stack_slots_for + #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC + #define TARGET_DWARF_HANDLE_FRAME_UNSPEC arm_dwarf_handle_frame_unspec + ++#undef TARGET_DWARF_REGISTER_SPAN ++#define TARGET_DWARF_REGISTER_SPAN arm_dwarf_register_span ++ + #undef TARGET_CANNOT_COPY_INSN_P + #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p + +@@ -399,6 +435,30 @@ static bool arm_allocate_stack_slots_for + #define TARGET_ASM_OUTPUT_DWARF_DTPREL arm_output_dwarf_dtprel + #endif + ++#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD ++#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD arm_multipass_dfa_lookahead ++ ++#undef TARGET_INVALID_PARAMETER_TYPE ++#define TARGET_INVALID_PARAMETER_TYPE arm_invalid_parameter_type ++ ++#undef TARGET_INVALID_RETURN_TYPE ++#define TARGET_INVALID_RETURN_TYPE arm_invalid_return_type ++ ++#undef TARGET_PROMOTED_TYPE ++#define TARGET_PROMOTED_TYPE arm_promoted_type ++ ++#undef TARGET_CONVERT_TO_TYPE ++#define TARGET_CONVERT_TO_TYPE arm_convert_to_type ++ ++#undef TARGET_SCALAR_MODE_SUPPORTED_P ++#define TARGET_SCALAR_MODE_SUPPORTED_P arm_scalar_mode_supported_p ++ ++#undef TARGET_VECTOR_MIN_ALIGNMENT ++#define TARGET_VECTOR_MIN_ALIGNMENT arm_vector_min_alignment ++ ++#undef TARGET_VECTOR_ALWAYS_MISALIGN ++#define TARGET_VECTOR_ALWAYS_MISALIGN arm_vector_always_misalign ++ + struct gcc_target targetm = TARGET_INITIALIZER; /* Obstack for minipool constant handling. */ -@@ -423,18 +483,18 @@ +@@ -424,18 +484,18 @@ enum processor_type arm_tune = arm_none; /* The default processor used if not overridden by commandline. */ static enum processor_type arm_default_cpu = arm_none; @@ -1061,7 +1669,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c /* Which ABI to use. */ enum arm_abi_type arm_abi; -@@ -473,9 +533,19 @@ +@@ -474,9 +534,19 @@ static int thumb_call_reg_needed; #define FL_DIV (1 << 18) /* Hardware divide. */ #define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */ #define FL_NEON (1 << 20) /* Neon instructions. */ @@ -1081,7 +1689,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c #define FL_FOR_ARCH2 FL_NOTM #define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32) #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M) -@@ -497,6 +567,7 @@ +@@ -498,6 +568,7 @@ static int thumb_call_reg_needed; #define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM) #define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_DIV) #define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_DIV) @@ -1089,7 +1697,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c /* The bits in this mask specify which instructions we are allowed to generate. */ -@@ -533,6 +604,9 @@ +@@ -534,6 +605,9 @@ int arm_arch6k = 0; /* Nonzero if instructions not present in the 'M' profile can be used. */ int arm_arch_notm = 0; @@ -1099,7 +1707,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c /* Nonzero if this chip can benefit from load scheduling. */ int arm_ld_sched = 0; -@@ -551,6 +625,9 @@ +@@ -552,6 +626,9 @@ int arm_arch_xscale = 0; /* Nonzero if tuning for XScale */ int arm_tune_xscale = 0; @@ -1109,7 +1717,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c /* Nonzero if we want to tune for stores that access the write-buffer. This typically means an ARM6 or ARM7 with MMU or MPU. */ int arm_tune_wbuf = 0; -@@ -561,6 +638,9 @@ +@@ -562,6 +639,9 @@ int arm_tune_cortex_a9 = 0; /* Nonzero if generating Thumb instructions. */ int thumb_code = 0; @@ -1119,7 +1727,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c /* Nonzero if we should define __THUMB_INTERWORK__ in the preprocessor. XXX This is a bit of a hack, it's intended to help work around -@@ -593,6 +673,8 @@ +@@ -594,6 +674,8 @@ static int after_arm_reorg = 0; /* The maximum number of insns to be used when loading a constant. */ static int arm_constant_limit = 3; @@ -1128,7 +1736,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c /* For an explanation of these variables, see final_prescan_insn below. */ int arm_ccfsm_state; /* arm_current_cc is also used for Thumb-2 cond_exec blocks. */ -@@ -673,9 +755,11 @@ +@@ -674,9 +756,11 @@ static const struct processors all_archi {"armv7-a", cortexa8, "7A", FL_CO_PROC | FL_FOR_ARCH7A, NULL}, {"armv7-r", cortexr4, "7R", FL_CO_PROC | FL_FOR_ARCH7R, NULL}, {"armv7-m", cortexm3, "7M", FL_CO_PROC | FL_FOR_ARCH7M, NULL}, @@ -1140,7 +1748,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c {NULL, arm_none, NULL, 0 , NULL} }; -@@ -705,49 +789,34 @@ +@@ -706,49 +790,34 @@ static struct arm_cpu_select arm_select[ /* The name of the preprocessor macro to define for this architecture. */ @@ -1212,7 +1820,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c struct float_abi { const char * name; -@@ -765,6 +834,23 @@ +@@ -766,6 +835,23 @@ static const struct float_abi all_float_ }; @@ -1236,15 +1844,15 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c struct abi_name { const char *name; -@@ -922,6 +1008,44 @@ - set_optab_libfunc (umod_optab, DImode, NULL); +@@ -924,6 +1010,45 @@ arm_init_libfuncs (void) set_optab_libfunc (smod_optab, SImode, NULL); set_optab_libfunc (umod_optab, SImode, NULL); + + + /* Half-precision float operations. The compiler handles all operations + with NULL libfuncs by converting the SFmode. */ + switch (arm_fp16_format) -+ { ++ { + case ARM_FP16_FORMAT_IEEE: + case ARM_FP16_FORMAT_ALTERNATIVE: + @@ -1257,7 +1865,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c + (arm_fp16_format == ARM_FP16_FORMAT_IEEE + ? "__gnu_h2f_ieee" + : "__gnu_h2f_alternative")); -+ ++ + /* Arithmetic. */ + set_optab_libfunc (add_optab, HFmode, NULL); + set_optab_libfunc (sdiv_optab, HFmode, NULL); @@ -1277,11 +1885,12 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c + + default: + break; -+ } ++ } ++ + if (TARGET_AAPCS_BASED) + synchronize_libfunc = init_one_libfunc ("__sync_synchronize"); } - - /* On AAPCS systems, this is the "struct __va_list". */ -@@ -1135,6 +1259,7 @@ +@@ -1139,6 +1264,7 @@ void arm_override_options (void) { unsigned i; @@ -1289,7 +1898,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c enum processor_type target_arch_cpu = arm_none; enum processor_type selected_cpu = arm_none; -@@ -1152,7 +1277,11 @@ +@@ -1156,7 +1282,11 @@ arm_override_options (void) { /* Set the architecture define. */ if (i != ARM_OPT_SET_TUNE) @@ -1302,7 +1911,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c /* Determine the processor core for which we should tune code-generation. */ -@@ -1178,8 +1307,8 @@ +@@ -1182,8 +1312,8 @@ arm_override_options (void) make sure that they are compatible. We only generate a warning though, and we prefer the CPU over the architecture. */ @@ -1313,7 +1922,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c ptr->string); insn_flags = sel->flags; -@@ -1279,7 +1408,11 @@ +@@ -1283,7 +1413,11 @@ arm_override_options (void) insn_flags = sel->flags; } @@ -1326,7 +1935,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c arm_default_cpu = (enum processor_type) (sel - all_cores); if (arm_tune == arm_none) arm_tune = arm_default_cpu; -@@ -1289,8 +1422,35 @@ +@@ -1293,8 +1427,35 @@ arm_override_options (void) chosen. */ gcc_assert (arm_tune != arm_none); @@ -1362,7 +1971,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c if (target_abi_name) { for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++) -@@ -1383,6 +1543,7 @@ +@@ -1387,6 +1548,7 @@ arm_override_options (void) arm_arch6 = (insn_flags & FL_ARCH6) != 0; arm_arch6k = (insn_flags & FL_ARCH6K) != 0; arm_arch_notm = (insn_flags & FL_NOTM) != 0; @@ -1370,7 +1979,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0; arm_arch_xscale = (insn_flags & FL_XSCALE) != 0; arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0; -@@ -1390,12 +1551,25 @@ +@@ -1394,12 +1556,25 @@ arm_override_options (void) arm_ld_sched = (tune_flags & FL_LDSCHED) != 0; arm_tune_strongarm = (tune_flags & FL_STRONG) != 0; thumb_code = (TARGET_ARM == 0); @@ -1397,7 +2006,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c /* If we are not using the default (ARM mode) section anchor offset ranges, then set the correct ranges now. */ if (TARGET_THUMB1) -@@ -1434,7 +1608,6 @@ +@@ -1438,7 +1613,6 @@ arm_override_options (void) if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT) error ("iwmmxt abi requires an iwmmxt capable cpu"); @@ -1405,7 +2014,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c if (target_fpu_name == NULL && target_fpe_name != NULL) { if (streq (target_fpe_name, "2")) -@@ -1445,46 +1618,52 @@ +@@ -1449,46 +1623,52 @@ arm_override_options (void) error ("invalid floating point emulation option: -mfpe=%s", target_fpe_name); } @@ -1491,7 +2100,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c } if (target_float_abi_name != NULL) -@@ -1505,9 +1684,6 @@ +@@ -1509,9 +1689,6 @@ arm_override_options (void) else arm_float_abi = TARGET_DEFAULT_FLOAT_ABI; @@ -1501,7 +2110,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c /* FPA and iWMMXt are incompatible because the insn encodings overlap. VFP and iWMMXt can theoretically coexist, but it's unlikely such silicon will ever exist. GCC makes no attempt to support this combination. */ -@@ -1518,15 +1694,40 @@ +@@ -1522,15 +1699,40 @@ arm_override_options (void) if (TARGET_THUMB2 && TARGET_IWMMXT) sorry ("Thumb-2 iWMMXt"); @@ -1545,7 +2154,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c && (tune_flags & FL_MODE32) == 0) flag_schedule_insns = flag_schedule_insns_after_reload = 0; -@@ -1616,8 +1817,7 @@ +@@ -1620,8 +1822,7 @@ arm_override_options (void) fix_cm3_ldrd = 0; } @@ -1555,7 +2164,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c { /* Don't warn since it's on by default in -O2. */ flag_schedule_insns = 0; -@@ -1653,6 +1853,36 @@ +@@ -1664,6 +1865,36 @@ arm_override_options (void) /* Register global variables with the garbage collector. */ arm_add_gc_roots (); @@ -1592,7 +2201,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c } static void -@@ -1782,6 +2012,14 @@ +@@ -1793,6 +2024,14 @@ arm_allocate_stack_slots_for_args (void) return !IS_NAKED (arm_current_func_type ()); } @@ -1607,7 +2216,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c /* Return 1 if it is possible to return using a single instruction. If SIBLING is non-null, this is a test for a return before a sibling -@@ -2873,14 +3111,19 @@ +@@ -2884,14 +3123,19 @@ arm_canonicalize_comparison (enum rtx_co /* Define how to find the value returned by a function. */ @@ -1629,7 +2238,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c /* Promote integer types. */ if (INTEGRAL_TYPE_P (type)) PROMOTE_FUNCTION_MODE (mode, unsignedp, type); -@@ -2897,7 +3140,36 @@ +@@ -2908,7 +3152,36 @@ arm_function_value(const_tree type, cons } } @@ -1667,7 +2276,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c } /* Determine the amount of memory needed to store the possible return -@@ -2907,10 +3179,12 @@ +@@ -2918,10 +3191,12 @@ arm_apply_result_size (void) { int size = 16; @@ -1681,7 +2290,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c if (TARGET_FPA) size += 12; if (TARGET_MAVERICK) -@@ -2923,27 +3197,56 @@ +@@ -2934,27 +3209,56 @@ arm_apply_result_size (void) return size; } @@ -1750,7 +2359,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c if (arm_abi != ARM_ABI_APCS) { -@@ -2960,7 +3263,7 @@ +@@ -2971,7 +3275,7 @@ arm_return_in_memory (const_tree type, c the aggregate is either huge or of variable size, and in either case we will want to return it via memory and not in a register. */ if (size < 0 || size > UNITS_PER_WORD) @@ -1759,7 +2368,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c if (TREE_CODE (type) == RECORD_TYPE) { -@@ -2980,18 +3283,18 @@ +@@ -2991,18 +3295,18 @@ arm_return_in_memory (const_tree type, c continue; if (field == NULL) @@ -1781,7 +2390,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c /* Now check the remaining fields, if any. Only bitfields are allowed, since they are not addressable. */ -@@ -3003,10 +3306,10 @@ +@@ -3014,10 +3318,10 @@ arm_return_in_memory (const_tree type, c continue; if (!DECL_BIT_FIELD_TYPE (field)) @@ -1794,7 +2403,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c } if (TREE_CODE (type) == UNION_TYPE) -@@ -3023,18 +3326,18 @@ +@@ -3034,18 +3338,18 @@ arm_return_in_memory (const_tree type, c continue; if (FLOAT_TYPE_P (TREE_TYPE (field))) @@ -1817,7 +2426,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c } /* Indicate whether or not words of a double are in big-endian order. */ -@@ -3059,14 +3362,780 @@ +@@ -3070,14 +3374,780 @@ arm_float_words_big_endian (void) return 1; } @@ -2599,7 +3208,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c /* On the ARM, the offset starts at 0. */ pcum->nregs = 0; pcum->iwmmxt_nregs = 0; -@@ -3120,6 +4189,17 @@ +@@ -3131,6 +4201,17 @@ arm_function_arg (CUMULATIVE_ARGS *pcum, { int nregs; @@ -2617,7 +3226,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c /* Varargs vectors are treated the same as long long. named_count avoids having to change the way arm handles 'named' */ if (TARGET_IWMMXT_ABI -@@ -3161,10 +4241,16 @@ +@@ -3172,10 +4253,16 @@ arm_function_arg (CUMULATIVE_ARGS *pcum, static int arm_arg_partial_bytes (CUMULATIVE_ARGS *pcum, enum machine_mode mode, @@ -2635,7 +3244,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c if (TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (mode)) return 0; -@@ -3173,7 +4259,40 @@ +@@ -3184,7 +4271,40 @@ arm_arg_partial_bytes (CUMULATIVE_ARGS * && pcum->can_split) return (NUM_ARG_REGS - nregs) * UNITS_PER_WORD; @@ -2677,7 +3286,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c } /* Variable sized types are passed by reference. This is a GCC -@@ -3226,6 +4345,8 @@ +@@ -3237,6 +4357,8 @@ const struct attribute_spec arm_attribut /* Whereas these functions are always known to reside within the 26 bit addressing range. */ { "short_call", 0, 0, false, true, true, NULL }, @@ -2686,7 +3295,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c /* Interrupt Service Routines have special prologue and epilogue requirements. */ { "isr", 0, 1, false, false, false, arm_handle_isr_attribute }, { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute }, -@@ -3328,6 +4449,21 @@ +@@ -3339,6 +4461,21 @@ arm_handle_isr_attribute (tree *node, tr return NULL_TREE; } @@ -2708,7 +3317,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c #if TARGET_DLLIMPORT_DECL_ATTRIBUTES /* Handle the "notshared" attribute. This attribute is another way of requesting hidden visibility. ARM's compiler supports -@@ -3489,7 +4625,7 @@ +@@ -3500,7 +4637,7 @@ arm_is_long_call_p (tree decl) /* Return nonzero if it is ok to make a tail-call to DECL. */ static bool @@ -2717,7 +3326,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c { unsigned long func_type; -@@ -3522,6 +4658,21 @@ +@@ -3533,6 +4670,21 @@ arm_function_ok_for_sibcall (tree decl, if (IS_INTERRUPT (func_type)) return false; @@ -2739,7 +3348,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c /* Never tailcall if function may be called with a misaligned SP. */ if (IS_STACKALIGN (func_type)) return false; -@@ -4120,6 +5271,7 @@ +@@ -4131,6 +5283,7 @@ arm_legitimate_index_p (enum machine_mod if (GET_MODE_SIZE (mode) <= 4 && ! (arm_arch4 && (mode == HImode @@ -2747,7 +3356,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c || (mode == QImode && outer == SIGN_EXTEND)))) { if (code == MULT) -@@ -4148,13 +5300,15 @@ +@@ -4159,13 +5312,15 @@ arm_legitimate_index_p (enum machine_mod load. */ if (arm_arch4) { @@ -2765,7 +3374,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c return (code == CONST_INT && INTVAL (index) < range -@@ -4325,7 +5479,8 @@ +@@ -4336,7 +5491,8 @@ thumb1_legitimate_address_p (enum machin return 1; /* This is PC relative data after arm_reorg runs. */ @@ -2775,7 +3384,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c && (GET_CODE (x) == LABEL_REF || (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS -@@ -5024,7 +6179,7 @@ +@@ -5035,7 +6191,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code ou case UMOD: if (TARGET_HARD_FLOAT && mode == SFmode) *total = COSTS_N_INSNS (2); @@ -2784,7 +3393,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c *total = COSTS_N_INSNS (4); else *total = COSTS_N_INSNS (20); -@@ -5063,23 +6218,6 @@ +@@ -5074,23 +6230,6 @@ arm_rtx_costs_1 (rtx x, enum rtx_code ou return true; case MINUS: @@ -2808,7 +3417,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c if (mode == DImode) { *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); -@@ -5102,7 +6240,9 @@ +@@ -5113,7 +6252,9 @@ arm_rtx_costs_1 (rtx x, enum rtx_code ou if (GET_MODE_CLASS (mode) == MODE_FLOAT) { @@ -2819,7 +3428,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c { *total = COSTS_N_INSNS (1); if (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE -@@ -5143,6 +6283,17 @@ +@@ -5154,6 +6295,17 @@ arm_rtx_costs_1 (rtx x, enum rtx_code ou return true; } @@ -2837,7 +3446,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c if (subcode == MULT && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT && ((INTVAL (XEXP (XEXP (x, 1), 1)) & -@@ -5164,6 +6315,19 @@ +@@ -5175,6 +6327,19 @@ arm_rtx_costs_1 (rtx x, enum rtx_code ou return true; } @@ -2857,7 +3466,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c /* Fall through */ case PLUS: -@@ -5192,7 +6356,9 @@ +@@ -5203,7 +6368,9 @@ arm_rtx_costs_1 (rtx x, enum rtx_code ou if (GET_MODE_CLASS (mode) == MODE_FLOAT) { @@ -2868,7 +3477,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c { *total = COSTS_N_INSNS (1); if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE -@@ -5307,7 +6473,9 @@ +@@ -5318,7 +6485,9 @@ arm_rtx_costs_1 (rtx x, enum rtx_code ou case NEG: if (GET_MODE_CLASS (mode) == MODE_FLOAT) { @@ -2879,7 +3488,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c { *total = COSTS_N_INSNS (1); return false; -@@ -5460,7 +6628,9 @@ +@@ -5471,7 +6640,9 @@ arm_rtx_costs_1 (rtx x, enum rtx_code ou case ABS: if (GET_MODE_CLASS (mode == MODE_FLOAT)) { @@ -2890,7 +3499,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c { *total = COSTS_N_INSNS (1); return false; -@@ -5563,7 +6733,8 @@ +@@ -5574,7 +6745,8 @@ arm_rtx_costs_1 (rtx x, enum rtx_code ou return true; case CONST_DOUBLE: @@ -2900,7 +3509,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c *total = COSTS_N_INSNS (1); else *total = COSTS_N_INSNS (4); -@@ -5638,7 +6809,8 @@ +@@ -5649,7 +6821,8 @@ arm_size_rtx_costs (rtx x, enum rtx_code return false; case MINUS: @@ -2910,7 +3519,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c { *total = COSTS_N_INSNS (1); return false; -@@ -5668,7 +6840,8 @@ +@@ -5679,7 +6852,8 @@ arm_size_rtx_costs (rtx x, enum rtx_code return false; case PLUS: @@ -2920,7 +3529,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c { *total = COSTS_N_INSNS (1); return false; -@@ -5698,7 +6871,8 @@ +@@ -5709,7 +6883,8 @@ arm_size_rtx_costs (rtx x, enum rtx_code return false; case NEG: @@ -2930,7 +3539,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c { *total = COSTS_N_INSNS (1); return false; -@@ -5722,7 +6896,8 @@ +@@ -5733,7 +6908,8 @@ arm_size_rtx_costs (rtx x, enum rtx_code return false; case ABS: @@ -2940,7 +3549,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c *total = COSTS_N_INSNS (1); else *total = COSTS_N_INSNS (1 + ARM_NUM_REGS (mode)); -@@ -5939,7 +7114,9 @@ +@@ -5950,7 +7126,9 @@ arm_fastmul_rtx_costs (rtx x, enum rtx_c if (GET_MODE_CLASS (mode) == MODE_FLOAT) { @@ -2951,7 +3560,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c { *total = COSTS_N_INSNS (1); return false; -@@ -6096,7 +7273,9 @@ +@@ -6107,7 +7285,9 @@ arm_9e_rtx_costs (rtx x, enum rtx_code c if (GET_MODE_CLASS (mode) == MODE_FLOAT) { @@ -2962,7 +3571,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c { *total = COSTS_N_INSNS (1); return false; -@@ -6919,10 +8098,13 @@ +@@ -6930,10 +8110,13 @@ arm_coproc_mem_operand (rtx op, bool wb) } /* Return TRUE if OP is a memory operand which we can load or store a vector @@ -2979,7 +3588,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c { rtx ind; -@@ -6955,23 +8137,16 @@ +@@ -6966,23 +8149,16 @@ neon_vector_mem_operand (rtx op, bool co return arm_address_register_rtx_p (ind, 0); /* Allow post-increment with Neon registers. */ @@ -3007,7 +3616,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c && GET_CODE (ind) == PLUS && GET_CODE (XEXP (ind, 0)) == REG && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) -@@ -7038,10 +8213,19 @@ +@@ -7049,10 +8225,19 @@ arm_eliminable_register (rtx x) enum reg_class coproc_secondary_reload_class (enum machine_mode mode, rtx x, bool wb) { @@ -3028,7 +3637,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c return NO_REGS; if (arm_coproc_mem_operand (x, wb) || s_register_operand (x, mode)) -@@ -7438,6 +8622,9 @@ +@@ -7449,6 +8634,9 @@ load_multiple_sequence (rtx *operands, i int base_reg = -1; int i; @@ -3038,7 +3647,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c /* Can only handle 2, 3, or 4 insns at present, though could be easily extended if required. */ gcc_assert (nops >= 2 && nops <= 4); -@@ -7667,6 +8854,9 @@ +@@ -7678,6 +8866,9 @@ store_multiple_sequence (rtx *operands, int base_reg = -1; int i; @@ -3048,7 +3657,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c /* Can only handle 2, 3, or 4 insns at present, though could be easily extended if required. */ gcc_assert (nops >= 2 && nops <= 4); -@@ -7874,7 +9064,7 @@ +@@ -7885,7 +9076,7 @@ arm_gen_load_multiple (int base_regno, i As a compromise, we use ldr for counts of 1 or 2 regs, and ldm for counts of 3 or 4 regs. */ @@ -3057,7 +3666,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c { rtx seq; -@@ -7937,7 +9127,7 @@ +@@ -7948,7 +9139,7 @@ arm_gen_store_multiple (int base_regno, /* See arm_gen_load_multiple for discussion of the pros/cons of ldm/stm usage for XScale. */ @@ -3066,7 +3675,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c { rtx seq; -@@ -9555,7 +10745,10 @@ +@@ -9566,7 +10757,10 @@ create_fix_barrier (Mfix *fix, HOST_WIDE gcc_assert (GET_CODE (from) != BARRIER); /* Count the length of this insn. */ @@ -3078,7 +3687,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c /* If there is a jump table, add its length. */ tmp = is_jump_table (from); -@@ -9867,6 +11060,8 @@ +@@ -9878,6 +11072,8 @@ arm_reorg (void) insn = table; } } @@ -3087,7 +3696,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c } fix = minipool_fix_head; -@@ -10072,6 +11267,21 @@ +@@ -10083,6 +11279,21 @@ static void vfp_output_fldmd (FILE * stream, unsigned int base, int reg, int count) { int i; @@ -3109,7 +3718,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c /* Workaround ARM10 VFPr1 bug. */ if (count == 2 && !arm_arch6) -@@ -10142,6 +11352,56 @@ +@@ -10153,6 +11364,56 @@ vfp_emit_fstmd (int base_reg, int count) rtx tmp, reg; int i; @@ -3166,7 +3775,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two register pairs are stored by a store multiple insn. We avoid this by pushing an extra pair. */ -@@ -10758,7 +12018,7 @@ +@@ -10769,7 +12030,7 @@ output_move_double (rtx *operands) } /* Output a move, load or store for quad-word vectors in ARM registers. Only @@ -3175,7 +3784,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c const char * output_move_quad (rtx *operands) -@@ -10954,6 +12214,12 @@ +@@ -10965,6 +12226,12 @@ output_move_neon (rtx *operands) ops[1] = reg; break; @@ -3188,16 +3797,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c case POST_MODIFY: /* FIXME: Not currently enabled in neon_vector_mem_operand. */ gcc_unreachable (); -@@ -10968,7 +12234,7 @@ - { - /* We're only using DImode here because it's a convenient size. */ - ops[0] = gen_rtx_REG (DImode, REGNO (reg) + 2 * i); -- ops[1] = adjust_address (mem, SImode, 8 * i); -+ ops[1] = adjust_address (mem, DImode, 8 * i); - if (reg_overlap_mentioned_p (ops[0], mem)) - { - gcc_assert (overlap == -1); -@@ -11557,7 +12823,7 @@ +@@ -11568,7 +12835,7 @@ arm_get_vfp_saved_size (void) if (count > 0) { /* Workaround ARM10 VFPr1 bug. */ @@ -3206,7 +3806,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c count++; saved += count * 8; } -@@ -11886,6 +13152,41 @@ +@@ -11897,6 +13164,41 @@ arm_output_function_prologue (FILE *f, H return_used_this_function = 0; } @@ -3248,7 +3848,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c const char * arm_output_epilogue (rtx sibling) { -@@ -11946,7 +13247,7 @@ +@@ -11957,7 +13259,7 @@ arm_output_epilogue (rtx sibling) /* This variable is for the Virtual Frame Pointer, not VFP regs. */ int vfp_offset = offsets->frame; @@ -3257,7 +3857,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c { for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) -@@ -12169,7 +13470,7 @@ +@@ -12180,7 +13482,7 @@ arm_output_epilogue (rtx sibling) SP_REGNUM, HARD_FRAME_POINTER_REGNUM); } @@ -3266,7 +3866,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c { for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++) if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) -@@ -12253,22 +13554,19 @@ +@@ -12264,22 +13566,19 @@ arm_output_epilogue (rtx sibling) to load use the LDR instruction - it is faster. For Thumb-2 always use pop and the assembler will pick the best instruction.*/ if (TARGET_ARM && saved_regs_mask == (1 << LR_REGNUM) @@ -3297,7 +3897,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c else print_multi_reg (f, "pop\t", SP_REGNUM, saved_regs_mask, 0); } -@@ -12389,6 +13687,32 @@ +@@ -12400,6 +13699,32 @@ emit_multi_reg_push (unsigned long mask) gcc_assert (num_regs && num_regs <= 16); @@ -3330,7 +3930,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c /* We don't record the PC in the dwarf frame information. */ num_dwarf_regs = num_regs; if (mask & (1 << PC_REGNUM)) -@@ -12737,22 +14061,23 @@ +@@ -12748,22 +14073,23 @@ arm_get_frame_offsets (void) { int reg = -1; @@ -3367,7 +3967,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c if (reg != -1) { -@@ -12876,7 +14201,7 @@ +@@ -12887,7 +14213,7 @@ arm_save_coproc_regs(void) /* Save any floating point call-saved registers used by this function. */ @@ -3376,7 +3976,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c { for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) -@@ -13483,7 +14808,11 @@ +@@ -13494,7 +14820,11 @@ arm_print_operand (FILE *stream, rtx x, { fprintf (stream, ", %s ", shift); if (val == -1) @@ -3389,7 +3989,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c else fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val); } -@@ -13704,6 +15033,30 @@ +@@ -13715,6 +15045,30 @@ arm_print_operand (FILE *stream, rtx x, } return; @@ -3420,7 +4020,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c /* Print a VFP/Neon double precision or quad precision register name. */ case 'P': case 'q': -@@ -13821,6 +15174,57 @@ +@@ -13832,6 +15186,57 @@ arm_print_operand (FILE *stream, rtx x, } return; @@ -3478,7 +4078,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c default: if (x == 0) { -@@ -13854,6 +15258,12 @@ +@@ -13865,6 +15270,12 @@ arm_print_operand (FILE *stream, rtx x, default: gcc_assert (GET_CODE (x) != NEG); fputc ('#', stream); @@ -3491,7 +4091,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c output_addr_const (stream, x); break; } -@@ -14245,6 +15655,10 @@ +@@ -14256,6 +15667,10 @@ arm_final_prescan_insn (rtx insn) first insn after the following code_label if REVERSE is true. */ rtx start_insn = insn; @@ -3502,7 +4102,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c /* If in state 4, check if the target branch is reached, in order to change back to state 0. */ if (arm_ccfsm_state == 4) -@@ -14618,6 +16032,11 @@ +@@ -14629,6 +16044,11 @@ arm_hard_regno_mode_ok (unsigned int reg if (mode == DFmode) return VFP_REGNO_OK_FOR_DOUBLE (regno); @@ -3514,7 +4114,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c if (TARGET_NEON) return (VALID_NEON_DREG_MODE (mode) && VFP_REGNO_OK_FOR_DOUBLE (regno)) || (VALID_NEON_QREG_MODE (mode) -@@ -14637,16 +16056,16 @@ +@@ -14648,16 +16068,16 @@ arm_hard_regno_mode_ok (unsigned int reg return mode == SImode; if (IS_IWMMXT_REGNUM (regno)) @@ -3536,7 +4136,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c if (regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM) -@@ -16103,6 +17522,15 @@ +@@ -16114,6 +17534,15 @@ arm_init_neon_builtins (void) } static void @@ -3552,7 +4152,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c arm_init_builtins (void) { arm_init_tls_builtins (); -@@ -16112,6 +17540,71 @@ +@@ -16123,6 +17552,71 @@ arm_init_builtins (void) if (TARGET_NEON) arm_init_neon_builtins (); @@ -3624,7 +4224,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c } /* Errors in the source file can cause expand_expr to return const0_rtx -@@ -17191,6 +18684,7 @@ +@@ -17202,6 +18696,7 @@ thumb_shiftable_const (unsigned HOST_WID unsigned HOST_WIDE_INT mask = 0xff; int i; @@ -3632,7 +4232,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c if (val == 0) /* XXX */ return 0; -@@ -18279,40 +19773,8 @@ +@@ -18290,40 +19785,8 @@ arm_file_start (void) else { int set_float_abi_attributes = 0; @@ -3675,7 +4275,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c { if (TARGET_HARD_FLOAT) asm_fprintf (asm_out_file, "\t.eabi_attribute 27, 3\n"); -@@ -18362,6 +19824,11 @@ +@@ -18373,6 +19836,11 @@ arm_file_start (void) val = 6; asm_fprintf (asm_out_file, "\t.eabi_attribute 30, %d\n", val); @@ -3687,7 +4287,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c if (arm_lang_output_object_attributes_hook) arm_lang_output_object_attributes_hook(); } -@@ -18591,6 +20058,23 @@ +@@ -18602,6 +20070,23 @@ arm_emit_vector_const (FILE *file, rtx x return 1; } @@ -3711,7 +4311,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c const char * arm_output_load_gr (rtx *operands) { -@@ -18628,19 +20112,24 @@ +@@ -18639,19 +20124,24 @@ arm_output_load_gr (rtx *operands) that way. */ static void @@ -3743,7 +4343,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c if (nregs < NUM_ARG_REGS) *pretend_size = (NUM_ARG_REGS - nregs) * UNITS_PER_WORD; } -@@ -19024,9 +20513,10 @@ +@@ -19035,9 +20525,10 @@ arm_vector_mode_supported_p (enum machin || mode == V16QImode || mode == V4SFmode || mode == V2DImode)) return true; @@ -3757,7 +4357,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c return true; return false; -@@ -19057,9 +20547,14 @@ +@@ -19068,9 +20559,14 @@ arm_dbx_register_number (unsigned int re if (IS_FPA_REGNUM (regno)) return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM; @@ -3774,7 +4374,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c if (IS_IWMMXT_GR_REGNUM (regno)) return 104 + regno - FIRST_IWMMXT_GR_REGNUM; -@@ -19070,6 +20565,39 @@ +@@ -19081,6 +20577,39 @@ arm_dbx_register_number (unsigned int re gcc_unreachable (); } @@ -3814,7 +4414,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c #ifdef TARGET_UNWIND_INFO /* Emit unwind directives for a store-multiple instruction or stack pointer -@@ -19556,6 +21084,7 @@ +@@ -19567,6 +21096,7 @@ arm_issue_rate (void) case cortexr4f: case cortexa8: case cortexa9: @@ -3822,7 +4422,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c return 2; default: -@@ -19620,6 +21149,10 @@ +@@ -19631,6 +21161,10 @@ arm_mangle_type (const_tree type) return "St9__va_list"; } @@ -3833,7 +4433,7 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c if (TREE_CODE (type) != VECTOR_TYPE) return NULL; -@@ -19676,6 +21209,86 @@ +@@ -19687,6 +21221,86 @@ arm_optimization_options (int level, int given on the command line. */ if (level > 0) flag_section_anchors = 2; @@ -3920,35 +4520,9 @@ diff -Nur a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c } #include "gt-arm.h" -diff -Nur a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def ---- a/gcc/config/arm/arm-cores.def 2009-02-20 16:20:38.000000000 +0100 -+++ b/gcc/config/arm/arm-cores.def 2010-01-25 09:50:28.975687047 +0100 -@@ -104,6 +104,7 @@ - ARM_CORE("xscale", xscale, 5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE, xscale) - ARM_CORE("iwmmxt", iwmmxt, 5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT, xscale) - ARM_CORE("iwmmxt2", iwmmxt2, 5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT, xscale) -+ARM_CORE("marvell-f", marvell_f, 5TE, FL_LDSCHED | FL_VFPV2 | FL_MARVELL_F, 9e) - - /* V5TEJ Architecture Processors */ - ARM_CORE("arm926ej-s", arm926ejs, 5TEJ, FL_LDSCHED, 9e) -@@ -117,9 +118,13 @@ - ARM_CORE("mpcorenovfp", mpcorenovfp, 6K, FL_LDSCHED, 9e) - ARM_CORE("mpcore", mpcore, 6K, FL_LDSCHED | FL_VFPV2, 9e) - ARM_CORE("arm1156t2-s", arm1156t2s, 6T2, FL_LDSCHED, 9e) -+ -+/* V7 Architecture Processors */ -+ARM_CORE("cortex-a5", cortexa5, 7A, FL_LDSCHED, 9e) - ARM_CORE("cortex-a8", cortexa8, 7A, FL_LDSCHED, 9e) - ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, 9e) - ARM_CORE("cortex-r4", cortexr4, 7R, FL_LDSCHED, 9e) - ARM_CORE("cortex-r4f", cortexr4f, 7R, FL_LDSCHED, 9e) - ARM_CORE("cortex-m3", cortexm3, 7M, FL_LDSCHED, 9e) - ARM_CORE("cortex-m1", cortexm1, 6M, FL_LDSCHED, 9e) -+ARM_CORE("cortex-m0", cortexm0, 6M, FL_LDSCHED, 9e) -diff -Nur a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h ---- a/gcc/config/arm/arm.h 2009-04-23 02:31:13.000000000 +0200 -+++ b/gcc/config/arm/arm.h 2010-01-25 09:50:28.975687047 +0100 -@@ -85,6 +85,10 @@ +--- a/gcc/config/arm/arm.h ++++ b/gcc/config/arm/arm.h +@@ -85,6 +85,10 @@ extern char arm_arch_name[]; builtin_define ("__IWMMXT__"); \ if (TARGET_AAPCS_BASED) \ builtin_define ("__ARM_EABI__"); \ @@ -3959,7 +4533,7 @@ diff -Nur a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h } while (0) /* The various ARM cores. */ -@@ -199,6 +203,13 @@ +@@ -199,6 +203,13 @@ extern void (*arm_lang_output_object_att #define TARGET_AAPCS_BASED \ (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS) @@ -3973,7 +4547,7 @@ diff -Nur a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h #define TARGET_HARD_TP (target_thread_pointer == TP_CP15) #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT) -@@ -211,35 +222,43 @@ +@@ -211,35 +222,43 @@ extern void (*arm_lang_output_object_att /* Thumb-1 only. */ #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) @@ -4027,7 +4601,7 @@ diff -Nur a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h /* Should MOVW/MOVT be used in preference to a constant pool. */ #define TARGET_USE_MOVT (arm_arch_thumb2 && !optimize_size) -@@ -289,40 +308,30 @@ +@@ -289,40 +308,30 @@ enum arm_fp_model ARM_FP_MODEL_VFP }; @@ -4089,7 +4663,7 @@ diff -Nur a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h enum float_abi_type { -@@ -337,6 +346,21 @@ +@@ -337,6 +346,21 @@ extern enum float_abi_type arm_float_abi #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT #endif @@ -4111,7 +4685,7 @@ diff -Nur a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h /* Which ABI to use. */ enum arm_abi_type { -@@ -383,12 +407,18 @@ +@@ -383,12 +407,18 @@ extern int arm_arch6; /* Nonzero if instructions not present in the 'M' profile can be used. */ extern int arm_arch_notm; @@ -4130,7 +4704,7 @@ diff -Nur a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h /* Nonzero if this chip is a StrongARM. */ extern int arm_tune_strongarm; -@@ -404,6 +434,9 @@ +@@ -404,6 +434,9 @@ extern int arm_arch_xscale; /* Nonzero if tuning for XScale. */ extern int arm_tune_xscale; @@ -4140,7 +4714,7 @@ diff -Nur a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h /* Nonzero if tuning for stores via the write buffer. */ extern int arm_tune_wbuf; -@@ -423,6 +456,10 @@ +@@ -423,6 +456,10 @@ extern int arm_arch_thumb2; /* Nonzero if chip supports integer division instruction. */ extern int arm_arch_hwdiv; @@ -4151,7 +4725,7 @@ diff -Nur a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h #ifndef TARGET_DEFAULT #define TARGET_DEFAULT (MASK_APCS_FRAME) #endif -@@ -757,12 +794,11 @@ +@@ -757,12 +794,11 @@ extern int arm_structure_size_boundary; fixed_regs[regno] = call_used_regs[regno] = 1; \ } \ \ @@ -4169,7 +4743,7 @@ diff -Nur a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h for (regno = FIRST_HI_REGNUM; \ regno <= LAST_HI_REGNUM; ++regno) \ fixed_regs[regno] = call_used_regs[regno] = 1; \ -@@ -881,6 +917,9 @@ +@@ -881,6 +917,9 @@ extern int arm_structure_size_boundary; /* The number of (integer) argument register available. */ #define NUM_ARG_REGS 4 @@ -4179,7 +4753,7 @@ diff -Nur a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h /* Return the register number of the N'th (integer) argument. */ #define ARG_REGISTER(N) (N - 1) -@@ -1059,7 +1098,7 @@ +@@ -1059,7 +1098,7 @@ extern int arm_structure_size_boundary; (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) #define VALID_IWMMXT_REG_MODE(MODE) \ @@ -4188,7 +4762,7 @@ diff -Nur a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h /* Modes valid for Neon D registers. */ #define VALID_NEON_DREG_MODE(MODE) \ -@@ -1230,11 +1269,14 @@ +@@ -1230,11 +1269,14 @@ enum reg_class || reg_classes_intersect_p (VFP_REGS, (CLASS)) \ : 0) @@ -4207,7 +4781,7 @@ diff -Nur a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h || (CLASS) == CC_REG) /* The class value for index registers, and the one for base regs. */ -@@ -1245,7 +1287,7 @@ +@@ -1245,7 +1287,7 @@ enum reg_class when addressing quantities in QI or HI mode; if we don't know the mode, then we must be conservative. */ #define MODE_BASE_REG_CLASS(MODE) \ @@ -4216,7 +4790,7 @@ diff -Nur a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h (((MODE) == SImode) ? BASE_REGS : LO_REGS)) /* For Thumb we can not support SP+reg addressing, so we return LO_REGS -@@ -1346,6 +1388,9 @@ +@@ -1346,6 +1388,9 @@ enum reg_class else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \ /* Need to be careful, -256 is not a valid offset. */ \ low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \ @@ -4226,7 +4800,7 @@ diff -Nur a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h else if (MODE == SImode \ || (MODE == SFmode && TARGET_SOFT_FLOAT) \ || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \ -@@ -1416,13 +1461,17 @@ +@@ -1416,13 +1461,17 @@ do { \ /* If defined, gives a class of registers that cannot be used as the operand of a SUBREG that changes the mode of the object illegally. */ @@ -4247,7 +4821,7 @@ diff -Nur a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \ (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \ (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \ -@@ -1491,9 +1540,10 @@ +@@ -1491,9 +1540,10 @@ do { \ /* Define how to find the value returned by a library function assuming the value has mode MODE. */ @@ -4261,7 +4835,7 @@ diff -Nur a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \ : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \ && GET_MODE_CLASS (MODE) == MODE_FLOAT \ -@@ -1502,22 +1552,16 @@ +@@ -1502,22 +1552,16 @@ do { \ ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \ : gen_rtx_REG (MODE, ARG_REGISTER (1))) @@ -4294,7 +4868,7 @@ diff -Nur a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h && TARGET_HARD_FLOAT_ABI && TARGET_FPA)) /* Amount of memory needed for an untyped call to save all possible return -@@ -1617,9 +1661,27 @@ +@@ -1617,9 +1661,27 @@ machine_function; that is in text_section. */ extern GTY(()) rtx thumb_call_via_label[14]; @@ -4324,7 +4898,7 @@ diff -Nur a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h typedef struct { /* This is the number of registers of arguments scanned so far. */ -@@ -1628,9 +1690,33 @@ +@@ -1628,9 +1690,33 @@ typedef struct int iwmmxt_nregs; int named_count; int nargs; @@ -4359,7 +4933,7 @@ diff -Nur a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h /* Define where to put the arguments to a function. Value is zero to push the argument on the stack, or a hard register in which to store the argument. -@@ -1674,13 +1760,7 @@ +@@ -1674,13 +1760,7 @@ typedef struct of mode MODE and data type TYPE. (TYPE is null for libcalls where that information may not be available.) */ #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ @@ -4374,7 +4948,7 @@ diff -Nur a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h /* If defined, a C expression that gives the alignment boundary, in bits, of an argument with the specified mode and type. If it is not defined, -@@ -1692,9 +1772,11 @@ +@@ -1692,9 +1772,11 @@ typedef struct /* 1 if N is a possible register number for function argument passing. On the ARM, r0-r3 are used to pass args. */ @@ -4389,7 +4963,7 @@ diff -Nur a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) -@@ -2324,7 +2406,8 @@ +@@ -2324,7 +2406,8 @@ do { \ /* Try to generate sequences that don't involve branches, we can then use conditional instructions */ #define BRANCH_COST(speed_p, predictable_p) \ @@ -4399,7 +4973,7 @@ diff -Nur a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h /* Position Independent Code. */ /* We decide which register to use based on the compilation options and -@@ -2392,6 +2475,7 @@ +@@ -2392,6 +2475,7 @@ extern int making_const_table; /* The arm5 clz instruction returns 32. */ #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) @@ -4407,7 +4981,7 @@ diff -Nur a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h #undef ASM_APP_OFF #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \ -@@ -2404,6 +2488,19 @@ +@@ -2404,6 +2488,19 @@ extern int making_const_table; if (TARGET_ARM) \ asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \ STACK_POINTER_REGNUM, REGNO); \ @@ -4427,7 +5001,7 @@ diff -Nur a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h else \ asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \ } while (0) -@@ -2415,6 +2512,14 @@ +@@ -2415,6 +2512,14 @@ extern int making_const_table; if (TARGET_ARM) \ asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \ STACK_POINTER_REGNUM, REGNO); \ @@ -4442,9 +5016,8 @@ diff -Nur a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h else \ asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \ } while (0) -diff -Nur a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md ---- a/gcc/config/arm/arm.md 2009-05-16 15:28:27.000000000 +0200 -+++ b/gcc/config/arm/arm.md 2010-01-25 09:50:28.985687200 +0100 +--- a/gcc/config/arm/arm.md ++++ b/gcc/config/arm/arm.md @@ -99,6 +99,7 @@ ; correctly for PIC usage. (UNSPEC_GOTSYM_OFF 24) ; The offset of the start of the the GOT from a @@ -4527,18 +5100,6 @@ diff -Nur a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md (include "vfp11.md") -@@ -472,9 +479,9 @@ - if (TARGET_THUMB1) - { - if (GET_CODE (operands[1]) != REG) -- operands[1] = force_reg (SImode, operands[1]); -+ operands[1] = force_reg (DImode, operands[1]); - if (GET_CODE (operands[2]) != REG) -- operands[2] = force_reg (SImode, operands[2]); -+ operands[2] = force_reg (DImode, operands[2]); - } - " - ) @@ -620,10 +627,11 @@ sub%?\\t%0, %1, #%n2 sub%?\\t%0, %1, #%n2 @@ -6552,32 +7113,54 @@ diff -Nur a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md "" ) -diff -Nur a/gcc/config/arm/arm-modes.def b/gcc/config/arm/arm-modes.def ---- a/gcc/config/arm/arm-modes.def 2007-08-02 12:49:31.000000000 +0200 -+++ b/gcc/config/arm/arm-modes.def 2010-01-25 09:50:28.985687200 +0100 -@@ -25,6 +25,11 @@ - FIXME What format is this? */ - FLOAT_MODE (XF, 12, 0); +--- a/gcc/config/arm/arm.opt ++++ b/gcc/config/arm/arm.opt +@@ -78,6 +78,10 @@ Specify if floating point hardware shoul + mfp= + Target RejectNegative Joined Undocumented Var(target_fpe_name) -+/* Half-precision floating point */ -+FLOAT_MODE (HF, 2, 0); -+ADJUST_FLOAT_FORMAT (HF, ((arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) -+ ? &arm_half_format : &ieee_half_format)); ++mfp16-format= ++Target RejectNegative Joined Var(target_fp16_format_name) ++Specify the __fp16 floating-point format + - /* CCFPEmode should be used with floating inequalities, - CCFPmode should be used with floating equalities. - CC_NOOVmode should be used with SImode integer equalities. -@@ -62,6 +67,4 @@ - INT_MODE (EI, 24); - INT_MODE (OI, 32); - INT_MODE (CI, 48); --/* ??? This should actually have 512 bits but the precision only has 9 -- bits. */ --FRACTIONAL_INT_MODE (XI, 511, 64); -+INT_MODE (XI, 64); -diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h ---- a/gcc/config/arm/arm_neon.h 2009-04-10 01:23:07.000000000 +0200 -+++ b/gcc/config/arm/arm_neon.h 2010-01-25 09:50:28.985687200 +0100 + ;; Now ignored. + mfpe + Target RejectNegative Mask(FPE) Undocumented +@@ -93,6 +97,10 @@ mhard-float + Target RejectNegative + Alias for -mfloat-abi=hard + ++mfix-janus-2cc ++Target Report Mask(FIX_JANUS) ++Work around hardware errata for Avalent Janus 2CC cores. ++ + mlittle-endian + Target Report RejectNegative InverseMask(BIG_END) + Assume target CPU is configured as little endian +@@ -101,6 +109,10 @@ mlong-calls + Target Report Mask(LONG_CALLS) + Generate call insns as indirect calls, if necessary + ++mmarvell-div ++Target Report Mask(MARVELL_DIV) ++Generate hardware integer division instructions supported by some Marvell cores. ++ + mpic-register= + Target RejectNegative Joined Var(arm_pic_register_string) + Specify the register to be used for PIC addressing +@@ -157,6 +169,10 @@ mvectorize-with-neon-quad + Target Report Mask(NEON_VECTORIZE_QUAD) + Use Neon quad-word (rather than double-word) registers for vectorization + ++mlow-irq-latency ++Target Report Var(low_irq_latency) ++Try to reduce interrupt latency of the generated code ++ + mword-relocations + Target Report Var(target_word_relocations) Init(TARGET_DEFAULT_WORD_RELOCATIONS) + Only generate absolute relocations on word sized values. +--- a/gcc/config/arm/arm_neon.h ++++ b/gcc/config/arm/arm_neon.h @@ -36,7 +36,11 @@ extern "C" { #endif @@ -6590,7 +7173,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h typedef __builtin_neon_qi int8x8_t __attribute__ ((__vector_size__ (8))); typedef __builtin_neon_hi int16x4_t __attribute__ ((__vector_size__ (8))); -@@ -61,7 +65,7 @@ +@@ -61,7 +65,7 @@ typedef __builtin_neon_uhi uint16x8_t __ typedef __builtin_neon_usi uint32x4_t __attribute__ ((__vector_size__ (16))); typedef __builtin_neon_udi uint64x2_t __attribute__ ((__vector_size__ (16))); @@ -6599,7 +7182,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h typedef __builtin_neon_poly8 poly8_t; typedef __builtin_neon_poly16 poly16_t; -@@ -5085,7 +5089,7 @@ +@@ -5085,7 +5089,7 @@ vset_lane_s32 (int32_t __a, int32x2_t __ __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) vset_lane_f32 (float32_t __a, float32x2_t __b, const int __c) { @@ -6608,7 +7191,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -@@ -5151,7 +5155,7 @@ +@@ -5151,7 +5155,7 @@ vsetq_lane_s32 (int32_t __a, int32x4_t _ __extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) vsetq_lane_f32 (float32_t __a, float32x4_t __b, const int __c) { @@ -6617,7 +7200,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -@@ -5283,7 +5287,7 @@ +@@ -5283,7 +5287,7 @@ vdup_n_s32 (int32_t __a) __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) vdup_n_f32 (float32_t __a) { @@ -6626,7 +7209,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -@@ -5349,7 +5353,7 @@ +@@ -5349,7 +5353,7 @@ vdupq_n_s32 (int32_t __a) __extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) vdupq_n_f32 (float32_t __a) { @@ -6635,7 +7218,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -@@ -5415,7 +5419,7 @@ +@@ -5415,7 +5419,7 @@ vmov_n_s32 (int32_t __a) __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) vmov_n_f32 (float32_t __a) { @@ -6644,7 +7227,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -@@ -5481,7 +5485,7 @@ +@@ -5481,7 +5485,7 @@ vmovq_n_s32 (int32_t __a) __extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) vmovq_n_f32 (float32_t __a) { @@ -6653,7 +7236,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -@@ -6591,7 +6595,7 @@ +@@ -6591,7 +6595,7 @@ vmul_n_s32 (int32x2_t __a, int32_t __b) __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) vmul_n_f32 (float32x2_t __a, float32_t __b) { @@ -6662,7 +7245,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -@@ -6621,7 +6625,7 @@ +@@ -6621,7 +6625,7 @@ vmulq_n_s32 (int32x4_t __a, int32_t __b) __extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) vmulq_n_f32 (float32x4_t __a, float32_t __b) { @@ -6671,7 +7254,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -@@ -6735,7 +6739,7 @@ +@@ -6735,7 +6739,7 @@ vmla_n_s32 (int32x2_t __a, int32x2_t __b __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) vmla_n_f32 (float32x2_t __a, float32x2_t __b, float32_t __c) { @@ -6680,7 +7263,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -@@ -6765,7 +6769,7 @@ +@@ -6765,7 +6769,7 @@ vmlaq_n_s32 (int32x4_t __a, int32x4_t __ __extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) vmlaq_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c) { @@ -6689,7 +7272,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -@@ -6831,7 +6835,7 @@ +@@ -6831,7 +6835,7 @@ vmls_n_s32 (int32x2_t __a, int32x2_t __b __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) vmls_n_f32 (float32x2_t __a, float32x2_t __b, float32_t __c) { @@ -6698,7 +7281,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -@@ -6861,7 +6865,7 @@ +@@ -6861,7 +6865,7 @@ vmlsq_n_s32 (int32x4_t __a, int32x4_t __ __extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) vmlsq_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c) { @@ -6707,7 +7290,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -@@ -7851,7 +7855,7 @@ +@@ -7851,7 +7855,7 @@ vld1_s64 (const int64_t * __a) __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) vld1_f32 (const float32_t * __a) { @@ -6716,7 +7299,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -@@ -7917,7 +7921,7 @@ +@@ -7917,7 +7921,7 @@ vld1q_s64 (const int64_t * __a) __extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) vld1q_f32 (const float32_t * __a) { @@ -6725,7 +7308,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -@@ -7977,7 +7981,7 @@ +@@ -7977,7 +7981,7 @@ vld1_lane_s32 (const int32_t * __a, int3 __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) vld1_lane_f32 (const float32_t * __a, float32x2_t __b, const int __c) { @@ -6734,7 +7317,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -@@ -8043,7 +8047,7 @@ +@@ -8043,7 +8047,7 @@ vld1q_lane_s32 (const int32_t * __a, int __extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) vld1q_lane_f32 (const float32_t * __a, float32x4_t __b, const int __c) { @@ -6743,7 +7326,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -@@ -8109,7 +8113,7 @@ +@@ -8109,7 +8113,7 @@ vld1_dup_s32 (const int32_t * __a) __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) vld1_dup_f32 (const float32_t * __a) { @@ -6752,7 +7335,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -@@ -8175,7 +8179,7 @@ +@@ -8175,7 +8179,7 @@ vld1q_dup_s32 (const int32_t * __a) __extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) vld1q_dup_f32 (const float32_t * __a) { @@ -6761,7 +7344,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -@@ -8247,7 +8251,7 @@ +@@ -8247,7 +8251,7 @@ vst1_s64 (int64_t * __a, int64x1_t __b) __extension__ static __inline void __attribute__ ((__always_inline__)) vst1_f32 (float32_t * __a, float32x2_t __b) { @@ -6770,7 +7353,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline void __attribute__ ((__always_inline__)) -@@ -8313,7 +8317,7 @@ +@@ -8313,7 +8317,7 @@ vst1q_s64 (int64_t * __a, int64x2_t __b) __extension__ static __inline void __attribute__ ((__always_inline__)) vst1q_f32 (float32_t * __a, float32x4_t __b) { @@ -6779,7 +7362,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline void __attribute__ ((__always_inline__)) -@@ -8373,7 +8377,7 @@ +@@ -8373,7 +8377,7 @@ vst1_lane_s32 (int32_t * __a, int32x2_t __extension__ static __inline void __attribute__ ((__always_inline__)) vst1_lane_f32 (float32_t * __a, float32x2_t __b, const int __c) { @@ -6788,7 +7371,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline void __attribute__ ((__always_inline__)) -@@ -8439,7 +8443,7 @@ +@@ -8439,7 +8443,7 @@ vst1q_lane_s32 (int32_t * __a, int32x4_t __extension__ static __inline void __attribute__ ((__always_inline__)) vst1q_lane_f32 (float32_t * __a, float32x4_t __b, const int __c) { @@ -6797,7 +7380,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline void __attribute__ ((__always_inline__)) -@@ -8512,7 +8516,7 @@ +@@ -8512,7 +8516,7 @@ __extension__ static __inline float32x2x vld2_f32 (const float32_t * __a) { union { float32x2x2_t __i; __builtin_neon_ti __o; } __rv; @@ -6806,7 +7389,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h return __rv.__i; } -@@ -8600,7 +8604,7 @@ +@@ -8600,7 +8604,7 @@ __extension__ static __inline float32x4x vld2q_f32 (const float32_t * __a) { union { float32x4x2_t __i; __builtin_neon_oi __o; } __rv; @@ -6815,7 +7398,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h return __rv.__i; } -@@ -8676,7 +8680,7 @@ +@@ -8676,7 +8680,7 @@ vld2_lane_f32 (const float32_t * __a, fl { union { float32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; union { float32x2x2_t __i; __builtin_neon_ti __o; } __rv; @@ -6824,7 +7407,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h return __rv.__i; } -@@ -8748,7 +8752,7 @@ +@@ -8748,7 +8752,7 @@ vld2q_lane_f32 (const float32_t * __a, f { union { float32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; union { float32x4x2_t __i; __builtin_neon_oi __o; } __rv; @@ -6833,7 +7416,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h return __rv.__i; } -@@ -8807,7 +8811,7 @@ +@@ -8807,7 +8811,7 @@ __extension__ static __inline float32x2x vld2_dup_f32 (const float32_t * __a) { union { float32x2x2_t __i; __builtin_neon_ti __o; } __rv; @@ -6842,7 +7425,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h return __rv.__i; } -@@ -8892,7 +8896,7 @@ +@@ -8892,7 +8896,7 @@ __extension__ static __inline void __att vst2_f32 (float32_t * __a, float32x2x2_t __b) { union { float32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; @@ -6851,7 +7434,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline void __attribute__ ((__always_inline__)) -@@ -8969,7 +8973,7 @@ +@@ -8969,7 +8973,7 @@ __extension__ static __inline void __att vst2q_f32 (float32_t * __a, float32x4x2_t __b) { union { float32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; @@ -6860,7 +7443,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline void __attribute__ ((__always_inline__)) -@@ -9032,7 +9036,7 @@ +@@ -9032,7 +9036,7 @@ __extension__ static __inline void __att vst2_lane_f32 (float32_t * __a, float32x2x2_t __b, const int __c) { union { float32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b }; @@ -6869,7 +7452,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline void __attribute__ ((__always_inline__)) -@@ -9088,7 +9092,7 @@ +@@ -9088,7 +9092,7 @@ __extension__ static __inline void __att vst2q_lane_f32 (float32_t * __a, float32x4x2_t __b, const int __c) { union { float32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; @@ -6878,7 +7461,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline void __attribute__ ((__always_inline__)) -@@ -9140,7 +9144,7 @@ +@@ -9140,7 +9144,7 @@ __extension__ static __inline float32x2x vld3_f32 (const float32_t * __a) { union { float32x2x3_t __i; __builtin_neon_ei __o; } __rv; @@ -6887,7 +7470,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h return __rv.__i; } -@@ -9228,7 +9232,7 @@ +@@ -9228,7 +9232,7 @@ __extension__ static __inline float32x4x vld3q_f32 (const float32_t * __a) { union { float32x4x3_t __i; __builtin_neon_ci __o; } __rv; @@ -6896,7 +7479,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h return __rv.__i; } -@@ -9304,7 +9308,7 @@ +@@ -9304,7 +9308,7 @@ vld3_lane_f32 (const float32_t * __a, fl { union { float32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; union { float32x2x3_t __i; __builtin_neon_ei __o; } __rv; @@ -6905,7 +7488,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h return __rv.__i; } -@@ -9376,7 +9380,7 @@ +@@ -9376,7 +9380,7 @@ vld3q_lane_f32 (const float32_t * __a, f { union { float32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; union { float32x4x3_t __i; __builtin_neon_ci __o; } __rv; @@ -6914,7 +7497,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h return __rv.__i; } -@@ -9435,7 +9439,7 @@ +@@ -9435,7 +9439,7 @@ __extension__ static __inline float32x2x vld3_dup_f32 (const float32_t * __a) { union { float32x2x3_t __i; __builtin_neon_ei __o; } __rv; @@ -6923,7 +7506,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h return __rv.__i; } -@@ -9520,7 +9524,7 @@ +@@ -9520,7 +9524,7 @@ __extension__ static __inline void __att vst3_f32 (float32_t * __a, float32x2x3_t __b) { union { float32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; @@ -6932,7 +7515,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline void __attribute__ ((__always_inline__)) -@@ -9597,7 +9601,7 @@ +@@ -9597,7 +9601,7 @@ __extension__ static __inline void __att vst3q_f32 (float32_t * __a, float32x4x3_t __b) { union { float32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; @@ -6941,7 +7524,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline void __attribute__ ((__always_inline__)) -@@ -9660,7 +9664,7 @@ +@@ -9660,7 +9664,7 @@ __extension__ static __inline void __att vst3_lane_f32 (float32_t * __a, float32x2x3_t __b, const int __c) { union { float32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; @@ -6950,7 +7533,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline void __attribute__ ((__always_inline__)) -@@ -9716,7 +9720,7 @@ +@@ -9716,7 +9720,7 @@ __extension__ static __inline void __att vst3q_lane_f32 (float32_t * __a, float32x4x3_t __b, const int __c) { union { float32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; @@ -6959,7 +7542,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline void __attribute__ ((__always_inline__)) -@@ -9768,7 +9772,7 @@ +@@ -9768,7 +9772,7 @@ __extension__ static __inline float32x2x vld4_f32 (const float32_t * __a) { union { float32x2x4_t __i; __builtin_neon_oi __o; } __rv; @@ -6968,7 +7551,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h return __rv.__i; } -@@ -9856,7 +9860,7 @@ +@@ -9856,7 +9860,7 @@ __extension__ static __inline float32x4x vld4q_f32 (const float32_t * __a) { union { float32x4x4_t __i; __builtin_neon_xi __o; } __rv; @@ -6977,7 +7560,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h return __rv.__i; } -@@ -9932,7 +9936,7 @@ +@@ -9932,7 +9936,7 @@ vld4_lane_f32 (const float32_t * __a, fl { union { float32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; union { float32x2x4_t __i; __builtin_neon_oi __o; } __rv; @@ -6986,7 +7569,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h return __rv.__i; } -@@ -10004,7 +10008,7 @@ +@@ -10004,7 +10008,7 @@ vld4q_lane_f32 (const float32_t * __a, f { union { float32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; union { float32x4x4_t __i; __builtin_neon_xi __o; } __rv; @@ -6995,7 +7578,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h return __rv.__i; } -@@ -10063,7 +10067,7 @@ +@@ -10063,7 +10067,7 @@ __extension__ static __inline float32x2x vld4_dup_f32 (const float32_t * __a) { union { float32x2x4_t __i; __builtin_neon_oi __o; } __rv; @@ -7004,7 +7587,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h return __rv.__i; } -@@ -10148,7 +10152,7 @@ +@@ -10148,7 +10152,7 @@ __extension__ static __inline void __att vst4_f32 (float32_t * __a, float32x2x4_t __b) { union { float32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; @@ -7013,7 +7596,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline void __attribute__ ((__always_inline__)) -@@ -10225,7 +10229,7 @@ +@@ -10225,7 +10229,7 @@ __extension__ static __inline void __att vst4q_f32 (float32_t * __a, float32x4x4_t __b) { union { float32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; @@ -7022,7 +7605,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline void __attribute__ ((__always_inline__)) -@@ -10288,7 +10292,7 @@ +@@ -10288,7 +10292,7 @@ __extension__ static __inline void __att vst4_lane_f32 (float32_t * __a, float32x2x4_t __b, const int __c) { union { float32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b }; @@ -7031,7 +7614,7 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline void __attribute__ ((__always_inline__)) -@@ -10344,7 +10348,7 @@ +@@ -10344,7 +10348,7 @@ __extension__ static __inline void __att vst4q_lane_f32 (float32_t * __a, float32x4x4_t __b, const int __c) { union { float32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; @@ -7040,161 +7623,73 @@ diff -Nur a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h } __extension__ static __inline void __attribute__ ((__always_inline__)) -diff -Nur a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt ---- a/gcc/config/arm/arm.opt 2009-02-20 16:20:38.000000000 +0100 -+++ b/gcc/config/arm/arm.opt 2010-01-25 09:50:28.985687200 +0100 -@@ -78,6 +78,10 @@ - mfp= - Target RejectNegative Joined Undocumented Var(target_fpe_name) - -+mfp16-format= -+Target RejectNegative Joined Var(target_fp16_format_name) -+Specify the __fp16 floating-point format -+ - ;; Now ignored. - mfpe - Target RejectNegative Mask(FPE) Undocumented -@@ -93,6 +97,10 @@ - Target RejectNegative - Alias for -mfloat-abi=hard +--- a/gcc/config/arm/bpabi-v6m.S ++++ b/gcc/config/arm/bpabi-v6m.S +@@ -69,9 +69,52 @@ FUNC_START aeabi_ulcmp -+mfix-janus-2cc -+Target Report Mask(FIX_JANUS) -+Work around hardware errata for Avalent Janus 2CC cores. -+ - mlittle-endian - Target Report RejectNegative InverseMask(BIG_END) - Assume target CPU is configured as little endian -@@ -101,6 +109,10 @@ - Target Report Mask(LONG_CALLS) - Generate call insns as indirect calls, if necessary + #endif /* L_aeabi_ulcmp */ -+mmarvell-div -+Target Report Mask(MARVELL_DIV) -+Generate hardware integer division instructions supported by some Marvell cores. ++.macro test_div_by_zero signed ++ cmp yyh, #0 ++ bne 7f ++ cmp yyl, #0 ++ bne 7f ++ cmp xxh, #0 ++ bne 2f ++ cmp xxl, #0 ++2: ++ .ifc \signed, unsigned ++ beq 3f ++ mov xxh, #0 ++ mvn xxh, xxh @ 0xffffffff ++ mov xxl, xxh ++3: ++ .else ++ beq 5f ++ blt 6f ++ mov xxl, #0 ++ mvn xxl, xxl @ 0xffffffff ++ lsr xxh, xxl, #1 @ 0x7fffffff ++ b 5f ++6: mov xxh, #0x80 ++ lsl xxh, xxh, #24 @ 0x80000000 ++ mov xxl, #0 ++5: ++ .endif ++ @ tailcalls are tricky on v6-m. ++ push {r0, r1, r2} ++ ldr r0, 1f ++ adr r1, 1f ++ add r0, r1 ++ str r0, [sp, #8] ++ @ We know we are not on armv4t, so pop pc is safe. ++ pop {r0, r1, pc} ++ .align 2 ++1: ++ .word __aeabi_ldiv0 - 1b ++7: ++.endm + - mpic-register= - Target RejectNegative Joined Var(arm_pic_register_string) - Specify the register to be used for PIC addressing -@@ -157,6 +169,10 @@ - Target Report Mask(NEON_VECTORIZE_QUAD) - Use Neon quad-word (rather than double-word) registers for vectorization + #ifdef L_aeabi_ldivmod -+mlow-irq-latency -+Target Report Var(low_irq_latency) -+Try to reduce interrupt latency of the generated code + FUNC_START aeabi_ldivmod ++ test_div_by_zero signed + - mword-relocations - Target Report Var(target_word_relocations) Init(TARGET_DEFAULT_WORD_RELOCATIONS) - Only generate absolute relocations on word sized values. -diff -Nur a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h ---- a/gcc/config/arm/arm-protos.h 2009-02-20 16:20:38.000000000 +0100 -+++ b/gcc/config/arm/arm-protos.h 2010-01-25 09:50:28.985687200 +0100 -@@ -88,7 +88,7 @@ - - extern int cirrus_memory_offset (rtx); - extern int arm_coproc_mem_operand (rtx, bool); --extern int neon_vector_mem_operand (rtx, bool); -+extern int neon_vector_mem_operand (rtx, int); - extern int neon_struct_mem_operand (rtx); - extern int arm_no_early_store_addr_dep (rtx, rtx); - extern int arm_no_early_alu_shift_dep (rtx, rtx); -@@ -144,6 +144,7 @@ - extern int arm_debugger_arg_offset (int, rtx); - extern bool arm_is_long_call_p (tree); - extern int arm_emit_vector_const (FILE *, rtx); -+extern void arm_emit_fp16_const (rtx c); - extern const char * arm_output_load_gr (rtx *); - extern const char *vfp_output_fstmd (rtx *); - extern void arm_set_return_address (rtx, rtx); -@@ -154,13 +155,15 @@ - - #if defined TREE_CODE - extern rtx arm_function_arg (CUMULATIVE_ARGS *, enum machine_mode, tree, int); -+extern void arm_function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode, -+ tree, bool); - extern void arm_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree); - extern bool arm_pad_arg_upward (enum machine_mode, const_tree); - extern bool arm_pad_reg_upward (enum machine_mode, tree, int); - extern bool arm_needs_doubleword_align (enum machine_mode, tree); --extern rtx arm_function_value(const_tree, const_tree); - #endif - extern int arm_apply_result_size (void); -+extern rtx aapcs_libcall_value (enum machine_mode); - - #endif /* RTX_CODE */ - -diff -Nur a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md ---- a/gcc/config/arm/arm-tune.md 2009-07-22 09:43:59.000000000 +0200 -+++ b/gcc/config/arm/arm-tune.md 2010-01-25 09:50:28.985687200 +0100 -@@ -1,5 +1,5 @@ - ;; -*- buffer-read-only: t -*- - ;; Generated automatically by gentune.sh from arm-cores.def - (define_attr "tune" -- "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,cortexa8,cortexa9,cortexr4,cortexr4f,cortexm3,cortexm1" -+ "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,marvell_f,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,cortexa5,cortexa8,cortexa9,cortexr4,cortexr4f,cortexm3,cortexm1,cortexm0" - (const (symbol_ref "arm_tune"))) -diff -Nur a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h ---- a/gcc/config/arm/bpabi.h 2009-02-20 16:20:38.000000000 +0100 -+++ b/gcc/config/arm/bpabi.h 2010-01-25 09:50:28.985687200 +0100 -@@ -30,7 +30,7 @@ - - /* Section 4.1 of the AAPCS requires the use of VFP format. */ - #undef FPUTYPE_DEFAULT --#define FPUTYPE_DEFAULT FPUTYPE_VFP -+#define FPUTYPE_DEFAULT "vfp" - - /* TARGET_BIG_ENDIAN_DEFAULT is set in - config.gcc for big endian configurations. */ -@@ -53,6 +53,8 @@ - - #define TARGET_FIX_V4BX_SPEC " %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*|march=armv4:--fix-v4bx}" + push {r0, r1} + mov r0, sp + push {r0, lr} +@@ -89,6 +132,8 @@ FUNC_START aeabi_ldivmod + #ifdef L_aeabi_uldivmod -+#define BE8_LINK_SPEC " %{mbig-endian:%{march=armv7-a|mcpu=cortex-a5|mcpu=cortex-a8|mcpu=cortex-a9:%{!r:--be8}}}" + FUNC_START aeabi_uldivmod ++ test_div_by_zero unsigned + - /* Tell the assembler to build BPABI binaries. */ - #undef SUBTARGET_EXTRA_ASM_SPEC - #define SUBTARGET_EXTRA_ASM_SPEC "%{mabi=apcs-gnu|mabi=atpcs:-meabi=gnu;:-meabi=5}" TARGET_FIX_V4BX_SPEC -@@ -65,7 +67,7 @@ - #define BPABI_LINK_SPEC \ - "%{mbig-endian:-EB} %{mlittle-endian:-EL} " \ - "%{static:-Bstatic} %{shared:-shared} %{symbolic:-Bsymbolic} " \ -- "-X" SUBTARGET_EXTRA_LINK_SPEC TARGET_FIX_V4BX_SPEC -+ "-X" SUBTARGET_EXTRA_LINK_SPEC TARGET_FIX_V4BX_SPEC BE8_LINK_SPEC - - #undef LINK_SPEC - #define LINK_SPEC BPABI_LINK_SPEC -@@ -90,16 +92,22 @@ - #define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (muldi3, lmul) - #endif - #ifdef L_fixdfdi --#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixdfdi, d2lz) -+#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixdfdi, d2lz) \ -+ extern DWtype __fixdfdi (DFtype) __attribute__((pcs("aapcs"))); \ -+ extern UDWtype __fixunsdfdi (DFtype) __asm__("__aeabi_d2ulz") __attribute__((pcs("aapcs"))); - #endif - #ifdef L_fixunsdfdi --#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixunsdfdi, d2ulz) -+#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixunsdfdi, d2ulz) \ -+ extern UDWtype __fixunsdfdi (DFtype) __attribute__((pcs("aapcs"))); - #endif - #ifdef L_fixsfdi --#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixsfdi, f2lz) -+#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixsfdi, f2lz) \ -+ extern DWtype __fixsfdi (SFtype) __attribute__((pcs("aapcs"))); \ -+ extern UDWtype __fixunssfdi (SFtype) __asm__("__aeabi_f2ulz") __attribute__((pcs("aapcs"))); - #endif - #ifdef L_fixunssfdi --#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixunssfdi, f2ulz) -+#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixunssfdi, f2ulz) \ -+ extern UDWtype __fixunssfdi (SFtype) __attribute__((pcs("aapcs"))); - #endif - #ifdef L_floatdidf - #define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (floatdidf, l2d) -diff -Nur a/gcc/config/arm/bpabi.S b/gcc/config/arm/bpabi.S ---- a/gcc/config/arm/bpabi.S 2009-04-10 01:23:07.000000000 +0200 -+++ b/gcc/config/arm/bpabi.S 2010-01-25 09:50:28.985687200 +0100 -@@ -64,20 +64,69 @@ + push {r0, r1} + mov r0, sp + push {r0, lr} +--- a/gcc/config/arm/bpabi.S ++++ b/gcc/config/arm/bpabi.S +@@ -64,20 +64,69 @@ ARM_FUNC_START aeabi_ulcmp #endif /* L_aeabi_ulcmp */ @@ -7268,7 +7763,7 @@ diff -Nur a/gcc/config/arm/bpabi.S b/gcc/config/arm/bpabi.S RET #endif /* L_aeabi_ldivmod */ -@@ -85,17 +134,20 @@ +@@ -85,17 +134,20 @@ ARM_FUNC_START aeabi_ldivmod #ifdef L_aeabi_uldivmod ARM_FUNC_START aeabi_uldivmod @@ -7293,74 +7788,64 @@ diff -Nur a/gcc/config/arm/bpabi.S b/gcc/config/arm/bpabi.S RET #endif /* L_aeabi_divmod */ -diff -Nur a/gcc/config/arm/bpabi-v6m.S b/gcc/config/arm/bpabi-v6m.S ---- a/gcc/config/arm/bpabi-v6m.S 2009-04-10 01:23:07.000000000 +0200 -+++ b/gcc/config/arm/bpabi-v6m.S 2010-01-25 09:50:28.985687200 +0100 -@@ -69,9 +69,52 @@ +--- a/gcc/config/arm/bpabi.h ++++ b/gcc/config/arm/bpabi.h +@@ -30,7 +30,7 @@ - #endif /* L_aeabi_ulcmp */ + /* Section 4.1 of the AAPCS requires the use of VFP format. */ + #undef FPUTYPE_DEFAULT +-#define FPUTYPE_DEFAULT FPUTYPE_VFP ++#define FPUTYPE_DEFAULT "vfp" -+.macro test_div_by_zero signed -+ cmp yyh, #0 -+ bne 7f -+ cmp yyl, #0 -+ bne 7f -+ cmp xxh, #0 -+ bne 2f -+ cmp xxl, #0 -+2: -+ .ifc \signed, unsigned -+ beq 3f -+ mov xxh, #0 -+ mvn xxh, xxh @ 0xffffffff -+ mov xxl, xxh -+3: -+ .else -+ beq 5f -+ blt 6f -+ mov xxl, #0 -+ mvn xxl, xxl @ 0xffffffff -+ lsr xxh, xxl, #1 @ 0x7fffffff -+ b 5f -+6: mov xxh, #0x80 -+ lsl xxh, xxh, #24 @ 0x80000000 -+ mov xxl, #0 -+5: -+ .endif -+ @ tailcalls are tricky on v6-m. -+ push {r0, r1, r2} -+ ldr r0, 1f -+ adr r1, 1f -+ add r0, r1 -+ str r0, [sp, #8] -+ @ We know we are not on armv4t, so pop pc is safe. -+ pop {r0, r1, pc} -+ .align 2 -+1: -+ .word __aeabi_ldiv0 - 1b -+7: -+.endm -+ - #ifdef L_aeabi_ldivmod + /* TARGET_BIG_ENDIAN_DEFAULT is set in + config.gcc for big endian configurations. */ +@@ -53,6 +53,8 @@ - FUNC_START aeabi_ldivmod -+ test_div_by_zero signed -+ - push {r0, r1} - mov r0, sp - push {r0, lr} -@@ -89,6 +132,8 @@ - #ifdef L_aeabi_uldivmod + #define TARGET_FIX_V4BX_SPEC " %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*|march=armv4:--fix-v4bx}" - FUNC_START aeabi_uldivmod -+ test_div_by_zero unsigned ++#define BE8_LINK_SPEC " %{mbig-endian:%{march=armv7-a|mcpu=cortex-a5|mcpu=cortex-a8|mcpu=cortex-a9:%{!r:--be8}}}" + - push {r0, r1} - mov r0, sp - push {r0, lr} -diff -Nur a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md ---- a/gcc/config/arm/constraints.md 2009-02-20 16:20:38.000000000 +0100 -+++ b/gcc/config/arm/constraints.md 2010-01-25 09:50:28.985687200 +0100 + /* Tell the assembler to build BPABI binaries. */ + #undef SUBTARGET_EXTRA_ASM_SPEC + #define SUBTARGET_EXTRA_ASM_SPEC "%{mabi=apcs-gnu|mabi=atpcs:-meabi=gnu;:-meabi=5}" TARGET_FIX_V4BX_SPEC +@@ -65,7 +67,7 @@ + #define BPABI_LINK_SPEC \ + "%{mbig-endian:-EB} %{mlittle-endian:-EL} " \ + "%{static:-Bstatic} %{shared:-shared} %{symbolic:-Bsymbolic} " \ +- "-X" SUBTARGET_EXTRA_LINK_SPEC TARGET_FIX_V4BX_SPEC ++ "-X" SUBTARGET_EXTRA_LINK_SPEC TARGET_FIX_V4BX_SPEC BE8_LINK_SPEC + + #undef LINK_SPEC + #define LINK_SPEC BPABI_LINK_SPEC +@@ -90,16 +92,22 @@ + #define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (muldi3, lmul) + #endif + #ifdef L_fixdfdi +-#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixdfdi, d2lz) ++#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixdfdi, d2lz) \ ++ extern DWtype __fixdfdi (DFtype) __attribute__((pcs("aapcs"))); \ ++ extern UDWtype __fixunsdfdi (DFtype) __asm__("__aeabi_d2ulz") __attribute__((pcs("aapcs"))); + #endif + #ifdef L_fixunsdfdi +-#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixunsdfdi, d2ulz) ++#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixunsdfdi, d2ulz) \ ++ extern UDWtype __fixunsdfdi (DFtype) __attribute__((pcs("aapcs"))); + #endif + #ifdef L_fixsfdi +-#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixsfdi, f2lz) ++#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixsfdi, f2lz) \ ++ extern DWtype __fixsfdi (SFtype) __attribute__((pcs("aapcs"))); \ ++ extern UDWtype __fixunssfdi (SFtype) __asm__("__aeabi_f2ulz") __attribute__((pcs("aapcs"))); + #endif + #ifdef L_fixunssfdi +-#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixunssfdi, f2ulz) ++#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixunssfdi, f2ulz) \ ++ extern UDWtype __fixunssfdi (SFtype) __attribute__((pcs("aapcs"))); + #endif + #ifdef L_floatdidf + #define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (floatdidf, l2d) +--- a/gcc/config/arm/constraints.md ++++ b/gcc/config/arm/constraints.md @@ -25,14 +25,15 @@ ;; In ARM state, 'l' is an alias for 'r' @@ -7473,9 +7958,8 @@ diff -Nur a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md (define_memory_constraint "Uq" "@internal -diff -Nur a/gcc/config/arm/fp16.c b/gcc/config/arm/fp16.c ---- a/gcc/config/arm/fp16.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/gcc/config/arm/fp16.c 2010-01-25 09:50:28.985687200 +0100 +--- /dev/null ++++ b/gcc/config/arm/fp16.c @@ -0,0 +1,145 @@ +/* Half-float conversion routines. + @@ -7622,9 +8106,8 @@ diff -Nur a/gcc/config/arm/fp16.c b/gcc/config/arm/fp16.c +{ + return __gnu_h2f_internal(a, 0); +} -diff -Nur a/gcc/config/arm/fpa.md b/gcc/config/arm/fpa.md ---- a/gcc/config/arm/fpa.md 2007-08-02 12:49:31.000000000 +0200 -+++ b/gcc/config/arm/fpa.md 2010-01-25 09:50:28.985687200 +0100 +--- a/gcc/config/arm/fpa.md ++++ b/gcc/config/arm/fpa.md @@ -599,10 +599,10 @@ { default: @@ -7638,9 +8121,8 @@ diff -Nur a/gcc/config/arm/fpa.md b/gcc/config/arm/fpa.md return \"stf%?e\\t%1, %0\"; return \"sfm%?\\t%1, 1, %0\"; } -diff -Nur a/gcc/config/arm/hwdiv.md b/gcc/config/arm/hwdiv.md ---- a/gcc/config/arm/hwdiv.md 1970-01-01 01:00:00.000000000 +0100 -+++ b/gcc/config/arm/hwdiv.md 2010-01-25 09:50:28.985687200 +0100 +--- /dev/null ++++ b/gcc/config/arm/hwdiv.md @@ -0,0 +1,41 @@ +;; ARM instruction patterns for hardware division +;; Copyright (C) 2005, 2006, 2007 Free Software Foundation, Inc. @@ -7683,10 +8165,9 @@ diff -Nur a/gcc/config/arm/hwdiv.md b/gcc/config/arm/hwdiv.md + (set_attr "insn" "udiv")] +) + -diff -Nur a/gcc/config/arm/ieee754-df.S b/gcc/config/arm/ieee754-df.S ---- a/gcc/config/arm/ieee754-df.S 2009-04-10 01:23:07.000000000 +0200 -+++ b/gcc/config/arm/ieee754-df.S 2010-01-25 09:50:28.985687200 +0100 -@@ -83,7 +83,7 @@ +--- a/gcc/config/arm/ieee754-df.S ++++ b/gcc/config/arm/ieee754-df.S +@@ -83,7 +83,7 @@ ARM_FUNC_ALIAS aeabi_dsub subdf3 ARM_FUNC_START adddf3 ARM_FUNC_ALIAS aeabi_dadd adddf3 @@ -7695,7 +8176,7 @@ diff -Nur a/gcc/config/arm/ieee754-df.S b/gcc/config/arm/ieee754-df.S @ Look for zeroes, equal values, INF, or NAN. shift1 lsl, r4, xh, #1 -@@ -427,7 +427,7 @@ +@@ -427,7 +427,7 @@ ARM_FUNC_ALIAS aeabi_ui2d floatunsidf do_it eq, t moveq r1, #0 RETc(eq) @@ -7704,7 +8185,7 @@ diff -Nur a/gcc/config/arm/ieee754-df.S b/gcc/config/arm/ieee754-df.S mov r4, #0x400 @ initial exponent add r4, r4, #(52-1 - 1) mov r5, #0 @ sign bit is 0 -@@ -447,7 +447,7 @@ +@@ -447,7 +447,7 @@ ARM_FUNC_ALIAS aeabi_i2d floatsidf do_it eq, t moveq r1, #0 RETc(eq) @@ -7713,7 +8194,7 @@ diff -Nur a/gcc/config/arm/ieee754-df.S b/gcc/config/arm/ieee754-df.S mov r4, #0x400 @ initial exponent add r4, r4, #(52-1 - 1) ands r5, r0, #0x80000000 @ sign bit in r5 -@@ -481,7 +481,7 @@ +@@ -481,7 +481,7 @@ ARM_FUNC_ALIAS aeabi_f2d extendsfdf2 RETc(eq) @ we are done already. @ value was denormalized. We can normalize it now. @@ -7722,7 +8203,7 @@ diff -Nur a/gcc/config/arm/ieee754-df.S b/gcc/config/arm/ieee754-df.S mov r4, #0x380 @ setup corresponding exponent and r5, xh, #0x80000000 @ move sign bit in r5 bic xh, xh, #0x80000000 -@@ -508,9 +508,9 @@ +@@ -508,9 +508,9 @@ ARM_FUNC_ALIAS aeabi_ul2d floatundidf @ compatibility. adr ip, LSYM(f0_ret) @ Push pc as well so that RETLDM works correctly. @@ -7734,7 +8215,7 @@ diff -Nur a/gcc/config/arm/ieee754-df.S b/gcc/config/arm/ieee754-df.S #endif mov r5, #0 -@@ -534,9 +534,9 @@ +@@ -534,9 +534,9 @@ ARM_FUNC_ALIAS aeabi_l2d floatdidf @ compatibility. adr ip, LSYM(f0_ret) @ Push pc as well so that RETLDM works correctly. @@ -7746,7 +8227,7 @@ diff -Nur a/gcc/config/arm/ieee754-df.S b/gcc/config/arm/ieee754-df.S #endif ands r5, ah, #0x80000000 @ sign bit in r5 -@@ -585,7 +585,7 @@ +@@ -585,7 +585,7 @@ ARM_FUNC_ALIAS aeabi_l2d floatdidf @ Legacy code expects the result to be returned in f0. Copy it @ there as well. LSYM(f0_ret): @@ -7755,7 +8236,7 @@ diff -Nur a/gcc/config/arm/ieee754-df.S b/gcc/config/arm/ieee754-df.S ldfd f0, [sp], #8 RETLDM -@@ -602,7 +602,7 @@ +@@ -602,7 +602,7 @@ LSYM(f0_ret): ARM_FUNC_START muldf3 ARM_FUNC_ALIAS aeabi_dmul muldf3 @@ -7764,7 +8245,7 @@ diff -Nur a/gcc/config/arm/ieee754-df.S b/gcc/config/arm/ieee754-df.S @ Mask out exponents, trap any zero/denormal/INF/NAN. mov ip, #0xff -@@ -910,7 +910,7 @@ +@@ -910,7 +910,7 @@ LSYM(Lml_n): ARM_FUNC_START divdf3 ARM_FUNC_ALIAS aeabi_ddiv divdf3 @@ -7773,35 +8254,7 @@ diff -Nur a/gcc/config/arm/ieee754-df.S b/gcc/config/arm/ieee754-df.S @ Mask out exponents, trap any zero/denormal/INF/NAN. mov ip, #0xff -@@ -1117,7 +1117,7 @@ - ARM_FUNC_ALIAS eqdf2 cmpdf2 - mov ip, #1 @ how should we specify unordered here? - --1: str ip, [sp, #-4] -+1: str ip, [sp, #-4]! - - @ Trap any INF/NAN first. - mov ip, xh, lsl #1 -@@ -1129,7 +1129,8 @@ - - @ Test for equality. - @ Note that 0.0 is equal to -0.0. --2: orrs ip, xl, xh, lsl #1 @ if x == 0.0 or -0.0 -+2: add sp, sp, #4 -+ orrs ip, xl, xh, lsl #1 @ if x == 0.0 or -0.0 - do_it eq, e - COND(orr,s,eq) ip, yl, yh, lsl #1 @ and y == 0.0 or -0.0 - teqne xh, yh @ or xh == yh -@@ -1168,7 +1169,7 @@ - bne 2b - orrs ip, yl, yh, lsl #12 - beq 2b @ y is not NAN --5: ldr r0, [sp, #-4] @ unordered return code -+5: ldr r0, [sp], #4 @ unordered return code - RET - - FUNC_END gedf2 -@@ -1194,7 +1195,7 @@ +@@ -1195,7 +1195,7 @@ ARM_FUNC_ALIAS aeabi_cdcmple aeabi_cdcmp @ The status-returning routines are required to preserve all @ registers except ip, lr, and cpsr. @@ -7810,10 +8263,9 @@ diff -Nur a/gcc/config/arm/ieee754-df.S b/gcc/config/arm/ieee754-df.S ARM_CALL cmpdf2 @ Set the Z flag correctly, and the C flag unconditionally. cmp r0, #0 -diff -Nur a/gcc/config/arm/ieee754-sf.S b/gcc/config/arm/ieee754-sf.S ---- a/gcc/config/arm/ieee754-sf.S 2009-04-10 01:23:07.000000000 +0200 -+++ b/gcc/config/arm/ieee754-sf.S 2010-01-25 09:50:28.985687200 +0100 -@@ -481,7 +481,7 @@ +--- a/gcc/config/arm/ieee754-sf.S ++++ b/gcc/config/arm/ieee754-sf.S +@@ -481,7 +481,7 @@ LSYM(Lml_x): and r3, ip, #0x80000000 @ Well, no way to make it shorter without the umull instruction. @@ -7822,7 +8274,7 @@ diff -Nur a/gcc/config/arm/ieee754-sf.S b/gcc/config/arm/ieee754-sf.S mov r4, r0, lsr #16 mov r5, r1, lsr #16 bic r0, r0, r4, lsl #16 -@@ -492,7 +492,7 @@ +@@ -492,7 +492,7 @@ LSYM(Lml_x): mla r0, r4, r1, r0 adds r3, r3, r0, lsl #16 adc r1, ip, r0, lsr #16 @@ -7831,35 +8283,7 @@ diff -Nur a/gcc/config/arm/ieee754-sf.S b/gcc/config/arm/ieee754-sf.S #else -@@ -822,7 +822,7 @@ - ARM_FUNC_ALIAS eqsf2 cmpsf2 - mov ip, #1 @ how should we specify unordered here? - --1: str ip, [sp, #-4] -+1: str ip, [sp, #-4]! - - @ Trap any INF/NAN first. - mov r2, r0, lsl #1 -@@ -834,7 +834,8 @@ - - @ Compare values. - @ Note that 0.0 is equal to -0.0. --2: orrs ip, r2, r3, lsr #1 @ test if both are 0, clear C flag -+2: add sp, sp, #4 -+ orrs ip, r2, r3, lsr #1 @ test if both are 0, clear C flag - do_it ne - teqne r0, r1 @ if not 0 compare sign - do_it pl -@@ -858,7 +859,7 @@ - bne 2b - movs ip, r1, lsl #9 - beq 2b @ r1 is not NAN --5: ldr r0, [sp, #-4] @ return unordered code. -+5: ldr r0, [sp], #4 @ return unordered code. - RET - - FUNC_END gesf2 -@@ -881,7 +882,7 @@ +@@ -882,7 +882,7 @@ ARM_FUNC_ALIAS aeabi_cfcmple aeabi_cfcmp @ The status-returning routines are required to preserve all @ registers except ip, lr, and cpsr. @@ -7868,10 +8292,9 @@ diff -Nur a/gcc/config/arm/ieee754-sf.S b/gcc/config/arm/ieee754-sf.S ARM_CALL cmpsf2 @ Set the Z flag correctly, and the C flag unconditionally. cmp r0, #0 -diff -Nur a/gcc/config/arm/lib1funcs.asm b/gcc/config/arm/lib1funcs.asm ---- a/gcc/config/arm/lib1funcs.asm 2009-04-10 01:23:07.000000000 +0200 -+++ b/gcc/config/arm/lib1funcs.asm 2010-01-25 09:50:28.985687200 +0100 -@@ -27,8 +27,17 @@ +--- a/gcc/config/arm/lib1funcs.asm ++++ b/gcc/config/arm/lib1funcs.asm +@@ -27,8 +27,17 @@ see the files COPYING3 and COPYING.RUNTI #if defined(__ELF__) && defined(__linux__) .section .note.GNU-stack,"",%progbits .previous @@ -7890,7 +8313,7 @@ diff -Nur a/gcc/config/arm/lib1funcs.asm b/gcc/config/arm/lib1funcs.asm /* ------------------------------------------------------------------------ */ /* We need to know what prefix to add to function names. */ -@@ -233,8 +242,8 @@ +@@ -233,8 +242,8 @@ LSYM(Lend_fde): .macro shift1 op, arg0, arg1, arg2 \op \arg0, \arg1, \arg2 .endm @@ -7901,7 +8324,7 @@ diff -Nur a/gcc/config/arm/lib1funcs.asm b/gcc/config/arm/lib1funcs.asm #define COND(op1, op2, cond) op1 ## op2 ## cond /* Perform an arithmetic operation with a variable shift operand. This requires two instructions and a scratch register on Thumb-2. */ -@@ -248,24 +257,133 @@ +@@ -248,24 +257,133 @@ LSYM(Lend_fde): .macro shift1 op, arg0, arg1, arg2 mov \arg0, \arg1, \op \arg2 .endm @@ -8039,7 +8462,7 @@ diff -Nur a/gcc/config/arm/lib1funcs.asm b/gcc/config/arm/lib1funcs.asm push { r1, lr } 98: cfi_push 98b - __\name, 0xe, -0x4, 0x8 bl SYM (__div0) -@@ -277,18 +395,19 @@ +@@ -277,18 +395,19 @@ LSYM(Lend_fde): pop { r1, pc } #endif .endm @@ -8062,7 +8485,7 @@ diff -Nur a/gcc/config/arm/lib1funcs.asm b/gcc/config/arm/lib1funcs.asm #endif cfi_end LSYM(Lend_div0) FUNC_END \name -@@ -413,6 +532,12 @@ +@@ -413,6 +532,12 @@ SYM (__\name): #define yyl r2 #endif @@ -8075,7 +8498,7 @@ diff -Nur a/gcc/config/arm/lib1funcs.asm b/gcc/config/arm/lib1funcs.asm #ifdef __thumb__ /* Register aliases. */ -@@ -437,6 +562,43 @@ +@@ -437,6 +562,43 @@ pc .req r15 #if __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__) @@ -8119,7 +8542,7 @@ diff -Nur a/gcc/config/arm/lib1funcs.asm b/gcc/config/arm/lib1funcs.asm clz \curbit, \dividend clz \result, \divisor sub \curbit, \result, \curbit -@@ -452,6 +614,7 @@ +@@ -452,6 +614,7 @@ pc .req r15 adc \result, \result, \result subcs \dividend, \dividend, \divisor, lsl #shift .endr @@ -8127,7 +8550,7 @@ diff -Nur a/gcc/config/arm/lib1funcs.asm b/gcc/config/arm/lib1funcs.asm #else /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ #if __ARM_ARCH__ >= 5 -@@ -499,18 +662,23 @@ +@@ -499,18 +662,23 @@ pc .req r15 @ Division loop 1: cmp \dividend, \divisor @@ -8151,7 +8574,7 @@ diff -Nur a/gcc/config/arm/lib1funcs.asm b/gcc/config/arm/lib1funcs.asm movnes \curbit, \curbit, lsr #4 @ No, any more bits to do? movne \divisor, \divisor, lsr #4 bne 1b -@@ -799,13 +967,14 @@ +@@ -799,13 +967,14 @@ LSYM(Lgot_result): /* ------------------------------------------------------------------------ */ #ifdef L_udivsi3 @@ -8168,7 +8591,7 @@ diff -Nur a/gcc/config/arm/lib1funcs.asm b/gcc/config/arm/lib1funcs.asm mov curbit, #1 mov result, #0 -@@ -819,9 +988,16 @@ +@@ -819,9 +988,16 @@ LSYM(Lgot_result): pop { work } RET @@ -8186,7 +8609,7 @@ diff -Nur a/gcc/config/arm/lib1funcs.asm b/gcc/config/arm/lib1funcs.asm RETc(eq) bcc LSYM(Ldiv0) cmp r0, r1 -@@ -834,7 +1010,8 @@ +@@ -834,7 +1010,8 @@ LSYM(Lgot_result): mov r0, r2 RET @@ -8196,7 +8619,7 @@ diff -Nur a/gcc/config/arm/lib1funcs.asm b/gcc/config/arm/lib1funcs.asm movne r0, #0 RET -@@ -845,19 +1022,24 @@ +@@ -845,19 +1022,24 @@ LSYM(Lgot_result): #endif /* ARM version */ @@ -8225,7 +8648,7 @@ diff -Nur a/gcc/config/arm/lib1funcs.asm b/gcc/config/arm/lib1funcs.asm ldmfd sp!, { r1, r2, lr } mul r3, r2, r0 sub r1, r1, r3 -@@ -904,19 +1086,20 @@ +@@ -904,19 +1086,20 @@ LSYM(Lover10): #endif /* ARM version. */ @@ -8249,7 +8672,7 @@ diff -Nur a/gcc/config/arm/lib1funcs.asm b/gcc/config/arm/lib1funcs.asm push { work } mov work, dividend eor work, divisor @ Save the sign of the result. -@@ -945,15 +1128,21 @@ +@@ -945,15 +1128,21 @@ LSYM(Lover12): pop { work } RET @@ -8273,7 +8696,7 @@ diff -Nur a/gcc/config/arm/lib1funcs.asm b/gcc/config/arm/lib1funcs.asm rsbmi r3, r0, #0 @ positive dividend value cmp r3, r1 bls 11f -@@ -963,14 +1152,18 @@ +@@ -963,14 +1152,18 @@ LSYM(Lover12): ARM_DIV_BODY r3, r1, r0, r2 cmp ip, #0 @@ -8293,7 +8716,7 @@ diff -Nur a/gcc/config/arm/lib1funcs.asm b/gcc/config/arm/lib1funcs.asm moveq r0, ip, asr #31 orreq r0, r0, #1 RET -@@ -979,24 +1172,30 @@ +@@ -979,24 +1172,30 @@ LSYM(Lover12): cmp ip, #0 mov r0, r3, lsr r2 @@ -8328,7 +8751,7 @@ diff -Nur a/gcc/config/arm/lib1funcs.asm b/gcc/config/arm/lib1funcs.asm ldmfd sp!, { r1, r2, lr } mul r3, r2, r0 sub r1, r1, r3 -@@ -1062,21 +1261,25 @@ +@@ -1062,21 +1261,25 @@ LSYM(Lover12): #endif /* ARM version */ @@ -8360,7 +8783,7 @@ diff -Nur a/gcc/config/arm/lib1funcs.asm b/gcc/config/arm/lib1funcs.asm #endif /* L_divmodsi_tools */ /* ------------------------------------------------------------------------ */ -@@ -1086,16 +1289,49 @@ +@@ -1086,16 +1289,49 @@ LSYM(Lover12): /* Constant taken from . */ #define SIGFPE 8 @@ -8411,7 +8834,7 @@ diff -Nur a/gcc/config/arm/lib1funcs.asm b/gcc/config/arm/lib1funcs.asm /* ------------------------------------------------------------------------ */ /* Dword shift operations. */ /* All the following Dword shift variants rely on the fact that -@@ -1292,7 +1528,7 @@ +@@ -1292,7 +1528,7 @@ FUNC_START clzdi2 push {r4, lr} # else ARM_FUNC_START clzdi2 @@ -8420,9 +8843,8 @@ diff -Nur a/gcc/config/arm/lib1funcs.asm b/gcc/config/arm/lib1funcs.asm # endif cmp xxh, #0 bne 1f -diff -Nur a/gcc/config/arm/linux-eabi.h b/gcc/config/arm/linux-eabi.h ---- a/gcc/config/arm/linux-eabi.h 2007-11-08 14:44:09.000000000 +0100 -+++ b/gcc/config/arm/linux-eabi.h 2010-01-25 09:50:28.995687913 +0100 +--- a/gcc/config/arm/linux-eabi.h ++++ b/gcc/config/arm/linux-eabi.h @@ -66,22 +66,14 @@ /* At this point, bpabi.h will have clobbered LINK_SPEC. We want to use the GNU/Linux version, not the generic BPABI version. */ @@ -8451,9 +8873,8 @@ diff -Nur a/gcc/config/arm/linux-eabi.h b/gcc/config/arm/linux-eabi.h - : "0" (_beg), "r" (_end), "r" (_flg), "r" (_scno)); \ -} +#define CLEAR_INSN_CACHE(BEG, END) not used -diff -Nur a/gcc/config/arm/linux-elf.h b/gcc/config/arm/linux-elf.h ---- a/gcc/config/arm/linux-elf.h 2009-02-20 16:20:38.000000000 +0100 -+++ b/gcc/config/arm/linux-elf.h 2010-01-25 09:50:28.995687913 +0100 +--- a/gcc/config/arm/linux-elf.h ++++ b/gcc/config/arm/linux-elf.h @@ -98,7 +98,7 @@ /* NWFPE always understands FPA instructions. */ @@ -8463,9 +8884,164 @@ diff -Nur a/gcc/config/arm/linux-elf.h b/gcc/config/arm/linux-elf.h /* Call the function profiler with a given profile label. */ #undef ARM_FUNCTION_PROFILER -diff -Nur a/gcc/config/arm/marvell-f.md b/gcc/config/arm/marvell-f.md ---- a/gcc/config/arm/marvell-f.md 1970-01-01 01:00:00.000000000 +0100 -+++ b/gcc/config/arm/marvell-f.md 2010-01-25 09:50:28.995687913 +0100 +--- /dev/null ++++ b/gcc/config/arm/marvell-f-vfp.md +@@ -0,0 +1,153 @@ ++;; Marvell 2850 VFP pipeline description ++;; Copyright (C) 2007 Free Software Foundation, Inc. ++;; Written by CodeSourcery, Inc. ++ ++;; This file is part of GCC. ++ ++;; GCC is distributed in the hope that it will be useful, but WITHOUT ++;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++;; License for more details. ++ ++;; You should have received a copy of the GNU General Public License ++;; along with GCC; see the file COPYING. If not, write to ++;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, ++;; Boston, MA 02110-1301, USA. ++ ++;; This automaton provides a pipeline description for the Marvell ++;; 2850 core. ++;; ++;; The model given here assumes that the condition for all conditional ++;; instructions is "true", i.e., that all of the instructions are ++;; actually executed. ++ ++(define_automaton "marvell_f_vfp") ++ ++;; This is a single-issue VFPv2 implementation with the following execution ++;; units: ++;; ++;; 1. Addition/subtraction unit; takes three cycles, pipelined. ++;; 2. Multiplication unit; takes four cycles, pipelined. ++;; 3. Add buffer, used for multiply-accumulate (see below). ++;; 4. Divide/square root unit, not pipelined. ++;; For single-precision: takes sixteen cycles, can accept another insn ++;; after fifteen cycles. ++;; For double-precision: takes thirty-one cycles, can accept another insn ++;; after thirty cycles. ++;; 5. Single-cycle unit, pipelined. ++;; This does absolute value/copy/negate/compare in one cycle and ++;; conversion in two cycles. ++;; ++;; When all three operands of a multiply-accumulate instruction are ready, ++;; one is issued to the add buffer (which can hold six operands in a FIFO) ++;; and the two to be multiplied are issued to the multiply unit. After ++;; four cycles in the multiply unit, one cycle is taken to issue the ++;; operand from the add buffer plus the multiplication result to the ++;; addition/subtraction unit. That issue takes priority over any add/sub ++;; instruction waiting at the normal issue stage, but may be performed in ++;; parallel with the issue of a non-add/sub instruction. The total time ++;; for a multiply-accumulate instruction to pass through the execution ++;; units is hence eight cycles. ++;; ++;; We do not need to explicitly model the add buffer because it can ++;; always issue the instruction at the head of its FIFO (due to the above ++;; priority rule) and there are more spaces in the add buffer (six) than ++;; there are stages (four) in the multiplication unit. ++;; ++;; Two instructions may be retired at once from the head of an 8-entry ++;; reorder buffer. Data from these first two instructions only may be ++;; forwarded to the inputs of the issue unit. We assume that the ++;; pressure on the reorder buffer will be sufficiently low that every ++;; instruction entering it will be eligible for data forwarding. Since ++;; data is forwarded to the issue unit and not the execution units (so ++;; for example single-cycle instructions cannot be issued back-to-back), ++;; the latencies given below are the cycle counts above plus one. ++ ++(define_cpu_unit "mf_vfp_issue" "marvell_f_vfp") ++(define_cpu_unit "mf_vfp_add" "marvell_f_vfp") ++(define_cpu_unit "mf_vfp_mul" "marvell_f_vfp") ++(define_cpu_unit "mf_vfp_div" "marvell_f_vfp") ++(define_cpu_unit "mf_vfp_single_cycle" "marvell_f_vfp") ++ ++;; An attribute to indicate whether our reservations are applicable. ++ ++(define_attr "marvell_f_vfp" "yes,no" ++ (const (if_then_else (and (eq_attr "tune" "marvell_f") ++ (eq_attr "fpu" "vfp")) ++ (const_string "yes") (const_string "no")))) ++ ++;; Reservations of functional units. The nothing*2 reservations at the ++;; start of many of the reservation strings correspond to the decode ++;; stages. We need to have these reservations so that we can correctly ++;; reserve parts of the core's A1 pipeline for loads and stores. For ++;; that case (since loads skip E1) the pipelines line up thus: ++;; A1 pipe: Issue E2 OF WR WB ... ++;; VFP pipe: Fetch Decode1 Decode2 Issue Execute1 ... ++;; For a load, we need to make a reservation of E2, and thus we must ++;; use Decode1 as the starting point for all VFP reservations here. ++;; ++;; For reservations of pipelined VFP execution units we only reserve ++;; the execution unit for the first execution cycle, omitting any trailing ++;; "nothing" reservations. ++ ++(define_insn_reservation "marvell_f_vfp_add" 4 ++ (and (eq_attr "marvell_f_vfp" "yes") ++ (eq_attr "type" "farith")) ++ "nothing*2,mf_vfp_issue,mf_vfp_add") ++ ++(define_insn_reservation "marvell_f_vfp_mul" 5 ++ (and (eq_attr "marvell_f_vfp" "yes") ++ (eq_attr "type" "fmuls,fmuld")) ++ "nothing*2,mf_vfp_issue,mf_vfp_mul") ++ ++(define_insn_reservation "marvell_f_vfp_divs" 17 ++ (and (eq_attr "marvell_f_vfp" "yes") ++ (eq_attr "type" "fdivs")) ++ "nothing*2,mf_vfp_issue,mf_vfp_div*15") ++ ++(define_insn_reservation "marvell_f_vfp_divd" 32 ++ (and (eq_attr "marvell_f_vfp" "yes") ++ (eq_attr "type" "fdivd")) ++ "nothing*2,mf_vfp_issue,mf_vfp_div*30") ++ ++;; The DFA lookahead is small enough that the "add" reservation here ++;; will always take priority over any addition/subtraction instruction ++;; issued five cycles after the multiply-accumulate instruction, as ++;; required. ++(define_insn_reservation "marvell_f_vfp_mac" 9 ++ (and (eq_attr "marvell_f_vfp" "yes") ++ (eq_attr "type" "fmacs,fmacd")) ++ "nothing*2,mf_vfp_issue,mf_vfp_mul,nothing*4,mf_vfp_add") ++ ++(define_insn_reservation "marvell_f_vfp_single" 2 ++ (and (eq_attr "marvell_f_vfp" "yes") ++ (eq_attr "type" "ffarith")) ++ "nothing*2,mf_vfp_issue,mf_vfp_single_cycle") ++ ++(define_insn_reservation "marvell_f_vfp_convert" 3 ++ (and (eq_attr "marvell_f_vfp" "yes") ++ (eq_attr "type" "f_cvt")) ++ "nothing*2,mf_vfp_issue,mf_vfp_single_cycle") ++ ++(define_insn_reservation "marvell_f_vfp_load" 2 ++ (and (eq_attr "marvell_f_vfp" "yes") ++ (eq_attr "type" "f_loads,f_loadd")) ++ "a1_e2+sram,a1_of,a1_wr+mf_vfp_issue,a1_wb+mf_vfp_single_cycle") ++ ++(define_insn_reservation "marvell_f_vfp_from_core" 2 ++ (and (eq_attr "marvell_f_vfp" "yes") ++ (eq_attr "type" "r_2_f")) ++ "a1_e2,a1_of,a1_wr+mf_vfp_issue,a1_wb+mf_vfp_single_cycle") ++ ++;; The interaction between the core and VFP pipelines during VFP ++;; store operations and core <-> VFP moves is not clear, so we guess. ++(define_insn_reservation "marvell_f_vfp_store" 3 ++ (and (eq_attr "marvell_f_vfp" "yes") ++ (eq_attr "type" "f_stores,f_stored")) ++ "a1_e2,a1_of,mf_vfp_issue,a1_wr+sram+mf_vfp_single_cycle") ++ ++(define_insn_reservation "marvell_f_vfp_to_core" 4 ++ (and (eq_attr "marvell_f_vfp" "yes") ++ (eq_attr "type" "f_2_r")) ++ "a1_e2,a1_of,a1_wr+mf_vfp_issue,a1_wb+mf_vfp_single_cycle") ++ +--- /dev/null ++++ b/gcc/config/arm/marvell-f.md @@ -0,0 +1,365 @@ +;; Marvell 2850 pipeline description +;; Copyright (C) 2005, 2006, 2007 Free Software Foundation, Inc. @@ -8832,204 +9408,9 @@ diff -Nur a/gcc/config/arm/marvell-f.md b/gcc/config/arm/marvell-f.md + (eq_attr "type" "store3,store4")) + "a1_e1,a1_e1+a1_e2,a1_e2+a1_of,a1_of+a1_wr+sram,a1_wr+sram+a1_wb,a1_wb") + -diff -Nur a/gcc/config/arm/marvell-f-vfp.md b/gcc/config/arm/marvell-f-vfp.md ---- a/gcc/config/arm/marvell-f-vfp.md 1970-01-01 01:00:00.000000000 +0100 -+++ b/gcc/config/arm/marvell-f-vfp.md 2010-01-25 09:50:28.995687913 +0100 -@@ -0,0 +1,153 @@ -+;; Marvell 2850 VFP pipeline description -+;; Copyright (C) 2007 Free Software Foundation, Inc. -+;; Written by CodeSourcery, Inc. -+ -+;; This file is part of GCC. -+ -+;; GCC is distributed in the hope that it will be useful, but WITHOUT -+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+;; License for more details. -+ -+;; You should have received a copy of the GNU General Public License -+;; along with GCC; see the file COPYING. If not, write to -+;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, -+;; Boston, MA 02110-1301, USA. -+ -+;; This automaton provides a pipeline description for the Marvell -+;; 2850 core. -+;; -+;; The model given here assumes that the condition for all conditional -+;; instructions is "true", i.e., that all of the instructions are -+;; actually executed. -+ -+(define_automaton "marvell_f_vfp") -+ -+;; This is a single-issue VFPv2 implementation with the following execution -+;; units: -+;; -+;; 1. Addition/subtraction unit; takes three cycles, pipelined. -+;; 2. Multiplication unit; takes four cycles, pipelined. -+;; 3. Add buffer, used for multiply-accumulate (see below). -+;; 4. Divide/square root unit, not pipelined. -+;; For single-precision: takes sixteen cycles, can accept another insn -+;; after fifteen cycles. -+;; For double-precision: takes thirty-one cycles, can accept another insn -+;; after thirty cycles. -+;; 5. Single-cycle unit, pipelined. -+;; This does absolute value/copy/negate/compare in one cycle and -+;; conversion in two cycles. -+;; -+;; When all three operands of a multiply-accumulate instruction are ready, -+;; one is issued to the add buffer (which can hold six operands in a FIFO) -+;; and the two to be multiplied are issued to the multiply unit. After -+;; four cycles in the multiply unit, one cycle is taken to issue the -+;; operand from the add buffer plus the multiplication result to the -+;; addition/subtraction unit. That issue takes priority over any add/sub -+;; instruction waiting at the normal issue stage, but may be performed in -+;; parallel with the issue of a non-add/sub instruction. The total time -+;; for a multiply-accumulate instruction to pass through the execution -+;; units is hence eight cycles. -+;; -+;; We do not need to explicitly model the add buffer because it can -+;; always issue the instruction at the head of its FIFO (due to the above -+;; priority rule) and there are more spaces in the add buffer (six) than -+;; there are stages (four) in the multiplication unit. -+;; -+;; Two instructions may be retired at once from the head of an 8-entry -+;; reorder buffer. Data from these first two instructions only may be -+;; forwarded to the inputs of the issue unit. We assume that the -+;; pressure on the reorder buffer will be sufficiently low that every -+;; instruction entering it will be eligible for data forwarding. Since -+;; data is forwarded to the issue unit and not the execution units (so -+;; for example single-cycle instructions cannot be issued back-to-back), -+;; the latencies given below are the cycle counts above plus one. -+ -+(define_cpu_unit "mf_vfp_issue" "marvell_f_vfp") -+(define_cpu_unit "mf_vfp_add" "marvell_f_vfp") -+(define_cpu_unit "mf_vfp_mul" "marvell_f_vfp") -+(define_cpu_unit "mf_vfp_div" "marvell_f_vfp") -+(define_cpu_unit "mf_vfp_single_cycle" "marvell_f_vfp") -+ -+;; An attribute to indicate whether our reservations are applicable. -+ -+(define_attr "marvell_f_vfp" "yes,no" -+ (const (if_then_else (and (eq_attr "tune" "marvell_f") -+ (eq_attr "fpu" "vfp")) -+ (const_string "yes") (const_string "no")))) -+ -+;; Reservations of functional units. The nothing*2 reservations at the -+;; start of many of the reservation strings correspond to the decode -+;; stages. We need to have these reservations so that we can correctly -+;; reserve parts of the core's A1 pipeline for loads and stores. For -+;; that case (since loads skip E1) the pipelines line up thus: -+;; A1 pipe: Issue E2 OF WR WB ... -+;; VFP pipe: Fetch Decode1 Decode2 Issue Execute1 ... -+;; For a load, we need to make a reservation of E2, and thus we must -+;; use Decode1 as the starting point for all VFP reservations here. -+;; -+;; For reservations of pipelined VFP execution units we only reserve -+;; the execution unit for the first execution cycle, omitting any trailing -+;; "nothing" reservations. -+ -+(define_insn_reservation "marvell_f_vfp_add" 4 -+ (and (eq_attr "marvell_f_vfp" "yes") -+ (eq_attr "type" "farith")) -+ "nothing*2,mf_vfp_issue,mf_vfp_add") -+ -+(define_insn_reservation "marvell_f_vfp_mul" 5 -+ (and (eq_attr "marvell_f_vfp" "yes") -+ (eq_attr "type" "fmuls,fmuld")) -+ "nothing*2,mf_vfp_issue,mf_vfp_mul") -+ -+(define_insn_reservation "marvell_f_vfp_divs" 17 -+ (and (eq_attr "marvell_f_vfp" "yes") -+ (eq_attr "type" "fdivs")) -+ "nothing*2,mf_vfp_issue,mf_vfp_div*15") -+ -+(define_insn_reservation "marvell_f_vfp_divd" 32 -+ (and (eq_attr "marvell_f_vfp" "yes") -+ (eq_attr "type" "fdivd")) -+ "nothing*2,mf_vfp_issue,mf_vfp_div*30") -+ -+;; The DFA lookahead is small enough that the "add" reservation here -+;; will always take priority over any addition/subtraction instruction -+;; issued five cycles after the multiply-accumulate instruction, as -+;; required. -+(define_insn_reservation "marvell_f_vfp_mac" 9 -+ (and (eq_attr "marvell_f_vfp" "yes") -+ (eq_attr "type" "fmacs,fmacd")) -+ "nothing*2,mf_vfp_issue,mf_vfp_mul,nothing*4,mf_vfp_add") -+ -+(define_insn_reservation "marvell_f_vfp_single" 2 -+ (and (eq_attr "marvell_f_vfp" "yes") -+ (eq_attr "type" "ffarith")) -+ "nothing*2,mf_vfp_issue,mf_vfp_single_cycle") -+ -+(define_insn_reservation "marvell_f_vfp_convert" 3 -+ (and (eq_attr "marvell_f_vfp" "yes") -+ (eq_attr "type" "f_cvt")) -+ "nothing*2,mf_vfp_issue,mf_vfp_single_cycle") -+ -+(define_insn_reservation "marvell_f_vfp_load" 2 -+ (and (eq_attr "marvell_f_vfp" "yes") -+ (eq_attr "type" "f_loads,f_loadd")) -+ "a1_e2+sram,a1_of,a1_wr+mf_vfp_issue,a1_wb+mf_vfp_single_cycle") -+ -+(define_insn_reservation "marvell_f_vfp_from_core" 2 -+ (and (eq_attr "marvell_f_vfp" "yes") -+ (eq_attr "type" "r_2_f")) -+ "a1_e2,a1_of,a1_wr+mf_vfp_issue,a1_wb+mf_vfp_single_cycle") -+ -+;; The interaction between the core and VFP pipelines during VFP -+;; store operations and core <-> VFP moves is not clear, so we guess. -+(define_insn_reservation "marvell_f_vfp_store" 3 -+ (and (eq_attr "marvell_f_vfp" "yes") -+ (eq_attr "type" "f_stores,f_stored")) -+ "a1_e2,a1_of,mf_vfp_issue,a1_wr+sram+mf_vfp_single_cycle") -+ -+(define_insn_reservation "marvell_f_vfp_to_core" 4 -+ (and (eq_attr "marvell_f_vfp" "yes") -+ (eq_attr "type" "f_2_r")) -+ "a1_e2,a1_of,a1_wr+mf_vfp_issue,a1_wb+mf_vfp_single_cycle") -+ -diff -Nur a/gcc/config/arm/montavista-linux.h b/gcc/config/arm/montavista-linux.h ---- a/gcc/config/arm/montavista-linux.h 1970-01-01 01:00:00.000000000 +0100 -+++ b/gcc/config/arm/montavista-linux.h 2010-01-25 09:50:28.995687913 +0100 -@@ -0,0 +1,33 @@ -+/* MontaVista GNU/Linux Configuration. -+ Copyright (C) 2009 -+ Free Software Foundation, Inc. -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 3, or (at your option) -+any later version. -+ -+GCC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GCC; see the file COPYING3. If not see -+. */ -+ -+/* Add -tarmv6 and -tthumb2 options for convenience in generating multilibs. -+*/ -+#undef CC1_SPEC -+#define CC1_SPEC " \ -+ %{tarmv6: -march=armv6 -mfloat-abi=softfp ; \ -+ tthumb2: -mthumb -march=armv7-a -mfloat-abi=softfp ; \ -+ : -march=armv5t}" -+ -+/* The various C libraries each have their own subdirectory. */ -+#undef SYSROOT_SUFFIX_SPEC -+#define SYSROOT_SUFFIX_SPEC \ -+ "%{tarmv6:/armv6 ; \ -+ tthumb2:/thumb2}" -diff -Nur a/gcc/config/arm/neon-gen.ml b/gcc/config/arm/neon-gen.ml ---- a/gcc/config/arm/neon-gen.ml 2009-04-10 01:23:07.000000000 +0200 -+++ b/gcc/config/arm/neon-gen.ml 2010-01-25 09:50:28.995687913 +0100 -@@ -122,6 +122,7 @@ +--- a/gcc/config/arm/neon-gen.ml ++++ b/gcc/config/arm/neon-gen.ml +@@ -122,6 +122,7 @@ let rec signed_ctype = function | T_uint16 | T_int16 -> T_intHI | T_uint32 | T_int32 -> T_intSI | T_uint64 | T_int64 -> T_intDI @@ -9037,7 +9418,7 @@ diff -Nur a/gcc/config/arm/neon-gen.ml b/gcc/config/arm/neon-gen.ml | T_poly8 -> T_intQI | T_poly16 -> T_intHI | T_arrayof (n, elt) -> T_arrayof (n, signed_ctype elt) -@@ -320,7 +321,7 @@ +@@ -320,7 +321,7 @@ let deftypes () = typeinfo; Format.print_newline (); (* Extra types not in . *) @@ -9046,7 +9427,7 @@ diff -Nur a/gcc/config/arm/neon-gen.ml b/gcc/config/arm/neon-gen.ml Format.printf "typedef __builtin_neon_poly8 poly8_t;\n"; Format.printf "typedef __builtin_neon_poly16 poly16_t;\n" -@@ -399,7 +400,11 @@ +@@ -399,7 +400,11 @@ let _ = "extern \"C\" {"; "#endif"; ""; @@ -9058,9 +9439,21 @@ diff -Nur a/gcc/config/arm/neon-gen.ml b/gcc/config/arm/neon-gen.ml ""]; deftypes (); arrtypes (); -diff -Nur a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md ---- a/gcc/config/arm/neon.md 2009-02-20 16:20:38.000000000 +0100 -+++ b/gcc/config/arm/neon.md 2010-01-25 09:50:28.995687913 +0100 +--- a/gcc/config/arm/neon-testgen.ml ++++ b/gcc/config/arm/neon-testgen.ml +@@ -51,8 +51,8 @@ let emit_prologue chan test_name = + Printf.fprintf chan "/* This file was autogenerated by neon-testgen. */\n\n"; + Printf.fprintf chan "/* { dg-do assemble } */\n"; + Printf.fprintf chan "/* { dg-require-effective-target arm_neon_ok } */\n"; +- Printf.fprintf chan +- "/* { dg-options \"-save-temps -O0 -mfpu=neon -mfloat-abi=softfp\" } */\n"; ++ Printf.fprintf chan "/* { dg-options \"-save-temps -O0\" } */\n"; ++ Printf.fprintf chan "/* { dg-add-options arm_neon } */\n"; + Printf.fprintf chan "\n#include \"arm_neon.h\"\n\n"; + Printf.fprintf chan "void test_%s (void)\n{\n" test_name + +--- a/gcc/config/arm/neon.md ++++ b/gcc/config/arm/neon.md @@ -159,7 +159,8 @@ (UNSPEC_VUZP1 201) (UNSPEC_VUZP2 202) @@ -9236,20 +9629,9 @@ diff -Nur a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md (define_insn "ior3" [(set (match_operand:VDQ 0 "s_register_operand" "=w,w") (ior:VDQ (match_operand:VDQ 1 "s_register_operand" "w,0") -@@ -3611,7 +3715,8 @@ - UNSPEC_VSHLL_N))] - "TARGET_NEON" - { -- neon_const_bounds (operands[2], 0, neon_element_bits (mode)); -+ /* The boundaries are: 0 < imm <= size. */ -+ neon_const_bounds (operands[2], 0, neon_element_bits (mode) + 1); - return "vshll.%T3%#\t%q0, %P1, %2"; - } - [(set_attr "neon_type" "neon_shift_1")] -diff -Nur a/gcc/config/arm/neon.ml b/gcc/config/arm/neon.ml ---- a/gcc/config/arm/neon.ml 2007-08-02 12:49:31.000000000 +0200 -+++ b/gcc/config/arm/neon.ml 2010-01-25 09:50:28.995687913 +0100 -@@ -50,7 +50,7 @@ +--- a/gcc/config/arm/neon.ml ++++ b/gcc/config/arm/neon.ml +@@ -50,7 +50,7 @@ type vectype = T_int8x8 | T_int8x16 | T_ptrto of vectype | T_const of vectype | T_void | T_intQI | T_intHI | T_intSI @@ -9258,7 +9640,7 @@ diff -Nur a/gcc/config/arm/neon.ml b/gcc/config/arm/neon.ml (* The meanings of the following are: TImode : "Tetra", two registers (four words). -@@ -1693,6 +1693,7 @@ +@@ -1693,6 +1693,7 @@ let string_of_vectype vt = | T_intHI -> "__builtin_neon_hi" | T_intSI -> "__builtin_neon_si" | T_intDI -> "__builtin_neon_di" @@ -9266,33 +9648,17 @@ diff -Nur a/gcc/config/arm/neon.ml b/gcc/config/arm/neon.ml | T_arrayof (num, base) -> let basename = name (fun x -> x) base in affix (Printf.sprintf "%sx%d" basename num) -diff -Nur a/gcc/config/arm/neon-testgen.ml b/gcc/config/arm/neon-testgen.ml ---- a/gcc/config/arm/neon-testgen.ml 2007-08-02 12:49:31.000000000 +0200 -+++ b/gcc/config/arm/neon-testgen.ml 2010-01-25 09:50:28.995687913 +0100 -@@ -51,8 +51,8 @@ - Printf.fprintf chan "/* This file was autogenerated by neon-testgen. */\n\n"; - Printf.fprintf chan "/* { dg-do assemble } */\n"; - Printf.fprintf chan "/* { dg-require-effective-target arm_neon_ok } */\n"; -- Printf.fprintf chan -- "/* { dg-options \"-save-temps -O0 -mfpu=neon -mfloat-abi=softfp\" } */\n"; -+ Printf.fprintf chan "/* { dg-options \"-save-temps -O0\" } */\n"; -+ Printf.fprintf chan "/* { dg-add-options arm_neon } */\n"; - Printf.fprintf chan "\n#include \"arm_neon.h\"\n\n"; - Printf.fprintf chan "void test_%s (void)\n{\n" test_name - -diff -Nur a/gcc/config/arm/netbsd-elf.h b/gcc/config/arm/netbsd-elf.h ---- a/gcc/config/arm/netbsd-elf.h 2007-08-02 12:49:31.000000000 +0200 -+++ b/gcc/config/arm/netbsd-elf.h 2010-01-25 09:50:28.995687913 +0100 -@@ -153,5 +153,5 @@ +--- a/gcc/config/arm/netbsd-elf.h ++++ b/gcc/config/arm/netbsd-elf.h +@@ -153,5 +153,5 @@ do \ while (0) #undef FPUTYPE_DEFAULT -#define FPUTYPE_DEFAULT FPUTYPE_VFP +#define FPUTYPE_DEFAULT "vfp" -diff -Nur a/gcc/config/arm/nocrt0.h b/gcc/config/arm/nocrt0.h ---- a/gcc/config/arm/nocrt0.h 1970-01-01 01:00:00.000000000 +0100 -+++ b/gcc/config/arm/nocrt0.h 2010-01-25 09:50:28.995687913 +0100 +--- /dev/null ++++ b/gcc/config/arm/nocrt0.h @@ -0,0 +1,25 @@ +/* Definitions for generic libgloss based cofigs where crt0 is supplied by + the linker script. @@ -9319,9 +9685,8 @@ diff -Nur a/gcc/config/arm/nocrt0.h b/gcc/config/arm/nocrt0.h + +#undef LIB_SPEC +#define LIB_SPEC "-lc" -diff -Nur a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md ---- a/gcc/config/arm/predicates.md 2009-02-20 16:20:38.000000000 +0100 -+++ b/gcc/config/arm/predicates.md 2010-01-25 09:50:28.995687913 +0100 +--- a/gcc/config/arm/predicates.md ++++ b/gcc/config/arm/predicates.md @@ -73,6 +73,10 @@ || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS)); }) @@ -9365,9 +9730,8 @@ diff -Nur a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md if (count <= 1 || GET_CODE (XVECEXP (op, 0, 0)) != SET) return false; -diff -Nur a/gcc/config/arm/sfp-machine.h b/gcc/config/arm/sfp-machine.h ---- a/gcc/config/arm/sfp-machine.h 2008-03-03 15:30:48.000000000 +0100 -+++ b/gcc/config/arm/sfp-machine.h 2010-01-25 09:50:28.995687913 +0100 +--- a/gcc/config/arm/sfp-machine.h ++++ b/gcc/config/arm/sfp-machine.h @@ -14,9 +14,11 @@ #define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y) #define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y) @@ -9388,10 +9752,9 @@ diff -Nur a/gcc/config/arm/sfp-machine.h b/gcc/config/arm/sfp-machine.h +#define __truncsfhf2 __gnu_f2h_ieee #endif /* __ARM_EABI__ */ -diff -Nur a/gcc/config/arm/t-arm b/gcc/config/arm/t-arm ---- a/gcc/config/arm/t-arm 2008-03-27 20:20:18.000000000 +0100 -+++ b/gcc/config/arm/t-arm 2010-01-25 09:50:28.995687913 +0100 -@@ -13,7 +13,9 @@ +--- a/gcc/config/arm/t-arm ++++ b/gcc/config/arm/t-arm +@@ -13,7 +13,9 @@ MD_INCLUDES= $(srcdir)/config/arm/arm-t $(srcdir)/config/arm/iwmmxt.md \ $(srcdir)/config/arm/vfp.md \ $(srcdir)/config/arm/neon.md \ @@ -9402,10 +9765,9 @@ diff -Nur a/gcc/config/arm/t-arm b/gcc/config/arm/t-arm s-config s-conditions s-flags s-codes s-constants s-emit s-recog s-preds \ s-opinit s-extract s-peep s-attr s-attrtab s-output: $(MD_INCLUDES) -diff -Nur a/gcc/config/arm/t-arm-elf b/gcc/config/arm/t-arm-elf ---- a/gcc/config/arm/t-arm-elf 2008-06-12 19:29:47.000000000 +0200 -+++ b/gcc/config/arm/t-arm-elf 2010-01-25 09:50:28.995687913 +0100 -@@ -24,10 +24,18 @@ +--- a/gcc/config/arm/t-arm-elf ++++ b/gcc/config/arm/t-arm-elf +@@ -24,10 +24,18 @@ MULTILIB_MATCHES = #MULTILIB_MATCHES += march?armv7=march?armv7-a #MULTILIB_MATCHES += march?armv7=march?armv7-r #MULTILIB_MATCHES += march?armv7=march?armv7-m @@ -9424,9 +9786,8 @@ diff -Nur a/gcc/config/arm/t-arm-elf b/gcc/config/arm/t-arm-elf # MULTILIB_OPTIONS += mcpu=ep9312 # MULTILIB_DIRNAMES += ep9312 # MULTILIB_EXCEPTIONS += *mthumb/*mcpu=ep9312* -diff -Nur a/gcc/config/arm/t-asa b/gcc/config/arm/t-asa ---- a/gcc/config/arm/t-asa 1970-01-01 01:00:00.000000000 +0100 -+++ b/gcc/config/arm/t-asa 2010-01-25 09:50:28.995687913 +0100 +--- /dev/null ++++ b/gcc/config/arm/t-asa @@ -0,0 +1,45 @@ +# Overrides for ASA + @@ -9473,9 +9834,8 @@ diff -Nur a/gcc/config/arm/t-asa b/gcc/config/arm/t-asa +MULTILIB_ALIASES += march?armv7-a/mfpu?neon/mfloat-abi?softfp=march?armv7-a/mfloat-abi?softfp +MULTILIB_ALIASES += mthumb/march?armv7-a/mfpu?neon/mfloat-abi?softfp=mthumb/march?armv7-a/mfpu?neon +MULTILIB_ALIASES += mthumb/march?armv7-a/mfpu?neon/mfloat-abi?softfp=mthumb/march?armv7-a/mfloat-abi?softfp -diff -Nur a/gcc/config/arm/t-bpabi b/gcc/config/arm/t-bpabi ---- a/gcc/config/arm/t-bpabi 2005-11-04 15:51:20.000000000 +0100 -+++ b/gcc/config/arm/t-bpabi 2010-01-25 09:50:28.995687913 +0100 +--- a/gcc/config/arm/t-bpabi ++++ b/gcc/config/arm/t-bpabi @@ -1,10 +1,13 @@ # Add the bpabi.S functions. -LIB1ASMFUNCS += _aeabi_lcmp _aeabi_ulcmp _aeabi_ldivmod _aeabi_uldivmod @@ -9491,489 +9851,33 @@ diff -Nur a/gcc/config/arm/t-bpabi b/gcc/config/arm/t-bpabi UNWIND_H = $(srcdir)/config/arm/unwind-arm.h LIB2ADDEH = $(srcdir)/config/arm/unwind-arm.c \ $(srcdir)/config/arm/libunwind.S \ -diff -Nur a/gcc/config/arm/t-cs-eabi b/gcc/config/arm/t-cs-eabi ---- a/gcc/config/arm/t-cs-eabi 1970-01-01 01:00:00.000000000 +0100 -+++ b/gcc/config/arm/t-cs-eabi 2010-01-25 09:50:28.995687913 +0100 -@@ -0,0 +1,198 @@ -+# Multilibs for SourceryG++ arm-none-eabi -+ -+MULTILIB_OPTIONS = mthumb -+MULTILIB_DIRNAMES = t -+MULTILIB_EXCEPTIONS = -+MULTILIB_MATCHES = -+MULTILIB_ALIASES = -+ -+MULTILIB_OPTIONS += march=armv7/march=armv7-a/march=armv5te/march=armv6-m -+MULTILIB_DIRNAMES += v7 v7a v5te v6m -+MULTILIB_MATCHES += march?armv7-a=march?armv7a -+MULTILIB_MATCHES += march?armv7=march?armv7r -+MULTILIB_MATCHES += march?armv7=march?armv7m -+MULTILIB_MATCHES += march?armv7=march?armv7-r -+MULTILIB_MATCHES += march?armv7=march?armv7-m -+MULTILIB_MATCHES += march?armv7=march?armv7e-m -+MULTILIB_MATCHES += march?armv7-a=mcpu?cortex-a9 -+MULTILIB_MATCHES += march?armv7-a=mcpu?cortex-a8 -+MULTILIB_MATCHES += march?armv7-a=mcpu?cortex-a5 -+MULTILIB_MATCHES += march?armv7=mcpu?cortex-r4 -+MULTILIB_MATCHES += march?armv7=mcpu?cortex-r4f -+MULTILIB_MATCHES += march?armv7=mcpu?cortex-m3 -+MULTILIB_MATCHES += march?armv6-m=mcpu?cortex-m1 -+MULTILIB_MATCHES += march?armv6-m=mcpu?cortex-m0 -+MULTILIB_MATCHES += march?armv5te=march?armv6 -+MULTILIB_MATCHES += march?armv5te=march?armv6j -+MULTILIB_MATCHES += march?armv5te=march?armv6k -+MULTILIB_MATCHES += march?armv5te=march?armv6z -+MULTILIB_MATCHES += march?armv5te=march?armv6zk -+MULTILIB_MATCHES += march?armv5te=march?armv6t2 -+MULTILIB_MATCHES += march?armv5te=march?iwmmxt -+MULTILIB_MATCHES += march?armv5te=march?iwmmxt2 -+MULTILIB_MATCHES += march?armv5te=mcpu?arm9e -+MULTILIB_MATCHES += march?armv5te=mcpu?arm946e-s -+MULTILIB_MATCHES += march?armv5te=mcpu?arm966e-s -+MULTILIB_MATCHES += march?armv5te=mcpu?arm968e-s -+MULTILIB_MATCHES += march?armv5te=mcpu?arm10e -+MULTILIB_MATCHES += march?armv5te=mcpu?arm1020e -+MULTILIB_MATCHES += march?armv5te=mcpu?arm1022e -+MULTILIB_MATCHES += march?armv5te=mcpu?xscale -+MULTILIB_MATCHES += march?armv5te=mcpu?iwmmxt -+MULTILIB_MATCHES += march?armv5te=mcpu?iwmmxt2 -+MULTILIB_MATCHES += march?armv5te=mcpu?marvell-f -+MULTILIB_MATCHES += march?armv5te=mcpu?arm926ej-s -+MULTILIB_MATCHES += march?armv5te=mcpu?arm1026ej-s -+MULTILIB_MATCHES += march?armv5te=mcpu?arm1136j-s -+MULTILIB_MATCHES += march?armv5te=mcpu?arm1136jf-s -+MULTILIB_MATCHES += march?armv5te=mcpu?arm1176jz-s -+MULTILIB_MATCHES += march?armv5te=mcpu?arm1176jzf-s -+MULTILIB_MATCHES += march?armv5te=mcpu?mpcorenovfp -+MULTILIB_MATCHES += march?armv5te=mcpu?mpcore -+MULTILIB_MATCHES += march?armv5te=mcpu?arm1156t2-s -+ -+MULTILIB_OPTIONS += mfloat-abi=softfp/mfloat-abi=hard -+MULTILIB_DIRNAMES += softfp hard -+MULTILIB_MATCHES += mfloat-abi?hard=mhard-float -+ -+MULTILIB_OPTIONS += mfpu=neon -+MULTILIB_DIRNAMES += neon -+MULTILIB_EXCEPTIONS += mfpu=neon -+MULTILIB_MATCHES += mfpu?neon=mfpu?neon-fp16 -+MULTILIB_MATCHES += mfpu?neon=mfpu?neon-vfpv4 -+ -+MULTILIB_ALIASES += mthumb=mthumb/mfpu?neon -+MULTILIB_ALIASES += mthumb=mthumb/march?armv5te/mfpu?neon -+MULTILIB_ALIASES += mbig-endian=mthumb/mfpu?neon/mbig-endian -+#MULTILIB_ALIASES += mfloat-abi?softfp=mthumb/mfloat-abi?softfp/mfpu?neon -+#MULTILIB_ALIASES += mfloat-abi?softfp=mfloat-abi?softfp/mfpu?neon -+#MULTILIB_ALIASES += mfloat-abi?softfp/mbig-endian=mfloat-abi?softfp/mfpu?neon/mbig-endian -+#MULTILIB_ALIASES += mfloat-abi?softfp/mbig-endian=mthumb/mfloat-abi?softfp/mfpu?neon/mbig-endian -+MULTILIB_ALIASES += mthumb/march?armv7/mfix-cortex-m3-ldrd=mthumb/march?armv7-a/mfpu?neon -+MULTILIB_ALIASES += mthumb/march?armv7/mbig-endian=mthumb/march?armv7-a/mfpu?neon/mbig-endian -+MULTILIB_ALIASES += march?armv7-a/mfloat-abi?softfp/mfpu?neon=mthumb/march?armv7-a/mfloat-abi?softfp/mfpu?neon -+MULTILIB_ALIASES += march?armv7-a/mfloat-abi?hard/mfpu?neon=mthumb/march?armv7-a/mfloat-abi?hard/mfpu?neon -+ -+MULTILIB_OPTIONS += mbig-endian -+MULTILIB_DIRNAMES += be -+MULTILIB_ALIASES += mbig-endian=mfpu?neon/mbig-endian -+ -+# ARMv6-M does not have ARM mode. -+MULTILIB_EXCEPTIONS += march=armv6-m -+ -+# Some ARMv7 variants have ARM mode. Use the ARM libraries. -+MULTILIB_EXCEPTIONS += march=armv7 march=armv7/* -+MULTILIB_ALIASES += mbig-endian=march?armv7/mbig-endian -+MULTILIB_ALIASES += march?armv5te/mfloat-abi?softfp=march?armv7/mfloat-abi?softfp -+MULTILIB_ALIASES += march?armv5te/mfloat-abi?softfp=march?armv7/mfloat-abi?softfp/mfpu?neon -+MULTILIB_ALIASES += march?armv5te/mfloat-abi?softfp/mbig-endian=march?armv7/mfloat-abi?softfp/mbig-endian -+MULTILIB_ALIASES += march?armv5te/mfloat-abi?softfp/mbig-endian=march?armv7/mfloat-abi?softfp/mfpu?neon/mbig-endian -+MULTILIB_ALIASES += mbig-endian=march?armv7/mfpu?neon/mbig-endian -+MULTILIB_ALIASES += mthumb/march?armv7/mfix-cortex-m3-ldrd=mthumb/march?armv7/mfloat-abi?softfp/mfpu?neon -+MULTILIB_ALIASES += mthumb/march?armv7/mfix-cortex-m3-ldrd=mthumb/march?armv7/mfpu?neon -+MULTILIB_ALIASES += mthumb/march?armv7/mbig-endian=mthumb/march?armv7/mfpu?neon/mbig-endian -+MULTILIB_ALIASES += mthumb/march?armv7/mbig-endian=mthumb/march?armv7/mfloat-abi?softfp/mfpu?neon/mbig-endian -+ -+# ARMv7-A is specially useful used with VFPv3 (enabled by NEON). Rest of the cases behaves as ARMv7. -+MULTILIB_ALIASES += mthumb/march?armv7/mfix-cortex-m3-ldrd=mthumb/march?armv7-a -+MULTILIB_ALIASES += mbig-endian=march?armv7-a/mbig-endian -+MULTILIB_ALIASES += march?armv5te/mfloat-abi?softfp/mbig-endian=march?armv7-a/mfloat-abi?softfp/mbig-endian -+MULTILIB_ALIASES += march?armv5te/mfloat-abi?softfp/mbig-endian=march?armv7-a/mfloat-abi?softfp/mfpu?neon/mbig-endian -+MULTILIB_ALIASES += mthumb/march?armv7/mfix-cortex-m3-ldrd=mthumb/march?armv7-a/mfloat-abi?softfp -+MULTILIB_ALIASES += mthumb/march?armv7/mbig-endian=mthumb/march?armv7-a/mbig-endian -+MULTILIB_ALIASES += mthumb/march?armv7/mbig-endian=mthumb/march?armv7-a/mfloat-abi?softfp/mbig-endian -+MULTILIB_ALIASES += mthumb/march?armv7/mfix-cortex-m3-ldrd=mthumb/march?armv7/mfloat-abi?softfp -+MULTILIB_ALIASES += march?armv5te=march?armv7-a -+MULTILIB_ALIASES += march?armv5te/mfloat-abi?softfp=march?armv7-a/mfloat-abi?softfp -+MULTILIB_ALIASES += march?armv5te=march?armv7-a/mfpu?neon -+MULTILIB_ALIASES += mbig-endian=march?armv7-a/mfpu?neon/mbig-endian -+MULTILIB_ALIASES += mthumb/march?armv7/mbig-endian=mthumb/march?armv7-a/mfloat-abi?softfp/mfpu?neon/mbig-endian -+ -+# ARMv5T thumb uses the ARMv5T ARM libraries (with or without VFP). -+MULTILIB_ALIASES += mthumb=mthumb/march?armv5te -+MULTILIB_ALIASES += march?armv5te/mfloat-abi?softfp=mthumb/march?armv5te/mfloat-abi?softfp -+MULTILIB_ALIASES += march?armv5te/mfloat-abi?softfp=march?armv5te/mfloat-abi?softfp/mfpu?neon -+MULTILIB_ALIASES += march?armv5te/mfloat-abi?softfp=mthumb/march?armv5te/mfloat-abi?softfp/mfpu?neon -+MULTILIB_ALIASES += march?armv5te=march?armv5te/mfpu?neon -+MULTILIB_ALIASES += mbig-endian=march?armv5te/mfpu?neon/mbig-endian -+MULTILIB_ALIASES += march?armv5te/mfloat-abi?softfp/mbig-endian=march?armv5te/mfloat-abi?softfp/mfpu?neon/mbig-endian -+MULTILIB_ALIASES += mbig-endian=mthumb/march?armv5te/mfpu?neon/mbig-endian -+MULTILIB_ALIASES += march?armv5te/mfloat-abi?softfp/mbig-endian=mthumb/march?armv5te/mfloat-abi?softfp/mfpu?neon/mbig-endian -+ -+# ARMv6-M and VFP are incompatible. -+# FIXME: The compiler should probably error. -+MULTILIB_EXCEPTIONS += *march=armv6-m/mfloat-abi=softfp -+MULTILIB_ALIASES += mthumb/march?armv6-m=mthumb/march?armv6-m/mfpu?neon -+MULTILIB_EXCEPTIONS += march=armv6-m*mfpu=neon -+MULTILIB_EXCEPTIONS += mthumb/march=armv6-m/mfloat-abi=softfp/mfpu=neon -+ -+# ARMv4t VFP isn't really supported, so use the soft-float libraries. -+MULTILIB_EXCEPTIONS += mfloat-abi?softfp -+MULTILIB_EXCEPTIONS += mfloat-abi?softfp/mfpu?neon -+MULTILIB_ALIASES += mthumb=mthumb/mfloat-abi?softfp -+MULTILIB_ALIASES += mthumb=mthumb/mfloat-abi?softfp/mfpu?neon -+ -+MULTILIB_ALIASES += mbig-endian=mfloat-abi?softfp/mbig-endian -+MULTILIB_ALIASES += mbig-endian=mfloat-abi?softfp/mfpu?neon/mbig-endian -+MULTILIB_ALIASES += mbig-endian=mthumb/mfloat-abi?softfp/mbig-endian -+MULTILIB_ALIASES += mbig-endian=mthumb/mfloat-abi?softfp/mfpu?neon/mbig-endian -+ -+# We don't have a big-endian ARMv6-M compatible multilibs. -+MULTILIB_EXCEPTIONS += *march=armv6-m*mbig-endian -+ -+# Use the generic libraries for big-endian ARMv5T -+MULTILIB_ALIASES += mbig-endian=march?armv5te/mbig-endian -+MULTILIB_ALIASES += mbig-endian=mfloat-abi?softfp/mbig-endian -+MULTILIB_ALIASES += mbig-endian=mthumb/march?armv5te/mbig-endian -+MULTILIB_ALIASES += march?armv5te/mfloat-abi?softfp/mbig-endian=mthumb/march?armv5te/mfloat-abi?softfp/mbig-endian -+ -+# Use ARM libraries for big-endian Thumb. -+MULTILIB_ALIASES += mbig-endian=mthumb/mbig-endian -+ -+# Don't bother with big-endian Thumb-2 VFP. Use the soft-float libraries -+# for now. -+MULTILIB_ALIASES += mthumb/march?armv7/mbig-endian=mthumb/march?armv7/mfloat-abi?softfp/mbig-endian -+ -+# The only -mfloat-abi=hard libraries provided are for little-endian -+# v7-A NEON. -+MULTILIB_EXCEPTIONS += mfloat-abi=hard* -+MULTILIB_EXCEPTIONS += *march=armv5te*mfloat-abi=hard* -+MULTILIB_EXCEPTIONS += *march=armv7/*mfloat-abi=hard* -+MULTILIB_EXCEPTIONS += *march=armv6-m*mfloat-abi=hard* -+MULTILIB_EXCEPTIONS += mthumb/mfloat-abi=hard* -+MULTILIB_EXCEPTIONS += *mfloat-abi=hard*mbig-endian -+MULTILIB_EXCEPTIONS += *mfloat-abi=hard -+ -+# FIXME: We need a sane way of doing this. -+# This isn't really a multilib, it's a hack to add an extra option -+# to the v7-m multilib. -+MULTILIB_OPTIONS += mfix-cortex-m3-ldrd -+MULTILIB_DIRNAMES += broken_ldrd -+ -+MULTILIB_EXCEPTIONS += mfix-cortex-m3-ldrd -+MULTILIB_EXCEPTIONS += mthumb/mfix-cortex-m3-ldrd -+MULTILIB_EXCEPTIONS += *march=armv6-m*mfix-cortex-m3-ldrd -+MULTILIB_EXCEPTIONS += *march=armv7-a*mfix-cortex-m3-ldrd -+MULTILIB_EXCEPTIONS += *mcpu=*mfix-cortex-m3-ldrd -+MULTILIB_EXCEPTIONS += *mbig-endian*mfix-cortex-m3-ldrd -+MULTILIB_EXCEPTIONS += *mfloat-abi=softfp*mfix-cortex-m3-ldrd -+MULTILIB_EXCEPTIONS += *march=armv5te*mfix-cortex-m3-ldrd -+MULTILIB_EXCEPTIONS += *mfpu=neon*mfix-cortex-m3-ldrd -+ -+MULTILIB_ALIASES += mthumb/march?armv7/mfix-cortex-m3-ldrd=mthumb/march?armv7 -+MULTILIB_ALIASES += mthumb/march?armv7/mfix-cortex-m3-ldrd=mthumb/march?armv7-a/mfix-cortex-m3-ldrd -+MULTILIB_ALIASES += mthumb/march?armv7/mfix-cortex-m3-ldrd=mthumb/march?armv7/mfpu?neon/mfix-cortex-m3-ldrd -+MULTILIB_ALIASES += mthumb/march?armv7/mfix-cortex-m3-ldrd=mthumb/march?armv7-a/mfpu?neon/mfix-cortex-m3-ldrd -+ -+# As of at least 4.2, gcc passes the wrong -L options if some multilibs are -+# omitted from MULTILIB_OSDIRNAMES -+MULTILIB_OSDIRNAMES = mthumb=!thumb -+MULTILIB_OSDIRNAMES += mbig-endian=!be -+MULTILIB_OSDIRNAMES += march.armv5te=!armv5te -+MULTILIB_OSDIRNAMES += march.armv5te/mfloat-abi.softfp=!vfp -+MULTILIB_OSDIRNAMES += march.armv5te/mfloat-abi.softfp/mbig-endian=!vfp-be -+MULTILIB_OSDIRNAMES += mthumb/march.armv7/mfix-cortex-m3-ldrd=!thumb2 -+MULTILIB_OSDIRNAMES += march.armv7-a/mfloat-abi.softfp/mfpu.neon=!armv7-a-neon -+MULTILIB_OSDIRNAMES += march.armv7-a/mfloat-abi.hard/mfpu.neon=!armv7-a-hard -+MULTILIB_OSDIRNAMES += mthumb/march.armv7/mbig-endian=!thumb2-be -+MULTILIB_OSDIRNAMES += mthumb/march.armv6-m=!armv6-m -diff -Nur a/gcc/config/arm/t-cs-eabi-lite b/gcc/config/arm/t-cs-eabi-lite ---- a/gcc/config/arm/t-cs-eabi-lite 1970-01-01 01:00:00.000000000 +0100 -+++ b/gcc/config/arm/t-cs-eabi-lite 2010-01-25 09:50:28.995687913 +0100 -@@ -0,0 +1,47 @@ -+# We build 4 multilibs: -+# ./ (default) -+# thumb/ -mthumb -+# thumb2/ -mthumb -march=armv7 -+# armv6-m/ -mthumb -march=armv6-m -+ -+MULTILIB_OPTIONS = mthumb -+MULTILIB_DIRNAMES = thumb -+MULTILIB_EXCEPTIONS = -+MULTILIB_MATCHES = -+MULTILIB_ALIASES = -+ -+MULTILIB_OPTIONS += march=armv7/march=armv6-m -+MULTILIB_DIRNAMES += v7 v6-m -+MULTILIB_EXCEPTIONS += march=armv7* -+MULTILIB_MATCHES += march?armv7=march?armv7-a -+MULTILIB_MATCHES += march?armv7=march?armv7-r -+MULTILIB_MATCHES += march?armv7=march?armv7-m -+MULTILIB_MATCHES += march?armv7=march?armv7e-m -+MULTILIB_MATCHES += march?armv7=mcpu?cortex-a9 -+MULTILIB_MATCHES += march?armv7=mcpu?cortex-a8 -+MULTILIB_MATCHES += march?armv7=mcpu?cortex-a5 -+MULTILIB_MATCHES += march?armv7=mcpu?cortex-r4 -+MULTILIB_MATCHES += march?armv7=mcpu?cortex-r4f -+MULTILIB_MATCHES += march?armv7=mcpu?cortex-m3 -+ -+MULTILIB_EXCEPTIONS += march=armv6-m -+MULTILIB_MATCHES += march?armv6-m=mcpu?cortex-m1 -+MULTILIB_MATCHES += march?armv6-m=mcpu?cortex-m0 -+ -+# FIXME: We need a sane way of doing this. -+# This isn't really a multilib, it's a hack to add an extra option -+# to the v7-m multilib. -+MULTILIB_OPTIONS += mfix-cortex-m3-ldrd -+MULTILIB_DIRNAMES += broken_ldrd -+ -+MULTILIB_EXCEPTIONS += mfix-cortex-m3-ldrd -+MULTILIB_EXCEPTIONS += mthumb/mfix-cortex-m3-ldrd -+MULTILIB_EXCEPTIONS += *march=armv6-m*mfix-cortex-m3-ldrd -+ -+MULTILIB_ALIASES += mthumb/march?armv7/mfix-cortex-m3-ldrd=mthumb/march?armv7 -+ -+# As of at least 4.2, gcc passes the wrong -L options if some multilibs are -+# omitted from MULTILIB_OSDIRNAMES -+MULTILIB_OSDIRNAMES = mthumb=!thumb -+MULTILIB_OSDIRNAMES += mthumb/march.armv7/mfix-cortex-m3-ldrd=!thumb2 -+MULTILIB_OSDIRNAMES += mthumb/march.armv6-m=!armv6-m -diff -Nur a/gcc/config/arm/t-cs-linux b/gcc/config/arm/t-cs-linux ---- a/gcc/config/arm/t-cs-linux 1970-01-01 01:00:00.000000000 +0100 -+++ b/gcc/config/arm/t-cs-linux 2010-01-25 09:50:28.995687913 +0100 -@@ -0,0 +1,112 @@ -+# Multilibs for SourceryG++ arm-none-linux-gnueabi -+ -+MULTILIB_OPTIONS = mthumb -+MULTILIB_DIRNAMES = t -+MULTILIB_EXCEPTIONS = -+MULTILIB_MATCHES = -+MULTILIB_ALIASES = -+ -+MULTILIB_OPTIONS += march=armv4t/march=armv7-a -+MULTILIB_DIRNAMES += v4t v7a -+ -+MULTILIB_MATCHES += march?armv7-a=march?armv7a -+MULTILIB_MATCHES += march?armv7-a=mcpu?cortex-a9 -+MULTILIB_MATCHES += march?armv7-a=mcpu?cortex-a8 -+MULTILIB_MATCHES += march?armv7-a=mcpu?cortex-a5 -+MULTILIB_MATCHES += march?armv4t=march?ep9312 -+MULTILIB_MATCHES += march?armv4t=mcpu?arm7tdmi -+MULTILIB_MATCHES += march?armv4t=mcpu?arm7tdmi-s -+MULTILIB_MATCHES += march?armv4t=mcpu?arm710t -+MULTILIB_MATCHES += march?armv4t=mcpu?arm720t -+MULTILIB_MATCHES += march?armv4t=mcpu?arm740t -+MULTILIB_MATCHES += march?armv4t=mcpu?arm9 -+MULTILIB_MATCHES += march?armv4t=mcpu?arm9tdmi -+MULTILIB_MATCHES += march?armv4t=mcpu?arm920 -+MULTILIB_MATCHES += march?armv4t=mcpu?arm920t -+MULTILIB_MATCHES += march?armv4t=mcpu?arm922t -+MULTILIB_MATCHES += march?armv4t=mcpu?arm940t -+MULTILIB_MATCHES += march?armv4t=mcpu?ep9312 -+MULTILIB_MATCHES += march?armv4t=march?armv5 -+MULTILIB_MATCHES += march?armv4t=march?armv5t -+MULTILIB_MATCHES += march?armv4t=march?arm10tdmi -+MULTILIB_MATCHES += march?armv4t=march?arm1020t -+ -+MULTILIB_OPTIONS += mfloat-abi=softfp/mfloat-abi=hard -+MULTILIB_DIRNAMES += softfp hard -+MULTILIB_MATCHES += mfloat-abi?hard=mhard-float -+ -+MULTILIB_OPTIONS += mfpu=neon -+MULTILIB_DIRNAMES += neon -+MULTILIB_EXCEPTIONS += mfpu=neon -+MULTILIB_MATCHES += mfpu?neon=mfpu?neon-fp16 -+MULTILIB_MATCHES += mfpu?neon=mfpu?neon-vfpv4 -+MULTILIB_ALIASES += mfloat-abi?softfp=mfloat-abi?softfp/mfpu?neon -+MULTILIB_ALIASES += mfloat-abi?softfp=mthumb/mfloat-abi?softfp/mfpu?neon -+MULTILIB_ALIASES += march?armv7-a/mfloat-abi?hard/mfpu?neon=mthumb/march?armv7-a/mfloat-abi?hard/mfpu?neon -+ -+MULTILIB_OPTIONS += mbig-endian -+MULTILIB_DIRNAMES += be -+MULTILIB_ALIASES += mbig-endian=mfpu?neon/mbig-endian -+MULTILIB_ALIASES += mfloat-abi?softfp/mbig-endian=mfloat-abi?softfp/mfpu?neon/mbig-endian -+MULTILIB_ALIASES += mbig-endian=mthumb/mfpu?neon/mbig-endian -+MULTILIB_ALIASES += mfloat-abi?softfp/mbig-endian=mthumb/mfloat-abi?softfp/mfpu?neon/mbig-endian -+ -+# Do not build Thumb libraries. -+MULTILIB_EXCEPTIONS += mthumb -+MULTILIB_EXCEPTIONS += mthumb/mfpu=neon -+ -+# Use ARM libraries for ARMv4t Thumb and VFP. -+MULTILIB_ALIASES += march?armv4t=mthumb/march?armv4t -+MULTILIB_ALIASES += march?armv4t=march?armv4t/mfloat-abi?softfp -+MULTILIB_ALIASES += march?armv4t=mthumb/march?armv4t/mfloat-abi?softfp -+MULTILIB_ALIASES += march?armv4t=march?armv4t/mfpu?neon -+MULTILIB_ALIASES += march?armv4t=march?armv4t/mfloat-abi?softfp/mfpu?neon -+MULTILIB_ALIASES += march?armv4t=mthumb/march?armv4t/mfpu?neon -+MULTILIB_ALIASES += march?armv4t=mthumb/march?armv4t/mfloat-abi?softfp/mfpu?neon -+ -+# We do not support ARMv4t big-endian. -+MULTILIB_EXCEPTIONS += *march=armv4t*mbig-endian -+ -+# Behave ARMv7-A as ARMv7 for some cases. -+MULTILIB_EXCEPTIONS += march=armv7-a -+MULTILIB_EXCEPTIONS += march=armv7-a/mfpu=neon -+MULTILIB_ALIASES += mfloat-abi?softfp=march?armv7-a/mfloat-abi?softfp -+MULTILIB_ALIASES += mbig-endian=march?armv7-a/mbig-endian -+MULTILIB_ALIASES += mbig-endian=march?armv7-a/mfpu?neon/mbig-endian -+MULTILIB_ALIASES += mfloat-abi?softfp/mbig-endian=march?armv7-a/mfloat-abi?softfp/mbig-endian -+MULTILIB_ALIASES += mfloat-abi?softfp/mbig-endian=march?armv7-a/mfloat-abi?softfp/mfpu?neon/mbig-endian -+MULTILIB_ALIASES += mthumb/march?armv7-a=mthumb/march?armv7-a/mfpu?neon -+MULTILIB_ALIASES += mthumb/march?armv7-a/mbig-endian=mthumb/march?armv7-a/mfpu?neon/mbig-endian -+MULTILIB_ALIASES += mthumb/march?armv7-a/mbig-endian=mthumb/march?armv7-a/mfloat-abi?softfp/mfpu?neon/mbig-endian -+MULTILIB_ALIASES += mthumb/march?armv7-a=mthumb/march?armv7-a/mfloat-abi?softfp -+ -+# Thumb-1 VFP isn't really a meaningful combination. Use the ARM VFP. -+MULTILIB_ALIASES += mfloat-abi?softfp=mthumb/mfloat-abi?softfp -+MULTILIB_ALIASES += mfloat-abi?softfp/mbig-endian=mthumb/mfloat-abi?softfp/mbig-endian -+ -+# Use ARM libraries for big-endian Thumb. -+MULTILIB_ALIASES += mbig-endian=mthumb/mbig-endian -+ -+# Don't bother with big-endian Thumb-2 VFP. Use the soft-float libraries -+# for now. -+MULTILIB_ALIASES += mthumb/march?armv7-a/mbig-endian=mthumb/march?armv7-a/mfloat-abi?softfp/mbig-endian -+ -+# The only -mfloat-abi=hard libraries provided are for little-endian -+# v7-A NEON. -+MULTILIB_EXCEPTIONS += mfloat-abi=hard* -+MULTILIB_EXCEPTIONS += *march=armv4t*mfloat-abi=hard* -+MULTILIB_EXCEPTIONS += mthumb/mfloat-abi=hard* -+MULTILIB_EXCEPTIONS += *mfloat-abi=hard*mbig-endian -+MULTILIB_EXCEPTIONS += *mfloat-abi=hard -+ -+# As of at least 4.2, gcc passes the wrong -L options if some multilibs are -+# omitted from MULTILIB_OSDIRNAMES -+MULTILIB_OSDIRNAMES = march.armv4t=!armv4t -+MULTILIB_OSDIRNAMES += mbig-endian=!be -+MULTILIB_OSDIRNAMES += mfloat-abi.softfp=!vfp -+MULTILIB_OSDIRNAMES += mfloat-abi.softfp/mbig-endian=!vfp-be -+MULTILIB_OSDIRNAMES += mthumb/march.armv7-a=!thumb2 -+MULTILIB_OSDIRNAMES += march.armv7-a/mfloat-abi.softfp/mfpu.neon=!armv7-a-neon -+MULTILIB_OSDIRNAMES += mthumb/march.armv7-a/mfloat-abi.softfp/mfpu.neon=!thumb2-neon -+MULTILIB_OSDIRNAMES += march.armv7-a/mfloat-abi.hard/mfpu.neon=!armv7-a-hard -+MULTILIB_OSDIRNAMES += mthumb/march.armv7-a/mbig-endian=!thumb2-be -diff -Nur a/gcc/config/arm/t-cs-linux-lite b/gcc/config/arm/t-cs-linux-lite ---- a/gcc/config/arm/t-cs-linux-lite 1970-01-01 01:00:00.000000000 +0100 -+++ b/gcc/config/arm/t-cs-linux-lite 2010-01-25 09:50:28.995687913 +0100 -@@ -0,0 +1,48 @@ -+# We build 3 multilibs: -+# ./ (default) -+# armv4t/ -march=armv4t [-mthumb] -+# thumb2/ -mthumb -march=armv7 -+MULTILIB_OPTIONS = mthumb -+MULTILIB_DIRNAMES = thumb -+MULTILIB_OPTIONS += march=armv4t/march=armv7 -+MULTILIB_DIRNAMES += v4t v7 -+MULTILIB_EXCEPTIONS += march=armv7 -+MULTILIB_EXCEPTIONS += mthumb -+ -+MULTILIB_ALIASES = march?armv4t=mthumb/march?armv4t -+ -+# As of at least 4.2, gcc passes the wrong -L options if some multilibs are -+# omitted from MULTILIB_OSDIRNAMES -+MULTILIB_OSDIRNAMES = march.armv4t=!armv4t -+MULTILIB_OSDIRNAMES += mthumb/march.armv7=!thumb2 -+ -+MULTILIB_MATCHES += march?armv7=march?armv7a -+MULTILIB_MATCHES += march?armv7=march?armv7r -+MULTILIB_MATCHES += march?armv7=march?armv7m -+MULTILIB_MATCHES += march?armv7=march?armv7-a -+MULTILIB_MATCHES += march?armv7=march?armv7-r -+MULTILIB_MATCHES += march?armv7=march?armv7-m -+MULTILIB_MATCHES += march?armv7=march?armv7e-m -+MULTILIB_MATCHES += march?armv7=mcpu?cortex-a9 -+MULTILIB_MATCHES += march?armv7=mcpu?cortex-a8 -+MULTILIB_MATCHES += march?armv7=mcpu?cortex-a5 -+MULTILIB_MATCHES += march?armv7=mcpu?cortex-r4 -+MULTILIB_MATCHES += march?armv7=mcpu?cortex-r4f -+MULTILIB_MATCHES += march?armv7=mcpu?cortex-m3 -+MULTILIB_MATCHES += march?armv4t=march?ep9312 -+MULTILIB_MATCHES += march?armv4t=mcpu?arm7tdmi -+MULTILIB_MATCHES += march?armv4t=mcpu?arm7tdmi-s -+MULTILIB_MATCHES += march?armv4t=mcpu?arm710t -+MULTILIB_MATCHES += march?armv4t=mcpu?arm720t -+MULTILIB_MATCHES += march?armv4t=mcpu?arm740t -+MULTILIB_MATCHES += march?armv4t=mcpu?arm9 -+MULTILIB_MATCHES += march?armv4t=mcpu?arm9tdmi -+MULTILIB_MATCHES += march?armv4t=mcpu?arm920 -+MULTILIB_MATCHES += march?armv4t=mcpu?arm920t -+MULTILIB_MATCHES += march?armv4t=mcpu?arm922t -+MULTILIB_MATCHES += march?armv4t=mcpu?arm940t -+MULTILIB_MATCHES += march?armv4t=mcpu?ep9312 -+MULTILIB_MATCHES += march?armv4t=march?armv5 -+MULTILIB_MATCHES += march?armv4t=march?armv5t -+MULTILIB_MATCHES += march?armv4t=march?arm10tdmi -+MULTILIB_MATCHES += march?armv4t=march?arm1020t -diff -Nur a/gcc/config/arm/t-cs-uclinux-eabi b/gcc/config/arm/t-cs-uclinux-eabi ---- a/gcc/config/arm/t-cs-uclinux-eabi 1970-01-01 01:00:00.000000000 +0100 -+++ b/gcc/config/arm/t-cs-uclinux-eabi 2010-01-25 09:50:28.995687913 +0100 -@@ -0,0 +1,55 @@ -+# EABI uClinux multilib selection. Other setting are inherited from t-arm-elf -+ -+# We build 3 multilibs: -+# . (default) -+# thumb2/ -mthumb -march=armv7 -mfix-cortex-m3-ldrd -+# armv6-m/ -mthumb -march=armv6-m -+ -+MULTILIB_OPTIONS = mthumb -+MULTILIB_DIRNAMES = thumb -+MULTILIB_EXCEPTIONS = -+MULTILIB_MATCHES = -+ -+MULTILIB_OPTIONS += march=armv7/march=armv6-m -+MULTILIB_DIRNAMES += armv7 armv6-m -+ -+MULTILIB_EXCEPTIONS += mthumb -+ -+MULTILIB_EXCEPTIONS += march=armv7 -+MULTILIB_MATCHES += march?armv7=march?armv7a -+MULTILIB_MATCHES += march?armv7=march?armv7r -+MULTILIB_MATCHES += march?armv7=march?armv7m -+MULTILIB_MATCHES += march?armv7=march?armv7-a -+MULTILIB_MATCHES += march?armv7=march?armv7-r -+MULTILIB_MATCHES += march?armv7=march?armv7-m -+MULTILIB_MATCHES += march?armv7=march?armv7e-m -+MULTILIB_MATCHES += march?armv7=mcpu?cortex-a9 -+MULTILIB_MATCHES += march?armv7=mcpu?cortex-a8 -+MULTILIB_MATCHES += march?armv7=mcpu?cortex-a5 -+MULTILIB_MATCHES += march?armv7=mcpu?cortex-r4 -+MULTILIB_MATCHES += march?armv7=mcpu?cortex-r4f -+MULTILIB_MATCHES += march?armv7=mcpu?cortex-m3 -+ -+MULTILIB_EXCEPTIONS += march=armv6-m -+MULTILIB_MATCHES += march?armv6-m=mcpu?cortex-m1 -+MULTILIB_MATCHES += march?armv6-m=mcpu?cortex-m0 -+ -+MULTILIB_ALIASES = -+ -+# FIXME: We need a sane way of doing this. -+# This isn't really a multilib, it's a hack to add an extra option -+# to the v7-m multilib. -+MULTILIB_OPTIONS += mfix-cortex-m3-ldrd -+MULTILIB_DIRNAMES += broken_ldrd -+ -+MULTILIB_EXCEPTIONS += mfix-cortex-m3-ldrd -+MULTILIB_EXCEPTIONS += mthumb/mfix-cortex-m3-ldrd -+MULTILIB_EXCEPTIONS += march=armv7/mfix-cortex-m3-ldrd -+MULTILIB_EXCEPTIONS += *march=armv6-m*mfix-cortex-m3-ldrd -+ -+MULTILIB_ALIASES += mthumb/march?armv7/mfix-cortex-m3-ldrd=mthumb/march?armv7 -+ -+ -+MULTILIB_OSDIRNAMES = mthumb/march.armv7/mfix-cortex-m3-ldrd=!thumb2 -+MULTILIB_OSDIRNAMES += mthumb/march.armv6-m=!armv6-m -+ -diff -Nur a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md ---- a/gcc/config/arm/thumb2.md 2008-11-21 00:00:00.000000000 +0100 -+++ b/gcc/config/arm/thumb2.md 2010-01-25 09:50:28.995687913 +0100 +--- a/gcc/config/arm/t-linux-eabi ++++ b/gcc/config/arm/t-linux-eabi +@@ -6,8 +6,8 @@ TARGET_LIBGCC2_CFLAGS = -fPIC + MULTILIB_OPTIONS = + MULTILIB_DIRNAMES = + +-# Use a version of div0 which raises SIGFPE. +-LIB1ASMFUNCS := $(filter-out _dvmd_tls,$(LIB1ASMFUNCS)) _dvmd_lnx ++# Use a version of div0 which raises SIGFPE, and a special __clear_cache. ++LIB1ASMFUNCS := $(filter-out _dvmd_tls,$(LIB1ASMFUNCS)) _dvmd_lnx _clear_cache + + # Multilib the standard Linux files. Don't include crti.o or crtn.o, + # which are provided by glibc. +--- a/gcc/config/arm/t-symbian ++++ b/gcc/config/arm/t-symbian +@@ -17,6 +17,9 @@ UNWIND_H = $(srcdir)/config/arm/unwind-a + LIB2ADDEH = $(srcdir)/unwind-c.c $(srcdir)/config/arm/pr-support.c + LIB2ADDEHDEP = $(UNWIND_H) + ++# Include half-float helpers. ++LIB2FUNCS_STATIC_EXTRA = $(srcdir)/config/arm/fp16.c ++ + # Create a multilib for processors with VFP floating-point, and a + # multilib for those without -- using the soft-float ABI in both + # cases. Symbian OS object should be compiled with interworking +--- a/gcc/config/arm/thumb2.md ++++ b/gcc/config/arm/thumb2.md @@ -24,6 +24,8 @@ ;; changes made in armv5t as "thumb2". These are considered part ;; the 16-bit Thumb-1 instruction set. @@ -10191,120 +10095,8 @@ diff -Nur a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md (const_int 2) (const_int 8)))] ) -diff -Nur a/gcc/config/arm/t-linux-eabi b/gcc/config/arm/t-linux-eabi ---- a/gcc/config/arm/t-linux-eabi 2009-01-24 22:06:08.000000000 +0100 -+++ b/gcc/config/arm/t-linux-eabi 2010-01-25 09:50:28.995687913 +0100 -@@ -6,8 +6,8 @@ - MULTILIB_OPTIONS = - MULTILIB_DIRNAMES = - --# Use a version of div0 which raises SIGFPE. --LIB1ASMFUNCS := $(filter-out _dvmd_tls,$(LIB1ASMFUNCS)) _dvmd_lnx -+# Use a version of div0 which raises SIGFPE, and a special __clear_cache. -+LIB1ASMFUNCS := $(filter-out _dvmd_tls,$(LIB1ASMFUNCS)) _dvmd_lnx _clear_cache - - # Multilib the standard Linux files. Don't include crti.o or crtn.o, - # which are provided by glibc. -diff -Nur a/gcc/config/arm/t-montavista-linux b/gcc/config/arm/t-montavista-linux ---- a/gcc/config/arm/t-montavista-linux 1970-01-01 01:00:00.000000000 +0100 -+++ b/gcc/config/arm/t-montavista-linux 2010-01-25 09:50:28.995687913 +0100 -@@ -0,0 +1,33 @@ -+# MontaVista GNU/Linux Configuration. -+# Copyright (C) 2009 -+# Free Software Foundation, Inc. -+# -+# This file is part of GCC. -+# -+# GCC is free software; you can redistribute it and/or modify -+# it under the terms of the GNU General Public License as published by -+# the Free Software Foundation; either version 3, or (at your option) -+# any later version. -+# -+# GCC is distributed in the hope that it will be useful, -+# but WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+# GNU General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with GCC; see the file COPYING3. If not see -+# . -+ -+MULTILIB_OPTIONS = tarmv6/tthumb2 -+MULTILIB_DIRNAMES = armv6 thumb2 -+ -+MULTILIB_EXCEPTIONS = -+ -+MULTILIB_OSDIRNAMES = -+ -+MULTILIB_ALIASES = -+ -+MULTILIB_MATCHES = -+ -+# These files must be built for each multilib. -+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crtbeginS.o crtendS.o crtbeginT.o -diff -Nur a/gcc/config/arm/t-symbian b/gcc/config/arm/t-symbian ---- a/gcc/config/arm/t-symbian 2008-06-12 19:29:47.000000000 +0200 -+++ b/gcc/config/arm/t-symbian 2010-01-25 09:50:28.995687913 +0100 -@@ -17,6 +17,9 @@ - LIB2ADDEH = $(srcdir)/unwind-c.c $(srcdir)/config/arm/pr-support.c - LIB2ADDEHDEP = $(UNWIND_H) - -+# Include half-float helpers. -+LIB2FUNCS_STATIC_EXTRA = $(srcdir)/config/arm/fp16.c -+ - # Create a multilib for processors with VFP floating-point, and a - # multilib for those without -- using the soft-float ABI in both - # cases. Symbian OS object should be compiled with interworking -diff -Nur a/gcc/config/arm/t-wrs-linux b/gcc/config/arm/t-wrs-linux ---- a/gcc/config/arm/t-wrs-linux 1970-01-01 01:00:00.000000000 +0100 -+++ b/gcc/config/arm/t-wrs-linux 2010-01-25 09:50:28.995687913 +0100 -@@ -0,0 +1,43 @@ -+# Wind River GNU/Linux Configuration. -+# Copyright (C) 2006, 2007, 2008 -+# Free Software Foundation, Inc. -+# -+# This file is part of GCC. -+# -+# GCC is free software; you can redistribute it and/or modify -+# it under the terms of the GNU General Public License as published by -+# the Free Software Foundation; either version 3, or (at your option) -+# any later version. -+# -+# GCC is distributed in the hope that it will be useful, -+# but WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+# GNU General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with GCC; see the file COPYING3. If not see -+# . -+ -+MULTILIB_OPTIONS = muclibc -+MULTILIB_OPTIONS += tarm926ej-s/tiwmmxt/txscale/tarm920t/tthumb2/tcortex-a8-be8 -+MULTILIB_OPTIONS += mfloat-abi=softfp -+MULTILIB_DIRNAMES = uclibc -+MULTILIB_DIRNAMES += tarm926ej-s tiwmmxt txscale tarm920t thumb2 cortex-a8-be8 -+MULTILIB_DIRNAMES += softfp -+ -+MULTILIB_EXCEPTIONS = *muclibc*/*tarm920t* -+MULTILIB_EXCEPTIONS += *muclibc*/*cortex-a8-be8* -+ -+MULTILIB_EXCEPTIONS += *tiwmmxt*/*mfloat-abi=softfp* -+MULTILIB_EXCEPTIONS += *txscale*/*mfloat-abi=softfp* -+MULTILIB_EXCEPTIONS += *tarm920t*/*mfloat-abi=softfp* -+MULTILIB_EXCEPTIONS += *thumb2*/*mfloat-abi=softfp* -+ -+MULTILIB_MATCHES = tiwmmxt=tiwmmxt2 -+ -+MULTILIB_ALIASES = tcortex-a8-be8=tcortex-a8-be8/mfloat-abi?softfp -+MULTILIB_OSDIRNAMES = -+ -+# These files must be built for each multilib. -+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crtbeginS.o crtendS.o crtbeginT.o -+ -diff -Nur a/gcc/config/arm/uclinux-eabi.h b/gcc/config/arm/uclinux-eabi.h ---- a/gcc/config/arm/uclinux-eabi.h 2009-02-20 16:20:38.000000000 +0100 -+++ b/gcc/config/arm/uclinux-eabi.h 2010-01-25 09:50:28.995687913 +0100 +--- a/gcc/config/arm/uclinux-eabi.h ++++ b/gcc/config/arm/uclinux-eabi.h @@ -50,6 +50,10 @@ #undef ARM_DEFAULT_ABI #define ARM_DEFAULT_ABI ARM_ABI_AAPCS_LINUX @@ -10316,10 +10108,9 @@ diff -Nur a/gcc/config/arm/uclinux-eabi.h b/gcc/config/arm/uclinux-eabi.h /* Clear the instruction cache from `beg' to `end'. This makes an inline system call to SYS_cacheflush. */ #undef CLEAR_INSN_CACHE -diff -Nur a/gcc/config/arm/unwind-arm.c b/gcc/config/arm/unwind-arm.c ---- a/gcc/config/arm/unwind-arm.c 2009-04-10 01:23:07.000000000 +0200 -+++ b/gcc/config/arm/unwind-arm.c 2010-01-25 09:50:28.995687913 +0100 -@@ -1000,7 +1000,6 @@ +--- a/gcc/config/arm/unwind-arm.c ++++ b/gcc/config/arm/unwind-arm.c +@@ -1000,7 +1000,6 @@ __gnu_Unwind_Backtrace(_Unwind_Trace_Fn while (code != _URC_END_OF_STACK && code != _URC_FAILURE); @@ -10327,7 +10118,7 @@ diff -Nur a/gcc/config/arm/unwind-arm.c b/gcc/config/arm/unwind-arm.c restore_non_core_regs (&saved_vrs); return code; } -@@ -1168,6 +1167,9 @@ +@@ -1168,6 +1167,9 @@ __gnu_unwind_pr_common (_Unwind_State st { matched = (void *)(ucbp + 1); rtti = _Unwind_decode_target2 ((_uw) &data[i + 1]); @@ -10337,7 +10128,7 @@ diff -Nur a/gcc/config/arm/unwind-arm.c b/gcc/config/arm/unwind-arm.c if (__cxa_type_match (ucbp, (type_info *) rtti, 0, &matched)) break; -@@ -1197,8 +1199,6 @@ +@@ -1197,8 +1199,6 @@ __gnu_unwind_pr_common (_Unwind_State st ucbp->barrier_cache.bitpattern[4] = (_uw) &data[1]; if (data[0] & uint32_highbit) @@ -10346,7 +10137,7 @@ diff -Nur a/gcc/config/arm/unwind-arm.c b/gcc/config/arm/unwind-arm.c { data += rtti_count + 1; /* Setup for entry to the handler. */ -@@ -1208,6 +1208,8 @@ +@@ -1208,6 +1208,8 @@ __gnu_unwind_pr_common (_Unwind_State st _Unwind_SetGR (context, 0, (_uw) ucbp); return _URC_INSTALL_CONTEXT; } @@ -10355,10 +10146,9 @@ diff -Nur a/gcc/config/arm/unwind-arm.c b/gcc/config/arm/unwind-arm.c } if (data[0] & uint32_highbit) data++; -diff -Nur a/gcc/config/arm/unwind-arm.h b/gcc/config/arm/unwind-arm.h ---- a/gcc/config/arm/unwind-arm.h 2009-04-10 01:23:07.000000000 +0200 -+++ b/gcc/config/arm/unwind-arm.h 2010-01-25 09:50:28.995687913 +0100 -@@ -229,9 +229,10 @@ +--- a/gcc/config/arm/unwind-arm.h ++++ b/gcc/config/arm/unwind-arm.h +@@ -229,9 +229,10 @@ extern "C" { return 0; #if (defined(linux) && !defined(__uClinux__)) || defined(__NetBSD__) @@ -10371,9 +10161,8 @@ diff -Nur a/gcc/config/arm/unwind-arm.h b/gcc/config/arm/unwind-arm.h #elif defined(__symbian__) || defined(__uClinux__) /* Absolute pointer. Nothing more to do. */ #else -diff -Nur a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md ---- a/gcc/config/arm/vec-common.md 2007-08-22 22:32:18.000000000 +0200 -+++ b/gcc/config/arm/vec-common.md 2010-01-25 09:50:28.995687913 +0100 +--- a/gcc/config/arm/vec-common.md ++++ b/gcc/config/arm/vec-common.md @@ -38,6 +38,11 @@ "TARGET_NEON || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))" @@ -10386,9 +10175,8 @@ diff -Nur a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md }) ;; Vector arithmetic. Expanders are blank, then unnamed insns implement -diff -Nur a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md ---- a/gcc/config/arm/vfp.md 2008-09-01 15:40:49.000000000 +0200 -+++ b/gcc/config/arm/vfp.md 2010-01-25 09:50:28.995687913 +0100 +--- a/gcc/config/arm/vfp.md ++++ b/gcc/config/arm/vfp.md @@ -51,7 +51,7 @@ ;; problems because small constants get converted into adds. (define_insn "*arm_movsi_vfp" @@ -11061,10 +10849,9 @@ diff -Nur a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md "@ fcmped%?\\t%P0, %P1 fcmpezd%?\\t%P0" -diff -Nur a/gcc/config/arm/vxworks.h b/gcc/config/arm/vxworks.h ---- a/gcc/config/arm/vxworks.h 2009-02-20 16:20:38.000000000 +0100 -+++ b/gcc/config/arm/vxworks.h 2010-01-25 09:50:28.995687913 +0100 -@@ -97,7 +97,7 @@ +--- a/gcc/config/arm/vxworks.h ++++ b/gcc/config/arm/vxworks.h +@@ -97,7 +97,7 @@ along with GCC; see the file COPYING3. /* There is no default multilib. */ #undef MULTILIB_DEFAULTS @@ -11073,89 +10860,8 @@ diff -Nur a/gcc/config/arm/vxworks.h b/gcc/config/arm/vxworks.h #undef FUNCTION_PROFILER #define FUNCTION_PROFILER VXWORKS_FUNCTION_PROFILER -diff -Nur a/gcc/config/arm/wrs-linux.h b/gcc/config/arm/wrs-linux.h ---- a/gcc/config/arm/wrs-linux.h 1970-01-01 01:00:00.000000000 +0100 -+++ b/gcc/config/arm/wrs-linux.h 2010-01-25 09:50:28.995687913 +0100 -@@ -0,0 +1,76 @@ -+/* Wind River GNU/Linux Configuration. -+ Copyright (C) 2006, 2007, 2008 -+ Free Software Foundation, Inc. -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 3, or (at your option) -+any later version. -+ -+GCC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GCC; see the file COPYING3. If not see -+. */ -+ -+/* Use the ARM926EJ-S by default. */ -+#undef SUBTARGET_CPU_DEFAULT -+#define SUBTARGET_CPU_DEFAULT TARGET_CPU_arm926ejs -+ -+/* Add a -tiwmmxt option for convenience in generating multilibs. -+ This option generates big-endian IWMMXT code. */ -+#undef CC1_SPEC -+#define CC1_SPEC " \ -+ %{tarm926ej-s: -mcpu=arm926ej-s ; \ -+ tiwmmxt: -mcpu=iwmmxt ; \ -+ tiwmmxt2: -mcpu=iwmmxt ; \ -+ txscale: -mcpu=xscale -mbig-endian ; \ -+ tarm920t: -mcpu=arm920t ; \ -+ tthumb2: %{!mcpu=*:%{!march=*:-march=armv6t2}} -mthumb ; \ -+ tcortex-a8-be8: -mcpu=cortex-a8 -mbig-endian -mfloat-abi=softfp \ -+ -mfpu=neon } \ -+ %{txscale:%{mfloat-abi=softfp:%eXScale VFP multilib not provided}} \ -+ %{tarm920t:%{mfloat-abi=softfp:%eARM920T VFP multilib not provided}} \ -+ %{profile:-p}" -+ -+/* Since the ARM926EJ-S is the default processor, we do not need to -+ provide an explicit multilib for that processor. */ -+#undef MULTILIB_DEFAULTS -+#define MULTILIB_DEFAULTS \ -+ { "tarm926ej-s" } -+ -+/* The GLIBC headers are in /usr/include, relative to the sysroot; the -+ uClibc headers are in /uclibc/usr/include. */ -+#undef SYSROOT_HEADERS_SUFFIX_SPEC -+#define SYSROOT_HEADERS_SUFFIX_SPEC \ -+ "%{muclibc:/uclibc}" -+ -+/* Translate -tiwmmxt appropriately for the assembler. The -meabi=5 -+ option is the relevant part of SUBTARGET_EXTRA_ASM_SPEC in bpabi.h. */ -+#undef SUBTARGET_EXTRA_ASM_SPEC -+#define SUBTARGET_EXTRA_ASM_SPEC \ -+ "%{tiwmmxt2:-mcpu=iwmmxt2} %{tiwmmxt:-mcpu=iwmmxt} %{txscale:-mcpu=xscale -EB} %{tcortex-a8-be8:-mcpu=cortex-a8 -EB} -meabi=5" -+ -+/* Translate -tiwmmxt for the linker. */ -+#undef SUBTARGET_EXTRA_LINK_SPEC -+#define SUBTARGET_EXTRA_LINK_SPEC \ -+ " %{tiwmmxt:-m armelf_linux_eabi ; \ -+ txscale:-m armelfb_linux_eabi ; \ -+ tcortex-a8-be8:-m armelfb_linux_eabi %{!r:--be8} ; \ -+ : -m armelf_linux_eabi}" -+ -+/* The various C libraries each have their own subdirectory. */ -+#undef SYSROOT_SUFFIX_SPEC -+#define SYSROOT_SUFFIX_SPEC \ -+ "%{muclibc:/uclibc}%{tiwmmxt:/tiwmmxt ; \ -+ tiwmmxt2:/tiwmmxt ; \ -+ txscale:/txscale ; \ -+ tarm920t:/tarm920t ; \ -+ tthumb2:/thumb2 ; \ -+ tcortex-a8-be8:/cortex-a8-be8}%{!tthumb2:%{!tcortex-a8-be8:%{mfloat-abi=softfp:/softfp}}}" -+ -diff -Nur a/gcc/config/i386/atom.md b/gcc/config/i386/atom.md ---- a/gcc/config/i386/atom.md 1970-01-01 01:00:00.000000000 +0100 -+++ b/gcc/config/i386/atom.md 2010-01-25 09:50:28.995687913 +0100 +--- /dev/null ++++ b/gcc/config/i386/atom.md @@ -0,0 +1,795 @@ +;; Atom Scheduling +;; Copyright (C) 2009 Free Software Foundation, Inc. @@ -11952,9 +11658,8 @@ diff -Nur a/gcc/config/i386/atom.md b/gcc/config/i386/atom.md + atom_ishift_mem, atom_ishift1_mem, + atom_rotate_mem, atom_rotate1_mem" + "ix86_dep_by_shift_count") -diff -Nur a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h ---- a/gcc/config/i386/cpuid.h 2009-04-10 01:23:07.000000000 +0200 -+++ b/gcc/config/i386/cpuid.h 2010-01-25 09:50:28.995687913 +0100 +--- a/gcc/config/i386/cpuid.h ++++ b/gcc/config/i386/cpuid.h @@ -29,6 +29,7 @@ #define bit_CMPXCHG16B (1 << 13) #define bit_SSE4_1 (1 << 19) @@ -11963,105 +11668,9 @@ diff -Nur a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h #define bit_POPCNT (1 << 23) #define bit_AES (1 << 25) #define bit_XSAVE (1 << 26) -diff -Nur a/gcc/config/i386/cs-linux.h b/gcc/config/i386/cs-linux.h ---- a/gcc/config/i386/cs-linux.h 1970-01-01 01:00:00.000000000 +0100 -+++ b/gcc/config/i386/cs-linux.h 2010-01-25 09:50:28.995687913 +0100 -@@ -0,0 +1,41 @@ -+/* Sourcery G++ IA32 GNU/Linux Configuration. -+ Copyright (C) 2007 -+ Free Software Foundation, Inc. -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 3, or (at your option) -+any later version. -+ -+GCC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GCC; see the file COPYING3. If not see -+. */ -+ -+/* This configuration may be used either with the system glibc (in -+ system32 and system64 subdirectories) or with the included glibc -+ (in the sgxx-glibc subdirectory). */ -+ -+#undef SYSROOT_SUFFIX_SPEC -+#define SYSROOT_SUFFIX_SPEC \ -+ "%{msgxx-glibc:/sgxx-glibc ; \ -+ m64:/system64 ; \ -+ mrhel3:/system64 ; \ -+ mrh73:/system32-old ; \ -+ :/system32}" -+ -+#undef SYSROOT_HEADERS_SUFFIX_SPEC -+#define SYSROOT_HEADERS_SUFFIX_SPEC SYSROOT_SUFFIX_SPEC -+ -+/* See mips/wrs-linux.h for details on this use of -+ STARTFILE_PREFIX_SPEC. */ -+#undef STARTFILE_PREFIX_SPEC -+#define STARTFILE_PREFIX_SPEC \ -+ "%{m64: /usr/local/lib64/ /lib64/ /usr/lib64/} \ -+ %{!m64: /usr/local/lib/ /lib/ /usr/lib/}" -diff -Nur a/gcc/config/i386/cs-linux-lite.h b/gcc/config/i386/cs-linux-lite.h ---- a/gcc/config/i386/cs-linux-lite.h 1970-01-01 01:00:00.000000000 +0100 -+++ b/gcc/config/i386/cs-linux-lite.h 2010-01-25 09:50:28.995687913 +0100 -@@ -0,0 +1,31 @@ -+/* Sourcery G++ Lite IA32 GNU/Linux Configuration. -+ Copyright (C) 2009 -+ Free Software Foundation, Inc. -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 3, or (at your option) -+any later version. -+ -+GCC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GCC; see the file COPYING3. If not see -+. */ -+ -+#undef SYSROOT_SUFFIX_SPEC -+#define SYSROOT_SUFFIX_SPEC \ -+ "%{march=atom:%{!m64:/atom} ; \ -+ march=core2:%{m64:/core2}}" -+ -+/* See mips/wrs-linux.h for details on this use of -+ STARTFILE_PREFIX_SPEC. */ -+#undef STARTFILE_PREFIX_SPEC -+#define STARTFILE_PREFIX_SPEC \ -+ "%{m64: /usr/local/lib64/ /lib64/ /usr/lib64/} \ -+ %{!m64: /usr/local/lib/ /lib/ /usr/lib/}" -diff -Nur a/gcc/config/i386/cs-linux.opt b/gcc/config/i386/cs-linux.opt ---- a/gcc/config/i386/cs-linux.opt 1970-01-01 01:00:00.000000000 +0100 -+++ b/gcc/config/i386/cs-linux.opt 2010-01-25 09:50:28.995687913 +0100 -@@ -0,0 +1,11 @@ -+; Additional options for Sourcery G++. -+ -+mrh73 -+Target Undocumented -+ -+mrhel3 -+Target Undocumented -+ -+msgxx-glibc -+Target -+Use included version of GLIBC -diff -Nur a/gcc/config/i386/cygming.h b/gcc/config/i386/cygming.h ---- a/gcc/config/i386/cygming.h 2009-07-12 17:56:41.000000000 +0200 -+++ b/gcc/config/i386/cygming.h 2010-01-25 09:50:28.995687913 +0100 -@@ -34,7 +34,7 @@ +--- a/gcc/config/i386/cygming.h ++++ b/gcc/config/i386/cygming.h +@@ -34,7 +34,7 @@ along with GCC; see the file COPYING3. #endif #undef TARGET_64BIT_MS_ABI @@ -12070,7 +11679,7 @@ diff -Nur a/gcc/config/i386/cygming.h b/gcc/config/i386/cygming.h #undef DEFAULT_ABI #define DEFAULT_ABI (TARGET_64BIT ? MS_ABI : SYSV_ABI) -@@ -203,7 +203,7 @@ +@@ -202,7 +202,7 @@ do { \ #define CHECK_STACK_LIMIT 4000 #undef STACK_BOUNDARY @@ -12079,10 +11688,9 @@ diff -Nur a/gcc/config/i386/cygming.h b/gcc/config/i386/cygming.h /* By default, target has a 80387, uses IEEE compatible arithmetic, returns float values in the 387 and needs stack probes. -diff -Nur a/gcc/config/i386/cygming.opt b/gcc/config/i386/cygming.opt ---- a/gcc/config/i386/cygming.opt 2007-08-02 12:49:31.000000000 +0200 -+++ b/gcc/config/i386/cygming.opt 2010-01-25 09:50:28.995687913 +0100 -@@ -45,3 +45,7 @@ +--- a/gcc/config/i386/cygming.opt ++++ b/gcc/config/i386/cygming.opt +@@ -45,3 +45,7 @@ Set Windows defines mwindows Target Create GUI application @@ -12090,10 +11698,9 @@ diff -Nur a/gcc/config/i386/cygming.opt b/gcc/config/i386/cygming.opt +mpe-aligned-commons +Target Var(use_pe_aligned_common) Init(HAVE_GAS_ALIGNED_COMM) +Use the GNU extension to the PE format for aligned common data -diff -Nur a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c ---- a/gcc/config/i386/driver-i386.c 2009-05-27 16:54:00.000000000 +0200 -+++ b/gcc/config/i386/driver-i386.c 2010-01-25 09:50:29.005686600 +0100 -@@ -378,7 +378,7 @@ +--- a/gcc/config/i386/driver-i386.c ++++ b/gcc/config/i386/driver-i386.c +@@ -378,7 +378,7 @@ const char *host_detect_local_cpu (int a /* Extended features */ unsigned int has_lahf_lm = 0, has_sse4a = 0; unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0; @@ -12102,7 +11709,7 @@ diff -Nur a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0; unsigned int has_pclmul = 0; -@@ -398,9 +398,22 @@ +@@ -398,9 +398,22 @@ const char *host_detect_local_cpu (int a __cpuid (1, eax, ebx, ecx, edx); @@ -12126,7 +11733,7 @@ diff -Nur a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c has_sse3 = ecx & bit_SSE3; has_ssse3 = ecx & bit_SSSE3; -@@ -408,6 +421,7 @@ +@@ -408,6 +421,7 @@ const char *host_detect_local_cpu (int a has_sse4_2 = ecx & bit_SSE4_2; has_avx = ecx & bit_AVX; has_cmpxchg16b = ecx & bit_CMPXCHG16B; @@ -12134,7 +11741,7 @@ diff -Nur a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c has_popcnt = ecx & bit_POPCNT; has_aes = ecx & bit_AES; has_pclmul = ecx & bit_PCLMUL; -@@ -505,8 +519,8 @@ +@@ -505,8 +519,8 @@ const char *host_detect_local_cpu (int a break; case PROCESSOR_PENTIUMPRO: if (has_longmode) @@ -12145,7 +11752,7 @@ diff -Nur a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c else if (arch) { if (has_sse3) -@@ -597,6 +611,8 @@ +@@ -597,6 +611,8 @@ const char *host_detect_local_cpu (int a options = concat (options, "-mcx16 ", NULL); if (has_lahf_lm) options = concat (options, "-msahf ", NULL); @@ -12154,10 +11761,56 @@ diff -Nur a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c if (has_aes) options = concat (options, "-maes ", NULL); if (has_pclmul) -diff -Nur a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c ---- a/gcc/config/i386/i386.c 2009-07-21 09:22:51.000000000 +0200 -+++ b/gcc/config/i386/i386.c 2010-01-25 09:50:29.005686600 +0100 -@@ -1036,6 +1036,79 @@ +--- a/gcc/config/i386/i386-c.c ++++ b/gcc/config/i386/i386-c.c +@@ -119,6 +119,10 @@ ix86_target_macros_internal (int isa_fla + def_or_undef (parse_in, "__core2"); + def_or_undef (parse_in, "__core2__"); + break; ++ case PROCESSOR_ATOM: ++ def_or_undef (parse_in, "__atom"); ++ def_or_undef (parse_in, "__atom__"); ++ break; + /* use PROCESSOR_max to not set/unset the arch macro. */ + case PROCESSOR_max: + break; +@@ -187,6 +191,9 @@ ix86_target_macros_internal (int isa_fla + case PROCESSOR_CORE2: + def_or_undef (parse_in, "__tune_core2__"); + break; ++ case PROCESSOR_ATOM: ++ def_or_undef (parse_in, "__tune_atom__"); ++ break; + case PROCESSOR_GENERIC32: + case PROCESSOR_GENERIC64: + break; +--- a/gcc/config/i386/i386-protos.h ++++ b/gcc/config/i386/i386-protos.h +@@ -86,6 +86,9 @@ extern void ix86_fixup_binary_operands_n + extern void ix86_expand_binary_operator (enum rtx_code, + enum machine_mode, rtx[]); + extern int ix86_binary_operator_ok (enum rtx_code, enum machine_mode, rtx[]); ++extern bool ix86_lea_for_add_ok (enum rtx_code, rtx, rtx[]); ++extern bool ix86_dep_by_shift_count (const_rtx set_insn, const_rtx use_insn); ++extern bool ix86_agi_dependent (rtx set_insn, rtx use_insn); + extern void ix86_expand_unary_operator (enum rtx_code, enum machine_mode, + rtx[]); + extern rtx ix86_build_const_vector (enum machine_mode, bool, rtx); +@@ -140,9 +143,8 @@ extern int ix86_function_arg_boundary (e + extern bool ix86_sol10_return_in_memory (const_tree,const_tree); + extern rtx ix86_force_to_memory (enum machine_mode, rtx); + extern void ix86_free_from_memory (enum machine_mode); +-extern int ix86_cfun_abi (void); +-extern int ix86_function_abi (const_tree); +-extern int ix86_function_type_abi (const_tree); ++extern enum calling_abi ix86_cfun_abi (void); ++extern enum calling_abi ix86_function_type_abi (const_tree); + extern void ix86_call_abi_override (const_tree); + extern tree ix86_fn_abi_va_list (tree); + extern tree ix86_canonical_va_list_type (tree); +--- a/gcc/config/i386/i386.c ++++ b/gcc/config/i386/i386.c +@@ -1036,6 +1036,79 @@ struct processor_costs core2_cost = { 1, /* cond_not_taken_branch_cost. */ }; @@ -12237,7 +11890,7 @@ diff -Nur a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c /* Generic64 should produce code tuned for Nocona and K8. */ static const struct processor_costs generic64_cost = { -@@ -1194,6 +1267,7 @@ +@@ -1194,6 +1267,7 @@ const struct processor_costs *ix86_cost #define m_PENT4 (1<