From: Paul Wassi <p.wassi@gmx.at>
Date: Fri, 4 Jan 2019 21:38:17 +0000 (+0100)
Subject: ar71xx: fix TL-MR3220-v2 switch port order
X-Git-Tag: v19.07.0-rc1~1313
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=78277ec162b06e859923936ee00d02920b4ccc6f;p=openwrt%2Fstaging%2Fpepe2k.git

ar71xx: fix TL-MR3220-v2 switch port order

Fix the switch port order for proper display on high
level interfaces.

Signed-off-by: Paul Wassi <p.wassi@gmx.at>
---

diff --git a/target/linux/ar71xx/base-files/etc/board.d/02_network b/target/linux/ar71xx/base-files/etc/board.d/02_network
index b761c7c920..13dfd2b000 100755
--- a/target/linux/ar71xx/base-files/etc/board.d/02_network
+++ b/target/linux/ar71xx/base-files/etc/board.d/02_network
@@ -41,7 +41,6 @@ ar71xx_setup_interfaces()
 	tew-712br|\
 	tew-732br|\
 	tl-mr3220|\
-	tl-mr3220-v2|\
 	tl-mr3420|\
 	tl-wdr3320-v2|\
 	tl-wdr3500|\
@@ -520,6 +519,7 @@ ar71xx_setup_interfaces()
 		ucidef_add_switch "switch0" \
 			"1:lan" "2:lan" "3:lan" "4:lan" "0:wan" "9@eth0"
 		;;
+	tl-mr3220-v2|\
 	tl-wr741nd-v4)
 		ucidef_set_interfaces_lan_wan "eth0.1" "eth1"
 		ucidef_add_switch "switch0" \