From: Zoltan HERPAI Date: Sat, 25 May 2024 22:51:10 +0000 (+0200) Subject: kernel/d1: Restore kernel files for v6.1 X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=766570d60b08a494ae1989af45121fcfe3467fee;p=openwrt%2Fstaging%2Fstintel.git kernel/d1: Restore kernel files for v6.1 This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Zoltan HERPAI --- diff --git a/target/linux/d1/config-6.1 b/target/linux/d1/config-6.1 new file mode 100644 index 0000000000..ef2112f706 --- /dev/null +++ b/target/linux/d1/config-6.1 @@ -0,0 +1,396 @@ +CONFIG_64BIT=y +# CONFIG_AHCI_SUNXI is not set +CONFIG_ARCH_CLOCKSOURCE_INIT=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_RV64I=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_SUNXI=y +CONFIG_ARCH_WANTS_THP_SWAP=y +CONFIG_ASN1=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_MQ_PCI=y +CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y +CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_CC_NO_ARRAY_BOUNDS=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CLZ_TAB=y +CONFIG_CMODEL_MEDANY=y +# CONFIG_CMODEL_MEDLOW is not set +CONFIG_COMMON_CLK=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +# CONFIG_COMPAT_32BIT_TIME is not set +CONFIG_COMPAT_BRK=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_COREDUMP=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_CPU_ISOLATION=y +CONFIG_CPU_RMAP=y +CONFIG_CRC16=y +# CONFIG_CRC32_SARWATE is not set +CONFIG_CRC32_SLICEBY8=y +CONFIG_CRC7=y +CONFIG_CRC_ITU_T=y +CONFIG_CRYPTO_DEV_ALLWINNER=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DMADEVICES=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +CONFIG_DMA_SUN6I=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DTC=y +CONFIG_DWMAC_GENERIC=y +CONFIG_DWMAC_SUN8I=y +CONFIG_DWMAC_SUNXI=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EFI=y +CONFIG_EFIVAR_FS=m +# CONFIG_EFI_BOOTLOADER_CONTROL is not set +# CONFIG_EFI_CAPSULE_LOADER is not set +# CONFIG_EFI_COCO_SECRET is not set +# CONFIG_EFI_DISABLE_PCI_DMA is not set +# CONFIG_EFI_DISABLE_RUNTIME is not set +CONFIG_EFI_EARLYCON=y +CONFIG_EFI_ESRT=y +CONFIG_EFI_GENERIC_STUB=y +CONFIG_EFI_PARAMS_FROM_FDT=y +CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_STUB=y +# CONFIG_EFI_TEST is not set +# CONFIG_EFI_ZBOOT is not set +CONFIG_ELF_CORE=y +# CONFIG_ERRATA_SIFIVE is not set +CONFIG_ERRATA_THEAD=y +CONFIG_ERRATA_THEAD_CMO=y +CONFIG_ERRATA_THEAD_PBMT=y +CONFIG_EXT4_FS=y +CONFIG_EXTCON=y +CONFIG_FAILOVER=y +CONFIG_FHANDLE=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FONT_8x16=y +CONFIG_FONT_AUTOSELECT=y +CONFIG_FONT_SUPPORT=y +CONFIG_FPU=y +CONFIG_FRAME_POINTER=y +CONFIG_FRAME_WARN=2048 +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IOREMAP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GLOB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_PCF857X=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HID=y +CONFIG_HID_GENERIC=y +CONFIG_HVC_DRIVER=y +CONFIG_HVC_RISCV_SBI=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_MV64XXX=y +CONFIG_I2C_OCORES=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INPUT=y +CONFIG_IOMMU_API=y +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set +CONFIG_IOMMU_DEFAULT_DMA_STRICT=y +# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set +CONFIG_IOMMU_SUPPORT=y +CONFIG_IO_URING=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_KALLSYMS=y +# CONFIG_KEYBOARD_SUN4I_LRADC is not set +# CONFIG_LEDS_PWM_MULTICOLOR is not set +# CONFIG_LEDS_SUN50I_A100 is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +CONFIG_LIBFDT=y +CONFIG_LOCALVERSION_AUTO=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_MAILBOX=y +# CONFIG_MAILBOX_TEST is not set +CONFIG_MDIO_BUS=y +CONFIG_MDIO_BUS_MUX=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +# CONFIG_MDIO_SUN4I is not set +CONFIG_MEMFD_CREATE=y +CONFIG_MFD_AXP20X=y +CONFIG_MFD_AXP20X_I2C=y +CONFIG_MFD_CORE=y +# CONFIG_MFD_SUN4I_GPADC is not set +CONFIG_MFD_SUN6I_PRCM=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_SUNXI=y +CONFIG_MMIOWB=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_MUSB_PIO_ONLY is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_VENDOR_ALLWINNER=y +CONFIG_NLS=y +# CONFIG_NONPORTABLE is not set +CONFIG_NOP_USB_XCEIV=y +CONFIG_NR_CPUS=8 +CONFIG_NVMEM=y +CONFIG_NVMEM_SUNXI_SID=y +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_DMA_DEFAULT_COHERENT=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IOMMU=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OID_REGISTRY=y +CONFIG_PADATA=y +CONFIG_PAGE_OFFSET=0xff60000000000000 +CONFIG_PAGE_POOL=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +# CONFIG_PAGE_TABLE_CHECK is not set +CONFIG_PANIC_TIMEOUT=0 +CONFIG_PCPU_DEV_REFCNT=y +CONFIG_PGTABLE_LEVELS=5 +CONFIG_PHYLIB=y +CONFIG_PHYLINK=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_PHY_SUN4I_USB=y +CONFIG_PHY_SUN50I_USB3=y +# CONFIG_PHY_SUN6I_MIPI_DPHY is not set +# CONFIG_PHY_SUN9I_USB is not set +CONFIG_PINCTRL=y +CONFIG_PINCTRL_SUN20I_D1=y +# CONFIG_PINCTRL_SUN4I_A10 is not set +# CONFIG_PINCTRL_SUN50I_A100 is not set +# CONFIG_PINCTRL_SUN50I_A100_R is not set +# CONFIG_PINCTRL_SUN50I_A64 is not set +# CONFIG_PINCTRL_SUN50I_A64_R is not set +# CONFIG_PINCTRL_SUN50I_H5 is not set +# CONFIG_PINCTRL_SUN50I_H6 is not set +# CONFIG_PINCTRL_SUN50I_H616 is not set +# CONFIG_PINCTRL_SUN50I_H616_R is not set +# CONFIG_PINCTRL_SUN50I_H6_R is not set +# CONFIG_PINCTRL_SUN5I is not set +# CONFIG_PINCTRL_SUN6I_A31 is not set +# CONFIG_PINCTRL_SUN6I_A31_R is not set +# CONFIG_PINCTRL_SUN8I_A23 is not set +# CONFIG_PINCTRL_SUN8I_A23_R is not set +# CONFIG_PINCTRL_SUN8I_A33 is not set +# CONFIG_PINCTRL_SUN8I_A83T is not set +# CONFIG_PINCTRL_SUN8I_A83T_R is not set +# CONFIG_PINCTRL_SUN8I_H3 is not set +# CONFIG_PINCTRL_SUN8I_H3_R is not set +# CONFIG_PINCTRL_SUN8I_V3S is not set +# CONFIG_PINCTRL_SUN9I_A80 is not set +# CONFIG_PINCTRL_SUN9I_A80_R is not set +CONFIG_PINCTRL_SUNXI=y +CONFIG_PORTABLE=y +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_POWER_SUPPLY=y +CONFIG_PPS=y +CONFIG_PREEMPT_NONE_BUILD=y +CONFIG_PRINTK_TIME=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_PWM=y +# CONFIG_PWM_CLK is not set +# CONFIG_PWM_SIFIVE is not set +# CONFIG_PWM_SUN4I is not set +# CONFIG_PWM_SUN8I_V536 is not set +CONFIG_PWM_SYSFS=y +# CONFIG_PWM_XILINX is not set +CONFIG_RATIONAL=y +CONFIG_RCU_TRACE=y +CONFIG_REALTEK_PHY=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_IRQ=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_AXP20X is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_SUN20I=y +# CONFIG_RESET_ATTACK_MITIGATION is not set +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_SIMPLE=y +CONFIG_RESET_SUNXI=y +CONFIG_RISCV=y +CONFIG_RISCV_ALTERNATIVE=y +CONFIG_RISCV_ALTERNATIVE_EARLY=y +CONFIG_RISCV_BOOT_SPINWAIT=y +CONFIG_RISCV_DMA_NONCOHERENT=y +CONFIG_RISCV_INTC=y +CONFIG_RISCV_ISA_C=y +CONFIG_RISCV_ISA_SVPBMT=y +CONFIG_RISCV_ISA_ZICBOM=y +CONFIG_RISCV_SBI=y +CONFIG_RISCV_SBI_V01=y +CONFIG_RISCV_TIMER=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_EFI is not set +CONFIG_RTC_DRV_GOLDFISH=y +CONFIG_RTC_DRV_SUN6I=y +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SCHED_DEBUG=y +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_DWLIB=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_EARLYCON_RISCV_SBI=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SG_POOL=y +CONFIG_SIFIVE_PLIC=y +CONFIG_SLUB_DEBUG=y +CONFIG_SMP=y +# CONFIG_SND_SUN20I_CODEC is not set +# CONFIG_SND_SUN4I_I2S is not set +# CONFIG_SND_SUN50I_DMIC is not set +CONFIG_SOCK_RX_QUEUE_MAPPING=y +# CONFIG_SOC_MICROCHIP_POLARFIRE is not set +# CONFIG_SOC_SIFIVE is not set +# CONFIG_SOC_STARFIVE is not set +# CONFIG_SOC_VIRT is not set +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +# CONFIG_SPI_SUN4I is not set +CONFIG_SPI_SUN6I=y +CONFIG_SRCU=y +CONFIG_STACKDEPOT=y +CONFIG_STACKTRACE=y +CONFIG_STMMAC_ETH=y +CONFIG_STMMAC_PLATFORM=y +CONFIG_SUN20I_D1_CCU=y +CONFIG_SUN20I_D1_R_CCU=y +# CONFIG_SUN4I_EMAC is not set +CONFIG_SUN4I_TIMER=y +CONFIG_SUN50I_IOMMU=y +CONFIG_SUN6I_MSGBOX=y +CONFIG_SUN6I_RTC_CCU=y +CONFIG_SUN8I_DE2_CCU=y +# CONFIG_SUN8I_R_CCU is not set +# CONFIG_SUN8I_THERMAL is not set +CONFIG_SUNXI_CCU=y +# CONFIG_SUNXI_RSB is not set +CONFIG_SUNXI_SRAM=y +CONFIG_SUNXI_WATCHDOG=y +CONFIG_SWIOTLB=y +CONFIG_SWPHY=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +# CONFIG_SYSFB_SIMPLEFB is not set +CONFIG_SYSFS_SYSCALL=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TOOLCHAIN_HAS_ZICBOM=y +CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE=y +CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y +CONFIG_TRACE_CLOCK=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_TUNE_GENERIC=y +# CONFIG_UACCE is not set +CONFIG_UCS2_STRING=y +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_HID=y +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_MUSB_HOST=y +CONFIG_USB_MUSB_SUNXI=y +CONFIG_USB_NET_DRIVERS=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_PHY=y +CONFIG_USB_SUPPORT=y +# CONFIG_USB_UHCI_HCD is not set +CONFIG_USB_XHCI_HCD=y +# CONFIG_USB_XHCI_PLATFORM is not set +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +# CONFIG_VHOST_MENU is not set +# CONFIG_VIRTIO_MENU is not set +CONFIG_VMAP_STACK=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_WATCHDOG_CORE=y +CONFIG_XPS=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA32=y diff --git a/target/linux/d1/patches-6.1/0001-dt-bindings-net-bluetooth-realtek-Add-RTL8723DS.patch b/target/linux/d1/patches-6.1/0001-dt-bindings-net-bluetooth-realtek-Add-RTL8723DS.patch new file mode 100644 index 0000000000..6636cddde6 --- /dev/null +++ b/target/linux/d1/patches-6.1/0001-dt-bindings-net-bluetooth-realtek-Add-RTL8723DS.patch @@ -0,0 +1,32 @@ +From e663d510ae6a81694a8e9e1ce07bb80dd6b77558 Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Sun, 24 Jul 2022 17:12:07 -0500 +Subject: [PATCH 001/117] dt-bindings: net: bluetooth: realtek: Add RTL8723DS + +RTL8723DS is another version of the RTL8723 WiFi + Bluetooth chip. It is +already supported by the hci_uart/btrtl driver. Document the compatible. + +Series-to: Marcel Holtmann +Series-to: Johan Hedberg +Series-to: Luiz Augusto von Dentz +Series-to: David S. Miller +Series-to: Eric Dumazet +Series-to: Jakub Kicinski +Series-to: Paolo Abeni +Series-cc: linux-bluetooth@vger.kernel.org + +Signed-off-by: Samuel Holland +--- + Documentation/devicetree/bindings/net/realtek-bluetooth.yaml | 1 + + 1 file changed, 1 insertion(+) + +--- a/Documentation/devicetree/bindings/net/realtek-bluetooth.yaml ++++ b/Documentation/devicetree/bindings/net/realtek-bluetooth.yaml +@@ -20,6 +20,7 @@ properties: + enum: + - realtek,rtl8723bs-bt + - realtek,rtl8723cs-bt ++ - realtek,rtl8723ds-bt + - realtek,rtl8822cs-bt + + device-wake-gpios: diff --git a/target/linux/d1/patches-6.1/0002-clk-sunxi-ng-mp-Avoid-computing-the-rate-twice.patch b/target/linux/d1/patches-6.1/0002-clk-sunxi-ng-mp-Avoid-computing-the-rate-twice.patch new file mode 100644 index 0000000000..22d4885e29 --- /dev/null +++ b/target/linux/d1/patches-6.1/0002-clk-sunxi-ng-mp-Avoid-computing-the-rate-twice.patch @@ -0,0 +1,51 @@ +From 74492b9ecd874496578693d9985649665b560308 Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Sun, 7 Aug 2022 20:08:49 -0500 +Subject: [PATCH 002/117] clk: sunxi-ng: mp: Avoid computing the rate twice + +ccu_mp_find_best() already computes a best_rate at the same time as the +best m and p factors. Return it so the caller does not need to duplicate +the division. + +Series-to: Chen-Yu Tsai +Series-to: Jernej Skrabec + +Signed-off-by: Samuel Holland +--- + drivers/clk/sunxi-ng/ccu_mp.c | 11 ++++++----- + 1 file changed, 6 insertions(+), 5 deletions(-) + +--- a/drivers/clk/sunxi-ng/ccu_mp.c ++++ b/drivers/clk/sunxi-ng/ccu_mp.c +@@ -10,9 +10,9 @@ + #include "ccu_gate.h" + #include "ccu_mp.h" + +-static void ccu_mp_find_best(unsigned long parent, unsigned long rate, +- unsigned int max_m, unsigned int max_p, +- unsigned int *m, unsigned int *p) ++static unsigned long ccu_mp_find_best(unsigned long parent, unsigned long rate, ++ unsigned int max_m, unsigned int max_p, ++ unsigned int *m, unsigned int *p) + { + unsigned long best_rate = 0; + unsigned int best_m = 0, best_p = 0; +@@ -35,6 +35,8 @@ static void ccu_mp_find_best(unsigned lo + + *m = best_m; + *p = best_p; ++ ++ return best_rate; + } + + static unsigned long ccu_mp_find_best_with_parent_adj(struct clk_hw *hw, +@@ -109,8 +111,7 @@ static unsigned long ccu_mp_round_rate(s + max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1); + + if (!clk_hw_can_set_rate_parent(&cmp->common.hw)) { +- ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p); +- rate = *parent_rate / p / m; ++ rate = ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p); + } else { + rate = ccu_mp_find_best_with_parent_adj(hw, parent_rate, rate, + max_m, max_p); diff --git a/target/linux/d1/patches-6.1/0003-dt-bindings-net-sun8i-emac-Add-phy-supply-property.patch b/target/linux/d1/patches-6.1/0003-dt-bindings-net-sun8i-emac-Add-phy-supply-property.patch new file mode 100644 index 0000000000..ec3f553b51 --- /dev/null +++ b/target/linux/d1/patches-6.1/0003-dt-bindings-net-sun8i-emac-Add-phy-supply-property.patch @@ -0,0 +1,22 @@ +From 7185f7b424dfd9082bf0859a60b98a2dbd784ed6 Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Mon, 5 Sep 2022 16:45:44 -0500 +Subject: [PATCH 003/117] dt-bindings: net: sun8i-emac: Add phy-supply property + +Signed-off-by: Samuel Holland +--- + .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml ++++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml +@@ -40,6 +40,9 @@ properties: + clock-names: + const: stmmaceth + ++ phy-supply: ++ description: PHY regulator ++ + syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: diff --git a/target/linux/d1/patches-6.1/0004-dt-bindings-net-sun8i-emac-Add-properties-from-dwmac.patch b/target/linux/d1/patches-6.1/0004-dt-bindings-net-sun8i-emac-Add-properties-from-dwmac.patch new file mode 100644 index 0000000000..9ac335ae3e --- /dev/null +++ b/target/linux/d1/patches-6.1/0004-dt-bindings-net-sun8i-emac-Add-properties-from-dwmac.patch @@ -0,0 +1,32 @@ +From d20bb97fac77e4d88424043627c769427fc0d35e Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Mon, 5 Sep 2022 16:46:34 -0500 +Subject: [PATCH 004/117] dt-bindings: net: sun8i-emac: Add properties from + dwmac binding + +Signed-off-by: Samuel Holland +--- + .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml ++++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml +@@ -40,6 +40,9 @@ properties: + clock-names: + const: stmmaceth + ++ resets: true ++ reset-names: true ++ + phy-supply: + description: PHY regulator + +@@ -49,6 +52,8 @@ properties: + Phandle to the device containing the EMAC or GMAC clock + register + ++ mdio: true ++ + required: + - compatible + - reg diff --git a/target/linux/d1/patches-6.1/0005-dt-bindings-display-sun8i-a83t-dw-hdmi-Remove-phy-ce.patch b/target/linux/d1/patches-6.1/0005-dt-bindings-display-sun8i-a83t-dw-hdmi-Remove-phy-ce.patch new file mode 100644 index 0000000000..402f291674 --- /dev/null +++ b/target/linux/d1/patches-6.1/0005-dt-bindings-display-sun8i-a83t-dw-hdmi-Remove-phy-ce.patch @@ -0,0 +1,28 @@ +From c99d1e681dc460892004054a314fa7f929f43490 Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Sat, 13 Aug 2022 10:45:59 -0500 +Subject: [PATCH 005/117] dt-bindings: display: sun8i-a83t-dw-hdmi: Remove + #phy-cells + +This device is not a PHY, and none of the nodes using this schema +contain a #phy-cells property. Likely this was a copy/paste error +introduced during the YAML conversion. + +Fixes: f5a98bfe7b37 ("dt-bindings: display: Convert Allwinner display pipeline to schemas") +Signed-off-by: Samuel Holland +--- + .../bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml | 3 --- + 1 file changed, 3 deletions(-) + +--- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml ++++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml +@@ -20,9 +20,6 @@ maintainers: + - Maxime Ripard + + properties: +- "#phy-cells": +- const: 0 +- + compatible: + oneOf: + - const: allwinner,sun8i-a83t-dw-hdmi diff --git a/target/linux/d1/patches-6.1/0006-dt-bindings-display-Add-D1-HDMI-compatibles.patch b/target/linux/d1/patches-6.1/0006-dt-bindings-display-Add-D1-HDMI-compatibles.patch new file mode 100644 index 0000000000..b62e45c09f --- /dev/null +++ b/target/linux/d1/patches-6.1/0006-dt-bindings-display-Add-D1-HDMI-compatibles.patch @@ -0,0 +1,34 @@ +From e214b79d45cccdd0cfe839e54da2b3c82b6c6be4 Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Thu, 31 Mar 2022 23:43:15 -0500 +Subject: [PATCH 006/117] dt-bindings: display: Add D1 HDMI compatibles + +Allwinner D1 contains a DesignWare HDMI controller with some changes in +platform integration, and a new HDMI PHY. Add their compatibles. + +Signed-off-by: Samuel Holland +--- + .../bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml | 1 + + .../bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml | 1 + + 2 files changed, 2 insertions(+) + +--- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml ++++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml +@@ -29,6 +29,7 @@ properties: + - enum: + - allwinner,sun8i-h3-dw-hdmi + - allwinner,sun8i-r40-dw-hdmi ++ - allwinner,sun20i-d1-dw-hdmi + - allwinner,sun50i-a64-dw-hdmi + - const: allwinner,sun8i-a83t-dw-hdmi + +--- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml ++++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml +@@ -19,6 +19,7 @@ properties: + - allwinner,sun8i-a83t-hdmi-phy + - allwinner,sun8i-h3-hdmi-phy + - allwinner,sun8i-r40-hdmi-phy ++ - allwinner,sun20i-d1-hdmi-phy + - allwinner,sun50i-a64-hdmi-phy + - allwinner,sun50i-h6-hdmi-phy + diff --git a/target/linux/d1/patches-6.1/0007-drm-sun4i-Add-support-for-D1-HDMI.patch b/target/linux/d1/patches-6.1/0007-drm-sun4i-Add-support-for-D1-HDMI.patch new file mode 100644 index 0000000000..b55c3a3f20 --- /dev/null +++ b/target/linux/d1/patches-6.1/0007-drm-sun4i-Add-support-for-D1-HDMI.patch @@ -0,0 +1,52 @@ +From 75dc74ecc1bf5e270659c6c78877053b50e6ae19 Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Wed, 30 Mar 2022 21:24:21 -0500 +Subject: [PATCH 007/117] drm/sun4i: Add support for D1 HDMI + +D1's HDMI controller contains some platform integration changes. +It now has no external TMDS clock. The controller also supports HDCP +without an external clock or reset. + +While the maximum HDMI frequency is not explicity stated, the BSP PHY +driver provides PLL configurations only up to 297 MHz, so use that as +the max frequency. + +Signed-off-by: Samuel Holland +--- + drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 11 ++++++++++- + 1 file changed, 10 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c ++++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c +@@ -133,7 +133,7 @@ static int sun8i_dw_hdmi_bind(struct dev + return dev_err_probe(dev, PTR_ERR(hdmi->rst_ctrl), + "Could not get ctrl reset control\n"); + +- hdmi->clk_tmds = devm_clk_get(dev, "tmds"); ++ hdmi->clk_tmds = devm_clk_get_optional(dev, "tmds"); + if (IS_ERR(hdmi->clk_tmds)) + return dev_err_probe(dev, PTR_ERR(hdmi->clk_tmds), + "Couldn't get the tmds clock\n"); +@@ -246,6 +246,11 @@ static const struct sun8i_dw_hdmi_quirks + .mode_valid = sun8i_dw_hdmi_mode_valid_a83t, + }; + ++static const struct sun8i_dw_hdmi_quirks sun20i_d1_quirks = { ++ .mode_valid = sun8i_dw_hdmi_mode_valid_a83t, ++ .use_drm_infoframe = true, ++}; ++ + static const struct sun8i_dw_hdmi_quirks sun50i_h6_quirks = { + .mode_valid = sun8i_dw_hdmi_mode_valid_h6, + .use_drm_infoframe = true, +@@ -257,6 +262,10 @@ static const struct of_device_id sun8i_d + .data = &sun8i_a83t_quirks, + }, + { ++ .compatible = "allwinner,sun20i-d1-dw-hdmi", ++ .data = &sun20i_d1_quirks, ++ }, ++ { + .compatible = "allwinner,sun50i-h6-dw-hdmi", + .data = &sun50i_h6_quirks, + }, diff --git a/target/linux/d1/patches-6.1/0008-drm-sun4i-sun8i-hdmi-phy-Add-support-for-D1-PHY.patch b/target/linux/d1/patches-6.1/0008-drm-sun4i-sun8i-hdmi-phy-Add-support-for-D1-PHY.patch new file mode 100644 index 0000000000..e8007cc5c4 --- /dev/null +++ b/target/linux/d1/patches-6.1/0008-drm-sun4i-sun8i-hdmi-phy-Add-support-for-D1-PHY.patch @@ -0,0 +1,251 @@ +From 11f9765a8e6723bcb7243f6dbc48e6deaf17b097 Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Sun, 3 Apr 2022 15:15:41 -0500 +Subject: [PATCH 008/117] drm/sun4i: sun8i-hdmi-phy: Add support for D1 PHY + +Signed-off-by: Samuel Holland +--- + drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 169 +++++++++++++++++++++++++ + drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 32 +++++ + 2 files changed, 201 insertions(+) + +--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h ++++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h +@@ -145,6 +145,175 @@ + + #define SUN8I_HDMI_PHY_CEC_REG 0x003c + ++#define SUN20I_HDMI_PHY_CTL0_REG 0x0040 ++#define SUN20I_HDMI_PHY_CTL0_PLL_LOCK_MODE_MAN BIT(31) ++#define SUN20I_HDMI_PHY_CTL0_PLL_LOCK_MODE BIT(30) ++#define SUN20I_HDMI_PHY_CTL0_FIFO_WORKC_EN BIT(29) ++#define SUN20I_HDMI_PHY_CTL0_FIFO_AUTOSYNC_DIS BIT(28) ++#define SUN20I_HDMI_PHY_CTL0_ENTX GENMASK(27, 24) ++#define SUN20I_HDMI_PHY_CTL0_ENBI GENMASK(23, 20) ++#define SUN20I_HDMI_PHY_CTL0_ENLDO BIT(18) ++#define SUN20I_HDMI_PHY_CTL0_ENLDO_FS BIT(17) ++#define SUN20I_HDMI_PHY_CTL0_ENCK BIT(16) ++#define SUN20I_HDMI_PHY_CTL0_REG_PLR GENMASK(15, 12) ++#define SUN20I_HDMI_PHY_CTL0_REG_DEN GENMASK(11, 8) ++#define SUN20I_HDMI_PHY_CTL0_REG_CSMPS GENMASK(7, 6) ++#define SUN20I_HDMI_PHY_CTL0_REG_CK_TEST_SEL BIT(5) ++#define SUN20I_HDMI_PHY_CTL0_REG_CK_SEL BIT(4) ++#define SUN20I_HDMI_PHY_CTL0_HPD_EN BIT(2) ++#define SUN20I_HDMI_PHY_CTL0_SCL_EN BIT(1) ++#define SUN20I_HDMI_PHY_CTL0_SDA_EN BIT(0) ++ ++#define SUN20I_HDMI_PHY_CTL1_REG 0x0044 ++#define SUN20I_HDMI_PHY_CTL1_RXSENSE_MODE_MAN BIT(31) ++#define SUN20I_HDMI_PHY_CTL1_RXSENSE_MODE BIT(30) ++#define SUN20I_HDMI_PHY_CTL1_RES_S GENMASK(29, 28) ++#define SUN20I_HDMI_PHY_CTL1_RES_SCKTMDS BIT(27) ++#define SUN20I_HDMI_PHY_CTL1_REG_SWI BIT(26) ++#define SUN20I_HDMI_PHY_CTL1_REG_SVR GENMASK(25, 24) ++#define SUN20I_HDMI_PHY_CTL1_REG_BST2 GENMASK(21, 20) ++#define SUN20I_HDMI_PHY_CTL1_REG_BST1 GENMASK(19, 18) ++#define SUN20I_HDMI_PHY_CTL1_REG_BST0 GENMASK(17, 16) ++#define SUN20I_HDMI_PHY_CTL1_REG_SP2_3 GENMASK(15, 12) ++#define SUN20I_HDMI_PHY_CTL1_REG_SP2_2 GENMASK(11, 8) ++#define SUN20I_HDMI_PHY_CTL1_REG_SP2_1 GENMASK(7, 4) ++#define SUN20I_HDMI_PHY_CTL1_REG_SP2_0 GENMASK(3, 0) ++ ++#define SUN20I_HDMI_PHY_CTL2_REG 0x0048 ++#define SUN20I_HDMI_PHY_CTL2_HPDO_MODE_MAN BIT(31) ++#define SUN20I_HDMI_PHY_CTL2_HPDO_MODE BIT(30) ++#define SUN20I_HDMI_PHY_CTL2_REG_RESDI GENMASK(29, 24) ++#define SUN20I_HDMI_PHY_CTL2_REG_SP1_3 GENMASK(23, 19) ++#define SUN20I_HDMI_PHY_CTL2_REG_SP1_2 GENMASK(18, 14) ++#define SUN20I_HDMI_PHY_CTL2_REG_SP1_1 GENMASK(13, 9) ++#define SUN20I_HDMI_PHY_CTL2_REG_SP1_0 GENMASK(8, 4) ++#define SUN20I_HDMI_PHY_CTL2_REG_P2OPT GENMASK(3, 0) ++ ++#define SUN20I_HDMI_PHY_CTL3_REG 0x004c ++#define SUN20I_HDMI_PHY_CTL3_REG_P2_3 GENMASK(31, 28) ++#define SUN20I_HDMI_PHY_CTL3_REG_P2_2 GENMASK(27, 24) ++#define SUN20I_HDMI_PHY_CTL3_REG_P2_1 GENMASK(23, 20) ++#define SUN20I_HDMI_PHY_CTL3_REG_P2_0 GENMASK(19, 16) ++#define SUN20I_HDMI_PHY_CTL3_REG_MC3 GENMASK(15, 12) ++#define SUN20I_HDMI_PHY_CTL3_REG_MC2 GENMASK(11, 8) ++#define SUN20I_HDMI_PHY_CTL3_REG_MC1 GENMASK(7, 4) ++#define SUN20I_HDMI_PHY_CTL3_REG_MC0 GENMASK(3, 0) ++ ++#define SUN20I_HDMI_PHY_CTL4_REG 0x0050 ++#define SUN20I_HDMI_PHY_CTL4_REG_SLV GENMASK(31, 29) ++#define SUN20I_HDMI_PHY_CTL4_REG_P1_3 GENMASK(28, 24) ++#define SUN20I_HDMI_PHY_CTL4_REG_P1_2 GENMASK(20, 16) ++#define SUN20I_HDMI_PHY_CTL4_REG_P1_1 GENMASK(12, 8) ++#define SUN20I_HDMI_PHY_CTL4_REG_P1_0 GENMASK(4, 0) ++ ++#define SUN20I_HDMI_PHY_CTL5_REG 0x0054 ++#define SUN20I_HDMI_PHY_CTL5_REG_P1OPT GENMASK(19, 16) ++#define SUN20I_HDMI_PHY_CTL5_REG_CKPDLYOPT BIT(12) ++#define SUN20I_HDMI_PHY_CTL5_REG_CALSW BIT(11) ++#define SUN20I_HDMI_PHY_CTL5_ENRESCK BIT(10) ++#define SUN20I_HDMI_PHY_CTL5_ENRES BIT(9) ++#define SUN20I_HDMI_PHY_CTL5_ENRCAL BIT(8) ++#define SUN20I_HDMI_PHY_CTL5_ENP2S GENMASK(7, 4) ++#define SUN20I_HDMI_PHY_CTL5_ENIB BIT(1) ++#define SUN20I_HDMI_PHY_CTL5_ENCALOG BIT(0) ++ ++#define SUN20I_HDMI_PLL_CTL0_REG 0x0058 ++#define SUN20I_HDMI_PLL_CTL0_CKO_SEL GENMASK(31, 30) ++#define SUN20I_HDMI_PLL_CTL0_BYPASS_PPLL BIT(29) ++#define SUN20I_HDMI_PLL_CTL0_ENVBS BIT(28) ++#define SUN20I_HDMI_PLL_CTL0_SLV GENMASK(26, 24) ++#define SUN20I_HDMI_PLL_CTL0_BCR BIT(23) ++#define SUN20I_HDMI_PLL_CTL0_BYPASS_CLRDPTH BIT(22) ++#define SUN20I_HDMI_PLL_CTL0_CLR_DPTH GENMASK(21, 20) ++#define SUN20I_HDMI_PLL_CTL0_CUTFB BIT(18) ++#define SUN20I_HDMI_PLL_CTL0_DIV2_CKBIT BIT(17) ++#define SUN20I_HDMI_PLL_CTL0_DIV2_CKTMDS BIT(16) ++#define SUN20I_HDMI_PLL_CTL0_DIV_PRE GENMASK(15, 12) ++#define SUN20I_HDMI_PLL_CTL0_DIVX1 BIT(10) ++#define SUN20I_HDMI_PLL_CTL0_SDRVEN BIT(9) ++#define SUN20I_HDMI_PLL_CTL0_VCORANGE BIT(8) ++#define SUN20I_HDMI_PLL_CTL0_N_CNTRL GENMASK(7, 6) ++#define SUN20I_HDMI_PLL_CTL0_GMP_CNTRL GENMASK(5, 4) ++#define SUN20I_HDMI_PLL_CTL0_PROP_CNTRL GENMASK(2, 0) ++ ++#define SUN20I_HDMI_PLL_CTL1_REG 0x005c ++#define SUN20I_HDMI_PLL_CTL1_CTRL_MODLE_CLKSRC BIT(31) ++#define SUN20I_HDMI_PLL_CTL1_PCNT_N GENMASK(27, 20) ++#define SUN20I_HDMI_PLL_CTL1_PCNT_EN BIT(19) ++#define SUN20I_HDMI_PLL_CTL1_SDM_EN BIT(18) ++#define SUN20I_HDMI_PLL_CTL1_PIXEL_REP GENMASK(17, 16) ++#define SUN20I_HDMI_PLL_CTL1_PWRON BIT(12) ++#define SUN20I_HDMI_PLL_CTL1_RESET BIT(11) ++#define SUN20I_HDMI_PLL_CTL1_SCKREF BIT(10) ++#define SUN20I_HDMI_PLL_CTL1_SCKFB BIT(9) ++#define SUN20I_HDMI_PLL_CTL1_DRV_ANA BIT(8) ++#define SUN20I_HDMI_PLL_CTL1_FAST_TECH BIT(7) ++#define SUN20I_HDMI_PLL_CTL1_GEAR_SHIFT BIT(6) ++#define SUN20I_HDMI_PLL_CTL1_REF_CNTRL GENMASK(5, 4) ++#define SUN20I_HDMI_PLL_CTL1_INT_CNTRL GENMASK(2, 0) ++ ++#define SUN20I_HDMI_AFIFO_CFG_REG 0x0060 ++#define SUN20I_HDMI_AFIFO_CFG_AFIFO_ERROR BIT(0) ++#define SUN20I_HDMI_AFIFO_CFG_AFIFO_ERROR_DET BIT(1) ++ ++#define SUN20I_HDMI_MODULATOR_CFG0_REG 0x0064 ++#define SUN20I_HDMI_MODULATOR_CFG1_REG 0x0068 ++ ++#define SUN20I_HDMI_INDEB_CTRL_REG 0x006c ++#define SUN20I_HDMI_INDEB_CTRL_HPDI_DEBUGMODE BIT(29) ++#define SUN20I_HDMI_INDEB_CTRL_HPDI_DEBUG BIT(28) ++#define SUN20I_HDMI_INDEB_CTRL_SDAI_DEBUGMODE BIT(25) ++#define SUN20I_HDMI_INDEB_CTRL_SDAI_DEBUG BIT(24) ++#define SUN20I_HDMI_INDEB_CTRL_SCLI_DEBUGMODE BIT(21) ++#define SUN20I_HDMI_INDEB_CTRL_SCLI_DEBUG BIT(20) ++#define SUN20I_HDMI_INDEB_CTRL_CECI_DEBUGMODE BIT(17) ++#define SUN20I_HDMI_INDEB_CTRL_CECI_DEBUG BIT(16) ++#define SUN20I_HDMI_INDEB_CTRL_TXDATA_DEBUGMODE GENMASK(1, 0) ++ ++#define SUN20I_HDMI_INDBG_TXD0_REG 0x0070 ++#define SUN20I_HDMI_INDBG_TXD1_REG 0x0074 ++#define SUN20I_HDMI_INDBG_TXD2_REG 0x0078 ++#define SUN20I_HDMI_INDBG_TXD3_REG 0x007c ++ ++#define SUN20I_HDMI_PLL_STS_REG 0x0080 ++#define SUN20I_HDMI_PLL_STS_PHY_CDETPCK_STATUS BIT(31) ++#define SUN20I_HDMI_PLL_STS_PHY_CDETP_STATUS GENMASK(30, 28) ++#define SUN20I_HDMI_PLL_STS_PHY_CDETNCK_STATUS BIT(27) ++#define SUN20I_HDMI_PLL_STS_PHY_CDETN_STATUS GENMASK(26, 24) ++#define SUN20I_HDMI_PLL_STS_PHY_HPDO_STATUS BIT(23) ++#define SUN20I_HDMI_PLL_STS_PHY_SCLO_STATUS BIT(22) ++#define SUN20I_HDMI_PLL_STS_PHY_SDAO_STATUS BIT(21) ++#define SUN20I_HDMI_PLL_STS_PHY_CECO_STATUS BIT(20) ++#define SUN20I_HDMI_PLL_STS_PHY_COUT2D_STATUS BIT(17) ++#define SUN20I_HDMI_PLL_STS_PHY_RCALEND2D_STS BIT(16) ++#define SUN20I_HDMI_PLL_STS_PHY_RESDO2D_STATUS GENMASK(13, 8) ++#define SUN20I_HDMI_PLL_STS_PLL_LOCK_STATUS BIT(4) ++#define SUN20I_HDMI_PLL_STS_RXSENSE_DLY_STATUS BIT(1) ++#define SUN20I_HDMI_PLL_STS_TX_READY_DLY_STATUS BIT(0) ++ ++#define SUN20I_HDMI_PRBS_CTL_REG 0x0084 ++#define SUN20I_HDMI_PRBS_SEED_GEN_REG 0x0088 ++#define SUN20I_HDMI_PRBS_SEED_CHK_REG 0x008c ++#define SUN20I_HDMI_PRBS_SEED_NUM_REG 0x0090 ++#define SUN20I_HDMI_PRBS_CYCLE_NUM_REG 0x0094 ++ ++#define SUN20I_HDMI_PLL_ODLY_REG 0x0098 ++#define SUN20I_HDMI_PLL_ODLY_RXSENSE_DLY_RESET BIT(31) ++#define SUN20I_HDMI_PLL_ODLY_RXSENSE_DLY_COUNT GENMASK(30, 16) ++#define SUN20I_HDMI_PLL_ODLY_TX_READY_DLY_RESET BIT(15) ++#define SUN20I_HDMI_PLL_ODLY_TX_READY_DLY_COUNT GENMASK(14, 0) ++ ++#define SUN20I_HDMI_PHY_CTL6_REG 0x009c ++#define SUN20I_HDMI_PHY_CTL6_SWITCH_CLKCH_DATA BIT(31) ++#define SUN20I_HDMI_PHY_CTL6_EN_CKDAT BIT(30) ++#define SUN20I_HDMI_PHY_CTL6_CLK_GREATE2_340M GENMASK(29, 20) ++#define SUN20I_HDMI_PHY_CTL6_CLK_GREATE1_340M GENMASK(19, 10) ++#define SUN20I_HDMI_PHY_CTL6_CLK_GREATE0_340M GENMASK(9, 0) ++ ++#define SUN20I_HDMI_PHY_CTL7_REG 0x00a0 ++#define SUN20I_HDMI_PHY_CTL7_CLK_LOW_340M GENMASK(21, 12) ++#define SUN20I_HDMI_PHY_CTL7_CLK_GREATE3_340M GENMASK(9, 0) ++ + struct sun8i_hdmi_phy; + + struct sun8i_hdmi_phy_variant { +--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c ++++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c +@@ -398,6 +398,28 @@ static const struct dw_hdmi_phy_ops sun8 + .setup_hpd = dw_hdmi_phy_setup_hpd, + }; + ++static int sun20i_d1_hdmi_phy_config(struct dw_hdmi *hdmi, void *data, ++ const struct drm_display_info *display, ++ const struct drm_display_mode *mode) ++{ ++ struct sun8i_hdmi_phy *phy = data; ++ ++ return 0; ++} ++ ++static void sun20i_d1_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) ++{ ++ struct sun8i_hdmi_phy *phy = data; ++} ++ ++static const struct dw_hdmi_phy_ops sun20i_d1_hdmi_phy_ops = { ++ .init = sun20i_d1_hdmi_phy_config, ++ .disable = sun20i_d1_hdmi_phy_disable, ++ .read_hpd = dw_hdmi_phy_read_hpd, ++ .update_hpd = dw_hdmi_phy_update_hpd, ++ .setup_hpd = dw_hdmi_phy_setup_hpd, ++}; ++ + static void sun8i_hdmi_phy_unlock(struct sun8i_hdmi_phy *phy) + { + /* enable read access to HDMI controller */ +@@ -576,6 +598,7 @@ void sun8i_hdmi_phy_set_ops(struct sun8i + const struct sun8i_hdmi_phy_variant *variant = phy->variant; + + if (variant->phy_ops) { ++ plat_data->phy_force_vendor = true; + plat_data->phy_ops = variant->phy_ops; + plat_data->phy_name = "sun8i_dw_hdmi_phy"; + plat_data->phy_data = phy; +@@ -612,6 +635,11 @@ static const struct sun8i_hdmi_phy_varia + .phy_init = &sun8i_hdmi_phy_init_h3, + }; + ++static const struct sun8i_hdmi_phy_variant sun20i_d1_hdmi_phy = { ++ .phy_ops = &sun20i_d1_hdmi_phy_ops, ++ .phy_init = &sun50i_hdmi_phy_init_h6, ++}; ++ + static const struct sun8i_hdmi_phy_variant sun50i_a64_hdmi_phy = { + .has_phy_clk = true, + .phy_ops = &sun8i_h3_hdmi_phy_ops, +@@ -639,6 +667,10 @@ static const struct of_device_id sun8i_h + .data = &sun8i_r40_hdmi_phy, + }, + { ++ .compatible = "allwinner,sun20i-d1-hdmi-phy", ++ .data = &sun20i_d1_hdmi_phy, ++ }, ++ { + .compatible = "allwinner,sun50i-a64-hdmi-phy", + .data = &sun50i_a64_hdmi_phy, + }, diff --git a/target/linux/d1/patches-6.1/0009-drm-sun4i-Copy-in-BSP-code-for-D1-HDMI-PHY.patch b/target/linux/d1/patches-6.1/0009-drm-sun4i-Copy-in-BSP-code-for-D1-HDMI-PHY.patch new file mode 100644 index 0000000000..85c81d5057 --- /dev/null +++ b/target/linux/d1/patches-6.1/0009-drm-sun4i-Copy-in-BSP-code-for-D1-HDMI-PHY.patch @@ -0,0 +1,621 @@ +From 7ea7d4abfd537230da58533803a2d0257addace8 Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Wed, 30 Mar 2022 00:46:07 -0500 +Subject: [PATCH 009/117] drm/sun4i: Copy in BSP code for D1 HDMI PHY + +Signed-off-by: Samuel Holland +--- + drivers/gpu/drm/sun4i/aw_phy.h | 411 +++++++++++++++++++++++++ + drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 1 + + drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 156 ++++++++++ + 3 files changed, 568 insertions(+) + create mode 100644 drivers/gpu/drm/sun4i/aw_phy.h + +--- /dev/null ++++ b/drivers/gpu/drm/sun4i/aw_phy.h +@@ -0,0 +1,411 @@ ++/* ++ * Allwinner SoCs hdmi2.0 driver. ++ * ++ * Copyright (C) 2016 Allwinner. ++ * ++ * This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without any ++ * warranty of any kind, whether express or implied. ++ */ ++ ++#ifndef AW_PHY_H_ ++#define AW_PHY_H_ ++ ++#define AW_PHY_TIMEOUT 1000 ++#define LOCK_TIMEOUT 100 ++ ++/* allwinner phy register offset */ ++#define HDMI_PHY_CTL0 0x40 ++#define HDMI_PHY_CTL1 0x44 ++#define HDMI_PHY_CTL2 0x48 ++#define HDMI_PHY_CTL3 0x4C ++#define HDMI_PHY_CTL4 0x50 ++#define HDMI_PHY_CTL5 0x54 ++#define HDMI_PLL_CTL0 0x58 ++#define HDMI_PLL_CTL1 0x5C ++#define HDMI_AFIFO_CFG 0x60 ++#define HDMI_MODULATOR_CFG0 0x64 ++#define HDMI_MODULATOR_CFG1 0x68 ++#define HDMI_PHY_INDEB_CTRL 0x6C ++#define HDMI_PHY_INDBG_TXD0 0x70 ++#define HDMI_PHY_INDBG_TXD1 0x74 ++#define HDMI_PHY_INDBG_TXD2 0x78 ++#define HDMI_PHY_INDBG_TXD3 0x7C ++#define HDMI_PHY_PLL_STS 0x80 ++#define HDMI_PRBS_CTL 0x84 ++#define HDMI_PRBS_SEED_GEN 0x88 ++#define HDMI_PRBS_SEED_CHK 0x8C ++#define HDMI_PRBS_SEED_NUM 0x90 ++#define HDMI_PRBS_CYCLE_NUM 0x94 ++#define HDMI_PHY_PLL_ODLY_CFG 0x98 ++#define HDMI_PHY_CTL6 0x9C ++#define HDMI_PHY_CTL7 0xA0 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 sda_en :1; // Default: 0; ++ u32 scl_en :1; // Default: 0; ++ u32 hpd_en :1; // Default: 0; ++ u32 res0 :1; // Default: 0; ++ u32 reg_ck_sel :1; // Default: 1; ++ u32 reg_ck_test_sel :1; // Default: 1; ++ u32 reg_csmps :2; // Default: 0; ++ u32 reg_den :4; // Default: F; ++ u32 reg_plr :4; // Default: 0; ++ u32 enck :1; // Default: 1; ++ u32 enldo_fs :1; // Default: 1; ++ u32 enldo :1; // Default: 1; ++ u32 res1 :1; // Default: 1; ++ u32 enbi :4; // Default: F; ++ u32 entx :4; // Default: F; ++ u32 async_fifo_autosync_disable :1; // Default: 0; ++ u32 async_fifo_workc_enable :1; // Default: 1; ++ u32 phy_pll_lock_mode :1; // Default: 1; ++ u32 phy_pll_lock_mode_man :1; // Default: 1; ++ } bits; ++} HDMI_PHY_CTL0_t; //=========================== 0x0040 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 reg_sp2_0 : 4 ; // Default: 0; ++ u32 reg_sp2_1 : 4 ; // Default: 0; ++ u32 reg_sp2_2 : 4 ; // Default: 0; ++ u32 reg_sp2_3 : 4 ; // Default: 0; ++ u32 reg_bst0 : 2 ; // Default: 3; ++ u32 reg_bst1 : 2 ; // Default: 3; ++ u32 reg_bst2 : 2 ; // Default: 3; ++ u32 res0 : 2 ; // Default: 0; ++ u32 reg_svr : 2 ; // Default: 2; ++ u32 reg_swi : 1 ; // Default: 0; ++ u32 res_scktmds : 1 ; // Default: 0; ++ u32 res_res_s : 2 ; // Default: 3; ++ u32 phy_rxsense_mode : 1 ; // Default: 0; ++ u32 res_rxsense_mode_man : 1 ; // Default: 0; ++ } bits; ++} HDMI_PHY_CTL1_t; //===================================================== 0x0044 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 reg_p2opt : 4 ; // Default: 0; ++ u32 reg_sp1_0 : 5 ; // Default: 0; ++ u32 reg_sp1_1 : 5 ; // Default: 0; ++ u32 reg_sp1_2 : 5 ; // Default: 0; ++ u32 reg_sp1_3 : 5 ; // Default: 0; ++ u32 reg_resdi : 6 ; // Default: 18; ++ u32 phy_hpdo_mode : 1 ; // Default: 0; ++ u32 phy_hpdo_mode_man : 1 ; // Default: 0; ++ } bits; ++} HDMI_PHY_CTL2_t; //===================================================== 0x0048 ++ ++ ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 reg_mc0 : 4 ; // Default: F; ++ u32 reg_mc1 : 4 ; // Default: F; ++ u32 reg_mc2 : 4 ; // Default: F; ++ u32 reg_mc3 : 4 ; // Default: F; ++ u32 reg_p2_0 : 4 ; // Default: F; ++ u32 reg_p2_1 : 4 ; // Default: F; ++ u32 reg_p2_2 : 4 ; // Default: F; ++ u32 reg_p2_3 : 4 ; // Default: F; ++ } bits; ++} HDMI_PHY_CTL3_t; //===================================================== 0x004C ++ ++ ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 reg_p1_0 : 5 ; // Default: 0x10; ++ u32 res0 : 3 ; // Default: 0; ++ u32 reg_p1_1 : 5 ; // Default: 0x10; ++ u32 res1 : 3 ; // Default: 0; ++ u32 reg_p1_2 : 5 ; // Default: 0x10; ++ u32 res2 : 3 ; // Default: 0; ++ u32 reg_p1_3 : 5 ; // Default: 0x10; ++ u32 reg_slv : 3 ; // Default: 0; ++ } bits; ++} HDMI_PHY_CTL4_t; //===================================================== 0x0050 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 encalog : 1 ; // Default: 0x1; ++ u32 enib : 1 ; // Default: 0x1; ++ u32 res0 : 2 ; // Default: 0; ++ u32 enp2s : 4 ; // Default: 0xF; ++ u32 enrcal : 1 ; // Default: 0x1; ++ u32 enres : 1 ; // Default: 1; ++ u32 enresck : 1 ; // Default: 1; ++ u32 reg_calsw : 1 ; // Default: 0; ++ u32 reg_ckpdlyopt : 1 ; // Default: 0; ++ u32 res1 : 3 ; // Default: 0; ++ u32 reg_p1opt : 4 ; // Default: 0; ++ u32 res2 : 12 ; // Default: 0; ++ } bits; ++} HDMI_PHY_CTL5_t; //===================================================== 0x0054 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 prop_cntrl : 3 ; // Default: 0x7; ++ u32 res0 : 1 ; // Default: 0; ++ u32 gmp_cntrl : 2 ; // Default: 1; ++ u32 n_cntrl : 2 ; // Default: 0; ++ u32 vcorange : 1 ; // Default: 0; ++ u32 sdrven : 1 ; // Default: 0; ++ u32 divx1 : 1 ; // Default: 0; ++ u32 res1 : 1 ; // Default: 0; ++ u32 div_pre : 4 ; // Default: 0; ++ u32 div2_cktmds : 1 ; // Default: 1; ++ u32 div2_ckbit : 1 ; // Default: 1; ++ u32 cutfb : 1 ; // Default: 0; ++ u32 res2 : 1 ; // Default: 0; ++ u32 clr_dpth : 2 ; // Default: 0; ++ u32 bypass_clrdpth : 1 ; // Default: 0; ++ u32 bcr : 1 ; // Default: 0; ++ u32 slv : 3 ; // Default: 4; ++ u32 res3 : 1 ; // Default: 0; ++ u32 envbs : 1 ; // Default: 0; ++ u32 bypass_ppll : 1 ; // Default: 0; ++ u32 cko_sel : 2 ; // Default: 0; ++ } bits; ++} HDMI_PLL_CTL0_t; //===================================================== 0x0058 ++ ++ ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 int_cntrl : 3 ; // Default: 0x0; ++ u32 res0 : 1 ; // Default: 0; ++ u32 ref_cntrl : 2 ; // Default: 3; ++ u32 gear_shift : 1 ; // Default: 0; ++ u32 fast_tech : 1 ; // Default: 0; ++ u32 drv_ana : 1 ; // Default: 1; ++ u32 sckfb : 1 ; // Default: 0; ++ u32 sckref : 1 ; // Default: 0; ++ u32 reset : 1 ; // Default: 0; ++ u32 pwron : 1 ; // Default: 0; ++ u32 res1 : 3 ; // Default: 0; ++ u32 pixel_rep : 2 ; // Default: 0; ++ u32 sdm_en : 1 ; // Default: 0; ++ u32 pcnt_en : 1 ; // Default: 0; ++ u32 pcnt_n : 8 ; // Default: 0xE; ++ u32 res2 : 3 ; // Default: 0; ++ u32 ctrl_modle_clksrc : 1 ; // Default: 0; ++ } bits; ++} HDMI_PLL_CTL1_t; //===================================================== 0x005C ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 hdmi_afifo_error : 1 ; // Default: 0x0; ++ u32 hdmi_afifo_error_det : 1 ; // Default: 0x0; ++ u32 res0 : 30 ; // Default: 0; ++ } bits; ++} HDMI_AFIFO_CFG_t; //===================================================== 0x0060 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 fnpll_mash_en : 1 ; // Default: 0x0; ++ u32 fnpll_mash_mod : 2 ; // Default: 0x0; ++ u32 fnpll_mash_stp : 9 ; // Default: 0x0; ++ u32 fnpll_mash_m12 : 1 ; // Default: 0x0; ++ u32 fnpll_mash_frq : 2 ; // Default: 0x0; ++ u32 fnpll_mash_bot : 17 ; // Default: 0x0; ++ } bits; ++} HDMI_MODULATOR_CFG0_t; //===================================================== 0x0064 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 fnpll_mash_dth : 1 ; // Default: 0x0; ++ u32 fnpll_mash_fen : 1 ; // Default: 0x0; ++ u32 fnpll_mash_frc : 17 ; // Default: 0x0; ++ u32 fnpll_mash_fnv : 8 ; // Default: 0x0; ++ u32 res0 : 5 ; // Default: 0x0; ++ } bits; ++} HDMI_MODULATOR_CFG1_t; //===================================================== 0x0068 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 txdata_debugmode : 2 ; // Default: 0x0; ++ u32 res0 : 14 ; // Default: 0x0; ++ u32 ceci_debug : 1 ; // Default: 0x0; ++ u32 ceci_debugmode : 1 ; // Default: 0x0; ++ u32 res1 : 2 ; // Default: 0x0; ++ u32 sdai_debug : 1 ; // Default: 0x0; ++ u32 sdai_debugmode : 1 ; // Default: 0x0; ++ u32 res2 : 2 ; // Default: 0x0; ++ u32 scli_debug : 1 ; // Default: 0x0; ++ u32 scli_debugmode : 1 ; // Default: 0x0; ++ u32 res3 : 2 ; // Default: 0x0; ++ u32 hpdi_debug : 1 ; // Default: 0x0; ++ u32 hpdi_debugmode : 1 ; // Default: 0x0; ++ u32 res4 : 2 ; // Default: 0x0; ++ } bits; ++} HDMI_PHY_INDBG_CTRL_t; //================================================== 0x006C ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 txdata0_debug_data : 32 ; // Default: 0x0; ++ } bits; ++} HDMI_PHY_INDBG_TXD0_t; //================================================== 0x0070 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 txdata1_debug_data : 32 ; // Default: 0x0; ++ } bits; ++} HDMI_PHY_INDBG_TXD1_t; //================================================== 0x0074 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 txdata2_debug_data : 32 ; // Default: 0x0; ++ } bits; ++} HDMI_PHY_INDBG_TXD2_t; //================================================== 0x0078 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 txdata3_debug_data : 32 ; // Default: 0x0; ++ } bits; ++} HDMI_PHY_INDBG_TXD3_t; //================================================== 0x007C ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 tx_ready_dly_status : 1 ; // Default: 0x0; ++ u32 rxsense_dly_status : 1 ; // Default: 0x0; ++ u32 res0 : 2 ; // Default: 0x0; ++ u32 pll_lock_status : 1 ; // Default: 0x0; ++ u32 res1 : 3 ; // Default: 0x0; ++ u32 phy_resdo2d_status : 6 ; // Default: 0x0; ++ u32 res2 : 2 ; // Default: 0x0; ++ u32 phy_rcalend2d_status : 1 ; // Default: 0x0; ++ u32 phy_cout2d_status : 1 ; // Default: 0x0; ++ u32 res3 : 2 ; // Default: 0x0; ++ u32 phy_ceco_status : 1 ; // Default: 0x0; ++ u32 phy_sdao_status : 1 ; // Default: 0x0; ++ u32 phy_sclo_status : 1 ; // Default: 0x0; ++ u32 phy_hpdo_status : 1 ; // Default: 0x0; ++ u32 phy_cdetn_status : 3 ; // Default: 0x0; ++ u32 phy_cdetnck_status : 1 ; // Default: 0x0; ++ u32 phy_cdetp_status : 3 ; // Default: 0x0; ++ u32 phy_cdetpck_status : 1 ; // Default: 0x0; ++ } bits; ++} HDMI_PHY_PLL_STS_t; //===================================================== 0x0080 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 prbs_en : 1 ; // Default: 0x0; ++ u32 prbs_start : 1 ; // Default: 0x0; ++ u32 prbs_seq_gen : 1 ; // Default: 0x0; ++ u32 prbs_seq_chk : 1 ; // Default: 0x0; ++ u32 prbs_mode : 4 ; // Default: 0x0; ++ u32 prbs_type : 2 ; // Default: 0x0; ++ u32 prbs_clk_pol : 1 ; // Default: 0x0; ++ u32 res0 : 21 ; // Default: 0x0; ++ } bits; ++} HDMI_PRBS_CTL_t; //===================================================== 0x0084 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 prbs_seed_gen : 32 ; // Default: 0x0; ++ } bits; ++} HDMI_PRBS_SEED_GEN_t; //================================================= 0x0088 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 prbs_seed_chk : 32 ; // Default: 0x0; ++ } bits; ++} HDMI_PRBS_SEED_CHK_t; //================================================= 0x008C ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 prbs_seed_num : 32 ; // Default: 0x0; ++ } bits; ++} HDMI_PRBS_SEED_NUM_t; //================================================= 0x0090 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 prbs_cycle_num : 32 ; // Default: 0x0; ++ } bits; ++} HDMI_PRBS_CYCLE_NUM_t; //================================================= 0x0094 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 tx_ready_dly_count : 15 ; // Default: 0x0; ++ u32 tx_ready_dly_reset : 1 ; // Default: 0x0; ++ u32 rxsense_dly_count : 15 ; // Default: 0x0; ++ u32 rxsense_dly_reset : 1 ; // Default: 0x0; ++ } bits; ++} HDMI_PHY_PLL_ODLY_CFG_t; //================================================= 0x0098 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 clk_greate0_340m : 10 ; // Default: 0x3FF; ++ u32 clk_greate1_340m : 10 ; // Default: 0x3FF; ++ u32 clk_greate2_340m : 10 ; // Default: 0x3FF; ++ u32 en_ckdat : 1 ; // Default: 0x3FF; ++ u32 switch_clkch_data_corresponding : 1 ; // Default: 0x3FF; ++ } bits; ++} HDMI_PHY_CTL6_t; //========================================================= 0x009C ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 clk_greate3_340m : 10 ; // Default: 0x0; ++ u32 res0 : 2 ; // Default: 0x3FF; ++ u32 clk_low_340m : 10 ; // Default: 0x3FF; ++ u32 res1 : 10 ; // Default: 0x3FF; ++ } bits; ++} HDMI_PHY_CTL7_t; //========================================================= 0x00A0 ++ ++struct __aw_phy_reg_t { ++ u32 res[16]; /* 0x0 ~ 0x3c */ ++ HDMI_PHY_CTL0_t phy_ctl0; /* 0x0040 */ ++ HDMI_PHY_CTL1_t phy_ctl1; /* 0x0044 */ ++ HDMI_PHY_CTL2_t phy_ctl2; /* 0x0048 */ ++ HDMI_PHY_CTL3_t phy_ctl3; /* 0x004c */ ++ HDMI_PHY_CTL4_t phy_ctl4; /* 0x0050 */ ++ HDMI_PHY_CTL5_t phy_ctl5; /* 0x0054 */ ++ HDMI_PLL_CTL0_t pll_ctl0; /* 0x0058 */ ++ HDMI_PLL_CTL1_t pll_ctl1; /* 0x005c */ ++ HDMI_AFIFO_CFG_t afifo_cfg; /* 0x0060 */ ++ HDMI_MODULATOR_CFG0_t modulator_cfg0; /* 0x0064 */ ++ HDMI_MODULATOR_CFG1_t modulator_cfg1; /* 0x0068 */ ++ HDMI_PHY_INDBG_CTRL_t phy_indbg_ctrl; /* 0x006c */ ++ HDMI_PHY_INDBG_TXD0_t phy_indbg_txd0; /* 0x0070 */ ++ HDMI_PHY_INDBG_TXD1_t phy_indbg_txd1; /* 0x0074 */ ++ HDMI_PHY_INDBG_TXD2_t phy_indbg_txd2; /* 0x0078 */ ++ HDMI_PHY_INDBG_TXD3_t phy_indbg_txd3; /* 0x007c */ ++ HDMI_PHY_PLL_STS_t phy_pll_sts; /* 0x0080 */ ++ HDMI_PRBS_CTL_t prbs_ctl; /* 0x0084 */ ++ HDMI_PRBS_SEED_GEN_t prbs_seed_gen; /* 0x0088 */ ++ HDMI_PRBS_SEED_CHK_t prbs_seed_chk; /* 0x008c */ ++ HDMI_PRBS_SEED_NUM_t prbs_seed_num; /* 0x0090 */ ++ HDMI_PRBS_CYCLE_NUM_t prbs_cycle_num; /* 0x0094 */ ++ HDMI_PHY_PLL_ODLY_CFG_t phy_pll_odly_cfg; /* 0x0098 */ ++ HDMI_PHY_CTL6_t phy_ctl6; /* 0x009c */ ++ HDMI_PHY_CTL7_t phy_ctl7; /* 0x00A0 */ ++}; ++ ++#endif /* AW_PHY_H_ */ +--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h ++++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h +@@ -334,6 +334,7 @@ struct sun8i_hdmi_phy { + struct clk *clk_pll1; + struct device *dev; + unsigned int rcal; ++ void __iomem *base; + struct regmap *regs; + struct reset_control *rst_phy; + const struct sun8i_hdmi_phy_variant *variant; +--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c ++++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c +@@ -9,6 +9,8 @@ + + #include "sun8i_dw_hdmi.h" + ++#include "aw_phy.h" ++ + /* + * Address can be actually any value. Here is set to same value as + * it is set in BSP driver. +@@ -398,11 +400,164 @@ static const struct dw_hdmi_phy_ops sun8 + .setup_hpd = dw_hdmi_phy_setup_hpd, + }; + ++static int sun20i_d1_hdmi_phy_enable(volatile struct __aw_phy_reg_t __iomem *phy_base) ++{ ++ int i = 0, status = 0; ++ ++ pr_info("enter %s\n", __func__); ++ ++ //enib -> enldo -> enrcal -> encalog -> enbi[3:0] -> enck -> enp2s[3:0] -> enres -> enresck -> entx[3:0] ++ phy_base->phy_ctl4.bits.reg_slv = 4; //low power voltage 1.08V, default is 3, set 4 as well as pll_ctl0 bit [24:26] ++ phy_base->phy_ctl5.bits.enib = 1; ++ phy_base->phy_ctl0.bits.enldo = 1; ++ phy_base->phy_ctl0.bits.enldo_fs = 1; ++ phy_base->phy_ctl5.bits.enrcal = 1; ++ ++ phy_base->phy_ctl5.bits.encalog = 1; ++ ++ for (i = 0; i < AW_PHY_TIMEOUT; i++) { ++ udelay(5); ++ status = phy_base->phy_pll_sts.bits.phy_rcalend2d_status; ++ if (status & 0x1) { ++ pr_info("[%s]:phy_rcalend2d_status\n", __func__); ++ break; ++ } ++ } ++ if ((i == AW_PHY_TIMEOUT) && !status) { ++ pr_err("phy_rcalend2d_status Timeout !\n"); ++ return -1; ++ } ++ ++ phy_base->phy_ctl0.bits.enbi = 0xF; ++ for (i = 0; i < AW_PHY_TIMEOUT; i++) { ++ udelay(5); ++ status = phy_base->phy_pll_sts.bits.pll_lock_status; ++ if (status & 0x1) { ++ pr_info("[%s]:pll_lock_status\n", __func__); ++ break; ++ } ++ } ++ if ((i == AW_PHY_TIMEOUT) && !status) { ++ pr_err("pll_lock_status Timeout! status = 0x%x\n", status); ++ return -1; ++ } ++ ++ phy_base->phy_ctl0.bits.enck = 1; ++ phy_base->phy_ctl5.bits.enp2s = 0xF; ++ phy_base->phy_ctl5.bits.enres = 1; ++ phy_base->phy_ctl5.bits.enresck = 1; ++ phy_base->phy_ctl0.bits.entx = 0xF; ++ ++ for (i = 0; i < AW_PHY_TIMEOUT; i++) { ++ udelay(5); ++ status = phy_base->phy_pll_sts.bits.tx_ready_dly_status; ++ if (status & 0x1) { ++ pr_info("[%s]:tx_ready_status\n", __func__); ++ break; ++ } ++ } ++ if ((i == AW_PHY_TIMEOUT) && !status) { ++ pr_err("tx_ready_status Timeout ! status = 0x%x\n", status); ++ return -1; ++ } ++ ++ return 0; ++} ++ + static int sun20i_d1_hdmi_phy_config(struct dw_hdmi *hdmi, void *data, + const struct drm_display_info *display, + const struct drm_display_mode *mode) + { + struct sun8i_hdmi_phy *phy = data; ++ volatile struct __aw_phy_reg_t __iomem *phy_base = phy->base; ++ int ret; ++ ++ pr_info("enter %s\n", __func__); ++ ++ /* enable all channel */ ++ phy_base->phy_ctl5.bits.reg_p1opt = 0xF; ++ ++ // phy_reset ++ phy_base->phy_ctl0.bits.entx = 0; ++ phy_base->phy_ctl5.bits.enresck = 0; ++ phy_base->phy_ctl5.bits.enres = 0; ++ phy_base->phy_ctl5.bits.enp2s = 0; ++ phy_base->phy_ctl0.bits.enck = 0; ++ phy_base->phy_ctl0.bits.enbi = 0; ++ phy_base->phy_ctl5.bits.encalog = 0; ++ phy_base->phy_ctl5.bits.enrcal = 0; ++ phy_base->phy_ctl0.bits.enldo_fs = 0; ++ phy_base->phy_ctl0.bits.enldo = 0; ++ phy_base->phy_ctl5.bits.enib = 0; ++ phy_base->pll_ctl1.bits.reset = 1; ++ phy_base->pll_ctl1.bits.pwron = 0; ++ phy_base->pll_ctl0.bits.envbs = 0; ++ ++ // phy_set_mpll ++ phy_base->pll_ctl0.bits.cko_sel = 0x3; ++ phy_base->pll_ctl0.bits.bypass_ppll = 0x1; ++ phy_base->pll_ctl1.bits.drv_ana = 1; ++ phy_base->pll_ctl1.bits.ctrl_modle_clksrc = 0x0; //0: PLL_video 1: MPLL ++ phy_base->pll_ctl1.bits.sdm_en = 0x0; //mpll sdm jitter is very large, not used for the time being ++ phy_base->pll_ctl1.bits.sckref = 0; //default value is 1 ++ phy_base->pll_ctl0.bits.slv = 4; ++ phy_base->pll_ctl0.bits.prop_cntrl = 7; //default value 7 ++ phy_base->pll_ctl0.bits.gmp_cntrl = 3; //default value 1 ++ phy_base->pll_ctl1.bits.ref_cntrl = 0; ++ phy_base->pll_ctl0.bits.vcorange = 1; ++ ++ // phy_set_div ++ phy_base->pll_ctl0.bits.div_pre = 0; //div7 = n+1 ++ phy_base->pll_ctl1.bits.pcnt_en = 0; ++ phy_base->pll_ctl1.bits.pcnt_n = 1; //div6 = 1 (pcnt_en=0) [div6 = n (pcnt_en = 1) note that some multiples are problematic] 4-256 ++ phy_base->pll_ctl1.bits.pixel_rep = 0; //div5 = n+1 ++ phy_base->pll_ctl0.bits.bypass_clrdpth = 0; ++ phy_base->pll_ctl0.bits.clr_dpth = 0; //div4 = 1 (bypass_clrdpth = 0) ++ //00: 2 01: 2.5 10: 3 11: 4 ++ phy_base->pll_ctl0.bits.n_cntrl = 1; //div ++ phy_base->pll_ctl0.bits.div2_ckbit = 0; //div1 = n+1 ++ phy_base->pll_ctl0.bits.div2_cktmds = 0; //div2 = n+1 ++ phy_base->pll_ctl0.bits.bcr = 0; //div3 0: [1:10] 1: [1:40] ++ phy_base->pll_ctl1.bits.pwron = 1; ++ phy_base->pll_ctl1.bits.reset = 0; ++ ++ // configure phy ++ /* config values taken from table */ ++ phy_base->phy_ctl1.dwval = ((phy_base->phy_ctl1.dwval & 0xFFC0FFFF) | /* config->phy_ctl1 */ 0x0); ++ phy_base->phy_ctl2.dwval = ((phy_base->phy_ctl2.dwval & 0xFF000000) | /* config->phy_ctl2 */ 0x0); ++ phy_base->phy_ctl3.dwval = ((phy_base->phy_ctl3.dwval & 0xFFFF0000) | /* config->phy_ctl3 */ 0xFFFF); ++ phy_base->phy_ctl4.dwval = ((phy_base->phy_ctl4.dwval & 0xE0000000) | /* config->phy_ctl4 */ 0xC0D0D0D); ++ //phy_base->pll_ctl0.dwval |= config->pll_ctl0; ++ //phy_base->pll_ctl1.dwval |= config->pll_ctl1; ++ ++ // phy_set_clk ++ phy_base->phy_ctl6.bits.switch_clkch_data_corresponding = 0; ++ phy_base->phy_ctl6.bits.clk_greate0_340m = 0x3FF; ++ phy_base->phy_ctl6.bits.clk_greate1_340m = 0x3FF; ++ phy_base->phy_ctl6.bits.clk_greate2_340m = 0x0; ++ phy_base->phy_ctl7.bits.clk_greate3_340m = 0x0; ++ phy_base->phy_ctl7.bits.clk_low_340m = 0x3E0; ++ phy_base->phy_ctl6.bits.en_ckdat = 1; //default value is 0 ++ ++ // phy_base->phy_ctl2.bits.reg_resdi = 0x18; ++ // phy_base->phy_ctl4.bits.reg_slv = 3; //low power voltage 1.08V, default value is 3 ++ ++ phy_base->phy_ctl1.bits.res_scktmds = 0; // ++ phy_base->phy_ctl0.bits.reg_csmps = 2; ++ phy_base->phy_ctl0.bits.reg_ck_test_sel = 0; //? ++ phy_base->phy_ctl0.bits.reg_ck_sel = 1; ++ phy_base->phy_indbg_ctrl.bits.txdata_debugmode = 0; ++ ++ // phy_enable ++ ret = sun20i_d1_hdmi_phy_enable(phy_base); ++ if (ret) ++ return ret; ++ ++ phy_base->phy_ctl0.bits.sda_en = 1; ++ phy_base->phy_ctl0.bits.scl_en = 1; ++ phy_base->phy_ctl0.bits.hpd_en = 1; ++ phy_base->phy_ctl0.bits.reg_den = 0xF; ++ phy_base->pll_ctl0.bits.envbs = 1; + + return 0; + } +@@ -720,6 +875,7 @@ static int sun8i_hdmi_phy_probe(struct p + return dev_err_probe(dev, PTR_ERR(regs), + "Couldn't map the HDMI PHY registers\n"); + ++ phy->base = regs; + phy->regs = devm_regmap_init_mmio(dev, regs, + &sun8i_hdmi_phy_regmap_config); + if (IS_ERR(phy->regs)) diff --git a/target/linux/d1/patches-6.1/0010-riscv-mm-Use-IOMMU-for-DMA-when-available.patch b/target/linux/d1/patches-6.1/0010-riscv-mm-Use-IOMMU-for-DMA-when-available.patch new file mode 100644 index 0000000000..18dfa573e3 --- /dev/null +++ b/target/linux/d1/patches-6.1/0010-riscv-mm-Use-IOMMU-for-DMA-when-available.patch @@ -0,0 +1,30 @@ +From 02a412de18479449c87ed7a332e3fe33d2eff3a4 Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Wed, 27 Apr 2022 18:47:53 -0500 +Subject: [PATCH 010/117] riscv: mm: Use IOMMU for DMA when available + +Signed-off-by: Samuel Holland +--- + arch/riscv/mm/dma-noncoherent.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/arch/riscv/mm/dma-noncoherent.c ++++ b/arch/riscv/mm/dma-noncoherent.c +@@ -7,6 +7,7 @@ + + #include + #include ++#include + #include + #include + +@@ -70,6 +71,9 @@ void arch_setup_dma_ops(struct device *d + dev_driver_string(dev), dev_name(dev)); + + dev->dma_coherent = coherent; ++ ++ if (iommu) ++ iommu_setup_dma_ops(dev, dma_base, dma_base + size - 1); + } + + void riscv_noncoherent_supported(void) diff --git a/target/linux/d1/patches-6.1/0011-genirq-Add-support-for-oneshot-safe-threaded-EOIs.patch b/target/linux/d1/patches-6.1/0011-genirq-Add-support-for-oneshot-safe-threaded-EOIs.patch new file mode 100644 index 0000000000..d8dd2878d1 --- /dev/null +++ b/target/linux/d1/patches-6.1/0011-genirq-Add-support-for-oneshot-safe-threaded-EOIs.patch @@ -0,0 +1,124 @@ +From ee6459d60f24d91052f0288155f44e6a7f991050 Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Sat, 7 May 2022 18:34:25 -0500 +Subject: [PATCH 011/117] genirq: Add support for oneshot-safe threaded EOIs + +irqchips can use the combination of flags IRQCHIP_ONESHOT_SAFE | +IRQCHIP_EOI_THREADED to elide mask operations. + +Signed-off-by: Samuel Holland +--- + kernel/irq/chip.c | 36 +++++++++++++++++------------------- + kernel/irq/internals.h | 2 +- + kernel/irq/manage.c | 12 ++++++------ + 3 files changed, 24 insertions(+), 26 deletions(-) + +--- a/kernel/irq/chip.c ++++ b/kernel/irq/chip.c +@@ -439,16 +439,6 @@ void unmask_irq(struct irq_desc *desc) + } + } + +-void unmask_threaded_irq(struct irq_desc *desc) +-{ +- struct irq_chip *chip = desc->irq_data.chip; +- +- if (chip->flags & IRQCHIP_EOI_THREADED) +- chip->irq_eoi(&desc->irq_data); +- +- unmask_irq(desc); +-} +- + /* + * handle_nested_irq - Handle a nested irq from a irq thread + * @irq: the interrupt number +@@ -656,25 +646,33 @@ out_unlock: + } + EXPORT_SYMBOL_GPL(handle_level_irq); + +-static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip) ++void unmask_eoi_threaded_irq(struct irq_desc *desc) + { +- if (!(desc->istate & IRQS_ONESHOT)) { ++ struct irq_chip *chip = desc->irq_data.chip; ++ ++ if (desc->istate & IRQS_ONESHOT) ++ unmask_irq(desc); ++ ++ if (chip->flags & IRQCHIP_EOI_THREADED) + chip->irq_eoi(&desc->irq_data); ++} ++ ++static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip) ++{ ++ /* Do not send EOI if the thread will do it for us. */ ++ if ((chip->flags & IRQCHIP_EOI_THREADED) && desc->threads_oneshot) + return; +- } ++ + /* + * We need to unmask in the following cases: + * - Oneshot irq which did not wake the thread (caused by a + * spurious interrupt or a primary handler handling it + * completely). + */ +- if (!irqd_irq_disabled(&desc->irq_data) && +- irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) { +- chip->irq_eoi(&desc->irq_data); ++ if ((desc->istate & IRQS_ONESHOT) && !desc->threads_oneshot) + unmask_irq(desc); +- } else if (!(chip->flags & IRQCHIP_EOI_THREADED)) { +- chip->irq_eoi(&desc->irq_data); +- } ++ ++ chip->irq_eoi(&desc->irq_data); + } + + /** +--- a/kernel/irq/internals.h ++++ b/kernel/irq/internals.h +@@ -93,7 +93,7 @@ extern void irq_percpu_enable(struct irq + extern void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu); + extern void mask_irq(struct irq_desc *desc); + extern void unmask_irq(struct irq_desc *desc); +-extern void unmask_threaded_irq(struct irq_desc *desc); ++extern void unmask_eoi_threaded_irq(struct irq_desc *desc); + + #ifdef CONFIG_SPARSE_IRQ + static inline void irq_mark_irq(unsigned int irq) { } +--- a/kernel/irq/manage.c ++++ b/kernel/irq/manage.c +@@ -1074,9 +1074,9 @@ static int irq_wait_for_interrupt(struct + static void irq_finalize_oneshot(struct irq_desc *desc, + struct irqaction *action) + { +- if (!(desc->istate & IRQS_ONESHOT) || +- action->handler == irq_forced_secondary_handler) ++ if (action->handler == irq_forced_secondary_handler) + return; ++ + again: + chip_bus_lock(desc); + raw_spin_lock_irq(&desc->lock); +@@ -1112,9 +1112,8 @@ again: + + desc->threads_oneshot &= ~action->thread_mask; + +- if (!desc->threads_oneshot && !irqd_irq_disabled(&desc->irq_data) && +- irqd_irq_masked(&desc->irq_data)) +- unmask_threaded_irq(desc); ++ if (!desc->threads_oneshot) ++ unmask_eoi_threaded_irq(desc); + + out_unlock: + raw_spin_unlock_irq(&desc->lock); +@@ -1662,7 +1661,8 @@ __setup_irq(unsigned int irq, struct irq + * !ONESHOT irqs the thread mask is 0 so we can avoid a + * conditional in irq_wake_thread(). + */ +- if (new->flags & IRQF_ONESHOT) { ++ if ((new->flags & IRQF_ONESHOT) || ++ (desc->irq_data.chip->flags & (IRQCHIP_ONESHOT_SAFE | IRQCHIP_EOI_THREADED)) == (IRQCHIP_ONESHOT_SAFE | IRQCHIP_EOI_THREADED)) { + /* + * Unlikely to have 32 resp 64 irqs sharing one line, + * but who knows. diff --git a/target/linux/d1/patches-6.1/0012-irqchip-sifive-plic-Enable-oneshot-safe-threaded-EOI.patch b/target/linux/d1/patches-6.1/0012-irqchip-sifive-plic-Enable-oneshot-safe-threaded-EOI.patch new file mode 100644 index 0000000000..8cb949f186 --- /dev/null +++ b/target/linux/d1/patches-6.1/0012-irqchip-sifive-plic-Enable-oneshot-safe-threaded-EOI.patch @@ -0,0 +1,24 @@ +From 1fbe96ec05c41b313b4e7cc4b39b191b4a3f7540 Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Sat, 7 May 2022 18:38:34 -0500 +Subject: [PATCH 012/117] irqchip/sifive-plic: Enable oneshot-safe threaded + EOIs + +Signed-off-by: Samuel Holland +--- + drivers/irqchip/irq-sifive-plic.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/drivers/irqchip/irq-sifive-plic.c ++++ b/drivers/irqchip/irq-sifive-plic.c +@@ -207,7 +207,9 @@ static struct irq_chip plic_chip = { + .irq_set_affinity = plic_set_affinity, + #endif + .irq_set_type = plic_irq_set_type, +- .flags = IRQCHIP_AFFINITY_PRE_STARTUP, ++ .flags = IRQCHIP_ONESHOT_SAFE | ++ IRQCHIP_EOI_THREADED | ++ IRQCHIP_AFFINITY_PRE_STARTUP, + }; + + static int plic_irq_set_type(struct irq_data *d, unsigned int type) diff --git a/target/linux/d1/patches-6.1/0013-irqchip-sifive-plic-Support-wake-IRQs.patch b/target/linux/d1/patches-6.1/0013-irqchip-sifive-plic-Support-wake-IRQs.patch new file mode 100644 index 0000000000..209d97597c --- /dev/null +++ b/target/linux/d1/patches-6.1/0013-irqchip-sifive-plic-Support-wake-IRQs.patch @@ -0,0 +1,32 @@ +From d6cf6473b0aaec455e48bccefe318a98a87b789f Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Sat, 28 May 2022 19:04:56 -0500 +Subject: [PATCH 013/117] irqchip/sifive-plic: Support wake IRQs + +Signed-off-by: Samuel Holland +--- + drivers/irqchip/irq-sifive-plic.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/drivers/irqchip/irq-sifive-plic.c ++++ b/drivers/irqchip/irq-sifive-plic.c +@@ -193,7 +193,8 @@ static struct irq_chip plic_edge_chip = + .irq_set_affinity = plic_set_affinity, + #endif + .irq_set_type = plic_irq_set_type, +- .flags = IRQCHIP_AFFINITY_PRE_STARTUP, ++ .flags = IRQCHIP_SKIP_SET_WAKE | ++ IRQCHIP_AFFINITY_PRE_STARTUP, + }; + + static struct irq_chip plic_chip = { +@@ -207,7 +208,8 @@ static struct irq_chip plic_chip = { + .irq_set_affinity = plic_set_affinity, + #endif + .irq_set_type = plic_irq_set_type, +- .flags = IRQCHIP_ONESHOT_SAFE | ++ .flags = IRQCHIP_SKIP_SET_WAKE | ++ IRQCHIP_ONESHOT_SAFE | + IRQCHIP_EOI_THREADED | + IRQCHIP_AFFINITY_PRE_STARTUP, + }; diff --git a/target/linux/d1/patches-6.1/0014-mmc-sunxi-mmc-Correct-the-maximum-segment-size.patch b/target/linux/d1/patches-6.1/0014-mmc-sunxi-mmc-Correct-the-maximum-segment-size.patch new file mode 100644 index 0000000000..7e8098a2cf --- /dev/null +++ b/target/linux/d1/patches-6.1/0014-mmc-sunxi-mmc-Correct-the-maximum-segment-size.patch @@ -0,0 +1,65 @@ +From 0e871e791a2530562851109346affa1c0d9987e0 Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Sun, 13 Jun 2021 23:15:56 -0500 +Subject: [PATCH 014/117] mmc: sunxi-mmc: Correct the maximum segment size + +According to the DMA descriptor documentation, the lowest two bits of +the size field are ignored, so the size must be rounded up to a multiple +of 4 bytes. Furthermore, 0 is not a valid buffer size; setting the size +to 0 will cause that DMA descriptor to be ignored. + +Together, these restrictions limit the maximum DMA segment size to 4 +less than the power-of-two width of the size field. + +Series-to: Ulf Hansson +Series-to: linux-mmc@vger.kernel.org + +Fixes: 3cbcb16095f9 ("mmc: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs") +Signed-off-by: Samuel Holland +--- + drivers/mmc/host/sunxi-mmc.c | 14 ++++++++------ + 1 file changed, 8 insertions(+), 6 deletions(-) + +--- a/drivers/mmc/host/sunxi-mmc.c ++++ b/drivers/mmc/host/sunxi-mmc.c +@@ -214,6 +214,9 @@ + #define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */ + #define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */ + ++/* Buffer size must be a multiple of 4 bytes. */ ++#define SDXC_IDMAC_SIZE_ALIGN 4 ++ + #define SDXC_CLK_400K 0 + #define SDXC_CLK_25M 1 + #define SDXC_CLK_50M 2 +@@ -361,17 +364,15 @@ static void sunxi_mmc_init_idma_des(stru + { + struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu; + dma_addr_t next_desc = host->sg_dma; +- int i, max_len = (1 << host->cfg->idma_des_size_bits); ++ int i; + + for (i = 0; i < data->sg_len; i++) { + pdes[i].config = cpu_to_le32(SDXC_IDMAC_DES0_CH | + SDXC_IDMAC_DES0_OWN | + SDXC_IDMAC_DES0_DIC); + +- if (data->sg[i].length == max_len) +- pdes[i].buf_size = 0; /* 0 == max_len */ +- else +- pdes[i].buf_size = cpu_to_le32(data->sg[i].length); ++ pdes[i].buf_size = cpu_to_le32(ALIGN(data->sg[i].length, ++ SDXC_IDMAC_SIZE_ALIGN)); + + next_desc += sizeof(struct sunxi_idma_des); + pdes[i].buf_addr_ptr1 = +@@ -1421,7 +1422,8 @@ static int sunxi_mmc_probe(struct platfo + mmc->max_blk_count = 8192; + mmc->max_blk_size = 4096; + mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des); +- mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits); ++ mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits) - ++ SDXC_IDMAC_SIZE_ALIGN; + mmc->max_req_size = mmc->max_seg_size * mmc->max_segs; + /* 400kHz ~ 52MHz */ + mmc->f_min = 400000; diff --git a/target/linux/d1/patches-6.1/0015-dt-bindings-display-Add-bindings-for-ClockworkPi-CWD.patch b/target/linux/d1/patches-6.1/0015-dt-bindings-display-Add-bindings-for-ClockworkPi-CWD.patch new file mode 100644 index 0000000000..665c55058c --- /dev/null +++ b/target/linux/d1/patches-6.1/0015-dt-bindings-display-Add-bindings-for-ClockworkPi-CWD.patch @@ -0,0 +1,82 @@ +From a8e905fb3fd0d26f724646275b72a7363b2f03d8 Mon Sep 17 00:00:00 2001 +From: Max Fierke +Date: Wed, 1 Jun 2022 00:17:47 -0500 +Subject: [PATCH 015/117] dt-bindings: display: Add bindings for ClockworkPi + CWD686 + +The CWD686 is a 6.86" IPS LCD panel used as the primary +display in the ClockworkPi DevTerm portable (all cores) + +Signed-off-by: Max Fierke +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Samuel Holland +--- + .../display/panel/clockwork,cwd686.yaml | 62 +++++++++++++++++++ + 1 file changed, 62 insertions(+) + create mode 100644 Documentation/devicetree/bindings/display/panel/clockwork,cwd686.yaml + +--- /dev/null ++++ b/Documentation/devicetree/bindings/display/panel/clockwork,cwd686.yaml +@@ -0,0 +1,62 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/display/panel/clockwork,cwd686.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Clockwork CWD686 6.86" IPS LCD panel ++ ++maintainers: ++ - Max Fierke ++ ++description: | ++ The Clockwork CWD686 is a 6.86" ICNL9707-based IPS LCD panel used within the ++ Clockwork DevTerm series of portable devices. The panel has a 480x1280 ++ resolution and uses 24 bit RGB per pixel. ++ ++allOf: ++ - $ref: panel-common.yaml# ++ ++properties: ++ compatible: ++ const: clockwork,cwd686 ++ ++ reg: ++ description: DSI virtual channel used by that screen ++ maxItems: 1 ++ ++ reset-gpios: true ++ rotation: true ++ backlight: true ++ iovcc-supply: true ++ vci-supply: true ++ ++required: ++ - compatible ++ - reg ++ - backlight ++ - reset-gpios ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ ++ backlight: backlight { ++ compatible = "gpio-backlight"; ++ gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ dsi { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ panel@0 { ++ compatible = "clockwork,cwd686"; ++ reg = <0>; ++ backlight = <&backlight>; ++ reset-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; ++ rotation = <90>; ++ }; ++ }; diff --git a/target/linux/d1/patches-6.1/0016-dt-bindings-display-Add-Sitronix-ST7701s-panel-bindi.patch b/target/linux/d1/patches-6.1/0016-dt-bindings-display-Add-Sitronix-ST7701s-panel-bindi.patch new file mode 100644 index 0000000000..85d8421f62 --- /dev/null +++ b/target/linux/d1/patches-6.1/0016-dt-bindings-display-Add-Sitronix-ST7701s-panel-bindi.patch @@ -0,0 +1,47 @@ +From d290546a88694dde6d2f64a973cd62ff2c69e27e Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Fri, 12 Aug 2022 01:59:35 -0500 +Subject: [PATCH 016/117] dt-bindings: display: Add Sitronix ST7701s panel + binding + +Signed-off-by: Samuel Holland +--- + .../display/panel/sitronix,st7701s.yaml | 32 +++++++++++++++++++ + 1 file changed, 32 insertions(+) + create mode 100644 Documentation/devicetree/bindings/display/panel/sitronix,st7701s.yaml + +--- /dev/null ++++ b/Documentation/devicetree/bindings/display/panel/sitronix,st7701s.yaml +@@ -0,0 +1,32 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/display/panel/sitronix,st7701s.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Sitronix ST7701 based LCD panels ++ ++maintainers: ++ - Samuel Holland ++ ++description: | ++ Panel used on Lichee RV 86 Panel ++ ++allOf: ++ - $ref: panel-common.yaml# ++ - $ref: /schemas/spi/spi-peripheral-props.yaml# ++ ++properties: ++ compatible: ++ items: ++ - const: sitronix,st7701s ++ ++ backlight: true ++ ++ reset-gpios: true ++ ++required: ++ - compatible ++ - reset-gpios ++ ++unevaluatedProperties: false diff --git a/target/linux/d1/patches-6.1/0017-drm-panel-Add-driver-for-ST7701s-DPI-LCD-panel.patch b/target/linux/d1/patches-6.1/0017-drm-panel-Add-driver-for-ST7701s-DPI-LCD-panel.patch new file mode 100644 index 0000000000..535478cf9e --- /dev/null +++ b/target/linux/d1/patches-6.1/0017-drm-panel-Add-driver-for-ST7701s-DPI-LCD-panel.patch @@ -0,0 +1,487 @@ +From 9d9b8bd567c30a821c82c27035243536c5234542 Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Tue, 29 Mar 2022 22:47:57 -0500 +Subject: [PATCH 017/117] drm/panel: Add driver for ST7701s DPI LCD panel + +Signed-off-by: Samuel Holland +--- + drivers/gpu/drm/panel/Kconfig | 8 + + drivers/gpu/drm/panel/Makefile | 1 + + .../gpu/drm/panel/panel-sitronix-st7701s.c | 444 ++++++++++++++++++ + 3 files changed, 453 insertions(+) + create mode 100644 drivers/gpu/drm/panel/panel-sitronix-st7701s.c + +--- a/drivers/gpu/drm/panel/Kconfig ++++ b/drivers/gpu/drm/panel/Kconfig +@@ -608,6 +608,14 @@ config DRM_PANEL_SITRONIX_ST7701 + ST7701 controller for 480X864 LCD panels with MIPI/RGB/SPI + system interfaces. + ++config DRM_PANEL_SITRONIX_ST7701S ++ tristate "Sitronix ST7701s panel driver" ++ depends on OF ++ depends on BACKLIGHT_CLASS_DEVICE ++ help ++ Say Y here if you want to enable support for the Sitronix ++ ST7701s controller with a SPI interface. ++ + config DRM_PANEL_SITRONIX_ST7703 + tristate "Sitronix ST7703 based MIPI touchscreen panels" + depends on OF +--- a/drivers/gpu/drm/panel/Makefile ++++ b/drivers/gpu/drm/panel/Makefile +@@ -61,6 +61,7 @@ obj-$(CONFIG_DRM_PANEL_SHARP_LS037V7DW01 + obj-$(CONFIG_DRM_PANEL_SHARP_LS043T1LE01) += panel-sharp-ls043t1le01.o + obj-$(CONFIG_DRM_PANEL_SHARP_LS060T1SX01) += panel-sharp-ls060t1sx01.o + obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7701) += panel-sitronix-st7701.o ++obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7701S) += panel-sitronix-st7701s.o + obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7703) += panel-sitronix-st7703.o + obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7789V) += panel-sitronix-st7789v.o + obj-$(CONFIG_DRM_PANEL_SONY_ACX565AKM) += panel-sony-acx565akm.o +--- /dev/null ++++ b/drivers/gpu/drm/panel/panel-sitronix-st7701s.c +@@ -0,0 +1,444 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (C) 2017 Free Electrons ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include